Pileus Git - ~andy/linux/blob - drivers/clocksource/sun4i_timer.c

   1 /*
   2  * Allwinner A1X SoCs timer handling.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * Based on code from
   9  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10  * Benn Huang <benn@allwinnertech.com>
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2.  This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/sched_clock.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #define TIMER_IRQ_EN_REG        0x00
  28 #define TIMER_IRQ_EN(val)               BIT(val)
  29 #define TIMER_IRQ_ST_REG        0x04
  30 #define TIMER_CTL_REG(val)      (0x10 * val + 0x10)
  31 #define TIMER_CTL_ENABLE                BIT(0)
  32 #define TIMER_CTL_RELOAD                BIT(1)
  33 #define TIMER_CTL_CLK_SRC(val)          (((val) & 0x3) << 2)
  34 #define TIMER_CTL_CLK_SRC_OSC24M                (1)
  35 #define TIMER_CTL_CLK_PRES(val)         (((val) & 0x7) << 4)
  36 #define TIMER_CTL_ONESHOT               BIT(7)
  37 #define TIMER_INTVAL_REG(val)   (0x10 * (val) + 0x14)
  38 #define TIMER_CNTVAL_REG(val)   (0x10 * (val) + 0x18)
  39
  40 static void __iomem *timer_base;
  41
  42 /*
  43  * When we disable a timer, we need to wait at least for 2 cycles of
  44  * the timer source clock. We will use for that the clocksource timer
  45  * that is already setup and runs at the same frequency than the other
  46  * timers, and we never will be disabled.
  47  */
  48 static void sun4i_clkevt_sync(void)
  49 {
  50         u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
  51
  52         while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < 3)
  53                 cpu_relax();
  54 }
  55
  56 static void sun4i_clkevt_time_stop(u8 timer)
  57 {
  58         u32 val = readl(timer_base + TIMER_CTL_REG(timer));
  59         writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
  60         sun4i_clkevt_sync();
  61 }
  62
  63 static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
  64 {
  65         writel(delay, timer_base + TIMER_INTVAL_REG(timer));
  66 }
  67
  68 static void sun4i_clkevt_time_start(u8 timer, bool periodic)
  69 {
  70         u32 val = readl(timer_base + TIMER_CTL_REG(timer));
  71
  72         if (periodic)
  73                 val &= ~TIMER_CTL_ONESHOT;
  74         else
  75                 val |= TIMER_CTL_ONESHOT;
  76
  77         writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
  78 }
  79
  80 static void sun4i_clkevt_mode(enum clock_event_mode mode,
  81                               struct clock_event_device *clk)
  82 {
  83         switch (mode) {
  84         case CLOCK_EVT_MODE_PERIODIC:
  85                 sun4i_clkevt_time_stop(0);
  86                 sun4i_clkevt_time_start(0, true);
  87                 break;
  88         case CLOCK_EVT_MODE_ONESHOT:
  89                 sun4i_clkevt_time_stop(0);
  90                 sun4i_clkevt_time_start(0, false);
  91                 break;
  92         case CLOCK_EVT_MODE_UNUSED:
  93         case CLOCK_EVT_MODE_SHUTDOWN:
  94         default:
  95                 sun4i_clkevt_time_stop(0);
  96                 break;
  97         }
  98 }
  99
 100 static int sun4i_clkevt_next_event(unsigned long evt,
 101                                    struct clock_event_device *unused)
 102 {
 103         sun4i_clkevt_time_stop(0);
 104         sun4i_clkevt_time_setup(0, evt);
 105         sun4i_clkevt_time_start(0, false);
 106
 107         return 0;
 108 }
 109
 110 static struct clock_event_device sun4i_clockevent = {
 111         .name = "sun4i_tick",
 112         .rating = 300,
 113         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 114         .set_mode = sun4i_clkevt_mode,
 115         .set_next_event = sun4i_clkevt_next_event,
 116 };
 117
 118
 119 static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
 120 {
 121         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 122
 123         writel(0x1, timer_base + TIMER_IRQ_ST_REG);
 124         evt->event_handler(evt);
 125
 126         return IRQ_HANDLED;
 127 }
 128
 129 static struct irqaction sun4i_timer_irq = {
 130         .name = "sun4i_timer0",
 131         .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 132         .handler = sun4i_timer_interrupt,
 133         .dev_id = &sun4i_clockevent,
 134 };
 135
 136 static u32 sun4i_timer_sched_read(void)
 137 {
 138         return ~readl(timer_base + TIMER_CNTVAL_REG(1));
 139 }
 140
 141 static void __init sun4i_timer_init(struct device_node *node)
 142 {
 143         unsigned long rate = 0;
 144         struct clk *clk;
 145         int ret, irq;
 146         u32 val;
 147
 148         timer_base = of_iomap(node, 0);
 149         if (!timer_base)
 150                 panic("Can't map registers");
 151
 152         irq = irq_of_parse_and_map(node, 0);
 153         if (irq <= 0)
 154                 panic("Can't parse IRQ");
 155
 156         clk = of_clk_get(node, 0);
 157         if (IS_ERR(clk))
 158                 panic("Can't get timer clock");
 159         clk_prepare_enable(clk);
 160
 161         rate = clk_get_rate(clk);
 162
 163         writel(~0, timer_base + TIMER_INTVAL_REG(1));
 164         writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
 165                TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
 166                timer_base + TIMER_CTL_REG(1));
 167
 168         setup_sched_clock(sun4i_timer_sched_read, 32, rate);
 169         clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
 170                               rate, 300, 32, clocksource_mmio_readl_down);
 171
 172         writel(rate / HZ, timer_base + TIMER_INTVAL_REG(0));
 173
 174         writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M) | TIMER_CTL_RELOAD,
 175                timer_base + TIMER_CTL_REG(0));
 176
 177         ret = setup_irq(irq, &sun4i_timer_irq);
 178         if (ret)
 179                 pr_warn("failed to setup irq %d\n", irq);
 180
 181         /* Enable timer0 interrupt */
 182         val = readl(timer_base + TIMER_IRQ_EN_REG);
 183         writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
 184
 185         sun4i_clockevent.cpumask = cpumask_of(0);
 186
 187         clockevents_config_and_register(&sun4i_clockevent, rate, 0x1,
 188                                         0xffffffff);
 189 }
 190 CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
 191                        sun4i_timer_init);