Pileus Git - ~andy/linux/blob - drivers/clocksource/sun4i_timer.c

   1 /*
   2  * Allwinner A1X SoCs timer handling.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * Based on code from
   9  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10  * Benn Huang <benn@allwinnertech.com>
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2.  This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/sched_clock.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #define TIMER_IRQ_EN_REG        0x00
  28 #define TIMER_IRQ_EN(val)               BIT(val)
  29 #define TIMER_IRQ_ST_REG        0x04
  30 #define TIMER_CTL_REG(val)      (0x10 * val + 0x10)
  31 #define TIMER_CTL_ENABLE                BIT(0)
  32 #define TIMER_CTL_RELOAD                BIT(1)
  33 #define TIMER_CTL_ONESHOT               BIT(7)
  34 #define TIMER_INTVAL_REG(val)   (0x10 * (val) + 0x14)
  35 #define TIMER_CNTVAL_REG(val)   (0x10 * (val) + 0x18)
  36
  37 #define TIMER_SCAL              16
  38
  39 static void __iomem *timer_base;
  40
  41 /*
  42  * When we disable a timer, we need to wait at least for 2 cycles of
  43  * the timer source clock. We will use for that the clocksource timer
  44  * that is already setup and runs at the same frequency than the other
  45  * timers, and we never will be disabled.
  46  */
  47 static void sun4i_clkevt_sync(void)
  48 {
  49         u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
  50
  51         while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < 3)
  52                 cpu_relax();
  53 }
  54
  55 static void sun4i_clkevt_time_stop(u8 timer)
  56 {
  57         u32 val = readl(timer_base + TIMER_CTL_REG(timer));
  58         writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
  59         sun4i_clkevt_sync();
  60 }
  61
  62 static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
  63 {
  64         writel(delay, timer_base + TIMER_INTVAL_REG(timer));
  65 }
  66
  67 static void sun4i_clkevt_time_start(u8 timer, bool periodic)
  68 {
  69         u32 val = readl(timer_base + TIMER_CTL_REG(timer));
  70
  71         if (periodic)
  72                 val &= ~TIMER_CTL_ONESHOT;
  73         else
  74                 val |= TIMER_CTL_ONESHOT;
  75
  76         writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
  77 }
  78
  79 static void sun4i_clkevt_mode(enum clock_event_mode mode,
  80                               struct clock_event_device *clk)
  81 {
  82         switch (mode) {
  83         case CLOCK_EVT_MODE_PERIODIC:
  84                 sun4i_clkevt_time_stop(0);
  85                 sun4i_clkevt_time_start(0, true);
  86                 break;
  87         case CLOCK_EVT_MODE_ONESHOT:
  88                 sun4i_clkevt_time_stop(0);
  89                 sun4i_clkevt_time_start(0, false);
  90                 break;
  91         case CLOCK_EVT_MODE_UNUSED:
  92         case CLOCK_EVT_MODE_SHUTDOWN:
  93         default:
  94                 sun4i_clkevt_time_stop(0);
  95                 break;
  96         }
  97 }
  98
  99 static int sun4i_clkevt_next_event(unsigned long evt,
 100                                    struct clock_event_device *unused)
 101 {
 102         sun4i_clkevt_time_stop(0);
 103         sun4i_clkevt_time_setup(0, evt);
 104         sun4i_clkevt_time_start(0, false);
 105
 106         return 0;
 107 }
 108
 109 static struct clock_event_device sun4i_clockevent = {
 110         .name = "sun4i_tick",
 111         .rating = 300,
 112         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 113         .set_mode = sun4i_clkevt_mode,
 114         .set_next_event = sun4i_clkevt_next_event,
 115 };
 116
 117
 118 static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
 119 {
 120         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 121
 122         writel(0x1, timer_base + TIMER_IRQ_ST_REG);
 123         evt->event_handler(evt);
 124
 125         return IRQ_HANDLED;
 126 }
 127
 128 static struct irqaction sun4i_timer_irq = {
 129         .name = "sun4i_timer0",
 130         .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 131         .handler = sun4i_timer_interrupt,
 132         .dev_id = &sun4i_clockevent,
 133 };
 134
 135 static u32 sun4i_timer_sched_read(void)
 136 {
 137         return ~readl(timer_base + TIMER_CNTVAL_REG(1));
 138 }
 139
 140 static void __init sun4i_timer_init(struct device_node *node)
 141 {
 142         unsigned long rate = 0;
 143         struct clk *clk;
 144         int ret, irq;
 145         u32 val;
 146
 147         timer_base = of_iomap(node, 0);
 148         if (!timer_base)
 149                 panic("Can't map registers");
 150
 151         irq = irq_of_parse_and_map(node, 0);
 152         if (irq <= 0)
 153                 panic("Can't parse IRQ");
 154
 155         clk = of_clk_get(node, 0);
 156         if (IS_ERR(clk))
 157                 panic("Can't get timer clock");
 158         clk_prepare_enable(clk);
 159
 160         rate = clk_get_rate(clk);
 161
 162         writel(~0, timer_base + TIMER_INTVAL_REG(1));
 163         writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
 164                TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
 165                timer_base + TIMER_CTL_REG(1));
 166
 167         setup_sched_clock(sun4i_timer_sched_read, 32, rate);
 168         clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
 169                               rate, 300, 32, clocksource_mmio_readl_down);
 170
 171         writel(rate / (TIMER_SCAL * HZ),
 172                timer_base + TIMER_INTVAL_REG(0));
 173
 174         /* set clock source to HOSC, 16 pre-division */
 175         val = readl(timer_base + TIMER_CTL_REG(0));
 176         val &= ~(0x07 << 4);
 177         val &= ~(0x03 << 2);
 178         val |= (4 << 4) | (1 << 2);
 179         writel(val, timer_base + TIMER_CTL_REG(0));
 180
 181         /* set mode to auto reload */
 182         val = readl(timer_base + TIMER_CTL_REG(0));
 183         writel(val | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0));
 184
 185         ret = setup_irq(irq, &sun4i_timer_irq);
 186         if (ret)
 187                 pr_warn("failed to setup irq %d\n", irq);
 188
 189         /* Enable timer0 interrupt */
 190         val = readl(timer_base + TIMER_IRQ_EN_REG);
 191         writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
 192
 193         sun4i_clockevent.cpumask = cpumask_of(0);
 194
 195         clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
 196                                         0x1, 0xff);
 197 }
 198 CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
 199                        sun4i_timer_init);