Pileus Git - ~andy/linux/blob - drivers/clocksource/sun4i_timer.c

   1 /*
   2  * Allwinner A1X SoCs timer handling.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * Based on code from
   9  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10  * Benn Huang <benn@allwinnertech.com>
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2.  This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/sched_clock.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #define TIMER_IRQ_EN_REG        0x00
  28 #define TIMER_IRQ_EN(val)               BIT(val)
  29 #define TIMER_IRQ_ST_REG        0x04
  30 #define TIMER_CTL_REG(val)      (0x10 * val + 0x10)
  31 #define TIMER_CTL_ENABLE                BIT(0)
  32 #define TIMER_CTL_RELOAD                BIT(1)
  33 #define TIMER_CTL_ONESHOT               BIT(7)
  34 #define TIMER_INTVAL_REG(val)   (0x10 * (val) + 0x14)
  35 #define TIMER_CNTVAL_REG(val)   (0x10 * (val) + 0x18)
  36
  37 #define TIMER_SCAL              16
  38
  39 static void __iomem *timer_base;
  40
  41 /*
  42  * When we disable a timer, we need to wait at least for 2 cycles of
  43  * the timer source clock. We will use for that the clocksource timer
  44  * that is already setup and runs at the same frequency than the other
  45  * timers, and we never will be disabled.
  46  */
  47 static void sun4i_clkevt_sync(void)
  48 {
  49         u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
  50
  51         while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < 3)
  52                 cpu_relax();
  53 }
  54
  55 static void sun4i_clkevt_mode(enum clock_event_mode mode,
  56                               struct clock_event_device *clk)
  57 {
  58         u32 u = readl(timer_base + TIMER_CTL_REG(0));
  59
  60         switch (mode) {
  61         case CLOCK_EVT_MODE_PERIODIC:
  62                 u &= ~(TIMER_CTL_ONESHOT);
  63                 writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
  64                 break;
  65
  66         case CLOCK_EVT_MODE_ONESHOT:
  67                 writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
  68                 break;
  69         case CLOCK_EVT_MODE_UNUSED:
  70         case CLOCK_EVT_MODE_SHUTDOWN:
  71         default:
  72                 writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
  73                 break;
  74         }
  75 }
  76
  77 static int sun4i_clkevt_next_event(unsigned long evt,
  78                                    struct clock_event_device *unused)
  79 {
  80         u32 val = readl(timer_base + TIMER_CTL_REG(0));
  81         writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
  82         sun4i_clkevt_sync();
  83
  84         writel(evt, timer_base + TIMER_INTVAL_REG(0));
  85
  86         val = readl(timer_base + TIMER_CTL_REG(0));
  87         writel(val | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
  88                timer_base + TIMER_CTL_REG(0));
  89
  90         return 0;
  91 }
  92
  93 static struct clock_event_device sun4i_clockevent = {
  94         .name = "sun4i_tick",
  95         .rating = 300,
  96         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  97         .set_mode = sun4i_clkevt_mode,
  98         .set_next_event = sun4i_clkevt_next_event,
  99 };
 100
 101
 102 static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
 103 {
 104         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 105
 106         writel(0x1, timer_base + TIMER_IRQ_ST_REG);
 107         evt->event_handler(evt);
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static struct irqaction sun4i_timer_irq = {
 113         .name = "sun4i_timer0",
 114         .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 115         .handler = sun4i_timer_interrupt,
 116         .dev_id = &sun4i_clockevent,
 117 };
 118
 119 static u32 sun4i_timer_sched_read(void)
 120 {
 121         return ~readl(timer_base + TIMER_CNTVAL_REG(1));
 122 }
 123
 124 static void __init sun4i_timer_init(struct device_node *node)
 125 {
 126         unsigned long rate = 0;
 127         struct clk *clk;
 128         int ret, irq;
 129         u32 val;
 130
 131         timer_base = of_iomap(node, 0);
 132         if (!timer_base)
 133                 panic("Can't map registers");
 134
 135         irq = irq_of_parse_and_map(node, 0);
 136         if (irq <= 0)
 137                 panic("Can't parse IRQ");
 138
 139         clk = of_clk_get(node, 0);
 140         if (IS_ERR(clk))
 141                 panic("Can't get timer clock");
 142         clk_prepare_enable(clk);
 143
 144         rate = clk_get_rate(clk);
 145
 146         writel(~0, timer_base + TIMER_INTVAL_REG(1));
 147         writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
 148                TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
 149                timer_base + TIMER_CTL_REG(1));
 150
 151         setup_sched_clock(sun4i_timer_sched_read, 32, rate);
 152         clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
 153                               rate, 300, 32, clocksource_mmio_readl_down);
 154
 155         writel(rate / (TIMER_SCAL * HZ),
 156                timer_base + TIMER_INTVAL_REG(0));
 157
 158         /* set clock source to HOSC, 16 pre-division */
 159         val = readl(timer_base + TIMER_CTL_REG(0));
 160         val &= ~(0x07 << 4);
 161         val &= ~(0x03 << 2);
 162         val |= (4 << 4) | (1 << 2);
 163         writel(val, timer_base + TIMER_CTL_REG(0));
 164
 165         /* set mode to auto reload */
 166         val = readl(timer_base + TIMER_CTL_REG(0));
 167         writel(val | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0));
 168
 169         ret = setup_irq(irq, &sun4i_timer_irq);
 170         if (ret)
 171                 pr_warn("failed to setup irq %d\n", irq);
 172
 173         /* Enable timer0 interrupt */
 174         val = readl(timer_base + TIMER_IRQ_EN_REG);
 175         writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
 176
 177         sun4i_clockevent.cpumask = cpumask_of(0);
 178
 179         clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
 180                                         0x1, 0xff);
 181 }
 182 CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
 183                        sun4i_timer_init);