Pileus Git - ~andy/linux/blob - drivers/clocksource/sun4i_timer.c

   1 /*
   2  * Allwinner A1X SoCs timer handling.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * Based on code from
   9  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10  * Benn Huang <benn@allwinnertech.com>
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2.  This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/sched_clock.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #define TIMER_IRQ_EN_REG        0x00
  28 #define TIMER_IRQ_EN(val)               BIT(val)
  29 #define TIMER_IRQ_ST_REG        0x04
  30 #define TIMER_CTL_REG(val)      (0x10 * val + 0x10)
  31 #define TIMER_CTL_ENABLE                BIT(0)
  32 #define TIMER_CTL_RELOAD                BIT(1)
  33 #define TIMER_CTL_ONESHOT               BIT(7)
  34 #define TIMER_INTVAL_REG(val)   (0x10 * (val) + 0x14)
  35 #define TIMER_CNTVAL_REG(val)   (0x10 * (val) + 0x18)
  36
  37 #define TIMER_SCAL              16
  38
  39 static void __iomem *timer_base;
  40
  41 static void sun4i_clkevt_mode(enum clock_event_mode mode,
  42                               struct clock_event_device *clk)
  43 {
  44         u32 u = readl(timer_base + TIMER_CTL_REG(0));
  45
  46         switch (mode) {
  47         case CLOCK_EVT_MODE_PERIODIC:
  48                 u &= ~(TIMER_CTL_ONESHOT);
  49                 writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
  50                 break;
  51
  52         case CLOCK_EVT_MODE_ONESHOT:
  53                 writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
  54                 break;
  55         case CLOCK_EVT_MODE_UNUSED:
  56         case CLOCK_EVT_MODE_SHUTDOWN:
  57         default:
  58                 writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
  59                 break;
  60         }
  61 }
  62
  63 static int sun4i_clkevt_next_event(unsigned long evt,
  64                                    struct clock_event_device *unused)
  65 {
  66         u32 u = readl(timer_base + TIMER_CTL_REG(0));
  67         writel(evt, timer_base + TIMER_CNTVAL_REG(0));
  68         writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
  69                timer_base + TIMER_CTL_REG(0));
  70
  71         return 0;
  72 }
  73
  74 static struct clock_event_device sun4i_clockevent = {
  75         .name = "sun4i_tick",
  76         .rating = 300,
  77         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  78         .set_mode = sun4i_clkevt_mode,
  79         .set_next_event = sun4i_clkevt_next_event,
  80 };
  81
  82
  83 static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
  84 {
  85         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
  86
  87         writel(0x1, timer_base + TIMER_IRQ_ST_REG);
  88         evt->event_handler(evt);
  89
  90         return IRQ_HANDLED;
  91 }
  92
  93 static struct irqaction sun4i_timer_irq = {
  94         .name = "sun4i_timer0",
  95         .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  96         .handler = sun4i_timer_interrupt,
  97         .dev_id = &sun4i_clockevent,
  98 };
  99
 100 static u32 sun4i_timer_sched_read(void)
 101 {
 102         return ~readl(timer_base + TIMER_CNTVAL_REG(1));
 103 }
 104
 105 static void __init sun4i_timer_init(struct device_node *node)
 106 {
 107         unsigned long rate = 0;
 108         struct clk *clk;
 109         int ret, irq;
 110         u32 val;
 111
 112         timer_base = of_iomap(node, 0);
 113         if (!timer_base)
 114                 panic("Can't map registers");
 115
 116         irq = irq_of_parse_and_map(node, 0);
 117         if (irq <= 0)
 118                 panic("Can't parse IRQ");
 119
 120         clk = of_clk_get(node, 0);
 121         if (IS_ERR(clk))
 122                 panic("Can't get timer clock");
 123
 124         rate = clk_get_rate(clk);
 125
 126         writel(~0, timer_base + TIMER_INTVAL_REG(1));
 127         writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
 128                TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
 129                timer_base + TIMER_CTL_REG(1));
 130
 131         setup_sched_clock(sun4i_timer_sched_read, 32, rate);
 132         clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
 133                               rate, 300, 32, clocksource_mmio_readl_down);
 134
 135         writel(rate / (TIMER_SCAL * HZ),
 136                timer_base + TIMER_INTVAL_REG(0));
 137
 138         /* set clock source to HOSC, 16 pre-division */
 139         val = readl(timer_base + TIMER_CTL_REG(0));
 140         val &= ~(0x07 << 4);
 141         val &= ~(0x03 << 2);
 142         val |= (4 << 4) | (1 << 2);
 143         writel(val, timer_base + TIMER_CTL_REG(0));
 144
 145         /* set mode to auto reload */
 146         val = readl(timer_base + TIMER_CTL_REG(0));
 147         writel(val | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0));
 148
 149         ret = setup_irq(irq, &sun4i_timer_irq);
 150         if (ret)
 151                 pr_warn("failed to setup irq %d\n", irq);
 152
 153         /* Enable timer0 interrupt */
 154         val = readl(timer_base + TIMER_IRQ_EN_REG);
 155         writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
 156
 157         sun4i_clockevent.cpumask = cpumask_of(0);
 158
 159         clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
 160                                         0x1, 0xff);
 161 }
 162 CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
 163                        sun4i_timer_init);