2 * (C) Copyright 2009 Intel Corporation
3 * Author: Jacob Pan (jacob.jun.pan@intel.com)
5 * Shared with ARM platforms, Jamie Iles, Picochip 2011
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Support for the Synopsys DesignWare APB Timers.
13 #include <linux/dw_apb_timer.h>
14 #include <linux/delay.h>
15 #include <linux/kernel.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <linux/slab.h>
21 #define APBT_MIN_PERIOD 4
22 #define APBT_MIN_DELTA_USEC 200
24 #define APBTMRS_INT_STATUS 0xa0
25 #define APBTMRS_EOI 0xa4
26 #define APBTMRS_RAW_INT_STATUS 0xa8
27 #define APBTMRS_COMP_VERSION 0xac
29 #define APBTMR_CONTROL_ENABLE (1 << 0)
30 /* 1: periodic, 0:free running. */
31 #define APBTMR_CONTROL_MODE_PERIODIC (1 << 1)
32 #define APBTMR_CONTROL_INT (1 << 2)
34 static inline struct dw_apb_clock_event_device *
35 ced_to_dw_apb_ced(struct clock_event_device *evt)
37 return container_of(evt, struct dw_apb_clock_event_device, ced);
40 static inline struct dw_apb_clocksource *
41 clocksource_to_dw_apb_clocksource(struct clocksource *cs)
43 return container_of(cs, struct dw_apb_clocksource, cs);
46 static unsigned long apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
48 return readl(timer->base + offs);
51 static void apbt_writel(struct dw_apb_timer *timer, unsigned long val,
54 writel(val, timer->base + offs);
57 static void apbt_disable_int(struct dw_apb_timer *timer)
59 unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
61 ctrl |= APBTMR_CONTROL_INT;
62 apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
66 * dw_apb_clockevent_pause() - stop the clock_event_device from running
68 * @dw_ced: The APB clock to stop generating events.
70 void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced)
72 disable_irq(dw_ced->timer.irq);
73 apbt_disable_int(&dw_ced->timer);
76 static void apbt_eoi(struct dw_apb_timer *timer)
78 apbt_readl(timer, APBTMR_N_EOI);
81 static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
83 struct clock_event_device *evt = data;
84 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
86 if (!evt->event_handler) {
87 pr_info("Spurious APBT timer interrupt %d", irq);
92 dw_ced->eoi(&dw_ced->timer);
94 evt->event_handler(evt);
98 static void apbt_enable_int(struct dw_apb_timer *timer)
100 unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
101 /* clear pending intr */
102 apbt_readl(timer, APBTMR_N_EOI);
103 ctrl &= ~APBTMR_CONTROL_INT;
104 apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
107 static void apbt_set_mode(enum clock_event_mode mode,
108 struct clock_event_device *evt)
111 unsigned long period;
112 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
114 pr_debug("%s CPU %d mode=%d\n", __func__, first_cpu(*evt->cpumask),
118 case CLOCK_EVT_MODE_PERIODIC:
119 period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
120 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
121 ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
122 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
124 * DW APB p. 46, have to disable timer before load counter,
125 * may cause sync problem.
127 ctrl &= ~APBTMR_CONTROL_ENABLE;
128 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
130 pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
131 apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
132 ctrl |= APBTMR_CONTROL_ENABLE;
133 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
136 case CLOCK_EVT_MODE_ONESHOT:
137 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
139 * set free running mode, this mode will let timer reload max
140 * timeout which will give time (3min on 25MHz clock) to rearm
141 * the next event, therefore emulate the one-shot mode.
143 ctrl &= ~APBTMR_CONTROL_ENABLE;
144 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
146 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
147 /* write again to set free running mode */
148 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
151 * DW APB p. 46, load counter with all 1s before starting free
154 apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
155 ctrl &= ~APBTMR_CONTROL_INT;
156 ctrl |= APBTMR_CONTROL_ENABLE;
157 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
160 case CLOCK_EVT_MODE_UNUSED:
161 case CLOCK_EVT_MODE_SHUTDOWN:
162 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
163 ctrl &= ~APBTMR_CONTROL_ENABLE;
164 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
167 case CLOCK_EVT_MODE_RESUME:
168 apbt_enable_int(&dw_ced->timer);
173 static int apbt_next_event(unsigned long delta,
174 struct clock_event_device *evt)
177 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
180 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
181 ctrl &= ~APBTMR_CONTROL_ENABLE;
182 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
183 /* write new count */
184 apbt_writel(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);
185 ctrl |= APBTMR_CONTROL_ENABLE;
186 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
192 * dw_apb_clockevent_init() - use an APB timer as a clock_event_device
194 * @cpu: The CPU the events will be targeted at.
195 * @name: The name used for the timer and the IRQ for it.
196 * @rating: The rating to give the timer.
197 * @base: I/O base for the timer registers.
198 * @irq: The interrupt number to use for the timer.
199 * @freq: The frequency that the timer counts at.
201 * This creates a clock_event_device for using with the generic clock layer
202 * but does not start and register it. This should be done with
203 * dw_apb_clockevent_register() as the next step. If this is the first time
204 * it has been called for a timer then the IRQ will be requested, if not it
205 * just be enabled to allow CPU hotplug to avoid repeatedly requesting and
208 struct dw_apb_clock_event_device *
209 dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
210 void __iomem *base, int irq, unsigned long freq)
212 struct dw_apb_clock_event_device *dw_ced =
213 kzalloc(sizeof(*dw_ced), GFP_KERNEL);
219 dw_ced->timer.base = base;
220 dw_ced->timer.irq = irq;
221 dw_ced->timer.freq = freq;
223 clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD);
224 dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff,
226 dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
227 dw_ced->ced.cpumask = cpumask_of(cpu);
228 dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
229 dw_ced->ced.set_mode = apbt_set_mode;
230 dw_ced->ced.set_next_event = apbt_next_event;
231 dw_ced->ced.irq = dw_ced->timer.irq;
232 dw_ced->ced.rating = rating;
233 dw_ced->ced.name = name;
235 dw_ced->irqaction.name = dw_ced->ced.name;
236 dw_ced->irqaction.handler = dw_apb_clockevent_irq;
237 dw_ced->irqaction.dev_id = &dw_ced->ced;
238 dw_ced->irqaction.irq = irq;
239 dw_ced->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL |
243 dw_ced->eoi = apbt_eoi;
244 err = setup_irq(irq, &dw_ced->irqaction);
246 pr_err("failed to request timer irq\n");
255 * dw_apb_clockevent_resume() - resume a clock that has been paused.
257 * @dw_ced: The APB clock to resume.
259 void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced)
261 enable_irq(dw_ced->timer.irq);
265 * dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
267 * @dw_ced: The APB clock to stop generating the events.
269 void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced)
271 free_irq(dw_ced->timer.irq, &dw_ced->ced);
275 * dw_apb_clockevent_register() - register the clock with the generic layer
277 * @dw_ced: The APB clock to register as a clock_event_device.
279 void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced)
281 apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);
282 clockevents_register_device(&dw_ced->ced);
283 apbt_enable_int(&dw_ced->timer);
287 * dw_apb_clocksource_start() - start the clocksource counting.
289 * @dw_cs: The clocksource to start.
291 * This is used to start the clocksource before registration and can be used
292 * to enable calibration of timers.
294 void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs)
297 * start count down from 0xffff_ffff. this is done by toggling the
298 * enable bit then load initial load count to ~0.
300 unsigned long ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);
302 ctrl &= ~APBTMR_CONTROL_ENABLE;
303 apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
304 apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);
305 /* enable, mask interrupt */
306 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
307 ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
308 apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
309 /* read it once to get cached counter value initialized */
310 dw_apb_clocksource_read(dw_cs);
313 static cycle_t __apbt_read_clocksource(struct clocksource *cs)
315 unsigned long current_count;
316 struct dw_apb_clocksource *dw_cs =
317 clocksource_to_dw_apb_clocksource(cs);
319 current_count = apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
321 return (cycle_t)~current_count;
324 static void apbt_restart_clocksource(struct clocksource *cs)
326 struct dw_apb_clocksource *dw_cs =
327 clocksource_to_dw_apb_clocksource(cs);
329 dw_apb_clocksource_start(dw_cs);
333 * dw_apb_clocksource_init() - use an APB timer as a clocksource.
335 * @rating: The rating to give the clocksource.
336 * @name: The name for the clocksource.
337 * @base: The I/O base for the timer registers.
338 * @freq: The frequency that the timer counts at.
340 * This creates a clocksource using an APB timer but does not yet register it
341 * with the clocksource system. This should be done with
342 * dw_apb_clocksource_register() as the next step.
344 struct dw_apb_clocksource *
345 dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
348 struct dw_apb_clocksource *dw_cs = kzalloc(sizeof(*dw_cs), GFP_KERNEL);
353 dw_cs->timer.base = base;
354 dw_cs->timer.freq = freq;
355 dw_cs->cs.name = name;
356 dw_cs->cs.rating = rating;
357 dw_cs->cs.read = __apbt_read_clocksource;
358 dw_cs->cs.mask = CLOCKSOURCE_MASK(32);
359 dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
360 dw_cs->cs.resume = apbt_restart_clocksource;
366 * dw_apb_clocksource_register() - register the APB clocksource.
368 * @dw_cs: The clocksource to register.
370 void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
372 clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
376 * dw_apb_clocksource_read() - read the current value of a clocksource.
378 * @dw_cs: The clocksource to read.
380 cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs)
382 return (cycle_t)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);