Pileus Git - ~andy/linux/blob - drivers/clk/versatile/clk-integrator.c

   1 #include <linux/clk.h>
   2 #include <linux/clkdev.h>
   3 #include <linux/err.h>
   4 #include <linux/io.h>
   5 #include <linux/clk-provider.h>
   6
   7 #include <mach/hardware.h>
   8 #include <mach/platform.h>
   9
  10 #include "clk-icst.h"
  11
  12 /*
  13  * Implementation of the ARM Integrator/AP and Integrator/CP clock tree.
  14  * Inspired by portions of:
  15  * plat-versatile/clock.c and plat-versatile/include/plat/clock.h
  16  */
  17 #define CM_LOCK         (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
  18 #define CM_AUXOSC       (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
  19
  20 /**
  21  * cp_auxvco_get() - get ICST VCO settings for the Integrator/CP
  22  * @vco: ICST VCO parameters to update with hardware status
  23  */
  24 static struct icst_vco cp_auxvco_get(void)
  25 {
  26         u32 val;
  27         struct icst_vco vco;
  28
  29         val = readl(CM_AUXOSC);
  30         vco.v = val & 0x1ff;
  31         vco.r = (val >> 9) & 0x7f;
  32         vco.s = (val >> 16) & 03;
  33         return vco;
  34 }
  35
  36 /**
  37  * cp_auxvco_set() - commit changes to Integrator/CP ICST VCO
  38  * @vco: ICST VCO parameters to commit
  39  */
  40 static void cp_auxvco_set(struct icst_vco vco)
  41 {
  42         u32 val;
  43
  44         val = readl(CM_AUXOSC) & ~0x7ffff;
  45         val |= vco.v | (vco.r << 9) | (vco.s << 16);
  46
  47         /* This magic unlocks the CM VCO so it can be controlled */
  48         writel(0xa05f, CM_LOCK);
  49         writel(val, CM_AUXOSC);
  50         /* This locks the CM again */
  51         writel(0, CM_LOCK);
  52 }
  53
  54 static const struct icst_params cp_auxvco_params = {
  55         .ref            = 24000000,
  56         .vco_max        = ICST525_VCO_MAX_5V,
  57         .vco_min        = ICST525_VCO_MIN,
  58         .vd_min         = 8,
  59         .vd_max         = 263,
  60         .rd_min         = 3,
  61         .rd_max         = 65,
  62         .s2div          = icst525_s2div,
  63         .idx2s          = icst525_idx2s,
  64 };
  65
  66 static const struct clk_icst_desc __initdata cp_icst_desc = {
  67         .params = &cp_auxvco_params,
  68         .getvco = cp_auxvco_get,
  69         .setvco = cp_auxvco_set,
  70 };
  71
  72 /*
  73  * integrator_clk_init() - set up the integrator clock tree
  74  * @is_cp: pass true if it's the Integrator/CP else AP is assumed
  75  */
  76 void __init integrator_clk_init(bool is_cp)
  77 {
  78         struct clk *clk;
  79
  80         /* APB clock dummy */
  81         clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
  82         clk_register_clkdev(clk, "apb_pclk", NULL);
  83
  84         /* UART reference clock */
  85         clk = clk_register_fixed_rate(NULL, "uartclk", NULL, CLK_IS_ROOT,
  86                                 14745600);
  87         clk_register_clkdev(clk, NULL, "uart0");
  88         clk_register_clkdev(clk, NULL, "uart1");
  89         if (is_cp)
  90                 clk_register_clkdev(clk, NULL, "mmci");
  91
  92         /* 24 MHz clock */
  93         clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT,
  94                                 24000000);
  95         clk_register_clkdev(clk, NULL, "kmi0");
  96         clk_register_clkdev(clk, NULL, "kmi1");
  97         if (!is_cp)
  98                 clk_register_clkdev(clk, NULL, "ap_timer");
  99
 100         if (!is_cp)
 101                 return;
 102
 103         /* 1 MHz clock */
 104         clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT,
 105                                 1000000);
 106         clk_register_clkdev(clk, NULL, "sp804");
 107
 108         /* ICST VCO clock used on the Integrator/CP CLCD */
 109         clk = icst_clk_register(NULL, &cp_icst_desc);
 110         clk_register_clkdev(clk, NULL, "clcd");
 111 }