Pileus Git - ~andy/linux/blob - drivers/clk/tegra/clk-tegra114.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/clk-provider.h>
  20 #include <linux/clkdev.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/delay.h>
  24 #include <linux/export.h>
  25 #include <linux/clk/tegra.h>
  26
  27 #include "clk.h"
  28
  29 #define RST_DEVICES_L                   0x004
  30 #define RST_DEVICES_H                   0x008
  31 #define RST_DEVICES_U                   0x00C
  32 #define RST_DFLL_DVCO                   0x2F4
  33 #define RST_DEVICES_V                   0x358
  34 #define RST_DEVICES_W                   0x35C
  35 #define RST_DEVICES_X                   0x28C
  36 #define RST_DEVICES_SET_L               0x300
  37 #define RST_DEVICES_CLR_L               0x304
  38 #define RST_DEVICES_SET_H               0x308
  39 #define RST_DEVICES_CLR_H               0x30c
  40 #define RST_DEVICES_SET_U               0x310
  41 #define RST_DEVICES_CLR_U               0x314
  42 #define RST_DEVICES_SET_V               0x430
  43 #define RST_DEVICES_CLR_V               0x434
  44 #define RST_DEVICES_SET_W               0x438
  45 #define RST_DEVICES_CLR_W               0x43c
  46 #define CPU_FINETRIM_SELECT             0x4d4   /* override default prop dlys */
  47 #define CPU_FINETRIM_DR                 0x4d8   /* rise->rise prop dly A */
  48 #define CPU_FINETRIM_R                  0x4e4   /* rise->rise prop dly inc A */
  49 #define RST_DEVICES_NUM                 5
  50
  51 /* RST_DFLL_DVCO bitfields */
  52 #define DVFS_DFLL_RESET_SHIFT           0
  53
  54 /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
  55 #define CPU_FINETRIM_1_FCPU_1           BIT(0)  /* fcpu0 */
  56 #define CPU_FINETRIM_1_FCPU_2           BIT(1)  /* fcpu1 */
  57 #define CPU_FINETRIM_1_FCPU_3           BIT(2)  /* fcpu2 */
  58 #define CPU_FINETRIM_1_FCPU_4           BIT(3)  /* fcpu3 */
  59 #define CPU_FINETRIM_1_FCPU_5           BIT(4)  /* fl2 */
  60 #define CPU_FINETRIM_1_FCPU_6           BIT(5)  /* ftop */
  61
  62 /* CPU_FINETRIM_R bitfields */
  63 #define CPU_FINETRIM_R_FCPU_1_SHIFT     0               /* fcpu0 */
  64 #define CPU_FINETRIM_R_FCPU_1_MASK      (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
  65 #define CPU_FINETRIM_R_FCPU_2_SHIFT     2               /* fcpu1 */
  66 #define CPU_FINETRIM_R_FCPU_2_MASK      (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
  67 #define CPU_FINETRIM_R_FCPU_3_SHIFT     4               /* fcpu2 */
  68 #define CPU_FINETRIM_R_FCPU_3_MASK      (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
  69 #define CPU_FINETRIM_R_FCPU_4_SHIFT     6               /* fcpu3 */
  70 #define CPU_FINETRIM_R_FCPU_4_MASK      (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
  71 #define CPU_FINETRIM_R_FCPU_5_SHIFT     8               /* fl2 */
  72 #define CPU_FINETRIM_R_FCPU_5_MASK      (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
  73 #define CPU_FINETRIM_R_FCPU_6_SHIFT     10              /* ftop */
  74 #define CPU_FINETRIM_R_FCPU_6_MASK      (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
  75
  76 #define CLK_OUT_ENB_L                   0x010
  77 #define CLK_OUT_ENB_H                   0x014
  78 #define CLK_OUT_ENB_U                   0x018
  79 #define CLK_OUT_ENB_V                   0x360
  80 #define CLK_OUT_ENB_W                   0x364
  81 #define CLK_OUT_ENB_X                   0x280
  82 #define CLK_OUT_ENB_SET_L               0x320
  83 #define CLK_OUT_ENB_CLR_L               0x324
  84 #define CLK_OUT_ENB_SET_H               0x328
  85 #define CLK_OUT_ENB_CLR_H               0x32c
  86 #define CLK_OUT_ENB_SET_U               0x330
  87 #define CLK_OUT_ENB_CLR_U               0x334
  88 #define CLK_OUT_ENB_SET_V               0x440
  89 #define CLK_OUT_ENB_CLR_V               0x444
  90 #define CLK_OUT_ENB_SET_W               0x448
  91 #define CLK_OUT_ENB_CLR_W               0x44c
  92 #define CLK_OUT_ENB_SET_X               0x284
  93 #define CLK_OUT_ENB_CLR_X               0x288
  94 #define CLK_OUT_ENB_NUM                 6
  95
  96 #define PLLC_BASE 0x80
  97 #define PLLC_MISC2 0x88
  98 #define PLLC_MISC 0x8c
  99 #define PLLC2_BASE 0x4e8
 100 #define PLLC2_MISC 0x4ec
 101 #define PLLC3_BASE 0x4fc
 102 #define PLLC3_MISC 0x500
 103 #define PLLM_BASE 0x90
 104 #define PLLM_MISC 0x9c
 105 #define PLLP_BASE 0xa0
 106 #define PLLP_MISC 0xac
 107 #define PLLX_BASE 0xe0
 108 #define PLLX_MISC 0xe4
 109 #define PLLX_MISC2 0x514
 110 #define PLLX_MISC3 0x518
 111 #define PLLD_BASE 0xd0
 112 #define PLLD_MISC 0xdc
 113 #define PLLD2_BASE 0x4b8
 114 #define PLLD2_MISC 0x4bc
 115 #define PLLE_BASE 0xe8
 116 #define PLLE_MISC 0xec
 117 #define PLLA_BASE 0xb0
 118 #define PLLA_MISC 0xbc
 119 #define PLLU_BASE 0xc0
 120 #define PLLU_MISC 0xcc
 121 #define PLLRE_BASE 0x4c4
 122 #define PLLRE_MISC 0x4c8
 123
 124 #define PLL_MISC_LOCK_ENABLE 18
 125 #define PLLC_MISC_LOCK_ENABLE 24
 126 #define PLLDU_MISC_LOCK_ENABLE 22
 127 #define PLLE_MISC_LOCK_ENABLE 9
 128 #define PLLRE_MISC_LOCK_ENABLE 30
 129
 130 #define PLLC_IDDQ_BIT 26
 131 #define PLLX_IDDQ_BIT 3
 132 #define PLLRE_IDDQ_BIT 16
 133
 134 #define PLL_BASE_LOCK BIT(27)
 135 #define PLLE_MISC_LOCK BIT(11)
 136 #define PLLRE_MISC_LOCK BIT(24)
 137 #define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
 138
 139 #define PLLE_AUX 0x48c
 140 #define PLLC_OUT 0x84
 141 #define PLLM_OUT 0x94
 142 #define PLLP_OUTA 0xa4
 143 #define PLLP_OUTB 0xa8
 144 #define PLLA_OUT 0xb4
 145
 146 #define AUDIO_SYNC_CLK_I2S0 0x4a0
 147 #define AUDIO_SYNC_CLK_I2S1 0x4a4
 148 #define AUDIO_SYNC_CLK_I2S2 0x4a8
 149 #define AUDIO_SYNC_CLK_I2S3 0x4ac
 150 #define AUDIO_SYNC_CLK_I2S4 0x4b0
 151 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
 152
 153 #define AUDIO_SYNC_DOUBLER 0x49c
 154
 155 #define PMC_CLK_OUT_CNTRL 0x1a8
 156 #define PMC_DPD_PADS_ORIDE 0x1c
 157 #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
 158 #define PMC_CTRL 0
 159 #define PMC_CTRL_BLINK_ENB 7
 160 #define PMC_BLINK_TIMER 0x40
 161
 162 #define OSC_CTRL                        0x50
 163 #define OSC_CTRL_OSC_FREQ_SHIFT         28
 164 #define OSC_CTRL_PLL_REF_DIV_SHIFT      26
 165
 166 #define PLLXC_SW_MAX_P                  6
 167
 168 #define CCLKG_BURST_POLICY 0x368
 169 #define CCLKLP_BURST_POLICY 0x370
 170 #define SCLK_BURST_POLICY 0x028
 171 #define SYSTEM_CLK_RATE 0x030
 172
 173 #define UTMIP_PLL_CFG2 0x488
 174 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
 175 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 176 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 177 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 178 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 179
 180 #define UTMIP_PLL_CFG1 0x484
 181 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
 182 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 183 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
 184 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 185 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
 186 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 187 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 188
 189 #define UTMIPLL_HW_PWRDN_CFG0                   0x52c
 190 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE   BIT(25)
 191 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE        BIT(24)
 192 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET       BIT(6)
 193 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE     BIT(5)
 194 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL      BIT(4)
 195 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL  BIT(2)
 196 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE     BIT(1)
 197 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL        BIT(0)
 198
 199 #define CLK_SOURCE_I2S0 0x1d8
 200 #define CLK_SOURCE_I2S1 0x100
 201 #define CLK_SOURCE_I2S2 0x104
 202 #define CLK_SOURCE_NDFLASH 0x160
 203 #define CLK_SOURCE_I2S3 0x3bc
 204 #define CLK_SOURCE_I2S4 0x3c0
 205 #define CLK_SOURCE_SPDIF_OUT 0x108
 206 #define CLK_SOURCE_SPDIF_IN 0x10c
 207 #define CLK_SOURCE_PWM 0x110
 208 #define CLK_SOURCE_ADX 0x638
 209 #define CLK_SOURCE_AMX 0x63c
 210 #define CLK_SOURCE_HDA 0x428
 211 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
 212 #define CLK_SOURCE_SBC1 0x134
 213 #define CLK_SOURCE_SBC2 0x118
 214 #define CLK_SOURCE_SBC3 0x11c
 215 #define CLK_SOURCE_SBC4 0x1b4
 216 #define CLK_SOURCE_SBC5 0x3c8
 217 #define CLK_SOURCE_SBC6 0x3cc
 218 #define CLK_SOURCE_SATA_OOB 0x420
 219 #define CLK_SOURCE_SATA 0x424
 220 #define CLK_SOURCE_NDSPEED 0x3f8
 221 #define CLK_SOURCE_VFIR 0x168
 222 #define CLK_SOURCE_SDMMC1 0x150
 223 #define CLK_SOURCE_SDMMC2 0x154
 224 #define CLK_SOURCE_SDMMC3 0x1bc
 225 #define CLK_SOURCE_SDMMC4 0x164
 226 #define CLK_SOURCE_VDE 0x1c8
 227 #define CLK_SOURCE_CSITE 0x1d4
 228 #define CLK_SOURCE_LA 0x1f8
 229 #define CLK_SOURCE_TRACE 0x634
 230 #define CLK_SOURCE_OWR 0x1cc
 231 #define CLK_SOURCE_NOR 0x1d0
 232 #define CLK_SOURCE_MIPI 0x174
 233 #define CLK_SOURCE_I2C1 0x124
 234 #define CLK_SOURCE_I2C2 0x198
 235 #define CLK_SOURCE_I2C3 0x1b8
 236 #define CLK_SOURCE_I2C4 0x3c4
 237 #define CLK_SOURCE_I2C5 0x128
 238 #define CLK_SOURCE_UARTA 0x178
 239 #define CLK_SOURCE_UARTB 0x17c
 240 #define CLK_SOURCE_UARTC 0x1a0
 241 #define CLK_SOURCE_UARTD 0x1c0
 242 #define CLK_SOURCE_UARTE 0x1c4
 243 #define CLK_SOURCE_UARTA_DBG 0x178
 244 #define CLK_SOURCE_UARTB_DBG 0x17c
 245 #define CLK_SOURCE_UARTC_DBG 0x1a0
 246 #define CLK_SOURCE_UARTD_DBG 0x1c0
 247 #define CLK_SOURCE_UARTE_DBG 0x1c4
 248 #define CLK_SOURCE_3D 0x158
 249 #define CLK_SOURCE_2D 0x15c
 250 #define CLK_SOURCE_VI_SENSOR 0x1a8
 251 #define CLK_SOURCE_VI 0x148
 252 #define CLK_SOURCE_EPP 0x16c
 253 #define CLK_SOURCE_MSENC 0x1f0
 254 #define CLK_SOURCE_TSEC 0x1f4
 255 #define CLK_SOURCE_HOST1X 0x180
 256 #define CLK_SOURCE_HDMI 0x18c
 257 #define CLK_SOURCE_DISP1 0x138
 258 #define CLK_SOURCE_DISP2 0x13c
 259 #define CLK_SOURCE_CILAB 0x614
 260 #define CLK_SOURCE_CILCD 0x618
 261 #define CLK_SOURCE_CILE 0x61c
 262 #define CLK_SOURCE_DSIALP 0x620
 263 #define CLK_SOURCE_DSIBLP 0x624
 264 #define CLK_SOURCE_TSENSOR 0x3b8
 265 #define CLK_SOURCE_D_AUDIO 0x3d0
 266 #define CLK_SOURCE_DAM0 0x3d8
 267 #define CLK_SOURCE_DAM1 0x3dc
 268 #define CLK_SOURCE_DAM2 0x3e0
 269 #define CLK_SOURCE_ACTMON 0x3e8
 270 #define CLK_SOURCE_EXTERN1 0x3ec
 271 #define CLK_SOURCE_EXTERN2 0x3f0
 272 #define CLK_SOURCE_EXTERN3 0x3f4
 273 #define CLK_SOURCE_I2CSLOW 0x3fc
 274 #define CLK_SOURCE_SE 0x42c
 275 #define CLK_SOURCE_MSELECT 0x3b4
 276 #define CLK_SOURCE_DFLL_REF 0x62c
 277 #define CLK_SOURCE_DFLL_SOC 0x630
 278 #define CLK_SOURCE_SOC_THERM 0x644
 279 #define CLK_SOURCE_XUSB_HOST_SRC 0x600
 280 #define CLK_SOURCE_XUSB_FALCON_SRC 0x604
 281 #define CLK_SOURCE_XUSB_FS_SRC 0x608
 282 #define CLK_SOURCE_XUSB_SS_SRC 0x610
 283 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c
 284 #define CLK_SOURCE_EMC 0x19c
 285
 286 /* PLLM override registers */
 287 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
 288 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
 289
 290 /* Tegra CPU clock and reset control regs */
 291 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
 292
 293 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 294
 295 static void __iomem *clk_base;
 296 static void __iomem *pmc_base;
 297
 298 static DEFINE_SPINLOCK(pll_d_lock);
 299 static DEFINE_SPINLOCK(pll_d2_lock);
 300 static DEFINE_SPINLOCK(pll_u_lock);
 301 static DEFINE_SPINLOCK(pll_div_lock);
 302 static DEFINE_SPINLOCK(pll_re_lock);
 303 static DEFINE_SPINLOCK(clk_doubler_lock);
 304 static DEFINE_SPINLOCK(clk_out_lock);
 305 static DEFINE_SPINLOCK(sysrate_lock);
 306
 307 static struct div_nmp pllxc_nmp = {
 308         .divm_shift = 0,
 309         .divm_width = 8,
 310         .divn_shift = 8,
 311         .divn_width = 8,
 312         .divp_shift = 20,
 313         .divp_width = 4,
 314 };
 315
 316 static struct pdiv_map pllxc_p[] = {
 317         { .pdiv = 1, .hw_val = 0 },
 318         { .pdiv = 2, .hw_val = 1 },
 319         { .pdiv = 3, .hw_val = 2 },
 320         { .pdiv = 4, .hw_val = 3 },
 321         { .pdiv = 5, .hw_val = 4 },
 322         { .pdiv = 6, .hw_val = 5 },
 323         { .pdiv = 8, .hw_val = 6 },
 324         { .pdiv = 10, .hw_val = 7 },
 325         { .pdiv = 12, .hw_val = 8 },
 326         { .pdiv = 16, .hw_val = 9 },
 327         { .pdiv = 12, .hw_val = 10 },
 328         { .pdiv = 16, .hw_val = 11 },
 329         { .pdiv = 20, .hw_val = 12 },
 330         { .pdiv = 24, .hw_val = 13 },
 331         { .pdiv = 32, .hw_val = 14 },
 332         { .pdiv = 0, .hw_val = 0 },
 333 };
 334
 335 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
 336         { 12000000, 624000000, 104, 0, 2},
 337         { 12000000, 600000000, 100, 0, 2},
 338         { 13000000, 600000000,  92, 0, 2},      /* actual: 598.0 MHz */
 339         { 16800000, 600000000,  71, 0, 2},      /* actual: 596.4 MHz */
 340         { 19200000, 600000000,  62, 0, 2},      /* actual: 595.2 MHz */
 341         { 26000000, 600000000,  92, 1, 2},      /* actual: 598.0 MHz */
 342         { 0, 0, 0, 0, 0, 0 },
 343 };
 344
 345 static struct tegra_clk_pll_params pll_c_params = {
 346         .input_min = 12000000,
 347         .input_max = 800000000,
 348         .cf_min = 12000000,
 349         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
 350         .vco_min = 600000000,
 351         .vco_max = 1400000000,
 352         .base_reg = PLLC_BASE,
 353         .misc_reg = PLLC_MISC,
 354         .lock_mask = PLL_BASE_LOCK,
 355         .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
 356         .lock_delay = 300,
 357         .iddq_reg = PLLC_MISC,
 358         .iddq_bit_idx = PLLC_IDDQ_BIT,
 359         .max_p = PLLXC_SW_MAX_P,
 360         .dyn_ramp_reg = PLLC_MISC2,
 361         .stepa_shift = 17,
 362         .stepb_shift = 9,
 363         .pdiv_tohw = pllxc_p,
 364         .div_nmp = &pllxc_nmp,
 365 };
 366
 367 static struct div_nmp pllcx_nmp = {
 368         .divm_shift = 0,
 369         .divm_width = 2,
 370         .divn_shift = 8,
 371         .divn_width = 8,
 372         .divp_shift = 20,
 373         .divp_width = 3,
 374 };
 375
 376 static struct pdiv_map pllc_p[] = {
 377         { .pdiv = 1, .hw_val = 0 },
 378         { .pdiv = 2, .hw_val = 1 },
 379         { .pdiv = 4, .hw_val = 3 },
 380         { .pdiv = 8, .hw_val = 5 },
 381         { .pdiv = 16, .hw_val = 7 },
 382         { .pdiv = 0, .hw_val = 0 },
 383 };
 384
 385 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
 386         {12000000, 600000000, 100, 0, 2},
 387         {13000000, 600000000, 92, 0, 2},        /* actual: 598.0 MHz */
 388         {16800000, 600000000, 71, 0, 2},        /* actual: 596.4 MHz */
 389         {19200000, 600000000, 62, 0, 2},        /* actual: 595.2 MHz */
 390         {26000000, 600000000, 92, 1, 2},        /* actual: 598.0 MHz */
 391         {0, 0, 0, 0, 0, 0},
 392 };
 393
 394 static struct tegra_clk_pll_params pll_c2_params = {
 395         .input_min = 12000000,
 396         .input_max = 48000000,
 397         .cf_min = 12000000,
 398         .cf_max = 19200000,
 399         .vco_min = 600000000,
 400         .vco_max = 1200000000,
 401         .base_reg = PLLC2_BASE,
 402         .misc_reg = PLLC2_MISC,
 403         .lock_mask = PLL_BASE_LOCK,
 404         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 405         .lock_delay = 300,
 406         .pdiv_tohw = pllc_p,
 407         .div_nmp = &pllcx_nmp,
 408         .max_p = 7,
 409         .ext_misc_reg[0] = 0x4f0,
 410         .ext_misc_reg[1] = 0x4f4,
 411         .ext_misc_reg[2] = 0x4f8,
 412 };
 413
 414 static struct tegra_clk_pll_params pll_c3_params = {
 415         .input_min = 12000000,
 416         .input_max = 48000000,
 417         .cf_min = 12000000,
 418         .cf_max = 19200000,
 419         .vco_min = 600000000,
 420         .vco_max = 1200000000,
 421         .base_reg = PLLC3_BASE,
 422         .misc_reg = PLLC3_MISC,
 423         .lock_mask = PLL_BASE_LOCK,
 424         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 425         .lock_delay = 300,
 426         .pdiv_tohw = pllc_p,
 427         .div_nmp = &pllcx_nmp,
 428         .max_p = 7,
 429         .ext_misc_reg[0] = 0x504,
 430         .ext_misc_reg[1] = 0x508,
 431         .ext_misc_reg[2] = 0x50c,
 432 };
 433
 434 static struct div_nmp pllm_nmp = {
 435         .divm_shift = 0,
 436         .divm_width = 8,
 437         .override_divm_shift = 0,
 438         .divn_shift = 8,
 439         .divn_width = 8,
 440         .override_divn_shift = 8,
 441         .divp_shift = 20,
 442         .divp_width = 1,
 443         .override_divp_shift = 27,
 444 };
 445
 446 static struct pdiv_map pllm_p[] = {
 447         { .pdiv = 1, .hw_val = 0 },
 448         { .pdiv = 2, .hw_val = 1 },
 449         { .pdiv = 0, .hw_val = 0 },
 450 };
 451
 452 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
 453         {12000000, 800000000, 66, 0, 1},        /* actual: 792.0 MHz */
 454         {13000000, 800000000, 61, 0, 1},        /* actual: 793.0 MHz */
 455         {16800000, 800000000, 47, 0, 1},        /* actual: 789.6 MHz */
 456         {19200000, 800000000, 41, 0, 1},        /* actual: 787.2 MHz */
 457         {26000000, 800000000, 61, 1, 1},        /* actual: 793.0 MHz */
 458         {0, 0, 0, 0, 0, 0},
 459 };
 460
 461 static struct tegra_clk_pll_params pll_m_params = {
 462         .input_min = 12000000,
 463         .input_max = 500000000,
 464         .cf_min = 12000000,
 465         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
 466         .vco_min = 400000000,
 467         .vco_max = 1066000000,
 468         .base_reg = PLLM_BASE,
 469         .misc_reg = PLLM_MISC,
 470         .lock_mask = PLL_BASE_LOCK,
 471         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 472         .lock_delay = 300,
 473         .max_p = 2,
 474         .pdiv_tohw = pllm_p,
 475         .div_nmp = &pllm_nmp,
 476         .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
 477         .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
 478 };
 479
 480 static struct div_nmp pllp_nmp = {
 481         .divm_shift = 0,
 482         .divm_width = 5,
 483         .divn_shift = 8,
 484         .divn_width = 10,
 485         .divp_shift = 20,
 486         .divp_width = 3,
 487 };
 488
 489 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
 490         {12000000, 216000000, 432, 12, 1, 8},
 491         {13000000, 216000000, 432, 13, 1, 8},
 492         {16800000, 216000000, 360, 14, 1, 8},
 493         {19200000, 216000000, 360, 16, 1, 8},
 494         {26000000, 216000000, 432, 26, 1, 8},
 495         {0, 0, 0, 0, 0, 0},
 496 };
 497
 498 static struct tegra_clk_pll_params pll_p_params = {
 499         .input_min = 2000000,
 500         .input_max = 31000000,
 501         .cf_min = 1000000,
 502         .cf_max = 6000000,
 503         .vco_min = 200000000,
 504         .vco_max = 700000000,
 505         .base_reg = PLLP_BASE,
 506         .misc_reg = PLLP_MISC,
 507         .lock_mask = PLL_BASE_LOCK,
 508         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 509         .lock_delay = 300,
 510         .div_nmp = &pllp_nmp,
 511 };
 512
 513 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
 514         {9600000, 282240000, 147, 5, 0, 4},
 515         {9600000, 368640000, 192, 5, 0, 4},
 516         {9600000, 240000000, 200, 8, 0, 8},
 517
 518         {28800000, 282240000, 245, 25, 0, 8},
 519         {28800000, 368640000, 320, 25, 0, 8},
 520         {28800000, 240000000, 200, 24, 0, 8},
 521         {0, 0, 0, 0, 0, 0},
 522 };
 523
 524
 525 static struct tegra_clk_pll_params pll_a_params = {
 526         .input_min = 2000000,
 527         .input_max = 31000000,
 528         .cf_min = 1000000,
 529         .cf_max = 6000000,
 530         .vco_min = 200000000,
 531         .vco_max = 700000000,
 532         .base_reg = PLLA_BASE,
 533         .misc_reg = PLLA_MISC,
 534         .lock_mask = PLL_BASE_LOCK,
 535         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 536         .lock_delay = 300,
 537         .div_nmp = &pllp_nmp,
 538 };
 539
 540 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
 541         {12000000, 216000000, 864, 12, 2, 12},
 542         {13000000, 216000000, 864, 13, 2, 12},
 543         {16800000, 216000000, 720, 14, 2, 12},
 544         {19200000, 216000000, 720, 16, 2, 12},
 545         {26000000, 216000000, 864, 26, 2, 12},
 546
 547         {12000000, 594000000, 594, 12, 0, 12},
 548         {13000000, 594000000, 594, 13, 0, 12},
 549         {16800000, 594000000, 495, 14, 0, 12},
 550         {19200000, 594000000, 495, 16, 0, 12},
 551         {26000000, 594000000, 594, 26, 0, 12},
 552
 553         {12000000, 1000000000, 1000, 12, 0, 12},
 554         {13000000, 1000000000, 1000, 13, 0, 12},
 555         {19200000, 1000000000, 625, 12, 0, 12},
 556         {26000000, 1000000000, 1000, 26, 0, 12},
 557
 558         {0, 0, 0, 0, 0, 0},
 559 };
 560
 561 static struct tegra_clk_pll_params pll_d_params = {
 562         .input_min = 2000000,
 563         .input_max = 40000000,
 564         .cf_min = 1000000,
 565         .cf_max = 6000000,
 566         .vco_min = 500000000,
 567         .vco_max = 1000000000,
 568         .base_reg = PLLD_BASE,
 569         .misc_reg = PLLD_MISC,
 570         .lock_mask = PLL_BASE_LOCK,
 571         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 572         .lock_delay = 1000,
 573         .div_nmp = &pllp_nmp,
 574 };
 575
 576 static struct tegra_clk_pll_params pll_d2_params = {
 577         .input_min = 2000000,
 578         .input_max = 40000000,
 579         .cf_min = 1000000,
 580         .cf_max = 6000000,
 581         .vco_min = 500000000,
 582         .vco_max = 1000000000,
 583         .base_reg = PLLD2_BASE,
 584         .misc_reg = PLLD2_MISC,
 585         .lock_mask = PLL_BASE_LOCK,
 586         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 587         .lock_delay = 1000,
 588         .div_nmp = &pllp_nmp,
 589 };
 590
 591 static struct pdiv_map pllu_p[] = {
 592         { .pdiv = 1, .hw_val = 1 },
 593         { .pdiv = 2, .hw_val = 0 },
 594         { .pdiv = 0, .hw_val = 0 },
 595 };
 596
 597 static struct div_nmp pllu_nmp = {
 598         .divm_shift = 0,
 599         .divm_width = 5,
 600         .divn_shift = 8,
 601         .divn_width = 10,
 602         .divp_shift = 20,
 603         .divp_width = 1,
 604 };
 605
 606 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
 607         {12000000, 480000000, 960, 12, 0, 12},
 608         {13000000, 480000000, 960, 13, 0, 12},
 609         {16800000, 480000000, 400, 7, 0, 5},
 610         {19200000, 480000000, 200, 4, 0, 3},
 611         {26000000, 480000000, 960, 26, 0, 12},
 612         {0, 0, 0, 0, 0, 0},
 613 };
 614
 615 static struct tegra_clk_pll_params pll_u_params = {
 616         .input_min = 2000000,
 617         .input_max = 40000000,
 618         .cf_min = 1000000,
 619         .cf_max = 6000000,
 620         .vco_min = 480000000,
 621         .vco_max = 960000000,
 622         .base_reg = PLLU_BASE,
 623         .misc_reg = PLLU_MISC,
 624         .lock_mask = PLL_BASE_LOCK,
 625         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 626         .lock_delay = 1000,
 627         .pdiv_tohw = pllu_p,
 628         .div_nmp = &pllu_nmp,
 629 };
 630
 631 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
 632         /* 1 GHz */
 633         {12000000, 1000000000, 83, 0, 1},       /* actual: 996.0 MHz */
 634         {13000000, 1000000000, 76, 0, 1},       /* actual: 988.0 MHz */
 635         {16800000, 1000000000, 59, 0, 1},       /* actual: 991.2 MHz */
 636         {19200000, 1000000000, 52, 0, 1},       /* actual: 998.4 MHz */
 637         {26000000, 1000000000, 76, 1, 1},       /* actual: 988.0 MHz */
 638
 639         {0, 0, 0, 0, 0, 0},
 640 };
 641
 642 static struct tegra_clk_pll_params pll_x_params = {
 643         .input_min = 12000000,
 644         .input_max = 800000000,
 645         .cf_min = 12000000,
 646         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
 647         .vco_min = 700000000,
 648         .vco_max = 2400000000U,
 649         .base_reg = PLLX_BASE,
 650         .misc_reg = PLLX_MISC,
 651         .lock_mask = PLL_BASE_LOCK,
 652         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 653         .lock_delay = 300,
 654         .iddq_reg = PLLX_MISC3,
 655         .iddq_bit_idx = PLLX_IDDQ_BIT,
 656         .max_p = PLLXC_SW_MAX_P,
 657         .dyn_ramp_reg = PLLX_MISC2,
 658         .stepa_shift = 16,
 659         .stepb_shift = 24,
 660         .pdiv_tohw = pllxc_p,
 661         .div_nmp = &pllxc_nmp,
 662 };
 663
 664 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
 665         /* PLLE special case: use cpcon field to store cml divider value */
 666         {336000000, 100000000, 100, 21, 16, 11},
 667         {312000000, 100000000, 200, 26, 24, 13},
 668         {0, 0, 0, 0, 0, 0},
 669 };
 670
 671 static struct div_nmp plle_nmp = {
 672         .divm_shift = 0,
 673         .divm_width = 8,
 674         .divn_shift = 8,
 675         .divn_width = 8,
 676         .divp_shift = 24,
 677         .divp_width = 4,
 678 };
 679
 680 static struct tegra_clk_pll_params pll_e_params = {
 681         .input_min = 12000000,
 682         .input_max = 1000000000,
 683         .cf_min = 12000000,
 684         .cf_max = 75000000,
 685         .vco_min = 1600000000,
 686         .vco_max = 2400000000U,
 687         .base_reg = PLLE_BASE,
 688         .misc_reg = PLLE_MISC,
 689         .aux_reg = PLLE_AUX,
 690         .lock_mask = PLLE_MISC_LOCK,
 691         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
 692         .lock_delay = 300,
 693         .div_nmp = &plle_nmp,
 694 };
 695
 696 static struct div_nmp pllre_nmp = {
 697         .divm_shift = 0,
 698         .divm_width = 8,
 699         .divn_shift = 8,
 700         .divn_width = 8,
 701         .divp_shift = 16,
 702         .divp_width = 4,
 703 };
 704
 705 static struct tegra_clk_pll_params pll_re_vco_params = {
 706         .input_min = 12000000,
 707         .input_max = 1000000000,
 708         .cf_min = 12000000,
 709         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
 710         .vco_min = 300000000,
 711         .vco_max = 600000000,
 712         .base_reg = PLLRE_BASE,
 713         .misc_reg = PLLRE_MISC,
 714         .lock_mask = PLLRE_MISC_LOCK,
 715         .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
 716         .lock_delay = 300,
 717         .iddq_reg = PLLRE_MISC,
 718         .iddq_bit_idx = PLLRE_IDDQ_BIT,
 719         .div_nmp = &pllre_nmp,
 720 };
 721
 722 /* Peripheral clock registers */
 723
 724 static struct tegra_clk_periph_regs periph_l_regs = {
 725         .enb_reg = CLK_OUT_ENB_L,
 726         .enb_set_reg = CLK_OUT_ENB_SET_L,
 727         .enb_clr_reg = CLK_OUT_ENB_CLR_L,
 728         .rst_reg = RST_DEVICES_L,
 729         .rst_set_reg = RST_DEVICES_SET_L,
 730         .rst_clr_reg = RST_DEVICES_CLR_L,
 731 };
 732
 733 static struct tegra_clk_periph_regs periph_h_regs = {
 734         .enb_reg = CLK_OUT_ENB_H,
 735         .enb_set_reg = CLK_OUT_ENB_SET_H,
 736         .enb_clr_reg = CLK_OUT_ENB_CLR_H,
 737         .rst_reg = RST_DEVICES_H,
 738         .rst_set_reg = RST_DEVICES_SET_H,
 739         .rst_clr_reg = RST_DEVICES_CLR_H,
 740 };
 741
 742 static struct tegra_clk_periph_regs periph_u_regs = {
 743         .enb_reg = CLK_OUT_ENB_U,
 744         .enb_set_reg = CLK_OUT_ENB_SET_U,
 745         .enb_clr_reg = CLK_OUT_ENB_CLR_U,
 746         .rst_reg = RST_DEVICES_U,
 747         .rst_set_reg = RST_DEVICES_SET_U,
 748         .rst_clr_reg = RST_DEVICES_CLR_U,
 749 };
 750
 751 static struct tegra_clk_periph_regs periph_v_regs = {
 752         .enb_reg = CLK_OUT_ENB_V,
 753         .enb_set_reg = CLK_OUT_ENB_SET_V,
 754         .enb_clr_reg = CLK_OUT_ENB_CLR_V,
 755         .rst_reg = RST_DEVICES_V,
 756         .rst_set_reg = RST_DEVICES_SET_V,
 757         .rst_clr_reg = RST_DEVICES_CLR_V,
 758 };
 759
 760 static struct tegra_clk_periph_regs periph_w_regs = {
 761         .enb_reg = CLK_OUT_ENB_W,
 762         .enb_set_reg = CLK_OUT_ENB_SET_W,
 763         .enb_clr_reg = CLK_OUT_ENB_CLR_W,
 764         .rst_reg = RST_DEVICES_W,
 765         .rst_set_reg = RST_DEVICES_SET_W,
 766         .rst_clr_reg = RST_DEVICES_CLR_W,
 767 };
 768
 769 /* possible OSC frequencies in Hz */
 770 static unsigned long tegra114_input_freq[] = {
 771         [0] = 13000000,
 772         [1] = 16800000,
 773         [4] = 19200000,
 774         [5] = 38400000,
 775         [8] = 12000000,
 776         [9] = 48000000,
 777         [12] = 260000000,
 778 };
 779
 780 #define MASK(x) (BIT(x) - 1)
 781
 782 #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
 783                             _clk_num, _regs, _gate_flags, _clk_id)      \
 784         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 785                         30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num,    \
 786                         periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
 787                         _parents##_idx, 0)
 788
 789 #define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
 790                             _clk_num, _regs, _gate_flags, _clk_id, flags)\
 791         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 792                         30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num,    \
 793                         periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
 794                         _parents##_idx, flags)
 795
 796 #define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
 797                              _clk_num, _regs, _gate_flags, _clk_id)     \
 798         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 799                         29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num,    \
 800                         periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
 801                         _parents##_idx, 0)
 802
 803 #define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
 804                             _clk_num, _regs, _gate_flags, _clk_id)      \
 805         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 806                         30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
 807                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 808                         _clk_id, _parents##_idx, 0)
 809
 810 #define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
 811                             _clk_num, _regs, _gate_flags, _clk_id, flags)\
 812         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 813                         30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
 814                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 815                         _clk_id, _parents##_idx, flags)
 816
 817 #define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\
 818                             _clk_num, _regs, _gate_flags, _clk_id)      \
 819         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 820                         29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
 821                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 822                         _clk_id, _parents##_idx, 0)
 823
 824 #define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
 825                              _clk_num, _regs, _clk_id)                  \
 826         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 827                         30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\
 828                         _clk_num, periph_clk_enb_refcnt, 0, _clk_id,    \
 829                         _parents##_idx, 0)
 830
 831 #define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\
 832                              _clk_num, _regs, _clk_id)                  \
 833         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 834                         30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num,   \
 835                         periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
 836
 837 #define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
 838                               _mux_shift, _mux_mask, _clk_num, _regs,   \
 839                               _gate_flags, _clk_id)                     \
 840         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 841                         _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs,    \
 842                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 843                         _clk_id, _parents##_idx, 0)
 844
 845 #define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \
 846                              _clk_num, _regs, _gate_flags, _clk_id)      \
 847         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \
 848                         29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
 849                         _clk_num, periph_clk_enb_refcnt, _gate_flags,    \
 850                         _clk_id, _parents##_idx, 0)
 851
 852 #define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset,  _clk_num,\
 853                                  _regs, _gate_flags, _clk_id)           \
 854         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \
 855                         _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \
 856                         periph_clk_enb_refcnt, _gate_flags , _clk_id,   \
 857                         mux_d_audio_clk_idx, 0)
 858
 859 enum tegra114_clk {
 860         rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
 861         ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19,
 862         gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27,
 863         host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40,
 864         sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48,
 865         mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56,
 866         emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65,
 867         i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73,
 868         la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80,
 869         i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91,
 870         csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102,
 871         i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1,
 872         dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x,
 873         audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120,
 874         extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128,
 875         cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148,
 876         dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192,
 877         vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k,
 878         clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2,
 879         pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3,
 880         pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0,
 881         pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0,
 882         pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync,
 883         i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0,
 884         audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
 885         blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
 886         xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
 887         dfll_ref = 264, dfll_soc,
 888
 889         /* Mux clocks */
 890
 891         audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux,
 892         spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux,
 893         dsib_mux, clk_max,
 894 };
 895
 896 struct utmi_clk_param {
 897         /* Oscillator Frequency in KHz */
 898         u32 osc_frequency;
 899         /* UTMIP PLL Enable Delay Count  */
 900         u8 enable_delay_count;
 901         /* UTMIP PLL Stable count */
 902         u8 stable_count;
 903         /*  UTMIP PLL Active delay count */
 904         u8 active_delay_count;
 905         /* UTMIP PLL Xtal frequency count */
 906         u8 xtal_freq_count;
 907 };
 908
 909 static const struct utmi_clk_param utmi_parameters[] = {
 910         {.osc_frequency = 13000000, .enable_delay_count = 0x02,
 911          .stable_count = 0x33, .active_delay_count = 0x05,
 912          .xtal_freq_count = 0x7F},
 913         {.osc_frequency = 19200000, .enable_delay_count = 0x03,
 914          .stable_count = 0x4B, .active_delay_count = 0x06,
 915          .xtal_freq_count = 0xBB},
 916         {.osc_frequency = 12000000, .enable_delay_count = 0x02,
 917          .stable_count = 0x2F, .active_delay_count = 0x04,
 918          .xtal_freq_count = 0x76},
 919         {.osc_frequency = 26000000, .enable_delay_count = 0x04,
 920          .stable_count = 0x66, .active_delay_count = 0x09,
 921          .xtal_freq_count = 0xFE},
 922         {.osc_frequency = 16800000, .enable_delay_count = 0x03,
 923          .stable_count = 0x41, .active_delay_count = 0x0A,
 924          .xtal_freq_count = 0xA4},
 925 };
 926
 927 /* peripheral mux definitions */
 928
 929 #define MUX_I2S_SPDIF(_id)                                              \
 930 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
 931                                                            #_id, "pll_p",\
 932                                                            "clk_m"};
 933 MUX_I2S_SPDIF(audio0)
 934 MUX_I2S_SPDIF(audio1)
 935 MUX_I2S_SPDIF(audio2)
 936 MUX_I2S_SPDIF(audio3)
 937 MUX_I2S_SPDIF(audio4)
 938 MUX_I2S_SPDIF(audio)
 939
 940 #define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
 941 #define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
 942 #define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
 943 #define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
 944 #define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
 945 #define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
 946
 947 static const char *mux_pllp_pllc_pllm_clkm[] = {
 948         "pll_p", "pll_c", "pll_m", "clk_m"
 949 };
 950 #define mux_pllp_pllc_pllm_clkm_idx NULL
 951
 952 static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
 953 #define mux_pllp_pllc_pllm_idx NULL
 954
 955 static const char *mux_pllp_pllc_clk32_clkm[] = {
 956         "pll_p", "pll_c", "clk_32k", "clk_m"
 957 };
 958 #define mux_pllp_pllc_clk32_clkm_idx NULL
 959
 960 static const char *mux_plla_pllc_pllp_clkm[] = {
 961         "pll_a_out0", "pll_c", "pll_p", "clk_m"
 962 };
 963 #define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
 964
 965 static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
 966         "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
 967 };
 968 static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
 969         [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
 970 };
 971
 972 static const char *mux_pllp_clkm[] = {
 973         "pll_p", "clk_m"
 974 };
 975 static u32 mux_pllp_clkm_idx[] = {
 976         [0] = 0, [1] = 3,
 977 };
 978
 979 static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
 980         "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
 981 };
 982 #define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
 983
 984 static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
 985         "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
 986         "pll_d2_out0", "clk_m"
 987 };
 988 #define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
 989
 990 static const char *mux_pllm_pllc_pllp_plla[] = {
 991         "pll_m", "pll_c", "pll_p", "pll_a_out0"
 992 };
 993 #define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
 994
 995 static const char *mux_pllp_pllc_clkm[] = {
 996         "pll_p", "pll_c", "pll_m"
 997 };
 998 static u32 mux_pllp_pllc_clkm_idx[] = {
 999         [0] = 0, [1] = 1, [2] = 3,
1000 };
1001
1002 static const char *mux_pllp_pllc_clkm_clk32[] = {
1003         "pll_p", "pll_c", "clk_m", "clk_32k"
1004 };
1005 #define mux_pllp_pllc_clkm_clk32_idx NULL
1006
1007 static const char *mux_plla_clk32_pllp_clkm_plle[] = {
1008         "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
1009 };
1010 #define mux_plla_clk32_pllp_clkm_plle_idx NULL
1011
1012 static const char *mux_clkm_pllp_pllc_pllre[] = {
1013         "clk_m", "pll_p", "pll_c", "pll_re_out"
1014 };
1015 static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
1016         [0] = 0, [1] = 1, [2] = 3, [3] = 5,
1017 };
1018
1019 static const char *mux_clkm_48M_pllp_480M[] = {
1020         "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
1021 };
1022 #define mux_clkm_48M_pllp_480M_idx NULL
1023
1024 static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
1025         "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
1026 };
1027 static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
1028         [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
1029 };
1030
1031 static const char *mux_plld_out0_plld2_out0[] = {
1032         "pll_d_out0", "pll_d2_out0",
1033 };
1034 #define mux_plld_out0_plld2_out0_idx NULL
1035
1036 static const char *mux_d_audio_clk[] = {
1037         "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
1038         "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
1039 };
1040 static u32 mux_d_audio_clk_idx[] = {
1041         [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
1042         [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
1043 };
1044
1045 static const char *mux_pllmcp_clkm[] = {
1046         "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
1047 };
1048
1049 static const struct clk_div_table pll_re_div_table[] = {
1050         { .val = 0, .div = 1 },
1051         { .val = 1, .div = 2 },
1052         { .val = 2, .div = 3 },
1053         { .val = 3, .div = 4 },
1054         { .val = 4, .div = 5 },
1055         { .val = 5, .div = 6 },
1056         { .val = 0, .div = 0 },
1057 };
1058
1059 static struct clk *clks[clk_max];
1060 static struct clk_onecell_data clk_data;
1061
1062 static unsigned long osc_freq;
1063 static unsigned long pll_ref_freq;
1064
1065 static int __init tegra114_osc_clk_init(void __iomem *clk_base)
1066 {
1067         struct clk *clk;
1068         u32 val, pll_ref_div;
1069
1070         val = readl_relaxed(clk_base + OSC_CTRL);
1071
1072         osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
1073         if (!osc_freq) {
1074                 WARN_ON(1);
1075                 return -EINVAL;
1076         }
1077
1078         /* clk_m */
1079         clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1080                                       osc_freq);
1081         clk_register_clkdev(clk, "clk_m", NULL);
1082         clks[clk_m] = clk;
1083
1084         /* pll_ref */
1085         val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
1086         pll_ref_div = 1 << val;
1087         clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1088                                         CLK_SET_RATE_PARENT, 1, pll_ref_div);
1089         clk_register_clkdev(clk, "pll_ref", NULL);
1090         clks[pll_ref] = clk;
1091
1092         pll_ref_freq = osc_freq / pll_ref_div;
1093
1094         return 0;
1095 }
1096
1097 static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
1098 {
1099         struct clk *clk;
1100
1101         /* clk_32k */
1102         clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1103                                       32768);
1104         clk_register_clkdev(clk, "clk_32k", NULL);
1105         clks[clk_32k] = clk;
1106
1107         /* clk_m_div2 */
1108         clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1109                                         CLK_SET_RATE_PARENT, 1, 2);
1110         clk_register_clkdev(clk, "clk_m_div2", NULL);
1111         clks[clk_m_div2] = clk;
1112
1113         /* clk_m_div4 */
1114         clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1115                                         CLK_SET_RATE_PARENT, 1, 4);
1116         clk_register_clkdev(clk, "clk_m_div4", NULL);
1117         clks[clk_m_div4] = clk;
1118
1119 }
1120
1121 static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
1122 {
1123         u32 reg;
1124         int i;
1125
1126         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1127                 if (osc_freq == utmi_parameters[i].osc_frequency)
1128                         break;
1129         }
1130
1131         if (i >= ARRAY_SIZE(utmi_parameters)) {
1132                 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1133                        osc_freq);
1134                 return;
1135         }
1136
1137         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1138
1139         /* Program UTMIP PLL stable and active counts */
1140         /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1141         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1142         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1143
1144         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1145
1146         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1147                                             active_delay_count);
1148
1149         /* Remove power downs from UTMIP PLL control bits */
1150         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1151         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1152         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1153
1154         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1155
1156         /* Program UTMIP PLL delay and oscillator frequency counts */
1157         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1158         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1159
1160         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1161                                             enable_delay_count);
1162
1163         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1164         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1165                                            xtal_freq_count);
1166
1167         /* Remove power downs from UTMIP PLL control bits */
1168         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1169         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1170         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1171         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1172         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1173
1174         /* Setup HW control of UTMIPLL */
1175         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1176         reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1177         reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1178         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1179         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1180
1181         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1182         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1183         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1184         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1185
1186         udelay(1);
1187
1188         /* Setup SW override of UTMIPLL assuming USB2.0
1189            ports are assigned to USB2 */
1190         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1191         reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1192         reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1193         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1194
1195         udelay(1);
1196
1197         /* Enable HW control UTMIPLL */
1198         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1199         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1200         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1201 }
1202
1203 static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params)
1204 {
1205         pll_params->vco_min =
1206                 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq;
1207 }
1208
1209 static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1210                                       void __iomem *clk_base)
1211 {
1212         u32 val;
1213         u32 step_a, step_b;
1214
1215         switch (pll_ref_freq) {
1216         case 12000000:
1217         case 13000000:
1218         case 26000000:
1219                 step_a = 0x2B;
1220                 step_b = 0x0B;
1221                 break;
1222         case 16800000:
1223                 step_a = 0x1A;
1224                 step_b = 0x09;
1225                 break;
1226         case 19200000:
1227                 step_a = 0x12;
1228                 step_b = 0x08;
1229                 break;
1230         default:
1231                 pr_err("%s: Unexpected reference rate %lu\n",
1232                         __func__, pll_ref_freq);
1233                 WARN_ON(1);
1234                 return -EINVAL;
1235         }
1236
1237         val = step_a << pll_params->stepa_shift;
1238         val |= step_b << pll_params->stepb_shift;
1239         writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1240
1241         return 0;
1242 }
1243
1244 static void __init _init_iddq(struct tegra_clk_pll_params *pll_params,
1245                               void __iomem *clk_base)
1246 {
1247         u32 val, val_iddq;
1248
1249         val = readl_relaxed(clk_base + pll_params->base_reg);
1250         val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1251
1252         if (val & BIT(30))
1253                 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1254         else {
1255                 val_iddq |= BIT(pll_params->iddq_bit_idx);
1256                 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1257         }
1258 }
1259
1260 static void __init tegra114_pll_init(void __iomem *clk_base,
1261                                      void __iomem *pmc)
1262 {
1263         u32 val;
1264         struct clk *clk;
1265
1266         /* PLLC */
1267         _clip_vco_min(&pll_c_params);
1268         if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) {
1269                 _init_iddq(&pll_c_params, clk_base);
1270                 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1271                                 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK,
1272                                 pll_c_freq_table, NULL);
1273                 clk_register_clkdev(clk, "pll_c", NULL);
1274                 clks[pll_c] = clk;
1275
1276                 /* PLLC_OUT1 */
1277                 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1278                                 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1279                                 8, 8, 1, NULL);
1280                 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1281                                         clk_base + PLLC_OUT, 1, 0,
1282                                         CLK_SET_RATE_PARENT, 0, NULL);
1283                 clk_register_clkdev(clk, "pll_c_out1", NULL);
1284                 clks[pll_c_out1] = clk;
1285         }
1286
1287         /* PLLC2 */
1288         _clip_vco_min(&pll_c2_params);
1289         clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0,
1290                              &pll_c2_params, TEGRA_PLL_USE_LOCK,
1291                              pll_cx_freq_table, NULL);
1292         clk_register_clkdev(clk, "pll_c2", NULL);
1293         clks[pll_c2] = clk;
1294
1295         /* PLLC3 */
1296         _clip_vco_min(&pll_c3_params);
1297         clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0,
1298                              &pll_c3_params, TEGRA_PLL_USE_LOCK,
1299                              pll_cx_freq_table, NULL);
1300         clk_register_clkdev(clk, "pll_c3", NULL);
1301         clks[pll_c3] = clk;
1302
1303         /* PLLP */
1304         clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0,
1305                             408000000, &pll_p_params,
1306                             TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
1307                             pll_p_freq_table, NULL);
1308         clk_register_clkdev(clk, "pll_p", NULL);
1309         clks[pll_p] = clk;
1310
1311         /* PLLP_OUT1 */
1312         clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
1313                                 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1314                                 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1315         clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
1316                                 clk_base + PLLP_OUTA, 1, 0,
1317                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1318                                 &pll_div_lock);
1319         clk_register_clkdev(clk, "pll_p_out1", NULL);
1320         clks[pll_p_out1] = clk;
1321
1322         /* PLLP_OUT2 */
1323         clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
1324                                 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1325                                 TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
1326                                 8, 1, &pll_div_lock);
1327         clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
1328                                 clk_base + PLLP_OUTA, 17, 16,
1329                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1330                                 &pll_div_lock);
1331         clk_register_clkdev(clk, "pll_p_out2", NULL);
1332         clks[pll_p_out2] = clk;
1333
1334         /* PLLP_OUT3 */
1335         clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
1336                                 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1337                                 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1338         clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
1339                                 clk_base + PLLP_OUTB, 1, 0,
1340                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1341                                 &pll_div_lock);
1342         clk_register_clkdev(clk, "pll_p_out3", NULL);
1343         clks[pll_p_out3] = clk;
1344
1345         /* PLLP_OUT4 */
1346         clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
1347                                 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1348                                 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
1349                                 &pll_div_lock);
1350         clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
1351                                 clk_base + PLLP_OUTB, 17, 16,
1352                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1353                                 &pll_div_lock);
1354         clk_register_clkdev(clk, "pll_p_out4", NULL);
1355         clks[pll_p_out4] = clk;
1356
1357         /* PLLM */
1358         _clip_vco_min(&pll_m_params);
1359         clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1360                              CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
1361                              &pll_m_params, TEGRA_PLL_USE_LOCK,
1362                              pll_m_freq_table, NULL);
1363         clk_register_clkdev(clk, "pll_m", NULL);
1364         clks[pll_m] = clk;
1365
1366         /* PLLM_OUT1 */
1367         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1368                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1369                                 8, 8, 1, NULL);
1370         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1371                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1372                                 CLK_SET_RATE_PARENT, 0, NULL);
1373         clk_register_clkdev(clk, "pll_m_out1", NULL);
1374         clks[pll_m_out1] = clk;
1375
1376         /* PLLM_UD */
1377         clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1378                                         CLK_SET_RATE_PARENT, 1, 1);
1379
1380         /* PLLX */
1381         _clip_vco_min(&pll_x_params);
1382         if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) {
1383                 _init_iddq(&pll_x_params, clk_base);
1384                 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
1385                                 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params,
1386                                 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL);
1387                 clk_register_clkdev(clk, "pll_x", NULL);
1388                 clks[pll_x] = clk;
1389         }
1390
1391         /* PLLX_OUT0 */
1392         clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
1393                                         CLK_SET_RATE_PARENT, 1, 2);
1394         clk_register_clkdev(clk, "pll_x_out0", NULL);
1395         clks[pll_x_out0] = clk;
1396
1397         /* PLLU */
1398         val = readl(clk_base + pll_u_params.base_reg);
1399         val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1400         writel(val, clk_base + pll_u_params.base_reg);
1401
1402         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1403                             0, &pll_u_params, TEGRA_PLLU |
1404                             TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1405                             TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock);
1406         clk_register_clkdev(clk, "pll_u", NULL);
1407         clks[pll_u] = clk;
1408
1409         tegra114_utmi_param_configure(clk_base);
1410
1411         /* PLLU_480M */
1412         clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1413                                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1414                                 22, 0, &pll_u_lock);
1415         clk_register_clkdev(clk, "pll_u_480M", NULL);
1416         clks[pll_u_480M] = clk;
1417
1418         /* PLLU_60M */
1419         clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1420                                         CLK_SET_RATE_PARENT, 1, 8);
1421         clk_register_clkdev(clk, "pll_u_60M", NULL);
1422         clks[pll_u_60M] = clk;
1423
1424         /* PLLU_48M */
1425         clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1426                                         CLK_SET_RATE_PARENT, 1, 10);
1427         clk_register_clkdev(clk, "pll_u_48M", NULL);
1428         clks[pll_u_48M] = clk;
1429
1430         /* PLLU_12M */
1431         clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1432                                         CLK_SET_RATE_PARENT, 1, 40);
1433         clk_register_clkdev(clk, "pll_u_12M", NULL);
1434         clks[pll_u_12M] = clk;
1435
1436         /* PLLD */
1437         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1438                             0, &pll_d_params,
1439                             TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1440                             TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock);
1441         clk_register_clkdev(clk, "pll_d", NULL);
1442         clks[pll_d] = clk;
1443
1444         /* PLLD_OUT0 */
1445         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1446                                         CLK_SET_RATE_PARENT, 1, 2);
1447         clk_register_clkdev(clk, "pll_d_out0", NULL);
1448         clks[pll_d_out0] = clk;
1449
1450         /* PLLD2 */
1451         clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
1452                             0, &pll_d2_params,
1453                             TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1454                             TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock);
1455         clk_register_clkdev(clk, "pll_d2", NULL);
1456         clks[pll_d2] = clk;
1457
1458         /* PLLD2_OUT0 */
1459         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1460                                         CLK_SET_RATE_PARENT, 1, 2);
1461         clk_register_clkdev(clk, "pll_d2_out0", NULL);
1462         clks[pll_d2_out0] = clk;
1463
1464         /* PLLA */
1465         clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0,
1466                             0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
1467                             TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
1468         clk_register_clkdev(clk, "pll_a", NULL);
1469         clks[pll_a] = clk;
1470
1471         /* PLLA_OUT0 */
1472         clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
1473                                 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1474                                 8, 8, 1, NULL);
1475         clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
1476                                 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
1477                                 CLK_SET_RATE_PARENT, 0, NULL);
1478         clk_register_clkdev(clk, "pll_a_out0", NULL);
1479         clks[pll_a_out0] = clk;
1480
1481         /* PLLRE */
1482         _clip_vco_min(&pll_re_vco_params);
1483         clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1484                              0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK,
1485                              NULL, &pll_re_lock, pll_ref_freq);
1486         clk_register_clkdev(clk, "pll_re_vco", NULL);
1487         clks[pll_re_vco] = clk;
1488
1489         clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1490                                          clk_base + PLLRE_BASE, 16, 4, 0,
1491                                          pll_re_div_table, &pll_re_lock);
1492         clk_register_clkdev(clk, "pll_re_out", NULL);
1493         clks[pll_re_out] = clk;
1494
1495         /* PLLE */
1496         clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco",
1497                                       clk_base, 0, 100000000, &pll_e_params,
1498                                       pll_e_freq_table, NULL);
1499         clk_register_clkdev(clk, "pll_e_out0", NULL);
1500         clks[pll_e_out0] = clk;
1501 }
1502
1503 static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1504         "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
1505 };
1506
1507 static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1508         "clk_m_div4", "extern1",
1509 };
1510
1511 static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1512         "clk_m_div4", "extern2",
1513 };
1514
1515 static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1516         "clk_m_div4", "extern3",
1517 };
1518
1519 static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1520 {
1521         struct clk *clk;
1522
1523         /* spdif_in_sync */
1524         clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1525                                              24000000);
1526         clk_register_clkdev(clk, "spdif_in_sync", NULL);
1527         clks[spdif_in_sync] = clk;
1528
1529         /* i2s0_sync */
1530         clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1531         clk_register_clkdev(clk, "i2s0_sync", NULL);
1532         clks[i2s0_sync] = clk;
1533
1534         /* i2s1_sync */
1535         clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1536         clk_register_clkdev(clk, "i2s1_sync", NULL);
1537         clks[i2s1_sync] = clk;
1538
1539         /* i2s2_sync */
1540         clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1541         clk_register_clkdev(clk, "i2s2_sync", NULL);
1542         clks[i2s2_sync] = clk;
1543
1544         /* i2s3_sync */
1545         clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1546         clk_register_clkdev(clk, "i2s3_sync", NULL);
1547         clks[i2s3_sync] = clk;
1548
1549         /* i2s4_sync */
1550         clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1551         clk_register_clkdev(clk, "i2s4_sync", NULL);
1552         clks[i2s4_sync] = clk;
1553
1554         /* vimclk_sync */
1555         clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1556         clk_register_clkdev(clk, "vimclk_sync", NULL);
1557         clks[vimclk_sync] = clk;
1558
1559         /* audio0 */
1560         clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1561                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1562                                clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
1563                                NULL);
1564         clks[audio0_mux] = clk;
1565         clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1566                                 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1567                                 CLK_GATE_SET_TO_DISABLE, NULL);
1568         clk_register_clkdev(clk, "audio0", NULL);
1569         clks[audio0] = clk;
1570
1571         /* audio1 */
1572         clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1573                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1574                                clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
1575                                NULL);
1576         clks[audio1_mux] = clk;
1577         clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1578                                 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1579                                 CLK_GATE_SET_TO_DISABLE, NULL);
1580         clk_register_clkdev(clk, "audio1", NULL);
1581         clks[audio1] = clk;
1582
1583         /* audio2 */
1584         clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1585                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1586                                clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
1587                                NULL);
1588         clks[audio2_mux] = clk;
1589         clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1590                                 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1591                                 CLK_GATE_SET_TO_DISABLE, NULL);
1592         clk_register_clkdev(clk, "audio2", NULL);
1593         clks[audio2] = clk;
1594
1595         /* audio3 */
1596         clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1597                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1598                                clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
1599                                NULL);
1600         clks[audio3_mux] = clk;
1601         clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1602                                 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1603                                 CLK_GATE_SET_TO_DISABLE, NULL);
1604         clk_register_clkdev(clk, "audio3", NULL);
1605         clks[audio3] = clk;
1606
1607         /* audio4 */
1608         clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1609                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1610                                clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
1611                                NULL);
1612         clks[audio4_mux] = clk;
1613         clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1614                                 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1615                                 CLK_GATE_SET_TO_DISABLE, NULL);
1616         clk_register_clkdev(clk, "audio4", NULL);
1617         clks[audio4] = clk;
1618
1619         /* spdif */
1620         clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1621                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1622                                clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
1623                                NULL);
1624         clks[spdif_mux] = clk;
1625         clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1626                                 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1627                                 CLK_GATE_SET_TO_DISABLE, NULL);
1628         clk_register_clkdev(clk, "spdif", NULL);
1629         clks[spdif] = clk;
1630
1631         /* audio0_2x */
1632         clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1633                                         CLK_SET_RATE_PARENT, 2, 1);
1634         clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1635                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1,
1636                                 0, &clk_doubler_lock);
1637         clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1638                                   TEGRA_PERIPH_NO_RESET, clk_base,
1639                                   CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1640                                   periph_clk_enb_refcnt);
1641         clk_register_clkdev(clk, "audio0_2x", NULL);
1642         clks[audio0_2x] = clk;
1643
1644         /* audio1_2x */
1645         clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1646                                         CLK_SET_RATE_PARENT, 2, 1);
1647         clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1648                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1,
1649                                 0, &clk_doubler_lock);
1650         clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1651                                   TEGRA_PERIPH_NO_RESET, clk_base,
1652                                   CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1653                                   periph_clk_enb_refcnt);
1654         clk_register_clkdev(clk, "audio1_2x", NULL);
1655         clks[audio1_2x] = clk;
1656
1657         /* audio2_2x */
1658         clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1659                                         CLK_SET_RATE_PARENT, 2, 1);
1660         clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1661                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1,
1662                                 0, &clk_doubler_lock);
1663         clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1664                                   TEGRA_PERIPH_NO_RESET, clk_base,
1665                                   CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1666                                   periph_clk_enb_refcnt);
1667         clk_register_clkdev(clk, "audio2_2x", NULL);
1668         clks[audio2_2x] = clk;
1669
1670         /* audio3_2x */
1671         clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1672                                         CLK_SET_RATE_PARENT, 2, 1);
1673         clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1674                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1,
1675                                 0, &clk_doubler_lock);
1676         clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1677                                   TEGRA_PERIPH_NO_RESET, clk_base,
1678                                   CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1679                                   periph_clk_enb_refcnt);
1680         clk_register_clkdev(clk, "audio3_2x", NULL);
1681         clks[audio3_2x] = clk;
1682
1683         /* audio4_2x */
1684         clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1685                                         CLK_SET_RATE_PARENT, 2, 1);
1686         clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1687                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1,
1688                                 0, &clk_doubler_lock);
1689         clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1690                                   TEGRA_PERIPH_NO_RESET, clk_base,
1691                                   CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1692                                   periph_clk_enb_refcnt);
1693         clk_register_clkdev(clk, "audio4_2x", NULL);
1694         clks[audio4_2x] = clk;
1695
1696         /* spdif_2x */
1697         clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1698                                         CLK_SET_RATE_PARENT, 2, 1);
1699         clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1700                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1,
1701                                 0, &clk_doubler_lock);
1702         clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1703                                   TEGRA_PERIPH_NO_RESET, clk_base,
1704                                   CLK_SET_RATE_PARENT, 118,
1705                                   &periph_v_regs, periph_clk_enb_refcnt);
1706         clk_register_clkdev(clk, "spdif_2x", NULL);
1707         clks[spdif_2x] = clk;
1708 }
1709
1710 static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1711 {
1712         struct clk *clk;
1713
1714         /* clk_out_1 */
1715         clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1716                                ARRAY_SIZE(clk_out1_parents), 0,
1717                                pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1718                                &clk_out_lock);
1719         clks[clk_out_1_mux] = clk;
1720         clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1721                                 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1722                                 &clk_out_lock);
1723         clk_register_clkdev(clk, "extern1", "clk_out_1");
1724         clks[clk_out_1] = clk;
1725
1726         /* clk_out_2 */
1727         clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1728                                ARRAY_SIZE(clk_out2_parents), 0,
1729                                pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1730                                &clk_out_lock);
1731         clks[clk_out_2_mux] = clk;
1732         clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1733                                 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1734                                 &clk_out_lock);
1735         clk_register_clkdev(clk, "extern2", "clk_out_2");
1736         clks[clk_out_2] = clk;
1737
1738         /* clk_out_3 */
1739         clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1740                                ARRAY_SIZE(clk_out3_parents), 0,
1741                                pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1742                                &clk_out_lock);
1743         clks[clk_out_3_mux] = clk;
1744         clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1745                                 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1746                                 &clk_out_lock);
1747         clk_register_clkdev(clk, "extern3", "clk_out_3");
1748         clks[clk_out_3] = clk;
1749
1750         /* blink */
1751         /* clear the blink timer register to directly output clk_32k */
1752         writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1753         clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1754                                 pmc_base + PMC_DPD_PADS_ORIDE,
1755                                 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1756         clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1757                                 pmc_base + PMC_CTRL,
1758                                 PMC_CTRL_BLINK_ENB, 0, NULL);
1759         clk_register_clkdev(clk, "blink", NULL);
1760         clks[blink] = clk;
1761
1762 }
1763
1764 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1765                                "pll_p", "pll_p_out2", "unused",
1766                                "clk_32k", "pll_m_out1" };
1767
1768 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1769                                         "pll_p", "pll_p_out4", "unused",
1770                                         "unused", "pll_x" };
1771
1772 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1773                                          "pll_p", "pll_p_out4", "unused",
1774                                          "unused", "pll_x", "pll_x_out0" };
1775
1776 static void __init tegra114_super_clk_init(void __iomem *clk_base)
1777 {
1778         struct clk *clk;
1779
1780         /* CCLKG */
1781         clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1782                                         ARRAY_SIZE(cclk_g_parents),
1783                                         CLK_SET_RATE_PARENT,
1784                                         clk_base + CCLKG_BURST_POLICY,
1785                                         0, 4, 0, 0, NULL);
1786         clk_register_clkdev(clk, "cclk_g", NULL);
1787         clks[cclk_g] = clk;
1788
1789         /* CCLKLP */
1790         clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1791                                         ARRAY_SIZE(cclk_lp_parents),
1792                                         CLK_SET_RATE_PARENT,
1793                                         clk_base + CCLKLP_BURST_POLICY,
1794                                         0, 4, 8, 9, NULL);
1795         clk_register_clkdev(clk, "cclk_lp", NULL);
1796         clks[cclk_lp] = clk;
1797
1798         /* SCLK */
1799         clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1800                                         ARRAY_SIZE(sclk_parents),
1801                                         CLK_SET_RATE_PARENT,
1802                                         clk_base + SCLK_BURST_POLICY,
1803                                         0, 4, 0, 0, NULL);
1804         clk_register_clkdev(clk, "sclk", NULL);
1805         clks[sclk] = clk;
1806
1807         /* HCLK */
1808         clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1809                                    clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1810                                    &sysrate_lock);
1811         clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT |
1812                                 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1813                                 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1814         clk_register_clkdev(clk, "hclk", NULL);
1815         clks[hclk] = clk;
1816
1817         /* PCLK */
1818         clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1819                                    clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1820                                    &sysrate_lock);
1821         clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
1822                                 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1823                                 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1824         clk_register_clkdev(clk, "pclk", NULL);
1825         clks[pclk] = clk;
1826 }
1827
1828 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1829         TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1830         TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1831         TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1832         TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1833         TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1834         TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1835         TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1836         TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm),
1837         TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx),
1838         TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx),
1839         TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda),
1840         TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x),
1841         TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1842         TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1843         TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1844         TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1845         TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1846         TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1847         TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1848         TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1849         TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1850         TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
1851         TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
1852         TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
1853         TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
1854         TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
1855         TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED),
1856         TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1857         TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace),
1858         TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1859         TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
1860         TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1861         TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1),
1862         TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2),
1863         TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3),
1864         TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4),
1865         TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5),
1866         TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
1867         TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
1868         TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
1869         TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
1870         TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
1871         TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
1872         TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1873         TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
1874         TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
1875         TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, msenc),
1876         TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec),
1877         TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
1878         TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
1879         TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab),
1880         TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd),
1881         TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile),
1882         TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp),
1883         TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp),
1884         TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1885         TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
1886         TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
1887         TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
1888         TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
1889         TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1890         TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se),
1891         TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED),
1892         TEGRA_INIT_DATA_MUX("dfll_ref", "ref", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_ref),
1893         TEGRA_INIT_DATA_MUX("dfll_soc", "soc", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_soc),
1894         TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm),
1895         TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src),
1896         TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src),
1897         TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src),
1898         TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src),
1899         TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src),
1900         TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio),
1901         TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0),
1902         TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1),
1903         TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2),
1904 };
1905
1906 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1907         TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1),
1908         TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2),
1909 };
1910
1911 static __init void tegra114_periph_clk_init(void __iomem *clk_base)
1912 {
1913         struct tegra_periph_init_data *data;
1914         struct clk *clk;
1915         int i;
1916         u32 val;
1917
1918         /* apbdma */
1919         clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base,
1920                                   0, 34, &periph_h_regs,
1921                                   periph_clk_enb_refcnt);
1922         clks[apbdma] = clk;
1923
1924         /* rtc */
1925         clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1926                                     TEGRA_PERIPH_ON_APB |
1927                                     TEGRA_PERIPH_NO_RESET, clk_base,
1928                                     0, 4, &periph_l_regs,
1929                                     periph_clk_enb_refcnt);
1930         clk_register_clkdev(clk, NULL, "rtc-tegra");
1931         clks[rtc] = clk;
1932
1933         /* kbc */
1934         clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1935                                     TEGRA_PERIPH_ON_APB |
1936                                     TEGRA_PERIPH_NO_RESET, clk_base,
1937                                     0, 36, &periph_h_regs,
1938                                     periph_clk_enb_refcnt);
1939         clks[kbc] = clk;
1940
1941         /* timer */
1942         clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
1943                                   0, 5, &periph_l_regs,
1944                                   periph_clk_enb_refcnt);
1945         clk_register_clkdev(clk, NULL, "timer");
1946         clks[timer] = clk;
1947
1948         /* kfuse */
1949         clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1950                                   TEGRA_PERIPH_ON_APB, clk_base,  0, 40,
1951                                   &periph_h_regs, periph_clk_enb_refcnt);
1952         clks[kfuse] = clk;
1953
1954         /* fuse */
1955         clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1956                                   TEGRA_PERIPH_ON_APB, clk_base,  0, 39,
1957                                   &periph_h_regs, periph_clk_enb_refcnt);
1958         clks[fuse] = clk;
1959
1960         /* fuse_burn */
1961         clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1962                                   TEGRA_PERIPH_ON_APB, clk_base,  0, 39,
1963                                   &periph_h_regs, periph_clk_enb_refcnt);
1964         clks[fuse_burn] = clk;
1965
1966         /* apbif */
1967         clk = tegra_clk_register_periph_gate("apbif", "clk_m",
1968                                   TEGRA_PERIPH_ON_APB, clk_base,  0, 107,
1969                                   &periph_v_regs, periph_clk_enb_refcnt);
1970         clks[apbif] = clk;
1971
1972         /* hda2hdmi */
1973         clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1974                                     TEGRA_PERIPH_ON_APB, clk_base,  0, 128,
1975                                     &periph_w_regs, periph_clk_enb_refcnt);
1976         clks[hda2hdmi] = clk;
1977
1978         /* vcp */
1979         clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base,  0,
1980                                   29, &periph_l_regs,
1981                                   periph_clk_enb_refcnt);
1982         clks[vcp] = clk;
1983
1984         /* bsea */
1985         clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base,
1986                                   0, 62, &periph_h_regs,
1987                                   periph_clk_enb_refcnt);
1988         clks[bsea] = clk;
1989
1990         /* bsev */
1991         clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base,
1992                                   0, 63, &periph_h_regs,
1993                                   periph_clk_enb_refcnt);
1994         clks[bsev] = clk;
1995
1996         /* mipi-cal */
1997         clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
1998                                    0, 56, &periph_h_regs,
1999                                   periph_clk_enb_refcnt);
2000         clks[mipi_cal] = clk;
2001
2002         /* usbd */
2003         clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base,
2004                                   0, 22, &periph_l_regs,
2005                                   periph_clk_enb_refcnt);
2006         clks[usbd] = clk;
2007
2008         /* usb2 */
2009         clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base,
2010                                   0, 58, &periph_h_regs,
2011                                   periph_clk_enb_refcnt);
2012         clks[usb2] = clk;
2013
2014         /* usb3 */
2015         clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base,
2016                                   0, 59, &periph_h_regs,
2017                                   periph_clk_enb_refcnt);
2018         clks[usb3] = clk;
2019
2020         /* csi */
2021         clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
2022                                    0, 52, &periph_h_regs,
2023                                   periph_clk_enb_refcnt);
2024         clks[csi] = clk;
2025
2026         /* isp */
2027         clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0,
2028                                   23, &periph_l_regs,
2029                                   periph_clk_enb_refcnt);
2030         clks[isp] = clk;
2031
2032         /* csus */
2033         clk = tegra_clk_register_periph_gate("csus", "clk_m",
2034                                   TEGRA_PERIPH_NO_RESET, clk_base, 0, 92,
2035                                   &periph_u_regs, periph_clk_enb_refcnt);
2036         clks[csus] = clk;
2037
2038         /* dds */
2039         clk = tegra_clk_register_periph_gate("dds", "clk_m",
2040                                   TEGRA_PERIPH_ON_APB, clk_base, 0, 150,
2041                                   &periph_w_regs, periph_clk_enb_refcnt);
2042         clks[dds] = clk;
2043
2044         /* dp2 */
2045         clk = tegra_clk_register_periph_gate("dp2", "clk_m",
2046                                   TEGRA_PERIPH_ON_APB, clk_base, 0, 152,
2047                                   &periph_w_regs, periph_clk_enb_refcnt);
2048         clks[dp2] = clk;
2049
2050         /* dtv */
2051         clk = tegra_clk_register_periph_gate("dtv", "clk_m",
2052                                     TEGRA_PERIPH_ON_APB, clk_base, 0, 79,
2053                                     &periph_u_regs, periph_clk_enb_refcnt);
2054         clks[dtv] = clk;
2055
2056         /* dsia */
2057         clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
2058                                ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
2059                                clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
2060         clks[dsia_mux] = clk;
2061         clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
2062                                     0, 48, &periph_h_regs,
2063                                     periph_clk_enb_refcnt);
2064         clks[dsia] = clk;
2065
2066         /* dsib */
2067         clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
2068                                ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
2069                                clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
2070         clks[dsib_mux] = clk;
2071         clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
2072                                     0, 82, &periph_u_regs,
2073                                     periph_clk_enb_refcnt);
2074         clks[dsib] = clk;
2075
2076         /* xusb_hs_src */
2077         val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
2078         val |= BIT(25); /* always select PLLU_60M */
2079         writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
2080
2081         clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
2082                                         1, 1);
2083         clks[xusb_hs_src] = clk;
2084
2085         /* xusb_host */
2086         clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0,
2087                                     clk_base, 0, 89, &periph_u_regs,
2088                                     periph_clk_enb_refcnt);
2089         clks[xusb_host] = clk;
2090
2091         /* xusb_ss */
2092         clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0,
2093                                     clk_base, 0, 156, &periph_w_regs,
2094                                     periph_clk_enb_refcnt);
2095         clks[xusb_host] = clk;
2096
2097         /* xusb_dev */
2098         clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0,
2099                                     clk_base, 0, 95, &periph_u_regs,
2100                                     periph_clk_enb_refcnt);
2101         clks[xusb_dev] = clk;
2102
2103         /* emc */
2104         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
2105                                ARRAY_SIZE(mux_pllmcp_clkm), 0,
2106                                clk_base + CLK_SOURCE_EMC,
2107                                29, 3, 0, NULL);
2108         clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
2109                                 CLK_IGNORE_UNUSED, 57, &periph_h_regs,
2110                                 periph_clk_enb_refcnt);
2111         clks[emc] = clk;
2112
2113         for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
2114                 data = &tegra_periph_clk_list[i];
2115                 clk = tegra_clk_register_periph(data->name, data->parent_names,
2116                                 data->num_parents, &data->periph,
2117                                 clk_base, data->offset, data->flags);
2118                 clks[data->clk_id] = clk;
2119         }
2120
2121         for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
2122                 data = &tegra_periph_nodiv_clk_list[i];
2123                 clk = tegra_clk_register_periph_nodiv(data->name,
2124                                 data->parent_names, data->num_parents,
2125                                 &data->periph, clk_base, data->offset);
2126                 clks[data->clk_id] = clk;
2127         }
2128 }
2129
2130 /* Tegra114 CPU clock and reset control functions */
2131 static void tegra114_wait_cpu_in_reset(u32 cpu)
2132 {
2133         unsigned int reg;
2134
2135         do {
2136                 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2137                 cpu_relax();
2138         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
2139 }
2140 static void tegra114_disable_cpu_clock(u32 cpu)
2141 {
2142         /* flow controller would take care in the power sequence. */
2143 }
2144
2145 static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
2146         .wait_for_reset = tegra114_wait_cpu_in_reset,
2147         .disable_clock  = tegra114_disable_cpu_clock,
2148 };
2149
2150 static const struct of_device_id pmc_match[] __initconst = {
2151         { .compatible = "nvidia,tegra114-pmc" },
2152         {},
2153 };
2154
2155 /*
2156  * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
2157  * breaks
2158  */
2159 static __initdata struct tegra_clk_init_table init_table[] = {
2160         {uarta, pll_p, 408000000, 0},
2161         {uartb, pll_p, 408000000, 0},
2162         {uartc, pll_p, 408000000, 0},
2163         {uartd, pll_p, 408000000, 0},
2164         {pll_a, clk_max, 564480000, 1},
2165         {pll_a_out0, clk_max, 11289600, 1},
2166         {extern1, pll_a_out0, 0, 1},
2167         {clk_out_1_mux, extern1, 0, 1},
2168         {clk_out_1, clk_max, 0, 1},
2169         {i2s0, pll_a_out0, 11289600, 0},
2170         {i2s1, pll_a_out0, 11289600, 0},
2171         {i2s2, pll_a_out0, 11289600, 0},
2172         {i2s3, pll_a_out0, 11289600, 0},
2173         {i2s4, pll_a_out0, 11289600, 0},
2174         {dfll_soc, pll_p, 51000000, 1},
2175         {dfll_ref, pll_p, 51000000, 1},
2176         {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
2177 };
2178
2179 static void __init tegra114_clock_apply_init_table(void)
2180 {
2181         tegra_init_from_table(init_table, clks, clk_max);
2182 }
2183
2184
2185 /**
2186  * tegra114_car_barrier - wait for pending writes to the CAR to complete
2187  *
2188  * Wait for any outstanding writes to the CAR MMIO space from this CPU
2189  * to complete before continuing execution.  No return value.
2190  */
2191 static void tegra114_car_barrier(void)
2192 {
2193         wmb();          /* probably unnecessary */
2194         readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
2195 }
2196
2197 /**
2198  * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
2199  *
2200  * When the CPU rail voltage is in the high-voltage range, use the
2201  * built-in hardwired clock propagation delays in the CPU clock
2202  * shaper.  No return value.
2203  */
2204 void tegra114_clock_tune_cpu_trimmers_high(void)
2205 {
2206         u32 select = 0;
2207
2208         /* Use hardwired rise->rise & fall->fall clock propagation delays */
2209         select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
2210                     CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
2211                     CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
2212         writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
2213
2214         tegra114_car_barrier();
2215 }
2216 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
2217
2218 /**
2219  * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
2220  *
2221  * When the CPU rail voltage is in the low-voltage range, use the
2222  * extended clock propagation delays set by
2223  * tegra114_clock_tune_cpu_trimmers_init().  The intention is to
2224  * maintain the input clock duty cycle that the FCPU subsystem
2225  * expects.  No return value.
2226  */
2227 void tegra114_clock_tune_cpu_trimmers_low(void)
2228 {
2229         u32 select = 0;
2230
2231         /*
2232          * Use software-specified rise->rise & fall->fall clock
2233          * propagation delays (from
2234          * tegra114_clock_tune_cpu_trimmers_init()
2235          */
2236         select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
2237                    CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
2238                    CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
2239         writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
2240
2241         tegra114_car_barrier();
2242 }
2243 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
2244
2245 /**
2246  * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
2247  *
2248  * Program extended clock propagation delays into the FCPU clock
2249  * shaper and enable them.  XXX Define the purpose - peak current
2250  * reduction?  No return value.
2251  */
2252 /* XXX Initial voltage rail state assumption issues? */
2253 void tegra114_clock_tune_cpu_trimmers_init(void)
2254 {
2255         u32 dr = 0, r = 0;
2256
2257         /* Increment the rise->rise clock delay by four steps */
2258         r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
2259               CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
2260               CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
2261         writel_relaxed(r, clk_base + CPU_FINETRIM_R);
2262
2263         /*
2264          * Use the rise->rise clock propagation delay specified in the
2265          * r field
2266          */
2267         dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
2268                CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
2269                CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
2270         writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
2271
2272         tegra114_clock_tune_cpu_trimmers_low();
2273 }
2274 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
2275
2276 /**
2277  * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
2278  *
2279  * Assert the reset line of the DFLL's DVCO.  No return value.
2280  */
2281 void tegra114_clock_assert_dfll_dvco_reset(void)
2282 {
2283         u32 v;
2284
2285         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
2286         v |= (1 << DVFS_DFLL_RESET_SHIFT);
2287         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
2288         tegra114_car_barrier();
2289 }
2290 EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
2291
2292 /**
2293  * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
2294  *
2295  * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
2296  * operate.  No return value.
2297  */
2298 void tegra114_clock_deassert_dfll_dvco_reset(void)
2299 {
2300         u32 v;
2301
2302         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
2303         v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
2304         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
2305         tegra114_car_barrier();
2306 }
2307 EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
2308
2309 static void __init tegra114_clock_init(struct device_node *np)
2310 {
2311         struct device_node *node;
2312         int i;
2313
2314         clk_base = of_iomap(np, 0);
2315         if (!clk_base) {
2316                 pr_err("ioremap tegra114 CAR failed\n");
2317                 return;
2318         }
2319
2320         node = of_find_matching_node(NULL, pmc_match);
2321         if (!node) {
2322                 pr_err("Failed to find pmc node\n");
2323                 WARN_ON(1);
2324                 return;
2325         }
2326
2327         pmc_base = of_iomap(node, 0);
2328         if (!pmc_base) {
2329                 pr_err("Can't map pmc registers\n");
2330                 WARN_ON(1);
2331                 return;
2332         }
2333
2334         if (tegra114_osc_clk_init(clk_base) < 0)
2335                 return;
2336
2337         tegra114_fixed_clk_init(clk_base);
2338         tegra114_pll_init(clk_base, pmc_base);
2339         tegra114_periph_clk_init(clk_base);
2340         tegra114_audio_clk_init(clk_base);
2341         tegra114_pmc_clk_init(pmc_base);
2342         tegra114_super_clk_init(clk_base);
2343
2344         for (i = 0; i < ARRAY_SIZE(clks); i++) {
2345                 if (IS_ERR(clks[i])) {
2346                         pr_err
2347                             ("Tegra114 clk %d: register failed with %ld\n",
2348                              i, PTR_ERR(clks[i]));
2349                 }
2350                 if (!clks[i])
2351                         clks[i] = ERR_PTR(-EINVAL);
2352         }
2353
2354         clk_data.clks = clks;
2355         clk_data.clk_num = ARRAY_SIZE(clks);
2356         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
2357
2358         tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
2359
2360         tegra_cpu_car_ops = &tegra114_cpu_car_ops;
2361 }
2362 CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);