Pileus Git - ~andy/linux/blob - drivers/clk/spear/spear1310_clock.c

   1 /*
   2  * arch/arm/mach-spear13xx/spear1310_clock.c
   3  *
   4  * SPEAr1310 machine clock framework source file
   5  *
   6  * Copyright (C) 2012 ST Microelectronics
   7  * Viresh Kumar <viresh.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/spinlock_types.h>
  20 #include <mach/spear.h>
  21 #include "clk.h"
  22
  23 /* PLL related registers and bit values */
  24 #define SPEAR1310_PLL_CFG                       (VA_MISC_BASE + 0x210)
  25         /* PLL_CFG bit values */
  26         #define SPEAR1310_CLCD_SYNT_CLK_MASK            1
  27         #define SPEAR1310_CLCD_SYNT_CLK_SHIFT           31
  28         #define SPEAR1310_RAS_SYNT2_3_CLK_MASK          2
  29         #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT         29
  30         #define SPEAR1310_RAS_SYNT_CLK_MASK             2
  31         #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT         27
  32         #define SPEAR1310_PLL_CLK_MASK                  2
  33         #define SPEAR1310_PLL3_CLK_SHIFT                24
  34         #define SPEAR1310_PLL2_CLK_SHIFT                22
  35         #define SPEAR1310_PLL1_CLK_SHIFT                20
  36
  37 #define SPEAR1310_PLL1_CTR                      (VA_MISC_BASE + 0x214)
  38 #define SPEAR1310_PLL1_FRQ                      (VA_MISC_BASE + 0x218)
  39 #define SPEAR1310_PLL2_CTR                      (VA_MISC_BASE + 0x220)
  40 #define SPEAR1310_PLL2_FRQ                      (VA_MISC_BASE + 0x224)
  41 #define SPEAR1310_PLL3_CTR                      (VA_MISC_BASE + 0x22C)
  42 #define SPEAR1310_PLL3_FRQ                      (VA_MISC_BASE + 0x230)
  43 #define SPEAR1310_PLL4_CTR                      (VA_MISC_BASE + 0x238)
  44 #define SPEAR1310_PLL4_FRQ                      (VA_MISC_BASE + 0x23C)
  45 #define SPEAR1310_PERIP_CLK_CFG                 (VA_MISC_BASE + 0x244)
  46         /* PERIP_CLK_CFG bit values */
  47         #define SPEAR1310_GPT_OSC24_VAL                 0
  48         #define SPEAR1310_GPT_APB_VAL                   1
  49         #define SPEAR1310_GPT_CLK_MASK                  1
  50         #define SPEAR1310_GPT3_CLK_SHIFT                11
  51         #define SPEAR1310_GPT2_CLK_SHIFT                10
  52         #define SPEAR1310_GPT1_CLK_SHIFT                9
  53         #define SPEAR1310_GPT0_CLK_SHIFT                8
  54         #define SPEAR1310_UART_CLK_PLL5_VAL             0
  55         #define SPEAR1310_UART_CLK_OSC24_VAL            1
  56         #define SPEAR1310_UART_CLK_SYNT_VAL             2
  57         #define SPEAR1310_UART_CLK_MASK                 2
  58         #define SPEAR1310_UART_CLK_SHIFT                4
  59
  60         #define SPEAR1310_AUX_CLK_PLL5_VAL              0
  61         #define SPEAR1310_AUX_CLK_SYNT_VAL              1
  62         #define SPEAR1310_CLCD_CLK_MASK                 2
  63         #define SPEAR1310_CLCD_CLK_SHIFT                2
  64         #define SPEAR1310_C3_CLK_MASK                   1
  65         #define SPEAR1310_C3_CLK_SHIFT                  1
  66
  67 #define SPEAR1310_GMAC_CLK_CFG                  (VA_MISC_BASE + 0x248)
  68         #define SPEAR1310_GMAC_PHY_IF_SEL_MASK          3
  69         #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT         4
  70         #define SPEAR1310_GMAC_PHY_CLK_MASK             1
  71         #define SPEAR1310_GMAC_PHY_CLK_SHIFT            3
  72         #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK       2
  73         #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT      1
  74
  75 #define SPEAR1310_I2S_CLK_CFG                   (VA_MISC_BASE + 0x24C)
  76         /* I2S_CLK_CFG register mask */
  77         #define SPEAR1310_I2S_SCLK_X_MASK               0x1F
  78         #define SPEAR1310_I2S_SCLK_X_SHIFT              27
  79         #define SPEAR1310_I2S_SCLK_Y_MASK               0x1F
  80         #define SPEAR1310_I2S_SCLK_Y_SHIFT              22
  81         #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT         21
  82         #define SPEAR1310_I2S_SCLK_SYNTH_ENB            20
  83         #define SPEAR1310_I2S_PRS1_CLK_X_MASK           0xFF
  84         #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT          12
  85         #define SPEAR1310_I2S_PRS1_CLK_Y_MASK           0xFF
  86         #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT          4
  87         #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT         3
  88         #define SPEAR1310_I2S_REF_SEL_MASK              1
  89         #define SPEAR1310_I2S_REF_SHIFT                 2
  90         #define SPEAR1310_I2S_SRC_CLK_MASK              2
  91         #define SPEAR1310_I2S_SRC_CLK_SHIFT             0
  92
  93 #define SPEAR1310_C3_CLK_SYNT                   (VA_MISC_BASE + 0x250)
  94 #define SPEAR1310_UART_CLK_SYNT                 (VA_MISC_BASE + 0x254)
  95 #define SPEAR1310_GMAC_CLK_SYNT                 (VA_MISC_BASE + 0x258)
  96 #define SPEAR1310_SDHCI_CLK_SYNT                (VA_MISC_BASE + 0x25C)
  97 #define SPEAR1310_CFXD_CLK_SYNT                 (VA_MISC_BASE + 0x260)
  98 #define SPEAR1310_ADC_CLK_SYNT                  (VA_MISC_BASE + 0x264)
  99 #define SPEAR1310_AMBA_CLK_SYNT                 (VA_MISC_BASE + 0x268)
 100 #define SPEAR1310_CLCD_CLK_SYNT                 (VA_MISC_BASE + 0x270)
 101 #define SPEAR1310_RAS_CLK_SYNT0                 (VA_MISC_BASE + 0x280)
 102 #define SPEAR1310_RAS_CLK_SYNT1                 (VA_MISC_BASE + 0x288)
 103 #define SPEAR1310_RAS_CLK_SYNT2                 (VA_MISC_BASE + 0x290)
 104 #define SPEAR1310_RAS_CLK_SYNT3                 (VA_MISC_BASE + 0x298)
 105         /* Check Fractional synthesizer reg masks */
 106
 107 #define SPEAR1310_PERIP1_CLK_ENB                (VA_MISC_BASE + 0x300)
 108         /* PERIP1_CLK_ENB register masks */
 109         #define SPEAR1310_RTC_CLK_ENB                   31
 110         #define SPEAR1310_ADC_CLK_ENB                   30
 111         #define SPEAR1310_C3_CLK_ENB                    29
 112         #define SPEAR1310_JPEG_CLK_ENB                  28
 113         #define SPEAR1310_CLCD_CLK_ENB                  27
 114         #define SPEAR1310_DMA_CLK_ENB                   25
 115         #define SPEAR1310_GPIO1_CLK_ENB                 24
 116         #define SPEAR1310_GPIO0_CLK_ENB                 23
 117         #define SPEAR1310_GPT1_CLK_ENB                  22
 118         #define SPEAR1310_GPT0_CLK_ENB                  21
 119         #define SPEAR1310_I2S0_CLK_ENB                  20
 120         #define SPEAR1310_I2S1_CLK_ENB                  19
 121         #define SPEAR1310_I2C0_CLK_ENB                  18
 122         #define SPEAR1310_SSP_CLK_ENB                   17
 123         #define SPEAR1310_UART_CLK_ENB                  15
 124         #define SPEAR1310_PCIE_SATA_2_CLK_ENB           14
 125         #define SPEAR1310_PCIE_SATA_1_CLK_ENB           13
 126         #define SPEAR1310_PCIE_SATA_0_CLK_ENB           12
 127         #define SPEAR1310_UOC_CLK_ENB                   11
 128         #define SPEAR1310_UHC1_CLK_ENB                  10
 129         #define SPEAR1310_UHC0_CLK_ENB                  9
 130         #define SPEAR1310_GMAC_CLK_ENB                  8
 131         #define SPEAR1310_CFXD_CLK_ENB                  7
 132         #define SPEAR1310_SDHCI_CLK_ENB                 6
 133         #define SPEAR1310_SMI_CLK_ENB                   5
 134         #define SPEAR1310_FSMC_CLK_ENB                  4
 135         #define SPEAR1310_SYSRAM0_CLK_ENB               3
 136         #define SPEAR1310_SYSRAM1_CLK_ENB               2
 137         #define SPEAR1310_SYSROM_CLK_ENB                1
 138         #define SPEAR1310_BUS_CLK_ENB                   0
 139
 140 #define SPEAR1310_PERIP2_CLK_ENB                (VA_MISC_BASE + 0x304)
 141         /* PERIP2_CLK_ENB register masks */
 142         #define SPEAR1310_THSENS_CLK_ENB                8
 143         #define SPEAR1310_I2S_REF_PAD_CLK_ENB           7
 144         #define SPEAR1310_ACP_CLK_ENB                   6
 145         #define SPEAR1310_GPT3_CLK_ENB                  5
 146         #define SPEAR1310_GPT2_CLK_ENB                  4
 147         #define SPEAR1310_KBD_CLK_ENB                   3
 148         #define SPEAR1310_CPU_DBG_CLK_ENB               2
 149         #define SPEAR1310_DDR_CORE_CLK_ENB              1
 150         #define SPEAR1310_DDR_CTRL_CLK_ENB              0
 151
 152 #define SPEAR1310_RAS_CLK_ENB                   (VA_MISC_BASE + 0x310)
 153         /* RAS_CLK_ENB register masks */
 154         #define SPEAR1310_SYNT3_CLK_ENB                 17
 155         #define SPEAR1310_SYNT2_CLK_ENB                 16
 156         #define SPEAR1310_SYNT1_CLK_ENB                 15
 157         #define SPEAR1310_SYNT0_CLK_ENB                 14
 158         #define SPEAR1310_PCLK3_CLK_ENB                 13
 159         #define SPEAR1310_PCLK2_CLK_ENB                 12
 160         #define SPEAR1310_PCLK1_CLK_ENB                 11
 161         #define SPEAR1310_PCLK0_CLK_ENB                 10
 162         #define SPEAR1310_PLL3_CLK_ENB                  9
 163         #define SPEAR1310_PLL2_CLK_ENB                  8
 164         #define SPEAR1310_C125M_PAD_CLK_ENB             7
 165         #define SPEAR1310_C30M_CLK_ENB                  6
 166         #define SPEAR1310_C48M_CLK_ENB                  5
 167         #define SPEAR1310_OSC_25M_CLK_ENB               4
 168         #define SPEAR1310_OSC_32K_CLK_ENB               3
 169         #define SPEAR1310_OSC_24M_CLK_ENB               2
 170         #define SPEAR1310_PCLK_CLK_ENB                  1
 171         #define SPEAR1310_ACLK_CLK_ENB                  0
 172
 173 /* RAS Area Control Register */
 174 #define SPEAR1310_RAS_CTRL_REG0                 (VA_SPEAR1310_RAS_BASE + 0x000)
 175         #define SPEAR1310_SSP1_CLK_MASK                 3
 176         #define SPEAR1310_SSP1_CLK_SHIFT                26
 177         #define SPEAR1310_TDM_CLK_MASK                  1
 178         #define SPEAR1310_TDM2_CLK_SHIFT                24
 179         #define SPEAR1310_TDM1_CLK_SHIFT                23
 180         #define SPEAR1310_I2C_CLK_MASK                  1
 181         #define SPEAR1310_I2C7_CLK_SHIFT                22
 182         #define SPEAR1310_I2C6_CLK_SHIFT                21
 183         #define SPEAR1310_I2C5_CLK_SHIFT                20
 184         #define SPEAR1310_I2C4_CLK_SHIFT                19
 185         #define SPEAR1310_I2C3_CLK_SHIFT                18
 186         #define SPEAR1310_I2C2_CLK_SHIFT                17
 187         #define SPEAR1310_I2C1_CLK_SHIFT                16
 188         #define SPEAR1310_GPT64_CLK_MASK                1
 189         #define SPEAR1310_GPT64_CLK_SHIFT               15
 190         #define SPEAR1310_RAS_UART_CLK_MASK             1
 191         #define SPEAR1310_UART5_CLK_SHIFT               14
 192         #define SPEAR1310_UART4_CLK_SHIFT               13
 193         #define SPEAR1310_UART3_CLK_SHIFT               12
 194         #define SPEAR1310_UART2_CLK_SHIFT               11
 195         #define SPEAR1310_UART1_CLK_SHIFT               10
 196         #define SPEAR1310_PCI_CLK_MASK                  1
 197         #define SPEAR1310_PCI_CLK_SHIFT                 0
 198
 199 #define SPEAR1310_RAS_CTRL_REG1                 (VA_SPEAR1310_RAS_BASE + 0x004)
 200         #define SPEAR1310_PHY_CLK_MASK                  0x3
 201         #define SPEAR1310_RMII_PHY_CLK_SHIFT            0
 202         #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT      2
 203
 204 #define SPEAR1310_RAS_SW_CLK_CTRL               (VA_SPEAR1310_RAS_BASE + 0x0148)
 205         #define SPEAR1310_CAN1_CLK_ENB                  25
 206         #define SPEAR1310_CAN0_CLK_ENB                  24
 207         #define SPEAR1310_GPT64_CLK_ENB                 23
 208         #define SPEAR1310_SSP1_CLK_ENB                  22
 209         #define SPEAR1310_I2C7_CLK_ENB                  21
 210         #define SPEAR1310_I2C6_CLK_ENB                  20
 211         #define SPEAR1310_I2C5_CLK_ENB                  19
 212         #define SPEAR1310_I2C4_CLK_ENB                  18
 213         #define SPEAR1310_I2C3_CLK_ENB                  17
 214         #define SPEAR1310_I2C2_CLK_ENB                  16
 215         #define SPEAR1310_I2C1_CLK_ENB                  15
 216         #define SPEAR1310_UART5_CLK_ENB                 14
 217         #define SPEAR1310_UART4_CLK_ENB                 13
 218         #define SPEAR1310_UART3_CLK_ENB                 12
 219         #define SPEAR1310_UART2_CLK_ENB                 11
 220         #define SPEAR1310_UART1_CLK_ENB                 10
 221         #define SPEAR1310_RS485_1_CLK_ENB               9
 222         #define SPEAR1310_RS485_0_CLK_ENB               8
 223         #define SPEAR1310_TDM2_CLK_ENB                  7
 224         #define SPEAR1310_TDM1_CLK_ENB                  6
 225         #define SPEAR1310_PCI_CLK_ENB                   5
 226         #define SPEAR1310_GMII_CLK_ENB                  4
 227         #define SPEAR1310_MII2_CLK_ENB                  3
 228         #define SPEAR1310_MII1_CLK_ENB                  2
 229         #define SPEAR1310_MII0_CLK_ENB                  1
 230         #define SPEAR1310_ESRAM_CLK_ENB                 0
 231
 232 static DEFINE_SPINLOCK(_lock);
 233
 234 /* pll rate configuration table, in ascending order of rates */
 235 static struct pll_rate_tbl pll_rtbl[] = {
 236         /* PCLK 24MHz */
 237         {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
 238         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
 239         {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
 240         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
 241         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
 242         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
 243         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 244 };
 245
 246 /* vco-pll4 rate configuration table, in ascending order of rates */
 247 static struct pll_rate_tbl pll4_rtbl[] = {
 248         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
 249         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
 250         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
 251         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 252 };
 253
 254 /* aux rate configuration table, in ascending order of rates */
 255 static struct aux_rate_tbl aux_rtbl[] = {
 256         /* For VCO1div2 = 500 MHz */
 257         {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
 258         {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
 259         {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
 260         {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
 261         {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
 262         {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
 263 };
 264
 265 /* gmac rate configuration table, in ascending order of rates */
 266 static struct aux_rate_tbl gmac_rtbl[] = {
 267         /* For gmac phy input clk */
 268         {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
 269         {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
 270         {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
 271         {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
 272 };
 273
 274 /* clcd rate configuration table, in ascending order of rates */
 275 static struct frac_rate_tbl clcd_rtbl[] = {
 276         {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
 277         {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
 278         {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
 279         {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
 280         {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
 281         {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
 282         {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
 283         {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
 284         {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
 285         {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
 286 };
 287
 288 /* i2s prescaler1 masks */
 289 static struct aux_clk_masks i2s_prs1_masks = {
 290         .eq_sel_mask = AUX_EQ_SEL_MASK,
 291         .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
 292         .eq1_mask = AUX_EQ1_SEL,
 293         .eq2_mask = AUX_EQ2_SEL,
 294         .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
 295         .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
 296         .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
 297         .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
 298 };
 299
 300 /* i2s sclk (bit clock) syynthesizers masks */
 301 static struct aux_clk_masks i2s_sclk_masks = {
 302         .eq_sel_mask = AUX_EQ_SEL_MASK,
 303         .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
 304         .eq1_mask = AUX_EQ1_SEL,
 305         .eq2_mask = AUX_EQ2_SEL,
 306         .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
 307         .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
 308         .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
 309         .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
 310         .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
 311 };
 312
 313 /* i2s prs1 aux rate configuration table, in ascending order of rates */
 314 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
 315         /* For parent clk = 49.152 MHz */
 316         {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
 317         {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
 318         {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
 319         {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
 320
 321         /*
 322          * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
 323          * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
 324          */
 325         {.xscale = 1, .yscale = 3, .eq = 0},
 326
 327         /* For parent clk = 49.152 MHz */
 328         {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
 329
 330         {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
 331 };
 332
 333 /* i2s sclk aux rate configuration table, in ascending order of rates */
 334 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
 335         /* For i2s_ref_clk = 12.288MHz */
 336         {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
 337         {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
 338 };
 339
 340 /* adc rate configuration table, in ascending order of rates */
 341 /* possible adc range is 2.5 MHz to 20 MHz. */
 342 static struct aux_rate_tbl adc_rtbl[] = {
 343         /* For ahb = 166.67 MHz */
 344         {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
 345         {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
 346         {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
 347         {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
 348 };
 349
 350 /* General synth rate configuration table, in ascending order of rates */
 351 static struct frac_rate_tbl gen_rtbl[] = {
 352         /* For vco1div4 = 250 MHz */
 353         {.div = 0x14000}, /* 25 MHz */
 354         {.div = 0x0A000}, /* 50 MHz */
 355         {.div = 0x05000}, /* 100 MHz */
 356         {.div = 0x02000}, /* 250 MHz */
 357 };
 358
 359 /* clock parents */
 360 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
 361 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
 362 static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", };
 363 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
 364 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
 365         "osc_25m_clk", };
 366 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
 367 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
 368 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
 369 static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
 370         "i2s_src_pad_clk", };
 371 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
 372 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
 373         "pll3_clk", };
 374 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
 375         "pll2_clk", };
 376 static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
 377         "ras_pll2_clk", "ras_syn0_clk", };
 378 static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
 379         "ras_pll2_clk", "ras_syn0_clk", };
 380 static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", };
 381 static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", };
 382 static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
 383         "ras_plclk0_clk", };
 384 static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
 385 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
 386
 387 void __init spear1310_clk_init(void)
 388 {
 389         struct clk *clk, *clk1;
 390
 391         clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
 392                         32000);
 393         clk_register_clkdev(clk, "osc_32k_clk", NULL);
 394
 395         clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
 396                         24000000);
 397         clk_register_clkdev(clk, "osc_24m_clk", NULL);
 398
 399         clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
 400                         25000000);
 401         clk_register_clkdev(clk, "osc_25m_clk", NULL);
 402
 403         clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT,
 404                         125000000);
 405         clk_register_clkdev(clk, "gmii_pad_clk", NULL);
 406
 407         clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
 408                         CLK_IS_ROOT, 12288000);
 409         clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
 410
 411         /* clock derived from 32 KHz osc clk */
 412         clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
 413                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
 414                         &_lock);
 415         clk_register_clkdev(clk, NULL, "e0580000.rtc");
 416
 417         /* clock derived from 24 or 25 MHz osc clk */
 418         /* vco-pll */
 419         clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
 420                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 421                         SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 422                         &_lock);
 423         clk_register_clkdev(clk, "vco1_mclk", NULL);
 424         clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
 425                         0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
 426                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 427         clk_register_clkdev(clk, "vco1_clk", NULL);
 428         clk_register_clkdev(clk1, "pll1_clk", NULL);
 429
 430         clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
 431                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 432                         SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 433                         &_lock);
 434         clk_register_clkdev(clk, "vco2_mclk", NULL);
 435         clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
 436                         0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
 437                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 438         clk_register_clkdev(clk, "vco2_clk", NULL);
 439         clk_register_clkdev(clk1, "pll2_clk", NULL);
 440
 441         clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
 442                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 443                         SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 444                         &_lock);
 445         clk_register_clkdev(clk, "vco3_mclk", NULL);
 446         clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
 447                         0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
 448                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 449         clk_register_clkdev(clk, "vco3_clk", NULL);
 450         clk_register_clkdev(clk1, "pll3_clk", NULL);
 451
 452         clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
 453                         0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
 454                         ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
 455         clk_register_clkdev(clk, "vco4_clk", NULL);
 456         clk_register_clkdev(clk1, "pll4_clk", NULL);
 457
 458         clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
 459                         48000000);
 460         clk_register_clkdev(clk, "pll5_clk", NULL);
 461
 462         clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
 463                         25000000);
 464         clk_register_clkdev(clk, "pll6_clk", NULL);
 465
 466         /* vco div n clocks */
 467         clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
 468                         2);
 469         clk_register_clkdev(clk, "vco1div2_clk", NULL);
 470
 471         clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
 472                         4);
 473         clk_register_clkdev(clk, "vco1div4_clk", NULL);
 474
 475         clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
 476                         2);
 477         clk_register_clkdev(clk, "vco2div2_clk", NULL);
 478
 479         clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
 480                         2);
 481         clk_register_clkdev(clk, "vco3div2_clk", NULL);
 482
 483         /* peripherals */
 484         clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
 485                         128);
 486         clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
 487                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
 488                         &_lock);
 489         clk_register_clkdev(clk, NULL, "spear_thermal");
 490
 491         /* clock derived from pll4 clk */
 492         clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
 493                         1);
 494         clk_register_clkdev(clk, "ddr_clk", NULL);
 495
 496         /* clock derived from pll1 clk */
 497         clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
 498                         CLK_SET_RATE_PARENT, 1, 2);
 499         clk_register_clkdev(clk, "cpu_clk", NULL);
 500
 501         clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
 502                         2);
 503         clk_register_clkdev(clk, NULL, "ec800620.wdt");
 504
 505         clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
 506                         2);
 507         clk_register_clkdev(clk, NULL, "smp_twd");
 508
 509         clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
 510                         6);
 511         clk_register_clkdev(clk, "ahb_clk", NULL);
 512
 513         clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
 514                         12);
 515         clk_register_clkdev(clk, "apb_clk", NULL);
 516
 517         /* gpt clocks */
 518         clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
 519                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 520                         SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 521                         &_lock);
 522         clk_register_clkdev(clk, "gpt0_mclk", NULL);
 523         clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
 524                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
 525                         &_lock);
 526         clk_register_clkdev(clk, NULL, "gpt0");
 527
 528         clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
 529                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 530                         SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 531                         &_lock);
 532         clk_register_clkdev(clk, "gpt1_mclk", NULL);
 533         clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
 534                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
 535                         &_lock);
 536         clk_register_clkdev(clk, NULL, "gpt1");
 537
 538         clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
 539                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 540                         SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 541                         &_lock);
 542         clk_register_clkdev(clk, "gpt2_mclk", NULL);
 543         clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
 544                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
 545                         &_lock);
 546         clk_register_clkdev(clk, NULL, "gpt2");
 547
 548         clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
 549                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 550                         SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 551                         &_lock);
 552         clk_register_clkdev(clk, "gpt3_mclk", NULL);
 553         clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
 554                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
 555                         &_lock);
 556         clk_register_clkdev(clk, NULL, "gpt3");
 557
 558         /* others */
 559         clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk",
 560                         0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl,
 561                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 562         clk_register_clkdev(clk, "uart_syn_clk", NULL);
 563         clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 564
 565         clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
 566                         ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
 567                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
 568                         SPEAR1310_UART_CLK_MASK, 0, &_lock);
 569         clk_register_clkdev(clk, "uart0_mclk", NULL);
 570
 571         clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
 572                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 573                         SPEAR1310_UART_CLK_ENB, 0, &_lock);
 574         clk_register_clkdev(clk, NULL, "e0000000.serial");
 575
 576         clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
 577                         "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
 578                         aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 579         clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
 580         clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
 581
 582         clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
 583                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 584                         SPEAR1310_SDHCI_CLK_ENB, 0, &_lock);
 585         clk_register_clkdev(clk, NULL, "b3000000.sdhci");
 586
 587         clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
 588                         0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl,
 589                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 590         clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
 591         clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
 592
 593         clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
 594                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 595                         SPEAR1310_CFXD_CLK_ENB, 0, &_lock);
 596         clk_register_clkdev(clk, NULL, "b2800000.cf");
 597         clk_register_clkdev(clk, NULL, "arasan_xd");
 598
 599         clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk",
 600                         0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl,
 601                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 602         clk_register_clkdev(clk, "c3_syn_clk", NULL);
 603         clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
 604
 605         clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
 606                         ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT,
 607                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
 608                         SPEAR1310_C3_CLK_MASK, 0, &_lock);
 609         clk_register_clkdev(clk, "c3_mclk", NULL);
 610
 611         clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
 612                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
 613                         &_lock);
 614         clk_register_clkdev(clk, NULL, "c3");
 615
 616         /* gmac */
 617         clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
 618                         ARRAY_SIZE(gmac_phy_input_parents), 0,
 619                         SPEAR1310_GMAC_CLK_CFG,
 620                         SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
 621                         SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
 622         clk_register_clkdev(clk, "phy_input_mclk", NULL);
 623
 624         clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
 625                         0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl,
 626                         ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
 627         clk_register_clkdev(clk, "phy_syn_clk", NULL);
 628         clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
 629
 630         clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
 631                         ARRAY_SIZE(gmac_phy_parents), 0,
 632                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
 633                         SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
 634         clk_register_clkdev(clk, "stmmacphy.0", NULL);
 635
 636         /* clcd */
 637         clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
 638                         ARRAY_SIZE(clcd_synth_parents), 0,
 639                         SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
 640                         SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
 641         clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
 642
 643         clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
 644                         SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
 645                         ARRAY_SIZE(clcd_rtbl), &_lock);
 646         clk_register_clkdev(clk, "clcd_syn_clk", NULL);
 647
 648         clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
 649                         ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT,
 650                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
 651                         SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
 652         clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
 653
 654         clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
 655                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
 656                         &_lock);
 657         clk_register_clkdev(clk, NULL, "e1000000.clcd");
 658
 659         /* i2s */
 660         clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
 661                         ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
 662                         SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
 663                         0, &_lock);
 664         clk_register_clkdev(clk, "i2s_src_mclk", NULL);
 665
 666         clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
 667                         SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
 668                         ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
 669         clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
 670
 671         clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
 672                         ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
 673                         SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
 674                         SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
 675         clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
 676
 677         clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
 678                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
 679                         0, &_lock);
 680         clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
 681
 682         clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
 683                         "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,
 684                         &i2s_sclk_masks, i2s_sclk_rtbl,
 685                         ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
 686         clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
 687         clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
 688
 689         /* clock derived from ahb clk */
 690         clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
 691                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
 692                         &_lock);
 693         clk_register_clkdev(clk, NULL, "e0280000.i2c");
 694
 695         clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
 696                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
 697                         &_lock);
 698         clk_register_clkdev(clk, NULL, "ea800000.dma");
 699         clk_register_clkdev(clk, NULL, "eb000000.dma");
 700
 701         clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
 702                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
 703                         &_lock);
 704         clk_register_clkdev(clk, NULL, "b2000000.jpeg");
 705
 706         clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
 707                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
 708                         &_lock);
 709         clk_register_clkdev(clk, NULL, "e2000000.eth");
 710
 711         clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
 712                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
 713                         &_lock);
 714         clk_register_clkdev(clk, NULL, "b0000000.flash");
 715
 716         clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
 717                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
 718                         &_lock);
 719         clk_register_clkdev(clk, NULL, "ea000000.flash");
 720
 721         clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
 722                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
 723                         &_lock);
 724         clk_register_clkdev(clk, NULL, "e4000000.ohci");
 725         clk_register_clkdev(clk, NULL, "e4800000.ehci");
 726
 727         clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
 728                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
 729                         &_lock);
 730         clk_register_clkdev(clk, NULL, "e5000000.ohci");
 731         clk_register_clkdev(clk, NULL, "e5800000.ehci");
 732
 733         clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
 734                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
 735                         &_lock);
 736         clk_register_clkdev(clk, NULL, "e3800000.otg");
 737
 738         clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
 739                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
 740                         0, &_lock);
 741         clk_register_clkdev(clk, NULL, "dw_pcie.0");
 742         clk_register_clkdev(clk, NULL, "b1000000.ahci");
 743
 744         clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
 745                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
 746                         0, &_lock);
 747         clk_register_clkdev(clk, NULL, "dw_pcie.1");
 748         clk_register_clkdev(clk, NULL, "b1800000.ahci");
 749
 750         clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
 751                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
 752                         0, &_lock);
 753         clk_register_clkdev(clk, NULL, "dw_pcie.2");
 754         clk_register_clkdev(clk, NULL, "b4000000.ahci");
 755
 756         clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
 757                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
 758                         &_lock);
 759         clk_register_clkdev(clk, "sysram0_clk", NULL);
 760
 761         clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
 762                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
 763                         &_lock);
 764         clk_register_clkdev(clk, "sysram1_clk", NULL);
 765
 766         clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
 767                         0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
 768                         ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
 769         clk_register_clkdev(clk, "adc_syn_clk", NULL);
 770         clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
 771
 772         clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
 773                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 774                         SPEAR1310_ADC_CLK_ENB, 0, &_lock);
 775         clk_register_clkdev(clk, NULL, "e0080000.adc");
 776
 777         /* clock derived from apb clk */
 778         clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
 779                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
 780                         &_lock);
 781         clk_register_clkdev(clk, NULL, "e0100000.spi");
 782
 783         clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
 784                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
 785                         &_lock);
 786         clk_register_clkdev(clk, NULL, "e0600000.gpio");
 787
 788         clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
 789                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
 790                         &_lock);
 791         clk_register_clkdev(clk, NULL, "e0680000.gpio");
 792
 793         clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
 794                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
 795                         &_lock);
 796         clk_register_clkdev(clk, NULL, "e0180000.i2s");
 797
 798         clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
 799                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
 800                         &_lock);
 801         clk_register_clkdev(clk, NULL, "e0200000.i2s");
 802
 803         clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
 804                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
 805                         &_lock);
 806         clk_register_clkdev(clk, NULL, "e0300000.kbd");
 807
 808         /* RAS clks */
 809         clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
 810                         ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1310_PLL_CFG,
 811                         SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
 812                         SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 813         clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
 814
 815         clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
 816                         ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1310_PLL_CFG,
 817                         SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
 818                         SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 819         clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
 820
 821         clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
 822                         SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 823                         &_lock);
 824         clk_register_clkdev(clk, "gen_syn0_clk", NULL);
 825
 826         clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
 827                         SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 828                         &_lock);
 829         clk_register_clkdev(clk, "gen_syn1_clk", NULL);
 830
 831         clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
 832                         SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 833                         &_lock);
 834         clk_register_clkdev(clk, "gen_syn2_clk", NULL);
 835
 836         clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
 837                         SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 838                         &_lock);
 839         clk_register_clkdev(clk, "gen_syn3_clk", NULL);
 840
 841         clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
 842                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
 843                         &_lock);
 844         clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
 845
 846         clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
 847                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
 848                         &_lock);
 849         clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
 850
 851         clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
 852                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
 853                         &_lock);
 854         clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
 855
 856         clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
 857                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
 858                         &_lock);
 859         clk_register_clkdev(clk, "ras_pll2_clk", NULL);
 860
 861         clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
 862                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
 863                         &_lock);
 864         clk_register_clkdev(clk, "ras_pll3_clk", NULL);
 865
 866         clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0,
 867                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
 868                         &_lock);
 869         clk_register_clkdev(clk, "ras_tx125_clk", NULL);
 870
 871         clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
 872                         30000000);
 873         clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
 874                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
 875                         &_lock);
 876         clk_register_clkdev(clk, "ras_30m_clk", NULL);
 877
 878         clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
 879                         48000000);
 880         clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
 881                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
 882                         &_lock);
 883         clk_register_clkdev(clk, "ras_48m_clk", NULL);
 884
 885         clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
 886                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
 887                         &_lock);
 888         clk_register_clkdev(clk, "ras_ahb_clk", NULL);
 889
 890         clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
 891                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
 892                         &_lock);
 893         clk_register_clkdev(clk, "ras_apb_clk", NULL);
 894
 895         clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT,
 896                         50000000);
 897
 898         clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT,
 899                         50000000);
 900
 901         clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
 902                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
 903                         &_lock);
 904         clk_register_clkdev(clk, NULL, "c_can_platform.0");
 905
 906         clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
 907                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
 908                         &_lock);
 909         clk_register_clkdev(clk, NULL, "c_can_platform.1");
 910
 911         clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
 912                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
 913                         &_lock);
 914         clk_register_clkdev(clk, NULL, "5c400000.eth");
 915
 916         clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
 917                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
 918                         &_lock);
 919         clk_register_clkdev(clk, NULL, "5c500000.eth");
 920
 921         clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
 922                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
 923                         &_lock);
 924         clk_register_clkdev(clk, NULL, "5c600000.eth");
 925
 926         clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
 927                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
 928                         &_lock);
 929         clk_register_clkdev(clk, NULL, "5c700000.eth");
 930
 931         clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
 932                         smii_rgmii_phy_parents,
 933                         ARRAY_SIZE(smii_rgmii_phy_parents), 0,
 934                         SPEAR1310_RAS_CTRL_REG1,
 935                         SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
 936                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 937         clk_register_clkdev(clk, "stmmacphy.1", NULL);
 938         clk_register_clkdev(clk, "stmmacphy.2", NULL);
 939         clk_register_clkdev(clk, "stmmacphy.4", NULL);
 940
 941         clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
 942                         ARRAY_SIZE(rmii_phy_parents), 0,
 943                         SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
 944                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 945         clk_register_clkdev(clk, "stmmacphy.3", NULL);
 946
 947         clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
 948                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 949                         SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 950                         0, &_lock);
 951         clk_register_clkdev(clk, "uart1_mclk", NULL);
 952
 953         clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
 954                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
 955                         &_lock);
 956         clk_register_clkdev(clk, NULL, "5c800000.serial");
 957
 958         clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
 959                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 960                         SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 961                         0, &_lock);
 962         clk_register_clkdev(clk, "uart2_mclk", NULL);
 963
 964         clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
 965                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
 966                         &_lock);
 967         clk_register_clkdev(clk, NULL, "5c900000.serial");
 968
 969         clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
 970                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 971                         SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 972                         0, &_lock);
 973         clk_register_clkdev(clk, "uart3_mclk", NULL);
 974
 975         clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
 976                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
 977                         &_lock);
 978         clk_register_clkdev(clk, NULL, "5ca00000.serial");
 979
 980         clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
 981                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 982                         SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 983                         0, &_lock);
 984         clk_register_clkdev(clk, "uart4_mclk", NULL);
 985
 986         clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
 987                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
 988                         &_lock);
 989         clk_register_clkdev(clk, NULL, "5cb00000.serial");
 990
 991         clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
 992                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 993                         SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 994                         0, &_lock);
 995         clk_register_clkdev(clk, "uart5_mclk", NULL);
 996
 997         clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
 998                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
 999                         &_lock);
1000         clk_register_clkdev(clk, NULL, "5cc00000.serial");
1001
1002         clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
1003                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1004                         SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1005                         &_lock);
1006         clk_register_clkdev(clk, "i2c1_mclk", NULL);
1007
1008         clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
1009                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
1010                         &_lock);
1011         clk_register_clkdev(clk, NULL, "5cd00000.i2c");
1012
1013         clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
1014                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1015                         SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1016                         &_lock);
1017         clk_register_clkdev(clk, "i2c2_mclk", NULL);
1018
1019         clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
1020                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1021                         &_lock);
1022         clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1023
1024         clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
1025                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1026                         SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1027                         &_lock);
1028         clk_register_clkdev(clk, "i2c3_mclk", NULL);
1029
1030         clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
1031                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1032                         &_lock);
1033         clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1034
1035         clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
1036                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1037                         SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1038                         &_lock);
1039         clk_register_clkdev(clk, "i2c4_mclk", NULL);
1040
1041         clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
1042                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1043                         &_lock);
1044         clk_register_clkdev(clk, NULL, "5d000000.i2c");
1045
1046         clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
1047                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1048                         SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1049                         &_lock);
1050         clk_register_clkdev(clk, "i2c5_mclk", NULL);
1051
1052         clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
1053                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1054                         &_lock);
1055         clk_register_clkdev(clk, NULL, "5d100000.i2c");
1056
1057         clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
1058                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1059                         SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1060                         &_lock);
1061         clk_register_clkdev(clk, "i2c6_mclk", NULL);
1062
1063         clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
1064                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1065                         &_lock);
1066         clk_register_clkdev(clk, NULL, "5d200000.i2c");
1067
1068         clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
1069                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1070                         SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1071                         &_lock);
1072         clk_register_clkdev(clk, "i2c7_mclk", NULL);
1073
1074         clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
1075                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1076                         &_lock);
1077         clk_register_clkdev(clk, NULL, "5d300000.i2c");
1078
1079         clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
1080                         ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1081                         SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
1082                         &_lock);
1083         clk_register_clkdev(clk, "ssp1_mclk", NULL);
1084
1085         clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
1086                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1087                         &_lock);
1088         clk_register_clkdev(clk, NULL, "5d400000.spi");
1089
1090         clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
1091                         ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1092                         SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
1093                         &_lock);
1094         clk_register_clkdev(clk, "pci_mclk", NULL);
1095
1096         clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
1097                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1098                         &_lock);
1099         clk_register_clkdev(clk, NULL, "pci");
1100
1101         clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
1102                         ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1103                         SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1104                         &_lock);
1105         clk_register_clkdev(clk, "tdm1_mclk", NULL);
1106
1107         clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
1108                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1109                         &_lock);
1110         clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1111
1112         clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
1113                         ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1114                         SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1115                         &_lock);
1116         clk_register_clkdev(clk, "tdm2_mclk", NULL);
1117
1118         clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
1119                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1120                         &_lock);
1121         clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
1122 }