2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Padmavathi Venna <padma.v@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * Common Clock Framework support for Audio Subsystem Clock Controller.
12 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 #include <linux/syscore_ops.h>
18 #include <dt-bindings/clk/exynos-audss-clk.h>
20 static DEFINE_SPINLOCK(lock);
21 static struct clk **clk_table;
22 static void __iomem *reg_base;
23 static struct clk_onecell_data clk_data;
25 #define ASS_CLK_SRC 0x0
26 #define ASS_CLK_DIV 0x4
27 #define ASS_CLK_GATE 0x8
29 static unsigned long reg_save[][2] = {
35 /* list of all parent clock list */
36 static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
37 static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
39 #ifdef CONFIG_PM_SLEEP
40 static int exynos_audss_clk_suspend(void)
44 for (i = 0; i < ARRAY_SIZE(reg_save); i++)
45 reg_save[i][1] = readl(reg_base + reg_save[i][0]);
50 static void exynos_audss_clk_resume(void)
54 for (i = 0; i < ARRAY_SIZE(reg_save); i++)
55 writel(reg_save[i][1], reg_base + reg_save[i][0]);
58 static struct syscore_ops exynos_audss_clk_syscore_ops = {
59 .suspend = exynos_audss_clk_suspend,
60 .resume = exynos_audss_clk_resume,
62 #endif /* CONFIG_PM_SLEEP */
64 /* register exynos_audss clocks */
65 void __init exynos_audss_clk_init(struct device_node *np)
67 reg_base = of_iomap(np, 0);
69 pr_err("%s: failed to map audss registers\n", __func__);
73 clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
76 pr_err("%s: could not allocate clk lookup table\n", __func__);
80 clk_data.clks = clk_table;
81 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
82 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
84 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
85 mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
86 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
88 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
89 mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
90 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
92 clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
93 "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
96 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
97 "dout_aud_bus", "dout_srp", 0,
98 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
100 clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
101 "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
104 clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
105 "dout_srp", CLK_SET_RATE_PARENT,
106 reg_base + ASS_CLK_GATE, 0, 0, &lock);
108 clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
109 "dout_aud_bus", CLK_SET_RATE_PARENT,
110 reg_base + ASS_CLK_GATE, 2, 0, &lock);
112 clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
113 "dout_i2s", CLK_SET_RATE_PARENT,
114 reg_base + ASS_CLK_GATE, 3, 0, &lock);
116 clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
117 "sclk_pcm", CLK_SET_RATE_PARENT,
118 reg_base + ASS_CLK_GATE, 4, 0, &lock);
120 clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
121 "div_pcm0", CLK_SET_RATE_PARENT,
122 reg_base + ASS_CLK_GATE, 5, 0, &lock);
124 #ifdef CONFIG_PM_SLEEP
125 register_syscore_ops(&exynos_audss_clk_syscore_ops);
128 pr_info("Exynos: Audss: clock setup completed\n");
130 CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
131 exynos_audss_clk_init);
132 CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
133 exynos_audss_clk_init);