Pileus Git - ~andy/linux/blob - drivers/clk/clk-vt8500.c

   1 /*
   2  * Clock implementation for VIA/Wondermedia SoC's
   3  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #include <linux/io.h>
  17 #include <linux/of.h>
  18 #include <linux/slab.h>
  19 #include <linux/bitops.h>
  20 #include <linux/clkdev.h>
  21 #include <linux/clk-provider.h>
  22
  23 /* All clocks share the same lock as none can be changed concurrently */
  24 static DEFINE_SPINLOCK(_lock);
  25
  26 struct clk_device {
  27         struct clk_hw   hw;
  28         void __iomem    *div_reg;
  29         unsigned int    div_mask;
  30         void __iomem    *en_reg;
  31         int             en_bit;
  32         spinlock_t      *lock;
  33 };
  34
  35 /*
  36  * Add new PLL_TYPE_x definitions here as required. Use the first known model
  37  * to support the new type as the name.
  38  * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
  39  * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
  40  */
  41
  42 #define PLL_TYPE_VT8500         0
  43 #define PLL_TYPE_WM8650         1
  44
  45 struct clk_pll {
  46         struct clk_hw   hw;
  47         void __iomem    *reg;
  48         spinlock_t      *lock;
  49         int             type;
  50 };
  51
  52 static void __iomem *pmc_base;
  53
  54 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
  55
  56 #define VT8500_PMC_BUSY_MASK            0x18
  57
  58 static void vt8500_pmc_wait_busy(void)
  59 {
  60         while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
  61                 cpu_relax();
  62 }
  63
  64 static int vt8500_dclk_enable(struct clk_hw *hw)
  65 {
  66         struct clk_device *cdev = to_clk_device(hw);
  67         u32 en_val;
  68         unsigned long flags = 0;
  69
  70         spin_lock_irqsave(cdev->lock, flags);
  71
  72         en_val = readl(cdev->en_reg);
  73         en_val |= BIT(cdev->en_bit);
  74         writel(en_val, cdev->en_reg);
  75
  76         spin_unlock_irqrestore(cdev->lock, flags);
  77         return 0;
  78 }
  79
  80 static void vt8500_dclk_disable(struct clk_hw *hw)
  81 {
  82         struct clk_device *cdev = to_clk_device(hw);
  83         u32 en_val;
  84         unsigned long flags = 0;
  85
  86         spin_lock_irqsave(cdev->lock, flags);
  87
  88         en_val = readl(cdev->en_reg);
  89         en_val &= ~BIT(cdev->en_bit);
  90         writel(en_val, cdev->en_reg);
  91
  92         spin_unlock_irqrestore(cdev->lock, flags);
  93 }
  94
  95 static int vt8500_dclk_is_enabled(struct clk_hw *hw)
  96 {
  97         struct clk_device *cdev = to_clk_device(hw);
  98         u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
  99
 100         return en_val ? 1 : 0;
 101 }
 102
 103 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
 104                                 unsigned long parent_rate)
 105 {
 106         struct clk_device *cdev = to_clk_device(hw);
 107         u32 div = readl(cdev->div_reg) & cdev->div_mask;
 108
 109         /* Special case for SDMMC devices */
 110         if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
 111                 div = 64 * (div & 0x1f);
 112
 113         /* div == 0 is actually the highest divisor */
 114         if (div == 0)
 115                 div = (cdev->div_mask + 1);
 116
 117         return parent_rate / div;
 118 }
 119
 120 static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
 121                                 unsigned long *prate)
 122 {
 123         u32 divisor = *prate / rate;
 124
 125         return *prate / divisor;
 126 }
 127
 128 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
 129                                 unsigned long parent_rate)
 130 {
 131         struct clk_device *cdev = to_clk_device(hw);
 132         u32 divisor = parent_rate / rate;
 133         unsigned long flags = 0;
 134
 135         if (divisor == cdev->div_mask + 1)
 136                 divisor = 0;
 137
 138         if (divisor > cdev->div_mask) {
 139                 pr_err("%s: invalid divisor for clock\n", __func__);
 140                 return -EINVAL;
 141         }
 142
 143         spin_lock_irqsave(cdev->lock, flags);
 144
 145         vt8500_pmc_wait_busy();
 146         writel(divisor, cdev->div_reg);
 147         vt8500_pmc_wait_busy();
 148
 149         spin_lock_irqsave(cdev->lock, flags);
 150
 151         return 0;
 152 }
 153
 154
 155 static const struct clk_ops vt8500_gated_clk_ops = {
 156         .enable = vt8500_dclk_enable,
 157         .disable = vt8500_dclk_disable,
 158         .is_enabled = vt8500_dclk_is_enabled,
 159 };
 160
 161 static const struct clk_ops vt8500_divisor_clk_ops = {
 162         .round_rate = vt8500_dclk_round_rate,
 163         .set_rate = vt8500_dclk_set_rate,
 164         .recalc_rate = vt8500_dclk_recalc_rate,
 165 };
 166
 167 static const struct clk_ops vt8500_gated_divisor_clk_ops = {
 168         .enable = vt8500_dclk_enable,
 169         .disable = vt8500_dclk_disable,
 170         .is_enabled = vt8500_dclk_is_enabled,
 171         .round_rate = vt8500_dclk_round_rate,
 172         .set_rate = vt8500_dclk_set_rate,
 173         .recalc_rate = vt8500_dclk_recalc_rate,
 174 };
 175
 176 #define CLK_INIT_GATED                  BIT(0)
 177 #define CLK_INIT_DIVISOR                BIT(1)
 178 #define CLK_INIT_GATED_DIVISOR          (CLK_INIT_DIVISOR | CLK_INIT_GATED)
 179
 180 static __init void vtwm_device_clk_init(struct device_node *node)
 181 {
 182         u32 en_reg, div_reg;
 183         struct clk *clk;
 184         struct clk_device *dev_clk;
 185         const char *clk_name = node->name;
 186         const char *parent_name;
 187         struct clk_init_data init;
 188         int rc;
 189         int clk_init_flags = 0;
 190
 191         dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
 192         if (WARN_ON(!dev_clk))
 193                 return;
 194
 195         dev_clk->lock = &_lock;
 196
 197         rc = of_property_read_u32(node, "enable-reg", &en_reg);
 198         if (!rc) {
 199                 dev_clk->en_reg = pmc_base + en_reg;
 200                 rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
 201                 if (rc) {
 202                         pr_err("%s: enable-bit property required for gated clock\n",
 203                                                                 __func__);
 204                         return;
 205                 }
 206                 clk_init_flags |= CLK_INIT_GATED;
 207         }
 208
 209         rc = of_property_read_u32(node, "divisor-reg", &div_reg);
 210         if (!rc) {
 211                 dev_clk->div_reg = pmc_base + div_reg;
 212                 /*
 213                  * use 0x1f as the default mask since it covers
 214                  * almost all the clocks and reduces dts properties
 215                  */
 216                 dev_clk->div_mask = 0x1f;
 217
 218                 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
 219                 clk_init_flags |= CLK_INIT_DIVISOR;
 220         }
 221
 222         of_property_read_string(node, "clock-output-names", &clk_name);
 223
 224         switch (clk_init_flags) {
 225         case CLK_INIT_GATED:
 226                 init.ops = &vt8500_gated_clk_ops;
 227                 break;
 228         case CLK_INIT_DIVISOR:
 229                 init.ops = &vt8500_divisor_clk_ops;
 230                 break;
 231         case CLK_INIT_GATED_DIVISOR:
 232                 init.ops = &vt8500_gated_divisor_clk_ops;
 233                 break;
 234         default:
 235                 pr_err("%s: Invalid clock description in device tree\n",
 236                                                                 __func__);
 237                 kfree(dev_clk);
 238                 return;
 239         }
 240
 241         init.name = clk_name;
 242         init.flags = 0;
 243         parent_name = of_clk_get_parent_name(node, 0);
 244         init.parent_names = &parent_name;
 245         init.num_parents = 1;
 246
 247         dev_clk->hw.init = &init;
 248
 249         clk = clk_register(NULL, &dev_clk->hw);
 250         if (WARN_ON(IS_ERR(clk))) {
 251                 kfree(dev_clk);
 252                 return;
 253         }
 254         rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 255         clk_register_clkdev(clk, clk_name, NULL);
 256 }
 257
 258
 259 /* PLL clock related functions */
 260
 261 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
 262
 263 /* Helper macros for PLL_VT8500 */
 264 #define VT8500_PLL_MUL(x)       ((x & 0x1F) << 1)
 265 #define VT8500_PLL_DIV(x)       ((x & 0x100) ? 1 : 2)
 266
 267 #define VT8500_BITS_TO_FREQ(r, m, d)                                    \
 268                                 ((r / d) * m)
 269
 270 #define VT8500_BITS_TO_VAL(m, d)                                        \
 271                                 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
 272
 273 /* Helper macros for PLL_WM8650 */
 274 #define WM8650_PLL_MUL(x)       (x & 0x3FF)
 275 #define WM8650_PLL_DIV(x)       (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
 276
 277 #define WM8650_BITS_TO_FREQ(r, m, d1, d2)                               \
 278                                 (r * m / (d1 * (1 << d2)))
 279
 280 #define WM8650_BITS_TO_VAL(m, d1, d2)                                   \
 281                                 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
 282
 283
 284 static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 285                                 u32 *multiplier, u32 *prediv)
 286 {
 287         unsigned long tclk;
 288
 289         /* sanity check */
 290         if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
 291                 pr_err("%s: requested rate out of range\n", __func__);
 292                 *multiplier = 0;
 293                 *prediv = 1;
 294                 return;
 295         }
 296         if (rate <= parent_rate * 31)
 297                 /* use the prediv to double the resolution */
 298                 *prediv = 2;
 299         else
 300                 *prediv = 1;
 301
 302         *multiplier = rate / (parent_rate / *prediv);
 303         tclk = (parent_rate / *prediv) * *multiplier;
 304
 305         if (tclk != rate)
 306                 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
 307                                                                 rate, tclk);
 308 }
 309
 310 static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 311                                 u32 *multiplier, u32 *divisor1, u32 *divisor2)
 312 {
 313         u32 mul, div1, div2;
 314         u32 best_mul, best_div1, best_div2;
 315         unsigned long tclk, rate_err, best_err;
 316
 317         best_err = (unsigned long)-1;
 318
 319         /* Find the closest match (lower or equal to requested) */
 320         for (div1 = 5; div1 >= 3; div1--)
 321                 for (div2 = 3; div2 >= 0; div2--)
 322                         for (mul = 3; mul <= 1023; mul++) {
 323                                 tclk = parent_rate * mul / (div1 * (1 << div2));
 324                                 if (tclk > rate)
 325                                         continue;
 326                                 /* error will always be +ve */
 327                                 rate_err = rate - tclk;
 328                                 if (rate_err == 0) {
 329                                         *multiplier = mul;
 330                                         *divisor1 = div1;
 331                                         *divisor2 = div2;
 332                                         return;
 333                                 }
 334
 335                                 if (rate_err < best_err) {
 336                                         best_err = rate_err;
 337                                         best_mul = mul;
 338                                         best_div1 = div1;
 339                                         best_div2 = div2;
 340                                 }
 341                         }
 342
 343         /* if we got here, it wasn't an exact match */
 344         pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
 345                                                         rate - best_err);
 346         *multiplier = mul;
 347         *divisor1 = div1;
 348         *divisor2 = div2;
 349 }
 350
 351 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 352                                 unsigned long parent_rate)
 353 {
 354         struct clk_pll *pll = to_clk_pll(hw);
 355         u32 mul, div1, div2;
 356         u32 pll_val;
 357         unsigned long flags = 0;
 358
 359         /* sanity check */
 360
 361         switch (pll->type) {
 362         case PLL_TYPE_VT8500:
 363                 vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
 364                 pll_val = VT8500_BITS_TO_VAL(mul, div1);
 365                 break;
 366         case PLL_TYPE_WM8650:
 367                 wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
 368                 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
 369                 break;
 370         default:
 371                 pr_err("%s: invalid pll type\n", __func__);
 372                 return 0;
 373         }
 374
 375         spin_lock_irqsave(pll->lock, flags);
 376
 377         vt8500_pmc_wait_busy();
 378         writel(pll_val, pll->reg);
 379         vt8500_pmc_wait_busy();
 380
 381         spin_unlock_irqrestore(pll->lock, flags);
 382
 383         return 0;
 384 }
 385
 386 static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 387                                 unsigned long *prate)
 388 {
 389         struct clk_pll *pll = to_clk_pll(hw);
 390         u32 mul, div1, div2;
 391         long round_rate;
 392
 393         switch (pll->type) {
 394         case PLL_TYPE_VT8500:
 395                 vt8500_find_pll_bits(rate, *prate, &mul, &div1);
 396                 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
 397                 break;
 398         case PLL_TYPE_WM8650:
 399                 wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
 400                 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
 401                 break;
 402         default:
 403                 round_rate = 0;
 404         }
 405
 406         return round_rate;
 407 }
 408
 409 static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
 410                                 unsigned long parent_rate)
 411 {
 412         struct clk_pll *pll = to_clk_pll(hw);
 413         u32 pll_val = readl(pll->reg);
 414         unsigned long pll_freq;
 415
 416         switch (pll->type) {
 417         case PLL_TYPE_VT8500:
 418                 pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
 419                 pll_freq /= VT8500_PLL_DIV(pll_val);
 420                 break;
 421         case PLL_TYPE_WM8650:
 422                 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
 423                 pll_freq /= WM8650_PLL_DIV(pll_val);
 424                 break;
 425         default:
 426                 pll_freq = 0;
 427         }
 428
 429         return pll_freq;
 430 }
 431
 432 const struct clk_ops vtwm_pll_ops = {
 433         .round_rate = vtwm_pll_round_rate,
 434         .set_rate = vtwm_pll_set_rate,
 435         .recalc_rate = vtwm_pll_recalc_rate,
 436 };
 437
 438 static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
 439 {
 440         u32 reg;
 441         struct clk *clk;
 442         struct clk_pll *pll_clk;
 443         const char *clk_name = node->name;
 444         const char *parent_name;
 445         struct clk_init_data init;
 446         int rc;
 447
 448         rc = of_property_read_u32(node, "reg", &reg);
 449         if (WARN_ON(rc))
 450                 return;
 451
 452         pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
 453         if (WARN_ON(!pll_clk))
 454                 return;
 455
 456         pll_clk->reg = pmc_base + reg;
 457         pll_clk->lock = &_lock;
 458         pll_clk->type = pll_type;
 459
 460         of_property_read_string(node, "clock-output-names", &clk_name);
 461
 462         init.name = clk_name;
 463         init.ops = &vtwm_pll_ops;
 464         init.flags = 0;
 465         parent_name = of_clk_get_parent_name(node, 0);
 466         init.parent_names = &parent_name;
 467         init.num_parents = 1;
 468
 469         pll_clk->hw.init = &init;
 470
 471         clk = clk_register(NULL, &pll_clk->hw);
 472         if (WARN_ON(IS_ERR(clk))) {
 473                 kfree(pll_clk);
 474                 return;
 475         }
 476         rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 477         clk_register_clkdev(clk, clk_name, NULL);
 478 }
 479
 480
 481 /* Wrappers for initialization functions */
 482
 483 static void __init vt8500_pll_init(struct device_node *node)
 484 {
 485         vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
 486 }
 487
 488 static void __init wm8650_pll_init(struct device_node *node)
 489 {
 490         vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
 491 }
 492
 493 static const __initconst struct of_device_id clk_match[] = {
 494         { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
 495         { .compatible = "via,vt8500-pll-clock", .data = vt8500_pll_init, },
 496         { .compatible = "wm,wm8650-pll-clock", .data = wm8650_pll_init, },
 497         { .compatible = "via,vt8500-device-clock",
 498                                         .data = vtwm_device_clk_init, },
 499         { /* sentinel */ }
 500 };
 501
 502 void __init vtwm_clk_init(void __iomem *base)
 503 {
 504         if (!base)
 505                 return;
 506
 507         pmc_base = base;
 508
 509         of_clk_init(clk_match);
 510 }