2 * Intel GTT (Graphics Translation Table) routines
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
15 * /fairy-tale-mode off
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
26 #include "intel-agp.h"
27 #include <drm/intel-gtt.h>
30 * If we have Intel graphics, we're not going to have anything other than
31 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
32 * on the Intel IOMMU support (CONFIG_DMAR).
33 * Only newer chipsets need to bother with this, of course.
36 #define USE_PCI_DMA_API 1
38 #define USE_PCI_DMA_API 0
41 struct intel_gtt_driver {
43 unsigned int is_g33 : 1;
44 unsigned int is_pineview : 1;
45 unsigned int is_ironlake : 1;
46 unsigned int has_pgtbl_enable : 1;
47 unsigned int dma_mask_size : 8;
48 /* Chipset specific GTT setup */
50 /* This should undo anything done in ->setup() save the unmapping
51 * of the mmio register file, that's done in the generic code. */
52 void (*cleanup)(void);
53 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
54 /* Flags is a more or less chipset specific opaque value.
55 * For chipsets that need to support old ums (non-gem) code, this
56 * needs to be identical to the various supported agp memory types! */
57 bool (*check_flags)(unsigned int flags);
58 void (*chipset_flush)(void);
61 static struct _intel_private {
62 struct intel_gtt base;
63 const struct intel_gtt_driver *driver;
64 struct pci_dev *pcidev; /* device one */
65 struct pci_dev *bridge_dev;
66 u8 __iomem *registers;
67 phys_addr_t gtt_bus_addr;
68 phys_addr_t gma_bus_addr;
70 u32 __iomem *gtt; /* I915G */
71 int num_dcache_entries;
73 void __iomem *i9xx_flush_page;
74 void *i8xx_flush_page;
77 struct page *i8xx_page;
78 struct resource ifp_resource;
80 struct page *scratch_page;
81 dma_addr_t scratch_page_dma;
84 #define INTEL_GTT_GEN intel_private.driver->gen
85 #define IS_G33 intel_private.driver->is_g33
86 #define IS_PINEVIEW intel_private.driver->is_pineview
87 #define IS_IRONLAKE intel_private.driver->is_ironlake
88 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
90 int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
91 struct scatterlist **sg_list, int *num_sg)
94 struct scatterlist *sg;
98 return 0; /* already mapped (for e.g. resume */
100 DBG("try mapping %lu pages\n", (unsigned long)num_entries);
102 if (sg_alloc_table(&st, num_entries, GFP_KERNEL))
105 *sg_list = sg = st.sgl;
107 for (i = 0 ; i < num_entries; i++, sg = sg_next(sg))
108 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
110 *num_sg = pci_map_sg(intel_private.pcidev, *sg_list,
111 num_entries, PCI_DMA_BIDIRECTIONAL);
112 if (unlikely(!*num_sg))
121 EXPORT_SYMBOL(intel_gtt_map_memory);
123 void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
126 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
128 pci_unmap_sg(intel_private.pcidev, sg_list,
129 num_sg, PCI_DMA_BIDIRECTIONAL);
132 st.orig_nents = st.nents = num_sg;
136 EXPORT_SYMBOL(intel_gtt_unmap_memory);
138 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
143 /* Exists to support ARGB cursors */
144 static struct page *i8xx_alloc_pages(void)
148 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
152 if (set_pages_uc(page, 4) < 0) {
153 set_pages_wb(page, 4);
154 __free_pages(page, 2);
158 atomic_inc(&agp_bridge->current_memory_agp);
162 static void i8xx_destroy_pages(struct page *page)
167 set_pages_wb(page, 4);
169 __free_pages(page, 2);
170 atomic_dec(&agp_bridge->current_memory_agp);
173 #define I810_GTT_ORDER 4
174 static int i810_setup(void)
179 /* i81x does not preallocate the gtt. It's always 64kb in size. */
180 gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
181 if (gtt_table == NULL)
183 intel_private.i81x_gtt_table = gtt_table;
185 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr);
186 reg_addr &= 0xfff80000;
188 intel_private.registers = ioremap(reg_addr, KB(64));
189 if (!intel_private.registers)
192 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
193 intel_private.registers+I810_PGETBL_CTL);
195 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
197 if ((readl(intel_private.registers+I810_DRAM_CTL)
198 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
199 dev_info(&intel_private.pcidev->dev,
200 "detected 4MB dedicated video ram\n");
201 intel_private.num_dcache_entries = 1024;
207 static void i810_cleanup(void)
209 writel(0, intel_private.registers+I810_PGETBL_CTL);
210 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
213 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
218 if ((pg_start + mem->page_count)
219 > intel_private.num_dcache_entries)
222 if (!mem->is_flushed)
223 global_cache_flush();
225 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
226 dma_addr_t addr = i << PAGE_SHIFT;
227 intel_private.driver->write_entry(addr,
230 readl(intel_private.gtt+i-1);
236 * The i810/i830 requires a physical address to program its mouse
237 * pointer into hardware.
238 * However the Xserver still writes to it through the agp aperture.
240 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
242 struct agp_memory *new;
246 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
249 /* kludge to get 4 physical pages for ARGB cursor */
250 page = i8xx_alloc_pages();
259 new = agp_create_memory(pg_count);
263 new->pages[0] = page;
265 /* kludge to get 4 physical pages for ARGB cursor */
266 new->pages[1] = new->pages[0] + 1;
267 new->pages[2] = new->pages[1] + 1;
268 new->pages[3] = new->pages[2] + 1;
270 new->page_count = pg_count;
271 new->num_scratch_pages = pg_count;
272 new->type = AGP_PHYS_MEMORY;
273 new->physical = page_to_phys(new->pages[0]);
277 static void intel_i810_free_by_type(struct agp_memory *curr)
279 agp_free_key(curr->key);
280 if (curr->type == AGP_PHYS_MEMORY) {
281 if (curr->page_count == 4)
282 i8xx_destroy_pages(curr->pages[0]);
284 agp_bridge->driver->agp_destroy_page(curr->pages[0],
285 AGP_PAGE_DESTROY_UNMAP);
286 agp_bridge->driver->agp_destroy_page(curr->pages[0],
287 AGP_PAGE_DESTROY_FREE);
289 agp_free_page_array(curr);
294 static int intel_gtt_setup_scratch_page(void)
299 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
303 set_pages_uc(page, 1);
305 if (intel_private.base.needs_dmar) {
306 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
307 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
308 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
311 intel_private.scratch_page_dma = dma_addr;
313 intel_private.scratch_page_dma = page_to_phys(page);
315 intel_private.scratch_page = page;
320 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
323 u32 pte_flags = I810_PTE_VALID;
326 case AGP_DCACHE_MEMORY:
327 pte_flags |= I810_PTE_LOCAL;
329 case AGP_USER_CACHED_MEMORY:
330 pte_flags |= I830_PTE_SYSTEM_CACHED;
334 writel(addr | pte_flags, intel_private.gtt + entry);
337 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
345 static unsigned int intel_gtt_stolen_size(void)
350 static const int ddt[4] = { 0, 16, 32, 64 };
351 unsigned int stolen_size = 0;
353 if (INTEL_GTT_GEN == 1)
354 return 0; /* no stolen mem on i81x */
356 pci_read_config_word(intel_private.bridge_dev,
357 I830_GMCH_CTRL, &gmch_ctrl);
359 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
360 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
361 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
362 case I830_GMCH_GMS_STOLEN_512:
363 stolen_size = KB(512);
365 case I830_GMCH_GMS_STOLEN_1024:
368 case I830_GMCH_GMS_STOLEN_8192:
371 case I830_GMCH_GMS_LOCAL:
372 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
373 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
374 MB(ddt[I830_RDRAM_DDT(rdct)]);
381 } else if (INTEL_GTT_GEN == 6) {
383 * SandyBridge has new memory control reg at 0x50.w
386 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
387 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
388 case SNB_GMCH_GMS_STOLEN_32M:
389 stolen_size = MB(32);
391 case SNB_GMCH_GMS_STOLEN_64M:
392 stolen_size = MB(64);
394 case SNB_GMCH_GMS_STOLEN_96M:
395 stolen_size = MB(96);
397 case SNB_GMCH_GMS_STOLEN_128M:
398 stolen_size = MB(128);
400 case SNB_GMCH_GMS_STOLEN_160M:
401 stolen_size = MB(160);
403 case SNB_GMCH_GMS_STOLEN_192M:
404 stolen_size = MB(192);
406 case SNB_GMCH_GMS_STOLEN_224M:
407 stolen_size = MB(224);
409 case SNB_GMCH_GMS_STOLEN_256M:
410 stolen_size = MB(256);
412 case SNB_GMCH_GMS_STOLEN_288M:
413 stolen_size = MB(288);
415 case SNB_GMCH_GMS_STOLEN_320M:
416 stolen_size = MB(320);
418 case SNB_GMCH_GMS_STOLEN_352M:
419 stolen_size = MB(352);
421 case SNB_GMCH_GMS_STOLEN_384M:
422 stolen_size = MB(384);
424 case SNB_GMCH_GMS_STOLEN_416M:
425 stolen_size = MB(416);
427 case SNB_GMCH_GMS_STOLEN_448M:
428 stolen_size = MB(448);
430 case SNB_GMCH_GMS_STOLEN_480M:
431 stolen_size = MB(480);
433 case SNB_GMCH_GMS_STOLEN_512M:
434 stolen_size = MB(512);
438 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
439 case I855_GMCH_GMS_STOLEN_1M:
442 case I855_GMCH_GMS_STOLEN_4M:
445 case I855_GMCH_GMS_STOLEN_8M:
448 case I855_GMCH_GMS_STOLEN_16M:
449 stolen_size = MB(16);
451 case I855_GMCH_GMS_STOLEN_32M:
452 stolen_size = MB(32);
454 case I915_GMCH_GMS_STOLEN_48M:
455 stolen_size = MB(48);
457 case I915_GMCH_GMS_STOLEN_64M:
458 stolen_size = MB(64);
460 case G33_GMCH_GMS_STOLEN_128M:
461 stolen_size = MB(128);
463 case G33_GMCH_GMS_STOLEN_256M:
464 stolen_size = MB(256);
466 case INTEL_GMCH_GMS_STOLEN_96M:
467 stolen_size = MB(96);
469 case INTEL_GMCH_GMS_STOLEN_160M:
470 stolen_size = MB(160);
472 case INTEL_GMCH_GMS_STOLEN_224M:
473 stolen_size = MB(224);
475 case INTEL_GMCH_GMS_STOLEN_352M:
476 stolen_size = MB(352);
484 if (stolen_size > 0) {
485 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
486 stolen_size / KB(1), local ? "local" : "stolen");
488 dev_info(&intel_private.bridge_dev->dev,
489 "no pre-allocated video memory detected\n");
496 static void i965_adjust_pgetbl_size(unsigned int size_flag)
498 u32 pgetbl_ctl, pgetbl_ctl2;
500 /* ensure that ppgtt is disabled */
501 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
502 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
503 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
505 /* write the new ggtt size */
506 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
507 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
508 pgetbl_ctl |= size_flag;
509 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
512 static unsigned int i965_gtt_total_entries(void)
518 pci_read_config_word(intel_private.bridge_dev,
519 I830_GMCH_CTRL, &gmch_ctl);
521 if (INTEL_GTT_GEN == 5) {
522 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
523 case G4x_GMCH_SIZE_1M:
524 case G4x_GMCH_SIZE_VT_1M:
525 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
527 case G4x_GMCH_SIZE_VT_1_5M:
528 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
530 case G4x_GMCH_SIZE_2M:
531 case G4x_GMCH_SIZE_VT_2M:
532 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
537 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
539 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
540 case I965_PGETBL_SIZE_128KB:
543 case I965_PGETBL_SIZE_256KB:
546 case I965_PGETBL_SIZE_512KB:
549 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
550 case I965_PGETBL_SIZE_1MB:
553 case I965_PGETBL_SIZE_2MB:
556 case I965_PGETBL_SIZE_1_5MB:
557 size = KB(1024 + 512);
560 dev_info(&intel_private.pcidev->dev,
561 "unknown page table size, assuming 512KB\n");
568 static unsigned int intel_gtt_total_entries(void)
572 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
573 return i965_gtt_total_entries();
574 else if (INTEL_GTT_GEN == 6) {
577 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
578 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
580 case SNB_GTT_SIZE_0M:
581 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
584 case SNB_GTT_SIZE_1M:
587 case SNB_GTT_SIZE_2M:
593 /* On previous hardware, the GTT size was just what was
594 * required to map the aperture.
596 return intel_private.base.gtt_mappable_entries;
600 static unsigned int intel_gtt_mappable_entries(void)
602 unsigned int aperture_size;
604 if (INTEL_GTT_GEN == 1) {
607 pci_read_config_dword(intel_private.bridge_dev,
608 I810_SMRAM_MISCC, &smram_miscc);
610 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
611 == I810_GFX_MEM_WIN_32M)
612 aperture_size = MB(32);
614 aperture_size = MB(64);
615 } else if (INTEL_GTT_GEN == 2) {
618 pci_read_config_word(intel_private.bridge_dev,
619 I830_GMCH_CTRL, &gmch_ctrl);
621 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
622 aperture_size = MB(64);
624 aperture_size = MB(128);
626 /* 9xx supports large sizes, just look at the length */
627 aperture_size = pci_resource_len(intel_private.pcidev, 2);
630 return aperture_size >> PAGE_SHIFT;
633 static void intel_gtt_teardown_scratch_page(void)
635 set_pages_wb(intel_private.scratch_page, 1);
636 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
637 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
638 put_page(intel_private.scratch_page);
639 __free_page(intel_private.scratch_page);
642 static void intel_gtt_cleanup(void)
644 intel_private.driver->cleanup();
646 iounmap(intel_private.gtt);
647 iounmap(intel_private.registers);
649 intel_gtt_teardown_scratch_page();
652 static int intel_gtt_init(void)
657 ret = intel_private.driver->setup();
661 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
662 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
664 /* save the PGETBL reg for resume */
665 intel_private.PGETBL_save =
666 readl(intel_private.registers+I810_PGETBL_CTL)
667 & ~I810_PGETBL_ENABLED;
668 /* we only ever restore the register when enabling the PGTBL... */
670 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
672 dev_info(&intel_private.bridge_dev->dev,
673 "detected gtt size: %dK total, %dK mappable\n",
674 intel_private.base.gtt_total_entries * 4,
675 intel_private.base.gtt_mappable_entries * 4);
677 gtt_map_size = intel_private.base.gtt_total_entries * 4;
679 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
681 if (!intel_private.gtt) {
682 intel_private.driver->cleanup();
683 iounmap(intel_private.registers);
687 global_cache_flush(); /* FIXME: ? */
689 intel_private.base.stolen_size = intel_gtt_stolen_size();
691 ret = intel_gtt_setup_scratch_page();
697 intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
702 static int intel_fake_agp_fetch_size(void)
704 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
705 unsigned int aper_size;
708 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
711 for (i = 0; i < num_sizes; i++) {
712 if (aper_size == intel_fake_agp_sizes[i].size) {
713 agp_bridge->current_size =
714 (void *) (intel_fake_agp_sizes + i);
722 static void i830_cleanup(void)
724 if (intel_private.i8xx_flush_page) {
725 kunmap(intel_private.i8xx_flush_page);
726 intel_private.i8xx_flush_page = NULL;
729 __free_page(intel_private.i8xx_page);
730 intel_private.i8xx_page = NULL;
733 static void intel_i830_setup_flush(void)
735 /* return if we've already set the flush mechanism up */
736 if (intel_private.i8xx_page)
739 intel_private.i8xx_page = alloc_page(GFP_KERNEL);
740 if (!intel_private.i8xx_page)
743 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
744 if (!intel_private.i8xx_flush_page)
748 /* The chipset_flush interface needs to get data that has already been
749 * flushed out of the CPU all the way out to main memory, because the GPU
750 * doesn't snoop those buffers.
752 * The 8xx series doesn't have the same lovely interface for flushing the
753 * chipset write buffers that the later chips do. According to the 865
754 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
755 * that buffer out, we just fill 1KB and clflush it out, on the assumption
756 * that it'll push whatever was in there out. It appears to work.
758 static void i830_chipset_flush(void)
760 unsigned int *pg = intel_private.i8xx_flush_page;
765 clflush_cache_range(pg, 1024);
766 else if (wbinvd_on_all_cpus() != 0)
767 printk(KERN_ERR "Timed out waiting for cache flush.\n");
770 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
773 u32 pte_flags = I810_PTE_VALID;
775 if (flags == AGP_USER_CACHED_MEMORY)
776 pte_flags |= I830_PTE_SYSTEM_CACHED;
778 writel(addr | pte_flags, intel_private.gtt + entry);
781 static bool intel_enable_gtt(void)
786 if (INTEL_GTT_GEN <= 2)
787 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
790 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
793 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
795 if (INTEL_GTT_GEN >= 6)
798 if (INTEL_GTT_GEN == 2) {
801 pci_read_config_word(intel_private.bridge_dev,
802 I830_GMCH_CTRL, &gmch_ctrl);
803 gmch_ctrl |= I830_GMCH_ENABLED;
804 pci_write_config_word(intel_private.bridge_dev,
805 I830_GMCH_CTRL, gmch_ctrl);
807 pci_read_config_word(intel_private.bridge_dev,
808 I830_GMCH_CTRL, &gmch_ctrl);
809 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
810 dev_err(&intel_private.pcidev->dev,
811 "failed to enable the GTT: GMCH_CTRL=%x\n",
817 reg = intel_private.registers+I810_PGETBL_CTL;
818 writel(intel_private.PGETBL_save, reg);
819 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
820 dev_err(&intel_private.pcidev->dev,
821 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
822 readl(reg), intel_private.PGETBL_save);
829 static int i830_setup(void)
833 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr);
834 reg_addr &= 0xfff80000;
836 intel_private.registers = ioremap(reg_addr, KB(64));
837 if (!intel_private.registers)
840 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
842 intel_i830_setup_flush();
847 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
849 agp_bridge->gatt_table_real = NULL;
850 agp_bridge->gatt_table = NULL;
851 agp_bridge->gatt_bus_addr = 0;
856 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
861 static int intel_fake_agp_configure(void)
865 if (!intel_enable_gtt())
868 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
870 for (i = 0; i < intel_private.base.gtt_total_entries; i++) {
871 intel_private.driver->write_entry(intel_private.scratch_page_dma,
874 readl(intel_private.gtt+i-1); /* PCI Posting. */
876 global_cache_flush();
881 static bool i830_check_flags(unsigned int flags)
885 case AGP_PHYS_MEMORY:
886 case AGP_USER_CACHED_MEMORY:
887 case AGP_USER_MEMORY:
894 void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
896 unsigned int pg_start,
899 struct scatterlist *sg;
905 /* sg may merge pages, but we have to separate
906 * per-page addr for GTT */
907 for_each_sg(sg_list, sg, sg_len, i) {
908 len = sg_dma_len(sg) >> PAGE_SHIFT;
909 for (m = 0; m < len; m++) {
910 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
911 intel_private.driver->write_entry(addr,
916 readl(intel_private.gtt+j-1);
918 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
920 void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
921 struct page **pages, unsigned int flags)
925 for (i = 0, j = first_entry; i < num_entries; i++, j++) {
926 dma_addr_t addr = page_to_phys(pages[i]);
927 intel_private.driver->write_entry(addr,
930 readl(intel_private.gtt+j-1);
932 EXPORT_SYMBOL(intel_gtt_insert_pages);
934 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
935 off_t pg_start, int type)
939 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
940 return i810_insert_dcache_entries(mem, pg_start, type);
942 if (mem->page_count == 0)
945 if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
948 if (type != mem->type)
951 if (!intel_private.driver->check_flags(type))
954 if (!mem->is_flushed)
955 global_cache_flush();
957 if (intel_private.base.needs_dmar) {
958 ret = intel_gtt_map_memory(mem->pages, mem->page_count,
959 &mem->sg_list, &mem->num_sg);
963 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
966 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
972 mem->is_flushed = true;
976 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
980 for (i = first_entry; i < (first_entry + num_entries); i++) {
981 intel_private.driver->write_entry(intel_private.scratch_page_dma,
984 readl(intel_private.gtt+i-1);
986 EXPORT_SYMBOL(intel_gtt_clear_range);
988 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
989 off_t pg_start, int type)
991 if (mem->page_count == 0)
994 if (intel_private.base.needs_dmar) {
995 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
1000 intel_gtt_clear_range(pg_start, mem->page_count);
1005 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1008 struct agp_memory *new;
1010 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
1011 if (pg_count != intel_private.num_dcache_entries)
1014 new = agp_create_memory(1);
1018 new->type = AGP_DCACHE_MEMORY;
1019 new->page_count = pg_count;
1020 new->num_scratch_pages = 0;
1021 agp_free_page_array(new);
1024 if (type == AGP_PHYS_MEMORY)
1025 return alloc_agpphysmem_i8xx(pg_count, type);
1026 /* always return NULL for other allocation types for now */
1030 static int intel_alloc_chipset_flush_resource(void)
1033 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1034 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1035 pcibios_align_resource, intel_private.bridge_dev);
1040 static void intel_i915_setup_chipset_flush(void)
1045 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1046 if (!(temp & 0x1)) {
1047 intel_alloc_chipset_flush_resource();
1048 intel_private.resource_valid = 1;
1049 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1053 intel_private.resource_valid = 1;
1054 intel_private.ifp_resource.start = temp;
1055 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1056 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1057 /* some BIOSes reserve this area in a pnp some don't */
1059 intel_private.resource_valid = 0;
1063 static void intel_i965_g33_setup_chipset_flush(void)
1065 u32 temp_hi, temp_lo;
1068 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1069 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1071 if (!(temp_lo & 0x1)) {
1073 intel_alloc_chipset_flush_resource();
1075 intel_private.resource_valid = 1;
1076 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1077 upper_32_bits(intel_private.ifp_resource.start));
1078 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1083 l64 = ((u64)temp_hi << 32) | temp_lo;
1085 intel_private.resource_valid = 1;
1086 intel_private.ifp_resource.start = l64;
1087 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1088 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1089 /* some BIOSes reserve this area in a pnp some don't */
1091 intel_private.resource_valid = 0;
1095 static void intel_i9xx_setup_flush(void)
1097 /* return if already configured */
1098 if (intel_private.ifp_resource.start)
1101 if (INTEL_GTT_GEN == 6)
1104 /* setup a resource for this object */
1105 intel_private.ifp_resource.name = "Intel Flush Page";
1106 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1108 /* Setup chipset flush for 915 */
1109 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1110 intel_i965_g33_setup_chipset_flush();
1112 intel_i915_setup_chipset_flush();
1115 if (intel_private.ifp_resource.start)
1116 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1117 if (!intel_private.i9xx_flush_page)
1118 dev_err(&intel_private.pcidev->dev,
1119 "can't ioremap flush page - no chipset flushing\n");
1122 static void i9xx_cleanup(void)
1124 if (intel_private.i9xx_flush_page)
1125 iounmap(intel_private.i9xx_flush_page);
1126 if (intel_private.resource_valid)
1127 release_resource(&intel_private.ifp_resource);
1128 intel_private.ifp_resource.start = 0;
1129 intel_private.resource_valid = 0;
1132 static void i9xx_chipset_flush(void)
1134 if (intel_private.i9xx_flush_page)
1135 writel(1, intel_private.i9xx_flush_page);
1138 static void i965_write_entry(dma_addr_t addr,
1144 pte_flags = I810_PTE_VALID;
1145 if (flags == AGP_USER_CACHED_MEMORY)
1146 pte_flags |= I830_PTE_SYSTEM_CACHED;
1148 /* Shift high bits down */
1149 addr |= (addr >> 28) & 0xf0;
1150 writel(addr | pte_flags, intel_private.gtt + entry);
1153 static bool gen6_check_flags(unsigned int flags)
1158 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1161 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1162 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1165 if (type_mask == AGP_USER_MEMORY)
1166 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1167 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1168 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1170 pte_flags |= GEN6_PTE_GFDT;
1171 } else { /* set 'normal'/'cached' to LLC by default */
1172 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1174 pte_flags |= GEN6_PTE_GFDT;
1177 /* gen6 has bit11-4 for physical addr bit39-32 */
1178 addr |= (addr >> 28) & 0xff0;
1179 writel(addr | pte_flags, intel_private.gtt + entry);
1182 static void gen6_cleanup(void)
1186 static int i9xx_setup(void)
1190 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr);
1192 reg_addr &= 0xfff80000;
1194 intel_private.registers = ioremap(reg_addr, 128 * 4096);
1195 if (!intel_private.registers)
1198 if (INTEL_GTT_GEN == 3) {
1201 pci_read_config_dword(intel_private.pcidev,
1202 I915_PTEADDR, >t_addr);
1203 intel_private.gtt_bus_addr = gtt_addr;
1207 switch (INTEL_GTT_GEN) {
1214 gtt_offset = KB(512);
1217 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1220 intel_i9xx_setup_flush();
1225 static const struct agp_bridge_driver intel_fake_agp_driver = {
1226 .owner = THIS_MODULE,
1227 .size_type = FIXED_APER_SIZE,
1228 .aperture_sizes = intel_fake_agp_sizes,
1229 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1230 .configure = intel_fake_agp_configure,
1231 .fetch_size = intel_fake_agp_fetch_size,
1232 .cleanup = intel_gtt_cleanup,
1233 .agp_enable = intel_fake_agp_enable,
1234 .cache_flush = global_cache_flush,
1235 .create_gatt_table = intel_fake_agp_create_gatt_table,
1236 .free_gatt_table = intel_fake_agp_free_gatt_table,
1237 .insert_memory = intel_fake_agp_insert_entries,
1238 .remove_memory = intel_fake_agp_remove_entries,
1239 .alloc_by_type = intel_fake_agp_alloc_by_type,
1240 .free_by_type = intel_i810_free_by_type,
1241 .agp_alloc_page = agp_generic_alloc_page,
1242 .agp_alloc_pages = agp_generic_alloc_pages,
1243 .agp_destroy_page = agp_generic_destroy_page,
1244 .agp_destroy_pages = agp_generic_destroy_pages,
1247 static const struct intel_gtt_driver i81x_gtt_driver = {
1249 .has_pgtbl_enable = 1,
1250 .dma_mask_size = 32,
1251 .setup = i810_setup,
1252 .cleanup = i810_cleanup,
1253 .check_flags = i830_check_flags,
1254 .write_entry = i810_write_entry,
1256 static const struct intel_gtt_driver i8xx_gtt_driver = {
1258 .has_pgtbl_enable = 1,
1259 .setup = i830_setup,
1260 .cleanup = i830_cleanup,
1261 .write_entry = i830_write_entry,
1262 .dma_mask_size = 32,
1263 .check_flags = i830_check_flags,
1264 .chipset_flush = i830_chipset_flush,
1266 static const struct intel_gtt_driver i915_gtt_driver = {
1268 .has_pgtbl_enable = 1,
1269 .setup = i9xx_setup,
1270 .cleanup = i9xx_cleanup,
1271 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1272 .write_entry = i830_write_entry,
1273 .dma_mask_size = 32,
1274 .check_flags = i830_check_flags,
1275 .chipset_flush = i9xx_chipset_flush,
1277 static const struct intel_gtt_driver g33_gtt_driver = {
1280 .setup = i9xx_setup,
1281 .cleanup = i9xx_cleanup,
1282 .write_entry = i965_write_entry,
1283 .dma_mask_size = 36,
1284 .check_flags = i830_check_flags,
1285 .chipset_flush = i9xx_chipset_flush,
1287 static const struct intel_gtt_driver pineview_gtt_driver = {
1289 .is_pineview = 1, .is_g33 = 1,
1290 .setup = i9xx_setup,
1291 .cleanup = i9xx_cleanup,
1292 .write_entry = i965_write_entry,
1293 .dma_mask_size = 36,
1294 .check_flags = i830_check_flags,
1295 .chipset_flush = i9xx_chipset_flush,
1297 static const struct intel_gtt_driver i965_gtt_driver = {
1299 .has_pgtbl_enable = 1,
1300 .setup = i9xx_setup,
1301 .cleanup = i9xx_cleanup,
1302 .write_entry = i965_write_entry,
1303 .dma_mask_size = 36,
1304 .check_flags = i830_check_flags,
1305 .chipset_flush = i9xx_chipset_flush,
1307 static const struct intel_gtt_driver g4x_gtt_driver = {
1309 .setup = i9xx_setup,
1310 .cleanup = i9xx_cleanup,
1311 .write_entry = i965_write_entry,
1312 .dma_mask_size = 36,
1313 .check_flags = i830_check_flags,
1314 .chipset_flush = i9xx_chipset_flush,
1316 static const struct intel_gtt_driver ironlake_gtt_driver = {
1319 .setup = i9xx_setup,
1320 .cleanup = i9xx_cleanup,
1321 .write_entry = i965_write_entry,
1322 .dma_mask_size = 36,
1323 .check_flags = i830_check_flags,
1324 .chipset_flush = i9xx_chipset_flush,
1326 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1328 .setup = i9xx_setup,
1329 .cleanup = gen6_cleanup,
1330 .write_entry = gen6_write_entry,
1331 .dma_mask_size = 40,
1332 .check_flags = gen6_check_flags,
1333 .chipset_flush = i9xx_chipset_flush,
1336 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1337 * driver and gmch_driver must be non-null, and find_gmch will determine
1338 * which one should be used if a gmch_chip_id is present.
1340 static const struct intel_gtt_driver_description {
1341 unsigned int gmch_chip_id;
1343 const struct intel_gtt_driver *gtt_driver;
1344 } intel_gtt_chipsets[] = {
1345 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1347 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1349 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1351 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1353 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1355 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1357 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1359 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1361 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1363 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1365 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1367 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1369 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1371 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1373 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1375 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1377 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1379 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1381 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1383 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1385 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1387 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1389 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1391 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1393 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1394 &pineview_gtt_driver },
1395 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1396 &pineview_gtt_driver },
1397 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1399 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1401 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1403 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1405 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1407 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1409 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1411 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1412 "HD Graphics", &ironlake_gtt_driver },
1413 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1414 "HD Graphics", &ironlake_gtt_driver },
1415 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1416 "Sandybridge", &sandybridge_gtt_driver },
1417 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1418 "Sandybridge", &sandybridge_gtt_driver },
1419 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1420 "Sandybridge", &sandybridge_gtt_driver },
1421 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1422 "Sandybridge", &sandybridge_gtt_driver },
1423 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1424 "Sandybridge", &sandybridge_gtt_driver },
1425 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1426 "Sandybridge", &sandybridge_gtt_driver },
1427 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1428 "Sandybridge", &sandybridge_gtt_driver },
1432 static int find_gmch(u16 device)
1434 struct pci_dev *gmch_device;
1436 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1437 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1438 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1439 device, gmch_device);
1445 intel_private.pcidev = gmch_device;
1449 int intel_gmch_probe(struct pci_dev *pdev,
1450 struct agp_bridge_data *bridge)
1453 intel_private.driver = NULL;
1455 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1456 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1457 intel_private.driver =
1458 intel_gtt_chipsets[i].gtt_driver;
1463 if (!intel_private.driver)
1466 bridge->driver = &intel_fake_agp_driver;
1467 bridge->dev_private_data = &intel_private;
1470 intel_private.bridge_dev = pci_dev_get(pdev);
1472 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1474 mask = intel_private.driver->dma_mask_size;
1475 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1476 dev_err(&intel_private.pcidev->dev,
1477 "set gfx device dma mask %d-bit failed!\n", mask);
1479 pci_set_consistent_dma_mask(intel_private.pcidev,
1480 DMA_BIT_MASK(mask));
1482 /*if (bridge->driver == &intel_810_driver)
1485 if (intel_gtt_init() != 0)
1490 EXPORT_SYMBOL(intel_gmch_probe);
1492 const struct intel_gtt *intel_gtt_get(void)
1494 return &intel_private.base;
1496 EXPORT_SYMBOL(intel_gtt_get);
1498 void intel_gtt_chipset_flush(void)
1500 if (intel_private.driver->chipset_flush)
1501 intel_private.driver->chipset_flush();
1503 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1505 void intel_gmch_remove(struct pci_dev *pdev)
1507 if (intel_private.pcidev)
1508 pci_dev_put(intel_private.pcidev);
1509 if (intel_private.bridge_dev)
1510 pci_dev_put(intel_private.bridge_dev);
1512 EXPORT_SYMBOL(intel_gmch_remove);
1514 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1515 MODULE_LICENSE("GPL and additional rights");