Pileus Git - ~andy/linux/blob - drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  14 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  17 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
  18 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
  19 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  20 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  21 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  22 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  23 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  24 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  25 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  26 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  27 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  28 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  29 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  30 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  31 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  32 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  33 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  34 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  35 #define PCI_DEVICE_ID_INTEL_IGD_HB          0x2A40
  36 #define PCI_DEVICE_ID_INTEL_IGD_IG          0x2A42
  37
  38 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  39                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
  40                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  41                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  42                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  43                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB || \
  44                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
  45
  46 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  47                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  48                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
  49
  50 extern int agp_memory_reserved;
  51
  52
  53 /* Intel 815 register */
  54 #define INTEL_815_APCONT        0x51
  55 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
  56
  57 /* Intel i820 registers */
  58 #define INTEL_I820_RDCR         0x51
  59 #define INTEL_I820_ERRSTS       0xc8
  60
  61 /* Intel i840 registers */
  62 #define INTEL_I840_MCHCFG       0x50
  63 #define INTEL_I840_ERRSTS       0xc8
  64
  65 /* Intel i850 registers */
  66 #define INTEL_I850_MCHCFG       0x50
  67 #define INTEL_I850_ERRSTS       0xc8
  68
  69 /* intel 915G registers */
  70 #define I915_GMADDR     0x18
  71 #define I915_MMADDR     0x10
  72 #define I915_PTEADDR    0x1C
  73 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
  74 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
  75 #define G33_GMCH_GMS_STOLEN_128M       (0x8 << 4)
  76 #define G33_GMCH_GMS_STOLEN_256M       (0x9 << 4)
  77 #define I915_IFPADDR    0x60
  78
  79 /* Intel 965G registers */
  80 #define I965_MSAC 0x62
  81 #define I965_IFPADDR    0x70
  82
  83 /* Intel 7505 registers */
  84 #define INTEL_I7505_APSIZE      0x74
  85 #define INTEL_I7505_NCAPID      0x60
  86 #define INTEL_I7505_NISTAT      0x6c
  87 #define INTEL_I7505_ATTBASE     0x78
  88 #define INTEL_I7505_ERRSTS      0x42
  89 #define INTEL_I7505_AGPCTRL     0x70
  90 #define INTEL_I7505_MCHCFG      0x50
  91
  92 static const struct aper_size_info_fixed intel_i810_sizes[] =
  93 {
  94         {64, 16384, 4},
  95         /* The 32M mode still requires a 64k gatt */
  96         {32, 8192, 4}
  97 };
  98
  99 #define AGP_DCACHE_MEMORY       1
 100 #define AGP_PHYS_MEMORY         2
 101 #define INTEL_AGP_CACHED_MEMORY 3
 102
 103 static struct gatt_mask intel_i810_masks[] =
 104 {
 105         {.mask = I810_PTE_VALID, .type = 0},
 106         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 107         {.mask = I810_PTE_VALID, .type = 0},
 108         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 109          .type = INTEL_AGP_CACHED_MEMORY}
 110 };
 111
 112 static struct _intel_private {
 113         struct pci_dev *pcidev; /* device one */
 114         u8 __iomem *registers;
 115         u32 __iomem *gtt;               /* I915G */
 116         int num_dcache_entries;
 117         /* gtt_entries is the number of gtt entries that are already mapped
 118          * to stolen memory.  Stolen memory is larger than the memory mapped
 119          * through gtt_entries, as it includes some reserved space for the BIOS
 120          * popup and for the GTT.
 121          */
 122         int gtt_entries;                        /* i830+ */
 123         union {
 124                 void __iomem *i9xx_flush_page;
 125                 void *i8xx_flush_page;
 126         };
 127         struct page *i8xx_page;
 128         struct resource ifp_resource;
 129 } intel_private;
 130
 131 static int intel_i810_fetch_size(void)
 132 {
 133         u32 smram_miscc;
 134         struct aper_size_info_fixed *values;
 135
 136         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 137         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 138
 139         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 140                 printk(KERN_WARNING PFX "i810 is disabled\n");
 141                 return 0;
 142         }
 143         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 144                 agp_bridge->previous_size =
 145                         agp_bridge->current_size = (void *) (values + 1);
 146                 agp_bridge->aperture_size_idx = 1;
 147                 return values[1].size;
 148         } else {
 149                 agp_bridge->previous_size =
 150                         agp_bridge->current_size = (void *) (values);
 151                 agp_bridge->aperture_size_idx = 0;
 152                 return values[0].size;
 153         }
 154
 155         return 0;
 156 }
 157
 158 static int intel_i810_configure(void)
 159 {
 160         struct aper_size_info_fixed *current_size;
 161         u32 temp;
 162         int i;
 163
 164         current_size = A_SIZE_FIX(agp_bridge->current_size);
 165
 166         if (!intel_private.registers) {
 167                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 168                 temp &= 0xfff80000;
 169
 170                 intel_private.registers = ioremap(temp, 128 * 4096);
 171                 if (!intel_private.registers) {
 172                         printk(KERN_ERR PFX "Unable to remap memory.\n");
 173                         return -ENOMEM;
 174                 }
 175         }
 176
 177         if ((readl(intel_private.registers+I810_DRAM_CTL)
 178                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 179                 /* This will need to be dynamically assigned */
 180                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
 181                 intel_private.num_dcache_entries = 1024;
 182         }
 183         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 184         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 185         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 186         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 187
 188         if (agp_bridge->driver->needs_scratch_page) {
 189                 for (i = 0; i < current_size->num_entries; i++) {
 190                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 191                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI posting. */
 192                 }
 193         }
 194         global_cache_flush();
 195         return 0;
 196 }
 197
 198 static void intel_i810_cleanup(void)
 199 {
 200         writel(0, intel_private.registers+I810_PGETBL_CTL);
 201         readl(intel_private.registers); /* PCI Posting. */
 202         iounmap(intel_private.registers);
 203 }
 204
 205 static void intel_i810_tlbflush(struct agp_memory *mem)
 206 {
 207         return;
 208 }
 209
 210 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 211 {
 212         return;
 213 }
 214
 215 /* Exists to support ARGB cursors */
 216 static void *i8xx_alloc_pages(void)
 217 {
 218         struct page * page;
 219
 220         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 221         if (page == NULL)
 222                 return NULL;
 223
 224         if (set_pages_uc(page, 4) < 0) {
 225                 set_pages_wb(page, 4);
 226                 __free_pages(page, 2);
 227                 return NULL;
 228         }
 229         get_page(page);
 230         atomic_inc(&agp_bridge->current_memory_agp);
 231         return page_address(page);
 232 }
 233
 234 static void i8xx_destroy_pages(void *addr)
 235 {
 236         struct page *page;
 237
 238         if (addr == NULL)
 239                 return;
 240
 241         page = virt_to_page(addr);
 242         set_pages_wb(page, 4);
 243         put_page(page);
 244         __free_pages(page, 2);
 245         atomic_dec(&agp_bridge->current_memory_agp);
 246 }
 247
 248 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 249                                         int type)
 250 {
 251         if (type < AGP_USER_TYPES)
 252                 return type;
 253         else if (type == AGP_USER_CACHED_MEMORY)
 254                 return INTEL_AGP_CACHED_MEMORY;
 255         else
 256                 return 0;
 257 }
 258
 259 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 260                                 int type)
 261 {
 262         int i, j, num_entries;
 263         void *temp;
 264         int ret = -EINVAL;
 265         int mask_type;
 266
 267         if (mem->page_count == 0)
 268                 goto out;
 269
 270         temp = agp_bridge->current_size;
 271         num_entries = A_SIZE_FIX(temp)->num_entries;
 272
 273         if ((pg_start + mem->page_count) > num_entries)
 274                 goto out_err;
 275
 276
 277         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 278                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 279                         ret = -EBUSY;
 280                         goto out_err;
 281                 }
 282         }
 283
 284         if (type != mem->type)
 285                 goto out_err;
 286
 287         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 288
 289         switch (mask_type) {
 290         case AGP_DCACHE_MEMORY:
 291                 if (!mem->is_flushed)
 292                         global_cache_flush();
 293                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 294                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 295                                intel_private.registers+I810_PTE_BASE+(i*4));
 296                 }
 297                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 298                 break;
 299         case AGP_PHYS_MEMORY:
 300         case AGP_NORMAL_MEMORY:
 301                 if (!mem->is_flushed)
 302                         global_cache_flush();
 303                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 304                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 305                                                                mem->memory[i],
 306                                                                mask_type),
 307                                intel_private.registers+I810_PTE_BASE+(j*4));
 308                 }
 309                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 310                 break;
 311         default:
 312                 goto out_err;
 313         }
 314
 315         agp_bridge->driver->tlb_flush(mem);
 316 out:
 317         ret = 0;
 318 out_err:
 319         mem->is_flushed = 1;
 320         return ret;
 321 }
 322
 323 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 324                                 int type)
 325 {
 326         int i;
 327
 328         if (mem->page_count == 0)
 329                 return 0;
 330
 331         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 332                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 333         }
 334         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 335
 336         agp_bridge->driver->tlb_flush(mem);
 337         return 0;
 338 }
 339
 340 /*
 341  * The i810/i830 requires a physical address to program its mouse
 342  * pointer into hardware.
 343  * However the Xserver still writes to it through the agp aperture.
 344  */
 345 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 346 {
 347         struct agp_memory *new;
 348         void *addr;
 349
 350         switch (pg_count) {
 351         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
 352                 break;
 353         case 4:
 354                 /* kludge to get 4 physical pages for ARGB cursor */
 355                 addr = i8xx_alloc_pages();
 356                 break;
 357         default:
 358                 return NULL;
 359         }
 360
 361         if (addr == NULL)
 362                 return NULL;
 363
 364         new = agp_create_memory(pg_count);
 365         if (new == NULL)
 366                 return NULL;
 367
 368         new->memory[0] = virt_to_gart(addr);
 369         if (pg_count == 4) {
 370                 /* kludge to get 4 physical pages for ARGB cursor */
 371                 new->memory[1] = new->memory[0] + PAGE_SIZE;
 372                 new->memory[2] = new->memory[1] + PAGE_SIZE;
 373                 new->memory[3] = new->memory[2] + PAGE_SIZE;
 374         }
 375         new->page_count = pg_count;
 376         new->num_scratch_pages = pg_count;
 377         new->type = AGP_PHYS_MEMORY;
 378         new->physical = new->memory[0];
 379         return new;
 380 }
 381
 382 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 383 {
 384         struct agp_memory *new;
 385
 386         if (type == AGP_DCACHE_MEMORY) {
 387                 if (pg_count != intel_private.num_dcache_entries)
 388                         return NULL;
 389
 390                 new = agp_create_memory(1);
 391                 if (new == NULL)
 392                         return NULL;
 393
 394                 new->type = AGP_DCACHE_MEMORY;
 395                 new->page_count = pg_count;
 396                 new->num_scratch_pages = 0;
 397                 agp_free_page_array(new);
 398                 return new;
 399         }
 400         if (type == AGP_PHYS_MEMORY)
 401                 return alloc_agpphysmem_i8xx(pg_count, type);
 402         return NULL;
 403 }
 404
 405 static void intel_i810_free_by_type(struct agp_memory *curr)
 406 {
 407         agp_free_key(curr->key);
 408         if (curr->type == AGP_PHYS_MEMORY) {
 409                 if (curr->page_count == 4)
 410                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
 411                 else {
 412                         agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
 413                                                              AGP_PAGE_DESTROY_UNMAP);
 414                         agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
 415                                                              AGP_PAGE_DESTROY_FREE);
 416                 }
 417                 agp_free_page_array(curr);
 418         }
 419         kfree(curr);
 420 }
 421
 422 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 423         unsigned long addr, int type)
 424 {
 425         /* Type checking must be done elsewhere */
 426         return addr | bridge->driver->masks[type].mask;
 427 }
 428
 429 static struct aper_size_info_fixed intel_i830_sizes[] =
 430 {
 431         {128, 32768, 5},
 432         /* The 64M mode still requires a 128k gatt */
 433         {64, 16384, 5},
 434         {256, 65536, 6},
 435         {512, 131072, 7},
 436 };
 437
 438 static void intel_i830_init_gtt_entries(void)
 439 {
 440         u16 gmch_ctrl;
 441         int gtt_entries;
 442         u8 rdct;
 443         int local = 0;
 444         static const int ddt[4] = { 0, 16, 32, 64 };
 445         int size; /* reserved space (in kb) at the top of stolen memory */
 446
 447         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 448
 449         if (IS_I965) {
 450                 u32 pgetbl_ctl;
 451                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 452
 453                 /* The 965 has a field telling us the size of the GTT,
 454                  * which may be larger than what is necessary to map the
 455                  * aperture.
 456                  */
 457                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 458                 case I965_PGETBL_SIZE_128KB:
 459                         size = 128;
 460                         break;
 461                 case I965_PGETBL_SIZE_256KB:
 462                         size = 256;
 463                         break;
 464                 case I965_PGETBL_SIZE_512KB:
 465                         size = 512;
 466                         break;
 467                 case I965_PGETBL_SIZE_1MB:
 468                         size = 1024;
 469                         break;
 470                 case I965_PGETBL_SIZE_2MB:
 471                         size = 2048;
 472                         break;
 473                 case I965_PGETBL_SIZE_1_5MB:
 474                         size = 1024 + 512;
 475                         break;
 476                 default:
 477                         printk(KERN_INFO PFX "Unknown page table size, "
 478                                "assuming 512KB\n");
 479                         size = 512;
 480                 }
 481                 size += 4; /* add in BIOS popup space */
 482         } else if (IS_G33) {
 483         /* G33's GTT size defined in gmch_ctrl */
 484                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 485                 case G33_PGETBL_SIZE_1M:
 486                         size = 1024;
 487                         break;
 488                 case G33_PGETBL_SIZE_2M:
 489                         size = 2048;
 490                         break;
 491                 default:
 492                         printk(KERN_INFO PFX "Unknown page table size 0x%x, "
 493                                 "assuming 512KB\n",
 494                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 495                         size = 512;
 496                 }
 497                 size += 4;
 498         } else {
 499                 /* On previous hardware, the GTT size was just what was
 500                  * required to map the aperture.
 501                  */
 502                 size = agp_bridge->driver->fetch_size() + 4;
 503         }
 504
 505         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 506             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 507                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 508                 case I830_GMCH_GMS_STOLEN_512:
 509                         gtt_entries = KB(512) - KB(size);
 510                         break;
 511                 case I830_GMCH_GMS_STOLEN_1024:
 512                         gtt_entries = MB(1) - KB(size);
 513                         break;
 514                 case I830_GMCH_GMS_STOLEN_8192:
 515                         gtt_entries = MB(8) - KB(size);
 516                         break;
 517                 case I830_GMCH_GMS_LOCAL:
 518                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 519                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 520                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 521                         local = 1;
 522                         break;
 523                 default:
 524                         gtt_entries = 0;
 525                         break;
 526                 }
 527         } else {
 528                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 529                 case I855_GMCH_GMS_STOLEN_1M:
 530                         gtt_entries = MB(1) - KB(size);
 531                         break;
 532                 case I855_GMCH_GMS_STOLEN_4M:
 533                         gtt_entries = MB(4) - KB(size);
 534                         break;
 535                 case I855_GMCH_GMS_STOLEN_8M:
 536                         gtt_entries = MB(8) - KB(size);
 537                         break;
 538                 case I855_GMCH_GMS_STOLEN_16M:
 539                         gtt_entries = MB(16) - KB(size);
 540                         break;
 541                 case I855_GMCH_GMS_STOLEN_32M:
 542                         gtt_entries = MB(32) - KB(size);
 543                         break;
 544                 case I915_GMCH_GMS_STOLEN_48M:
 545                         /* Check it's really I915G */
 546                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
 547                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 548                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 549                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 550                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
 551                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
 552                             IS_I965 || IS_G33)
 553                                 gtt_entries = MB(48) - KB(size);
 554                         else
 555                                 gtt_entries = 0;
 556                         break;
 557                 case I915_GMCH_GMS_STOLEN_64M:
 558                         /* Check it's really I915G */
 559                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
 560                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 561                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 562                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 563                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
 564                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
 565                             IS_I965 || IS_G33)
 566                                 gtt_entries = MB(64) - KB(size);
 567                         else
 568                                 gtt_entries = 0;
 569                         break;
 570                 case G33_GMCH_GMS_STOLEN_128M:
 571                         if (IS_G33)
 572                                 gtt_entries = MB(128) - KB(size);
 573                         else
 574                                 gtt_entries = 0;
 575                         break;
 576                 case G33_GMCH_GMS_STOLEN_256M:
 577                         if (IS_G33)
 578                                 gtt_entries = MB(256) - KB(size);
 579                         else
 580                                 gtt_entries = 0;
 581                         break;
 582                 default:
 583                         gtt_entries = 0;
 584                         break;
 585                 }
 586         }
 587         if (gtt_entries > 0)
 588                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
 589                        gtt_entries / KB(1), local ? "local" : "stolen");
 590         else
 591                 printk(KERN_INFO PFX
 592                        "No pre-allocated video memory detected.\n");
 593         gtt_entries /= KB(4);
 594
 595         intel_private.gtt_entries = gtt_entries;
 596 }
 597
 598 static void intel_i830_fini_flush(void)
 599 {
 600         kunmap(intel_private.i8xx_page);
 601         intel_private.i8xx_flush_page = NULL;
 602         unmap_page_from_agp(intel_private.i8xx_page);
 603         flush_agp_mappings();
 604
 605         __free_page(intel_private.i8xx_page);
 606 }
 607
 608 static void intel_i830_setup_flush(void)
 609 {
 610
 611         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 612         if (!intel_private.i8xx_page) {
 613                 return;
 614         }
 615
 616         /* make page uncached */
 617         map_page_into_agp(intel_private.i8xx_page);
 618         flush_agp_mappings();
 619
 620         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 621         if (!intel_private.i8xx_flush_page)
 622                 intel_i830_fini_flush();
 623 }
 624
 625 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 626 {
 627         unsigned int *pg = intel_private.i8xx_flush_page;
 628         int i;
 629
 630         for (i = 0; i < 256; i+=2)
 631                 *(pg + i) = i;
 632
 633         wmb();
 634 }
 635
 636 /* The intel i830 automatically initializes the agp aperture during POST.
 637  * Use the memory already set aside for in the GTT.
 638  */
 639 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 640 {
 641         int page_order;
 642         struct aper_size_info_fixed *size;
 643         int num_entries;
 644         u32 temp;
 645
 646         size = agp_bridge->current_size;
 647         page_order = size->page_order;
 648         num_entries = size->num_entries;
 649         agp_bridge->gatt_table_real = NULL;
 650
 651         pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
 652         temp &= 0xfff80000;
 653
 654         intel_private.registers = ioremap(temp,128 * 4096);
 655         if (!intel_private.registers)
 656                 return -ENOMEM;
 657
 658         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 659         global_cache_flush();   /* FIXME: ?? */
 660
 661         /* we have to call this as early as possible after the MMIO base address is known */
 662         intel_i830_init_gtt_entries();
 663
 664         agp_bridge->gatt_table = NULL;
 665
 666         agp_bridge->gatt_bus_addr = temp;
 667
 668         return 0;
 669 }
 670
 671 /* Return the gatt table to a sane state. Use the top of stolen
 672  * memory for the GTT.
 673  */
 674 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 675 {
 676         return 0;
 677 }
 678
 679 static int intel_i830_fetch_size(void)
 680 {
 681         u16 gmch_ctrl;
 682         struct aper_size_info_fixed *values;
 683
 684         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 685
 686         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 687             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 688                 /* 855GM/852GM/865G has 128MB aperture size */
 689                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 690                 agp_bridge->aperture_size_idx = 0;
 691                 return values[0].size;
 692         }
 693
 694         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 695
 696         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 697                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 698                 agp_bridge->aperture_size_idx = 0;
 699                 return values[0].size;
 700         } else {
 701                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 702                 agp_bridge->aperture_size_idx = 1;
 703                 return values[1].size;
 704         }
 705
 706         return 0;
 707 }
 708
 709 static int intel_i830_configure(void)
 710 {
 711         struct aper_size_info_fixed *current_size;
 712         u32 temp;
 713         u16 gmch_ctrl;
 714         int i;
 715
 716         current_size = A_SIZE_FIX(agp_bridge->current_size);
 717
 718         pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
 719         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 720
 721         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 722         gmch_ctrl |= I830_GMCH_ENABLED;
 723         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 724
 725         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 726         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 727
 728         if (agp_bridge->driver->needs_scratch_page) {
 729                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 730                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 731                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI Posting. */
 732                 }
 733         }
 734
 735         global_cache_flush();
 736
 737         intel_i830_setup_flush();
 738         return 0;
 739 }
 740
 741 static void intel_i830_cleanup(void)
 742 {
 743         iounmap(intel_private.registers);
 744 }
 745
 746 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
 747 {
 748         int i,j,num_entries;
 749         void *temp;
 750         int ret = -EINVAL;
 751         int mask_type;
 752
 753         if (mem->page_count == 0)
 754                 goto out;
 755
 756         temp = agp_bridge->current_size;
 757         num_entries = A_SIZE_FIX(temp)->num_entries;
 758
 759         if (pg_start < intel_private.gtt_entries) {
 760                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 761                                 pg_start,intel_private.gtt_entries);
 762
 763                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 764                 goto out_err;
 765         }
 766
 767         if ((pg_start + mem->page_count) > num_entries)
 768                 goto out_err;
 769
 770         /* The i830 can't check the GTT for entries since its read only,
 771          * depend on the caller to make the correct offset decisions.
 772          */
 773
 774         if (type != mem->type)
 775                 goto out_err;
 776
 777         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 778
 779         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 780             mask_type != INTEL_AGP_CACHED_MEMORY)
 781                 goto out_err;
 782
 783         if (!mem->is_flushed)
 784                 global_cache_flush();
 785
 786         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 787                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 788                                                        mem->memory[i], mask_type),
 789                        intel_private.registers+I810_PTE_BASE+(j*4));
 790         }
 791         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 792         agp_bridge->driver->tlb_flush(mem);
 793
 794 out:
 795         ret = 0;
 796 out_err:
 797         mem->is_flushed = 1;
 798         return ret;
 799 }
 800
 801 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
 802                                 int type)
 803 {
 804         int i;
 805
 806         if (mem->page_count == 0)
 807                 return 0;
 808
 809         if (pg_start < intel_private.gtt_entries) {
 810                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
 811                 return -EINVAL;
 812         }
 813
 814         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 815                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 816         }
 817         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 818
 819         agp_bridge->driver->tlb_flush(mem);
 820         return 0;
 821 }
 822
 823 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
 824 {
 825         if (type == AGP_PHYS_MEMORY)
 826                 return alloc_agpphysmem_i8xx(pg_count, type);
 827         /* always return NULL for other allocation types for now */
 828         return NULL;
 829 }
 830
 831 static int intel_alloc_chipset_flush_resource(void)
 832 {
 833         int ret;
 834         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
 835                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
 836                                      pcibios_align_resource, agp_bridge->dev);
 837
 838         return ret;
 839 }
 840
 841 static void intel_i915_setup_chipset_flush(void)
 842 {
 843         int ret;
 844         u32 temp;
 845
 846         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
 847         if (!(temp & 0x1)) {
 848                 intel_alloc_chipset_flush_resource();
 849
 850                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 851         } else {
 852                 temp &= ~1;
 853
 854                 intel_private.ifp_resource.start = temp;
 855                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
 856                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 857                 if (ret) {
 858                         intel_private.ifp_resource.start = 0;
 859                         printk("Failed inserting resource into tree\n");
 860                 }
 861         }
 862 }
 863
 864 static void intel_i965_g33_setup_chipset_flush(void)
 865 {
 866         u32 temp_hi, temp_lo;
 867         int ret;
 868
 869         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
 870         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
 871
 872         if (!(temp_lo & 0x1)) {
 873
 874                 intel_alloc_chipset_flush_resource();
 875
 876                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
 877                         upper_32_bits(intel_private.ifp_resource.start));
 878                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 879         } else {
 880                 u64 l64;
 881
 882                 temp_lo &= ~0x1;
 883                 l64 = ((u64)temp_hi << 32) | temp_lo;
 884
 885                 intel_private.ifp_resource.start = l64;
 886                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
 887                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 888                 if (!ret) {
 889                         printk("Failed inserting resource into tree - continuing\n");
 890                 }
 891         }
 892 }
 893
 894 static void intel_i9xx_setup_flush(void)
 895 {
 896         /* setup a resource for this object */
 897         memset(&intel_private.ifp_resource, 0, sizeof(intel_private.ifp_resource));
 898
 899         intel_private.ifp_resource.name = "Intel Flush Page";
 900         intel_private.ifp_resource.flags = IORESOURCE_MEM;
 901
 902         /* Setup chipset flush for 915 */
 903         if (IS_I965 || IS_G33) {
 904                 intel_i965_g33_setup_chipset_flush();
 905         } else {
 906                 intel_i915_setup_chipset_flush();
 907         }
 908
 909         if (intel_private.ifp_resource.start) {
 910                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
 911                 if (!intel_private.i9xx_flush_page)
 912                         printk("unable to ioremap flush  page - no chipset flushing");
 913         }
 914 }
 915
 916 static int intel_i915_configure(void)
 917 {
 918         struct aper_size_info_fixed *current_size;
 919         u32 temp;
 920         u16 gmch_ctrl;
 921         int i;
 922
 923         current_size = A_SIZE_FIX(agp_bridge->current_size);
 924
 925         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
 926
 927         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 928
 929         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 930         gmch_ctrl |= I830_GMCH_ENABLED;
 931         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 932
 933         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 934         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 935
 936         if (agp_bridge->driver->needs_scratch_page) {
 937                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 938                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
 939                         readl(intel_private.gtt+i);     /* PCI Posting. */
 940                 }
 941         }
 942
 943         global_cache_flush();
 944
 945         intel_i9xx_setup_flush();
 946
 947         return 0;
 948 }
 949
 950 static void intel_i915_cleanup(void)
 951 {
 952         if (intel_private.i9xx_flush_page)
 953                 iounmap(intel_private.i9xx_flush_page);
 954         iounmap(intel_private.gtt);
 955         iounmap(intel_private.registers);
 956 }
 957
 958 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
 959 {
 960         if (intel_private.i9xx_flush_page)
 961                 writel(1, intel_private.i9xx_flush_page);
 962 }
 963
 964 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
 965                                 int type)
 966 {
 967         int i,j,num_entries;
 968         void *temp;
 969         int ret = -EINVAL;
 970         int mask_type;
 971
 972         if (mem->page_count == 0)
 973                 goto out;
 974
 975         temp = agp_bridge->current_size;
 976         num_entries = A_SIZE_FIX(temp)->num_entries;
 977
 978         if (pg_start < intel_private.gtt_entries) {
 979                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 980                                 pg_start,intel_private.gtt_entries);
 981
 982                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 983                 goto out_err;
 984         }
 985
 986         if ((pg_start + mem->page_count) > num_entries)
 987                 goto out_err;
 988
 989         /* The i915 can't check the GTT for entries since its read only,
 990          * depend on the caller to make the correct offset decisions.
 991          */
 992
 993         if (type != mem->type)
 994                 goto out_err;
 995
 996         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 997
 998         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 999             mask_type != INTEL_AGP_CACHED_MEMORY)
1000                 goto out_err;
1001
1002         if (!mem->is_flushed)
1003                 global_cache_flush();
1004
1005         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1006                 writel(agp_bridge->driver->mask_memory(agp_bridge,
1007                         mem->memory[i], mask_type), intel_private.gtt+j);
1008         }
1009
1010         readl(intel_private.gtt+j-1);
1011         agp_bridge->driver->tlb_flush(mem);
1012
1013  out:
1014         ret = 0;
1015  out_err:
1016         mem->is_flushed = 1;
1017         return ret;
1018 }
1019
1020 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
1021                                 int type)
1022 {
1023         int i;
1024
1025         if (mem->page_count == 0)
1026                 return 0;
1027
1028         if (pg_start < intel_private.gtt_entries) {
1029                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
1030                 return -EINVAL;
1031         }
1032
1033         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1034                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1035         }
1036         readl(intel_private.gtt+i-1);
1037
1038         agp_bridge->driver->tlb_flush(mem);
1039         return 0;
1040 }
1041
1042 /* Return the aperture size by just checking the resource length.  The effect
1043  * described in the spec of the MSAC registers is just changing of the
1044  * resource size.
1045  */
1046 static int intel_i9xx_fetch_size(void)
1047 {
1048         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1049         int aper_size; /* size in megabytes */
1050         int i;
1051
1052         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1053
1054         for (i = 0; i < num_sizes; i++) {
1055                 if (aper_size == intel_i830_sizes[i].size) {
1056                         agp_bridge->current_size = intel_i830_sizes + i;
1057                         agp_bridge->previous_size = agp_bridge->current_size;
1058                         return aper_size;
1059                 }
1060         }
1061
1062         return 0;
1063 }
1064
1065 /* The intel i915 automatically initializes the agp aperture during POST.
1066  * Use the memory already set aside for in the GTT.
1067  */
1068 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1069 {
1070         int page_order;
1071         struct aper_size_info_fixed *size;
1072         int num_entries;
1073         u32 temp, temp2;
1074         int gtt_map_size = 256 * 1024;
1075
1076         size = agp_bridge->current_size;
1077         page_order = size->page_order;
1078         num_entries = size->num_entries;
1079         agp_bridge->gatt_table_real = NULL;
1080
1081         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1082         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
1083
1084         if (IS_G33)
1085             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1086         intel_private.gtt = ioremap(temp2, gtt_map_size);
1087         if (!intel_private.gtt)
1088                 return -ENOMEM;
1089
1090         temp &= 0xfff80000;
1091
1092         intel_private.registers = ioremap(temp,128 * 4096);
1093         if (!intel_private.registers) {
1094                 iounmap(intel_private.gtt);
1095                 return -ENOMEM;
1096         }
1097
1098         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1099         global_cache_flush();   /* FIXME: ? */
1100
1101         /* we have to call this as early as possible after the MMIO base address is known */
1102         intel_i830_init_gtt_entries();
1103
1104         agp_bridge->gatt_table = NULL;
1105
1106         agp_bridge->gatt_bus_addr = temp;
1107
1108         return 0;
1109 }
1110
1111 /*
1112  * The i965 supports 36-bit physical addresses, but to keep
1113  * the format of the GTT the same, the bits that don't fit
1114  * in a 32-bit word are shifted down to bits 4..7.
1115  *
1116  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1117  * is always zero on 32-bit architectures, so no need to make
1118  * this conditional.
1119  */
1120 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1121         unsigned long addr, int type)
1122 {
1123         /* Shift high bits down */
1124         addr |= (addr >> 28) & 0xf0;
1125
1126         /* Type checking must be done elsewhere */
1127         return addr | bridge->driver->masks[type].mask;
1128 }
1129
1130 /* The intel i965 automatically initializes the agp aperture during POST.
1131  * Use the memory already set aside for in the GTT.
1132  */
1133 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1134 {
1135        int page_order;
1136        struct aper_size_info_fixed *size;
1137        int num_entries;
1138        u32 temp;
1139        int gtt_offset, gtt_size;
1140
1141        size = agp_bridge->current_size;
1142        page_order = size->page_order;
1143        num_entries = size->num_entries;
1144        agp_bridge->gatt_table_real = NULL;
1145
1146        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1147
1148        temp &= 0xfff00000;
1149
1150        if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
1151                gtt_offset = gtt_size = MB(2);
1152        else
1153                gtt_offset = gtt_size = KB(512);
1154
1155        intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1156
1157        if (!intel_private.gtt)
1158                return -ENOMEM;
1159
1160        intel_private.registers = ioremap(temp, 128 * 4096);
1161        if (!intel_private.registers) {
1162                 iounmap(intel_private.gtt);
1163                 return -ENOMEM;
1164         }
1165
1166        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1167        global_cache_flush();   /* FIXME: ? */
1168
1169        /* we have to call this as early as possible after the MMIO base address is known */
1170        intel_i830_init_gtt_entries();
1171
1172        agp_bridge->gatt_table = NULL;
1173
1174        agp_bridge->gatt_bus_addr = temp;
1175
1176        return 0;
1177 }
1178
1179
1180 static int intel_fetch_size(void)
1181 {
1182         int i;
1183         u16 temp;
1184         struct aper_size_info_16 *values;
1185
1186         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1187         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1188
1189         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1190                 if (temp == values[i].size_value) {
1191                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1192                         agp_bridge->aperture_size_idx = i;
1193                         return values[i].size;
1194                 }
1195         }
1196
1197         return 0;
1198 }
1199
1200 static int __intel_8xx_fetch_size(u8 temp)
1201 {
1202         int i;
1203         struct aper_size_info_8 *values;
1204
1205         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1206
1207         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1208                 if (temp == values[i].size_value) {
1209                         agp_bridge->previous_size =
1210                                 agp_bridge->current_size = (void *) (values + i);
1211                         agp_bridge->aperture_size_idx = i;
1212                         return values[i].size;
1213                 }
1214         }
1215         return 0;
1216 }
1217
1218 static int intel_8xx_fetch_size(void)
1219 {
1220         u8 temp;
1221
1222         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1223         return __intel_8xx_fetch_size(temp);
1224 }
1225
1226 static int intel_815_fetch_size(void)
1227 {
1228         u8 temp;
1229
1230         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1231          * one non-reserved bit, so mask the others out ... */
1232         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1233         temp &= (1 << 3);
1234
1235         return __intel_8xx_fetch_size(temp);
1236 }
1237
1238 static void intel_tlbflush(struct agp_memory *mem)
1239 {
1240         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1241         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1242 }
1243
1244
1245 static void intel_8xx_tlbflush(struct agp_memory *mem)
1246 {
1247         u32 temp;
1248         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1249         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1250         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1251         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1252 }
1253
1254
1255 static void intel_cleanup(void)
1256 {
1257         u16 temp;
1258         struct aper_size_info_16 *previous_size;
1259
1260         previous_size = A_SIZE_16(agp_bridge->previous_size);
1261         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1262         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1263         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1264 }
1265
1266
1267 static void intel_8xx_cleanup(void)
1268 {
1269         u16 temp;
1270         struct aper_size_info_8 *previous_size;
1271
1272         previous_size = A_SIZE_8(agp_bridge->previous_size);
1273         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1274         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1275         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1276 }
1277
1278
1279 static int intel_configure(void)
1280 {
1281         u32 temp;
1282         u16 temp2;
1283         struct aper_size_info_16 *current_size;
1284
1285         current_size = A_SIZE_16(agp_bridge->current_size);
1286
1287         /* aperture size */
1288         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1289
1290         /* address to map to */
1291         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1292         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1293
1294         /* attbase - aperture base */
1295         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1296
1297         /* agpctrl */
1298         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1299
1300         /* paccfg/nbxcfg */
1301         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1302         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1303                         (temp2 & ~(1 << 10)) | (1 << 9));
1304         /* clear any possible error conditions */
1305         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1306         return 0;
1307 }
1308
1309 static int intel_815_configure(void)
1310 {
1311         u32 temp, addr;
1312         u8 temp2;
1313         struct aper_size_info_8 *current_size;
1314
1315         /* attbase - aperture base */
1316         /* the Intel 815 chipset spec. says that bits 29-31 in the
1317         * ATTBASE register are reserved -> try not to write them */
1318         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1319                 printk (KERN_EMERG PFX "gatt bus addr too high");
1320                 return -EINVAL;
1321         }
1322
1323         current_size = A_SIZE_8(agp_bridge->current_size);
1324
1325         /* aperture size */
1326         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1327                         current_size->size_value);
1328
1329         /* address to map to */
1330         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1331         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1332
1333         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1334         addr &= INTEL_815_ATTBASE_MASK;
1335         addr |= agp_bridge->gatt_bus_addr;
1336         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1337
1338         /* agpctrl */
1339         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1340
1341         /* apcont */
1342         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1343         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1344
1345         /* clear any possible error conditions */
1346         /* Oddness : this chipset seems to have no ERRSTS register ! */
1347         return 0;
1348 }
1349
1350 static void intel_820_tlbflush(struct agp_memory *mem)
1351 {
1352         return;
1353 }
1354
1355 static void intel_820_cleanup(void)
1356 {
1357         u8 temp;
1358         struct aper_size_info_8 *previous_size;
1359
1360         previous_size = A_SIZE_8(agp_bridge->previous_size);
1361         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1362         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1363                         temp & ~(1 << 1));
1364         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1365                         previous_size->size_value);
1366 }
1367
1368
1369 static int intel_820_configure(void)
1370 {
1371         u32 temp;
1372         u8 temp2;
1373         struct aper_size_info_8 *current_size;
1374
1375         current_size = A_SIZE_8(agp_bridge->current_size);
1376
1377         /* aperture size */
1378         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1379
1380         /* address to map to */
1381         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1382         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1383
1384         /* attbase - aperture base */
1385         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1386
1387         /* agpctrl */
1388         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1389
1390         /* global enable aperture access */
1391         /* This flag is not accessed through MCHCFG register as in */
1392         /* i850 chipset. */
1393         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1394         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1395         /* clear any possible AGP-related error conditions */
1396         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1397         return 0;
1398 }
1399
1400 static int intel_840_configure(void)
1401 {
1402         u32 temp;
1403         u16 temp2;
1404         struct aper_size_info_8 *current_size;
1405
1406         current_size = A_SIZE_8(agp_bridge->current_size);
1407
1408         /* aperture size */
1409         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1410
1411         /* address to map to */
1412         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1413         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1414
1415         /* attbase - aperture base */
1416         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1417
1418         /* agpctrl */
1419         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1420
1421         /* mcgcfg */
1422         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1423         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1424         /* clear any possible error conditions */
1425         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1426         return 0;
1427 }
1428
1429 static int intel_845_configure(void)
1430 {
1431         u32 temp;
1432         u8 temp2;
1433         struct aper_size_info_8 *current_size;
1434
1435         current_size = A_SIZE_8(agp_bridge->current_size);
1436
1437         /* aperture size */
1438         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1439
1440         if (agp_bridge->apbase_config != 0) {
1441                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1442                                        agp_bridge->apbase_config);
1443         } else {
1444                 /* address to map to */
1445                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1446                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1447                 agp_bridge->apbase_config = temp;
1448         }
1449
1450         /* attbase - aperture base */
1451         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1452
1453         /* agpctrl */
1454         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1455
1456         /* agpm */
1457         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1458         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1459         /* clear any possible error conditions */
1460         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1461
1462         intel_i830_setup_flush();
1463         return 0;
1464 }
1465
1466 static int intel_850_configure(void)
1467 {
1468         u32 temp;
1469         u16 temp2;
1470         struct aper_size_info_8 *current_size;
1471
1472         current_size = A_SIZE_8(agp_bridge->current_size);
1473
1474         /* aperture size */
1475         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1476
1477         /* address to map to */
1478         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1479         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1480
1481         /* attbase - aperture base */
1482         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1483
1484         /* agpctrl */
1485         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1486
1487         /* mcgcfg */
1488         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1489         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1490         /* clear any possible AGP-related error conditions */
1491         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1492         return 0;
1493 }
1494
1495 static int intel_860_configure(void)
1496 {
1497         u32 temp;
1498         u16 temp2;
1499         struct aper_size_info_8 *current_size;
1500
1501         current_size = A_SIZE_8(agp_bridge->current_size);
1502
1503         /* aperture size */
1504         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1505
1506         /* address to map to */
1507         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1508         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1509
1510         /* attbase - aperture base */
1511         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1512
1513         /* agpctrl */
1514         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1515
1516         /* mcgcfg */
1517         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1518         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1519         /* clear any possible AGP-related error conditions */
1520         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1521         return 0;
1522 }
1523
1524 static int intel_830mp_configure(void)
1525 {
1526         u32 temp;
1527         u16 temp2;
1528         struct aper_size_info_8 *current_size;
1529
1530         current_size = A_SIZE_8(agp_bridge->current_size);
1531
1532         /* aperture size */
1533         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1534
1535         /* address to map to */
1536         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1537         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1538
1539         /* attbase - aperture base */
1540         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1541
1542         /* agpctrl */
1543         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1544
1545         /* gmch */
1546         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1547         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1548         /* clear any possible AGP-related error conditions */
1549         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1550         return 0;
1551 }
1552
1553 static int intel_7505_configure(void)
1554 {
1555         u32 temp;
1556         u16 temp2;
1557         struct aper_size_info_8 *current_size;
1558
1559         current_size = A_SIZE_8(agp_bridge->current_size);
1560
1561         /* aperture size */
1562         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1563
1564         /* address to map to */
1565         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1566         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1567
1568         /* attbase - aperture base */
1569         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1570
1571         /* agpctrl */
1572         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1573
1574         /* mchcfg */
1575         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1576         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1577
1578         return 0;
1579 }
1580
1581 /* Setup function */
1582 static const struct gatt_mask intel_generic_masks[] =
1583 {
1584         {.mask = 0x00000017, .type = 0}
1585 };
1586
1587 static const struct aper_size_info_8 intel_815_sizes[2] =
1588 {
1589         {64, 16384, 4, 0},
1590         {32, 8192, 3, 8},
1591 };
1592
1593 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1594 {
1595         {256, 65536, 6, 0},
1596         {128, 32768, 5, 32},
1597         {64, 16384, 4, 48},
1598         {32, 8192, 3, 56},
1599         {16, 4096, 2, 60},
1600         {8, 2048, 1, 62},
1601         {4, 1024, 0, 63}
1602 };
1603
1604 static const struct aper_size_info_16 intel_generic_sizes[7] =
1605 {
1606         {256, 65536, 6, 0},
1607         {128, 32768, 5, 32},
1608         {64, 16384, 4, 48},
1609         {32, 8192, 3, 56},
1610         {16, 4096, 2, 60},
1611         {8, 2048, 1, 62},
1612         {4, 1024, 0, 63}
1613 };
1614
1615 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1616 {
1617         {256, 65536, 6, 0},
1618         {128, 32768, 5, 32},
1619         {64, 16384, 4, 48},
1620         {32, 8192, 3, 56}
1621 };
1622
1623 static const struct agp_bridge_driver intel_generic_driver = {
1624         .owner                  = THIS_MODULE,
1625         .aperture_sizes         = intel_generic_sizes,
1626         .size_type              = U16_APER_SIZE,
1627         .num_aperture_sizes     = 7,
1628         .configure              = intel_configure,
1629         .fetch_size             = intel_fetch_size,
1630         .cleanup                = intel_cleanup,
1631         .tlb_flush              = intel_tlbflush,
1632         .mask_memory            = agp_generic_mask_memory,
1633         .masks                  = intel_generic_masks,
1634         .agp_enable             = agp_generic_enable,
1635         .cache_flush            = global_cache_flush,
1636         .create_gatt_table      = agp_generic_create_gatt_table,
1637         .free_gatt_table        = agp_generic_free_gatt_table,
1638         .insert_memory          = agp_generic_insert_memory,
1639         .remove_memory          = agp_generic_remove_memory,
1640         .alloc_by_type          = agp_generic_alloc_by_type,
1641         .free_by_type           = agp_generic_free_by_type,
1642         .agp_alloc_page         = agp_generic_alloc_page,
1643         .agp_destroy_page       = agp_generic_destroy_page,
1644         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1645 };
1646
1647 static const struct agp_bridge_driver intel_810_driver = {
1648         .owner                  = THIS_MODULE,
1649         .aperture_sizes         = intel_i810_sizes,
1650         .size_type              = FIXED_APER_SIZE,
1651         .num_aperture_sizes     = 2,
1652         .needs_scratch_page     = TRUE,
1653         .configure              = intel_i810_configure,
1654         .fetch_size             = intel_i810_fetch_size,
1655         .cleanup                = intel_i810_cleanup,
1656         .tlb_flush              = intel_i810_tlbflush,
1657         .mask_memory            = intel_i810_mask_memory,
1658         .masks                  = intel_i810_masks,
1659         .agp_enable             = intel_i810_agp_enable,
1660         .cache_flush            = global_cache_flush,
1661         .create_gatt_table      = agp_generic_create_gatt_table,
1662         .free_gatt_table        = agp_generic_free_gatt_table,
1663         .insert_memory          = intel_i810_insert_entries,
1664         .remove_memory          = intel_i810_remove_entries,
1665         .alloc_by_type          = intel_i810_alloc_by_type,
1666         .free_by_type           = intel_i810_free_by_type,
1667         .agp_alloc_page         = agp_generic_alloc_page,
1668         .agp_destroy_page       = agp_generic_destroy_page,
1669         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1670 };
1671
1672 static const struct agp_bridge_driver intel_815_driver = {
1673         .owner                  = THIS_MODULE,
1674         .aperture_sizes         = intel_815_sizes,
1675         .size_type              = U8_APER_SIZE,
1676         .num_aperture_sizes     = 2,
1677         .configure              = intel_815_configure,
1678         .fetch_size             = intel_815_fetch_size,
1679         .cleanup                = intel_8xx_cleanup,
1680         .tlb_flush              = intel_8xx_tlbflush,
1681         .mask_memory            = agp_generic_mask_memory,
1682         .masks                  = intel_generic_masks,
1683         .agp_enable             = agp_generic_enable,
1684         .cache_flush            = global_cache_flush,
1685         .create_gatt_table      = agp_generic_create_gatt_table,
1686         .free_gatt_table        = agp_generic_free_gatt_table,
1687         .insert_memory          = agp_generic_insert_memory,
1688         .remove_memory          = agp_generic_remove_memory,
1689         .alloc_by_type          = agp_generic_alloc_by_type,
1690         .free_by_type           = agp_generic_free_by_type,
1691         .agp_alloc_page         = agp_generic_alloc_page,
1692         .agp_destroy_page       = agp_generic_destroy_page,
1693         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1694 };
1695
1696 static const struct agp_bridge_driver intel_830_driver = {
1697         .owner                  = THIS_MODULE,
1698         .aperture_sizes         = intel_i830_sizes,
1699         .size_type              = FIXED_APER_SIZE,
1700         .num_aperture_sizes     = 4,
1701         .needs_scratch_page     = TRUE,
1702         .configure              = intel_i830_configure,
1703         .fetch_size             = intel_i830_fetch_size,
1704         .cleanup                = intel_i830_cleanup,
1705         .tlb_flush              = intel_i810_tlbflush,
1706         .mask_memory            = intel_i810_mask_memory,
1707         .masks                  = intel_i810_masks,
1708         .agp_enable             = intel_i810_agp_enable,
1709         .cache_flush            = global_cache_flush,
1710         .create_gatt_table      = intel_i830_create_gatt_table,
1711         .free_gatt_table        = intel_i830_free_gatt_table,
1712         .insert_memory          = intel_i830_insert_entries,
1713         .remove_memory          = intel_i830_remove_entries,
1714         .alloc_by_type          = intel_i830_alloc_by_type,
1715         .free_by_type           = intel_i810_free_by_type,
1716         .agp_alloc_page         = agp_generic_alloc_page,
1717         .agp_destroy_page       = agp_generic_destroy_page,
1718         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1719         .chipset_flush          = intel_i830_chipset_flush,
1720 };
1721
1722 static const struct agp_bridge_driver intel_820_driver = {
1723         .owner                  = THIS_MODULE,
1724         .aperture_sizes         = intel_8xx_sizes,
1725         .size_type              = U8_APER_SIZE,
1726         .num_aperture_sizes     = 7,
1727         .configure              = intel_820_configure,
1728         .fetch_size             = intel_8xx_fetch_size,
1729         .cleanup                = intel_820_cleanup,
1730         .tlb_flush              = intel_820_tlbflush,
1731         .mask_memory            = agp_generic_mask_memory,
1732         .masks                  = intel_generic_masks,
1733         .agp_enable             = agp_generic_enable,
1734         .cache_flush            = global_cache_flush,
1735         .create_gatt_table      = agp_generic_create_gatt_table,
1736         .free_gatt_table        = agp_generic_free_gatt_table,
1737         .insert_memory          = agp_generic_insert_memory,
1738         .remove_memory          = agp_generic_remove_memory,
1739         .alloc_by_type          = agp_generic_alloc_by_type,
1740         .free_by_type           = agp_generic_free_by_type,
1741         .agp_alloc_page         = agp_generic_alloc_page,
1742         .agp_destroy_page       = agp_generic_destroy_page,
1743         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1744 };
1745
1746 static const struct agp_bridge_driver intel_830mp_driver = {
1747         .owner                  = THIS_MODULE,
1748         .aperture_sizes         = intel_830mp_sizes,
1749         .size_type              = U8_APER_SIZE,
1750         .num_aperture_sizes     = 4,
1751         .configure              = intel_830mp_configure,
1752         .fetch_size             = intel_8xx_fetch_size,
1753         .cleanup                = intel_8xx_cleanup,
1754         .tlb_flush              = intel_8xx_tlbflush,
1755         .mask_memory            = agp_generic_mask_memory,
1756         .masks                  = intel_generic_masks,
1757         .agp_enable             = agp_generic_enable,
1758         .cache_flush            = global_cache_flush,
1759         .create_gatt_table      = agp_generic_create_gatt_table,
1760         .free_gatt_table        = agp_generic_free_gatt_table,
1761         .insert_memory          = agp_generic_insert_memory,
1762         .remove_memory          = agp_generic_remove_memory,
1763         .alloc_by_type          = agp_generic_alloc_by_type,
1764         .free_by_type           = agp_generic_free_by_type,
1765         .agp_alloc_page         = agp_generic_alloc_page,
1766         .agp_destroy_page       = agp_generic_destroy_page,
1767         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1768 };
1769
1770 static const struct agp_bridge_driver intel_840_driver = {
1771         .owner                  = THIS_MODULE,
1772         .aperture_sizes         = intel_8xx_sizes,
1773         .size_type              = U8_APER_SIZE,
1774         .num_aperture_sizes     = 7,
1775         .configure              = intel_840_configure,
1776         .fetch_size             = intel_8xx_fetch_size,
1777         .cleanup                = intel_8xx_cleanup,
1778         .tlb_flush              = intel_8xx_tlbflush,
1779         .mask_memory            = agp_generic_mask_memory,
1780         .masks                  = intel_generic_masks,
1781         .agp_enable             = agp_generic_enable,
1782         .cache_flush            = global_cache_flush,
1783         .create_gatt_table      = agp_generic_create_gatt_table,
1784         .free_gatt_table        = agp_generic_free_gatt_table,
1785         .insert_memory          = agp_generic_insert_memory,
1786         .remove_memory          = agp_generic_remove_memory,
1787         .alloc_by_type          = agp_generic_alloc_by_type,
1788         .free_by_type           = agp_generic_free_by_type,
1789         .agp_alloc_page         = agp_generic_alloc_page,
1790         .agp_destroy_page       = agp_generic_destroy_page,
1791         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1792 };
1793
1794 static const struct agp_bridge_driver intel_845_driver = {
1795         .owner                  = THIS_MODULE,
1796         .aperture_sizes         = intel_8xx_sizes,
1797         .size_type              = U8_APER_SIZE,
1798         .num_aperture_sizes     = 7,
1799         .configure              = intel_845_configure,
1800         .fetch_size             = intel_8xx_fetch_size,
1801         .cleanup                = intel_8xx_cleanup,
1802         .tlb_flush              = intel_8xx_tlbflush,
1803         .mask_memory            = agp_generic_mask_memory,
1804         .masks                  = intel_generic_masks,
1805         .agp_enable             = agp_generic_enable,
1806         .cache_flush            = global_cache_flush,
1807         .create_gatt_table      = agp_generic_create_gatt_table,
1808         .free_gatt_table        = agp_generic_free_gatt_table,
1809         .insert_memory          = agp_generic_insert_memory,
1810         .remove_memory          = agp_generic_remove_memory,
1811         .alloc_by_type          = agp_generic_alloc_by_type,
1812         .free_by_type           = agp_generic_free_by_type,
1813         .agp_alloc_page         = agp_generic_alloc_page,
1814         .agp_destroy_page       = agp_generic_destroy_page,
1815         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1816         .chipset_flush          = intel_i830_chipset_flush,
1817 };
1818
1819 static const struct agp_bridge_driver intel_850_driver = {
1820         .owner                  = THIS_MODULE,
1821         .aperture_sizes         = intel_8xx_sizes,
1822         .size_type              = U8_APER_SIZE,
1823         .num_aperture_sizes     = 7,
1824         .configure              = intel_850_configure,
1825         .fetch_size             = intel_8xx_fetch_size,
1826         .cleanup                = intel_8xx_cleanup,
1827         .tlb_flush              = intel_8xx_tlbflush,
1828         .mask_memory            = agp_generic_mask_memory,
1829         .masks                  = intel_generic_masks,
1830         .agp_enable             = agp_generic_enable,
1831         .cache_flush            = global_cache_flush,
1832         .create_gatt_table      = agp_generic_create_gatt_table,
1833         .free_gatt_table        = agp_generic_free_gatt_table,
1834         .insert_memory          = agp_generic_insert_memory,
1835         .remove_memory          = agp_generic_remove_memory,
1836         .alloc_by_type          = agp_generic_alloc_by_type,
1837         .free_by_type           = agp_generic_free_by_type,
1838         .agp_alloc_page         = agp_generic_alloc_page,
1839         .agp_destroy_page       = agp_generic_destroy_page,
1840         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1841 };
1842
1843 static const struct agp_bridge_driver intel_860_driver = {
1844         .owner                  = THIS_MODULE,
1845         .aperture_sizes         = intel_8xx_sizes,
1846         .size_type              = U8_APER_SIZE,
1847         .num_aperture_sizes     = 7,
1848         .configure              = intel_860_configure,
1849         .fetch_size             = intel_8xx_fetch_size,
1850         .cleanup                = intel_8xx_cleanup,
1851         .tlb_flush              = intel_8xx_tlbflush,
1852         .mask_memory            = agp_generic_mask_memory,
1853         .masks                  = intel_generic_masks,
1854         .agp_enable             = agp_generic_enable,
1855         .cache_flush            = global_cache_flush,
1856         .create_gatt_table      = agp_generic_create_gatt_table,
1857         .free_gatt_table        = agp_generic_free_gatt_table,
1858         .insert_memory          = agp_generic_insert_memory,
1859         .remove_memory          = agp_generic_remove_memory,
1860         .alloc_by_type          = agp_generic_alloc_by_type,
1861         .free_by_type           = agp_generic_free_by_type,
1862         .agp_alloc_page         = agp_generic_alloc_page,
1863         .agp_destroy_page       = agp_generic_destroy_page,
1864         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1865 };
1866
1867 static const struct agp_bridge_driver intel_915_driver = {
1868         .owner                  = THIS_MODULE,
1869         .aperture_sizes         = intel_i830_sizes,
1870         .size_type              = FIXED_APER_SIZE,
1871         .num_aperture_sizes     = 4,
1872         .needs_scratch_page     = TRUE,
1873         .configure              = intel_i915_configure,
1874         .fetch_size             = intel_i9xx_fetch_size,
1875         .cleanup                = intel_i915_cleanup,
1876         .tlb_flush              = intel_i810_tlbflush,
1877         .mask_memory            = intel_i810_mask_memory,
1878         .masks                  = intel_i810_masks,
1879         .agp_enable             = intel_i810_agp_enable,
1880         .cache_flush            = global_cache_flush,
1881         .create_gatt_table      = intel_i915_create_gatt_table,
1882         .free_gatt_table        = intel_i830_free_gatt_table,
1883         .insert_memory          = intel_i915_insert_entries,
1884         .remove_memory          = intel_i915_remove_entries,
1885         .alloc_by_type          = intel_i830_alloc_by_type,
1886         .free_by_type           = intel_i810_free_by_type,
1887         .agp_alloc_page         = agp_generic_alloc_page,
1888         .agp_destroy_page       = agp_generic_destroy_page,
1889         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1890         .chipset_flush          = intel_i915_chipset_flush,
1891 };
1892
1893 static const struct agp_bridge_driver intel_i965_driver = {
1894        .owner                  = THIS_MODULE,
1895        .aperture_sizes         = intel_i830_sizes,
1896        .size_type              = FIXED_APER_SIZE,
1897        .num_aperture_sizes     = 4,
1898        .needs_scratch_page     = TRUE,
1899        .configure              = intel_i915_configure,
1900        .fetch_size             = intel_i9xx_fetch_size,
1901        .cleanup                = intel_i915_cleanup,
1902        .tlb_flush              = intel_i810_tlbflush,
1903        .mask_memory            = intel_i965_mask_memory,
1904        .masks                  = intel_i810_masks,
1905        .agp_enable             = intel_i810_agp_enable,
1906        .cache_flush            = global_cache_flush,
1907        .create_gatt_table      = intel_i965_create_gatt_table,
1908        .free_gatt_table        = intel_i830_free_gatt_table,
1909        .insert_memory          = intel_i915_insert_entries,
1910        .remove_memory          = intel_i915_remove_entries,
1911        .alloc_by_type          = intel_i830_alloc_by_type,
1912        .free_by_type           = intel_i810_free_by_type,
1913        .agp_alloc_page         = agp_generic_alloc_page,
1914        .agp_destroy_page       = agp_generic_destroy_page,
1915        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1916         .chipset_flush          = intel_i915_chipset_flush,
1917 };
1918
1919 static const struct agp_bridge_driver intel_7505_driver = {
1920         .owner                  = THIS_MODULE,
1921         .aperture_sizes         = intel_8xx_sizes,
1922         .size_type              = U8_APER_SIZE,
1923         .num_aperture_sizes     = 7,
1924         .configure              = intel_7505_configure,
1925         .fetch_size             = intel_8xx_fetch_size,
1926         .cleanup                = intel_8xx_cleanup,
1927         .tlb_flush              = intel_8xx_tlbflush,
1928         .mask_memory            = agp_generic_mask_memory,
1929         .masks                  = intel_generic_masks,
1930         .agp_enable             = agp_generic_enable,
1931         .cache_flush            = global_cache_flush,
1932         .create_gatt_table      = agp_generic_create_gatt_table,
1933         .free_gatt_table        = agp_generic_free_gatt_table,
1934         .insert_memory          = agp_generic_insert_memory,
1935         .remove_memory          = agp_generic_remove_memory,
1936         .alloc_by_type          = agp_generic_alloc_by_type,
1937         .free_by_type           = agp_generic_free_by_type,
1938         .agp_alloc_page         = agp_generic_alloc_page,
1939         .agp_destroy_page       = agp_generic_destroy_page,
1940         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1941 };
1942
1943 static const struct agp_bridge_driver intel_g33_driver = {
1944         .owner                  = THIS_MODULE,
1945         .aperture_sizes         = intel_i830_sizes,
1946         .size_type              = FIXED_APER_SIZE,
1947         .num_aperture_sizes     = 4,
1948         .needs_scratch_page     = TRUE,
1949         .configure              = intel_i915_configure,
1950         .fetch_size             = intel_i9xx_fetch_size,
1951         .cleanup                = intel_i915_cleanup,
1952         .tlb_flush              = intel_i810_tlbflush,
1953         .mask_memory            = intel_i965_mask_memory,
1954         .masks                  = intel_i810_masks,
1955         .agp_enable             = intel_i810_agp_enable,
1956         .cache_flush            = global_cache_flush,
1957         .create_gatt_table      = intel_i915_create_gatt_table,
1958         .free_gatt_table        = intel_i830_free_gatt_table,
1959         .insert_memory          = intel_i915_insert_entries,
1960         .remove_memory          = intel_i915_remove_entries,
1961         .alloc_by_type          = intel_i830_alloc_by_type,
1962         .free_by_type           = intel_i810_free_by_type,
1963         .agp_alloc_page         = agp_generic_alloc_page,
1964         .agp_destroy_page       = agp_generic_destroy_page,
1965         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1966         .chipset_flush          = intel_i915_chipset_flush,
1967 };
1968
1969 static int find_gmch(u16 device)
1970 {
1971         struct pci_dev *gmch_device;
1972
1973         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1974         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1975                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1976                                 device, gmch_device);
1977         }
1978
1979         if (!gmch_device)
1980                 return 0;
1981
1982         intel_private.pcidev = gmch_device;
1983         return 1;
1984 }
1985
1986 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1987  * driver and gmch_driver must be non-null, and find_gmch will determine
1988  * which one should be used if a gmch_chip_id is present.
1989  */
1990 static const struct intel_driver_description {
1991         unsigned int chip_id;
1992         unsigned int gmch_chip_id;
1993         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
1994         char *name;
1995         const struct agp_bridge_driver *driver;
1996         const struct agp_bridge_driver *gmch_driver;
1997 } intel_agp_chipsets[] = {
1998         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1999         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2000         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2001         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2002                 NULL, &intel_810_driver },
2003         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2004                 NULL, &intel_810_driver },
2005         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2006                 NULL, &intel_810_driver },
2007         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2008                 &intel_815_driver, &intel_810_driver },
2009         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2010         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2011         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2012                 &intel_830mp_driver, &intel_830_driver },
2013         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2014         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2015         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2016                 &intel_845_driver, &intel_830_driver },
2017         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2018         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2019         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2020                 &intel_845_driver, &intel_830_driver },
2021         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2022         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2023                 &intel_845_driver, &intel_830_driver },
2024         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2025         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2026                 NULL, &intel_915_driver },
2027         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2028                 NULL, &intel_915_driver },
2029         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2030                 NULL, &intel_915_driver },
2031         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2032                 NULL, &intel_915_driver },
2033         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2034                 NULL, &intel_915_driver },
2035         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2036                 NULL, &intel_915_driver },
2037         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2038                 NULL, &intel_i965_driver },
2039         { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
2040                 NULL, &intel_i965_driver },
2041         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2042                 NULL, &intel_i965_driver },
2043         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2044                 NULL, &intel_i965_driver },
2045         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2046                 NULL, &intel_i965_driver },
2047         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2048                 NULL, &intel_i965_driver },
2049         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2050         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2051         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2052                 NULL, &intel_g33_driver },
2053         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2054                 NULL, &intel_g33_driver },
2055         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2056                 NULL, &intel_g33_driver },
2057         { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
2058             "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2059         { 0, 0, 0, NULL, NULL, NULL }
2060 };
2061
2062 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2063                                      const struct pci_device_id *ent)
2064 {
2065         struct agp_bridge_data *bridge;
2066         u8 cap_ptr = 0;
2067         struct resource *r;
2068         int i;
2069
2070         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2071
2072         bridge = agp_alloc_bridge();
2073         if (!bridge)
2074                 return -ENOMEM;
2075
2076         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2077                 /* In case that multiple models of gfx chip may
2078                    stand on same host bridge type, this can be
2079                    sure we detect the right IGD. */
2080                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2081                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2082                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2083                                 bridge->driver =
2084                                         intel_agp_chipsets[i].gmch_driver;
2085                                 break;
2086                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2087                                 continue;
2088                         } else {
2089                                 bridge->driver = intel_agp_chipsets[i].driver;
2090                                 break;
2091                         }
2092                 }
2093         }
2094
2095         if (intel_agp_chipsets[i].name == NULL) {
2096                 if (cap_ptr)
2097                         printk(KERN_WARNING PFX "Unsupported Intel chipset"
2098                                "(device id: %04x)\n", pdev->device);
2099                 agp_put_bridge(bridge);
2100                 return -ENODEV;
2101         }
2102
2103         if (bridge->driver == NULL) {
2104                 /* bridge has no AGP and no IGD detected */
2105                 if (cap_ptr)
2106                         printk(KERN_WARNING PFX "Failed to find bridge device "
2107                                 "(chip_id: %04x)\n",
2108                                 intel_agp_chipsets[i].gmch_chip_id);
2109                 agp_put_bridge(bridge);
2110                 return -ENODEV;
2111         }
2112
2113         bridge->dev = pdev;
2114         bridge->capndx = cap_ptr;
2115         bridge->dev_private_data = &intel_private;
2116
2117         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
2118                 intel_agp_chipsets[i].name);
2119
2120         /*
2121         * The following fixes the case where the BIOS has "forgotten" to
2122         * provide an address range for the GART.
2123         * 20030610 - hamish@zot.org
2124         */
2125         r = &pdev->resource[0];
2126         if (!r->start && r->end) {
2127                 if (pci_assign_resource(pdev, 0)) {
2128                         printk(KERN_ERR PFX "could not assign resource 0\n");
2129                         agp_put_bridge(bridge);
2130                         return -ENODEV;
2131                 }
2132         }
2133
2134         /*
2135         * If the device has not been properly setup, the following will catch
2136         * the problem and should stop the system from crashing.
2137         * 20030610 - hamish@zot.org
2138         */
2139         if (pci_enable_device(pdev)) {
2140                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
2141                 agp_put_bridge(bridge);
2142                 return -ENODEV;
2143         }
2144
2145         /* Fill in the mode register */
2146         if (cap_ptr) {
2147                 pci_read_config_dword(pdev,
2148                                 bridge->capndx+PCI_AGP_STATUS,
2149                                 &bridge->mode);
2150         }
2151
2152         pci_set_drvdata(pdev, bridge);
2153         return agp_add_bridge(bridge);
2154 }
2155
2156 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2157 {
2158         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2159
2160         agp_remove_bridge(bridge);
2161
2162         if (intel_private.pcidev)
2163                 pci_dev_put(intel_private.pcidev);
2164
2165         agp_put_bridge(bridge);
2166 }
2167
2168 #ifdef CONFIG_PM
2169 static int agp_intel_resume(struct pci_dev *pdev)
2170 {
2171         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2172
2173         pci_restore_state(pdev);
2174
2175         /* We should restore our graphics device's config space,
2176          * as host bridge (00:00) resumes before graphics device (02:00),
2177          * then our access to its pci space can work right.
2178          */
2179         if (intel_private.pcidev)
2180                 pci_restore_state(intel_private.pcidev);
2181
2182         if (bridge->driver == &intel_generic_driver)
2183                 intel_configure();
2184         else if (bridge->driver == &intel_850_driver)
2185                 intel_850_configure();
2186         else if (bridge->driver == &intel_845_driver)
2187                 intel_845_configure();
2188         else if (bridge->driver == &intel_830mp_driver)
2189                 intel_830mp_configure();
2190         else if (bridge->driver == &intel_915_driver)
2191                 intel_i915_configure();
2192         else if (bridge->driver == &intel_830_driver)
2193                 intel_i830_configure();
2194         else if (bridge->driver == &intel_810_driver)
2195                 intel_i810_configure();
2196         else if (bridge->driver == &intel_i965_driver)
2197                 intel_i915_configure();
2198
2199         return 0;
2200 }
2201 #endif
2202
2203 static struct pci_device_id agp_intel_pci_table[] = {
2204 #define ID(x)                                           \
2205         {                                               \
2206         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2207         .class_mask     = ~0,                           \
2208         .vendor         = PCI_VENDOR_ID_INTEL,          \
2209         .device         = x,                            \
2210         .subvendor      = PCI_ANY_ID,                   \
2211         .subdevice      = PCI_ANY_ID,                   \
2212         }
2213         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2214         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2215         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2216         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2217         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2218         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2219         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2220         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2221         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2222         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2223         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2224         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2225         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2226         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2227         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2228         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2229         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2230         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2231         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2232         ID(PCI_DEVICE_ID_INTEL_7505_0),
2233         ID(PCI_DEVICE_ID_INTEL_7205_0),
2234         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2235         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2236         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2237         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2238         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2239         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2240         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2241         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2242         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2243         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2244         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2245         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2246         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2247         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2248         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2249         ID(PCI_DEVICE_ID_INTEL_IGD_HB),
2250         { }
2251 };
2252
2253 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2254
2255 static struct pci_driver agp_intel_pci_driver = {
2256         .name           = "agpgart-intel",
2257         .id_table       = agp_intel_pci_table,
2258         .probe          = agp_intel_probe,
2259         .remove         = __devexit_p(agp_intel_remove),
2260 #ifdef CONFIG_PM
2261         .resume         = agp_intel_resume,
2262 #endif
2263 };
2264
2265 static int __init agp_intel_init(void)
2266 {
2267         if (agp_off)
2268                 return -EINVAL;
2269         return pci_register_driver(&agp_intel_pci_driver);
2270 }
2271
2272 static void __exit agp_intel_cleanup(void)
2273 {
2274         pci_unregister_driver(&agp_intel_pci_driver);
2275 }
2276
2277 module_init(agp_intel_init);
2278 module_exit(agp_intel_cleanup);
2279
2280 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2281 MODULE_LICENSE("GPL and additional rights");