Pileus Git - ~andy/linux/blob - drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  14 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  17 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
  18 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
  19 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  20 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  21 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  22 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  23 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  24 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  25 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  26 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  27 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  28 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  29 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  30 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  31 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  32 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  33 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  34 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  35
  36 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  37                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
  38                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  39                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  40                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  41                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  42
  43 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  44                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  45                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
  46
  47 extern int agp_memory_reserved;
  48
  49
  50 /* Intel 815 register */
  51 #define INTEL_815_APCONT        0x51
  52 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
  53
  54 /* Intel i820 registers */
  55 #define INTEL_I820_RDCR         0x51
  56 #define INTEL_I820_ERRSTS       0xc8
  57
  58 /* Intel i840 registers */
  59 #define INTEL_I840_MCHCFG       0x50
  60 #define INTEL_I840_ERRSTS       0xc8
  61
  62 /* Intel i850 registers */
  63 #define INTEL_I850_MCHCFG       0x50
  64 #define INTEL_I850_ERRSTS       0xc8
  65
  66 /* intel 915G registers */
  67 #define I915_GMADDR     0x18
  68 #define I915_MMADDR     0x10
  69 #define I915_PTEADDR    0x1C
  70 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
  71 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
  72 #define G33_GMCH_GMS_STOLEN_128M       (0x8 << 4)
  73 #define G33_GMCH_GMS_STOLEN_256M       (0x9 << 4)
  74 #define I915_IFPADDR    0x60
  75
  76 /* Intel 965G registers */
  77 #define I965_MSAC 0x62
  78 #define I965_IFPADDR    0x70
  79
  80 /* Intel 7505 registers */
  81 #define INTEL_I7505_APSIZE      0x74
  82 #define INTEL_I7505_NCAPID      0x60
  83 #define INTEL_I7505_NISTAT      0x6c
  84 #define INTEL_I7505_ATTBASE     0x78
  85 #define INTEL_I7505_ERRSTS      0x42
  86 #define INTEL_I7505_AGPCTRL     0x70
  87 #define INTEL_I7505_MCHCFG      0x50
  88
  89 static const struct aper_size_info_fixed intel_i810_sizes[] =
  90 {
  91         {64, 16384, 4},
  92         /* The 32M mode still requires a 64k gatt */
  93         {32, 8192, 4}
  94 };
  95
  96 #define AGP_DCACHE_MEMORY       1
  97 #define AGP_PHYS_MEMORY         2
  98 #define INTEL_AGP_CACHED_MEMORY 3
  99
 100 static struct gatt_mask intel_i810_masks[] =
 101 {
 102         {.mask = I810_PTE_VALID, .type = 0},
 103         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 104         {.mask = I810_PTE_VALID, .type = 0},
 105         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 106          .type = INTEL_AGP_CACHED_MEMORY}
 107 };
 108
 109 static struct _intel_private {
 110         struct pci_dev *pcidev; /* device one */
 111         u8 __iomem *registers;
 112         u32 __iomem *gtt;               /* I915G */
 113         int num_dcache_entries;
 114         /* gtt_entries is the number of gtt entries that are already mapped
 115          * to stolen memory.  Stolen memory is larger than the memory mapped
 116          * through gtt_entries, as it includes some reserved space for the BIOS
 117          * popup and for the GTT.
 118          */
 119         int gtt_entries;                        /* i830+ */
 120         union {
 121                 void __iomem *i9xx_flush_page;
 122                 void *i8xx_flush_page;
 123         };
 124         struct page *i8xx_page;
 125         struct resource ifp_resource;
 126 } intel_private;
 127
 128 static int intel_i810_fetch_size(void)
 129 {
 130         u32 smram_miscc;
 131         struct aper_size_info_fixed *values;
 132
 133         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 134         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 135
 136         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 137                 printk(KERN_WARNING PFX "i810 is disabled\n");
 138                 return 0;
 139         }
 140         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 141                 agp_bridge->previous_size =
 142                         agp_bridge->current_size = (void *) (values + 1);
 143                 agp_bridge->aperture_size_idx = 1;
 144                 return values[1].size;
 145         } else {
 146                 agp_bridge->previous_size =
 147                         agp_bridge->current_size = (void *) (values);
 148                 agp_bridge->aperture_size_idx = 0;
 149                 return values[0].size;
 150         }
 151
 152         return 0;
 153 }
 154
 155 static int intel_i810_configure(void)
 156 {
 157         struct aper_size_info_fixed *current_size;
 158         u32 temp;
 159         int i;
 160
 161         current_size = A_SIZE_FIX(agp_bridge->current_size);
 162
 163         if (!intel_private.registers) {
 164                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 165                 temp &= 0xfff80000;
 166
 167                 intel_private.registers = ioremap(temp, 128 * 4096);
 168                 if (!intel_private.registers) {
 169                         printk(KERN_ERR PFX "Unable to remap memory.\n");
 170                         return -ENOMEM;
 171                 }
 172         }
 173
 174         if ((readl(intel_private.registers+I810_DRAM_CTL)
 175                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 176                 /* This will need to be dynamically assigned */
 177                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
 178                 intel_private.num_dcache_entries = 1024;
 179         }
 180         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 181         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 182         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 183         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 184
 185         if (agp_bridge->driver->needs_scratch_page) {
 186                 for (i = 0; i < current_size->num_entries; i++) {
 187                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 188                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI posting. */
 189                 }
 190         }
 191         global_cache_flush();
 192         return 0;
 193 }
 194
 195 static void intel_i810_cleanup(void)
 196 {
 197         writel(0, intel_private.registers+I810_PGETBL_CTL);
 198         readl(intel_private.registers); /* PCI Posting. */
 199         iounmap(intel_private.registers);
 200 }
 201
 202 static void intel_i810_tlbflush(struct agp_memory *mem)
 203 {
 204         return;
 205 }
 206
 207 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 208 {
 209         return;
 210 }
 211
 212 /* Exists to support ARGB cursors */
 213 static void *i8xx_alloc_pages(void)
 214 {
 215         struct page * page;
 216
 217         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 218         if (page == NULL)
 219                 return NULL;
 220
 221         if (set_pages_uc(page, 4) < 0) {
 222                 set_pages_wb(page, 4);
 223                 __free_pages(page, 2);
 224                 return NULL;
 225         }
 226         get_page(page);
 227         atomic_inc(&agp_bridge->current_memory_agp);
 228         return page_address(page);
 229 }
 230
 231 static void i8xx_destroy_pages(void *addr)
 232 {
 233         struct page *page;
 234
 235         if (addr == NULL)
 236                 return;
 237
 238         page = virt_to_page(addr);
 239         set_pages_wb(page, 4);
 240         put_page(page);
 241         __free_pages(page, 2);
 242         atomic_dec(&agp_bridge->current_memory_agp);
 243 }
 244
 245 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 246                                         int type)
 247 {
 248         if (type < AGP_USER_TYPES)
 249                 return type;
 250         else if (type == AGP_USER_CACHED_MEMORY)
 251                 return INTEL_AGP_CACHED_MEMORY;
 252         else
 253                 return 0;
 254 }
 255
 256 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 257                                 int type)
 258 {
 259         int i, j, num_entries;
 260         void *temp;
 261         int ret = -EINVAL;
 262         int mask_type;
 263
 264         if (mem->page_count == 0)
 265                 goto out;
 266
 267         temp = agp_bridge->current_size;
 268         num_entries = A_SIZE_FIX(temp)->num_entries;
 269
 270         if ((pg_start + mem->page_count) > num_entries)
 271                 goto out_err;
 272
 273
 274         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 275                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 276                         ret = -EBUSY;
 277                         goto out_err;
 278                 }
 279         }
 280
 281         if (type != mem->type)
 282                 goto out_err;
 283
 284         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 285
 286         switch (mask_type) {
 287         case AGP_DCACHE_MEMORY:
 288                 if (!mem->is_flushed)
 289                         global_cache_flush();
 290                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 291                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 292                                intel_private.registers+I810_PTE_BASE+(i*4));
 293                 }
 294                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 295                 break;
 296         case AGP_PHYS_MEMORY:
 297         case AGP_NORMAL_MEMORY:
 298                 if (!mem->is_flushed)
 299                         global_cache_flush();
 300                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 301                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 302                                                                mem->memory[i],
 303                                                                mask_type),
 304                                intel_private.registers+I810_PTE_BASE+(j*4));
 305                 }
 306                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 307                 break;
 308         default:
 309                 goto out_err;
 310         }
 311
 312         agp_bridge->driver->tlb_flush(mem);
 313 out:
 314         ret = 0;
 315 out_err:
 316         mem->is_flushed = 1;
 317         return ret;
 318 }
 319
 320 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 321                                 int type)
 322 {
 323         int i;
 324
 325         if (mem->page_count == 0)
 326                 return 0;
 327
 328         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 329                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 330         }
 331         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 332
 333         agp_bridge->driver->tlb_flush(mem);
 334         return 0;
 335 }
 336
 337 /*
 338  * The i810/i830 requires a physical address to program its mouse
 339  * pointer into hardware.
 340  * However the Xserver still writes to it through the agp aperture.
 341  */
 342 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 343 {
 344         struct agp_memory *new;
 345         void *addr;
 346
 347         switch (pg_count) {
 348         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
 349                 break;
 350         case 4:
 351                 /* kludge to get 4 physical pages for ARGB cursor */
 352                 addr = i8xx_alloc_pages();
 353                 break;
 354         default:
 355                 return NULL;
 356         }
 357
 358         if (addr == NULL)
 359                 return NULL;
 360
 361         new = agp_create_memory(pg_count);
 362         if (new == NULL)
 363                 return NULL;
 364
 365         new->memory[0] = virt_to_gart(addr);
 366         if (pg_count == 4) {
 367                 /* kludge to get 4 physical pages for ARGB cursor */
 368                 new->memory[1] = new->memory[0] + PAGE_SIZE;
 369                 new->memory[2] = new->memory[1] + PAGE_SIZE;
 370                 new->memory[3] = new->memory[2] + PAGE_SIZE;
 371         }
 372         new->page_count = pg_count;
 373         new->num_scratch_pages = pg_count;
 374         new->type = AGP_PHYS_MEMORY;
 375         new->physical = new->memory[0];
 376         return new;
 377 }
 378
 379 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 380 {
 381         struct agp_memory *new;
 382
 383         if (type == AGP_DCACHE_MEMORY) {
 384                 if (pg_count != intel_private.num_dcache_entries)
 385                         return NULL;
 386
 387                 new = agp_create_memory(1);
 388                 if (new == NULL)
 389                         return NULL;
 390
 391                 new->type = AGP_DCACHE_MEMORY;
 392                 new->page_count = pg_count;
 393                 new->num_scratch_pages = 0;
 394                 agp_free_page_array(new);
 395                 return new;
 396         }
 397         if (type == AGP_PHYS_MEMORY)
 398                 return alloc_agpphysmem_i8xx(pg_count, type);
 399         return NULL;
 400 }
 401
 402 static void intel_i810_free_by_type(struct agp_memory *curr)
 403 {
 404         agp_free_key(curr->key);
 405         if (curr->type == AGP_PHYS_MEMORY) {
 406                 if (curr->page_count == 4)
 407                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
 408                 else {
 409                         agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
 410                                                              AGP_PAGE_DESTROY_UNMAP);
 411                         agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
 412                                                              AGP_PAGE_DESTROY_FREE);
 413                 }
 414                 agp_free_page_array(curr);
 415         }
 416         kfree(curr);
 417 }
 418
 419 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 420         unsigned long addr, int type)
 421 {
 422         /* Type checking must be done elsewhere */
 423         return addr | bridge->driver->masks[type].mask;
 424 }
 425
 426 static struct aper_size_info_fixed intel_i830_sizes[] =
 427 {
 428         {128, 32768, 5},
 429         /* The 64M mode still requires a 128k gatt */
 430         {64, 16384, 5},
 431         {256, 65536, 6},
 432         {512, 131072, 7},
 433 };
 434
 435 static void intel_i830_init_gtt_entries(void)
 436 {
 437         u16 gmch_ctrl;
 438         int gtt_entries;
 439         u8 rdct;
 440         int local = 0;
 441         static const int ddt[4] = { 0, 16, 32, 64 };
 442         int size; /* reserved space (in kb) at the top of stolen memory */
 443
 444         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 445
 446         if (IS_I965) {
 447                 u32 pgetbl_ctl;
 448                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 449
 450                 /* The 965 has a field telling us the size of the GTT,
 451                  * which may be larger than what is necessary to map the
 452                  * aperture.
 453                  */
 454                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 455                 case I965_PGETBL_SIZE_128KB:
 456                         size = 128;
 457                         break;
 458                 case I965_PGETBL_SIZE_256KB:
 459                         size = 256;
 460                         break;
 461                 case I965_PGETBL_SIZE_512KB:
 462                         size = 512;
 463                         break;
 464                 default:
 465                         printk(KERN_INFO PFX "Unknown page table size, "
 466                                "assuming 512KB\n");
 467                         size = 512;
 468                 }
 469                 size += 4; /* add in BIOS popup space */
 470         } else if (IS_G33) {
 471         /* G33's GTT size defined in gmch_ctrl */
 472                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 473                 case G33_PGETBL_SIZE_1M:
 474                         size = 1024;
 475                         break;
 476                 case G33_PGETBL_SIZE_2M:
 477                         size = 2048;
 478                         break;
 479                 default:
 480                         printk(KERN_INFO PFX "Unknown page table size 0x%x, "
 481                                 "assuming 512KB\n",
 482                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 483                         size = 512;
 484                 }
 485                 size += 4;
 486         } else {
 487                 /* On previous hardware, the GTT size was just what was
 488                  * required to map the aperture.
 489                  */
 490                 size = agp_bridge->driver->fetch_size() + 4;
 491         }
 492
 493         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 494             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 495                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 496                 case I830_GMCH_GMS_STOLEN_512:
 497                         gtt_entries = KB(512) - KB(size);
 498                         break;
 499                 case I830_GMCH_GMS_STOLEN_1024:
 500                         gtt_entries = MB(1) - KB(size);
 501                         break;
 502                 case I830_GMCH_GMS_STOLEN_8192:
 503                         gtt_entries = MB(8) - KB(size);
 504                         break;
 505                 case I830_GMCH_GMS_LOCAL:
 506                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 507                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 508                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 509                         local = 1;
 510                         break;
 511                 default:
 512                         gtt_entries = 0;
 513                         break;
 514                 }
 515         } else {
 516                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 517                 case I855_GMCH_GMS_STOLEN_1M:
 518                         gtt_entries = MB(1) - KB(size);
 519                         break;
 520                 case I855_GMCH_GMS_STOLEN_4M:
 521                         gtt_entries = MB(4) - KB(size);
 522                         break;
 523                 case I855_GMCH_GMS_STOLEN_8M:
 524                         gtt_entries = MB(8) - KB(size);
 525                         break;
 526                 case I855_GMCH_GMS_STOLEN_16M:
 527                         gtt_entries = MB(16) - KB(size);
 528                         break;
 529                 case I855_GMCH_GMS_STOLEN_32M:
 530                         gtt_entries = MB(32) - KB(size);
 531                         break;
 532                 case I915_GMCH_GMS_STOLEN_48M:
 533                         /* Check it's really I915G */
 534                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
 535                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 536                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 537                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 538                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
 539                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
 540                             IS_I965 || IS_G33)
 541                                 gtt_entries = MB(48) - KB(size);
 542                         else
 543                                 gtt_entries = 0;
 544                         break;
 545                 case I915_GMCH_GMS_STOLEN_64M:
 546                         /* Check it's really I915G */
 547                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
 548                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 549                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 550                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 551                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
 552                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
 553                             IS_I965 || IS_G33)
 554                                 gtt_entries = MB(64) - KB(size);
 555                         else
 556                                 gtt_entries = 0;
 557                         break;
 558                 case G33_GMCH_GMS_STOLEN_128M:
 559                         if (IS_G33)
 560                                 gtt_entries = MB(128) - KB(size);
 561                         else
 562                                 gtt_entries = 0;
 563                         break;
 564                 case G33_GMCH_GMS_STOLEN_256M:
 565                         if (IS_G33)
 566                                 gtt_entries = MB(256) - KB(size);
 567                         else
 568                                 gtt_entries = 0;
 569                         break;
 570                 default:
 571                         gtt_entries = 0;
 572                         break;
 573                 }
 574         }
 575         if (gtt_entries > 0)
 576                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
 577                        gtt_entries / KB(1), local ? "local" : "stolen");
 578         else
 579                 printk(KERN_INFO PFX
 580                        "No pre-allocated video memory detected.\n");
 581         gtt_entries /= KB(4);
 582
 583         intel_private.gtt_entries = gtt_entries;
 584 }
 585
 586 static void intel_i830_fini_flush(void)
 587 {
 588         kunmap(intel_private.i8xx_page);
 589         intel_private.i8xx_flush_page = NULL;
 590         unmap_page_from_agp(intel_private.i8xx_page);
 591         flush_agp_mappings();
 592
 593         __free_page(intel_private.i8xx_page);
 594 }
 595
 596 static void intel_i830_setup_flush(void)
 597 {
 598
 599         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 600         if (!intel_private.i8xx_page) {
 601                 return;
 602         }
 603
 604         /* make page uncached */
 605         map_page_into_agp(intel_private.i8xx_page);
 606         flush_agp_mappings();
 607
 608         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 609         if (!intel_private.i8xx_flush_page)
 610                 intel_i830_fini_flush();
 611 }
 612
 613 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 614 {
 615         unsigned int *pg = intel_private.i8xx_flush_page;
 616         int i;
 617
 618         for (i = 0; i < 256; i+=2)
 619                 *(pg + i) = i;
 620
 621         wmb();
 622 }
 623
 624 /* The intel i830 automatically initializes the agp aperture during POST.
 625  * Use the memory already set aside for in the GTT.
 626  */
 627 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 628 {
 629         int page_order;
 630         struct aper_size_info_fixed *size;
 631         int num_entries;
 632         u32 temp;
 633
 634         size = agp_bridge->current_size;
 635         page_order = size->page_order;
 636         num_entries = size->num_entries;
 637         agp_bridge->gatt_table_real = NULL;
 638
 639         pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
 640         temp &= 0xfff80000;
 641
 642         intel_private.registers = ioremap(temp,128 * 4096);
 643         if (!intel_private.registers)
 644                 return -ENOMEM;
 645
 646         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 647         global_cache_flush();   /* FIXME: ?? */
 648
 649         /* we have to call this as early as possible after the MMIO base address is known */
 650         intel_i830_init_gtt_entries();
 651
 652         agp_bridge->gatt_table = NULL;
 653
 654         agp_bridge->gatt_bus_addr = temp;
 655
 656         return 0;
 657 }
 658
 659 /* Return the gatt table to a sane state. Use the top of stolen
 660  * memory for the GTT.
 661  */
 662 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 663 {
 664         return 0;
 665 }
 666
 667 static int intel_i830_fetch_size(void)
 668 {
 669         u16 gmch_ctrl;
 670         struct aper_size_info_fixed *values;
 671
 672         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 673
 674         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 675             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 676                 /* 855GM/852GM/865G has 128MB aperture size */
 677                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 678                 agp_bridge->aperture_size_idx = 0;
 679                 return values[0].size;
 680         }
 681
 682         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 683
 684         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 685                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 686                 agp_bridge->aperture_size_idx = 0;
 687                 return values[0].size;
 688         } else {
 689                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 690                 agp_bridge->aperture_size_idx = 1;
 691                 return values[1].size;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int intel_i830_configure(void)
 698 {
 699         struct aper_size_info_fixed *current_size;
 700         u32 temp;
 701         u16 gmch_ctrl;
 702         int i;
 703
 704         current_size = A_SIZE_FIX(agp_bridge->current_size);
 705
 706         pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
 707         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 708
 709         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 710         gmch_ctrl |= I830_GMCH_ENABLED;
 711         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 712
 713         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 714         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 715
 716         if (agp_bridge->driver->needs_scratch_page) {
 717                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 718                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 719                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI Posting. */
 720                 }
 721         }
 722
 723         global_cache_flush();
 724
 725         intel_i830_setup_flush();
 726         return 0;
 727 }
 728
 729 static void intel_i830_cleanup(void)
 730 {
 731         iounmap(intel_private.registers);
 732 }
 733
 734 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
 735 {
 736         int i,j,num_entries;
 737         void *temp;
 738         int ret = -EINVAL;
 739         int mask_type;
 740
 741         if (mem->page_count == 0)
 742                 goto out;
 743
 744         temp = agp_bridge->current_size;
 745         num_entries = A_SIZE_FIX(temp)->num_entries;
 746
 747         if (pg_start < intel_private.gtt_entries) {
 748                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 749                                 pg_start,intel_private.gtt_entries);
 750
 751                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 752                 goto out_err;
 753         }
 754
 755         if ((pg_start + mem->page_count) > num_entries)
 756                 goto out_err;
 757
 758         /* The i830 can't check the GTT for entries since its read only,
 759          * depend on the caller to make the correct offset decisions.
 760          */
 761
 762         if (type != mem->type)
 763                 goto out_err;
 764
 765         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 766
 767         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 768             mask_type != INTEL_AGP_CACHED_MEMORY)
 769                 goto out_err;
 770
 771         if (!mem->is_flushed)
 772                 global_cache_flush();
 773
 774         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 775                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 776                                                        mem->memory[i], mask_type),
 777                        intel_private.registers+I810_PTE_BASE+(j*4));
 778         }
 779         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 780         agp_bridge->driver->tlb_flush(mem);
 781
 782 out:
 783         ret = 0;
 784 out_err:
 785         mem->is_flushed = 1;
 786         return ret;
 787 }
 788
 789 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
 790                                 int type)
 791 {
 792         int i;
 793
 794         if (mem->page_count == 0)
 795                 return 0;
 796
 797         if (pg_start < intel_private.gtt_entries) {
 798                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
 799                 return -EINVAL;
 800         }
 801
 802         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 803                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 804         }
 805         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 806
 807         agp_bridge->driver->tlb_flush(mem);
 808         return 0;
 809 }
 810
 811 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
 812 {
 813         if (type == AGP_PHYS_MEMORY)
 814                 return alloc_agpphysmem_i8xx(pg_count, type);
 815         /* always return NULL for other allocation types for now */
 816         return NULL;
 817 }
 818
 819 static int intel_alloc_chipset_flush_resource(void)
 820 {
 821         int ret;
 822         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
 823                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
 824                                      pcibios_align_resource, agp_bridge->dev);
 825
 826         return ret;
 827 }
 828
 829 static void intel_i915_setup_chipset_flush(void)
 830 {
 831         int ret;
 832         u32 temp;
 833
 834         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
 835         if (!(temp & 0x1)) {
 836                 intel_alloc_chipset_flush_resource();
 837
 838                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 839         } else {
 840                 temp &= ~1;
 841
 842                 intel_private.ifp_resource.start = temp;
 843                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
 844                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 845                 if (ret) {
 846                         intel_private.ifp_resource.start = 0;
 847                         printk("Failed inserting resource into tree\n");
 848                 }
 849         }
 850 }
 851
 852 static void intel_i965_g33_setup_chipset_flush(void)
 853 {
 854         u32 temp_hi, temp_lo;
 855         int ret;
 856
 857         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
 858         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
 859
 860         if (!(temp_lo & 0x1)) {
 861
 862                 intel_alloc_chipset_flush_resource();
 863
 864                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, (intel_private.ifp_resource.start >> 32));
 865                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 866         } else {
 867                 u64 l64;
 868
 869                 temp_lo &= ~0x1;
 870                 l64 = ((u64)temp_hi << 32) | temp_lo;
 871
 872                 intel_private.ifp_resource.start = l64;
 873                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
 874                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 875                 if (!ret) {
 876                         printk("Failed inserting resource into tree - continuing\n");
 877                 }
 878         }
 879 }
 880
 881 static void intel_i9xx_setup_flush(void)
 882 {
 883         /* setup a resource for this object */
 884         memset(&intel_private.ifp_resource, 0, sizeof(intel_private.ifp_resource));
 885
 886         intel_private.ifp_resource.name = "Intel Flush Page";
 887         intel_private.ifp_resource.flags = IORESOURCE_MEM;
 888
 889         /* Setup chipset flush for 915 */
 890         if (IS_I965 || IS_G33) {
 891                 intel_i965_g33_setup_chipset_flush();
 892         } else {
 893                 intel_i915_setup_chipset_flush();
 894         }
 895
 896         if (intel_private.ifp_resource.start) {
 897                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
 898                 if (!intel_private.i9xx_flush_page)
 899                         printk("unable to ioremap flush  page - no chipset flushing");
 900         }
 901 }
 902
 903 static int intel_i915_configure(void)
 904 {
 905         struct aper_size_info_fixed *current_size;
 906         u32 temp;
 907         u16 gmch_ctrl;
 908         int i;
 909
 910         current_size = A_SIZE_FIX(agp_bridge->current_size);
 911
 912         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
 913
 914         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 915
 916         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 917         gmch_ctrl |= I830_GMCH_ENABLED;
 918         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 919
 920         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 921         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 922
 923         if (agp_bridge->driver->needs_scratch_page) {
 924                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 925                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
 926                         readl(intel_private.gtt+i);     /* PCI Posting. */
 927                 }
 928         }
 929
 930         global_cache_flush();
 931
 932         intel_i9xx_setup_flush();
 933
 934         return 0;
 935 }
 936
 937 static void intel_i915_cleanup(void)
 938 {
 939         if (intel_private.i9xx_flush_page)
 940                 iounmap(intel_private.i9xx_flush_page);
 941         iounmap(intel_private.gtt);
 942         iounmap(intel_private.registers);
 943 }
 944
 945 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
 946 {
 947         if (intel_private.i9xx_flush_page)
 948                 writel(1, intel_private.i9xx_flush_page);
 949 }
 950
 951 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
 952                                 int type)
 953 {
 954         int i,j,num_entries;
 955         void *temp;
 956         int ret = -EINVAL;
 957         int mask_type;
 958
 959         if (mem->page_count == 0)
 960                 goto out;
 961
 962         temp = agp_bridge->current_size;
 963         num_entries = A_SIZE_FIX(temp)->num_entries;
 964
 965         if (pg_start < intel_private.gtt_entries) {
 966                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 967                                 pg_start,intel_private.gtt_entries);
 968
 969                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 970                 goto out_err;
 971         }
 972
 973         if ((pg_start + mem->page_count) > num_entries)
 974                 goto out_err;
 975
 976         /* The i915 can't check the GTT for entries since its read only,
 977          * depend on the caller to make the correct offset decisions.
 978          */
 979
 980         if (type != mem->type)
 981                 goto out_err;
 982
 983         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 984
 985         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 986             mask_type != INTEL_AGP_CACHED_MEMORY)
 987                 goto out_err;
 988
 989         if (!mem->is_flushed)
 990                 global_cache_flush();
 991
 992         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 993                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 994                         mem->memory[i], mask_type), intel_private.gtt+j);
 995         }
 996
 997         readl(intel_private.gtt+j-1);
 998         agp_bridge->driver->tlb_flush(mem);
 999
1000  out:
1001         ret = 0;
1002  out_err:
1003         mem->is_flushed = 1;
1004         return ret;
1005 }
1006
1007 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
1008                                 int type)
1009 {
1010         int i;
1011
1012         if (mem->page_count == 0)
1013                 return 0;
1014
1015         if (pg_start < intel_private.gtt_entries) {
1016                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
1017                 return -EINVAL;
1018         }
1019
1020         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1021                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1022         }
1023         readl(intel_private.gtt+i-1);
1024
1025         agp_bridge->driver->tlb_flush(mem);
1026         return 0;
1027 }
1028
1029 /* Return the aperture size by just checking the resource length.  The effect
1030  * described in the spec of the MSAC registers is just changing of the
1031  * resource size.
1032  */
1033 static int intel_i9xx_fetch_size(void)
1034 {
1035         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1036         int aper_size; /* size in megabytes */
1037         int i;
1038
1039         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1040
1041         for (i = 0; i < num_sizes; i++) {
1042                 if (aper_size == intel_i830_sizes[i].size) {
1043                         agp_bridge->current_size = intel_i830_sizes + i;
1044                         agp_bridge->previous_size = agp_bridge->current_size;
1045                         return aper_size;
1046                 }
1047         }
1048
1049         return 0;
1050 }
1051
1052 /* The intel i915 automatically initializes the agp aperture during POST.
1053  * Use the memory already set aside for in the GTT.
1054  */
1055 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1056 {
1057         int page_order;
1058         struct aper_size_info_fixed *size;
1059         int num_entries;
1060         u32 temp, temp2;
1061         int gtt_map_size = 256 * 1024;
1062
1063         size = agp_bridge->current_size;
1064         page_order = size->page_order;
1065         num_entries = size->num_entries;
1066         agp_bridge->gatt_table_real = NULL;
1067
1068         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1069         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
1070
1071         if (IS_G33)
1072             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1073         intel_private.gtt = ioremap(temp2, gtt_map_size);
1074         if (!intel_private.gtt)
1075                 return -ENOMEM;
1076
1077         temp &= 0xfff80000;
1078
1079         intel_private.registers = ioremap(temp,128 * 4096);
1080         if (!intel_private.registers) {
1081                 iounmap(intel_private.gtt);
1082                 return -ENOMEM;
1083         }
1084
1085         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1086         global_cache_flush();   /* FIXME: ? */
1087
1088         /* we have to call this as early as possible after the MMIO base address is known */
1089         intel_i830_init_gtt_entries();
1090
1091         agp_bridge->gatt_table = NULL;
1092
1093         agp_bridge->gatt_bus_addr = temp;
1094
1095         return 0;
1096 }
1097
1098 /*
1099  * The i965 supports 36-bit physical addresses, but to keep
1100  * the format of the GTT the same, the bits that don't fit
1101  * in a 32-bit word are shifted down to bits 4..7.
1102  *
1103  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1104  * is always zero on 32-bit architectures, so no need to make
1105  * this conditional.
1106  */
1107 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1108         unsigned long addr, int type)
1109 {
1110         /* Shift high bits down */
1111         addr |= (addr >> 28) & 0xf0;
1112
1113         /* Type checking must be done elsewhere */
1114         return addr | bridge->driver->masks[type].mask;
1115 }
1116
1117 /* The intel i965 automatically initializes the agp aperture during POST.
1118  * Use the memory already set aside for in the GTT.
1119  */
1120 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1121 {
1122        int page_order;
1123        struct aper_size_info_fixed *size;
1124        int num_entries;
1125        u32 temp;
1126
1127        size = agp_bridge->current_size;
1128        page_order = size->page_order;
1129        num_entries = size->num_entries;
1130        agp_bridge->gatt_table_real = NULL;
1131
1132        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1133
1134        temp &= 0xfff00000;
1135        intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
1136
1137         if (!intel_private.gtt)
1138                 return -ENOMEM;
1139
1140
1141        intel_private.registers = ioremap(temp,128 * 4096);
1142        if (!intel_private.registers) {
1143                 iounmap(intel_private.gtt);
1144                 return -ENOMEM;
1145         }
1146
1147        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1148        global_cache_flush();   /* FIXME: ? */
1149
1150        /* we have to call this as early as possible after the MMIO base address is known */
1151        intel_i830_init_gtt_entries();
1152
1153        agp_bridge->gatt_table = NULL;
1154
1155        agp_bridge->gatt_bus_addr = temp;
1156
1157        return 0;
1158 }
1159
1160
1161 static int intel_fetch_size(void)
1162 {
1163         int i;
1164         u16 temp;
1165         struct aper_size_info_16 *values;
1166
1167         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1168         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1169
1170         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1171                 if (temp == values[i].size_value) {
1172                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1173                         agp_bridge->aperture_size_idx = i;
1174                         return values[i].size;
1175                 }
1176         }
1177
1178         return 0;
1179 }
1180
1181 static int __intel_8xx_fetch_size(u8 temp)
1182 {
1183         int i;
1184         struct aper_size_info_8 *values;
1185
1186         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1187
1188         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1189                 if (temp == values[i].size_value) {
1190                         agp_bridge->previous_size =
1191                                 agp_bridge->current_size = (void *) (values + i);
1192                         agp_bridge->aperture_size_idx = i;
1193                         return values[i].size;
1194                 }
1195         }
1196         return 0;
1197 }
1198
1199 static int intel_8xx_fetch_size(void)
1200 {
1201         u8 temp;
1202
1203         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1204         return __intel_8xx_fetch_size(temp);
1205 }
1206
1207 static int intel_815_fetch_size(void)
1208 {
1209         u8 temp;
1210
1211         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1212          * one non-reserved bit, so mask the others out ... */
1213         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1214         temp &= (1 << 3);
1215
1216         return __intel_8xx_fetch_size(temp);
1217 }
1218
1219 static void intel_tlbflush(struct agp_memory *mem)
1220 {
1221         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1222         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1223 }
1224
1225
1226 static void intel_8xx_tlbflush(struct agp_memory *mem)
1227 {
1228         u32 temp;
1229         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1230         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1231         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1232         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1233 }
1234
1235
1236 static void intel_cleanup(void)
1237 {
1238         u16 temp;
1239         struct aper_size_info_16 *previous_size;
1240
1241         previous_size = A_SIZE_16(agp_bridge->previous_size);
1242         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1243         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1244         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1245 }
1246
1247
1248 static void intel_8xx_cleanup(void)
1249 {
1250         u16 temp;
1251         struct aper_size_info_8 *previous_size;
1252
1253         previous_size = A_SIZE_8(agp_bridge->previous_size);
1254         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1255         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1256         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1257 }
1258
1259
1260 static int intel_configure(void)
1261 {
1262         u32 temp;
1263         u16 temp2;
1264         struct aper_size_info_16 *current_size;
1265
1266         current_size = A_SIZE_16(agp_bridge->current_size);
1267
1268         /* aperture size */
1269         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1270
1271         /* address to map to */
1272         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1273         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1274
1275         /* attbase - aperture base */
1276         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1277
1278         /* agpctrl */
1279         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1280
1281         /* paccfg/nbxcfg */
1282         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1283         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1284                         (temp2 & ~(1 << 10)) | (1 << 9));
1285         /* clear any possible error conditions */
1286         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1287         return 0;
1288 }
1289
1290 static int intel_815_configure(void)
1291 {
1292         u32 temp, addr;
1293         u8 temp2;
1294         struct aper_size_info_8 *current_size;
1295
1296         /* attbase - aperture base */
1297         /* the Intel 815 chipset spec. says that bits 29-31 in the
1298         * ATTBASE register are reserved -> try not to write them */
1299         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1300                 printk (KERN_EMERG PFX "gatt bus addr too high");
1301                 return -EINVAL;
1302         }
1303
1304         current_size = A_SIZE_8(agp_bridge->current_size);
1305
1306         /* aperture size */
1307         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1308                         current_size->size_value);
1309
1310         /* address to map to */
1311         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1312         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1313
1314         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1315         addr &= INTEL_815_ATTBASE_MASK;
1316         addr |= agp_bridge->gatt_bus_addr;
1317         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1318
1319         /* agpctrl */
1320         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1321
1322         /* apcont */
1323         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1324         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1325
1326         /* clear any possible error conditions */
1327         /* Oddness : this chipset seems to have no ERRSTS register ! */
1328         return 0;
1329 }
1330
1331 static void intel_820_tlbflush(struct agp_memory *mem)
1332 {
1333         return;
1334 }
1335
1336 static void intel_820_cleanup(void)
1337 {
1338         u8 temp;
1339         struct aper_size_info_8 *previous_size;
1340
1341         previous_size = A_SIZE_8(agp_bridge->previous_size);
1342         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1343         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1344                         temp & ~(1 << 1));
1345         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1346                         previous_size->size_value);
1347 }
1348
1349
1350 static int intel_820_configure(void)
1351 {
1352         u32 temp;
1353         u8 temp2;
1354         struct aper_size_info_8 *current_size;
1355
1356         current_size = A_SIZE_8(agp_bridge->current_size);
1357
1358         /* aperture size */
1359         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1360
1361         /* address to map to */
1362         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1363         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1364
1365         /* attbase - aperture base */
1366         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1367
1368         /* agpctrl */
1369         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1370
1371         /* global enable aperture access */
1372         /* This flag is not accessed through MCHCFG register as in */
1373         /* i850 chipset. */
1374         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1375         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1376         /* clear any possible AGP-related error conditions */
1377         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1378         return 0;
1379 }
1380
1381 static int intel_840_configure(void)
1382 {
1383         u32 temp;
1384         u16 temp2;
1385         struct aper_size_info_8 *current_size;
1386
1387         current_size = A_SIZE_8(agp_bridge->current_size);
1388
1389         /* aperture size */
1390         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1391
1392         /* address to map to */
1393         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1394         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1395
1396         /* attbase - aperture base */
1397         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1398
1399         /* agpctrl */
1400         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1401
1402         /* mcgcfg */
1403         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1404         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1405         /* clear any possible error conditions */
1406         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1407         return 0;
1408 }
1409
1410 static int intel_845_configure(void)
1411 {
1412         u32 temp;
1413         u8 temp2;
1414         struct aper_size_info_8 *current_size;
1415
1416         current_size = A_SIZE_8(agp_bridge->current_size);
1417
1418         /* aperture size */
1419         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1420
1421         if (agp_bridge->apbase_config != 0) {
1422                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1423                                        agp_bridge->apbase_config);
1424         } else {
1425                 /* address to map to */
1426                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1427                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1428                 agp_bridge->apbase_config = temp;
1429         }
1430
1431         /* attbase - aperture base */
1432         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1433
1434         /* agpctrl */
1435         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1436
1437         /* agpm */
1438         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1439         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1440         /* clear any possible error conditions */
1441         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1442
1443         intel_i830_setup_flush();
1444         return 0;
1445 }
1446
1447 static int intel_850_configure(void)
1448 {
1449         u32 temp;
1450         u16 temp2;
1451         struct aper_size_info_8 *current_size;
1452
1453         current_size = A_SIZE_8(agp_bridge->current_size);
1454
1455         /* aperture size */
1456         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1457
1458         /* address to map to */
1459         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1460         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1461
1462         /* attbase - aperture base */
1463         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1464
1465         /* agpctrl */
1466         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1467
1468         /* mcgcfg */
1469         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1470         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1471         /* clear any possible AGP-related error conditions */
1472         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1473         return 0;
1474 }
1475
1476 static int intel_860_configure(void)
1477 {
1478         u32 temp;
1479         u16 temp2;
1480         struct aper_size_info_8 *current_size;
1481
1482         current_size = A_SIZE_8(agp_bridge->current_size);
1483
1484         /* aperture size */
1485         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1486
1487         /* address to map to */
1488         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1489         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1490
1491         /* attbase - aperture base */
1492         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1493
1494         /* agpctrl */
1495         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1496
1497         /* mcgcfg */
1498         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1499         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1500         /* clear any possible AGP-related error conditions */
1501         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1502         return 0;
1503 }
1504
1505 static int intel_830mp_configure(void)
1506 {
1507         u32 temp;
1508         u16 temp2;
1509         struct aper_size_info_8 *current_size;
1510
1511         current_size = A_SIZE_8(agp_bridge->current_size);
1512
1513         /* aperture size */
1514         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1515
1516         /* address to map to */
1517         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1518         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1519
1520         /* attbase - aperture base */
1521         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1522
1523         /* agpctrl */
1524         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1525
1526         /* gmch */
1527         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1528         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1529         /* clear any possible AGP-related error conditions */
1530         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1531         return 0;
1532 }
1533
1534 static int intel_7505_configure(void)
1535 {
1536         u32 temp;
1537         u16 temp2;
1538         struct aper_size_info_8 *current_size;
1539
1540         current_size = A_SIZE_8(agp_bridge->current_size);
1541
1542         /* aperture size */
1543         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1544
1545         /* address to map to */
1546         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1547         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1548
1549         /* attbase - aperture base */
1550         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1551
1552         /* agpctrl */
1553         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1554
1555         /* mchcfg */
1556         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1557         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1558
1559         return 0;
1560 }
1561
1562 /* Setup function */
1563 static const struct gatt_mask intel_generic_masks[] =
1564 {
1565         {.mask = 0x00000017, .type = 0}
1566 };
1567
1568 static const struct aper_size_info_8 intel_815_sizes[2] =
1569 {
1570         {64, 16384, 4, 0},
1571         {32, 8192, 3, 8},
1572 };
1573
1574 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1575 {
1576         {256, 65536, 6, 0},
1577         {128, 32768, 5, 32},
1578         {64, 16384, 4, 48},
1579         {32, 8192, 3, 56},
1580         {16, 4096, 2, 60},
1581         {8, 2048, 1, 62},
1582         {4, 1024, 0, 63}
1583 };
1584
1585 static const struct aper_size_info_16 intel_generic_sizes[7] =
1586 {
1587         {256, 65536, 6, 0},
1588         {128, 32768, 5, 32},
1589         {64, 16384, 4, 48},
1590         {32, 8192, 3, 56},
1591         {16, 4096, 2, 60},
1592         {8, 2048, 1, 62},
1593         {4, 1024, 0, 63}
1594 };
1595
1596 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1597 {
1598         {256, 65536, 6, 0},
1599         {128, 32768, 5, 32},
1600         {64, 16384, 4, 48},
1601         {32, 8192, 3, 56}
1602 };
1603
1604 static const struct agp_bridge_driver intel_generic_driver = {
1605         .owner                  = THIS_MODULE,
1606         .aperture_sizes         = intel_generic_sizes,
1607         .size_type              = U16_APER_SIZE,
1608         .num_aperture_sizes     = 7,
1609         .configure              = intel_configure,
1610         .fetch_size             = intel_fetch_size,
1611         .cleanup                = intel_cleanup,
1612         .tlb_flush              = intel_tlbflush,
1613         .mask_memory            = agp_generic_mask_memory,
1614         .masks                  = intel_generic_masks,
1615         .agp_enable             = agp_generic_enable,
1616         .cache_flush            = global_cache_flush,
1617         .create_gatt_table      = agp_generic_create_gatt_table,
1618         .free_gatt_table        = agp_generic_free_gatt_table,
1619         .insert_memory          = agp_generic_insert_memory,
1620         .remove_memory          = agp_generic_remove_memory,
1621         .alloc_by_type          = agp_generic_alloc_by_type,
1622         .free_by_type           = agp_generic_free_by_type,
1623         .agp_alloc_page         = agp_generic_alloc_page,
1624         .agp_destroy_page       = agp_generic_destroy_page,
1625         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1626 };
1627
1628 static const struct agp_bridge_driver intel_810_driver = {
1629         .owner                  = THIS_MODULE,
1630         .aperture_sizes         = intel_i810_sizes,
1631         .size_type              = FIXED_APER_SIZE,
1632         .num_aperture_sizes     = 2,
1633         .needs_scratch_page     = TRUE,
1634         .configure              = intel_i810_configure,
1635         .fetch_size             = intel_i810_fetch_size,
1636         .cleanup                = intel_i810_cleanup,
1637         .tlb_flush              = intel_i810_tlbflush,
1638         .mask_memory            = intel_i810_mask_memory,
1639         .masks                  = intel_i810_masks,
1640         .agp_enable             = intel_i810_agp_enable,
1641         .cache_flush            = global_cache_flush,
1642         .create_gatt_table      = agp_generic_create_gatt_table,
1643         .free_gatt_table        = agp_generic_free_gatt_table,
1644         .insert_memory          = intel_i810_insert_entries,
1645         .remove_memory          = intel_i810_remove_entries,
1646         .alloc_by_type          = intel_i810_alloc_by_type,
1647         .free_by_type           = intel_i810_free_by_type,
1648         .agp_alloc_page         = agp_generic_alloc_page,
1649         .agp_destroy_page       = agp_generic_destroy_page,
1650         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1651 };
1652
1653 static const struct agp_bridge_driver intel_815_driver = {
1654         .owner                  = THIS_MODULE,
1655         .aperture_sizes         = intel_815_sizes,
1656         .size_type              = U8_APER_SIZE,
1657         .num_aperture_sizes     = 2,
1658         .configure              = intel_815_configure,
1659         .fetch_size             = intel_815_fetch_size,
1660         .cleanup                = intel_8xx_cleanup,
1661         .tlb_flush              = intel_8xx_tlbflush,
1662         .mask_memory            = agp_generic_mask_memory,
1663         .masks                  = intel_generic_masks,
1664         .agp_enable             = agp_generic_enable,
1665         .cache_flush            = global_cache_flush,
1666         .create_gatt_table      = agp_generic_create_gatt_table,
1667         .free_gatt_table        = agp_generic_free_gatt_table,
1668         .insert_memory          = agp_generic_insert_memory,
1669         .remove_memory          = agp_generic_remove_memory,
1670         .alloc_by_type          = agp_generic_alloc_by_type,
1671         .free_by_type           = agp_generic_free_by_type,
1672         .agp_alloc_page         = agp_generic_alloc_page,
1673         .agp_destroy_page       = agp_generic_destroy_page,
1674         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1675 };
1676
1677 static const struct agp_bridge_driver intel_830_driver = {
1678         .owner                  = THIS_MODULE,
1679         .aperture_sizes         = intel_i830_sizes,
1680         .size_type              = FIXED_APER_SIZE,
1681         .num_aperture_sizes     = 4,
1682         .needs_scratch_page     = TRUE,
1683         .configure              = intel_i830_configure,
1684         .fetch_size             = intel_i830_fetch_size,
1685         .cleanup                = intel_i830_cleanup,
1686         .tlb_flush              = intel_i810_tlbflush,
1687         .mask_memory            = intel_i810_mask_memory,
1688         .masks                  = intel_i810_masks,
1689         .agp_enable             = intel_i810_agp_enable,
1690         .cache_flush            = global_cache_flush,
1691         .create_gatt_table      = intel_i830_create_gatt_table,
1692         .free_gatt_table        = intel_i830_free_gatt_table,
1693         .insert_memory          = intel_i830_insert_entries,
1694         .remove_memory          = intel_i830_remove_entries,
1695         .alloc_by_type          = intel_i830_alloc_by_type,
1696         .free_by_type           = intel_i810_free_by_type,
1697         .agp_alloc_page         = agp_generic_alloc_page,
1698         .agp_destroy_page       = agp_generic_destroy_page,
1699         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1700         .chipset_flush          = intel_i830_chipset_flush,
1701 };
1702
1703 static const struct agp_bridge_driver intel_820_driver = {
1704         .owner                  = THIS_MODULE,
1705         .aperture_sizes         = intel_8xx_sizes,
1706         .size_type              = U8_APER_SIZE,
1707         .num_aperture_sizes     = 7,
1708         .configure              = intel_820_configure,
1709         .fetch_size             = intel_8xx_fetch_size,
1710         .cleanup                = intel_820_cleanup,
1711         .tlb_flush              = intel_820_tlbflush,
1712         .mask_memory            = agp_generic_mask_memory,
1713         .masks                  = intel_generic_masks,
1714         .agp_enable             = agp_generic_enable,
1715         .cache_flush            = global_cache_flush,
1716         .create_gatt_table      = agp_generic_create_gatt_table,
1717         .free_gatt_table        = agp_generic_free_gatt_table,
1718         .insert_memory          = agp_generic_insert_memory,
1719         .remove_memory          = agp_generic_remove_memory,
1720         .alloc_by_type          = agp_generic_alloc_by_type,
1721         .free_by_type           = agp_generic_free_by_type,
1722         .agp_alloc_page         = agp_generic_alloc_page,
1723         .agp_destroy_page       = agp_generic_destroy_page,
1724         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1725 };
1726
1727 static const struct agp_bridge_driver intel_830mp_driver = {
1728         .owner                  = THIS_MODULE,
1729         .aperture_sizes         = intel_830mp_sizes,
1730         .size_type              = U8_APER_SIZE,
1731         .num_aperture_sizes     = 4,
1732         .configure              = intel_830mp_configure,
1733         .fetch_size             = intel_8xx_fetch_size,
1734         .cleanup                = intel_8xx_cleanup,
1735         .tlb_flush              = intel_8xx_tlbflush,
1736         .mask_memory            = agp_generic_mask_memory,
1737         .masks                  = intel_generic_masks,
1738         .agp_enable             = agp_generic_enable,
1739         .cache_flush            = global_cache_flush,
1740         .create_gatt_table      = agp_generic_create_gatt_table,
1741         .free_gatt_table        = agp_generic_free_gatt_table,
1742         .insert_memory          = agp_generic_insert_memory,
1743         .remove_memory          = agp_generic_remove_memory,
1744         .alloc_by_type          = agp_generic_alloc_by_type,
1745         .free_by_type           = agp_generic_free_by_type,
1746         .agp_alloc_page         = agp_generic_alloc_page,
1747         .agp_destroy_page       = agp_generic_destroy_page,
1748         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1749 };
1750
1751 static const struct agp_bridge_driver intel_840_driver = {
1752         .owner                  = THIS_MODULE,
1753         .aperture_sizes         = intel_8xx_sizes,
1754         .size_type              = U8_APER_SIZE,
1755         .num_aperture_sizes     = 7,
1756         .configure              = intel_840_configure,
1757         .fetch_size             = intel_8xx_fetch_size,
1758         .cleanup                = intel_8xx_cleanup,
1759         .tlb_flush              = intel_8xx_tlbflush,
1760         .mask_memory            = agp_generic_mask_memory,
1761         .masks                  = intel_generic_masks,
1762         .agp_enable             = agp_generic_enable,
1763         .cache_flush            = global_cache_flush,
1764         .create_gatt_table      = agp_generic_create_gatt_table,
1765         .free_gatt_table        = agp_generic_free_gatt_table,
1766         .insert_memory          = agp_generic_insert_memory,
1767         .remove_memory          = agp_generic_remove_memory,
1768         .alloc_by_type          = agp_generic_alloc_by_type,
1769         .free_by_type           = agp_generic_free_by_type,
1770         .agp_alloc_page         = agp_generic_alloc_page,
1771         .agp_destroy_page       = agp_generic_destroy_page,
1772         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1773 };
1774
1775 static const struct agp_bridge_driver intel_845_driver = {
1776         .owner                  = THIS_MODULE,
1777         .aperture_sizes         = intel_8xx_sizes,
1778         .size_type              = U8_APER_SIZE,
1779         .num_aperture_sizes     = 7,
1780         .configure              = intel_845_configure,
1781         .fetch_size             = intel_8xx_fetch_size,
1782         .cleanup                = intel_8xx_cleanup,
1783         .tlb_flush              = intel_8xx_tlbflush,
1784         .mask_memory            = agp_generic_mask_memory,
1785         .masks                  = intel_generic_masks,
1786         .agp_enable             = agp_generic_enable,
1787         .cache_flush            = global_cache_flush,
1788         .create_gatt_table      = agp_generic_create_gatt_table,
1789         .free_gatt_table        = agp_generic_free_gatt_table,
1790         .insert_memory          = agp_generic_insert_memory,
1791         .remove_memory          = agp_generic_remove_memory,
1792         .alloc_by_type          = agp_generic_alloc_by_type,
1793         .free_by_type           = agp_generic_free_by_type,
1794         .agp_alloc_page         = agp_generic_alloc_page,
1795         .agp_destroy_page       = agp_generic_destroy_page,
1796         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1797         .chipset_flush          = intel_i830_chipset_flush,
1798 };
1799
1800 static const struct agp_bridge_driver intel_850_driver = {
1801         .owner                  = THIS_MODULE,
1802         .aperture_sizes         = intel_8xx_sizes,
1803         .size_type              = U8_APER_SIZE,
1804         .num_aperture_sizes     = 7,
1805         .configure              = intel_850_configure,
1806         .fetch_size             = intel_8xx_fetch_size,
1807         .cleanup                = intel_8xx_cleanup,
1808         .tlb_flush              = intel_8xx_tlbflush,
1809         .mask_memory            = agp_generic_mask_memory,
1810         .masks                  = intel_generic_masks,
1811         .agp_enable             = agp_generic_enable,
1812         .cache_flush            = global_cache_flush,
1813         .create_gatt_table      = agp_generic_create_gatt_table,
1814         .free_gatt_table        = agp_generic_free_gatt_table,
1815         .insert_memory          = agp_generic_insert_memory,
1816         .remove_memory          = agp_generic_remove_memory,
1817         .alloc_by_type          = agp_generic_alloc_by_type,
1818         .free_by_type           = agp_generic_free_by_type,
1819         .agp_alloc_page         = agp_generic_alloc_page,
1820         .agp_destroy_page       = agp_generic_destroy_page,
1821         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1822 };
1823
1824 static const struct agp_bridge_driver intel_860_driver = {
1825         .owner                  = THIS_MODULE,
1826         .aperture_sizes         = intel_8xx_sizes,
1827         .size_type              = U8_APER_SIZE,
1828         .num_aperture_sizes     = 7,
1829         .configure              = intel_860_configure,
1830         .fetch_size             = intel_8xx_fetch_size,
1831         .cleanup                = intel_8xx_cleanup,
1832         .tlb_flush              = intel_8xx_tlbflush,
1833         .mask_memory            = agp_generic_mask_memory,
1834         .masks                  = intel_generic_masks,
1835         .agp_enable             = agp_generic_enable,
1836         .cache_flush            = global_cache_flush,
1837         .create_gatt_table      = agp_generic_create_gatt_table,
1838         .free_gatt_table        = agp_generic_free_gatt_table,
1839         .insert_memory          = agp_generic_insert_memory,
1840         .remove_memory          = agp_generic_remove_memory,
1841         .alloc_by_type          = agp_generic_alloc_by_type,
1842         .free_by_type           = agp_generic_free_by_type,
1843         .agp_alloc_page         = agp_generic_alloc_page,
1844         .agp_destroy_page       = agp_generic_destroy_page,
1845         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1846 };
1847
1848 static const struct agp_bridge_driver intel_915_driver = {
1849         .owner                  = THIS_MODULE,
1850         .aperture_sizes         = intel_i830_sizes,
1851         .size_type              = FIXED_APER_SIZE,
1852         .num_aperture_sizes     = 4,
1853         .needs_scratch_page     = TRUE,
1854         .configure              = intel_i915_configure,
1855         .fetch_size             = intel_i9xx_fetch_size,
1856         .cleanup                = intel_i915_cleanup,
1857         .tlb_flush              = intel_i810_tlbflush,
1858         .mask_memory            = intel_i810_mask_memory,
1859         .masks                  = intel_i810_masks,
1860         .agp_enable             = intel_i810_agp_enable,
1861         .cache_flush            = global_cache_flush,
1862         .create_gatt_table      = intel_i915_create_gatt_table,
1863         .free_gatt_table        = intel_i830_free_gatt_table,
1864         .insert_memory          = intel_i915_insert_entries,
1865         .remove_memory          = intel_i915_remove_entries,
1866         .alloc_by_type          = intel_i830_alloc_by_type,
1867         .free_by_type           = intel_i810_free_by_type,
1868         .agp_alloc_page         = agp_generic_alloc_page,
1869         .agp_destroy_page       = agp_generic_destroy_page,
1870         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1871         .chipset_flush          = intel_i915_chipset_flush,
1872 };
1873
1874 static const struct agp_bridge_driver intel_i965_driver = {
1875        .owner                  = THIS_MODULE,
1876        .aperture_sizes         = intel_i830_sizes,
1877        .size_type              = FIXED_APER_SIZE,
1878        .num_aperture_sizes     = 4,
1879        .needs_scratch_page     = TRUE,
1880        .configure              = intel_i915_configure,
1881        .fetch_size             = intel_i9xx_fetch_size,
1882        .cleanup                = intel_i915_cleanup,
1883        .tlb_flush              = intel_i810_tlbflush,
1884        .mask_memory            = intel_i965_mask_memory,
1885        .masks                  = intel_i810_masks,
1886        .agp_enable             = intel_i810_agp_enable,
1887        .cache_flush            = global_cache_flush,
1888        .create_gatt_table      = intel_i965_create_gatt_table,
1889        .free_gatt_table        = intel_i830_free_gatt_table,
1890        .insert_memory          = intel_i915_insert_entries,
1891        .remove_memory          = intel_i915_remove_entries,
1892        .alloc_by_type          = intel_i830_alloc_by_type,
1893        .free_by_type           = intel_i810_free_by_type,
1894        .agp_alloc_page         = agp_generic_alloc_page,
1895        .agp_destroy_page       = agp_generic_destroy_page,
1896        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1897         .chipset_flush          = intel_i915_chipset_flush,
1898 };
1899
1900 static const struct agp_bridge_driver intel_7505_driver = {
1901         .owner                  = THIS_MODULE,
1902         .aperture_sizes         = intel_8xx_sizes,
1903         .size_type              = U8_APER_SIZE,
1904         .num_aperture_sizes     = 7,
1905         .configure              = intel_7505_configure,
1906         .fetch_size             = intel_8xx_fetch_size,
1907         .cleanup                = intel_8xx_cleanup,
1908         .tlb_flush              = intel_8xx_tlbflush,
1909         .mask_memory            = agp_generic_mask_memory,
1910         .masks                  = intel_generic_masks,
1911         .agp_enable             = agp_generic_enable,
1912         .cache_flush            = global_cache_flush,
1913         .create_gatt_table      = agp_generic_create_gatt_table,
1914         .free_gatt_table        = agp_generic_free_gatt_table,
1915         .insert_memory          = agp_generic_insert_memory,
1916         .remove_memory          = agp_generic_remove_memory,
1917         .alloc_by_type          = agp_generic_alloc_by_type,
1918         .free_by_type           = agp_generic_free_by_type,
1919         .agp_alloc_page         = agp_generic_alloc_page,
1920         .agp_destroy_page       = agp_generic_destroy_page,
1921         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1922 };
1923
1924 static const struct agp_bridge_driver intel_g33_driver = {
1925         .owner                  = THIS_MODULE,
1926         .aperture_sizes         = intel_i830_sizes,
1927         .size_type              = FIXED_APER_SIZE,
1928         .num_aperture_sizes     = 4,
1929         .needs_scratch_page     = TRUE,
1930         .configure              = intel_i915_configure,
1931         .fetch_size             = intel_i9xx_fetch_size,
1932         .cleanup                = intel_i915_cleanup,
1933         .tlb_flush              = intel_i810_tlbflush,
1934         .mask_memory            = intel_i965_mask_memory,
1935         .masks                  = intel_i810_masks,
1936         .agp_enable             = intel_i810_agp_enable,
1937         .cache_flush            = global_cache_flush,
1938         .create_gatt_table      = intel_i915_create_gatt_table,
1939         .free_gatt_table        = intel_i830_free_gatt_table,
1940         .insert_memory          = intel_i915_insert_entries,
1941         .remove_memory          = intel_i915_remove_entries,
1942         .alloc_by_type          = intel_i830_alloc_by_type,
1943         .free_by_type           = intel_i810_free_by_type,
1944         .agp_alloc_page         = agp_generic_alloc_page,
1945         .agp_destroy_page       = agp_generic_destroy_page,
1946         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1947         .chipset_flush          = intel_i915_chipset_flush,
1948 };
1949
1950 static int find_gmch(u16 device)
1951 {
1952         struct pci_dev *gmch_device;
1953
1954         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1955         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1956                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1957                                 device, gmch_device);
1958         }
1959
1960         if (!gmch_device)
1961                 return 0;
1962
1963         intel_private.pcidev = gmch_device;
1964         return 1;
1965 }
1966
1967 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1968  * driver and gmch_driver must be non-null, and find_gmch will determine
1969  * which one should be used if a gmch_chip_id is present.
1970  */
1971 static const struct intel_driver_description {
1972         unsigned int chip_id;
1973         unsigned int gmch_chip_id;
1974         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
1975         char *name;
1976         const struct agp_bridge_driver *driver;
1977         const struct agp_bridge_driver *gmch_driver;
1978 } intel_agp_chipsets[] = {
1979         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1980         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
1981         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
1982         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
1983                 NULL, &intel_810_driver },
1984         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
1985                 NULL, &intel_810_driver },
1986         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
1987                 NULL, &intel_810_driver },
1988         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
1989                 &intel_815_driver, &intel_810_driver },
1990         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
1991         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
1992         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
1993                 &intel_830mp_driver, &intel_830_driver },
1994         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
1995         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
1996         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
1997                 &intel_845_driver, &intel_830_driver },
1998         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
1999         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2000         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2001                 &intel_845_driver, &intel_830_driver },
2002         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2003         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2004                 &intel_845_driver, &intel_830_driver },
2005         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2006         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2007                 NULL, &intel_915_driver },
2008         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2009                 NULL, &intel_915_driver },
2010         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2011                 NULL, &intel_915_driver },
2012         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2013                 NULL, &intel_915_driver },
2014         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2015                 NULL, &intel_915_driver },
2016         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2017                 NULL, &intel_915_driver },
2018         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2019                 NULL, &intel_i965_driver },
2020         { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
2021                 NULL, &intel_i965_driver },
2022         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2023                 NULL, &intel_i965_driver },
2024         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2025                 NULL, &intel_i965_driver },
2026         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2027                 NULL, &intel_i965_driver },
2028         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2029                 NULL, &intel_i965_driver },
2030         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2031         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2032         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2033                 NULL, &intel_g33_driver },
2034         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2035                 NULL, &intel_g33_driver },
2036         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2037                 NULL, &intel_g33_driver },
2038         { 0, 0, 0, NULL, NULL, NULL }
2039 };
2040
2041 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2042                                      const struct pci_device_id *ent)
2043 {
2044         struct agp_bridge_data *bridge;
2045         u8 cap_ptr = 0;
2046         struct resource *r;
2047         int i;
2048
2049         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2050
2051         bridge = agp_alloc_bridge();
2052         if (!bridge)
2053                 return -ENOMEM;
2054
2055         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2056                 /* In case that multiple models of gfx chip may
2057                    stand on same host bridge type, this can be
2058                    sure we detect the right IGD. */
2059                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2060                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2061                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2062                                 bridge->driver =
2063                                         intel_agp_chipsets[i].gmch_driver;
2064                                 break;
2065                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2066                                 continue;
2067                         } else {
2068                                 bridge->driver = intel_agp_chipsets[i].driver;
2069                                 break;
2070                         }
2071                 }
2072         }
2073
2074         if (intel_agp_chipsets[i].name == NULL) {
2075                 if (cap_ptr)
2076                         printk(KERN_WARNING PFX "Unsupported Intel chipset"
2077                                "(device id: %04x)\n", pdev->device);
2078                 agp_put_bridge(bridge);
2079                 return -ENODEV;
2080         }
2081
2082         if (bridge->driver == NULL) {
2083                 /* bridge has no AGP and no IGD detected */
2084                 if (cap_ptr)
2085                         printk(KERN_WARNING PFX "Failed to find bridge device "
2086                                 "(chip_id: %04x)\n",
2087                                 intel_agp_chipsets[i].gmch_chip_id);
2088                 agp_put_bridge(bridge);
2089                 return -ENODEV;
2090         }
2091
2092         bridge->dev = pdev;
2093         bridge->capndx = cap_ptr;
2094         bridge->dev_private_data = &intel_private;
2095
2096         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
2097                 intel_agp_chipsets[i].name);
2098
2099         /*
2100         * The following fixes the case where the BIOS has "forgotten" to
2101         * provide an address range for the GART.
2102         * 20030610 - hamish@zot.org
2103         */
2104         r = &pdev->resource[0];
2105         if (!r->start && r->end) {
2106                 if (pci_assign_resource(pdev, 0)) {
2107                         printk(KERN_ERR PFX "could not assign resource 0\n");
2108                         agp_put_bridge(bridge);
2109                         return -ENODEV;
2110                 }
2111         }
2112
2113         /*
2114         * If the device has not been properly setup, the following will catch
2115         * the problem and should stop the system from crashing.
2116         * 20030610 - hamish@zot.org
2117         */
2118         if (pci_enable_device(pdev)) {
2119                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
2120                 agp_put_bridge(bridge);
2121                 return -ENODEV;
2122         }
2123
2124         /* Fill in the mode register */
2125         if (cap_ptr) {
2126                 pci_read_config_dword(pdev,
2127                                 bridge->capndx+PCI_AGP_STATUS,
2128                                 &bridge->mode);
2129         }
2130
2131         pci_set_drvdata(pdev, bridge);
2132         return agp_add_bridge(bridge);
2133 }
2134
2135 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2136 {
2137         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2138
2139         agp_remove_bridge(bridge);
2140
2141         if (intel_private.pcidev)
2142                 pci_dev_put(intel_private.pcidev);
2143
2144         agp_put_bridge(bridge);
2145 }
2146
2147 #ifdef CONFIG_PM
2148 static int agp_intel_resume(struct pci_dev *pdev)
2149 {
2150         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2151
2152         pci_restore_state(pdev);
2153
2154         /* We should restore our graphics device's config space,
2155          * as host bridge (00:00) resumes before graphics device (02:00),
2156          * then our access to its pci space can work right.
2157          */
2158         if (intel_private.pcidev)
2159                 pci_restore_state(intel_private.pcidev);
2160
2161         if (bridge->driver == &intel_generic_driver)
2162                 intel_configure();
2163         else if (bridge->driver == &intel_850_driver)
2164                 intel_850_configure();
2165         else if (bridge->driver == &intel_845_driver)
2166                 intel_845_configure();
2167         else if (bridge->driver == &intel_830mp_driver)
2168                 intel_830mp_configure();
2169         else if (bridge->driver == &intel_915_driver)
2170                 intel_i915_configure();
2171         else if (bridge->driver == &intel_830_driver)
2172                 intel_i830_configure();
2173         else if (bridge->driver == &intel_810_driver)
2174                 intel_i810_configure();
2175         else if (bridge->driver == &intel_i965_driver)
2176                 intel_i915_configure();
2177
2178         return 0;
2179 }
2180 #endif
2181
2182 static struct pci_device_id agp_intel_pci_table[] = {
2183 #define ID(x)                                           \
2184         {                                               \
2185         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2186         .class_mask     = ~0,                           \
2187         .vendor         = PCI_VENDOR_ID_INTEL,          \
2188         .device         = x,                            \
2189         .subvendor      = PCI_ANY_ID,                   \
2190         .subdevice      = PCI_ANY_ID,                   \
2191         }
2192         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2193         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2194         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2195         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2196         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2197         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2198         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2199         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2200         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2201         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2202         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2203         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2204         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2205         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2206         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2207         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2208         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2209         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2210         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2211         ID(PCI_DEVICE_ID_INTEL_7505_0),
2212         ID(PCI_DEVICE_ID_INTEL_7205_0),
2213         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2214         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2215         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2216         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2217         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2218         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2219         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2220         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2221         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2222         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2223         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2224         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2225         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2226         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2227         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2228         { }
2229 };
2230
2231 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2232
2233 static struct pci_driver agp_intel_pci_driver = {
2234         .name           = "agpgart-intel",
2235         .id_table       = agp_intel_pci_table,
2236         .probe          = agp_intel_probe,
2237         .remove         = __devexit_p(agp_intel_remove),
2238 #ifdef CONFIG_PM
2239         .resume         = agp_intel_resume,
2240 #endif
2241 };
2242
2243 static int __init agp_intel_init(void)
2244 {
2245         if (agp_off)
2246                 return -EINVAL;
2247         return pci_register_driver(&agp_intel_pci_driver);
2248 }
2249
2250 static void __exit agp_intel_cleanup(void)
2251 {
2252         pci_unregister_driver(&agp_intel_pci_driver);
2253 }
2254
2255 module_init(agp_intel_init);
2256 module_exit(agp_intel_cleanup);
2257
2258 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2259 MODULE_LICENSE("GPL and additional rights");