Pileus Git - ~andy/linux/blob - drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  14 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  17 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
  18 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
  19 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  20 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  21 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  22 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  23 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  24 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  25 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  26 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  27 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  28 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  29 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  30 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  31 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  32 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  33 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  34 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  35
  36 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  37                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
  38                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  39                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  40                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  41                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  42
  43 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  44                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  45                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
  46
  47 extern int agp_memory_reserved;
  48
  49
  50 /* Intel 815 register */
  51 #define INTEL_815_APCONT        0x51
  52 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
  53
  54 /* Intel i820 registers */
  55 #define INTEL_I820_RDCR         0x51
  56 #define INTEL_I820_ERRSTS       0xc8
  57
  58 /* Intel i840 registers */
  59 #define INTEL_I840_MCHCFG       0x50
  60 #define INTEL_I840_ERRSTS       0xc8
  61
  62 /* Intel i850 registers */
  63 #define INTEL_I850_MCHCFG       0x50
  64 #define INTEL_I850_ERRSTS       0xc8
  65
  66 /* intel 915G registers */
  67 #define I915_GMADDR     0x18
  68 #define I915_MMADDR     0x10
  69 #define I915_PTEADDR    0x1C
  70 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
  71 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
  72 #define G33_GMCH_GMS_STOLEN_128M       (0x8 << 4)
  73 #define G33_GMCH_GMS_STOLEN_256M       (0x9 << 4)
  74 #define I915_IFPADDR    0x60
  75
  76 /* Intel 965G registers */
  77 #define I965_MSAC 0x62
  78 #define I965_IFPADDR    0x70
  79
  80 /* Intel 7505 registers */
  81 #define INTEL_I7505_APSIZE      0x74
  82 #define INTEL_I7505_NCAPID      0x60
  83 #define INTEL_I7505_NISTAT      0x6c
  84 #define INTEL_I7505_ATTBASE     0x78
  85 #define INTEL_I7505_ERRSTS      0x42
  86 #define INTEL_I7505_AGPCTRL     0x70
  87 #define INTEL_I7505_MCHCFG      0x50
  88
  89 static const struct aper_size_info_fixed intel_i810_sizes[] =
  90 {
  91         {64, 16384, 4},
  92         /* The 32M mode still requires a 64k gatt */
  93         {32, 8192, 4}
  94 };
  95
  96 #define AGP_DCACHE_MEMORY       1
  97 #define AGP_PHYS_MEMORY         2
  98 #define INTEL_AGP_CACHED_MEMORY 3
  99
 100 static struct gatt_mask intel_i810_masks[] =
 101 {
 102         {.mask = I810_PTE_VALID, .type = 0},
 103         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 104         {.mask = I810_PTE_VALID, .type = 0},
 105         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 106          .type = INTEL_AGP_CACHED_MEMORY}
 107 };
 108
 109 static struct _intel_private {
 110         struct pci_dev *pcidev; /* device one */
 111         u8 __iomem *registers;
 112         u32 __iomem *gtt;               /* I915G */
 113         int num_dcache_entries;
 114         /* gtt_entries is the number of gtt entries that are already mapped
 115          * to stolen memory.  Stolen memory is larger than the memory mapped
 116          * through gtt_entries, as it includes some reserved space for the BIOS
 117          * popup and for the GTT.
 118          */
 119         int gtt_entries;                        /* i830+ */
 120         union {
 121                 void __iomem *i9xx_flush_page;
 122                 void *i8xx_flush_page;
 123         };
 124         struct page *i8xx_page;
 125         struct resource ifp_resource;
 126 } intel_private;
 127
 128 static int intel_i810_fetch_size(void)
 129 {
 130         u32 smram_miscc;
 131         struct aper_size_info_fixed *values;
 132
 133         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 134         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 135
 136         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 137                 printk(KERN_WARNING PFX "i810 is disabled\n");
 138                 return 0;
 139         }
 140         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 141                 agp_bridge->previous_size =
 142                         agp_bridge->current_size = (void *) (values + 1);
 143                 agp_bridge->aperture_size_idx = 1;
 144                 return values[1].size;
 145         } else {
 146                 agp_bridge->previous_size =
 147                         agp_bridge->current_size = (void *) (values);
 148                 agp_bridge->aperture_size_idx = 0;
 149                 return values[0].size;
 150         }
 151
 152         return 0;
 153 }
 154
 155 static int intel_i810_configure(void)
 156 {
 157         struct aper_size_info_fixed *current_size;
 158         u32 temp;
 159         int i;
 160
 161         current_size = A_SIZE_FIX(agp_bridge->current_size);
 162
 163         if (!intel_private.registers) {
 164                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 165                 temp &= 0xfff80000;
 166
 167                 intel_private.registers = ioremap(temp, 128 * 4096);
 168                 if (!intel_private.registers) {
 169                         printk(KERN_ERR PFX "Unable to remap memory.\n");
 170                         return -ENOMEM;
 171                 }
 172         }
 173
 174         if ((readl(intel_private.registers+I810_DRAM_CTL)
 175                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 176                 /* This will need to be dynamically assigned */
 177                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
 178                 intel_private.num_dcache_entries = 1024;
 179         }
 180         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 181         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 182         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 183         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 184
 185         if (agp_bridge->driver->needs_scratch_page) {
 186                 for (i = 0; i < current_size->num_entries; i++) {
 187                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 188                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI posting. */
 189                 }
 190         }
 191         global_cache_flush();
 192         return 0;
 193 }
 194
 195 static void intel_i810_cleanup(void)
 196 {
 197         writel(0, intel_private.registers+I810_PGETBL_CTL);
 198         readl(intel_private.registers); /* PCI Posting. */
 199         iounmap(intel_private.registers);
 200 }
 201
 202 static void intel_i810_tlbflush(struct agp_memory *mem)
 203 {
 204         return;
 205 }
 206
 207 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 208 {
 209         return;
 210 }
 211
 212 /* Exists to support ARGB cursors */
 213 static void *i8xx_alloc_pages(void)
 214 {
 215         struct page * page;
 216
 217         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 218         if (page == NULL)
 219                 return NULL;
 220
 221         if (set_pages_uc(page, 4) < 0) {
 222                 set_pages_wb(page, 4);
 223                 __free_pages(page, 2);
 224                 return NULL;
 225         }
 226         get_page(page);
 227         atomic_inc(&agp_bridge->current_memory_agp);
 228         return page_address(page);
 229 }
 230
 231 static void i8xx_destroy_pages(void *addr)
 232 {
 233         struct page *page;
 234
 235         if (addr == NULL)
 236                 return;
 237
 238         page = virt_to_page(addr);
 239         set_pages_wb(page, 4);
 240         put_page(page);
 241         __free_pages(page, 2);
 242         atomic_dec(&agp_bridge->current_memory_agp);
 243 }
 244
 245 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 246                                         int type)
 247 {
 248         if (type < AGP_USER_TYPES)
 249                 return type;
 250         else if (type == AGP_USER_CACHED_MEMORY)
 251                 return INTEL_AGP_CACHED_MEMORY;
 252         else
 253                 return 0;
 254 }
 255
 256 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 257                                 int type)
 258 {
 259         int i, j, num_entries;
 260         void *temp;
 261         int ret = -EINVAL;
 262         int mask_type;
 263
 264         if (mem->page_count == 0)
 265                 goto out;
 266
 267         temp = agp_bridge->current_size;
 268         num_entries = A_SIZE_FIX(temp)->num_entries;
 269
 270         if ((pg_start + mem->page_count) > num_entries)
 271                 goto out_err;
 272
 273
 274         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 275                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 276                         ret = -EBUSY;
 277                         goto out_err;
 278                 }
 279         }
 280
 281         if (type != mem->type)
 282                 goto out_err;
 283
 284         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 285
 286         switch (mask_type) {
 287         case AGP_DCACHE_MEMORY:
 288                 if (!mem->is_flushed)
 289                         global_cache_flush();
 290                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 291                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 292                                intel_private.registers+I810_PTE_BASE+(i*4));
 293                 }
 294                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 295                 break;
 296         case AGP_PHYS_MEMORY:
 297         case AGP_NORMAL_MEMORY:
 298                 if (!mem->is_flushed)
 299                         global_cache_flush();
 300                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 301                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 302                                                                mem->memory[i],
 303                                                                mask_type),
 304                                intel_private.registers+I810_PTE_BASE+(j*4));
 305                 }
 306                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 307                 break;
 308         default:
 309                 goto out_err;
 310         }
 311
 312         agp_bridge->driver->tlb_flush(mem);
 313 out:
 314         ret = 0;
 315 out_err:
 316         mem->is_flushed = 1;
 317         return ret;
 318 }
 319
 320 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 321                                 int type)
 322 {
 323         int i;
 324
 325         if (mem->page_count == 0)
 326                 return 0;
 327
 328         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 329                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 330         }
 331         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 332
 333         agp_bridge->driver->tlb_flush(mem);
 334         return 0;
 335 }
 336
 337 /*
 338  * The i810/i830 requires a physical address to program its mouse
 339  * pointer into hardware.
 340  * However the Xserver still writes to it through the agp aperture.
 341  */
 342 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 343 {
 344         struct agp_memory *new;
 345         void *addr;
 346
 347         switch (pg_count) {
 348         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
 349                 break;
 350         case 4:
 351                 /* kludge to get 4 physical pages for ARGB cursor */
 352                 addr = i8xx_alloc_pages();
 353                 break;
 354         default:
 355                 return NULL;
 356         }
 357
 358         if (addr == NULL)
 359                 return NULL;
 360
 361         new = agp_create_memory(pg_count);
 362         if (new == NULL)
 363                 return NULL;
 364
 365         new->memory[0] = virt_to_gart(addr);
 366         if (pg_count == 4) {
 367                 /* kludge to get 4 physical pages for ARGB cursor */
 368                 new->memory[1] = new->memory[0] + PAGE_SIZE;
 369                 new->memory[2] = new->memory[1] + PAGE_SIZE;
 370                 new->memory[3] = new->memory[2] + PAGE_SIZE;
 371         }
 372         new->page_count = pg_count;
 373         new->num_scratch_pages = pg_count;
 374         new->type = AGP_PHYS_MEMORY;
 375         new->physical = new->memory[0];
 376         return new;
 377 }
 378
 379 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 380 {
 381         struct agp_memory *new;
 382
 383         if (type == AGP_DCACHE_MEMORY) {
 384                 if (pg_count != intel_private.num_dcache_entries)
 385                         return NULL;
 386
 387                 new = agp_create_memory(1);
 388                 if (new == NULL)
 389                         return NULL;
 390
 391                 new->type = AGP_DCACHE_MEMORY;
 392                 new->page_count = pg_count;
 393                 new->num_scratch_pages = 0;
 394                 agp_free_page_array(new);
 395                 return new;
 396         }
 397         if (type == AGP_PHYS_MEMORY)
 398                 return alloc_agpphysmem_i8xx(pg_count, type);
 399         return NULL;
 400 }
 401
 402 static void intel_i810_free_by_type(struct agp_memory *curr)
 403 {
 404         agp_free_key(curr->key);
 405         if (curr->type == AGP_PHYS_MEMORY) {
 406                 if (curr->page_count == 4)
 407                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
 408                 else {
 409                         agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
 410                                                              AGP_PAGE_DESTROY_UNMAP);
 411                         agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
 412                                                              AGP_PAGE_DESTROY_FREE);
 413                 }
 414                 agp_free_page_array(curr);
 415         }
 416         kfree(curr);
 417 }
 418
 419 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 420         unsigned long addr, int type)
 421 {
 422         /* Type checking must be done elsewhere */
 423         return addr | bridge->driver->masks[type].mask;
 424 }
 425
 426 static struct aper_size_info_fixed intel_i830_sizes[] =
 427 {
 428         {128, 32768, 5},
 429         /* The 64M mode still requires a 128k gatt */
 430         {64, 16384, 5},
 431         {256, 65536, 6},
 432         {512, 131072, 7},
 433 };
 434
 435 static void intel_i830_init_gtt_entries(void)
 436 {
 437         u16 gmch_ctrl;
 438         int gtt_entries;
 439         u8 rdct;
 440         int local = 0;
 441         static const int ddt[4] = { 0, 16, 32, 64 };
 442         int size; /* reserved space (in kb) at the top of stolen memory */
 443
 444         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 445
 446         if (IS_I965) {
 447                 u32 pgetbl_ctl;
 448                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 449
 450                 /* The 965 has a field telling us the size of the GTT,
 451                  * which may be larger than what is necessary to map the
 452                  * aperture.
 453                  */
 454                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 455                 case I965_PGETBL_SIZE_128KB:
 456                         size = 128;
 457                         break;
 458                 case I965_PGETBL_SIZE_256KB:
 459                         size = 256;
 460                         break;
 461                 case I965_PGETBL_SIZE_512KB:
 462                         size = 512;
 463                         break;
 464                 default:
 465                         printk(KERN_INFO PFX "Unknown page table size, "
 466                                "assuming 512KB\n");
 467                         size = 512;
 468                 }
 469                 size += 4; /* add in BIOS popup space */
 470         } else if (IS_G33) {
 471         /* G33's GTT size defined in gmch_ctrl */
 472                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 473                 case G33_PGETBL_SIZE_1M:
 474                         size = 1024;
 475                         break;
 476                 case G33_PGETBL_SIZE_2M:
 477                         size = 2048;
 478                         break;
 479                 default:
 480                         printk(KERN_INFO PFX "Unknown page table size 0x%x, "
 481                                 "assuming 512KB\n",
 482                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 483                         size = 512;
 484                 }
 485                 size += 4;
 486         } else {
 487                 /* On previous hardware, the GTT size was just what was
 488                  * required to map the aperture.
 489                  */
 490                 size = agp_bridge->driver->fetch_size() + 4;
 491         }
 492
 493         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 494             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 495                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 496                 case I830_GMCH_GMS_STOLEN_512:
 497                         gtt_entries = KB(512) - KB(size);
 498                         break;
 499                 case I830_GMCH_GMS_STOLEN_1024:
 500                         gtt_entries = MB(1) - KB(size);
 501                         break;
 502                 case I830_GMCH_GMS_STOLEN_8192:
 503                         gtt_entries = MB(8) - KB(size);
 504                         break;
 505                 case I830_GMCH_GMS_LOCAL:
 506                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 507                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 508                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 509                         local = 1;
 510                         break;
 511                 default:
 512                         gtt_entries = 0;
 513                         break;
 514                 }
 515         } else {
 516                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 517                 case I855_GMCH_GMS_STOLEN_1M:
 518                         gtt_entries = MB(1) - KB(size);
 519                         break;
 520                 case I855_GMCH_GMS_STOLEN_4M:
 521                         gtt_entries = MB(4) - KB(size);
 522                         break;
 523                 case I855_GMCH_GMS_STOLEN_8M:
 524                         gtt_entries = MB(8) - KB(size);
 525                         break;
 526                 case I855_GMCH_GMS_STOLEN_16M:
 527                         gtt_entries = MB(16) - KB(size);
 528                         break;
 529                 case I855_GMCH_GMS_STOLEN_32M:
 530                         gtt_entries = MB(32) - KB(size);
 531                         break;
 532                 case I915_GMCH_GMS_STOLEN_48M:
 533                         /* Check it's really I915G */
 534                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
 535                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 536                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 537                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 538                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
 539                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
 540                             IS_I965 || IS_G33)
 541                                 gtt_entries = MB(48) - KB(size);
 542                         else
 543                                 gtt_entries = 0;
 544                         break;
 545                 case I915_GMCH_GMS_STOLEN_64M:
 546                         /* Check it's really I915G */
 547                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
 548                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 549                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 550                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 551                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
 552                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
 553                             IS_I965 || IS_G33)
 554                                 gtt_entries = MB(64) - KB(size);
 555                         else
 556                                 gtt_entries = 0;
 557                         break;
 558                 case G33_GMCH_GMS_STOLEN_128M:
 559                         if (IS_G33)
 560                                 gtt_entries = MB(128) - KB(size);
 561                         else
 562                                 gtt_entries = 0;
 563                         break;
 564                 case G33_GMCH_GMS_STOLEN_256M:
 565                         if (IS_G33)
 566                                 gtt_entries = MB(256) - KB(size);
 567                         else
 568                                 gtt_entries = 0;
 569                         break;
 570                 default:
 571                         gtt_entries = 0;
 572                         break;
 573                 }
 574         }
 575         if (gtt_entries > 0)
 576                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
 577                        gtt_entries / KB(1), local ? "local" : "stolen");
 578         else
 579                 printk(KERN_INFO PFX
 580                        "No pre-allocated video memory detected.\n");
 581         gtt_entries /= KB(4);
 582
 583         intel_private.gtt_entries = gtt_entries;
 584 }
 585
 586 static void intel_i830_fini_flush(void)
 587 {
 588         kunmap(intel_private.i8xx_page);
 589         intel_private.i8xx_flush_page = NULL;
 590         unmap_page_from_agp(intel_private.i8xx_page);
 591         flush_agp_mappings();
 592
 593         __free_page(intel_private.i8xx_page);
 594 }
 595
 596 static void intel_i830_setup_flush(void)
 597 {
 598
 599         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 600         if (!intel_private.i8xx_page) {
 601                 return;
 602         }
 603
 604         /* make page uncached */
 605         map_page_into_agp(intel_private.i8xx_page);
 606         flush_agp_mappings();
 607
 608         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 609         if (!intel_private.i8xx_flush_page)
 610                 intel_i830_fini_flush();
 611 }
 612
 613 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 614 {
 615         unsigned int *pg = intel_private.i8xx_flush_page;
 616         int i;
 617
 618         for (i = 0; i < 256; i+=2)
 619                 *(pg + i) = i;
 620
 621         wmb();
 622 }
 623
 624 /* The intel i830 automatically initializes the agp aperture during POST.
 625  * Use the memory already set aside for in the GTT.
 626  */
 627 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 628 {
 629         int page_order;
 630         struct aper_size_info_fixed *size;
 631         int num_entries;
 632         u32 temp;
 633
 634         size = agp_bridge->current_size;
 635         page_order = size->page_order;
 636         num_entries = size->num_entries;
 637         agp_bridge->gatt_table_real = NULL;
 638
 639         pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
 640         temp &= 0xfff80000;
 641
 642         intel_private.registers = ioremap(temp,128 * 4096);
 643         if (!intel_private.registers)
 644                 return -ENOMEM;
 645
 646         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 647         global_cache_flush();   /* FIXME: ?? */
 648
 649         /* we have to call this as early as possible after the MMIO base address is known */
 650         intel_i830_init_gtt_entries();
 651
 652         agp_bridge->gatt_table = NULL;
 653
 654         agp_bridge->gatt_bus_addr = temp;
 655
 656         return 0;
 657 }
 658
 659 /* Return the gatt table to a sane state. Use the top of stolen
 660  * memory for the GTT.
 661  */
 662 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 663 {
 664         return 0;
 665 }
 666
 667 static int intel_i830_fetch_size(void)
 668 {
 669         u16 gmch_ctrl;
 670         struct aper_size_info_fixed *values;
 671
 672         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 673
 674         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 675             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 676                 /* 855GM/852GM/865G has 128MB aperture size */
 677                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 678                 agp_bridge->aperture_size_idx = 0;
 679                 return values[0].size;
 680         }
 681
 682         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 683
 684         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 685                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 686                 agp_bridge->aperture_size_idx = 0;
 687                 return values[0].size;
 688         } else {
 689                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 690                 agp_bridge->aperture_size_idx = 1;
 691                 return values[1].size;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int intel_i830_configure(void)
 698 {
 699         struct aper_size_info_fixed *current_size;
 700         u32 temp;
 701         u16 gmch_ctrl;
 702         int i;
 703
 704         current_size = A_SIZE_FIX(agp_bridge->current_size);
 705
 706         pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
 707         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 708
 709         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 710         gmch_ctrl |= I830_GMCH_ENABLED;
 711         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 712
 713         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 714         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 715
 716         if (agp_bridge->driver->needs_scratch_page) {
 717                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 718                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 719                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI Posting. */
 720                 }
 721         }
 722
 723         global_cache_flush();
 724
 725         intel_i830_setup_flush();
 726         return 0;
 727 }
 728
 729 static void intel_i830_cleanup(void)
 730 {
 731         iounmap(intel_private.registers);
 732 }
 733
 734 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
 735 {
 736         int i,j,num_entries;
 737         void *temp;
 738         int ret = -EINVAL;
 739         int mask_type;
 740
 741         if (mem->page_count == 0)
 742                 goto out;
 743
 744         temp = agp_bridge->current_size;
 745         num_entries = A_SIZE_FIX(temp)->num_entries;
 746
 747         if (pg_start < intel_private.gtt_entries) {
 748                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 749                                 pg_start,intel_private.gtt_entries);
 750
 751                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 752                 goto out_err;
 753         }
 754
 755         if ((pg_start + mem->page_count) > num_entries)
 756                 goto out_err;
 757
 758         /* The i830 can't check the GTT for entries since its read only,
 759          * depend on the caller to make the correct offset decisions.
 760          */
 761
 762         if (type != mem->type)
 763                 goto out_err;
 764
 765         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 766
 767         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 768             mask_type != INTEL_AGP_CACHED_MEMORY)
 769                 goto out_err;
 770
 771         if (!mem->is_flushed)
 772                 global_cache_flush();
 773
 774         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 775                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 776                                                        mem->memory[i], mask_type),
 777                        intel_private.registers+I810_PTE_BASE+(j*4));
 778         }
 779         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 780         agp_bridge->driver->tlb_flush(mem);
 781
 782 out:
 783         ret = 0;
 784 out_err:
 785         mem->is_flushed = 1;
 786         return ret;
 787 }
 788
 789 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
 790                                 int type)
 791 {
 792         int i;
 793
 794         if (mem->page_count == 0)
 795                 return 0;
 796
 797         if (pg_start < intel_private.gtt_entries) {
 798                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
 799                 return -EINVAL;
 800         }
 801
 802         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 803                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 804         }
 805         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 806
 807         agp_bridge->driver->tlb_flush(mem);
 808         return 0;
 809 }
 810
 811 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
 812 {
 813         if (type == AGP_PHYS_MEMORY)
 814                 return alloc_agpphysmem_i8xx(pg_count, type);
 815         /* always return NULL for other allocation types for now */
 816         return NULL;
 817 }
 818
 819 static int intel_alloc_chipset_flush_resource(void)
 820 {
 821         int ret;
 822         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
 823                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
 824                                      pcibios_align_resource, agp_bridge->dev);
 825
 826         return ret;
 827 }
 828
 829 static void intel_i915_setup_chipset_flush(void)
 830 {
 831         int ret;
 832         u32 temp;
 833
 834         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
 835         if (!(temp & 0x1)) {
 836                 intel_alloc_chipset_flush_resource();
 837
 838                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 839         } else {
 840                 temp &= ~1;
 841
 842                 intel_private.ifp_resource.start = temp;
 843                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
 844                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 845                 if (ret) {
 846                         intel_private.ifp_resource.start = 0;
 847                         printk("Failed inserting resource into tree\n");
 848                 }
 849         }
 850 }
 851
 852 static void intel_i965_g33_setup_chipset_flush(void)
 853 {
 854         u32 temp_hi, temp_lo;
 855         int ret;
 856
 857         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
 858         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
 859
 860         if (!(temp_lo & 0x1)) {
 861
 862                 intel_alloc_chipset_flush_resource();
 863
 864                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
 865                         upper_32_bits(intel_private.ifp_resource.start));
 866                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 867         } else {
 868                 u64 l64;
 869
 870                 temp_lo &= ~0x1;
 871                 l64 = ((u64)temp_hi << 32) | temp_lo;
 872
 873                 intel_private.ifp_resource.start = l64;
 874                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
 875                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 876                 if (!ret) {
 877                         printk("Failed inserting resource into tree - continuing\n");
 878                 }
 879         }
 880 }
 881
 882 static void intel_i9xx_setup_flush(void)
 883 {
 884         /* setup a resource for this object */
 885         memset(&intel_private.ifp_resource, 0, sizeof(intel_private.ifp_resource));
 886
 887         intel_private.ifp_resource.name = "Intel Flush Page";
 888         intel_private.ifp_resource.flags = IORESOURCE_MEM;
 889
 890         /* Setup chipset flush for 915 */
 891         if (IS_I965 || IS_G33) {
 892                 intel_i965_g33_setup_chipset_flush();
 893         } else {
 894                 intel_i915_setup_chipset_flush();
 895         }
 896
 897         if (intel_private.ifp_resource.start) {
 898                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
 899                 if (!intel_private.i9xx_flush_page)
 900                         printk("unable to ioremap flush  page - no chipset flushing");
 901         }
 902 }
 903
 904 static int intel_i915_configure(void)
 905 {
 906         struct aper_size_info_fixed *current_size;
 907         u32 temp;
 908         u16 gmch_ctrl;
 909         int i;
 910
 911         current_size = A_SIZE_FIX(agp_bridge->current_size);
 912
 913         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
 914
 915         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 916
 917         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 918         gmch_ctrl |= I830_GMCH_ENABLED;
 919         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 920
 921         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 922         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 923
 924         if (agp_bridge->driver->needs_scratch_page) {
 925                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 926                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
 927                         readl(intel_private.gtt+i);     /* PCI Posting. */
 928                 }
 929         }
 930
 931         global_cache_flush();
 932
 933         intel_i9xx_setup_flush();
 934
 935         return 0;
 936 }
 937
 938 static void intel_i915_cleanup(void)
 939 {
 940         if (intel_private.i9xx_flush_page)
 941                 iounmap(intel_private.i9xx_flush_page);
 942         iounmap(intel_private.gtt);
 943         iounmap(intel_private.registers);
 944 }
 945
 946 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
 947 {
 948         if (intel_private.i9xx_flush_page)
 949                 writel(1, intel_private.i9xx_flush_page);
 950 }
 951
 952 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
 953                                 int type)
 954 {
 955         int i,j,num_entries;
 956         void *temp;
 957         int ret = -EINVAL;
 958         int mask_type;
 959
 960         if (mem->page_count == 0)
 961                 goto out;
 962
 963         temp = agp_bridge->current_size;
 964         num_entries = A_SIZE_FIX(temp)->num_entries;
 965
 966         if (pg_start < intel_private.gtt_entries) {
 967                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 968                                 pg_start,intel_private.gtt_entries);
 969
 970                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 971                 goto out_err;
 972         }
 973
 974         if ((pg_start + mem->page_count) > num_entries)
 975                 goto out_err;
 976
 977         /* The i915 can't check the GTT for entries since its read only,
 978          * depend on the caller to make the correct offset decisions.
 979          */
 980
 981         if (type != mem->type)
 982                 goto out_err;
 983
 984         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 985
 986         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 987             mask_type != INTEL_AGP_CACHED_MEMORY)
 988                 goto out_err;
 989
 990         if (!mem->is_flushed)
 991                 global_cache_flush();
 992
 993         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 994                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 995                         mem->memory[i], mask_type), intel_private.gtt+j);
 996         }
 997
 998         readl(intel_private.gtt+j-1);
 999         agp_bridge->driver->tlb_flush(mem);
1000
1001  out:
1002         ret = 0;
1003  out_err:
1004         mem->is_flushed = 1;
1005         return ret;
1006 }
1007
1008 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
1009                                 int type)
1010 {
1011         int i;
1012
1013         if (mem->page_count == 0)
1014                 return 0;
1015
1016         if (pg_start < intel_private.gtt_entries) {
1017                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
1018                 return -EINVAL;
1019         }
1020
1021         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1022                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1023         }
1024         readl(intel_private.gtt+i-1);
1025
1026         agp_bridge->driver->tlb_flush(mem);
1027         return 0;
1028 }
1029
1030 /* Return the aperture size by just checking the resource length.  The effect
1031  * described in the spec of the MSAC registers is just changing of the
1032  * resource size.
1033  */
1034 static int intel_i9xx_fetch_size(void)
1035 {
1036         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1037         int aper_size; /* size in megabytes */
1038         int i;
1039
1040         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1041
1042         for (i = 0; i < num_sizes; i++) {
1043                 if (aper_size == intel_i830_sizes[i].size) {
1044                         agp_bridge->current_size = intel_i830_sizes + i;
1045                         agp_bridge->previous_size = agp_bridge->current_size;
1046                         return aper_size;
1047                 }
1048         }
1049
1050         return 0;
1051 }
1052
1053 /* The intel i915 automatically initializes the agp aperture during POST.
1054  * Use the memory already set aside for in the GTT.
1055  */
1056 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1057 {
1058         int page_order;
1059         struct aper_size_info_fixed *size;
1060         int num_entries;
1061         u32 temp, temp2;
1062         int gtt_map_size = 256 * 1024;
1063
1064         size = agp_bridge->current_size;
1065         page_order = size->page_order;
1066         num_entries = size->num_entries;
1067         agp_bridge->gatt_table_real = NULL;
1068
1069         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1070         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
1071
1072         if (IS_G33)
1073             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1074         intel_private.gtt = ioremap(temp2, gtt_map_size);
1075         if (!intel_private.gtt)
1076                 return -ENOMEM;
1077
1078         temp &= 0xfff80000;
1079
1080         intel_private.registers = ioremap(temp,128 * 4096);
1081         if (!intel_private.registers) {
1082                 iounmap(intel_private.gtt);
1083                 return -ENOMEM;
1084         }
1085
1086         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1087         global_cache_flush();   /* FIXME: ? */
1088
1089         /* we have to call this as early as possible after the MMIO base address is known */
1090         intel_i830_init_gtt_entries();
1091
1092         agp_bridge->gatt_table = NULL;
1093
1094         agp_bridge->gatt_bus_addr = temp;
1095
1096         return 0;
1097 }
1098
1099 /*
1100  * The i965 supports 36-bit physical addresses, but to keep
1101  * the format of the GTT the same, the bits that don't fit
1102  * in a 32-bit word are shifted down to bits 4..7.
1103  *
1104  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1105  * is always zero on 32-bit architectures, so no need to make
1106  * this conditional.
1107  */
1108 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1109         unsigned long addr, int type)
1110 {
1111         /* Shift high bits down */
1112         addr |= (addr >> 28) & 0xf0;
1113
1114         /* Type checking must be done elsewhere */
1115         return addr | bridge->driver->masks[type].mask;
1116 }
1117
1118 /* The intel i965 automatically initializes the agp aperture during POST.
1119  * Use the memory already set aside for in the GTT.
1120  */
1121 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1122 {
1123        int page_order;
1124        struct aper_size_info_fixed *size;
1125        int num_entries;
1126        u32 temp;
1127
1128        size = agp_bridge->current_size;
1129        page_order = size->page_order;
1130        num_entries = size->num_entries;
1131        agp_bridge->gatt_table_real = NULL;
1132
1133        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1134
1135        temp &= 0xfff00000;
1136        intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
1137
1138         if (!intel_private.gtt)
1139                 return -ENOMEM;
1140
1141
1142        intel_private.registers = ioremap(temp,128 * 4096);
1143        if (!intel_private.registers) {
1144                 iounmap(intel_private.gtt);
1145                 return -ENOMEM;
1146         }
1147
1148        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1149        global_cache_flush();   /* FIXME: ? */
1150
1151        /* we have to call this as early as possible after the MMIO base address is known */
1152        intel_i830_init_gtt_entries();
1153
1154        agp_bridge->gatt_table = NULL;
1155
1156        agp_bridge->gatt_bus_addr = temp;
1157
1158        return 0;
1159 }
1160
1161
1162 static int intel_fetch_size(void)
1163 {
1164         int i;
1165         u16 temp;
1166         struct aper_size_info_16 *values;
1167
1168         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1169         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1170
1171         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1172                 if (temp == values[i].size_value) {
1173                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1174                         agp_bridge->aperture_size_idx = i;
1175                         return values[i].size;
1176                 }
1177         }
1178
1179         return 0;
1180 }
1181
1182 static int __intel_8xx_fetch_size(u8 temp)
1183 {
1184         int i;
1185         struct aper_size_info_8 *values;
1186
1187         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1188
1189         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1190                 if (temp == values[i].size_value) {
1191                         agp_bridge->previous_size =
1192                                 agp_bridge->current_size = (void *) (values + i);
1193                         agp_bridge->aperture_size_idx = i;
1194                         return values[i].size;
1195                 }
1196         }
1197         return 0;
1198 }
1199
1200 static int intel_8xx_fetch_size(void)
1201 {
1202         u8 temp;
1203
1204         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1205         return __intel_8xx_fetch_size(temp);
1206 }
1207
1208 static int intel_815_fetch_size(void)
1209 {
1210         u8 temp;
1211
1212         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1213          * one non-reserved bit, so mask the others out ... */
1214         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1215         temp &= (1 << 3);
1216
1217         return __intel_8xx_fetch_size(temp);
1218 }
1219
1220 static void intel_tlbflush(struct agp_memory *mem)
1221 {
1222         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1223         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1224 }
1225
1226
1227 static void intel_8xx_tlbflush(struct agp_memory *mem)
1228 {
1229         u32 temp;
1230         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1231         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1232         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1233         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1234 }
1235
1236
1237 static void intel_cleanup(void)
1238 {
1239         u16 temp;
1240         struct aper_size_info_16 *previous_size;
1241
1242         previous_size = A_SIZE_16(agp_bridge->previous_size);
1243         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1244         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1245         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1246 }
1247
1248
1249 static void intel_8xx_cleanup(void)
1250 {
1251         u16 temp;
1252         struct aper_size_info_8 *previous_size;
1253
1254         previous_size = A_SIZE_8(agp_bridge->previous_size);
1255         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1256         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1257         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1258 }
1259
1260
1261 static int intel_configure(void)
1262 {
1263         u32 temp;
1264         u16 temp2;
1265         struct aper_size_info_16 *current_size;
1266
1267         current_size = A_SIZE_16(agp_bridge->current_size);
1268
1269         /* aperture size */
1270         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1271
1272         /* address to map to */
1273         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1274         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1275
1276         /* attbase - aperture base */
1277         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1278
1279         /* agpctrl */
1280         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1281
1282         /* paccfg/nbxcfg */
1283         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1284         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1285                         (temp2 & ~(1 << 10)) | (1 << 9));
1286         /* clear any possible error conditions */
1287         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1288         return 0;
1289 }
1290
1291 static int intel_815_configure(void)
1292 {
1293         u32 temp, addr;
1294         u8 temp2;
1295         struct aper_size_info_8 *current_size;
1296
1297         /* attbase - aperture base */
1298         /* the Intel 815 chipset spec. says that bits 29-31 in the
1299         * ATTBASE register are reserved -> try not to write them */
1300         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1301                 printk (KERN_EMERG PFX "gatt bus addr too high");
1302                 return -EINVAL;
1303         }
1304
1305         current_size = A_SIZE_8(agp_bridge->current_size);
1306
1307         /* aperture size */
1308         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1309                         current_size->size_value);
1310
1311         /* address to map to */
1312         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1313         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1314
1315         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1316         addr &= INTEL_815_ATTBASE_MASK;
1317         addr |= agp_bridge->gatt_bus_addr;
1318         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1319
1320         /* agpctrl */
1321         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1322
1323         /* apcont */
1324         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1325         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1326
1327         /* clear any possible error conditions */
1328         /* Oddness : this chipset seems to have no ERRSTS register ! */
1329         return 0;
1330 }
1331
1332 static void intel_820_tlbflush(struct agp_memory *mem)
1333 {
1334         return;
1335 }
1336
1337 static void intel_820_cleanup(void)
1338 {
1339         u8 temp;
1340         struct aper_size_info_8 *previous_size;
1341
1342         previous_size = A_SIZE_8(agp_bridge->previous_size);
1343         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1344         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1345                         temp & ~(1 << 1));
1346         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1347                         previous_size->size_value);
1348 }
1349
1350
1351 static int intel_820_configure(void)
1352 {
1353         u32 temp;
1354         u8 temp2;
1355         struct aper_size_info_8 *current_size;
1356
1357         current_size = A_SIZE_8(agp_bridge->current_size);
1358
1359         /* aperture size */
1360         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1361
1362         /* address to map to */
1363         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1364         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1365
1366         /* attbase - aperture base */
1367         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1368
1369         /* agpctrl */
1370         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1371
1372         /* global enable aperture access */
1373         /* This flag is not accessed through MCHCFG register as in */
1374         /* i850 chipset. */
1375         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1376         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1377         /* clear any possible AGP-related error conditions */
1378         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1379         return 0;
1380 }
1381
1382 static int intel_840_configure(void)
1383 {
1384         u32 temp;
1385         u16 temp2;
1386         struct aper_size_info_8 *current_size;
1387
1388         current_size = A_SIZE_8(agp_bridge->current_size);
1389
1390         /* aperture size */
1391         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1392
1393         /* address to map to */
1394         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1395         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1396
1397         /* attbase - aperture base */
1398         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1399
1400         /* agpctrl */
1401         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1402
1403         /* mcgcfg */
1404         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1405         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1406         /* clear any possible error conditions */
1407         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1408         return 0;
1409 }
1410
1411 static int intel_845_configure(void)
1412 {
1413         u32 temp;
1414         u8 temp2;
1415         struct aper_size_info_8 *current_size;
1416
1417         current_size = A_SIZE_8(agp_bridge->current_size);
1418
1419         /* aperture size */
1420         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1421
1422         if (agp_bridge->apbase_config != 0) {
1423                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1424                                        agp_bridge->apbase_config);
1425         } else {
1426                 /* address to map to */
1427                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1428                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1429                 agp_bridge->apbase_config = temp;
1430         }
1431
1432         /* attbase - aperture base */
1433         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1434
1435         /* agpctrl */
1436         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1437
1438         /* agpm */
1439         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1440         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1441         /* clear any possible error conditions */
1442         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1443
1444         intel_i830_setup_flush();
1445         return 0;
1446 }
1447
1448 static int intel_850_configure(void)
1449 {
1450         u32 temp;
1451         u16 temp2;
1452         struct aper_size_info_8 *current_size;
1453
1454         current_size = A_SIZE_8(agp_bridge->current_size);
1455
1456         /* aperture size */
1457         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1458
1459         /* address to map to */
1460         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1461         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1462
1463         /* attbase - aperture base */
1464         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1465
1466         /* agpctrl */
1467         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1468
1469         /* mcgcfg */
1470         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1471         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1472         /* clear any possible AGP-related error conditions */
1473         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1474         return 0;
1475 }
1476
1477 static int intel_860_configure(void)
1478 {
1479         u32 temp;
1480         u16 temp2;
1481         struct aper_size_info_8 *current_size;
1482
1483         current_size = A_SIZE_8(agp_bridge->current_size);
1484
1485         /* aperture size */
1486         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1487
1488         /* address to map to */
1489         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1490         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1491
1492         /* attbase - aperture base */
1493         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1494
1495         /* agpctrl */
1496         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1497
1498         /* mcgcfg */
1499         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1500         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1501         /* clear any possible AGP-related error conditions */
1502         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1503         return 0;
1504 }
1505
1506 static int intel_830mp_configure(void)
1507 {
1508         u32 temp;
1509         u16 temp2;
1510         struct aper_size_info_8 *current_size;
1511
1512         current_size = A_SIZE_8(agp_bridge->current_size);
1513
1514         /* aperture size */
1515         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1516
1517         /* address to map to */
1518         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1519         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1520
1521         /* attbase - aperture base */
1522         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1523
1524         /* agpctrl */
1525         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1526
1527         /* gmch */
1528         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1529         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1530         /* clear any possible AGP-related error conditions */
1531         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1532         return 0;
1533 }
1534
1535 static int intel_7505_configure(void)
1536 {
1537         u32 temp;
1538         u16 temp2;
1539         struct aper_size_info_8 *current_size;
1540
1541         current_size = A_SIZE_8(agp_bridge->current_size);
1542
1543         /* aperture size */
1544         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1545
1546         /* address to map to */
1547         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1548         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1549
1550         /* attbase - aperture base */
1551         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1552
1553         /* agpctrl */
1554         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1555
1556         /* mchcfg */
1557         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1558         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1559
1560         return 0;
1561 }
1562
1563 /* Setup function */
1564 static const struct gatt_mask intel_generic_masks[] =
1565 {
1566         {.mask = 0x00000017, .type = 0}
1567 };
1568
1569 static const struct aper_size_info_8 intel_815_sizes[2] =
1570 {
1571         {64, 16384, 4, 0},
1572         {32, 8192, 3, 8},
1573 };
1574
1575 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1576 {
1577         {256, 65536, 6, 0},
1578         {128, 32768, 5, 32},
1579         {64, 16384, 4, 48},
1580         {32, 8192, 3, 56},
1581         {16, 4096, 2, 60},
1582         {8, 2048, 1, 62},
1583         {4, 1024, 0, 63}
1584 };
1585
1586 static const struct aper_size_info_16 intel_generic_sizes[7] =
1587 {
1588         {256, 65536, 6, 0},
1589         {128, 32768, 5, 32},
1590         {64, 16384, 4, 48},
1591         {32, 8192, 3, 56},
1592         {16, 4096, 2, 60},
1593         {8, 2048, 1, 62},
1594         {4, 1024, 0, 63}
1595 };
1596
1597 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1598 {
1599         {256, 65536, 6, 0},
1600         {128, 32768, 5, 32},
1601         {64, 16384, 4, 48},
1602         {32, 8192, 3, 56}
1603 };
1604
1605 static const struct agp_bridge_driver intel_generic_driver = {
1606         .owner                  = THIS_MODULE,
1607         .aperture_sizes         = intel_generic_sizes,
1608         .size_type              = U16_APER_SIZE,
1609         .num_aperture_sizes     = 7,
1610         .configure              = intel_configure,
1611         .fetch_size             = intel_fetch_size,
1612         .cleanup                = intel_cleanup,
1613         .tlb_flush              = intel_tlbflush,
1614         .mask_memory            = agp_generic_mask_memory,
1615         .masks                  = intel_generic_masks,
1616         .agp_enable             = agp_generic_enable,
1617         .cache_flush            = global_cache_flush,
1618         .create_gatt_table      = agp_generic_create_gatt_table,
1619         .free_gatt_table        = agp_generic_free_gatt_table,
1620         .insert_memory          = agp_generic_insert_memory,
1621         .remove_memory          = agp_generic_remove_memory,
1622         .alloc_by_type          = agp_generic_alloc_by_type,
1623         .free_by_type           = agp_generic_free_by_type,
1624         .agp_alloc_page         = agp_generic_alloc_page,
1625         .agp_destroy_page       = agp_generic_destroy_page,
1626         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1627 };
1628
1629 static const struct agp_bridge_driver intel_810_driver = {
1630         .owner                  = THIS_MODULE,
1631         .aperture_sizes         = intel_i810_sizes,
1632         .size_type              = FIXED_APER_SIZE,
1633         .num_aperture_sizes     = 2,
1634         .needs_scratch_page     = TRUE,
1635         .configure              = intel_i810_configure,
1636         .fetch_size             = intel_i810_fetch_size,
1637         .cleanup                = intel_i810_cleanup,
1638         .tlb_flush              = intel_i810_tlbflush,
1639         .mask_memory            = intel_i810_mask_memory,
1640         .masks                  = intel_i810_masks,
1641         .agp_enable             = intel_i810_agp_enable,
1642         .cache_flush            = global_cache_flush,
1643         .create_gatt_table      = agp_generic_create_gatt_table,
1644         .free_gatt_table        = agp_generic_free_gatt_table,
1645         .insert_memory          = intel_i810_insert_entries,
1646         .remove_memory          = intel_i810_remove_entries,
1647         .alloc_by_type          = intel_i810_alloc_by_type,
1648         .free_by_type           = intel_i810_free_by_type,
1649         .agp_alloc_page         = agp_generic_alloc_page,
1650         .agp_destroy_page       = agp_generic_destroy_page,
1651         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1652 };
1653
1654 static const struct agp_bridge_driver intel_815_driver = {
1655         .owner                  = THIS_MODULE,
1656         .aperture_sizes         = intel_815_sizes,
1657         .size_type              = U8_APER_SIZE,
1658         .num_aperture_sizes     = 2,
1659         .configure              = intel_815_configure,
1660         .fetch_size             = intel_815_fetch_size,
1661         .cleanup                = intel_8xx_cleanup,
1662         .tlb_flush              = intel_8xx_tlbflush,
1663         .mask_memory            = agp_generic_mask_memory,
1664         .masks                  = intel_generic_masks,
1665         .agp_enable             = agp_generic_enable,
1666         .cache_flush            = global_cache_flush,
1667         .create_gatt_table      = agp_generic_create_gatt_table,
1668         .free_gatt_table        = agp_generic_free_gatt_table,
1669         .insert_memory          = agp_generic_insert_memory,
1670         .remove_memory          = agp_generic_remove_memory,
1671         .alloc_by_type          = agp_generic_alloc_by_type,
1672         .free_by_type           = agp_generic_free_by_type,
1673         .agp_alloc_page         = agp_generic_alloc_page,
1674         .agp_destroy_page       = agp_generic_destroy_page,
1675         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1676 };
1677
1678 static const struct agp_bridge_driver intel_830_driver = {
1679         .owner                  = THIS_MODULE,
1680         .aperture_sizes         = intel_i830_sizes,
1681         .size_type              = FIXED_APER_SIZE,
1682         .num_aperture_sizes     = 4,
1683         .needs_scratch_page     = TRUE,
1684         .configure              = intel_i830_configure,
1685         .fetch_size             = intel_i830_fetch_size,
1686         .cleanup                = intel_i830_cleanup,
1687         .tlb_flush              = intel_i810_tlbflush,
1688         .mask_memory            = intel_i810_mask_memory,
1689         .masks                  = intel_i810_masks,
1690         .agp_enable             = intel_i810_agp_enable,
1691         .cache_flush            = global_cache_flush,
1692         .create_gatt_table      = intel_i830_create_gatt_table,
1693         .free_gatt_table        = intel_i830_free_gatt_table,
1694         .insert_memory          = intel_i830_insert_entries,
1695         .remove_memory          = intel_i830_remove_entries,
1696         .alloc_by_type          = intel_i830_alloc_by_type,
1697         .free_by_type           = intel_i810_free_by_type,
1698         .agp_alloc_page         = agp_generic_alloc_page,
1699         .agp_destroy_page       = agp_generic_destroy_page,
1700         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1701         .chipset_flush          = intel_i830_chipset_flush,
1702 };
1703
1704 static const struct agp_bridge_driver intel_820_driver = {
1705         .owner                  = THIS_MODULE,
1706         .aperture_sizes         = intel_8xx_sizes,
1707         .size_type              = U8_APER_SIZE,
1708         .num_aperture_sizes     = 7,
1709         .configure              = intel_820_configure,
1710         .fetch_size             = intel_8xx_fetch_size,
1711         .cleanup                = intel_820_cleanup,
1712         .tlb_flush              = intel_820_tlbflush,
1713         .mask_memory            = agp_generic_mask_memory,
1714         .masks                  = intel_generic_masks,
1715         .agp_enable             = agp_generic_enable,
1716         .cache_flush            = global_cache_flush,
1717         .create_gatt_table      = agp_generic_create_gatt_table,
1718         .free_gatt_table        = agp_generic_free_gatt_table,
1719         .insert_memory          = agp_generic_insert_memory,
1720         .remove_memory          = agp_generic_remove_memory,
1721         .alloc_by_type          = agp_generic_alloc_by_type,
1722         .free_by_type           = agp_generic_free_by_type,
1723         .agp_alloc_page         = agp_generic_alloc_page,
1724         .agp_destroy_page       = agp_generic_destroy_page,
1725         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1726 };
1727
1728 static const struct agp_bridge_driver intel_830mp_driver = {
1729         .owner                  = THIS_MODULE,
1730         .aperture_sizes         = intel_830mp_sizes,
1731         .size_type              = U8_APER_SIZE,
1732         .num_aperture_sizes     = 4,
1733         .configure              = intel_830mp_configure,
1734         .fetch_size             = intel_8xx_fetch_size,
1735         .cleanup                = intel_8xx_cleanup,
1736         .tlb_flush              = intel_8xx_tlbflush,
1737         .mask_memory            = agp_generic_mask_memory,
1738         .masks                  = intel_generic_masks,
1739         .agp_enable             = agp_generic_enable,
1740         .cache_flush            = global_cache_flush,
1741         .create_gatt_table      = agp_generic_create_gatt_table,
1742         .free_gatt_table        = agp_generic_free_gatt_table,
1743         .insert_memory          = agp_generic_insert_memory,
1744         .remove_memory          = agp_generic_remove_memory,
1745         .alloc_by_type          = agp_generic_alloc_by_type,
1746         .free_by_type           = agp_generic_free_by_type,
1747         .agp_alloc_page         = agp_generic_alloc_page,
1748         .agp_destroy_page       = agp_generic_destroy_page,
1749         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1750 };
1751
1752 static const struct agp_bridge_driver intel_840_driver = {
1753         .owner                  = THIS_MODULE,
1754         .aperture_sizes         = intel_8xx_sizes,
1755         .size_type              = U8_APER_SIZE,
1756         .num_aperture_sizes     = 7,
1757         .configure              = intel_840_configure,
1758         .fetch_size             = intel_8xx_fetch_size,
1759         .cleanup                = intel_8xx_cleanup,
1760         .tlb_flush              = intel_8xx_tlbflush,
1761         .mask_memory            = agp_generic_mask_memory,
1762         .masks                  = intel_generic_masks,
1763         .agp_enable             = agp_generic_enable,
1764         .cache_flush            = global_cache_flush,
1765         .create_gatt_table      = agp_generic_create_gatt_table,
1766         .free_gatt_table        = agp_generic_free_gatt_table,
1767         .insert_memory          = agp_generic_insert_memory,
1768         .remove_memory          = agp_generic_remove_memory,
1769         .alloc_by_type          = agp_generic_alloc_by_type,
1770         .free_by_type           = agp_generic_free_by_type,
1771         .agp_alloc_page         = agp_generic_alloc_page,
1772         .agp_destroy_page       = agp_generic_destroy_page,
1773         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1774 };
1775
1776 static const struct agp_bridge_driver intel_845_driver = {
1777         .owner                  = THIS_MODULE,
1778         .aperture_sizes         = intel_8xx_sizes,
1779         .size_type              = U8_APER_SIZE,
1780         .num_aperture_sizes     = 7,
1781         .configure              = intel_845_configure,
1782         .fetch_size             = intel_8xx_fetch_size,
1783         .cleanup                = intel_8xx_cleanup,
1784         .tlb_flush              = intel_8xx_tlbflush,
1785         .mask_memory            = agp_generic_mask_memory,
1786         .masks                  = intel_generic_masks,
1787         .agp_enable             = agp_generic_enable,
1788         .cache_flush            = global_cache_flush,
1789         .create_gatt_table      = agp_generic_create_gatt_table,
1790         .free_gatt_table        = agp_generic_free_gatt_table,
1791         .insert_memory          = agp_generic_insert_memory,
1792         .remove_memory          = agp_generic_remove_memory,
1793         .alloc_by_type          = agp_generic_alloc_by_type,
1794         .free_by_type           = agp_generic_free_by_type,
1795         .agp_alloc_page         = agp_generic_alloc_page,
1796         .agp_destroy_page       = agp_generic_destroy_page,
1797         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1798         .chipset_flush          = intel_i830_chipset_flush,
1799 };
1800
1801 static const struct agp_bridge_driver intel_850_driver = {
1802         .owner                  = THIS_MODULE,
1803         .aperture_sizes         = intel_8xx_sizes,
1804         .size_type              = U8_APER_SIZE,
1805         .num_aperture_sizes     = 7,
1806         .configure              = intel_850_configure,
1807         .fetch_size             = intel_8xx_fetch_size,
1808         .cleanup                = intel_8xx_cleanup,
1809         .tlb_flush              = intel_8xx_tlbflush,
1810         .mask_memory            = agp_generic_mask_memory,
1811         .masks                  = intel_generic_masks,
1812         .agp_enable             = agp_generic_enable,
1813         .cache_flush            = global_cache_flush,
1814         .create_gatt_table      = agp_generic_create_gatt_table,
1815         .free_gatt_table        = agp_generic_free_gatt_table,
1816         .insert_memory          = agp_generic_insert_memory,
1817         .remove_memory          = agp_generic_remove_memory,
1818         .alloc_by_type          = agp_generic_alloc_by_type,
1819         .free_by_type           = agp_generic_free_by_type,
1820         .agp_alloc_page         = agp_generic_alloc_page,
1821         .agp_destroy_page       = agp_generic_destroy_page,
1822         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1823 };
1824
1825 static const struct agp_bridge_driver intel_860_driver = {
1826         .owner                  = THIS_MODULE,
1827         .aperture_sizes         = intel_8xx_sizes,
1828         .size_type              = U8_APER_SIZE,
1829         .num_aperture_sizes     = 7,
1830         .configure              = intel_860_configure,
1831         .fetch_size             = intel_8xx_fetch_size,
1832         .cleanup                = intel_8xx_cleanup,
1833         .tlb_flush              = intel_8xx_tlbflush,
1834         .mask_memory            = agp_generic_mask_memory,
1835         .masks                  = intel_generic_masks,
1836         .agp_enable             = agp_generic_enable,
1837         .cache_flush            = global_cache_flush,
1838         .create_gatt_table      = agp_generic_create_gatt_table,
1839         .free_gatt_table        = agp_generic_free_gatt_table,
1840         .insert_memory          = agp_generic_insert_memory,
1841         .remove_memory          = agp_generic_remove_memory,
1842         .alloc_by_type          = agp_generic_alloc_by_type,
1843         .free_by_type           = agp_generic_free_by_type,
1844         .agp_alloc_page         = agp_generic_alloc_page,
1845         .agp_destroy_page       = agp_generic_destroy_page,
1846         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1847 };
1848
1849 static const struct agp_bridge_driver intel_915_driver = {
1850         .owner                  = THIS_MODULE,
1851         .aperture_sizes         = intel_i830_sizes,
1852         .size_type              = FIXED_APER_SIZE,
1853         .num_aperture_sizes     = 4,
1854         .needs_scratch_page     = TRUE,
1855         .configure              = intel_i915_configure,
1856         .fetch_size             = intel_i9xx_fetch_size,
1857         .cleanup                = intel_i915_cleanup,
1858         .tlb_flush              = intel_i810_tlbflush,
1859         .mask_memory            = intel_i810_mask_memory,
1860         .masks                  = intel_i810_masks,
1861         .agp_enable             = intel_i810_agp_enable,
1862         .cache_flush            = global_cache_flush,
1863         .create_gatt_table      = intel_i915_create_gatt_table,
1864         .free_gatt_table        = intel_i830_free_gatt_table,
1865         .insert_memory          = intel_i915_insert_entries,
1866         .remove_memory          = intel_i915_remove_entries,
1867         .alloc_by_type          = intel_i830_alloc_by_type,
1868         .free_by_type           = intel_i810_free_by_type,
1869         .agp_alloc_page         = agp_generic_alloc_page,
1870         .agp_destroy_page       = agp_generic_destroy_page,
1871         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1872         .chipset_flush          = intel_i915_chipset_flush,
1873 };
1874
1875 static const struct agp_bridge_driver intel_i965_driver = {
1876        .owner                  = THIS_MODULE,
1877        .aperture_sizes         = intel_i830_sizes,
1878        .size_type              = FIXED_APER_SIZE,
1879        .num_aperture_sizes     = 4,
1880        .needs_scratch_page     = TRUE,
1881        .configure              = intel_i915_configure,
1882        .fetch_size             = intel_i9xx_fetch_size,
1883        .cleanup                = intel_i915_cleanup,
1884        .tlb_flush              = intel_i810_tlbflush,
1885        .mask_memory            = intel_i965_mask_memory,
1886        .masks                  = intel_i810_masks,
1887        .agp_enable             = intel_i810_agp_enable,
1888        .cache_flush            = global_cache_flush,
1889        .create_gatt_table      = intel_i965_create_gatt_table,
1890        .free_gatt_table        = intel_i830_free_gatt_table,
1891        .insert_memory          = intel_i915_insert_entries,
1892        .remove_memory          = intel_i915_remove_entries,
1893        .alloc_by_type          = intel_i830_alloc_by_type,
1894        .free_by_type           = intel_i810_free_by_type,
1895        .agp_alloc_page         = agp_generic_alloc_page,
1896        .agp_destroy_page       = agp_generic_destroy_page,
1897        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1898         .chipset_flush          = intel_i915_chipset_flush,
1899 };
1900
1901 static const struct agp_bridge_driver intel_7505_driver = {
1902         .owner                  = THIS_MODULE,
1903         .aperture_sizes         = intel_8xx_sizes,
1904         .size_type              = U8_APER_SIZE,
1905         .num_aperture_sizes     = 7,
1906         .configure              = intel_7505_configure,
1907         .fetch_size             = intel_8xx_fetch_size,
1908         .cleanup                = intel_8xx_cleanup,
1909         .tlb_flush              = intel_8xx_tlbflush,
1910         .mask_memory            = agp_generic_mask_memory,
1911         .masks                  = intel_generic_masks,
1912         .agp_enable             = agp_generic_enable,
1913         .cache_flush            = global_cache_flush,
1914         .create_gatt_table      = agp_generic_create_gatt_table,
1915         .free_gatt_table        = agp_generic_free_gatt_table,
1916         .insert_memory          = agp_generic_insert_memory,
1917         .remove_memory          = agp_generic_remove_memory,
1918         .alloc_by_type          = agp_generic_alloc_by_type,
1919         .free_by_type           = agp_generic_free_by_type,
1920         .agp_alloc_page         = agp_generic_alloc_page,
1921         .agp_destroy_page       = agp_generic_destroy_page,
1922         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1923 };
1924
1925 static const struct agp_bridge_driver intel_g33_driver = {
1926         .owner                  = THIS_MODULE,
1927         .aperture_sizes         = intel_i830_sizes,
1928         .size_type              = FIXED_APER_SIZE,
1929         .num_aperture_sizes     = 4,
1930         .needs_scratch_page     = TRUE,
1931         .configure              = intel_i915_configure,
1932         .fetch_size             = intel_i9xx_fetch_size,
1933         .cleanup                = intel_i915_cleanup,
1934         .tlb_flush              = intel_i810_tlbflush,
1935         .mask_memory            = intel_i965_mask_memory,
1936         .masks                  = intel_i810_masks,
1937         .agp_enable             = intel_i810_agp_enable,
1938         .cache_flush            = global_cache_flush,
1939         .create_gatt_table      = intel_i915_create_gatt_table,
1940         .free_gatt_table        = intel_i830_free_gatt_table,
1941         .insert_memory          = intel_i915_insert_entries,
1942         .remove_memory          = intel_i915_remove_entries,
1943         .alloc_by_type          = intel_i830_alloc_by_type,
1944         .free_by_type           = intel_i810_free_by_type,
1945         .agp_alloc_page         = agp_generic_alloc_page,
1946         .agp_destroy_page       = agp_generic_destroy_page,
1947         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1948         .chipset_flush          = intel_i915_chipset_flush,
1949 };
1950
1951 static int find_gmch(u16 device)
1952 {
1953         struct pci_dev *gmch_device;
1954
1955         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1956         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1957                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1958                                 device, gmch_device);
1959         }
1960
1961         if (!gmch_device)
1962                 return 0;
1963
1964         intel_private.pcidev = gmch_device;
1965         return 1;
1966 }
1967
1968 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1969  * driver and gmch_driver must be non-null, and find_gmch will determine
1970  * which one should be used if a gmch_chip_id is present.
1971  */
1972 static const struct intel_driver_description {
1973         unsigned int chip_id;
1974         unsigned int gmch_chip_id;
1975         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
1976         char *name;
1977         const struct agp_bridge_driver *driver;
1978         const struct agp_bridge_driver *gmch_driver;
1979 } intel_agp_chipsets[] = {
1980         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1981         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
1982         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
1983         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
1984                 NULL, &intel_810_driver },
1985         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
1986                 NULL, &intel_810_driver },
1987         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
1988                 NULL, &intel_810_driver },
1989         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
1990                 &intel_815_driver, &intel_810_driver },
1991         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
1992         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
1993         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
1994                 &intel_830mp_driver, &intel_830_driver },
1995         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
1996         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
1997         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
1998                 &intel_845_driver, &intel_830_driver },
1999         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2000         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2001         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2002                 &intel_845_driver, &intel_830_driver },
2003         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2004         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2005                 &intel_845_driver, &intel_830_driver },
2006         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2007         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2008                 NULL, &intel_915_driver },
2009         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2010                 NULL, &intel_915_driver },
2011         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2012                 NULL, &intel_915_driver },
2013         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2014                 NULL, &intel_915_driver },
2015         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2016                 NULL, &intel_915_driver },
2017         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2018                 NULL, &intel_915_driver },
2019         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2020                 NULL, &intel_i965_driver },
2021         { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
2022                 NULL, &intel_i965_driver },
2023         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2024                 NULL, &intel_i965_driver },
2025         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2026                 NULL, &intel_i965_driver },
2027         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2028                 NULL, &intel_i965_driver },
2029         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2030                 NULL, &intel_i965_driver },
2031         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2032         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2033         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2034                 NULL, &intel_g33_driver },
2035         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2036                 NULL, &intel_g33_driver },
2037         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2038                 NULL, &intel_g33_driver },
2039         { 0, 0, 0, NULL, NULL, NULL }
2040 };
2041
2042 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2043                                      const struct pci_device_id *ent)
2044 {
2045         struct agp_bridge_data *bridge;
2046         u8 cap_ptr = 0;
2047         struct resource *r;
2048         int i;
2049
2050         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2051
2052         bridge = agp_alloc_bridge();
2053         if (!bridge)
2054                 return -ENOMEM;
2055
2056         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2057                 /* In case that multiple models of gfx chip may
2058                    stand on same host bridge type, this can be
2059                    sure we detect the right IGD. */
2060                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2061                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2062                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2063                                 bridge->driver =
2064                                         intel_agp_chipsets[i].gmch_driver;
2065                                 break;
2066                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2067                                 continue;
2068                         } else {
2069                                 bridge->driver = intel_agp_chipsets[i].driver;
2070                                 break;
2071                         }
2072                 }
2073         }
2074
2075         if (intel_agp_chipsets[i].name == NULL) {
2076                 if (cap_ptr)
2077                         printk(KERN_WARNING PFX "Unsupported Intel chipset"
2078                                "(device id: %04x)\n", pdev->device);
2079                 agp_put_bridge(bridge);
2080                 return -ENODEV;
2081         }
2082
2083         if (bridge->driver == NULL) {
2084                 /* bridge has no AGP and no IGD detected */
2085                 if (cap_ptr)
2086                         printk(KERN_WARNING PFX "Failed to find bridge device "
2087                                 "(chip_id: %04x)\n",
2088                                 intel_agp_chipsets[i].gmch_chip_id);
2089                 agp_put_bridge(bridge);
2090                 return -ENODEV;
2091         }
2092
2093         bridge->dev = pdev;
2094         bridge->capndx = cap_ptr;
2095         bridge->dev_private_data = &intel_private;
2096
2097         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
2098                 intel_agp_chipsets[i].name);
2099
2100         /*
2101         * The following fixes the case where the BIOS has "forgotten" to
2102         * provide an address range for the GART.
2103         * 20030610 - hamish@zot.org
2104         */
2105         r = &pdev->resource[0];
2106         if (!r->start && r->end) {
2107                 if (pci_assign_resource(pdev, 0)) {
2108                         printk(KERN_ERR PFX "could not assign resource 0\n");
2109                         agp_put_bridge(bridge);
2110                         return -ENODEV;
2111                 }
2112         }
2113
2114         /*
2115         * If the device has not been properly setup, the following will catch
2116         * the problem and should stop the system from crashing.
2117         * 20030610 - hamish@zot.org
2118         */
2119         if (pci_enable_device(pdev)) {
2120                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
2121                 agp_put_bridge(bridge);
2122                 return -ENODEV;
2123         }
2124
2125         /* Fill in the mode register */
2126         if (cap_ptr) {
2127                 pci_read_config_dword(pdev,
2128                                 bridge->capndx+PCI_AGP_STATUS,
2129                                 &bridge->mode);
2130         }
2131
2132         pci_set_drvdata(pdev, bridge);
2133         return agp_add_bridge(bridge);
2134 }
2135
2136 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2137 {
2138         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2139
2140         agp_remove_bridge(bridge);
2141
2142         if (intel_private.pcidev)
2143                 pci_dev_put(intel_private.pcidev);
2144
2145         agp_put_bridge(bridge);
2146 }
2147
2148 #ifdef CONFIG_PM
2149 static int agp_intel_resume(struct pci_dev *pdev)
2150 {
2151         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2152
2153         pci_restore_state(pdev);
2154
2155         /* We should restore our graphics device's config space,
2156          * as host bridge (00:00) resumes before graphics device (02:00),
2157          * then our access to its pci space can work right.
2158          */
2159         if (intel_private.pcidev)
2160                 pci_restore_state(intel_private.pcidev);
2161
2162         if (bridge->driver == &intel_generic_driver)
2163                 intel_configure();
2164         else if (bridge->driver == &intel_850_driver)
2165                 intel_850_configure();
2166         else if (bridge->driver == &intel_845_driver)
2167                 intel_845_configure();
2168         else if (bridge->driver == &intel_830mp_driver)
2169                 intel_830mp_configure();
2170         else if (bridge->driver == &intel_915_driver)
2171                 intel_i915_configure();
2172         else if (bridge->driver == &intel_830_driver)
2173                 intel_i830_configure();
2174         else if (bridge->driver == &intel_810_driver)
2175                 intel_i810_configure();
2176         else if (bridge->driver == &intel_i965_driver)
2177                 intel_i915_configure();
2178
2179         return 0;
2180 }
2181 #endif
2182
2183 static struct pci_device_id agp_intel_pci_table[] = {
2184 #define ID(x)                                           \
2185         {                                               \
2186         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2187         .class_mask     = ~0,                           \
2188         .vendor         = PCI_VENDOR_ID_INTEL,          \
2189         .device         = x,                            \
2190         .subvendor      = PCI_ANY_ID,                   \
2191         .subdevice      = PCI_ANY_ID,                   \
2192         }
2193         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2194         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2195         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2196         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2197         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2198         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2199         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2200         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2201         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2202         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2203         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2204         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2205         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2206         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2207         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2208         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2209         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2210         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2211         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2212         ID(PCI_DEVICE_ID_INTEL_7505_0),
2213         ID(PCI_DEVICE_ID_INTEL_7205_0),
2214         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2215         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2216         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2217         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2218         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2219         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2220         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2221         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2222         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2223         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2224         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2225         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2226         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2227         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2228         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2229         { }
2230 };
2231
2232 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2233
2234 static struct pci_driver agp_intel_pci_driver = {
2235         .name           = "agpgart-intel",
2236         .id_table       = agp_intel_pci_table,
2237         .probe          = agp_intel_probe,
2238         .remove         = __devexit_p(agp_intel_remove),
2239 #ifdef CONFIG_PM
2240         .resume         = agp_intel_resume,
2241 #endif
2242 };
2243
2244 static int __init agp_intel_init(void)
2245 {
2246         if (agp_off)
2247                 return -EINVAL;
2248         return pci_register_driver(&agp_intel_pci_driver);
2249 }
2250
2251 static void __exit agp_intel_cleanup(void)
2252 {
2253         pci_unregister_driver(&agp_intel_pci_driver);
2254 }
2255
2256 module_init(agp_intel_init);
2257 module_exit(agp_intel_cleanup);
2258
2259 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2260 MODULE_LICENSE("GPL and additional rights");