Pileus Git - ~andy/linux/blob - drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/bitops.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/delay.h>
  24 #include <linux/errno.h>
  25 #include <linux/fs.h>
  26 #include <linux/genhd.h>
  27 #include <linux/idr.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kdev_t.h>
  32 #include <linux/kthread.h>
  33 #include <linux/kernel.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/pci.h>
  38 #include <linux/poison.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/version.h>
  43
  44 #define NVME_Q_DEPTH 1024
  45 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  46 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  47 #define NVME_MINORS 64
  48 #define NVME_IO_TIMEOUT (5 * HZ)
  49 #define ADMIN_TIMEOUT   (60 * HZ)
  50
  51 static int nvme_major;
  52 module_param(nvme_major, int, 0);
  53
  54 static int use_threaded_interrupts;
  55 module_param(use_threaded_interrupts, int, 0);
  56
  57 static DEFINE_SPINLOCK(dev_list_lock);
  58 static LIST_HEAD(dev_list);
  59 static struct task_struct *nvme_thread;
  60
  61 /*
  62  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  63  */
  64 struct nvme_dev {
  65         struct list_head node;
  66         struct nvme_queue **queues;
  67         u32 __iomem *dbs;
  68         struct pci_dev *pci_dev;
  69         struct dma_pool *prp_page_pool;
  70         struct dma_pool *prp_small_pool;
  71         int instance;
  72         int queue_count;
  73         int db_stride;
  74         u32 ctrl_config;
  75         struct msix_entry *entry;
  76         struct nvme_bar __iomem *bar;
  77         struct list_head namespaces;
  78         char serial[20];
  79         char model[40];
  80         char firmware_rev[8];
  81         u32 max_hw_sectors;
  82 };
  83
  84 /*
  85  * An NVM Express namespace is equivalent to a SCSI LUN
  86  */
  87 struct nvme_ns {
  88         struct list_head list;
  89
  90         struct nvme_dev *dev;
  91         struct request_queue *queue;
  92         struct gendisk *disk;
  93
  94         int ns_id;
  95         int lba_shift;
  96 };
  97
  98 /*
  99  * An NVM Express queue.  Each device has at least two (one for admin
 100  * commands and one for I/O commands).
 101  */
 102 struct nvme_queue {
 103         struct device *q_dmadev;
 104         struct nvme_dev *dev;
 105         spinlock_t q_lock;
 106         struct nvme_command *sq_cmds;
 107         volatile struct nvme_completion *cqes;
 108         dma_addr_t sq_dma_addr;
 109         dma_addr_t cq_dma_addr;
 110         wait_queue_head_t sq_full;
 111         wait_queue_t sq_cong_wait;
 112         struct bio_list sq_cong;
 113         u32 __iomem *q_db;
 114         u16 q_depth;
 115         u16 cq_vector;
 116         u16 sq_head;
 117         u16 sq_tail;
 118         u16 cq_head;
 119         u16 cq_phase;
 120         unsigned long cmdid_data[];
 121 };
 122
 123 /*
 124  * Check we didin't inadvertently grow the command struct
 125  */
 126 static inline void _nvme_check_size(void)
 127 {
 128         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 130         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 131         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 132         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 133         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 134         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 135         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 136         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 137 }
 138
 139 typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
 140                                                 struct nvme_completion *);
 141
 142 struct nvme_cmd_info {
 143         nvme_completion_fn fn;
 144         void *ctx;
 145         unsigned long timeout;
 146 };
 147
 148 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 149 {
 150         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 151 }
 152
 153 /**
 154  * alloc_cmdid() - Allocate a Command ID
 155  * @nvmeq: The queue that will be used for this command
 156  * @ctx: A pointer that will be passed to the handler
 157  * @handler: The function to call on completion
 158  *
 159  * Allocate a Command ID for a queue.  The data passed in will
 160  * be passed to the completion handler.  This is implemented by using
 161  * the bottom two bits of the ctx pointer to store the handler ID.
 162  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 163  * We can change this if it becomes a problem.
 164  *
 165  * May be called with local interrupts disabled and the q_lock held,
 166  * or with interrupts enabled and no locks held.
 167  */
 168 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
 169                                 nvme_completion_fn handler, unsigned timeout)
 170 {
 171         int depth = nvmeq->q_depth - 1;
 172         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 173         int cmdid;
 174
 175         do {
 176                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 177                 if (cmdid >= depth)
 178                         return -EBUSY;
 179         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 180
 181         info[cmdid].fn = handler;
 182         info[cmdid].ctx = ctx;
 183         info[cmdid].timeout = jiffies + timeout;
 184         return cmdid;
 185 }
 186
 187 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 188                                 nvme_completion_fn handler, unsigned timeout)
 189 {
 190         int cmdid;
 191         wait_event_killable(nvmeq->sq_full,
 192                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 193         return (cmdid < 0) ? -EINTR : cmdid;
 194 }
 195
 196 /* Special values must be less than 0x1000 */
 197 #define CMD_CTX_BASE            ((void *)POISON_POINTER_DELTA)
 198 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 199 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 200 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 201 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
 202
 203 static void special_completion(struct nvme_dev *dev, void *ctx,
 204                                                 struct nvme_completion *cqe)
 205 {
 206         if (ctx == CMD_CTX_CANCELLED)
 207                 return;
 208         if (ctx == CMD_CTX_FLUSH)
 209                 return;
 210         if (ctx == CMD_CTX_COMPLETED) {
 211                 dev_warn(&dev->pci_dev->dev,
 212                                 "completed id %d twice on queue %d\n",
 213                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 214                 return;
 215         }
 216         if (ctx == CMD_CTX_INVALID) {
 217                 dev_warn(&dev->pci_dev->dev,
 218                                 "invalid id %d completed on queue %d\n",
 219                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 220                 return;
 221         }
 222
 223         dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
 224 }
 225
 226 /*
 227  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 228  */
 229 static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
 230                                                 nvme_completion_fn *fn)
 231 {
 232         void *ctx;
 233         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 234
 235         if (cmdid >= nvmeq->q_depth) {
 236                 *fn = special_completion;
 237                 return CMD_CTX_INVALID;
 238         }
 239         *fn = info[cmdid].fn;
 240         ctx = info[cmdid].ctx;
 241         info[cmdid].fn = special_completion;
 242         info[cmdid].ctx = CMD_CTX_COMPLETED;
 243         clear_bit(cmdid, nvmeq->cmdid_data);
 244         wake_up(&nvmeq->sq_full);
 245         return ctx;
 246 }
 247
 248 static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
 249                                                 nvme_completion_fn *fn)
 250 {
 251         void *ctx;
 252         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 253         if (fn)
 254                 *fn = info[cmdid].fn;
 255         ctx = info[cmdid].ctx;
 256         info[cmdid].fn = special_completion;
 257         info[cmdid].ctx = CMD_CTX_CANCELLED;
 258         return ctx;
 259 }
 260
 261 static struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
 262 {
 263         return dev->queues[get_cpu() + 1];
 264 }
 265
 266 static void put_nvmeq(struct nvme_queue *nvmeq)
 267 {
 268         put_cpu();
 269 }
 270
 271 /**
 272  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 273  * @nvmeq: The queue to use
 274  * @cmd: The command to send
 275  *
 276  * Safe to use from interrupt context
 277  */
 278 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 279 {
 280         unsigned long flags;
 281         u16 tail;
 282         spin_lock_irqsave(&nvmeq->q_lock, flags);
 283         tail = nvmeq->sq_tail;
 284         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 285         if (++tail == nvmeq->q_depth)
 286                 tail = 0;
 287         writel(tail, nvmeq->q_db);
 288         nvmeq->sq_tail = tail;
 289         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 290
 291         return 0;
 292 }
 293
 294 /*
 295  * The nvme_iod describes the data in an I/O, including the list of PRP
 296  * entries.  You can't see it in this data structure because C doesn't let
 297  * me express that.  Use nvme_alloc_iod to ensure there's enough space
 298  * allocated to store the PRP list.
 299  */
 300 struct nvme_iod {
 301         void *private;          /* For the use of the submitter of the I/O */
 302         int npages;             /* In the PRP list. 0 means small pool in use */
 303         int offset;             /* Of PRP list */
 304         int nents;              /* Used in scatterlist */
 305         int length;             /* Of data, in bytes */
 306         dma_addr_t first_dma;
 307         struct scatterlist sg[0];
 308 };
 309
 310 static __le64 **iod_list(struct nvme_iod *iod)
 311 {
 312         return ((void *)iod) + iod->offset;
 313 }
 314
 315 /*
 316  * Will slightly overestimate the number of pages needed.  This is OK
 317  * as it only leads to a small amount of wasted memory for the lifetime of
 318  * the I/O.
 319  */
 320 static int nvme_npages(unsigned size)
 321 {
 322         unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
 323         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 324 }
 325
 326 static struct nvme_iod *
 327 nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
 328 {
 329         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
 330                                 sizeof(__le64 *) * nvme_npages(nbytes) +
 331                                 sizeof(struct scatterlist) * nseg, gfp);
 332
 333         if (iod) {
 334                 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
 335                 iod->npages = -1;
 336                 iod->length = nbytes;
 337         }
 338
 339         return iod;
 340 }
 341
 342 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
 343 {
 344         const int last_prp = PAGE_SIZE / 8 - 1;
 345         int i;
 346         __le64 **list = iod_list(iod);
 347         dma_addr_t prp_dma = iod->first_dma;
 348
 349         if (iod->npages == 0)
 350                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 351         for (i = 0; i < iod->npages; i++) {
 352                 __le64 *prp_list = list[i];
 353                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 354                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 355                 prp_dma = next_prp_dma;
 356         }
 357         kfree(iod);
 358 }
 359
 360 static void requeue_bio(struct nvme_dev *dev, struct bio *bio)
 361 {
 362         struct nvme_queue *nvmeq = get_nvmeq(dev);
 363         if (bio_list_empty(&nvmeq->sq_cong))
 364                 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 365         bio_list_add(&nvmeq->sq_cong, bio);
 366         put_nvmeq(nvmeq);
 367         wake_up_process(nvme_thread);
 368 }
 369
 370 static void bio_completion(struct nvme_dev *dev, void *ctx,
 371                                                 struct nvme_completion *cqe)
 372 {
 373         struct nvme_iod *iod = ctx;
 374         struct bio *bio = iod->private;
 375         u16 status = le16_to_cpup(&cqe->status) >> 1;
 376
 377         dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
 378                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 379         nvme_free_iod(dev, iod);
 380         if (status) {
 381                 bio_endio(bio, -EIO);
 382         } else if (bio->bi_vcnt > bio->bi_idx) {
 383                 requeue_bio(dev, bio);
 384         } else {
 385                 bio_endio(bio, 0);
 386         }
 387 }
 388
 389 /* length is in bytes.  gfp flags indicates whether we may sleep. */
 390 static int nvme_setup_prps(struct nvme_dev *dev,
 391                         struct nvme_common_command *cmd, struct nvme_iod *iod,
 392                         int total_len, gfp_t gfp)
 393 {
 394         struct dma_pool *pool;
 395         int length = total_len;
 396         struct scatterlist *sg = iod->sg;
 397         int dma_len = sg_dma_len(sg);
 398         u64 dma_addr = sg_dma_address(sg);
 399         int offset = offset_in_page(dma_addr);
 400         __le64 *prp_list;
 401         __le64 **list = iod_list(iod);
 402         dma_addr_t prp_dma;
 403         int nprps, i;
 404
 405         cmd->prp1 = cpu_to_le64(dma_addr);
 406         length -= (PAGE_SIZE - offset);
 407         if (length <= 0)
 408                 return total_len;
 409
 410         dma_len -= (PAGE_SIZE - offset);
 411         if (dma_len) {
 412                 dma_addr += (PAGE_SIZE - offset);
 413         } else {
 414                 sg = sg_next(sg);
 415                 dma_addr = sg_dma_address(sg);
 416                 dma_len = sg_dma_len(sg);
 417         }
 418
 419         if (length <= PAGE_SIZE) {
 420                 cmd->prp2 = cpu_to_le64(dma_addr);
 421                 return total_len;
 422         }
 423
 424         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 425         if (nprps <= (256 / 8)) {
 426                 pool = dev->prp_small_pool;
 427                 iod->npages = 0;
 428         } else {
 429                 pool = dev->prp_page_pool;
 430                 iod->npages = 1;
 431         }
 432
 433         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 434         if (!prp_list) {
 435                 cmd->prp2 = cpu_to_le64(dma_addr);
 436                 iod->npages = -1;
 437                 return (total_len - length) + PAGE_SIZE;
 438         }
 439         list[0] = prp_list;
 440         iod->first_dma = prp_dma;
 441         cmd->prp2 = cpu_to_le64(prp_dma);
 442         i = 0;
 443         for (;;) {
 444                 if (i == PAGE_SIZE / 8) {
 445                         __le64 *old_prp_list = prp_list;
 446                         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 447                         if (!prp_list)
 448                                 return total_len - length;
 449                         list[iod->npages++] = prp_list;
 450                         prp_list[0] = old_prp_list[i - 1];
 451                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 452                         i = 1;
 453                 }
 454                 prp_list[i++] = cpu_to_le64(dma_addr);
 455                 dma_len -= PAGE_SIZE;
 456                 dma_addr += PAGE_SIZE;
 457                 length -= PAGE_SIZE;
 458                 if (length <= 0)
 459                         break;
 460                 if (dma_len > 0)
 461                         continue;
 462                 BUG_ON(dma_len < 0);
 463                 sg = sg_next(sg);
 464                 dma_addr = sg_dma_address(sg);
 465                 dma_len = sg_dma_len(sg);
 466         }
 467
 468         return total_len;
 469 }
 470
 471 /* NVMe scatterlists require no holes in the virtual address */
 472 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
 473                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
 474
 475 static int nvme_map_bio(struct device *dev, struct nvme_iod *iod,
 476                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 477 {
 478         struct bio_vec *bvec, *bvprv = NULL;
 479         struct scatterlist *sg = NULL;
 480         int i, old_idx, length = 0, nsegs = 0;
 481
 482         sg_init_table(iod->sg, psegs);
 483         old_idx = bio->bi_idx;
 484         bio_for_each_segment(bvec, bio, i) {
 485                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 486                         sg->length += bvec->bv_len;
 487                 } else {
 488                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
 489                                 break;
 490                         sg = sg ? sg + 1 : iod->sg;
 491                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 492                                                         bvec->bv_offset);
 493                         nsegs++;
 494                 }
 495                 length += bvec->bv_len;
 496                 bvprv = bvec;
 497         }
 498         bio->bi_idx = i;
 499         iod->nents = nsegs;
 500         sg_mark_end(sg);
 501         if (dma_map_sg(dev, iod->sg, iod->nents, dma_dir) == 0) {
 502                 bio->bi_idx = old_idx;
 503                 return -ENOMEM;
 504         }
 505         return length;
 506 }
 507
 508 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 509                                                                 int cmdid)
 510 {
 511         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 512
 513         memset(cmnd, 0, sizeof(*cmnd));
 514         cmnd->common.opcode = nvme_cmd_flush;
 515         cmnd->common.command_id = cmdid;
 516         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 517
 518         if (++nvmeq->sq_tail == nvmeq->q_depth)
 519                 nvmeq->sq_tail = 0;
 520         writel(nvmeq->sq_tail, nvmeq->q_db);
 521
 522         return 0;
 523 }
 524
 525 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
 526 {
 527         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
 528                                         special_completion, NVME_IO_TIMEOUT);
 529         if (unlikely(cmdid < 0))
 530                 return cmdid;
 531
 532         return nvme_submit_flush(nvmeq, ns, cmdid);
 533 }
 534
 535 /*
 536  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 537  */
 538 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 539                                                                 struct bio *bio)
 540 {
 541         struct nvme_command *cmnd;
 542         struct nvme_iod *iod;
 543         enum dma_data_direction dma_dir;
 544         int cmdid, length, result = -ENOMEM;
 545         u16 control;
 546         u32 dsmgmt;
 547         int psegs = bio_phys_segments(ns->queue, bio);
 548
 549         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
 550                 result = nvme_submit_flush_data(nvmeq, ns);
 551                 if (result)
 552                         return result;
 553         }
 554
 555         iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
 556         if (!iod)
 557                 goto nomem;
 558         iod->private = bio;
 559
 560         result = -EBUSY;
 561         cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
 562         if (unlikely(cmdid < 0))
 563                 goto free_iod;
 564
 565         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
 566                 return nvme_submit_flush(nvmeq, ns, cmdid);
 567
 568         control = 0;
 569         if (bio->bi_rw & REQ_FUA)
 570                 control |= NVME_RW_FUA;
 571         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 572                 control |= NVME_RW_LR;
 573
 574         dsmgmt = 0;
 575         if (bio->bi_rw & REQ_RAHEAD)
 576                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 577
 578         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 579
 580         memset(cmnd, 0, sizeof(*cmnd));
 581         if (bio_data_dir(bio)) {
 582                 cmnd->rw.opcode = nvme_cmd_write;
 583                 dma_dir = DMA_TO_DEVICE;
 584         } else {
 585                 cmnd->rw.opcode = nvme_cmd_read;
 586                 dma_dir = DMA_FROM_DEVICE;
 587         }
 588
 589         result = nvme_map_bio(nvmeq->q_dmadev, iod, bio, dma_dir, psegs);
 590         if (result < 0)
 591                 goto free_iod;
 592         length = result;
 593
 594         cmnd->rw.command_id = cmdid;
 595         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 596         length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
 597                                                                 GFP_ATOMIC);
 598         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 599         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
 600         cmnd->rw.control = cpu_to_le16(control);
 601         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 602
 603         bio->bi_sector += length >> 9;
 604
 605         if (++nvmeq->sq_tail == nvmeq->q_depth)
 606                 nvmeq->sq_tail = 0;
 607         writel(nvmeq->sq_tail, nvmeq->q_db);
 608
 609         return 0;
 610
 611  free_iod:
 612         nvme_free_iod(nvmeq->dev, iod);
 613  nomem:
 614         return result;
 615 }
 616
 617 /*
 618  * NB: return value of non-zero would mean that we were a stacking driver.
 619  * make_request must always succeed.
 620  */
 621 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 622 {
 623         struct nvme_ns *ns = q->queuedata;
 624         struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
 625         int result = -EBUSY;
 626
 627         spin_lock_irq(&nvmeq->q_lock);
 628         if (bio_list_empty(&nvmeq->sq_cong))
 629                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 630         if (unlikely(result)) {
 631                 if (bio_list_empty(&nvmeq->sq_cong))
 632                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 633                 bio_list_add(&nvmeq->sq_cong, bio);
 634         }
 635
 636         spin_unlock_irq(&nvmeq->q_lock);
 637         put_nvmeq(nvmeq);
 638
 639         return 0;
 640 }
 641
 642 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 643 {
 644         u16 head, phase;
 645
 646         head = nvmeq->cq_head;
 647         phase = nvmeq->cq_phase;
 648
 649         for (;;) {
 650                 void *ctx;
 651                 nvme_completion_fn fn;
 652                 struct nvme_completion cqe = nvmeq->cqes[head];
 653                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 654                         break;
 655                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 656                 if (++head == nvmeq->q_depth) {
 657                         head = 0;
 658                         phase = !phase;
 659                 }
 660
 661                 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
 662                 fn(nvmeq->dev, ctx, &cqe);
 663         }
 664
 665         /* If the controller ignores the cq head doorbell and continuously
 666          * writes to the queue, it is theoretically possible to wrap around
 667          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 668          * requires that 0.1% of your interrupts are handled, so this isn't
 669          * a big problem.
 670          */
 671         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 672                 return IRQ_NONE;
 673
 674         writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
 675         nvmeq->cq_head = head;
 676         nvmeq->cq_phase = phase;
 677
 678         return IRQ_HANDLED;
 679 }
 680
 681 static irqreturn_t nvme_irq(int irq, void *data)
 682 {
 683         irqreturn_t result;
 684         struct nvme_queue *nvmeq = data;
 685         spin_lock(&nvmeq->q_lock);
 686         result = nvme_process_cq(nvmeq);
 687         spin_unlock(&nvmeq->q_lock);
 688         return result;
 689 }
 690
 691 static irqreturn_t nvme_irq_check(int irq, void *data)
 692 {
 693         struct nvme_queue *nvmeq = data;
 694         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 695         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 696                 return IRQ_NONE;
 697         return IRQ_WAKE_THREAD;
 698 }
 699
 700 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 701 {
 702         spin_lock_irq(&nvmeq->q_lock);
 703         cancel_cmdid(nvmeq, cmdid, NULL);
 704         spin_unlock_irq(&nvmeq->q_lock);
 705 }
 706
 707 struct sync_cmd_info {
 708         struct task_struct *task;
 709         u32 result;
 710         int status;
 711 };
 712
 713 static void sync_completion(struct nvme_dev *dev, void *ctx,
 714                                                 struct nvme_completion *cqe)
 715 {
 716         struct sync_cmd_info *cmdinfo = ctx;
 717         cmdinfo->result = le32_to_cpup(&cqe->result);
 718         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 719         wake_up_process(cmdinfo->task);
 720 }
 721
 722 /*
 723  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 724  * if the result is positive, it's an NVM Express status code
 725  */
 726 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 727                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 728 {
 729         int cmdid;
 730         struct sync_cmd_info cmdinfo;
 731
 732         cmdinfo.task = current;
 733         cmdinfo.status = -EINTR;
 734
 735         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
 736                                                                 timeout);
 737         if (cmdid < 0)
 738                 return cmdid;
 739         cmd->common.command_id = cmdid;
 740
 741         set_current_state(TASK_KILLABLE);
 742         nvme_submit_cmd(nvmeq, cmd);
 743         schedule();
 744
 745         if (cmdinfo.status == -EINTR) {
 746                 nvme_abort_command(nvmeq, cmdid);
 747                 return -EINTR;
 748         }
 749
 750         if (result)
 751                 *result = cmdinfo.result;
 752
 753         return cmdinfo.status;
 754 }
 755
 756 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 757                                                                 u32 *result)
 758 {
 759         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 760 }
 761
 762 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 763 {
 764         int status;
 765         struct nvme_command c;
 766
 767         memset(&c, 0, sizeof(c));
 768         c.delete_queue.opcode = opcode;
 769         c.delete_queue.qid = cpu_to_le16(id);
 770
 771         status = nvme_submit_admin_cmd(dev, &c, NULL);
 772         if (status)
 773                 return -EIO;
 774         return 0;
 775 }
 776
 777 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 778                                                 struct nvme_queue *nvmeq)
 779 {
 780         int status;
 781         struct nvme_command c;
 782         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 783
 784         memset(&c, 0, sizeof(c));
 785         c.create_cq.opcode = nvme_admin_create_cq;
 786         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 787         c.create_cq.cqid = cpu_to_le16(qid);
 788         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 789         c.create_cq.cq_flags = cpu_to_le16(flags);
 790         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 791
 792         status = nvme_submit_admin_cmd(dev, &c, NULL);
 793         if (status)
 794                 return -EIO;
 795         return 0;
 796 }
 797
 798 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 799                                                 struct nvme_queue *nvmeq)
 800 {
 801         int status;
 802         struct nvme_command c;
 803         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 804
 805         memset(&c, 0, sizeof(c));
 806         c.create_sq.opcode = nvme_admin_create_sq;
 807         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 808         c.create_sq.sqid = cpu_to_le16(qid);
 809         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 810         c.create_sq.sq_flags = cpu_to_le16(flags);
 811         c.create_sq.cqid = cpu_to_le16(qid);
 812
 813         status = nvme_submit_admin_cmd(dev, &c, NULL);
 814         if (status)
 815                 return -EIO;
 816         return 0;
 817 }
 818
 819 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 820 {
 821         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 822 }
 823
 824 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 825 {
 826         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 827 }
 828
 829 static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
 830                                                         dma_addr_t dma_addr)
 831 {
 832         struct nvme_command c;
 833
 834         memset(&c, 0, sizeof(c));
 835         c.identify.opcode = nvme_admin_identify;
 836         c.identify.nsid = cpu_to_le32(nsid);
 837         c.identify.prp1 = cpu_to_le64(dma_addr);
 838         c.identify.cns = cpu_to_le32(cns);
 839
 840         return nvme_submit_admin_cmd(dev, &c, NULL);
 841 }
 842
 843 static int nvme_get_features(struct nvme_dev *dev, unsigned fid,
 844                                 unsigned nsid, dma_addr_t dma_addr)
 845 {
 846         struct nvme_command c;
 847
 848         memset(&c, 0, sizeof(c));
 849         c.features.opcode = nvme_admin_get_features;
 850         c.features.nsid = cpu_to_le32(nsid);
 851         c.features.prp1 = cpu_to_le64(dma_addr);
 852         c.features.fid = cpu_to_le32(fid);
 853
 854         return nvme_submit_admin_cmd(dev, &c, NULL);
 855 }
 856
 857 static int nvme_set_features(struct nvme_dev *dev, unsigned fid,
 858                         unsigned dword11, dma_addr_t dma_addr, u32 *result)
 859 {
 860         struct nvme_command c;
 861
 862         memset(&c, 0, sizeof(c));
 863         c.features.opcode = nvme_admin_set_features;
 864         c.features.prp1 = cpu_to_le64(dma_addr);
 865         c.features.fid = cpu_to_le32(fid);
 866         c.features.dword11 = cpu_to_le32(dword11);
 867
 868         return nvme_submit_admin_cmd(dev, &c, result);
 869 }
 870
 871 static void nvme_free_queue_mem(struct nvme_queue *nvmeq)
 872 {
 873         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 874                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 875         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 876                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 877         kfree(nvmeq);
 878 }
 879
 880 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 881 {
 882         struct nvme_queue *nvmeq = dev->queues[qid];
 883         int vector = dev->entry[nvmeq->cq_vector].vector;
 884
 885         irq_set_affinity_hint(vector, NULL);
 886         free_irq(vector, nvmeq);
 887
 888         /* Don't tell the adapter to delete the admin queue */
 889         if (qid) {
 890                 adapter_delete_sq(dev, qid);
 891                 adapter_delete_cq(dev, qid);
 892         }
 893
 894         nvme_free_queue_mem(nvmeq);
 895 }
 896
 897 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 898                                                         int depth, int vector)
 899 {
 900         struct device *dmadev = &dev->pci_dev->dev;
 901         unsigned extra = DIV_ROUND_UP(depth, 8) + (depth *
 902                                                 sizeof(struct nvme_cmd_info));
 903         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 904         if (!nvmeq)
 905                 return NULL;
 906
 907         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 908                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 909         if (!nvmeq->cqes)
 910                 goto free_nvmeq;
 911         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 912
 913         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 914                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 915         if (!nvmeq->sq_cmds)
 916                 goto free_cqdma;
 917
 918         nvmeq->q_dmadev = dmadev;
 919         nvmeq->dev = dev;
 920         spin_lock_init(&nvmeq->q_lock);
 921         nvmeq->cq_head = 0;
 922         nvmeq->cq_phase = 1;
 923         init_waitqueue_head(&nvmeq->sq_full);
 924         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
 925         bio_list_init(&nvmeq->sq_cong);
 926         nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
 927         nvmeq->q_depth = depth;
 928         nvmeq->cq_vector = vector;
 929
 930         return nvmeq;
 931
 932  free_cqdma:
 933         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 934                                                         nvmeq->cq_dma_addr);
 935  free_nvmeq:
 936         kfree(nvmeq);
 937         return NULL;
 938 }
 939
 940 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 941                                                         const char *name)
 942 {
 943         if (use_threaded_interrupts)
 944                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 945                                         nvme_irq_check, nvme_irq,
 946                                         IRQF_DISABLED | IRQF_SHARED,
 947                                         name, nvmeq);
 948         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 949                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 950 }
 951
 952 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 953                                         int qid, int cq_size, int vector)
 954 {
 955         int result;
 956         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 957
 958         if (!nvmeq)
 959                 return ERR_PTR(-ENOMEM);
 960
 961         result = adapter_alloc_cq(dev, qid, nvmeq);
 962         if (result < 0)
 963                 goto free_nvmeq;
 964
 965         result = adapter_alloc_sq(dev, qid, nvmeq);
 966         if (result < 0)
 967                 goto release_cq;
 968
 969         result = queue_request_irq(dev, nvmeq, "nvme");
 970         if (result < 0)
 971                 goto release_sq;
 972
 973         return nvmeq;
 974
 975  release_sq:
 976         adapter_delete_sq(dev, qid);
 977  release_cq:
 978         adapter_delete_cq(dev, qid);
 979  free_nvmeq:
 980         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 981                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 982         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 983                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 984         kfree(nvmeq);
 985         return ERR_PTR(result);
 986 }
 987
 988 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 989 {
 990         int result = 0;
 991         u32 aqa;
 992         u64 cap;
 993         unsigned long timeout;
 994         struct nvme_queue *nvmeq;
 995
 996         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 997
 998         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 999         if (!nvmeq)
1000                 return -ENOMEM;
1001
1002         aqa = nvmeq->q_depth - 1;
1003         aqa |= aqa << 16;
1004
1005         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1006         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1007         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1008         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1009
1010         writel(0, &dev->bar->cc);
1011         writel(aqa, &dev->bar->aqa);
1012         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1013         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1014         writel(dev->ctrl_config, &dev->bar->cc);
1015
1016         cap = readq(&dev->bar->cap);
1017         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1018         dev->db_stride = NVME_CAP_STRIDE(cap);
1019
1020         while (!result && !(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
1021                 msleep(100);
1022                 if (fatal_signal_pending(current))
1023                         result = -EINTR;
1024                 if (time_after(jiffies, timeout)) {
1025                         dev_err(&dev->pci_dev->dev,
1026                                 "Device not ready; aborting initialisation\n");
1027                         result = -ENODEV;
1028                 }
1029         }
1030
1031         if (result) {
1032                 nvme_free_queue_mem(nvmeq);
1033                 return result;
1034         }
1035
1036         result = queue_request_irq(dev, nvmeq, "nvme admin");
1037         dev->queues[0] = nvmeq;
1038         return result;
1039 }
1040
1041 static struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1042                                 unsigned long addr, unsigned length)
1043 {
1044         int i, err, count, nents, offset;
1045         struct scatterlist *sg;
1046         struct page **pages;
1047         struct nvme_iod *iod;
1048
1049         if (addr & 3)
1050                 return ERR_PTR(-EINVAL);
1051         if (!length)
1052                 return ERR_PTR(-EINVAL);
1053
1054         offset = offset_in_page(addr);
1055         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1056         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1057         if (!pages)
1058                 return ERR_PTR(-ENOMEM);
1059
1060         err = get_user_pages_fast(addr, count, 1, pages);
1061         if (err < count) {
1062                 count = err;
1063                 err = -EFAULT;
1064                 goto put_pages;
1065         }
1066
1067         iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1068         sg = iod->sg;
1069         sg_init_table(sg, count);
1070         for (i = 0; i < count; i++) {
1071                 sg_set_page(&sg[i], pages[i],
1072                                 min_t(int, length, PAGE_SIZE - offset), offset);
1073                 length -= (PAGE_SIZE - offset);
1074                 offset = 0;
1075         }
1076         sg_mark_end(&sg[i - 1]);
1077         iod->nents = count;
1078
1079         err = -ENOMEM;
1080         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1081                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1082         if (!nents)
1083                 goto free_iod;
1084
1085         kfree(pages);
1086         return iod;
1087
1088  free_iod:
1089         kfree(iod);
1090  put_pages:
1091         for (i = 0; i < count; i++)
1092                 put_page(pages[i]);
1093         kfree(pages);
1094         return ERR_PTR(err);
1095 }
1096
1097 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1098                         struct nvme_iod *iod)
1099 {
1100         int i;
1101
1102         dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1103                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1104
1105         for (i = 0; i < iod->nents; i++)
1106                 put_page(sg_page(&iod->sg[i]));
1107 }
1108
1109 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1110 {
1111         struct nvme_dev *dev = ns->dev;
1112         struct nvme_queue *nvmeq;
1113         struct nvme_user_io io;
1114         struct nvme_command c;
1115         unsigned length;
1116         int status;
1117         struct nvme_iod *iod;
1118
1119         if (copy_from_user(&io, uio, sizeof(io)))
1120                 return -EFAULT;
1121         length = (io.nblocks + 1) << ns->lba_shift;
1122
1123         switch (io.opcode) {
1124         case nvme_cmd_write:
1125         case nvme_cmd_read:
1126         case nvme_cmd_compare:
1127                 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1128                 break;
1129         default:
1130                 return -EINVAL;
1131         }
1132
1133         if (IS_ERR(iod))
1134                 return PTR_ERR(iod);
1135
1136         memset(&c, 0, sizeof(c));
1137         c.rw.opcode = io.opcode;
1138         c.rw.flags = io.flags;
1139         c.rw.nsid = cpu_to_le32(ns->ns_id);
1140         c.rw.slba = cpu_to_le64(io.slba);
1141         c.rw.length = cpu_to_le16(io.nblocks);
1142         c.rw.control = cpu_to_le16(io.control);
1143         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1144         c.rw.reftag = io.reftag;
1145         c.rw.apptag = io.apptag;
1146         c.rw.appmask = io.appmask;
1147         /* XXX: metadata */
1148         length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
1149
1150         nvmeq = get_nvmeq(dev);
1151         /*
1152          * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1153          * disabled.  We may be preempted at any point, and be rescheduled
1154          * to a different CPU.  That will cause cacheline bouncing, but no
1155          * additional races since q_lock already protects against other CPUs.
1156          */
1157         put_nvmeq(nvmeq);
1158         if (length != (io.nblocks + 1) << ns->lba_shift)
1159                 status = -ENOMEM;
1160         else
1161                 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
1162
1163         nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1164         nvme_free_iod(dev, iod);
1165         return status;
1166 }
1167
1168 static int nvme_user_admin_cmd(struct nvme_dev *dev,
1169                                         struct nvme_admin_cmd __user *ucmd)
1170 {
1171         struct nvme_admin_cmd cmd;
1172         struct nvme_command c;
1173         int status, length;
1174         struct nvme_iod *uninitialized_var(iod);
1175
1176         if (!capable(CAP_SYS_ADMIN))
1177                 return -EACCES;
1178         if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1179                 return -EFAULT;
1180
1181         memset(&c, 0, sizeof(c));
1182         c.common.opcode = cmd.opcode;
1183         c.common.flags = cmd.flags;
1184         c.common.nsid = cpu_to_le32(cmd.nsid);
1185         c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1186         c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1187         c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1188         c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1189         c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1190         c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1191         c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1192         c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1193
1194         length = cmd.data_len;
1195         if (cmd.data_len) {
1196                 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1197                                                                 length);
1198                 if (IS_ERR(iod))
1199                         return PTR_ERR(iod);
1200                 length = nvme_setup_prps(dev, &c.common, iod, length,
1201                                                                 GFP_KERNEL);
1202         }
1203
1204         if (length != cmd.data_len)
1205                 status = -ENOMEM;
1206         else
1207                 status = nvme_submit_admin_cmd(dev, &c, NULL);
1208
1209         if (cmd.data_len) {
1210                 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1211                 nvme_free_iod(dev, iod);
1212         }
1213         return status;
1214 }
1215
1216 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1217                                                         unsigned long arg)
1218 {
1219         struct nvme_ns *ns = bdev->bd_disk->private_data;
1220
1221         switch (cmd) {
1222         case NVME_IOCTL_ID:
1223                 return ns->ns_id;
1224         case NVME_IOCTL_ADMIN_CMD:
1225                 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
1226         case NVME_IOCTL_SUBMIT_IO:
1227                 return nvme_submit_io(ns, (void __user *)arg);
1228         default:
1229                 return -ENOTTY;
1230         }
1231 }
1232
1233 static const struct block_device_operations nvme_fops = {
1234         .owner          = THIS_MODULE,
1235         .ioctl          = nvme_ioctl,
1236         .compat_ioctl   = nvme_ioctl,
1237 };
1238
1239 static void nvme_timeout_ios(struct nvme_queue *nvmeq)
1240 {
1241         int depth = nvmeq->q_depth - 1;
1242         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1243         unsigned long now = jiffies;
1244         int cmdid;
1245
1246         for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1247                 void *ctx;
1248                 nvme_completion_fn fn;
1249                 static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, };
1250
1251                 if (!time_after(now, info[cmdid].timeout))
1252                         continue;
1253                 dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid);
1254                 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
1255                 fn(nvmeq->dev, ctx, &cqe);
1256         }
1257 }
1258
1259 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1260 {
1261         while (bio_list_peek(&nvmeq->sq_cong)) {
1262                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1263                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1264                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1265                         bio_list_add_head(&nvmeq->sq_cong, bio);
1266                         break;
1267                 }
1268                 if (bio_list_empty(&nvmeq->sq_cong))
1269                         remove_wait_queue(&nvmeq->sq_full,
1270                                                         &nvmeq->sq_cong_wait);
1271         }
1272 }
1273
1274 static int nvme_kthread(void *data)
1275 {
1276         struct nvme_dev *dev;
1277
1278         while (!kthread_should_stop()) {
1279                 __set_current_state(TASK_RUNNING);
1280                 spin_lock(&dev_list_lock);
1281                 list_for_each_entry(dev, &dev_list, node) {
1282                         int i;
1283                         for (i = 0; i < dev->queue_count; i++) {
1284                                 struct nvme_queue *nvmeq = dev->queues[i];
1285                                 if (!nvmeq)
1286                                         continue;
1287                                 spin_lock_irq(&nvmeq->q_lock);
1288                                 if (nvme_process_cq(nvmeq))
1289                                         printk("process_cq did something\n");
1290                                 nvme_timeout_ios(nvmeq);
1291                                 nvme_resubmit_bios(nvmeq);
1292                                 spin_unlock_irq(&nvmeq->q_lock);
1293                         }
1294                 }
1295                 spin_unlock(&dev_list_lock);
1296                 set_current_state(TASK_INTERRUPTIBLE);
1297                 schedule_timeout(HZ);
1298         }
1299         return 0;
1300 }
1301
1302 static DEFINE_IDA(nvme_index_ida);
1303
1304 static int nvme_get_ns_idx(void)
1305 {
1306         int index, error;
1307
1308         do {
1309                 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1310                         return -1;
1311
1312                 spin_lock(&dev_list_lock);
1313                 error = ida_get_new(&nvme_index_ida, &index);
1314                 spin_unlock(&dev_list_lock);
1315         } while (error == -EAGAIN);
1316
1317         if (error)
1318                 index = -1;
1319         return index;
1320 }
1321
1322 static void nvme_put_ns_idx(int index)
1323 {
1324         spin_lock(&dev_list_lock);
1325         ida_remove(&nvme_index_ida, index);
1326         spin_unlock(&dev_list_lock);
1327 }
1328
1329 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
1330                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1331 {
1332         struct nvme_ns *ns;
1333         struct gendisk *disk;
1334         int lbaf;
1335
1336         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1337                 return NULL;
1338
1339         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1340         if (!ns)
1341                 return NULL;
1342         ns->queue = blk_alloc_queue(GFP_KERNEL);
1343         if (!ns->queue)
1344                 goto out_free_ns;
1345         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1346         queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1347         queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1348 /*      queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); */
1349         blk_queue_make_request(ns->queue, nvme_make_request);
1350         ns->dev = dev;
1351         ns->queue->queuedata = ns;
1352
1353         disk = alloc_disk(NVME_MINORS);
1354         if (!disk)
1355                 goto out_free_queue;
1356         ns->ns_id = nsid;
1357         ns->disk = disk;
1358         lbaf = id->flbas & 0xf;
1359         ns->lba_shift = id->lbaf[lbaf].ds;
1360         blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1361         if (dev->max_hw_sectors)
1362                 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
1363
1364         disk->major = nvme_major;
1365         disk->minors = NVME_MINORS;
1366         disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1367         disk->fops = &nvme_fops;
1368         disk->private_data = ns;
1369         disk->queue = ns->queue;
1370         disk->driverfs_dev = &dev->pci_dev->dev;
1371         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1372         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1373
1374         return ns;
1375
1376  out_free_queue:
1377         blk_cleanup_queue(ns->queue);
1378  out_free_ns:
1379         kfree(ns);
1380         return NULL;
1381 }
1382
1383 static void nvme_ns_free(struct nvme_ns *ns)
1384 {
1385         int index = ns->disk->first_minor / NVME_MINORS;
1386         put_disk(ns->disk);
1387         nvme_put_ns_idx(index);
1388         blk_cleanup_queue(ns->queue);
1389         kfree(ns);
1390 }
1391
1392 static int set_queue_count(struct nvme_dev *dev, int count)
1393 {
1394         int status;
1395         u32 result;
1396         u32 q_count = (count - 1) | ((count - 1) << 16);
1397
1398         status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1399                                                                 &result);
1400         if (status)
1401                 return -EIO;
1402         return min(result & 0xffff, result >> 16) + 1;
1403 }
1404
1405 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1406 {
1407         int result, cpu, i, nr_io_queues, db_bar_size, q_depth;
1408
1409         nr_io_queues = num_online_cpus();
1410         result = set_queue_count(dev, nr_io_queues);
1411         if (result < 0)
1412                 return result;
1413         if (result < nr_io_queues)
1414                 nr_io_queues = result;
1415
1416         /* Deregister the admin queue's interrupt */
1417         free_irq(dev->entry[0].vector, dev->queues[0]);
1418
1419         db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1420         if (db_bar_size > 8192) {
1421                 iounmap(dev->bar);
1422                 dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
1423                                                                 db_bar_size);
1424                 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1425                 dev->queues[0]->q_db = dev->dbs;
1426         }
1427
1428         for (i = 0; i < nr_io_queues; i++)
1429                 dev->entry[i].entry = i;
1430         for (;;) {
1431                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1432                                                                 nr_io_queues);
1433                 if (result == 0) {
1434                         break;
1435                 } else if (result > 0) {
1436                         nr_io_queues = result;
1437                         continue;
1438                 } else {
1439                         nr_io_queues = 1;
1440                         break;
1441                 }
1442         }
1443
1444         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1445         /* XXX: handle failure here */
1446
1447         cpu = cpumask_first(cpu_online_mask);
1448         for (i = 0; i < nr_io_queues; i++) {
1449                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1450                 cpu = cpumask_next(cpu, cpu_online_mask);
1451         }
1452
1453         q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1,
1454                                                                 NVME_Q_DEPTH);
1455         for (i = 0; i < nr_io_queues; i++) {
1456                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1, q_depth, i);
1457                 if (IS_ERR(dev->queues[i + 1]))
1458                         return PTR_ERR(dev->queues[i + 1]);
1459                 dev->queue_count++;
1460         }
1461
1462         for (; i < num_possible_cpus(); i++) {
1463                 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1464                 dev->queues[i + 1] = dev->queues[target + 1];
1465         }
1466
1467         return 0;
1468 }
1469
1470 static void nvme_free_queues(struct nvme_dev *dev)
1471 {
1472         int i;
1473
1474         for (i = dev->queue_count - 1; i >= 0; i--)
1475                 nvme_free_queue(dev, i);
1476 }
1477
1478 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1479 {
1480         int res, nn, i;
1481         struct nvme_ns *ns, *next;
1482         struct nvme_id_ctrl *ctrl;
1483         struct nvme_id_ns *id_ns;
1484         void *mem;
1485         dma_addr_t dma_addr;
1486
1487         res = nvme_setup_io_queues(dev);
1488         if (res)
1489                 return res;
1490
1491         mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1492                                                                 GFP_KERNEL);
1493
1494         res = nvme_identify(dev, 0, 1, dma_addr);
1495         if (res) {
1496                 res = -EIO;
1497                 goto out_free;
1498         }
1499
1500         ctrl = mem;
1501         nn = le32_to_cpup(&ctrl->nn);
1502         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1503         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1504         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1505         if (ctrl->mdts) {
1506                 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
1507                 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
1508         }
1509
1510         id_ns = mem;
1511         for (i = 1; i <= nn; i++) {
1512                 res = nvme_identify(dev, i, 0, dma_addr);
1513                 if (res)
1514                         continue;
1515
1516                 if (id_ns->ncap == 0)
1517                         continue;
1518
1519                 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
1520                                                         dma_addr + 4096);
1521                 if (res)
1522                         continue;
1523
1524                 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
1525                 if (ns)
1526                         list_add_tail(&ns->list, &dev->namespaces);
1527         }
1528         list_for_each_entry(ns, &dev->namespaces, list)
1529                 add_disk(ns->disk);
1530
1531         goto out;
1532
1533  out_free:
1534         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1535                 list_del(&ns->list);
1536                 nvme_ns_free(ns);
1537         }
1538
1539  out:
1540         dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1541         return res;
1542 }
1543
1544 static int nvme_dev_remove(struct nvme_dev *dev)
1545 {
1546         struct nvme_ns *ns, *next;
1547
1548         spin_lock(&dev_list_lock);
1549         list_del(&dev->node);
1550         spin_unlock(&dev_list_lock);
1551
1552         /* TODO: wait all I/O finished or cancel them */
1553
1554         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1555                 list_del(&ns->list);
1556                 del_gendisk(ns->disk);
1557                 nvme_ns_free(ns);
1558         }
1559
1560         nvme_free_queues(dev);
1561
1562         return 0;
1563 }
1564
1565 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1566 {
1567         struct device *dmadev = &dev->pci_dev->dev;
1568         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1569                                                 PAGE_SIZE, PAGE_SIZE, 0);
1570         if (!dev->prp_page_pool)
1571                 return -ENOMEM;
1572
1573         /* Optimisation for I/Os between 4k and 128k */
1574         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1575                                                 256, 256, 0);
1576         if (!dev->prp_small_pool) {
1577                 dma_pool_destroy(dev->prp_page_pool);
1578                 return -ENOMEM;
1579         }
1580         return 0;
1581 }
1582
1583 static void nvme_release_prp_pools(struct nvme_dev *dev)
1584 {
1585         dma_pool_destroy(dev->prp_page_pool);
1586         dma_pool_destroy(dev->prp_small_pool);
1587 }
1588
1589 static DEFINE_IDA(nvme_instance_ida);
1590
1591 static int nvme_set_instance(struct nvme_dev *dev)
1592 {
1593         int instance, error;
1594
1595         do {
1596                 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
1597                         return -ENODEV;
1598
1599                 spin_lock(&dev_list_lock);
1600                 error = ida_get_new(&nvme_instance_ida, &instance);
1601                 spin_unlock(&dev_list_lock);
1602         } while (error == -EAGAIN);
1603
1604         if (error)
1605                 return -ENODEV;
1606
1607         dev->instance = instance;
1608         return 0;
1609 }
1610
1611 static void nvme_release_instance(struct nvme_dev *dev)
1612 {
1613         spin_lock(&dev_list_lock);
1614         ida_remove(&nvme_instance_ida, dev->instance);
1615         spin_unlock(&dev_list_lock);
1616 }
1617
1618 static int __devinit nvme_probe(struct pci_dev *pdev,
1619                                                 const struct pci_device_id *id)
1620 {
1621         int bars, result = -ENOMEM;
1622         struct nvme_dev *dev;
1623
1624         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1625         if (!dev)
1626                 return -ENOMEM;
1627         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1628                                                                 GFP_KERNEL);
1629         if (!dev->entry)
1630                 goto free;
1631         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1632                                                                 GFP_KERNEL);
1633         if (!dev->queues)
1634                 goto free;
1635
1636         if (pci_enable_device_mem(pdev))
1637                 goto free;
1638         pci_set_master(pdev);
1639         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1640         if (pci_request_selected_regions(pdev, bars, "nvme"))
1641                 goto disable;
1642
1643         INIT_LIST_HEAD(&dev->namespaces);
1644         dev->pci_dev = pdev;
1645         pci_set_drvdata(pdev, dev);
1646         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1647         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1648         result = nvme_set_instance(dev);
1649         if (result)
1650                 goto disable;
1651
1652         dev->entry[0].vector = pdev->irq;
1653
1654         result = nvme_setup_prp_pools(dev);
1655         if (result)
1656                 goto disable_msix;
1657
1658         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1659         if (!dev->bar) {
1660                 result = -ENOMEM;
1661                 goto disable_msix;
1662         }
1663
1664         result = nvme_configure_admin_queue(dev);
1665         if (result)
1666                 goto unmap;
1667         dev->queue_count++;
1668
1669         spin_lock(&dev_list_lock);
1670         list_add(&dev->node, &dev_list);
1671         spin_unlock(&dev_list_lock);
1672
1673         result = nvme_dev_add(dev);
1674         if (result)
1675                 goto delete;
1676
1677         return 0;
1678
1679  delete:
1680         spin_lock(&dev_list_lock);
1681         list_del(&dev->node);
1682         spin_unlock(&dev_list_lock);
1683
1684         nvme_free_queues(dev);
1685  unmap:
1686         iounmap(dev->bar);
1687  disable_msix:
1688         pci_disable_msix(pdev);
1689         nvme_release_instance(dev);
1690         nvme_release_prp_pools(dev);
1691  disable:
1692         pci_disable_device(pdev);
1693         pci_release_regions(pdev);
1694  free:
1695         kfree(dev->queues);
1696         kfree(dev->entry);
1697         kfree(dev);
1698         return result;
1699 }
1700
1701 static void __devexit nvme_remove(struct pci_dev *pdev)
1702 {
1703         struct nvme_dev *dev = pci_get_drvdata(pdev);
1704         nvme_dev_remove(dev);
1705         pci_disable_msix(pdev);
1706         iounmap(dev->bar);
1707         nvme_release_instance(dev);
1708         nvme_release_prp_pools(dev);
1709         pci_disable_device(pdev);
1710         pci_release_regions(pdev);
1711         kfree(dev->queues);
1712         kfree(dev->entry);
1713         kfree(dev);
1714 }
1715
1716 /* These functions are yet to be implemented */
1717 #define nvme_error_detected NULL
1718 #define nvme_dump_registers NULL
1719 #define nvme_link_reset NULL
1720 #define nvme_slot_reset NULL
1721 #define nvme_error_resume NULL
1722 #define nvme_suspend NULL
1723 #define nvme_resume NULL
1724
1725 static struct pci_error_handlers nvme_err_handler = {
1726         .error_detected = nvme_error_detected,
1727         .mmio_enabled   = nvme_dump_registers,
1728         .link_reset     = nvme_link_reset,
1729         .slot_reset     = nvme_slot_reset,
1730         .resume         = nvme_error_resume,
1731 };
1732
1733 /* Move to pci_ids.h later */
1734 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1735
1736 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1737         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1738         { 0, }
1739 };
1740 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1741
1742 static struct pci_driver nvme_driver = {
1743         .name           = "nvme",
1744         .id_table       = nvme_id_table,
1745         .probe          = nvme_probe,
1746         .remove         = __devexit_p(nvme_remove),
1747         .suspend        = nvme_suspend,
1748         .resume         = nvme_resume,
1749         .err_handler    = &nvme_err_handler,
1750 };
1751
1752 static int __init nvme_init(void)
1753 {
1754         int result;
1755
1756         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1757         if (IS_ERR(nvme_thread))
1758                 return PTR_ERR(nvme_thread);
1759
1760         result = register_blkdev(nvme_major, "nvme");
1761         if (result < 0)
1762                 goto kill_kthread;
1763         else if (result > 0)
1764                 nvme_major = result;
1765
1766         result = pci_register_driver(&nvme_driver);
1767         if (result)
1768                 goto unregister_blkdev;
1769         return 0;
1770
1771  unregister_blkdev:
1772         unregister_blkdev(nvme_major, "nvme");
1773  kill_kthread:
1774         kthread_stop(nvme_thread);
1775         return result;
1776 }
1777
1778 static void __exit nvme_exit(void)
1779 {
1780         pci_unregister_driver(&nvme_driver);
1781         unregister_blkdev(nvme_major, "nvme");
1782         kthread_stop(nvme_thread);
1783 }
1784
1785 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1786 MODULE_LICENSE("GPL");
1787 MODULE_VERSION("0.8");
1788 module_init(nvme_init);
1789 module_exit(nvme_exit);