Pileus Git - ~andy/linux/blob - drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kthread.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/pci.h>
  35 #include <linux/poison.h>
  36 #include <linux/sched.h>
  37 #include <linux/slab.h>
  38 #include <linux/types.h>
  39 #include <linux/version.h>
  40
  41 #define NVME_Q_DEPTH 1024
  42 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  43 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  44 #define NVME_MINORS 64
  45 #define IO_TIMEOUT      (5 * HZ)
  46 #define ADMIN_TIMEOUT   (60 * HZ)
  47
  48 static int nvme_major;
  49 module_param(nvme_major, int, 0);
  50
  51 static int use_threaded_interrupts;
  52 module_param(use_threaded_interrupts, int, 0);
  53
  54 static DEFINE_SPINLOCK(dev_list_lock);
  55 static LIST_HEAD(dev_list);
  56 static struct task_struct *nvme_thread;
  57
  58 /*
  59  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  60  */
  61 struct nvme_dev {
  62         struct list_head node;
  63         struct nvme_queue **queues;
  64         u32 __iomem *dbs;
  65         struct pci_dev *pci_dev;
  66         struct dma_pool *prp_page_pool;
  67         struct dma_pool *prp_small_pool;
  68         int instance;
  69         int queue_count;
  70         u32 ctrl_config;
  71         struct msix_entry *entry;
  72         struct nvme_bar __iomem *bar;
  73         struct list_head namespaces;
  74         char serial[20];
  75         char model[40];
  76         char firmware_rev[8];
  77 };
  78
  79 /*
  80  * An NVM Express namespace is equivalent to a SCSI LUN
  81  */
  82 struct nvme_ns {
  83         struct list_head list;
  84
  85         struct nvme_dev *dev;
  86         struct request_queue *queue;
  87         struct gendisk *disk;
  88
  89         int ns_id;
  90         int lba_shift;
  91 };
  92
  93 /*
  94  * An NVM Express queue.  Each device has at least two (one for admin
  95  * commands and one for I/O commands).
  96  */
  97 struct nvme_queue {
  98         struct device *q_dmadev;
  99         struct nvme_dev *dev;
 100         spinlock_t q_lock;
 101         struct nvme_command *sq_cmds;
 102         volatile struct nvme_completion *cqes;
 103         dma_addr_t sq_dma_addr;
 104         dma_addr_t cq_dma_addr;
 105         wait_queue_head_t sq_full;
 106         wait_queue_t sq_cong_wait;
 107         struct bio_list sq_cong;
 108         u32 __iomem *q_db;
 109         u16 q_depth;
 110         u16 cq_vector;
 111         u16 sq_head;
 112         u16 sq_tail;
 113         u16 cq_head;
 114         u16 cq_phase;
 115         unsigned long cmdid_data[];
 116 };
 117
 118 /*
 119  * Check we didin't inadvertently grow the command struct
 120  */
 121 static inline void _nvme_check_size(void)
 122 {
 123         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 124         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 125         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 126         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 127         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 128         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 130         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 131         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 132 }
 133
 134 struct nvme_cmd_info {
 135         unsigned long ctx;
 136         unsigned long timeout;
 137 };
 138
 139 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 140 {
 141         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 142 }
 143
 144 /**
 145  * alloc_cmdid() - Allocate a Command ID
 146  * @nvmeq: The queue that will be used for this command
 147  * @ctx: A pointer that will be passed to the handler
 148  * @handler: The ID of the handler to call
 149  *
 150  * Allocate a Command ID for a queue.  The data passed in will
 151  * be passed to the completion handler.  This is implemented by using
 152  * the bottom two bits of the ctx pointer to store the handler ID.
 153  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 154  * We can change this if it becomes a problem.
 155  */
 156 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 157                                                         unsigned timeout)
 158 {
 159         int depth = nvmeq->q_depth - 1;
 160         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 161         int cmdid;
 162
 163         BUG_ON((unsigned long)ctx & 3);
 164
 165         do {
 166                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 167                 if (cmdid >= depth)
 168                         return -EBUSY;
 169         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 170
 171         info[cmdid].ctx = (unsigned long)ctx | handler;
 172         info[cmdid].timeout = jiffies + timeout;
 173         return cmdid;
 174 }
 175
 176 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 177                                                 int handler, unsigned timeout)
 178 {
 179         int cmdid;
 180         wait_event_killable(nvmeq->sq_full,
 181                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 182         return (cmdid < 0) ? -EINTR : cmdid;
 183 }
 184
 185 /*
 186  * If you need more than four handlers, you'll need to change how
 187  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 188  * CMD_CTX value instead, if that works for your situation.
 189  */
 190 enum {
 191         sync_completion_id = 0,
 192         bio_completion_id,
 193 };
 194
 195 /* Special values must be a multiple of 4, and less than 0x1000 */
 196 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 197 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 198 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 199 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 200 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
 201
 202 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 203 {
 204         unsigned long data;
 205         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 206
 207         if (cmdid >= nvmeq->q_depth)
 208                 return CMD_CTX_INVALID;
 209         data = info[cmdid].ctx;
 210         info[cmdid].ctx = CMD_CTX_COMPLETED;
 211         clear_bit(cmdid, nvmeq->cmdid_data);
 212         wake_up(&nvmeq->sq_full);
 213         return data;
 214 }
 215
 216 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 217 {
 218         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 219         info[cmdid].ctx = CMD_CTX_CANCELLED;
 220 }
 221
 222 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 223 {
 224         return ns->dev->queues[get_cpu() + 1];
 225 }
 226
 227 static void put_nvmeq(struct nvme_queue *nvmeq)
 228 {
 229         put_cpu();
 230 }
 231
 232 /**
 233  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 234  * @nvmeq: The queue to use
 235  * @cmd: The command to send
 236  *
 237  * Safe to use from interrupt context
 238  */
 239 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 240 {
 241         unsigned long flags;
 242         u16 tail;
 243         spin_lock_irqsave(&nvmeq->q_lock, flags);
 244         tail = nvmeq->sq_tail;
 245         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 246         if (++tail == nvmeq->q_depth)
 247                 tail = 0;
 248         writel(tail, nvmeq->q_db);
 249         nvmeq->sq_tail = tail;
 250         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 251
 252         return 0;
 253 }
 254
 255 struct nvme_prps {
 256         int npages;
 257         dma_addr_t first_dma;
 258         __le64 *list[0];
 259 };
 260
 261 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 262 {
 263         const int last_prp = PAGE_SIZE / 8 - 1;
 264         int i;
 265         dma_addr_t prp_dma;
 266
 267         if (!prps)
 268                 return;
 269
 270         prp_dma = prps->first_dma;
 271
 272         if (prps->npages == 0)
 273                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 274         for (i = 0; i < prps->npages; i++) {
 275                 __le64 *prp_list = prps->list[i];
 276                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 277                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 278                 prp_dma = next_prp_dma;
 279         }
 280         kfree(prps);
 281 }
 282
 283 struct nvme_bio {
 284         struct bio *bio;
 285         int nents;
 286         struct nvme_prps *prps;
 287         struct scatterlist sg[0];
 288 };
 289
 290 /* XXX: use a mempool */
 291 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 292 {
 293         return kzalloc(sizeof(struct nvme_bio) +
 294                         sizeof(struct scatterlist) * nseg, gfp);
 295 }
 296
 297 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 298 {
 299         nvme_free_prps(nvmeq->dev, nbio->prps);
 300         kfree(nbio);
 301 }
 302
 303 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 304                                                 struct nvme_completion *cqe)
 305 {
 306         struct nvme_bio *nbio = ctx;
 307         struct bio *bio = nbio->bio;
 308         u16 status = le16_to_cpup(&cqe->status) >> 1;
 309
 310         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 311                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 312         free_nbio(nvmeq, nbio);
 313         if (status)
 314                 bio_endio(bio, -EIO);
 315         if (bio->bi_vcnt > bio->bi_idx) {
 316                 bio_list_add(&nvmeq->sq_cong, bio);
 317                 wake_up_process(nvme_thread);
 318         } else {
 319                 bio_endio(bio, 0);
 320         }
 321 }
 322
 323 /* length is in bytes */
 324 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 325                                         struct nvme_common_command *cmd,
 326                                         struct scatterlist *sg, int length)
 327 {
 328         struct dma_pool *pool;
 329         int dma_len = sg_dma_len(sg);
 330         u64 dma_addr = sg_dma_address(sg);
 331         int offset = offset_in_page(dma_addr);
 332         __le64 *prp_list;
 333         dma_addr_t prp_dma;
 334         int nprps, npages, i, prp_page;
 335         struct nvme_prps *prps = NULL;
 336
 337         cmd->prp1 = cpu_to_le64(dma_addr);
 338         length -= (PAGE_SIZE - offset);
 339         if (length <= 0)
 340                 return prps;
 341
 342         dma_len -= (PAGE_SIZE - offset);
 343         if (dma_len) {
 344                 dma_addr += (PAGE_SIZE - offset);
 345         } else {
 346                 sg = sg_next(sg);
 347                 dma_addr = sg_dma_address(sg);
 348                 dma_len = sg_dma_len(sg);
 349         }
 350
 351         if (length <= PAGE_SIZE) {
 352                 cmd->prp2 = cpu_to_le64(dma_addr);
 353                 return prps;
 354         }
 355
 356         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 357         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 358         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
 359         prp_page = 0;
 360         if (nprps <= (256 / 8)) {
 361                 pool = dev->prp_small_pool;
 362                 prps->npages = 0;
 363         } else {
 364                 pool = dev->prp_page_pool;
 365                 prps->npages = npages;
 366         }
 367
 368         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 369         prps->list[prp_page++] = prp_list;
 370         prps->first_dma = prp_dma;
 371         cmd->prp2 = cpu_to_le64(prp_dma);
 372         i = 0;
 373         for (;;) {
 374                 if (i == PAGE_SIZE / 8) {
 375                         __le64 *old_prp_list = prp_list;
 376                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 377                         prps->list[prp_page++] = prp_list;
 378                         prp_list[0] = old_prp_list[i - 1];
 379                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 380                         i = 1;
 381                 }
 382                 prp_list[i++] = cpu_to_le64(dma_addr);
 383                 dma_len -= PAGE_SIZE;
 384                 dma_addr += PAGE_SIZE;
 385                 length -= PAGE_SIZE;
 386                 if (length <= 0)
 387                         break;
 388                 if (dma_len > 0)
 389                         continue;
 390                 BUG_ON(dma_len < 0);
 391                 sg = sg_next(sg);
 392                 dma_addr = sg_dma_address(sg);
 393                 dma_len = sg_dma_len(sg);
 394         }
 395
 396         return prps;
 397 }
 398
 399 /* NVMe scatterlists require no holes in the virtual address */
 400 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
 401                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
 402
 403 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 404                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 405 {
 406         struct bio_vec *bvec, *bvprv = NULL;
 407         struct scatterlist *sg = NULL;
 408         int i, old_idx, length = 0, nsegs = 0;
 409
 410         sg_init_table(nbio->sg, psegs);
 411         old_idx = bio->bi_idx;
 412         bio_for_each_segment(bvec, bio, i) {
 413                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 414                         sg->length += bvec->bv_len;
 415                 } else {
 416                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
 417                                 break;
 418                         sg = sg ? sg + 1 : nbio->sg;
 419                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 420                                                         bvec->bv_offset);
 421                         nsegs++;
 422                 }
 423                 length += bvec->bv_len;
 424                 bvprv = bvec;
 425         }
 426         bio->bi_idx = i;
 427         nbio->nents = nsegs;
 428         sg_mark_end(sg);
 429         if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
 430                 bio->bi_idx = old_idx;
 431                 return -ENOMEM;
 432         }
 433         return length;
 434 }
 435
 436 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 437                                                                 int cmdid)
 438 {
 439         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 440
 441         memset(cmnd, 0, sizeof(*cmnd));
 442         cmnd->common.opcode = nvme_cmd_flush;
 443         cmnd->common.command_id = cmdid;
 444         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 445
 446         if (++nvmeq->sq_tail == nvmeq->q_depth)
 447                 nvmeq->sq_tail = 0;
 448         writel(nvmeq->sq_tail, nvmeq->q_db);
 449
 450         return 0;
 451 }
 452
 453 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
 454 {
 455         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
 456                                                 sync_completion_id, IO_TIMEOUT);
 457         if (unlikely(cmdid < 0))
 458                 return cmdid;
 459
 460         return nvme_submit_flush(nvmeq, ns, cmdid);
 461 }
 462
 463 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 464                                                                 struct bio *bio)
 465 {
 466         struct nvme_command *cmnd;
 467         struct nvme_bio *nbio;
 468         enum dma_data_direction dma_dir;
 469         int cmdid, length, result = -ENOMEM;
 470         u16 control;
 471         u32 dsmgmt;
 472         int psegs = bio_phys_segments(ns->queue, bio);
 473
 474         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
 475                 result = nvme_submit_flush_data(nvmeq, ns);
 476                 if (result)
 477                         return result;
 478         }
 479
 480         nbio = alloc_nbio(psegs, GFP_ATOMIC);
 481         if (!nbio)
 482                 goto nomem;
 483         nbio->bio = bio;
 484
 485         result = -EBUSY;
 486         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 487         if (unlikely(cmdid < 0))
 488                 goto free_nbio;
 489
 490         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
 491                 return nvme_submit_flush(nvmeq, ns, cmdid);
 492
 493         control = 0;
 494         if (bio->bi_rw & REQ_FUA)
 495                 control |= NVME_RW_FUA;
 496         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 497                 control |= NVME_RW_LR;
 498
 499         dsmgmt = 0;
 500         if (bio->bi_rw & REQ_RAHEAD)
 501                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 502
 503         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 504
 505         memset(cmnd, 0, sizeof(*cmnd));
 506         if (bio_data_dir(bio)) {
 507                 cmnd->rw.opcode = nvme_cmd_write;
 508                 dma_dir = DMA_TO_DEVICE;
 509         } else {
 510                 cmnd->rw.opcode = nvme_cmd_read;
 511                 dma_dir = DMA_FROM_DEVICE;
 512         }
 513
 514         result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
 515         if (result < 0)
 516                 goto free_nbio;
 517         length = result;
 518
 519         cmnd->rw.command_id = cmdid;
 520         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 521         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 522                                                                 length);
 523         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 524         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
 525         cmnd->rw.control = cpu_to_le16(control);
 526         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 527
 528         bio->bi_sector += length >> 9;
 529
 530         if (++nvmeq->sq_tail == nvmeq->q_depth)
 531                 nvmeq->sq_tail = 0;
 532         writel(nvmeq->sq_tail, nvmeq->q_db);
 533
 534         return 0;
 535
 536  free_nbio:
 537         free_nbio(nvmeq, nbio);
 538  nomem:
 539         return result;
 540 }
 541
 542 /*
 543  * NB: return value of non-zero would mean that we were a stacking driver.
 544  * make_request must always succeed.
 545  */
 546 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 547 {
 548         struct nvme_ns *ns = q->queuedata;
 549         struct nvme_queue *nvmeq = get_nvmeq(ns);
 550         int result = -EBUSY;
 551
 552         spin_lock_irq(&nvmeq->q_lock);
 553         if (bio_list_empty(&nvmeq->sq_cong))
 554                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 555         if (unlikely(result)) {
 556                 if (bio_list_empty(&nvmeq->sq_cong))
 557                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 558                 bio_list_add(&nvmeq->sq_cong, bio);
 559         }
 560
 561         spin_unlock_irq(&nvmeq->q_lock);
 562         put_nvmeq(nvmeq);
 563
 564         return 0;
 565 }
 566
 567 struct sync_cmd_info {
 568         struct task_struct *task;
 569         u32 result;
 570         int status;
 571 };
 572
 573 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 574                                                 struct nvme_completion *cqe)
 575 {
 576         struct sync_cmd_info *cmdinfo = ctx;
 577         if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
 578                 return;
 579         if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
 580                 return;
 581         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 582                 dev_warn(nvmeq->q_dmadev,
 583                                 "completed id %d twice on queue %d\n",
 584                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 585                 return;
 586         }
 587         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 588                 dev_warn(nvmeq->q_dmadev,
 589                                 "invalid id %d completed on queue %d\n",
 590                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 591                 return;
 592         }
 593         cmdinfo->result = le32_to_cpup(&cqe->result);
 594         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 595         wake_up_process(cmdinfo->task);
 596 }
 597
 598 typedef void (*completion_fn)(struct nvme_queue *, void *,
 599                                                 struct nvme_completion *);
 600
 601 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 602 {
 603         u16 head, phase;
 604
 605         static const completion_fn completions[4] = {
 606                 [sync_completion_id] = sync_completion,
 607                 [bio_completion_id]  = bio_completion,
 608         };
 609
 610         head = nvmeq->cq_head;
 611         phase = nvmeq->cq_phase;
 612
 613         for (;;) {
 614                 unsigned long data;
 615                 void *ptr;
 616                 unsigned char handler;
 617                 struct nvme_completion cqe = nvmeq->cqes[head];
 618                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 619                         break;
 620                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 621                 if (++head == nvmeq->q_depth) {
 622                         head = 0;
 623                         phase = !phase;
 624                 }
 625
 626                 data = free_cmdid(nvmeq, cqe.command_id);
 627                 handler = data & 3;
 628                 ptr = (void *)(data & ~3UL);
 629                 completions[handler](nvmeq, ptr, &cqe);
 630         }
 631
 632         /* If the controller ignores the cq head doorbell and continuously
 633          * writes to the queue, it is theoretically possible to wrap around
 634          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 635          * requires that 0.1% of your interrupts are handled, so this isn't
 636          * a big problem.
 637          */
 638         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 639                 return IRQ_NONE;
 640
 641         writel(head, nvmeq->q_db + 1);
 642         nvmeq->cq_head = head;
 643         nvmeq->cq_phase = phase;
 644
 645         return IRQ_HANDLED;
 646 }
 647
 648 static irqreturn_t nvme_irq(int irq, void *data)
 649 {
 650         irqreturn_t result;
 651         struct nvme_queue *nvmeq = data;
 652         spin_lock(&nvmeq->q_lock);
 653         result = nvme_process_cq(nvmeq);
 654         spin_unlock(&nvmeq->q_lock);
 655         return result;
 656 }
 657
 658 static irqreturn_t nvme_irq_check(int irq, void *data)
 659 {
 660         struct nvme_queue *nvmeq = data;
 661         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 662         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 663                 return IRQ_NONE;
 664         return IRQ_WAKE_THREAD;
 665 }
 666
 667 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 668 {
 669         spin_lock_irq(&nvmeq->q_lock);
 670         cancel_cmdid_data(nvmeq, cmdid);
 671         spin_unlock_irq(&nvmeq->q_lock);
 672 }
 673
 674 /*
 675  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 676  * if the result is positive, it's an NVM Express status code
 677  */
 678 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 679                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 680 {
 681         int cmdid;
 682         struct sync_cmd_info cmdinfo;
 683
 684         cmdinfo.task = current;
 685         cmdinfo.status = -EINTR;
 686
 687         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 688                                                                 timeout);
 689         if (cmdid < 0)
 690                 return cmdid;
 691         cmd->common.command_id = cmdid;
 692
 693         set_current_state(TASK_KILLABLE);
 694         nvme_submit_cmd(nvmeq, cmd);
 695         schedule();
 696
 697         if (cmdinfo.status == -EINTR) {
 698                 nvme_abort_command(nvmeq, cmdid);
 699                 return -EINTR;
 700         }
 701
 702         if (result)
 703                 *result = cmdinfo.result;
 704
 705         return cmdinfo.status;
 706 }
 707
 708 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 709                                                                 u32 *result)
 710 {
 711         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 712 }
 713
 714 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 715 {
 716         int status;
 717         struct nvme_command c;
 718
 719         memset(&c, 0, sizeof(c));
 720         c.delete_queue.opcode = opcode;
 721         c.delete_queue.qid = cpu_to_le16(id);
 722
 723         status = nvme_submit_admin_cmd(dev, &c, NULL);
 724         if (status)
 725                 return -EIO;
 726         return 0;
 727 }
 728
 729 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 730                                                 struct nvme_queue *nvmeq)
 731 {
 732         int status;
 733         struct nvme_command c;
 734         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 735
 736         memset(&c, 0, sizeof(c));
 737         c.create_cq.opcode = nvme_admin_create_cq;
 738         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 739         c.create_cq.cqid = cpu_to_le16(qid);
 740         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 741         c.create_cq.cq_flags = cpu_to_le16(flags);
 742         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 743
 744         status = nvme_submit_admin_cmd(dev, &c, NULL);
 745         if (status)
 746                 return -EIO;
 747         return 0;
 748 }
 749
 750 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 751                                                 struct nvme_queue *nvmeq)
 752 {
 753         int status;
 754         struct nvme_command c;
 755         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 756
 757         memset(&c, 0, sizeof(c));
 758         c.create_sq.opcode = nvme_admin_create_sq;
 759         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 760         c.create_sq.sqid = cpu_to_le16(qid);
 761         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 762         c.create_sq.sq_flags = cpu_to_le16(flags);
 763         c.create_sq.cqid = cpu_to_le16(qid);
 764
 765         status = nvme_submit_admin_cmd(dev, &c, NULL);
 766         if (status)
 767                 return -EIO;
 768         return 0;
 769 }
 770
 771 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 772 {
 773         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 774 }
 775
 776 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 777 {
 778         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 779 }
 780
 781 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 782 {
 783         struct nvme_queue *nvmeq = dev->queues[qid];
 784
 785         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 786
 787         /* Don't tell the adapter to delete the admin queue */
 788         if (qid) {
 789                 adapter_delete_sq(dev, qid);
 790                 adapter_delete_cq(dev, qid);
 791         }
 792
 793         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 794                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 795         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 796                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 797         kfree(nvmeq);
 798 }
 799
 800 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 801                                                         int depth, int vector)
 802 {
 803         struct device *dmadev = &dev->pci_dev->dev;
 804         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 805         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 806         if (!nvmeq)
 807                 return NULL;
 808
 809         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 810                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 811         if (!nvmeq->cqes)
 812                 goto free_nvmeq;
 813         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 814
 815         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 816                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 817         if (!nvmeq->sq_cmds)
 818                 goto free_cqdma;
 819
 820         nvmeq->q_dmadev = dmadev;
 821         nvmeq->dev = dev;
 822         spin_lock_init(&nvmeq->q_lock);
 823         nvmeq->cq_head = 0;
 824         nvmeq->cq_phase = 1;
 825         init_waitqueue_head(&nvmeq->sq_full);
 826         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
 827         bio_list_init(&nvmeq->sq_cong);
 828         nvmeq->q_db = &dev->dbs[qid * 2];
 829         nvmeq->q_depth = depth;
 830         nvmeq->cq_vector = vector;
 831
 832         return nvmeq;
 833
 834  free_cqdma:
 835         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 836                                                         nvmeq->cq_dma_addr);
 837  free_nvmeq:
 838         kfree(nvmeq);
 839         return NULL;
 840 }
 841
 842 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 843                                                         const char *name)
 844 {
 845         if (use_threaded_interrupts)
 846                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 847                                         nvme_irq_check, nvme_irq,
 848                                         IRQF_DISABLED | IRQF_SHARED,
 849                                         name, nvmeq);
 850         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 851                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 852 }
 853
 854 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 855                                         int qid, int cq_size, int vector)
 856 {
 857         int result;
 858         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 859
 860         if (!nvmeq)
 861                 return NULL;
 862
 863         result = adapter_alloc_cq(dev, qid, nvmeq);
 864         if (result < 0)
 865                 goto free_nvmeq;
 866
 867         result = adapter_alloc_sq(dev, qid, nvmeq);
 868         if (result < 0)
 869                 goto release_cq;
 870
 871         result = queue_request_irq(dev, nvmeq, "nvme");
 872         if (result < 0)
 873                 goto release_sq;
 874
 875         return nvmeq;
 876
 877  release_sq:
 878         adapter_delete_sq(dev, qid);
 879  release_cq:
 880         adapter_delete_cq(dev, qid);
 881  free_nvmeq:
 882         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 883                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 884         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 885                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 886         kfree(nvmeq);
 887         return NULL;
 888 }
 889
 890 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 891 {
 892         int result;
 893         u32 aqa;
 894         struct nvme_queue *nvmeq;
 895
 896         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 897
 898         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 899         if (!nvmeq)
 900                 return -ENOMEM;
 901
 902         aqa = nvmeq->q_depth - 1;
 903         aqa |= aqa << 16;
 904
 905         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 906         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 907         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 908         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
 909
 910         writel(0, &dev->bar->cc);
 911         writel(aqa, &dev->bar->aqa);
 912         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 913         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 914         writel(dev->ctrl_config, &dev->bar->cc);
 915
 916         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 917                 msleep(100);
 918                 if (fatal_signal_pending(current))
 919                         return -EINTR;
 920         }
 921
 922         result = queue_request_irq(dev, nvmeq, "nvme admin");
 923         dev->queues[0] = nvmeq;
 924         return result;
 925 }
 926
 927 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 928                                 unsigned long addr, unsigned length,
 929                                 struct scatterlist **sgp)
 930 {
 931         int i, err, count, nents, offset;
 932         struct scatterlist *sg;
 933         struct page **pages;
 934
 935         if (addr & 3)
 936                 return -EINVAL;
 937         if (!length)
 938                 return -EINVAL;
 939
 940         offset = offset_in_page(addr);
 941         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 942         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 943
 944         err = get_user_pages_fast(addr, count, 1, pages);
 945         if (err < count) {
 946                 count = err;
 947                 err = -EFAULT;
 948                 goto put_pages;
 949         }
 950
 951         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 952         sg_init_table(sg, count);
 953         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 954         length -= (PAGE_SIZE - offset);
 955         for (i = 1; i < count; i++) {
 956                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 957                 length -= PAGE_SIZE;
 958         }
 959
 960         err = -ENOMEM;
 961         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 962                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 963         if (!nents)
 964                 goto put_pages;
 965
 966         kfree(pages);
 967         *sgp = sg;
 968         return nents;
 969
 970  put_pages:
 971         for (i = 0; i < count; i++)
 972                 put_page(pages[i]);
 973         kfree(pages);
 974         return err;
 975 }
 976
 977 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 978                                 unsigned long addr, int length,
 979                                 struct scatterlist *sg, int nents)
 980 {
 981         int i, count;
 982
 983         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 984         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 985
 986         for (i = 0; i < count; i++)
 987                 put_page(sg_page(&sg[i]));
 988 }
 989
 990 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 991                                         unsigned long addr, unsigned length,
 992                                         struct nvme_command *cmd)
 993 {
 994         int err, nents;
 995         struct scatterlist *sg;
 996         struct nvme_prps *prps;
 997
 998         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 999         if (nents < 0)
1000                 return nents;
1001         prps = nvme_setup_prps(dev, &cmd->common, sg, length);
1002         err = nvme_submit_admin_cmd(dev, cmd, NULL);
1003         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
1004         nvme_free_prps(dev, prps);
1005         return err ? -EIO : 0;
1006 }
1007
1008 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
1009 {
1010         struct nvme_command c;
1011
1012         memset(&c, 0, sizeof(c));
1013         c.identify.opcode = nvme_admin_identify;
1014         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1015         c.identify.cns = cpu_to_le32(cns);
1016
1017         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1018 }
1019
1020 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1021 {
1022         struct nvme_command c;
1023
1024         memset(&c, 0, sizeof(c));
1025         c.features.opcode = nvme_admin_get_features;
1026         c.features.nsid = cpu_to_le32(ns->ns_id);
1027         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1028
1029         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1030 }
1031
1032 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1033 {
1034         struct nvme_dev *dev = ns->dev;
1035         struct nvme_queue *nvmeq;
1036         struct nvme_user_io io;
1037         struct nvme_command c;
1038         unsigned length;
1039         int nents, status;
1040         struct scatterlist *sg;
1041         struct nvme_prps *prps;
1042
1043         if (copy_from_user(&io, uio, sizeof(io)))
1044                 return -EFAULT;
1045         length = (io.nblocks + 1) << ns->lba_shift;
1046
1047         switch (io.opcode) {
1048         case nvme_cmd_write:
1049         case nvme_cmd_read:
1050                 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1051                                                                 length, &sg);
1052         default:
1053                 return -EFAULT;
1054         }
1055
1056         if (nents < 0)
1057                 return nents;
1058
1059         memset(&c, 0, sizeof(c));
1060         c.rw.opcode = io.opcode;
1061         c.rw.flags = io.flags;
1062         c.rw.nsid = cpu_to_le32(ns->ns_id);
1063         c.rw.slba = cpu_to_le64(io.slba);
1064         c.rw.length = cpu_to_le16(io.nblocks);
1065         c.rw.control = cpu_to_le16(io.control);
1066         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1067         c.rw.reftag = io.reftag;
1068         c.rw.apptag = io.apptag;
1069         c.rw.appmask = io.appmask;
1070         /* XXX: metadata */
1071         prps = nvme_setup_prps(dev, &c.common, sg, length);
1072
1073         nvmeq = get_nvmeq(ns);
1074         /*
1075          * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1076          * disabled.  We may be preempted at any point, and be rescheduled
1077          * to a different CPU.  That will cause cacheline bouncing, but no
1078          * additional races since q_lock already protects against other CPUs.
1079          */
1080         put_nvmeq(nvmeq);
1081         status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
1082
1083         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1084         nvme_free_prps(dev, prps);
1085         return status;
1086 }
1087
1088 static int nvme_download_firmware(struct nvme_ns *ns,
1089                                                 struct nvme_dlfw __user *udlfw)
1090 {
1091         struct nvme_dev *dev = ns->dev;
1092         struct nvme_dlfw dlfw;
1093         struct nvme_command c;
1094         int nents, status;
1095         struct scatterlist *sg;
1096         struct nvme_prps *prps;
1097
1098         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1099                 return -EFAULT;
1100         if (dlfw.length >= (1 << 30))
1101                 return -EINVAL;
1102
1103         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1104         if (nents < 0)
1105                 return nents;
1106
1107         memset(&c, 0, sizeof(c));
1108         c.dlfw.opcode = nvme_admin_download_fw;
1109         c.dlfw.numd = cpu_to_le32(dlfw.length);
1110         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1111         prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1112
1113         status = nvme_submit_admin_cmd(dev, &c, NULL);
1114         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1115         nvme_free_prps(dev, prps);
1116         return status;
1117 }
1118
1119 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1120 {
1121         struct nvme_dev *dev = ns->dev;
1122         struct nvme_command c;
1123
1124         memset(&c, 0, sizeof(c));
1125         c.common.opcode = nvme_admin_activate_fw;
1126         c.common.rsvd10[0] = cpu_to_le32(arg);
1127
1128         return nvme_submit_admin_cmd(dev, &c, NULL);
1129 }
1130
1131 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1132                                                         unsigned long arg)
1133 {
1134         struct nvme_ns *ns = bdev->bd_disk->private_data;
1135
1136         switch (cmd) {
1137         case NVME_IOCTL_IDENTIFY_NS:
1138                 return nvme_identify(ns, arg, 0);
1139         case NVME_IOCTL_IDENTIFY_CTRL:
1140                 return nvme_identify(ns, arg, 1);
1141         case NVME_IOCTL_GET_RANGE_TYPE:
1142                 return nvme_get_range_type(ns, arg);
1143         case NVME_IOCTL_SUBMIT_IO:
1144                 return nvme_submit_io(ns, (void __user *)arg);
1145         case NVME_IOCTL_DOWNLOAD_FW:
1146                 return nvme_download_firmware(ns, (void __user *)arg);
1147         case NVME_IOCTL_ACTIVATE_FW:
1148                 return nvme_activate_firmware(ns, arg);
1149         default:
1150                 return -ENOTTY;
1151         }
1152 }
1153
1154 static const struct block_device_operations nvme_fops = {
1155         .owner          = THIS_MODULE,
1156         .ioctl          = nvme_ioctl,
1157         .compat_ioctl   = nvme_ioctl,
1158 };
1159
1160 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1161 {
1162         while (bio_list_peek(&nvmeq->sq_cong)) {
1163                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1164                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1165                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1166                         bio_list_add_head(&nvmeq->sq_cong, bio);
1167                         break;
1168                 }
1169                 if (bio_list_empty(&nvmeq->sq_cong))
1170                         remove_wait_queue(&nvmeq->sq_full,
1171                                                         &nvmeq->sq_cong_wait);
1172         }
1173 }
1174
1175 static int nvme_kthread(void *data)
1176 {
1177         struct nvme_dev *dev;
1178
1179         while (!kthread_should_stop()) {
1180                 __set_current_state(TASK_RUNNING);
1181                 spin_lock(&dev_list_lock);
1182                 list_for_each_entry(dev, &dev_list, node) {
1183                         int i;
1184                         for (i = 0; i < dev->queue_count; i++) {
1185                                 struct nvme_queue *nvmeq = dev->queues[i];
1186                                 if (!nvmeq)
1187                                         continue;
1188                                 spin_lock_irq(&nvmeq->q_lock);
1189                                 if (nvme_process_cq(nvmeq))
1190                                         printk("process_cq did something\n");
1191                                 nvme_resubmit_bios(nvmeq);
1192                                 spin_unlock_irq(&nvmeq->q_lock);
1193                         }
1194                 }
1195                 spin_unlock(&dev_list_lock);
1196                 set_current_state(TASK_INTERRUPTIBLE);
1197                 schedule_timeout(HZ);
1198         }
1199         return 0;
1200 }
1201
1202 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1203                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1204 {
1205         struct nvme_ns *ns;
1206         struct gendisk *disk;
1207         int lbaf;
1208
1209         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1210                 return NULL;
1211
1212         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1213         if (!ns)
1214                 return NULL;
1215         ns->queue = blk_alloc_queue(GFP_KERNEL);
1216         if (!ns->queue)
1217                 goto out_free_ns;
1218         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1219                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1220         blk_queue_make_request(ns->queue, nvme_make_request);
1221         ns->dev = dev;
1222         ns->queue->queuedata = ns;
1223
1224         disk = alloc_disk(NVME_MINORS);
1225         if (!disk)
1226                 goto out_free_queue;
1227         ns->ns_id = index;
1228         ns->disk = disk;
1229         lbaf = id->flbas & 0xf;
1230         ns->lba_shift = id->lbaf[lbaf].ds;
1231
1232         disk->major = nvme_major;
1233         disk->minors = NVME_MINORS;
1234         disk->first_minor = NVME_MINORS * index;
1235         disk->fops = &nvme_fops;
1236         disk->private_data = ns;
1237         disk->queue = ns->queue;
1238         disk->driverfs_dev = &dev->pci_dev->dev;
1239         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1240         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1241
1242         return ns;
1243
1244  out_free_queue:
1245         blk_cleanup_queue(ns->queue);
1246  out_free_ns:
1247         kfree(ns);
1248         return NULL;
1249 }
1250
1251 static void nvme_ns_free(struct nvme_ns *ns)
1252 {
1253         put_disk(ns->disk);
1254         blk_cleanup_queue(ns->queue);
1255         kfree(ns);
1256 }
1257
1258 static int set_queue_count(struct nvme_dev *dev, int count)
1259 {
1260         int status;
1261         u32 result;
1262         struct nvme_command c;
1263         u32 q_count = (count - 1) | ((count - 1) << 16);
1264
1265         memset(&c, 0, sizeof(c));
1266         c.features.opcode = nvme_admin_get_features;
1267         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1268         c.features.dword11 = cpu_to_le32(q_count);
1269
1270         status = nvme_submit_admin_cmd(dev, &c, &result);
1271         if (status)
1272                 return -EIO;
1273         return min(result & 0xffff, result >> 16) + 1;
1274 }
1275
1276 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1277 {
1278         int result, cpu, i, nr_io_queues;
1279
1280         nr_io_queues = num_online_cpus();
1281         result = set_queue_count(dev, nr_io_queues);
1282         if (result < 0)
1283                 return result;
1284         if (result < nr_io_queues)
1285                 nr_io_queues = result;
1286
1287         /* Deregister the admin queue's interrupt */
1288         free_irq(dev->entry[0].vector, dev->queues[0]);
1289
1290         for (i = 0; i < nr_io_queues; i++)
1291                 dev->entry[i].entry = i;
1292         for (;;) {
1293                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1294                                                                 nr_io_queues);
1295                 if (result == 0) {
1296                         break;
1297                 } else if (result > 0) {
1298                         nr_io_queues = result;
1299                         continue;
1300                 } else {
1301                         nr_io_queues = 1;
1302                         break;
1303                 }
1304         }
1305
1306         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1307         /* XXX: handle failure here */
1308
1309         cpu = cpumask_first(cpu_online_mask);
1310         for (i = 0; i < nr_io_queues; i++) {
1311                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1312                 cpu = cpumask_next(cpu, cpu_online_mask);
1313         }
1314
1315         for (i = 0; i < nr_io_queues; i++) {
1316                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1317                                                         NVME_Q_DEPTH, i);
1318                 if (!dev->queues[i + 1])
1319                         return -ENOMEM;
1320                 dev->queue_count++;
1321         }
1322
1323         for (; i < num_possible_cpus(); i++) {
1324                 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1325                 dev->queues[i + 1] = dev->queues[target + 1];
1326         }
1327
1328         return 0;
1329 }
1330
1331 static void nvme_free_queues(struct nvme_dev *dev)
1332 {
1333         int i;
1334
1335         for (i = dev->queue_count - 1; i >= 0; i--)
1336                 nvme_free_queue(dev, i);
1337 }
1338
1339 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1340 {
1341         int res, nn, i;
1342         struct nvme_ns *ns, *next;
1343         struct nvme_id_ctrl *ctrl;
1344         void *id;
1345         dma_addr_t dma_addr;
1346         struct nvme_command cid, crt;
1347
1348         res = nvme_setup_io_queues(dev);
1349         if (res)
1350                 return res;
1351
1352         /* XXX: Switch to a SG list once prp2 works */
1353         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1354                                                                 GFP_KERNEL);
1355
1356         memset(&cid, 0, sizeof(cid));
1357         cid.identify.opcode = nvme_admin_identify;
1358         cid.identify.nsid = 0;
1359         cid.identify.prp1 = cpu_to_le64(dma_addr);
1360         cid.identify.cns = cpu_to_le32(1);
1361
1362         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1363         if (res) {
1364                 res = -EIO;
1365                 goto out_free;
1366         }
1367
1368         ctrl = id;
1369         nn = le32_to_cpup(&ctrl->nn);
1370         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1371         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1372         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1373
1374         cid.identify.cns = 0;
1375         memset(&crt, 0, sizeof(crt));
1376         crt.features.opcode = nvme_admin_get_features;
1377         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1378         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1379
1380         for (i = 0; i <= nn; i++) {
1381                 cid.identify.nsid = cpu_to_le32(i);
1382                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1383                 if (res)
1384                         continue;
1385
1386                 if (((struct nvme_id_ns *)id)->ncap == 0)
1387                         continue;
1388
1389                 crt.features.nsid = cpu_to_le32(i);
1390                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1391                 if (res)
1392                         continue;
1393
1394                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1395                 if (ns)
1396                         list_add_tail(&ns->list, &dev->namespaces);
1397         }
1398         list_for_each_entry(ns, &dev->namespaces, list)
1399                 add_disk(ns->disk);
1400
1401         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1402         return 0;
1403
1404  out_free:
1405         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1406                 list_del(&ns->list);
1407                 nvme_ns_free(ns);
1408         }
1409
1410         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1411         return res;
1412 }
1413
1414 static int nvme_dev_remove(struct nvme_dev *dev)
1415 {
1416         struct nvme_ns *ns, *next;
1417
1418         spin_lock(&dev_list_lock);
1419         list_del(&dev->node);
1420         spin_unlock(&dev_list_lock);
1421
1422         /* TODO: wait all I/O finished or cancel them */
1423
1424         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1425                 list_del(&ns->list);
1426                 del_gendisk(ns->disk);
1427                 nvme_ns_free(ns);
1428         }
1429
1430         nvme_free_queues(dev);
1431
1432         return 0;
1433 }
1434
1435 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1436 {
1437         struct device *dmadev = &dev->pci_dev->dev;
1438         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1439                                                 PAGE_SIZE, PAGE_SIZE, 0);
1440         if (!dev->prp_page_pool)
1441                 return -ENOMEM;
1442
1443         /* Optimisation for I/Os between 4k and 128k */
1444         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1445                                                 256, 256, 0);
1446         if (!dev->prp_small_pool) {
1447                 dma_pool_destroy(dev->prp_page_pool);
1448                 return -ENOMEM;
1449         }
1450         return 0;
1451 }
1452
1453 static void nvme_release_prp_pools(struct nvme_dev *dev)
1454 {
1455         dma_pool_destroy(dev->prp_page_pool);
1456         dma_pool_destroy(dev->prp_small_pool);
1457 }
1458
1459 /* XXX: Use an ida or something to let remove / add work correctly */
1460 static void nvme_set_instance(struct nvme_dev *dev)
1461 {
1462         static int instance;
1463         dev->instance = instance++;
1464 }
1465
1466 static void nvme_release_instance(struct nvme_dev *dev)
1467 {
1468 }
1469
1470 static int __devinit nvme_probe(struct pci_dev *pdev,
1471                                                 const struct pci_device_id *id)
1472 {
1473         int bars, result = -ENOMEM;
1474         struct nvme_dev *dev;
1475
1476         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1477         if (!dev)
1478                 return -ENOMEM;
1479         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1480                                                                 GFP_KERNEL);
1481         if (!dev->entry)
1482                 goto free;
1483         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1484                                                                 GFP_KERNEL);
1485         if (!dev->queues)
1486                 goto free;
1487
1488         if (pci_enable_device_mem(pdev))
1489                 goto free;
1490         pci_set_master(pdev);
1491         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1492         if (pci_request_selected_regions(pdev, bars, "nvme"))
1493                 goto disable;
1494
1495         INIT_LIST_HEAD(&dev->namespaces);
1496         dev->pci_dev = pdev;
1497         pci_set_drvdata(pdev, dev);
1498         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1499         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1500         nvme_set_instance(dev);
1501         dev->entry[0].vector = pdev->irq;
1502
1503         result = nvme_setup_prp_pools(dev);
1504         if (result)
1505                 goto disable_msix;
1506
1507         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1508         if (!dev->bar) {
1509                 result = -ENOMEM;
1510                 goto disable_msix;
1511         }
1512
1513         result = nvme_configure_admin_queue(dev);
1514         if (result)
1515                 goto unmap;
1516         dev->queue_count++;
1517
1518         spin_lock(&dev_list_lock);
1519         list_add(&dev->node, &dev_list);
1520         spin_unlock(&dev_list_lock);
1521
1522         result = nvme_dev_add(dev);
1523         if (result)
1524                 goto delete;
1525
1526         return 0;
1527
1528  delete:
1529         spin_lock(&dev_list_lock);
1530         list_del(&dev->node);
1531         spin_unlock(&dev_list_lock);
1532
1533         nvme_free_queues(dev);
1534  unmap:
1535         iounmap(dev->bar);
1536  disable_msix:
1537         pci_disable_msix(pdev);
1538         nvme_release_instance(dev);
1539         nvme_release_prp_pools(dev);
1540  disable:
1541         pci_disable_device(pdev);
1542         pci_release_regions(pdev);
1543  free:
1544         kfree(dev->queues);
1545         kfree(dev->entry);
1546         kfree(dev);
1547         return result;
1548 }
1549
1550 static void __devexit nvme_remove(struct pci_dev *pdev)
1551 {
1552         struct nvme_dev *dev = pci_get_drvdata(pdev);
1553         nvme_dev_remove(dev);
1554         pci_disable_msix(pdev);
1555         iounmap(dev->bar);
1556         nvme_release_instance(dev);
1557         nvme_release_prp_pools(dev);
1558         pci_disable_device(pdev);
1559         pci_release_regions(pdev);
1560         kfree(dev->queues);
1561         kfree(dev->entry);
1562         kfree(dev);
1563 }
1564
1565 /* These functions are yet to be implemented */
1566 #define nvme_error_detected NULL
1567 #define nvme_dump_registers NULL
1568 #define nvme_link_reset NULL
1569 #define nvme_slot_reset NULL
1570 #define nvme_error_resume NULL
1571 #define nvme_suspend NULL
1572 #define nvme_resume NULL
1573
1574 static struct pci_error_handlers nvme_err_handler = {
1575         .error_detected = nvme_error_detected,
1576         .mmio_enabled   = nvme_dump_registers,
1577         .link_reset     = nvme_link_reset,
1578         .slot_reset     = nvme_slot_reset,
1579         .resume         = nvme_error_resume,
1580 };
1581
1582 /* Move to pci_ids.h later */
1583 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1584
1585 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1586         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1587         { 0, }
1588 };
1589 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1590
1591 static struct pci_driver nvme_driver = {
1592         .name           = "nvme",
1593         .id_table       = nvme_id_table,
1594         .probe          = nvme_probe,
1595         .remove         = __devexit_p(nvme_remove),
1596         .suspend        = nvme_suspend,
1597         .resume         = nvme_resume,
1598         .err_handler    = &nvme_err_handler,
1599 };
1600
1601 static int __init nvme_init(void)
1602 {
1603         int result = -EBUSY;
1604
1605         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1606         if (IS_ERR(nvme_thread))
1607                 return PTR_ERR(nvme_thread);
1608
1609         nvme_major = register_blkdev(nvme_major, "nvme");
1610         if (nvme_major <= 0)
1611                 goto kill_kthread;
1612
1613         result = pci_register_driver(&nvme_driver);
1614         if (result)
1615                 goto unregister_blkdev;
1616         return 0;
1617
1618  unregister_blkdev:
1619         unregister_blkdev(nvme_major, "nvme");
1620  kill_kthread:
1621         kthread_stop(nvme_thread);
1622         return result;
1623 }
1624
1625 static void __exit nvme_exit(void)
1626 {
1627         pci_unregister_driver(&nvme_driver);
1628         unregister_blkdev(nvme_major, "nvme");
1629         kthread_stop(nvme_thread);
1630 }
1631
1632 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1633 MODULE_LICENSE("GPL");
1634 MODULE_VERSION("0.5");
1635 module_init(nvme_init);
1636 module_exit(nvme_exit);