Pileus Git - ~andy/linux/blob - drivers/block/nvme-core.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/bitops.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/delay.h>
  24 #include <linux/errno.h>
  25 #include <linux/fs.h>
  26 #include <linux/genhd.h>
  27 #include <linux/idr.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kdev_t.h>
  32 #include <linux/kthread.h>
  33 #include <linux/kernel.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/pci.h>
  38 #include <linux/poison.h>
  39 #include <linux/ptrace.h>
  40 #include <linux/sched.h>
  41 #include <linux/slab.h>
  42 #include <linux/types.h>
  43 #include <scsi/sg.h>
  44 #include <asm-generic/io-64-nonatomic-lo-hi.h>
  45
  46 #define NVME_Q_DEPTH 1024
  47 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  48 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  49 #define NVME_MINORS 64
  50 #define ADMIN_TIMEOUT   (60 * HZ)
  51
  52 static int nvme_major;
  53 module_param(nvme_major, int, 0);
  54
  55 static int use_threaded_interrupts;
  56 module_param(use_threaded_interrupts, int, 0);
  57
  58 static DEFINE_SPINLOCK(dev_list_lock);
  59 static LIST_HEAD(dev_list);
  60 static struct task_struct *nvme_thread;
  61
  62 /*
  63  * An NVM Express queue.  Each device has at least two (one for admin
  64  * commands and one for I/O commands).
  65  */
  66 struct nvme_queue {
  67         struct device *q_dmadev;
  68         struct nvme_dev *dev;
  69         spinlock_t q_lock;
  70         struct nvme_command *sq_cmds;
  71         volatile struct nvme_completion *cqes;
  72         dma_addr_t sq_dma_addr;
  73         dma_addr_t cq_dma_addr;
  74         wait_queue_head_t sq_full;
  75         wait_queue_t sq_cong_wait;
  76         struct bio_list sq_cong;
  77         u32 __iomem *q_db;
  78         u16 q_depth;
  79         u16 cq_vector;
  80         u16 sq_head;
  81         u16 sq_tail;
  82         u16 cq_head;
  83         u8 cq_phase;
  84         u8 cqe_seen;
  85         unsigned long cmdid_data[];
  86 };
  87
  88 /*
  89  * Check we didin't inadvertently grow the command struct
  90  */
  91 static inline void _nvme_check_size(void)
  92 {
  93         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
  94         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
  95         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
  96         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
  97         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
  98         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
  99         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 100         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 101         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 102         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 103         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 104 }
 105
 106 typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
 107                                                 struct nvme_completion *);
 108
 109 struct nvme_cmd_info {
 110         nvme_completion_fn fn;
 111         void *ctx;
 112         unsigned long timeout;
 113 };
 114
 115 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 116 {
 117         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 118 }
 119
 120 /**
 121  * alloc_cmdid() - Allocate a Command ID
 122  * @nvmeq: The queue that will be used for this command
 123  * @ctx: A pointer that will be passed to the handler
 124  * @handler: The function to call on completion
 125  *
 126  * Allocate a Command ID for a queue.  The data passed in will
 127  * be passed to the completion handler.  This is implemented by using
 128  * the bottom two bits of the ctx pointer to store the handler ID.
 129  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 130  * We can change this if it becomes a problem.
 131  *
 132  * May be called with local interrupts disabled and the q_lock held,
 133  * or with interrupts enabled and no locks held.
 134  */
 135 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
 136                                 nvme_completion_fn handler, unsigned timeout)
 137 {
 138         int depth = nvmeq->q_depth - 1;
 139         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 140         int cmdid;
 141
 142         do {
 143                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 144                 if (cmdid >= depth)
 145                         return -EBUSY;
 146         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 147
 148         info[cmdid].fn = handler;
 149         info[cmdid].ctx = ctx;
 150         info[cmdid].timeout = jiffies + timeout;
 151         return cmdid;
 152 }
 153
 154 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 155                                 nvme_completion_fn handler, unsigned timeout)
 156 {
 157         int cmdid;
 158         wait_event_killable(nvmeq->sq_full,
 159                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 160         return (cmdid < 0) ? -EINTR : cmdid;
 161 }
 162
 163 /* Special values must be less than 0x1000 */
 164 #define CMD_CTX_BASE            ((void *)POISON_POINTER_DELTA)
 165 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 166 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 167 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 168 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
 169
 170 static void special_completion(struct nvme_dev *dev, void *ctx,
 171                                                 struct nvme_completion *cqe)
 172 {
 173         if (ctx == CMD_CTX_CANCELLED)
 174                 return;
 175         if (ctx == CMD_CTX_FLUSH)
 176                 return;
 177         if (ctx == CMD_CTX_COMPLETED) {
 178                 dev_warn(&dev->pci_dev->dev,
 179                                 "completed id %d twice on queue %d\n",
 180                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 181                 return;
 182         }
 183         if (ctx == CMD_CTX_INVALID) {
 184                 dev_warn(&dev->pci_dev->dev,
 185                                 "invalid id %d completed on queue %d\n",
 186                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 187                 return;
 188         }
 189
 190         dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
 191 }
 192
 193 /*
 194  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 195  */
 196 static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
 197                                                 nvme_completion_fn *fn)
 198 {
 199         void *ctx;
 200         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 201
 202         if (cmdid >= nvmeq->q_depth) {
 203                 *fn = special_completion;
 204                 return CMD_CTX_INVALID;
 205         }
 206         if (fn)
 207                 *fn = info[cmdid].fn;
 208         ctx = info[cmdid].ctx;
 209         info[cmdid].fn = special_completion;
 210         info[cmdid].ctx = CMD_CTX_COMPLETED;
 211         clear_bit(cmdid, nvmeq->cmdid_data);
 212         wake_up(&nvmeq->sq_full);
 213         return ctx;
 214 }
 215
 216 static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
 217                                                 nvme_completion_fn *fn)
 218 {
 219         void *ctx;
 220         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 221         if (fn)
 222                 *fn = info[cmdid].fn;
 223         ctx = info[cmdid].ctx;
 224         info[cmdid].fn = special_completion;
 225         info[cmdid].ctx = CMD_CTX_CANCELLED;
 226         return ctx;
 227 }
 228
 229 struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
 230 {
 231         return dev->queues[get_cpu() + 1];
 232 }
 233
 234 void put_nvmeq(struct nvme_queue *nvmeq)
 235 {
 236         put_cpu();
 237 }
 238
 239 /**
 240  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 241  * @nvmeq: The queue to use
 242  * @cmd: The command to send
 243  *
 244  * Safe to use from interrupt context
 245  */
 246 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 247 {
 248         unsigned long flags;
 249         u16 tail;
 250         spin_lock_irqsave(&nvmeq->q_lock, flags);
 251         tail = nvmeq->sq_tail;
 252         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 253         if (++tail == nvmeq->q_depth)
 254                 tail = 0;
 255         writel(tail, nvmeq->q_db);
 256         nvmeq->sq_tail = tail;
 257         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 258
 259         return 0;
 260 }
 261
 262 static __le64 **iod_list(struct nvme_iod *iod)
 263 {
 264         return ((void *)iod) + iod->offset;
 265 }
 266
 267 /*
 268  * Will slightly overestimate the number of pages needed.  This is OK
 269  * as it only leads to a small amount of wasted memory for the lifetime of
 270  * the I/O.
 271  */
 272 static int nvme_npages(unsigned size)
 273 {
 274         unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
 275         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 276 }
 277
 278 static struct nvme_iod *
 279 nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
 280 {
 281         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
 282                                 sizeof(__le64 *) * nvme_npages(nbytes) +
 283                                 sizeof(struct scatterlist) * nseg, gfp);
 284
 285         if (iod) {
 286                 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
 287                 iod->npages = -1;
 288                 iod->length = nbytes;
 289                 iod->nents = 0;
 290                 iod->start_time = jiffies;
 291         }
 292
 293         return iod;
 294 }
 295
 296 void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
 297 {
 298         const int last_prp = PAGE_SIZE / 8 - 1;
 299         int i;
 300         __le64 **list = iod_list(iod);
 301         dma_addr_t prp_dma = iod->first_dma;
 302
 303         if (iod->npages == 0)
 304                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 305         for (i = 0; i < iod->npages; i++) {
 306                 __le64 *prp_list = list[i];
 307                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 308                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 309                 prp_dma = next_prp_dma;
 310         }
 311         kfree(iod);
 312 }
 313
 314 static void nvme_start_io_acct(struct bio *bio)
 315 {
 316         struct gendisk *disk = bio->bi_bdev->bd_disk;
 317         const int rw = bio_data_dir(bio);
 318         int cpu = part_stat_lock();
 319         part_round_stats(cpu, &disk->part0);
 320         part_stat_inc(cpu, &disk->part0, ios[rw]);
 321         part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
 322         part_inc_in_flight(&disk->part0, rw);
 323         part_stat_unlock();
 324 }
 325
 326 static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
 327 {
 328         struct gendisk *disk = bio->bi_bdev->bd_disk;
 329         const int rw = bio_data_dir(bio);
 330         unsigned long duration = jiffies - start_time;
 331         int cpu = part_stat_lock();
 332         part_stat_add(cpu, &disk->part0, ticks[rw], duration);
 333         part_round_stats(cpu, &disk->part0);
 334         part_dec_in_flight(&disk->part0, rw);
 335         part_stat_unlock();
 336 }
 337
 338 static void bio_completion(struct nvme_dev *dev, void *ctx,
 339                                                 struct nvme_completion *cqe)
 340 {
 341         struct nvme_iod *iod = ctx;
 342         struct bio *bio = iod->private;
 343         u16 status = le16_to_cpup(&cqe->status) >> 1;
 344
 345         if (iod->nents)
 346                 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
 347                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 348
 349         nvme_end_io_acct(bio, iod->start_time);
 350         nvme_free_iod(dev, iod);
 351         if (status)
 352                 bio_endio(bio, -EIO);
 353         else
 354                 bio_endio(bio, 0);
 355 }
 356
 357 /* length is in bytes.  gfp flags indicates whether we may sleep. */
 358 int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd,
 359                         struct nvme_iod *iod, int total_len, gfp_t gfp)
 360 {
 361         struct dma_pool *pool;
 362         int length = total_len;
 363         struct scatterlist *sg = iod->sg;
 364         int dma_len = sg_dma_len(sg);
 365         u64 dma_addr = sg_dma_address(sg);
 366         int offset = offset_in_page(dma_addr);
 367         __le64 *prp_list;
 368         __le64 **list = iod_list(iod);
 369         dma_addr_t prp_dma;
 370         int nprps, i;
 371
 372         cmd->prp1 = cpu_to_le64(dma_addr);
 373         length -= (PAGE_SIZE - offset);
 374         if (length <= 0)
 375                 return total_len;
 376
 377         dma_len -= (PAGE_SIZE - offset);
 378         if (dma_len) {
 379                 dma_addr += (PAGE_SIZE - offset);
 380         } else {
 381                 sg = sg_next(sg);
 382                 dma_addr = sg_dma_address(sg);
 383                 dma_len = sg_dma_len(sg);
 384         }
 385
 386         if (length <= PAGE_SIZE) {
 387                 cmd->prp2 = cpu_to_le64(dma_addr);
 388                 return total_len;
 389         }
 390
 391         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 392         if (nprps <= (256 / 8)) {
 393                 pool = dev->prp_small_pool;
 394                 iod->npages = 0;
 395         } else {
 396                 pool = dev->prp_page_pool;
 397                 iod->npages = 1;
 398         }
 399
 400         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 401         if (!prp_list) {
 402                 cmd->prp2 = cpu_to_le64(dma_addr);
 403                 iod->npages = -1;
 404                 return (total_len - length) + PAGE_SIZE;
 405         }
 406         list[0] = prp_list;
 407         iod->first_dma = prp_dma;
 408         cmd->prp2 = cpu_to_le64(prp_dma);
 409         i = 0;
 410         for (;;) {
 411                 if (i == PAGE_SIZE / 8) {
 412                         __le64 *old_prp_list = prp_list;
 413                         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 414                         if (!prp_list)
 415                                 return total_len - length;
 416                         list[iod->npages++] = prp_list;
 417                         prp_list[0] = old_prp_list[i - 1];
 418                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 419                         i = 1;
 420                 }
 421                 prp_list[i++] = cpu_to_le64(dma_addr);
 422                 dma_len -= PAGE_SIZE;
 423                 dma_addr += PAGE_SIZE;
 424                 length -= PAGE_SIZE;
 425                 if (length <= 0)
 426                         break;
 427                 if (dma_len > 0)
 428                         continue;
 429                 BUG_ON(dma_len < 0);
 430                 sg = sg_next(sg);
 431                 dma_addr = sg_dma_address(sg);
 432                 dma_len = sg_dma_len(sg);
 433         }
 434
 435         return total_len;
 436 }
 437
 438 struct nvme_bio_pair {
 439         struct bio b1, b2, *parent;
 440         struct bio_vec *bv1, *bv2;
 441         int err;
 442         atomic_t cnt;
 443 };
 444
 445 static void nvme_bio_pair_endio(struct bio *bio, int err)
 446 {
 447         struct nvme_bio_pair *bp = bio->bi_private;
 448
 449         if (err)
 450                 bp->err = err;
 451
 452         if (atomic_dec_and_test(&bp->cnt)) {
 453                 bio_endio(bp->parent, bp->err);
 454                 if (bp->bv1)
 455                         kfree(bp->bv1);
 456                 if (bp->bv2)
 457                         kfree(bp->bv2);
 458                 kfree(bp);
 459         }
 460 }
 461
 462 static struct nvme_bio_pair *nvme_bio_split(struct bio *bio, int idx,
 463                                                         int len, int offset)
 464 {
 465         struct nvme_bio_pair *bp;
 466
 467         BUG_ON(len > bio->bi_size);
 468         BUG_ON(idx > bio->bi_vcnt);
 469
 470         bp = kmalloc(sizeof(*bp), GFP_ATOMIC);
 471         if (!bp)
 472                 return NULL;
 473         bp->err = 0;
 474
 475         bp->b1 = *bio;
 476         bp->b2 = *bio;
 477
 478         bp->b1.bi_size = len;
 479         bp->b2.bi_size -= len;
 480         bp->b1.bi_vcnt = idx;
 481         bp->b2.bi_idx = idx;
 482         bp->b2.bi_sector += len >> 9;
 483
 484         if (offset) {
 485                 bp->bv1 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec),
 486                                                                 GFP_ATOMIC);
 487                 if (!bp->bv1)
 488                         goto split_fail_1;
 489
 490                 bp->bv2 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec),
 491                                                                 GFP_ATOMIC);
 492                 if (!bp->bv2)
 493                         goto split_fail_2;
 494
 495                 memcpy(bp->bv1, bio->bi_io_vec,
 496                         bio->bi_max_vecs * sizeof(struct bio_vec));
 497                 memcpy(bp->bv2, bio->bi_io_vec,
 498                         bio->bi_max_vecs * sizeof(struct bio_vec));
 499
 500                 bp->b1.bi_io_vec = bp->bv1;
 501                 bp->b2.bi_io_vec = bp->bv2;
 502                 bp->b2.bi_io_vec[idx].bv_offset += offset;
 503                 bp->b2.bi_io_vec[idx].bv_len -= offset;
 504                 bp->b1.bi_io_vec[idx].bv_len = offset;
 505                 bp->b1.bi_vcnt++;
 506         } else
 507                 bp->bv1 = bp->bv2 = NULL;
 508
 509         bp->b1.bi_private = bp;
 510         bp->b2.bi_private = bp;
 511
 512         bp->b1.bi_end_io = nvme_bio_pair_endio;
 513         bp->b2.bi_end_io = nvme_bio_pair_endio;
 514
 515         bp->parent = bio;
 516         atomic_set(&bp->cnt, 2);
 517
 518         return bp;
 519
 520  split_fail_2:
 521         kfree(bp->bv1);
 522  split_fail_1:
 523         kfree(bp);
 524         return NULL;
 525 }
 526
 527 static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
 528                                                 int idx, int len, int offset)
 529 {
 530         struct nvme_bio_pair *bp = nvme_bio_split(bio, idx, len, offset);
 531         if (!bp)
 532                 return -ENOMEM;
 533
 534         if (bio_list_empty(&nvmeq->sq_cong))
 535                 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 536         bio_list_add(&nvmeq->sq_cong, &bp->b1);
 537         bio_list_add(&nvmeq->sq_cong, &bp->b2);
 538
 539         return 0;
 540 }
 541
 542 /* NVMe scatterlists require no holes in the virtual address */
 543 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
 544                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
 545
 546 static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
 547                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 548 {
 549         struct bio_vec *bvec, *bvprv = NULL;
 550         struct scatterlist *sg = NULL;
 551         int i, length = 0, nsegs = 0, split_len = bio->bi_size;
 552
 553         if (nvmeq->dev->stripe_size)
 554                 split_len = nvmeq->dev->stripe_size -
 555                         ((bio->bi_sector << 9) & (nvmeq->dev->stripe_size - 1));
 556
 557         sg_init_table(iod->sg, psegs);
 558         bio_for_each_segment(bvec, bio, i) {
 559                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 560                         sg->length += bvec->bv_len;
 561                 } else {
 562                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
 563                                 return nvme_split_and_submit(bio, nvmeq, i,
 564                                                                 length, 0);
 565
 566                         sg = sg ? sg + 1 : iod->sg;
 567                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 568                                                         bvec->bv_offset);
 569                         nsegs++;
 570                 }
 571
 572                 if (split_len - length < bvec->bv_len)
 573                         return nvme_split_and_submit(bio, nvmeq, i, split_len,
 574                                                         split_len - length);
 575                 length += bvec->bv_len;
 576                 bvprv = bvec;
 577         }
 578         iod->nents = nsegs;
 579         sg_mark_end(sg);
 580         if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
 581                 return -ENOMEM;
 582
 583         BUG_ON(length != bio->bi_size);
 584         return length;
 585 }
 586
 587 /*
 588  * We reuse the small pool to allocate the 16-byte range here as it is not
 589  * worth having a special pool for these or additional cases to handle freeing
 590  * the iod.
 591  */
 592 static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 593                 struct bio *bio, struct nvme_iod *iod, int cmdid)
 594 {
 595         struct nvme_dsm_range *range;
 596         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 597
 598         range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
 599                                                         &iod->first_dma);
 600         if (!range)
 601                 return -ENOMEM;
 602
 603         iod_list(iod)[0] = (__le64 *)range;
 604         iod->npages = 0;
 605
 606         range->cattr = cpu_to_le32(0);
 607         range->nlb = cpu_to_le32(bio->bi_size >> ns->lba_shift);
 608         range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector));
 609
 610         memset(cmnd, 0, sizeof(*cmnd));
 611         cmnd->dsm.opcode = nvme_cmd_dsm;
 612         cmnd->dsm.command_id = cmdid;
 613         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 614         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 615         cmnd->dsm.nr = 0;
 616         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 617
 618         if (++nvmeq->sq_tail == nvmeq->q_depth)
 619                 nvmeq->sq_tail = 0;
 620         writel(nvmeq->sq_tail, nvmeq->q_db);
 621
 622         return 0;
 623 }
 624
 625 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 626                                                                 int cmdid)
 627 {
 628         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 629
 630         memset(cmnd, 0, sizeof(*cmnd));
 631         cmnd->common.opcode = nvme_cmd_flush;
 632         cmnd->common.command_id = cmdid;
 633         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 634
 635         if (++nvmeq->sq_tail == nvmeq->q_depth)
 636                 nvmeq->sq_tail = 0;
 637         writel(nvmeq->sq_tail, nvmeq->q_db);
 638
 639         return 0;
 640 }
 641
 642 int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
 643 {
 644         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
 645                                         special_completion, NVME_IO_TIMEOUT);
 646         if (unlikely(cmdid < 0))
 647                 return cmdid;
 648
 649         return nvme_submit_flush(nvmeq, ns, cmdid);
 650 }
 651
 652 /*
 653  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 654  */
 655 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 656                                                                 struct bio *bio)
 657 {
 658         struct nvme_command *cmnd;
 659         struct nvme_iod *iod;
 660         enum dma_data_direction dma_dir;
 661         int cmdid, length, result;
 662         u16 control;
 663         u32 dsmgmt;
 664         int psegs = bio_phys_segments(ns->queue, bio);
 665
 666         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
 667                 result = nvme_submit_flush_data(nvmeq, ns);
 668                 if (result)
 669                         return result;
 670         }
 671
 672         result = -ENOMEM;
 673         iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
 674         if (!iod)
 675                 goto nomem;
 676         iod->private = bio;
 677
 678         result = -EBUSY;
 679         cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
 680         if (unlikely(cmdid < 0))
 681                 goto free_iod;
 682
 683         if (bio->bi_rw & REQ_DISCARD) {
 684                 result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
 685                 if (result)
 686                         goto free_cmdid;
 687                 return result;
 688         }
 689         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
 690                 return nvme_submit_flush(nvmeq, ns, cmdid);
 691
 692         control = 0;
 693         if (bio->bi_rw & REQ_FUA)
 694                 control |= NVME_RW_FUA;
 695         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 696                 control |= NVME_RW_LR;
 697
 698         dsmgmt = 0;
 699         if (bio->bi_rw & REQ_RAHEAD)
 700                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 701
 702         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 703
 704         memset(cmnd, 0, sizeof(*cmnd));
 705         if (bio_data_dir(bio)) {
 706                 cmnd->rw.opcode = nvme_cmd_write;
 707                 dma_dir = DMA_TO_DEVICE;
 708         } else {
 709                 cmnd->rw.opcode = nvme_cmd_read;
 710                 dma_dir = DMA_FROM_DEVICE;
 711         }
 712
 713         result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs);
 714         if (result <= 0)
 715                 goto free_cmdid;
 716         length = result;
 717
 718         cmnd->rw.command_id = cmdid;
 719         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 720         length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
 721                                                                 GFP_ATOMIC);
 722         cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector));
 723         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
 724         cmnd->rw.control = cpu_to_le16(control);
 725         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 726
 727         nvme_start_io_acct(bio);
 728         if (++nvmeq->sq_tail == nvmeq->q_depth)
 729                 nvmeq->sq_tail = 0;
 730         writel(nvmeq->sq_tail, nvmeq->q_db);
 731
 732         return 0;
 733
 734  free_cmdid:
 735         free_cmdid(nvmeq, cmdid, NULL);
 736  free_iod:
 737         nvme_free_iod(nvmeq->dev, iod);
 738  nomem:
 739         return result;
 740 }
 741
 742 static int nvme_process_cq(struct nvme_queue *nvmeq)
 743 {
 744         u16 head, phase;
 745
 746         head = nvmeq->cq_head;
 747         phase = nvmeq->cq_phase;
 748
 749         for (;;) {
 750                 void *ctx;
 751                 nvme_completion_fn fn;
 752                 struct nvme_completion cqe = nvmeq->cqes[head];
 753                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 754                         break;
 755                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 756                 if (++head == nvmeq->q_depth) {
 757                         head = 0;
 758                         phase = !phase;
 759                 }
 760
 761                 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
 762                 fn(nvmeq->dev, ctx, &cqe);
 763         }
 764
 765         /* If the controller ignores the cq head doorbell and continuously
 766          * writes to the queue, it is theoretically possible to wrap around
 767          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 768          * requires that 0.1% of your interrupts are handled, so this isn't
 769          * a big problem.
 770          */
 771         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 772                 return 0;
 773
 774         writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
 775         nvmeq->cq_head = head;
 776         nvmeq->cq_phase = phase;
 777
 778         nvmeq->cqe_seen = 1;
 779         return 1;
 780 }
 781
 782 static void nvme_make_request(struct request_queue *q, struct bio *bio)
 783 {
 784         struct nvme_ns *ns = q->queuedata;
 785         struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
 786         int result = -EBUSY;
 787
 788         spin_lock_irq(&nvmeq->q_lock);
 789         if (bio_list_empty(&nvmeq->sq_cong))
 790                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 791         if (unlikely(result)) {
 792                 if (bio_list_empty(&nvmeq->sq_cong))
 793                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 794                 bio_list_add(&nvmeq->sq_cong, bio);
 795         }
 796
 797         nvme_process_cq(nvmeq);
 798         spin_unlock_irq(&nvmeq->q_lock);
 799         put_nvmeq(nvmeq);
 800 }
 801
 802 static irqreturn_t nvme_irq(int irq, void *data)
 803 {
 804         irqreturn_t result;
 805         struct nvme_queue *nvmeq = data;
 806         spin_lock(&nvmeq->q_lock);
 807         nvme_process_cq(nvmeq);
 808         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 809         nvmeq->cqe_seen = 0;
 810         spin_unlock(&nvmeq->q_lock);
 811         return result;
 812 }
 813
 814 static irqreturn_t nvme_irq_check(int irq, void *data)
 815 {
 816         struct nvme_queue *nvmeq = data;
 817         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 818         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 819                 return IRQ_NONE;
 820         return IRQ_WAKE_THREAD;
 821 }
 822
 823 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 824 {
 825         spin_lock_irq(&nvmeq->q_lock);
 826         cancel_cmdid(nvmeq, cmdid, NULL);
 827         spin_unlock_irq(&nvmeq->q_lock);
 828 }
 829
 830 struct sync_cmd_info {
 831         struct task_struct *task;
 832         u32 result;
 833         int status;
 834 };
 835
 836 static void sync_completion(struct nvme_dev *dev, void *ctx,
 837                                                 struct nvme_completion *cqe)
 838 {
 839         struct sync_cmd_info *cmdinfo = ctx;
 840         cmdinfo->result = le32_to_cpup(&cqe->result);
 841         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 842         wake_up_process(cmdinfo->task);
 843 }
 844
 845 /*
 846  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 847  * if the result is positive, it's an NVM Express status code
 848  */
 849 int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
 850                                                 u32 *result, unsigned timeout)
 851 {
 852         int cmdid;
 853         struct sync_cmd_info cmdinfo;
 854
 855         cmdinfo.task = current;
 856         cmdinfo.status = -EINTR;
 857
 858         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
 859                                                                 timeout);
 860         if (cmdid < 0)
 861                 return cmdid;
 862         cmd->common.command_id = cmdid;
 863
 864         set_current_state(TASK_KILLABLE);
 865         nvme_submit_cmd(nvmeq, cmd);
 866         schedule_timeout(timeout);
 867
 868         if (cmdinfo.status == -EINTR) {
 869                 nvme_abort_command(nvmeq, cmdid);
 870                 return -EINTR;
 871         }
 872
 873         if (result)
 874                 *result = cmdinfo.result;
 875
 876         return cmdinfo.status;
 877 }
 878
 879 int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 880                                                                 u32 *result)
 881 {
 882         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 883 }
 884
 885 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 886 {
 887         int status;
 888         struct nvme_command c;
 889
 890         memset(&c, 0, sizeof(c));
 891         c.delete_queue.opcode = opcode;
 892         c.delete_queue.qid = cpu_to_le16(id);
 893
 894         status = nvme_submit_admin_cmd(dev, &c, NULL);
 895         if (status)
 896                 return -EIO;
 897         return 0;
 898 }
 899
 900 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 901                                                 struct nvme_queue *nvmeq)
 902 {
 903         int status;
 904         struct nvme_command c;
 905         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 906
 907         memset(&c, 0, sizeof(c));
 908         c.create_cq.opcode = nvme_admin_create_cq;
 909         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 910         c.create_cq.cqid = cpu_to_le16(qid);
 911         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 912         c.create_cq.cq_flags = cpu_to_le16(flags);
 913         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 914
 915         status = nvme_submit_admin_cmd(dev, &c, NULL);
 916         if (status)
 917                 return -EIO;
 918         return 0;
 919 }
 920
 921 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 922                                                 struct nvme_queue *nvmeq)
 923 {
 924         int status;
 925         struct nvme_command c;
 926         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 927
 928         memset(&c, 0, sizeof(c));
 929         c.create_sq.opcode = nvme_admin_create_sq;
 930         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 931         c.create_sq.sqid = cpu_to_le16(qid);
 932         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 933         c.create_sq.sq_flags = cpu_to_le16(flags);
 934         c.create_sq.cqid = cpu_to_le16(qid);
 935
 936         status = nvme_submit_admin_cmd(dev, &c, NULL);
 937         if (status)
 938                 return -EIO;
 939         return 0;
 940 }
 941
 942 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 943 {
 944         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 945 }
 946
 947 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 948 {
 949         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 950 }
 951
 952 int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
 953                                                         dma_addr_t dma_addr)
 954 {
 955         struct nvme_command c;
 956
 957         memset(&c, 0, sizeof(c));
 958         c.identify.opcode = nvme_admin_identify;
 959         c.identify.nsid = cpu_to_le32(nsid);
 960         c.identify.prp1 = cpu_to_le64(dma_addr);
 961         c.identify.cns = cpu_to_le32(cns);
 962
 963         return nvme_submit_admin_cmd(dev, &c, NULL);
 964 }
 965
 966 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
 967                                         dma_addr_t dma_addr, u32 *result)
 968 {
 969         struct nvme_command c;
 970
 971         memset(&c, 0, sizeof(c));
 972         c.features.opcode = nvme_admin_get_features;
 973         c.features.nsid = cpu_to_le32(nsid);
 974         c.features.prp1 = cpu_to_le64(dma_addr);
 975         c.features.fid = cpu_to_le32(fid);
 976
 977         return nvme_submit_admin_cmd(dev, &c, result);
 978 }
 979
 980 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
 981                                         dma_addr_t dma_addr, u32 *result)
 982 {
 983         struct nvme_command c;
 984
 985         memset(&c, 0, sizeof(c));
 986         c.features.opcode = nvme_admin_set_features;
 987         c.features.prp1 = cpu_to_le64(dma_addr);
 988         c.features.fid = cpu_to_le32(fid);
 989         c.features.dword11 = cpu_to_le32(dword11);
 990
 991         return nvme_submit_admin_cmd(dev, &c, result);
 992 }
 993
 994 /**
 995  * nvme_cancel_ios - Cancel outstanding I/Os
 996  * @queue: The queue to cancel I/Os on
 997  * @timeout: True to only cancel I/Os which have timed out
 998  */
 999 static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1000 {
1001         int depth = nvmeq->q_depth - 1;
1002         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1003         unsigned long now = jiffies;
1004         int cmdid;
1005
1006         for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1007                 void *ctx;
1008                 nvme_completion_fn fn;
1009                 static struct nvme_completion cqe = {
1010                         .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
1011                 };
1012
1013                 if (timeout && !time_after(now, info[cmdid].timeout))
1014                         continue;
1015                 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1016                         continue;
1017                 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid);
1018                 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
1019                 fn(nvmeq->dev, ctx, &cqe);
1020         }
1021 }
1022
1023 static void nvme_free_queue_mem(struct nvme_queue *nvmeq)
1024 {
1025         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1026                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1027         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1028                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1029         kfree(nvmeq);
1030 }
1031
1032 static void nvme_free_queue(struct nvme_dev *dev, int qid)
1033 {
1034         struct nvme_queue *nvmeq = dev->queues[qid];
1035         int vector = dev->entry[nvmeq->cq_vector].vector;
1036
1037         spin_lock_irq(&nvmeq->q_lock);
1038         nvme_cancel_ios(nvmeq, false);
1039         while (bio_list_peek(&nvmeq->sq_cong)) {
1040                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1041                 bio_endio(bio, -EIO);
1042         }
1043         spin_unlock_irq(&nvmeq->q_lock);
1044
1045         irq_set_affinity_hint(vector, NULL);
1046         free_irq(vector, nvmeq);
1047
1048         /* Don't tell the adapter to delete the admin queue */
1049         if (qid) {
1050                 adapter_delete_sq(dev, qid);
1051                 adapter_delete_cq(dev, qid);
1052         }
1053
1054         nvme_free_queue_mem(nvmeq);
1055 }
1056
1057 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1058                                                         int depth, int vector)
1059 {
1060         struct device *dmadev = &dev->pci_dev->dev;
1061         unsigned extra = DIV_ROUND_UP(depth, 8) + (depth *
1062                                                 sizeof(struct nvme_cmd_info));
1063         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1064         if (!nvmeq)
1065                 return NULL;
1066
1067         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1068                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
1069         if (!nvmeq->cqes)
1070                 goto free_nvmeq;
1071         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1072
1073         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1074                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1075         if (!nvmeq->sq_cmds)
1076                 goto free_cqdma;
1077
1078         nvmeq->q_dmadev = dmadev;
1079         nvmeq->dev = dev;
1080         spin_lock_init(&nvmeq->q_lock);
1081         nvmeq->cq_head = 0;
1082         nvmeq->cq_phase = 1;
1083         init_waitqueue_head(&nvmeq->sq_full);
1084         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
1085         bio_list_init(&nvmeq->sq_cong);
1086         nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
1087         nvmeq->q_depth = depth;
1088         nvmeq->cq_vector = vector;
1089
1090         return nvmeq;
1091
1092  free_cqdma:
1093         dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1094                                                         nvmeq->cq_dma_addr);
1095  free_nvmeq:
1096         kfree(nvmeq);
1097         return NULL;
1098 }
1099
1100 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1101                                                         const char *name)
1102 {
1103         if (use_threaded_interrupts)
1104                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1105                                         nvme_irq_check, nvme_irq,
1106                                         IRQF_DISABLED | IRQF_SHARED,
1107                                         name, nvmeq);
1108         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1109                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
1110 }
1111
1112 static struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, int qid,
1113                                             int cq_size, int vector)
1114 {
1115         int result;
1116         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
1117
1118         if (!nvmeq)
1119                 return ERR_PTR(-ENOMEM);
1120
1121         result = adapter_alloc_cq(dev, qid, nvmeq);
1122         if (result < 0)
1123                 goto free_nvmeq;
1124
1125         result = adapter_alloc_sq(dev, qid, nvmeq);
1126         if (result < 0)
1127                 goto release_cq;
1128
1129         result = queue_request_irq(dev, nvmeq, "nvme");
1130         if (result < 0)
1131                 goto release_sq;
1132
1133         return nvmeq;
1134
1135  release_sq:
1136         adapter_delete_sq(dev, qid);
1137  release_cq:
1138         adapter_delete_cq(dev, qid);
1139  free_nvmeq:
1140         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1141                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1142         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1143                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1144         kfree(nvmeq);
1145         return ERR_PTR(result);
1146 }
1147
1148 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1149 {
1150         unsigned long timeout;
1151         u32 bit = enabled ? NVME_CSTS_RDY : 0;
1152
1153         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1154
1155         while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1156                 msleep(100);
1157                 if (fatal_signal_pending(current))
1158                         return -EINTR;
1159                 if (time_after(jiffies, timeout)) {
1160                         dev_err(&dev->pci_dev->dev,
1161                                 "Device not ready; aborting initialisation\n");
1162                         return -ENODEV;
1163                 }
1164         }
1165
1166         return 0;
1167 }
1168
1169 /*
1170  * If the device has been passed off to us in an enabled state, just clear
1171  * the enabled bit.  The spec says we should set the 'shutdown notification
1172  * bits', but doing so may cause the device to complete commands to the
1173  * admin queue ... and we don't know what memory that might be pointing at!
1174  */
1175 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1176 {
1177         u32 cc = readl(&dev->bar->cc);
1178
1179         if (cc & NVME_CC_ENABLE)
1180                 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
1181         return nvme_wait_ready(dev, cap, false);
1182 }
1183
1184 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1185 {
1186         return nvme_wait_ready(dev, cap, true);
1187 }
1188
1189 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1190 {
1191         int result;
1192         u32 aqa;
1193         u64 cap = readq(&dev->bar->cap);
1194         struct nvme_queue *nvmeq;
1195
1196         dev->dbs = ((void __iomem *)dev->bar) + 4096;
1197         dev->db_stride = NVME_CAP_STRIDE(cap);
1198
1199         result = nvme_disable_ctrl(dev, cap);
1200         if (result < 0)
1201                 return result;
1202
1203         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1204         if (!nvmeq)
1205                 return -ENOMEM;
1206
1207         aqa = nvmeq->q_depth - 1;
1208         aqa |= aqa << 16;
1209
1210         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1211         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1212         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1213         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1214
1215         writel(aqa, &dev->bar->aqa);
1216         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1217         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1218         writel(dev->ctrl_config, &dev->bar->cc);
1219
1220         result = nvme_enable_ctrl(dev, cap);
1221         if (result)
1222                 goto free_q;
1223
1224         result = queue_request_irq(dev, nvmeq, "nvme admin");
1225         if (result)
1226                 goto free_q;
1227
1228         dev->queues[0] = nvmeq;
1229         return result;
1230
1231  free_q:
1232         nvme_free_queue_mem(nvmeq);
1233         return result;
1234 }
1235
1236 struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1237                                 unsigned long addr, unsigned length)
1238 {
1239         int i, err, count, nents, offset;
1240         struct scatterlist *sg;
1241         struct page **pages;
1242         struct nvme_iod *iod;
1243
1244         if (addr & 3)
1245                 return ERR_PTR(-EINVAL);
1246         if (!length || length > INT_MAX - PAGE_SIZE)
1247                 return ERR_PTR(-EINVAL);
1248
1249         offset = offset_in_page(addr);
1250         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1251         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1252         if (!pages)
1253                 return ERR_PTR(-ENOMEM);
1254
1255         err = get_user_pages_fast(addr, count, 1, pages);
1256         if (err < count) {
1257                 count = err;
1258                 err = -EFAULT;
1259                 goto put_pages;
1260         }
1261
1262         iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1263         sg = iod->sg;
1264         sg_init_table(sg, count);
1265         for (i = 0; i < count; i++) {
1266                 sg_set_page(&sg[i], pages[i],
1267                             min_t(unsigned, length, PAGE_SIZE - offset),
1268                             offset);
1269                 length -= (PAGE_SIZE - offset);
1270                 offset = 0;
1271         }
1272         sg_mark_end(&sg[i - 1]);
1273         iod->nents = count;
1274
1275         err = -ENOMEM;
1276         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1277                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1278         if (!nents)
1279                 goto free_iod;
1280
1281         kfree(pages);
1282         return iod;
1283
1284  free_iod:
1285         kfree(iod);
1286  put_pages:
1287         for (i = 0; i < count; i++)
1288                 put_page(pages[i]);
1289         kfree(pages);
1290         return ERR_PTR(err);
1291 }
1292
1293 void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1294                         struct nvme_iod *iod)
1295 {
1296         int i;
1297
1298         dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1299                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1300
1301         for (i = 0; i < iod->nents; i++)
1302                 put_page(sg_page(&iod->sg[i]));
1303 }
1304
1305 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1306 {
1307         struct nvme_dev *dev = ns->dev;
1308         struct nvme_queue *nvmeq;
1309         struct nvme_user_io io;
1310         struct nvme_command c;
1311         unsigned length, meta_len;
1312         int status, i;
1313         struct nvme_iod *iod, *meta_iod = NULL;
1314         dma_addr_t meta_dma_addr;
1315         void *meta, *uninitialized_var(meta_mem);
1316
1317         if (copy_from_user(&io, uio, sizeof(io)))
1318                 return -EFAULT;
1319         length = (io.nblocks + 1) << ns->lba_shift;
1320         meta_len = (io.nblocks + 1) * ns->ms;
1321
1322         if (meta_len && ((io.metadata & 3) || !io.metadata))
1323                 return -EINVAL;
1324
1325         switch (io.opcode) {
1326         case nvme_cmd_write:
1327         case nvme_cmd_read:
1328         case nvme_cmd_compare:
1329                 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1330                 break;
1331         default:
1332                 return -EINVAL;
1333         }
1334
1335         if (IS_ERR(iod))
1336                 return PTR_ERR(iod);
1337
1338         memset(&c, 0, sizeof(c));
1339         c.rw.opcode = io.opcode;
1340         c.rw.flags = io.flags;
1341         c.rw.nsid = cpu_to_le32(ns->ns_id);
1342         c.rw.slba = cpu_to_le64(io.slba);
1343         c.rw.length = cpu_to_le16(io.nblocks);
1344         c.rw.control = cpu_to_le16(io.control);
1345         c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1346         c.rw.reftag = cpu_to_le32(io.reftag);
1347         c.rw.apptag = cpu_to_le16(io.apptag);
1348         c.rw.appmask = cpu_to_le16(io.appmask);
1349
1350         if (meta_len) {
1351                 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata, meta_len);
1352                 if (IS_ERR(meta_iod)) {
1353                         status = PTR_ERR(meta_iod);
1354                         meta_iod = NULL;
1355                         goto unmap;
1356                 }
1357
1358                 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1359                                                 &meta_dma_addr, GFP_KERNEL);
1360                 if (!meta_mem) {
1361                         status = -ENOMEM;
1362                         goto unmap;
1363                 }
1364
1365                 if (io.opcode & 1) {
1366                         int meta_offset = 0;
1367
1368                         for (i = 0; i < meta_iod->nents; i++) {
1369                                 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1370                                                 meta_iod->sg[i].offset;
1371                                 memcpy(meta_mem + meta_offset, meta,
1372                                                 meta_iod->sg[i].length);
1373                                 kunmap_atomic(meta);
1374                                 meta_offset += meta_iod->sg[i].length;
1375                         }
1376                 }
1377
1378                 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1379         }
1380
1381         length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
1382
1383         nvmeq = get_nvmeq(dev);
1384         /*
1385          * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1386          * disabled.  We may be preempted at any point, and be rescheduled
1387          * to a different CPU.  That will cause cacheline bouncing, but no
1388          * additional races since q_lock already protects against other CPUs.
1389          */
1390         put_nvmeq(nvmeq);
1391         if (length != (io.nblocks + 1) << ns->lba_shift)
1392                 status = -ENOMEM;
1393         else
1394                 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
1395
1396         if (meta_len) {
1397                 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1398                         int meta_offset = 0;
1399
1400                         for (i = 0; i < meta_iod->nents; i++) {
1401                                 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1402                                                 meta_iod->sg[i].offset;
1403                                 memcpy(meta, meta_mem + meta_offset,
1404                                                 meta_iod->sg[i].length);
1405                                 kunmap_atomic(meta);
1406                                 meta_offset += meta_iod->sg[i].length;
1407                         }
1408                 }
1409
1410                 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1411                                                                 meta_dma_addr);
1412         }
1413
1414  unmap:
1415         nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1416         nvme_free_iod(dev, iod);
1417
1418         if (meta_iod) {
1419                 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1420                 nvme_free_iod(dev, meta_iod);
1421         }
1422
1423         return status;
1424 }
1425
1426 static int nvme_user_admin_cmd(struct nvme_dev *dev,
1427                                         struct nvme_admin_cmd __user *ucmd)
1428 {
1429         struct nvme_admin_cmd cmd;
1430         struct nvme_command c;
1431         int status, length;
1432         struct nvme_iod *uninitialized_var(iod);
1433         unsigned timeout;
1434
1435         if (!capable(CAP_SYS_ADMIN))
1436                 return -EACCES;
1437         if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1438                 return -EFAULT;
1439
1440         memset(&c, 0, sizeof(c));
1441         c.common.opcode = cmd.opcode;
1442         c.common.flags = cmd.flags;
1443         c.common.nsid = cpu_to_le32(cmd.nsid);
1444         c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1445         c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1446         c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1447         c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1448         c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1449         c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1450         c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1451         c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1452
1453         length = cmd.data_len;
1454         if (cmd.data_len) {
1455                 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1456                                                                 length);
1457                 if (IS_ERR(iod))
1458                         return PTR_ERR(iod);
1459                 length = nvme_setup_prps(dev, &c.common, iod, length,
1460                                                                 GFP_KERNEL);
1461         }
1462
1463         timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1464                                                                 ADMIN_TIMEOUT;
1465         if (length != cmd.data_len)
1466                 status = -ENOMEM;
1467         else
1468                 status = nvme_submit_sync_cmd(dev->queues[0], &c, &cmd.result,
1469                                                                 timeout);
1470
1471         if (cmd.data_len) {
1472                 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1473                 nvme_free_iod(dev, iod);
1474         }
1475
1476         if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
1477                                                         sizeof(cmd.result)))
1478                 status = -EFAULT;
1479
1480         return status;
1481 }
1482
1483 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1484                                                         unsigned long arg)
1485 {
1486         struct nvme_ns *ns = bdev->bd_disk->private_data;
1487
1488         switch (cmd) {
1489         case NVME_IOCTL_ID:
1490                 force_successful_syscall_return();
1491                 return ns->ns_id;
1492         case NVME_IOCTL_ADMIN_CMD:
1493                 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
1494         case NVME_IOCTL_SUBMIT_IO:
1495                 return nvme_submit_io(ns, (void __user *)arg);
1496         case SG_GET_VERSION_NUM:
1497                 return nvme_sg_get_version_num((void __user *)arg);
1498         case SG_IO:
1499                 return nvme_sg_io(ns, (void __user *)arg);
1500         default:
1501                 return -ENOTTY;
1502         }
1503 }
1504
1505 static const struct block_device_operations nvme_fops = {
1506         .owner          = THIS_MODULE,
1507         .ioctl          = nvme_ioctl,
1508         .compat_ioctl   = nvme_ioctl,
1509 };
1510
1511 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1512 {
1513         while (bio_list_peek(&nvmeq->sq_cong)) {
1514                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1515                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1516
1517                 if (bio_list_empty(&nvmeq->sq_cong))
1518                         remove_wait_queue(&nvmeq->sq_full,
1519                                                         &nvmeq->sq_cong_wait);
1520                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1521                         if (bio_list_empty(&nvmeq->sq_cong))
1522                                 add_wait_queue(&nvmeq->sq_full,
1523                                                         &nvmeq->sq_cong_wait);
1524                         bio_list_add_head(&nvmeq->sq_cong, bio);
1525                         break;
1526                 }
1527         }
1528 }
1529
1530 static int nvme_kthread(void *data)
1531 {
1532         struct nvme_dev *dev;
1533
1534         while (!kthread_should_stop()) {
1535                 set_current_state(TASK_INTERRUPTIBLE);
1536                 spin_lock(&dev_list_lock);
1537                 list_for_each_entry(dev, &dev_list, node) {
1538                         int i;
1539                         for (i = 0; i < dev->queue_count; i++) {
1540                                 struct nvme_queue *nvmeq = dev->queues[i];
1541                                 if (!nvmeq)
1542                                         continue;
1543                                 spin_lock_irq(&nvmeq->q_lock);
1544                                 nvme_process_cq(nvmeq);
1545                                 nvme_cancel_ios(nvmeq, true);
1546                                 nvme_resubmit_bios(nvmeq);
1547                                 spin_unlock_irq(&nvmeq->q_lock);
1548                         }
1549                 }
1550                 spin_unlock(&dev_list_lock);
1551                 schedule_timeout(round_jiffies_relative(HZ));
1552         }
1553         return 0;
1554 }
1555
1556 static DEFINE_IDA(nvme_index_ida);
1557
1558 static int nvme_get_ns_idx(void)
1559 {
1560         int index, error;
1561
1562         do {
1563                 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1564                         return -1;
1565
1566                 spin_lock(&dev_list_lock);
1567                 error = ida_get_new(&nvme_index_ida, &index);
1568                 spin_unlock(&dev_list_lock);
1569         } while (error == -EAGAIN);
1570
1571         if (error)
1572                 index = -1;
1573         return index;
1574 }
1575
1576 static void nvme_put_ns_idx(int index)
1577 {
1578         spin_lock(&dev_list_lock);
1579         ida_remove(&nvme_index_ida, index);
1580         spin_unlock(&dev_list_lock);
1581 }
1582
1583 static void nvme_config_discard(struct nvme_ns *ns)
1584 {
1585         u32 logical_block_size = queue_logical_block_size(ns->queue);
1586         ns->queue->limits.discard_zeroes_data = 0;
1587         ns->queue->limits.discard_alignment = logical_block_size;
1588         ns->queue->limits.discard_granularity = logical_block_size;
1589         ns->queue->limits.max_discard_sectors = 0xffffffff;
1590         queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1591 }
1592
1593 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
1594                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1595 {
1596         struct nvme_ns *ns;
1597         struct gendisk *disk;
1598         int lbaf;
1599
1600         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1601                 return NULL;
1602
1603         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1604         if (!ns)
1605                 return NULL;
1606         ns->queue = blk_alloc_queue(GFP_KERNEL);
1607         if (!ns->queue)
1608                 goto out_free_ns;
1609         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1610         queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1611         queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1612         blk_queue_make_request(ns->queue, nvme_make_request);
1613         ns->dev = dev;
1614         ns->queue->queuedata = ns;
1615
1616         disk = alloc_disk(NVME_MINORS);
1617         if (!disk)
1618                 goto out_free_queue;
1619         ns->ns_id = nsid;
1620         ns->disk = disk;
1621         lbaf = id->flbas & 0xf;
1622         ns->lba_shift = id->lbaf[lbaf].ds;
1623         ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
1624         blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1625         if (dev->max_hw_sectors)
1626                 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
1627
1628         disk->major = nvme_major;
1629         disk->minors = NVME_MINORS;
1630         disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1631         disk->fops = &nvme_fops;
1632         disk->private_data = ns;
1633         disk->queue = ns->queue;
1634         disk->driverfs_dev = &dev->pci_dev->dev;
1635         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1636         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1637
1638         if (dev->oncs & NVME_CTRL_ONCS_DSM)
1639                 nvme_config_discard(ns);
1640
1641         return ns;
1642
1643  out_free_queue:
1644         blk_cleanup_queue(ns->queue);
1645  out_free_ns:
1646         kfree(ns);
1647         return NULL;
1648 }
1649
1650 static void nvme_ns_free(struct nvme_ns *ns)
1651 {
1652         int index = ns->disk->first_minor / NVME_MINORS;
1653         put_disk(ns->disk);
1654         nvme_put_ns_idx(index);
1655         blk_cleanup_queue(ns->queue);
1656         kfree(ns);
1657 }
1658
1659 static int set_queue_count(struct nvme_dev *dev, int count)
1660 {
1661         int status;
1662         u32 result;
1663         u32 q_count = (count - 1) | ((count - 1) << 16);
1664
1665         status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1666                                                                 &result);
1667         if (status)
1668                 return -EIO;
1669         return min(result & 0xffff, result >> 16) + 1;
1670 }
1671
1672 static int nvme_setup_io_queues(struct nvme_dev *dev)
1673 {
1674         struct pci_dev *pdev = dev->pci_dev;
1675         int result, cpu, i, vecs, nr_io_queues, db_bar_size, q_depth;
1676
1677         nr_io_queues = num_online_cpus();
1678         result = set_queue_count(dev, nr_io_queues);
1679         if (result < 0)
1680                 return result;
1681         if (result < nr_io_queues)
1682                 nr_io_queues = result;
1683
1684         /* Deregister the admin queue's interrupt */
1685         free_irq(dev->entry[0].vector, dev->queues[0]);
1686
1687         db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1688         if (db_bar_size > 8192) {
1689                 iounmap(dev->bar);
1690                 dev->bar = ioremap(pci_resource_start(pdev, 0), db_bar_size);
1691                 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1692                 dev->queues[0]->q_db = dev->dbs;
1693         }
1694
1695         vecs = nr_io_queues;
1696         for (i = 0; i < vecs; i++)
1697                 dev->entry[i].entry = i;
1698         for (;;) {
1699                 result = pci_enable_msix(pdev, dev->entry, vecs);
1700                 if (result <= 0)
1701                         break;
1702                 vecs = result;
1703         }
1704
1705         if (result < 0) {
1706                 vecs = nr_io_queues;
1707                 if (vecs > 32)
1708                         vecs = 32;
1709                 for (;;) {
1710                         result = pci_enable_msi_block(pdev, vecs);
1711                         if (result == 0) {
1712                                 for (i = 0; i < vecs; i++)
1713                                         dev->entry[i].vector = i + pdev->irq;
1714                                 break;
1715                         } else if (result < 0) {
1716                                 vecs = 1;
1717                                 break;
1718                         }
1719                         vecs = result;
1720                 }
1721         }
1722
1723         /*
1724          * Should investigate if there's a performance win from allocating
1725          * more queues than interrupt vectors; it might allow the submission
1726          * path to scale better, even if the receive path is limited by the
1727          * number of interrupts.
1728          */
1729         nr_io_queues = vecs;
1730
1731         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1732         /* XXX: handle failure here */
1733
1734         cpu = cpumask_first(cpu_online_mask);
1735         for (i = 0; i < nr_io_queues; i++) {
1736                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1737                 cpu = cpumask_next(cpu, cpu_online_mask);
1738         }
1739
1740         q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1,
1741                                                                 NVME_Q_DEPTH);
1742         for (i = 0; i < nr_io_queues; i++) {
1743                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1, q_depth, i);
1744                 if (IS_ERR(dev->queues[i + 1]))
1745                         return PTR_ERR(dev->queues[i + 1]);
1746                 dev->queue_count++;
1747         }
1748
1749         for (; i < num_possible_cpus(); i++) {
1750                 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1751                 dev->queues[i + 1] = dev->queues[target + 1];
1752         }
1753
1754         return 0;
1755 }
1756
1757 static void nvme_free_queues(struct nvme_dev *dev)
1758 {
1759         int i;
1760
1761         for (i = dev->queue_count - 1; i >= 0; i--)
1762                 nvme_free_queue(dev, i);
1763 }
1764
1765 /*
1766  * Return: error value if an error occurred setting up the queues or calling
1767  * Identify Device.  0 if these succeeded, even if adding some of the
1768  * namespaces failed.  At the moment, these failures are silent.  TBD which
1769  * failures should be reported.
1770  */
1771 static int nvme_dev_add(struct nvme_dev *dev)
1772 {
1773         int res;
1774         unsigned nn, i;
1775         struct nvme_ns *ns;
1776         struct nvme_id_ctrl *ctrl;
1777         struct nvme_id_ns *id_ns;
1778         void *mem;
1779         dma_addr_t dma_addr;
1780         int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
1781
1782         res = nvme_setup_io_queues(dev);
1783         if (res)
1784                 return res;
1785
1786         mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1787                                                                 GFP_KERNEL);
1788         if (!mem)
1789                 return -ENOMEM;
1790
1791         res = nvme_identify(dev, 0, 1, dma_addr);
1792         if (res) {
1793                 res = -EIO;
1794                 goto out;
1795         }
1796
1797         ctrl = mem;
1798         nn = le32_to_cpup(&ctrl->nn);
1799         dev->oncs = le16_to_cpup(&ctrl->oncs);
1800         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1801         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1802         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1803         if (ctrl->mdts)
1804                 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
1805         if ((dev->pci_dev->vendor == PCI_VENDOR_ID_INTEL) &&
1806                         (dev->pci_dev->device == 0x0953) && ctrl->vs[3])
1807                 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
1808
1809         id_ns = mem;
1810         for (i = 1; i <= nn; i++) {
1811                 res = nvme_identify(dev, i, 0, dma_addr);
1812                 if (res)
1813                         continue;
1814
1815                 if (id_ns->ncap == 0)
1816                         continue;
1817
1818                 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
1819                                                         dma_addr + 4096, NULL);
1820                 if (res)
1821                         memset(mem + 4096, 0, 4096);
1822
1823                 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
1824                 if (ns)
1825                         list_add_tail(&ns->list, &dev->namespaces);
1826         }
1827         list_for_each_entry(ns, &dev->namespaces, list)
1828                 add_disk(ns->disk);
1829         res = 0;
1830
1831  out:
1832         dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1833         return res;
1834 }
1835
1836 static int nvme_dev_remove(struct nvme_dev *dev)
1837 {
1838         struct nvme_ns *ns, *next;
1839
1840         spin_lock(&dev_list_lock);
1841         list_del(&dev->node);
1842         spin_unlock(&dev_list_lock);
1843
1844         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1845                 list_del(&ns->list);
1846                 del_gendisk(ns->disk);
1847                 nvme_ns_free(ns);
1848         }
1849
1850         nvme_free_queues(dev);
1851
1852         return 0;
1853 }
1854
1855 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1856 {
1857         struct device *dmadev = &dev->pci_dev->dev;
1858         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1859                                                 PAGE_SIZE, PAGE_SIZE, 0);
1860         if (!dev->prp_page_pool)
1861                 return -ENOMEM;
1862
1863         /* Optimisation for I/Os between 4k and 128k */
1864         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1865                                                 256, 256, 0);
1866         if (!dev->prp_small_pool) {
1867                 dma_pool_destroy(dev->prp_page_pool);
1868                 return -ENOMEM;
1869         }
1870         return 0;
1871 }
1872
1873 static void nvme_release_prp_pools(struct nvme_dev *dev)
1874 {
1875         dma_pool_destroy(dev->prp_page_pool);
1876         dma_pool_destroy(dev->prp_small_pool);
1877 }
1878
1879 static DEFINE_IDA(nvme_instance_ida);
1880
1881 static int nvme_set_instance(struct nvme_dev *dev)
1882 {
1883         int instance, error;
1884
1885         do {
1886                 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
1887                         return -ENODEV;
1888
1889                 spin_lock(&dev_list_lock);
1890                 error = ida_get_new(&nvme_instance_ida, &instance);
1891                 spin_unlock(&dev_list_lock);
1892         } while (error == -EAGAIN);
1893
1894         if (error)
1895                 return -ENODEV;
1896
1897         dev->instance = instance;
1898         return 0;
1899 }
1900
1901 static void nvme_release_instance(struct nvme_dev *dev)
1902 {
1903         spin_lock(&dev_list_lock);
1904         ida_remove(&nvme_instance_ida, dev->instance);
1905         spin_unlock(&dev_list_lock);
1906 }
1907
1908 static void nvme_free_dev(struct kref *kref)
1909 {
1910         struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
1911         nvme_dev_remove(dev);
1912         if (dev->pci_dev->msi_enabled)
1913                 pci_disable_msi(dev->pci_dev);
1914         else if (dev->pci_dev->msix_enabled)
1915                 pci_disable_msix(dev->pci_dev);
1916         iounmap(dev->bar);
1917         nvme_release_instance(dev);
1918         nvme_release_prp_pools(dev);
1919         pci_disable_device(dev->pci_dev);
1920         pci_release_regions(dev->pci_dev);
1921         kfree(dev->queues);
1922         kfree(dev->entry);
1923         kfree(dev);
1924 }
1925
1926 static int nvme_dev_open(struct inode *inode, struct file *f)
1927 {
1928         struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
1929                                                                 miscdev);
1930         kref_get(&dev->kref);
1931         f->private_data = dev;
1932         return 0;
1933 }
1934
1935 static int nvme_dev_release(struct inode *inode, struct file *f)
1936 {
1937         struct nvme_dev *dev = f->private_data;
1938         kref_put(&dev->kref, nvme_free_dev);
1939         return 0;
1940 }
1941
1942 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1943 {
1944         struct nvme_dev *dev = f->private_data;
1945         switch (cmd) {
1946         case NVME_IOCTL_ADMIN_CMD:
1947                 return nvme_user_admin_cmd(dev, (void __user *)arg);
1948         default:
1949                 return -ENOTTY;
1950         }
1951 }
1952
1953 static const struct file_operations nvme_dev_fops = {
1954         .owner          = THIS_MODULE,
1955         .open           = nvme_dev_open,
1956         .release        = nvme_dev_release,
1957         .unlocked_ioctl = nvme_dev_ioctl,
1958         .compat_ioctl   = nvme_dev_ioctl,
1959 };
1960
1961 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1962 {
1963         int bars, result = -ENOMEM;
1964         struct nvme_dev *dev;
1965
1966         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1967         if (!dev)
1968                 return -ENOMEM;
1969         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1970                                                                 GFP_KERNEL);
1971         if (!dev->entry)
1972                 goto free;
1973         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1974                                                                 GFP_KERNEL);
1975         if (!dev->queues)
1976                 goto free;
1977
1978         if (pci_enable_device_mem(pdev))
1979                 goto free;
1980         pci_set_master(pdev);
1981         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1982         if (pci_request_selected_regions(pdev, bars, "nvme"))
1983                 goto disable;
1984
1985         INIT_LIST_HEAD(&dev->namespaces);
1986         dev->pci_dev = pdev;
1987         pci_set_drvdata(pdev, dev);
1988
1989         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)))
1990                 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1991         else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))
1992                 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1993         else
1994                 goto disable;
1995
1996         result = nvme_set_instance(dev);
1997         if (result)
1998                 goto disable;
1999
2000         dev->entry[0].vector = pdev->irq;
2001
2002         result = nvme_setup_prp_pools(dev);
2003         if (result)
2004                 goto disable_msix;
2005
2006         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2007         if (!dev->bar) {
2008                 result = -ENOMEM;
2009                 goto disable_msix;
2010         }
2011
2012         result = nvme_configure_admin_queue(dev);
2013         if (result)
2014                 goto unmap;
2015         dev->queue_count++;
2016
2017         spin_lock(&dev_list_lock);
2018         list_add(&dev->node, &dev_list);
2019         spin_unlock(&dev_list_lock);
2020
2021         result = nvme_dev_add(dev);
2022         if (result)
2023                 goto delete;
2024
2025         scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2026         dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2027         dev->miscdev.parent = &pdev->dev;
2028         dev->miscdev.name = dev->name;
2029         dev->miscdev.fops = &nvme_dev_fops;
2030         result = misc_register(&dev->miscdev);
2031         if (result)
2032                 goto remove;
2033
2034         kref_init(&dev->kref);
2035         return 0;
2036
2037  remove:
2038         nvme_dev_remove(dev);
2039  delete:
2040         spin_lock(&dev_list_lock);
2041         list_del(&dev->node);
2042         spin_unlock(&dev_list_lock);
2043
2044         nvme_free_queues(dev);
2045  unmap:
2046         iounmap(dev->bar);
2047  disable_msix:
2048         if (dev->pci_dev->msi_enabled)
2049                 pci_disable_msi(dev->pci_dev);
2050         else if (dev->pci_dev->msix_enabled)
2051                 pci_disable_msix(dev->pci_dev);
2052         nvme_release_instance(dev);
2053         nvme_release_prp_pools(dev);
2054  disable:
2055         pci_disable_device(pdev);
2056         pci_release_regions(pdev);
2057  free:
2058         kfree(dev->queues);
2059         kfree(dev->entry);
2060         kfree(dev);
2061         return result;
2062 }
2063
2064 static void nvme_remove(struct pci_dev *pdev)
2065 {
2066         struct nvme_dev *dev = pci_get_drvdata(pdev);
2067         misc_deregister(&dev->miscdev);
2068         kref_put(&dev->kref, nvme_free_dev);
2069 }
2070
2071 /* These functions are yet to be implemented */
2072 #define nvme_error_detected NULL
2073 #define nvme_dump_registers NULL
2074 #define nvme_link_reset NULL
2075 #define nvme_slot_reset NULL
2076 #define nvme_error_resume NULL
2077 #define nvme_suspend NULL
2078 #define nvme_resume NULL
2079
2080 static const struct pci_error_handlers nvme_err_handler = {
2081         .error_detected = nvme_error_detected,
2082         .mmio_enabled   = nvme_dump_registers,
2083         .link_reset     = nvme_link_reset,
2084         .slot_reset     = nvme_slot_reset,
2085         .resume         = nvme_error_resume,
2086 };
2087
2088 /* Move to pci_ids.h later */
2089 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2090
2091 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
2092         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2093         { 0, }
2094 };
2095 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2096
2097 static struct pci_driver nvme_driver = {
2098         .name           = "nvme",
2099         .id_table       = nvme_id_table,
2100         .probe          = nvme_probe,
2101         .remove         = nvme_remove,
2102         .suspend        = nvme_suspend,
2103         .resume         = nvme_resume,
2104         .err_handler    = &nvme_err_handler,
2105 };
2106
2107 static int __init nvme_init(void)
2108 {
2109         int result;
2110
2111         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2112         if (IS_ERR(nvme_thread))
2113                 return PTR_ERR(nvme_thread);
2114
2115         result = register_blkdev(nvme_major, "nvme");
2116         if (result < 0)
2117                 goto kill_kthread;
2118         else if (result > 0)
2119                 nvme_major = result;
2120
2121         result = pci_register_driver(&nvme_driver);
2122         if (result)
2123                 goto unregister_blkdev;
2124         return 0;
2125
2126  unregister_blkdev:
2127         unregister_blkdev(nvme_major, "nvme");
2128  kill_kthread:
2129         kthread_stop(nvme_thread);
2130         return result;
2131 }
2132
2133 static void __exit nvme_exit(void)
2134 {
2135         pci_unregister_driver(&nvme_driver);
2136         unregister_blkdev(nvme_major, "nvme");
2137         kthread_stop(nvme_thread);
2138 }
2139
2140 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2141 MODULE_LICENSE("GPL");
2142 MODULE_VERSION("0.8");
2143 module_init(nvme_init);
2144 module_exit(nvme_exit);