]> Pileus Git - ~andy/linux/blob - drivers/block/nvme-core.c
NVMe: Only clear the enable bit when disabling controller
[~andy/linux] / drivers / block / nvme-core.c
1 /*
2  * NVM Express device driver
3  * Copyright (c) 2011, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  */
18
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/fs.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <scsi/sg.h>
43 #include <asm-generic/io-64-nonatomic-lo-hi.h>
44
45 #define NVME_Q_DEPTH 1024
46 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
47 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
48 #define NVME_MINORS 64
49 #define ADMIN_TIMEOUT   (60 * HZ)
50
51 static int nvme_major;
52 module_param(nvme_major, int, 0);
53
54 static int use_threaded_interrupts;
55 module_param(use_threaded_interrupts, int, 0);
56
57 static DEFINE_SPINLOCK(dev_list_lock);
58 static LIST_HEAD(dev_list);
59 static struct task_struct *nvme_thread;
60
61 /*
62  * An NVM Express queue.  Each device has at least two (one for admin
63  * commands and one for I/O commands).
64  */
65 struct nvme_queue {
66         struct device *q_dmadev;
67         struct nvme_dev *dev;
68         spinlock_t q_lock;
69         struct nvme_command *sq_cmds;
70         volatile struct nvme_completion *cqes;
71         dma_addr_t sq_dma_addr;
72         dma_addr_t cq_dma_addr;
73         wait_queue_head_t sq_full;
74         wait_queue_t sq_cong_wait;
75         struct bio_list sq_cong;
76         u32 __iomem *q_db;
77         u16 q_depth;
78         u16 cq_vector;
79         u16 sq_head;
80         u16 sq_tail;
81         u16 cq_head;
82         u16 cq_phase;
83         unsigned long cmdid_data[];
84 };
85
86 /*
87  * Check we didin't inadvertently grow the command struct
88  */
89 static inline void _nvme_check_size(void)
90 {
91         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
92         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
93         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
94         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
95         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
96         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
97         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
98         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
99         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
100         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
101         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
102 }
103
104 typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
105                                                 struct nvme_completion *);
106
107 struct nvme_cmd_info {
108         nvme_completion_fn fn;
109         void *ctx;
110         unsigned long timeout;
111 };
112
113 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
114 {
115         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
116 }
117
118 /**
119  * alloc_cmdid() - Allocate a Command ID
120  * @nvmeq: The queue that will be used for this command
121  * @ctx: A pointer that will be passed to the handler
122  * @handler: The function to call on completion
123  *
124  * Allocate a Command ID for a queue.  The data passed in will
125  * be passed to the completion handler.  This is implemented by using
126  * the bottom two bits of the ctx pointer to store the handler ID.
127  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
128  * We can change this if it becomes a problem.
129  *
130  * May be called with local interrupts disabled and the q_lock held,
131  * or with interrupts enabled and no locks held.
132  */
133 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
134                                 nvme_completion_fn handler, unsigned timeout)
135 {
136         int depth = nvmeq->q_depth - 1;
137         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
138         int cmdid;
139
140         do {
141                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
142                 if (cmdid >= depth)
143                         return -EBUSY;
144         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
145
146         info[cmdid].fn = handler;
147         info[cmdid].ctx = ctx;
148         info[cmdid].timeout = jiffies + timeout;
149         return cmdid;
150 }
151
152 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
153                                 nvme_completion_fn handler, unsigned timeout)
154 {
155         int cmdid;
156         wait_event_killable(nvmeq->sq_full,
157                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
158         return (cmdid < 0) ? -EINTR : cmdid;
159 }
160
161 /* Special values must be less than 0x1000 */
162 #define CMD_CTX_BASE            ((void *)POISON_POINTER_DELTA)
163 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
164 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
165 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
166 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
167
168 static void special_completion(struct nvme_dev *dev, void *ctx,
169                                                 struct nvme_completion *cqe)
170 {
171         if (ctx == CMD_CTX_CANCELLED)
172                 return;
173         if (ctx == CMD_CTX_FLUSH)
174                 return;
175         if (ctx == CMD_CTX_COMPLETED) {
176                 dev_warn(&dev->pci_dev->dev,
177                                 "completed id %d twice on queue %d\n",
178                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
179                 return;
180         }
181         if (ctx == CMD_CTX_INVALID) {
182                 dev_warn(&dev->pci_dev->dev,
183                                 "invalid id %d completed on queue %d\n",
184                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
185                 return;
186         }
187
188         dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
189 }
190
191 /*
192  * Called with local interrupts disabled and the q_lock held.  May not sleep.
193  */
194 static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
195                                                 nvme_completion_fn *fn)
196 {
197         void *ctx;
198         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
199
200         if (cmdid >= nvmeq->q_depth) {
201                 *fn = special_completion;
202                 return CMD_CTX_INVALID;
203         }
204         if (fn)
205                 *fn = info[cmdid].fn;
206         ctx = info[cmdid].ctx;
207         info[cmdid].fn = special_completion;
208         info[cmdid].ctx = CMD_CTX_COMPLETED;
209         clear_bit(cmdid, nvmeq->cmdid_data);
210         wake_up(&nvmeq->sq_full);
211         return ctx;
212 }
213
214 static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
215                                                 nvme_completion_fn *fn)
216 {
217         void *ctx;
218         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
219         if (fn)
220                 *fn = info[cmdid].fn;
221         ctx = info[cmdid].ctx;
222         info[cmdid].fn = special_completion;
223         info[cmdid].ctx = CMD_CTX_CANCELLED;
224         return ctx;
225 }
226
227 struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
228 {
229         return dev->queues[get_cpu() + 1];
230 }
231
232 void put_nvmeq(struct nvme_queue *nvmeq)
233 {
234         put_cpu();
235 }
236
237 /**
238  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
239  * @nvmeq: The queue to use
240  * @cmd: The command to send
241  *
242  * Safe to use from interrupt context
243  */
244 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
245 {
246         unsigned long flags;
247         u16 tail;
248         spin_lock_irqsave(&nvmeq->q_lock, flags);
249         tail = nvmeq->sq_tail;
250         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
251         if (++tail == nvmeq->q_depth)
252                 tail = 0;
253         writel(tail, nvmeq->q_db);
254         nvmeq->sq_tail = tail;
255         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
256
257         return 0;
258 }
259
260 static __le64 **iod_list(struct nvme_iod *iod)
261 {
262         return ((void *)iod) + iod->offset;
263 }
264
265 /*
266  * Will slightly overestimate the number of pages needed.  This is OK
267  * as it only leads to a small amount of wasted memory for the lifetime of
268  * the I/O.
269  */
270 static int nvme_npages(unsigned size)
271 {
272         unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
273         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
274 }
275
276 static struct nvme_iod *
277 nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
278 {
279         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
280                                 sizeof(__le64 *) * nvme_npages(nbytes) +
281                                 sizeof(struct scatterlist) * nseg, gfp);
282
283         if (iod) {
284                 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
285                 iod->npages = -1;
286                 iod->length = nbytes;
287                 iod->nents = 0;
288         }
289
290         return iod;
291 }
292
293 void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
294 {
295         const int last_prp = PAGE_SIZE / 8 - 1;
296         int i;
297         __le64 **list = iod_list(iod);
298         dma_addr_t prp_dma = iod->first_dma;
299
300         if (iod->npages == 0)
301                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
302         for (i = 0; i < iod->npages; i++) {
303                 __le64 *prp_list = list[i];
304                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
305                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
306                 prp_dma = next_prp_dma;
307         }
308         kfree(iod);
309 }
310
311 static void bio_completion(struct nvme_dev *dev, void *ctx,
312                                                 struct nvme_completion *cqe)
313 {
314         struct nvme_iod *iod = ctx;
315         struct bio *bio = iod->private;
316         u16 status = le16_to_cpup(&cqe->status) >> 1;
317
318         if (iod->nents)
319                 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
320                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
321         nvme_free_iod(dev, iod);
322         if (status)
323                 bio_endio(bio, -EIO);
324         else
325                 bio_endio(bio, 0);
326 }
327
328 /* length is in bytes.  gfp flags indicates whether we may sleep. */
329 int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd,
330                         struct nvme_iod *iod, int total_len, gfp_t gfp)
331 {
332         struct dma_pool *pool;
333         int length = total_len;
334         struct scatterlist *sg = iod->sg;
335         int dma_len = sg_dma_len(sg);
336         u64 dma_addr = sg_dma_address(sg);
337         int offset = offset_in_page(dma_addr);
338         __le64 *prp_list;
339         __le64 **list = iod_list(iod);
340         dma_addr_t prp_dma;
341         int nprps, i;
342
343         cmd->prp1 = cpu_to_le64(dma_addr);
344         length -= (PAGE_SIZE - offset);
345         if (length <= 0)
346                 return total_len;
347
348         dma_len -= (PAGE_SIZE - offset);
349         if (dma_len) {
350                 dma_addr += (PAGE_SIZE - offset);
351         } else {
352                 sg = sg_next(sg);
353                 dma_addr = sg_dma_address(sg);
354                 dma_len = sg_dma_len(sg);
355         }
356
357         if (length <= PAGE_SIZE) {
358                 cmd->prp2 = cpu_to_le64(dma_addr);
359                 return total_len;
360         }
361
362         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
363         if (nprps <= (256 / 8)) {
364                 pool = dev->prp_small_pool;
365                 iod->npages = 0;
366         } else {
367                 pool = dev->prp_page_pool;
368                 iod->npages = 1;
369         }
370
371         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
372         if (!prp_list) {
373                 cmd->prp2 = cpu_to_le64(dma_addr);
374                 iod->npages = -1;
375                 return (total_len - length) + PAGE_SIZE;
376         }
377         list[0] = prp_list;
378         iod->first_dma = prp_dma;
379         cmd->prp2 = cpu_to_le64(prp_dma);
380         i = 0;
381         for (;;) {
382                 if (i == PAGE_SIZE / 8) {
383                         __le64 *old_prp_list = prp_list;
384                         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
385                         if (!prp_list)
386                                 return total_len - length;
387                         list[iod->npages++] = prp_list;
388                         prp_list[0] = old_prp_list[i - 1];
389                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
390                         i = 1;
391                 }
392                 prp_list[i++] = cpu_to_le64(dma_addr);
393                 dma_len -= PAGE_SIZE;
394                 dma_addr += PAGE_SIZE;
395                 length -= PAGE_SIZE;
396                 if (length <= 0)
397                         break;
398                 if (dma_len > 0)
399                         continue;
400                 BUG_ON(dma_len < 0);
401                 sg = sg_next(sg);
402                 dma_addr = sg_dma_address(sg);
403                 dma_len = sg_dma_len(sg);
404         }
405
406         return total_len;
407 }
408
409 struct nvme_bio_pair {
410         struct bio b1, b2, *parent;
411         struct bio_vec *bv1, *bv2;
412         int err;
413         atomic_t cnt;
414 };
415
416 static void nvme_bio_pair_endio(struct bio *bio, int err)
417 {
418         struct nvme_bio_pair *bp = bio->bi_private;
419
420         if (err)
421                 bp->err = err;
422
423         if (atomic_dec_and_test(&bp->cnt)) {
424                 bio_endio(bp->parent, bp->err);
425                 if (bp->bv1)
426                         kfree(bp->bv1);
427                 if (bp->bv2)
428                         kfree(bp->bv2);
429                 kfree(bp);
430         }
431 }
432
433 static struct nvme_bio_pair *nvme_bio_split(struct bio *bio, int idx,
434                                                         int len, int offset)
435 {
436         struct nvme_bio_pair *bp;
437
438         BUG_ON(len > bio->bi_size);
439         BUG_ON(idx > bio->bi_vcnt);
440
441         bp = kmalloc(sizeof(*bp), GFP_ATOMIC);
442         if (!bp)
443                 return NULL;
444         bp->err = 0;
445
446         bp->b1 = *bio;
447         bp->b2 = *bio;
448
449         bp->b1.bi_size = len;
450         bp->b2.bi_size -= len;
451         bp->b1.bi_vcnt = idx;
452         bp->b2.bi_idx = idx;
453         bp->b2.bi_sector += len >> 9;
454
455         if (offset) {
456                 bp->bv1 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec),
457                                                                 GFP_ATOMIC);
458                 if (!bp->bv1)
459                         goto split_fail_1;
460
461                 bp->bv2 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec),
462                                                                 GFP_ATOMIC);
463                 if (!bp->bv2)
464                         goto split_fail_2;
465
466                 memcpy(bp->bv1, bio->bi_io_vec,
467                         bio->bi_max_vecs * sizeof(struct bio_vec));
468                 memcpy(bp->bv2, bio->bi_io_vec,
469                         bio->bi_max_vecs * sizeof(struct bio_vec));
470
471                 bp->b1.bi_io_vec = bp->bv1;
472                 bp->b2.bi_io_vec = bp->bv2;
473                 bp->b2.bi_io_vec[idx].bv_offset += offset;
474                 bp->b2.bi_io_vec[idx].bv_len -= offset;
475                 bp->b1.bi_io_vec[idx].bv_len = offset;
476                 bp->b1.bi_vcnt++;
477         } else
478                 bp->bv1 = bp->bv2 = NULL;
479
480         bp->b1.bi_private = bp;
481         bp->b2.bi_private = bp;
482
483         bp->b1.bi_end_io = nvme_bio_pair_endio;
484         bp->b2.bi_end_io = nvme_bio_pair_endio;
485
486         bp->parent = bio;
487         atomic_set(&bp->cnt, 2);
488
489         return bp;
490
491  split_fail_2:
492         kfree(bp->bv1);
493  split_fail_1:
494         kfree(bp);
495         return NULL;
496 }
497
498 static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
499                                                 int idx, int len, int offset)
500 {
501         struct nvme_bio_pair *bp = nvme_bio_split(bio, idx, len, offset);
502         if (!bp)
503                 return -ENOMEM;
504
505         if (bio_list_empty(&nvmeq->sq_cong))
506                 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
507         bio_list_add(&nvmeq->sq_cong, &bp->b1);
508         bio_list_add(&nvmeq->sq_cong, &bp->b2);
509
510         return 0;
511 }
512
513 /* NVMe scatterlists require no holes in the virtual address */
514 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
515                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
516
517 static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
518                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
519 {
520         struct bio_vec *bvec, *bvprv = NULL;
521         struct scatterlist *sg = NULL;
522         int i, length = 0, nsegs = 0, split_len = bio->bi_size;
523
524         if (nvmeq->dev->stripe_size)
525                 split_len = nvmeq->dev->stripe_size -
526                         ((bio->bi_sector << 9) & (nvmeq->dev->stripe_size - 1));
527
528         sg_init_table(iod->sg, psegs);
529         bio_for_each_segment(bvec, bio, i) {
530                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
531                         sg->length += bvec->bv_len;
532                 } else {
533                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
534                                 return nvme_split_and_submit(bio, nvmeq, i,
535                                                                 length, 0);
536
537                         sg = sg ? sg + 1 : iod->sg;
538                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
539                                                         bvec->bv_offset);
540                         nsegs++;
541                 }
542
543                 if (split_len - length < bvec->bv_len)
544                         return nvme_split_and_submit(bio, nvmeq, i, split_len,
545                                                         split_len - length);
546                 length += bvec->bv_len;
547                 bvprv = bvec;
548         }
549         iod->nents = nsegs;
550         sg_mark_end(sg);
551         if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
552                 return -ENOMEM;
553
554         BUG_ON(length != bio->bi_size);
555         return length;
556 }
557
558 /*
559  * We reuse the small pool to allocate the 16-byte range here as it is not
560  * worth having a special pool for these or additional cases to handle freeing
561  * the iod.
562  */
563 static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
564                 struct bio *bio, struct nvme_iod *iod, int cmdid)
565 {
566         struct nvme_dsm_range *range;
567         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
568
569         range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
570                                                         &iod->first_dma);
571         if (!range)
572                 return -ENOMEM;
573
574         iod_list(iod)[0] = (__le64 *)range;
575         iod->npages = 0;
576
577         range->cattr = cpu_to_le32(0);
578         range->nlb = cpu_to_le32(bio->bi_size >> ns->lba_shift);
579         range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector));
580
581         memset(cmnd, 0, sizeof(*cmnd));
582         cmnd->dsm.opcode = nvme_cmd_dsm;
583         cmnd->dsm.command_id = cmdid;
584         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
585         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
586         cmnd->dsm.nr = 0;
587         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
588
589         if (++nvmeq->sq_tail == nvmeq->q_depth)
590                 nvmeq->sq_tail = 0;
591         writel(nvmeq->sq_tail, nvmeq->q_db);
592
593         return 0;
594 }
595
596 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
597                                                                 int cmdid)
598 {
599         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
600
601         memset(cmnd, 0, sizeof(*cmnd));
602         cmnd->common.opcode = nvme_cmd_flush;
603         cmnd->common.command_id = cmdid;
604         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
605
606         if (++nvmeq->sq_tail == nvmeq->q_depth)
607                 nvmeq->sq_tail = 0;
608         writel(nvmeq->sq_tail, nvmeq->q_db);
609
610         return 0;
611 }
612
613 int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
614 {
615         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
616                                         special_completion, NVME_IO_TIMEOUT);
617         if (unlikely(cmdid < 0))
618                 return cmdid;
619
620         return nvme_submit_flush(nvmeq, ns, cmdid);
621 }
622
623 /*
624  * Called with local interrupts disabled and the q_lock held.  May not sleep.
625  */
626 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
627                                                                 struct bio *bio)
628 {
629         struct nvme_command *cmnd;
630         struct nvme_iod *iod;
631         enum dma_data_direction dma_dir;
632         int cmdid, length, result = -ENOMEM;
633         u16 control;
634         u32 dsmgmt;
635         int psegs = bio_phys_segments(ns->queue, bio);
636
637         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
638                 result = nvme_submit_flush_data(nvmeq, ns);
639                 if (result)
640                         return result;
641         }
642
643         iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
644         if (!iod)
645                 goto nomem;
646         iod->private = bio;
647
648         result = -EBUSY;
649         cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
650         if (unlikely(cmdid < 0))
651                 goto free_iod;
652
653         if (bio->bi_rw & REQ_DISCARD) {
654                 result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
655                 if (result)
656                         goto free_cmdid;
657                 return result;
658         }
659         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
660                 return nvme_submit_flush(nvmeq, ns, cmdid);
661
662         control = 0;
663         if (bio->bi_rw & REQ_FUA)
664                 control |= NVME_RW_FUA;
665         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
666                 control |= NVME_RW_LR;
667
668         dsmgmt = 0;
669         if (bio->bi_rw & REQ_RAHEAD)
670                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
671
672         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
673
674         memset(cmnd, 0, sizeof(*cmnd));
675         if (bio_data_dir(bio)) {
676                 cmnd->rw.opcode = nvme_cmd_write;
677                 dma_dir = DMA_TO_DEVICE;
678         } else {
679                 cmnd->rw.opcode = nvme_cmd_read;
680                 dma_dir = DMA_FROM_DEVICE;
681         }
682
683         result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs);
684         if (result <= 0)
685                 goto free_cmdid;
686         length = result;
687
688         cmnd->rw.command_id = cmdid;
689         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
690         length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
691                                                                 GFP_ATOMIC);
692         cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector));
693         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
694         cmnd->rw.control = cpu_to_le16(control);
695         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
696
697         if (++nvmeq->sq_tail == nvmeq->q_depth)
698                 nvmeq->sq_tail = 0;
699         writel(nvmeq->sq_tail, nvmeq->q_db);
700
701         return 0;
702
703  free_cmdid:
704         free_cmdid(nvmeq, cmdid, NULL);
705  free_iod:
706         nvme_free_iod(nvmeq->dev, iod);
707  nomem:
708         return result;
709 }
710
711 static void nvme_make_request(struct request_queue *q, struct bio *bio)
712 {
713         struct nvme_ns *ns = q->queuedata;
714         struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
715         int result = -EBUSY;
716
717         spin_lock_irq(&nvmeq->q_lock);
718         if (bio_list_empty(&nvmeq->sq_cong))
719                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
720         if (unlikely(result)) {
721                 if (bio_list_empty(&nvmeq->sq_cong))
722                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
723                 bio_list_add(&nvmeq->sq_cong, bio);
724         }
725
726         spin_unlock_irq(&nvmeq->q_lock);
727         put_nvmeq(nvmeq);
728 }
729
730 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
731 {
732         u16 head, phase;
733
734         head = nvmeq->cq_head;
735         phase = nvmeq->cq_phase;
736
737         for (;;) {
738                 void *ctx;
739                 nvme_completion_fn fn;
740                 struct nvme_completion cqe = nvmeq->cqes[head];
741                 if ((le16_to_cpu(cqe.status) & 1) != phase)
742                         break;
743                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
744                 if (++head == nvmeq->q_depth) {
745                         head = 0;
746                         phase = !phase;
747                 }
748
749                 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
750                 fn(nvmeq->dev, ctx, &cqe);
751         }
752
753         /* If the controller ignores the cq head doorbell and continuously
754          * writes to the queue, it is theoretically possible to wrap around
755          * the queue twice and mistakenly return IRQ_NONE.  Linux only
756          * requires that 0.1% of your interrupts are handled, so this isn't
757          * a big problem.
758          */
759         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
760                 return IRQ_NONE;
761
762         writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
763         nvmeq->cq_head = head;
764         nvmeq->cq_phase = phase;
765
766         return IRQ_HANDLED;
767 }
768
769 static irqreturn_t nvme_irq(int irq, void *data)
770 {
771         irqreturn_t result;
772         struct nvme_queue *nvmeq = data;
773         spin_lock(&nvmeq->q_lock);
774         result = nvme_process_cq(nvmeq);
775         spin_unlock(&nvmeq->q_lock);
776         return result;
777 }
778
779 static irqreturn_t nvme_irq_check(int irq, void *data)
780 {
781         struct nvme_queue *nvmeq = data;
782         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
783         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
784                 return IRQ_NONE;
785         return IRQ_WAKE_THREAD;
786 }
787
788 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
789 {
790         spin_lock_irq(&nvmeq->q_lock);
791         cancel_cmdid(nvmeq, cmdid, NULL);
792         spin_unlock_irq(&nvmeq->q_lock);
793 }
794
795 struct sync_cmd_info {
796         struct task_struct *task;
797         u32 result;
798         int status;
799 };
800
801 static void sync_completion(struct nvme_dev *dev, void *ctx,
802                                                 struct nvme_completion *cqe)
803 {
804         struct sync_cmd_info *cmdinfo = ctx;
805         cmdinfo->result = le32_to_cpup(&cqe->result);
806         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
807         wake_up_process(cmdinfo->task);
808 }
809
810 /*
811  * Returns 0 on success.  If the result is negative, it's a Linux error code;
812  * if the result is positive, it's an NVM Express status code
813  */
814 int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
815                                                 u32 *result, unsigned timeout)
816 {
817         int cmdid;
818         struct sync_cmd_info cmdinfo;
819
820         cmdinfo.task = current;
821         cmdinfo.status = -EINTR;
822
823         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
824                                                                 timeout);
825         if (cmdid < 0)
826                 return cmdid;
827         cmd->common.command_id = cmdid;
828
829         set_current_state(TASK_KILLABLE);
830         nvme_submit_cmd(nvmeq, cmd);
831         schedule_timeout(timeout);
832
833         if (cmdinfo.status == -EINTR) {
834                 nvme_abort_command(nvmeq, cmdid);
835                 return -EINTR;
836         }
837
838         if (result)
839                 *result = cmdinfo.result;
840
841         return cmdinfo.status;
842 }
843
844 int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
845                                                                 u32 *result)
846 {
847         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
848 }
849
850 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
851 {
852         int status;
853         struct nvme_command c;
854
855         memset(&c, 0, sizeof(c));
856         c.delete_queue.opcode = opcode;
857         c.delete_queue.qid = cpu_to_le16(id);
858
859         status = nvme_submit_admin_cmd(dev, &c, NULL);
860         if (status)
861                 return -EIO;
862         return 0;
863 }
864
865 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
866                                                 struct nvme_queue *nvmeq)
867 {
868         int status;
869         struct nvme_command c;
870         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
871
872         memset(&c, 0, sizeof(c));
873         c.create_cq.opcode = nvme_admin_create_cq;
874         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
875         c.create_cq.cqid = cpu_to_le16(qid);
876         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
877         c.create_cq.cq_flags = cpu_to_le16(flags);
878         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
879
880         status = nvme_submit_admin_cmd(dev, &c, NULL);
881         if (status)
882                 return -EIO;
883         return 0;
884 }
885
886 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
887                                                 struct nvme_queue *nvmeq)
888 {
889         int status;
890         struct nvme_command c;
891         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
892
893         memset(&c, 0, sizeof(c));
894         c.create_sq.opcode = nvme_admin_create_sq;
895         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
896         c.create_sq.sqid = cpu_to_le16(qid);
897         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
898         c.create_sq.sq_flags = cpu_to_le16(flags);
899         c.create_sq.cqid = cpu_to_le16(qid);
900
901         status = nvme_submit_admin_cmd(dev, &c, NULL);
902         if (status)
903                 return -EIO;
904         return 0;
905 }
906
907 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
908 {
909         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
910 }
911
912 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
913 {
914         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
915 }
916
917 int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
918                                                         dma_addr_t dma_addr)
919 {
920         struct nvme_command c;
921
922         memset(&c, 0, sizeof(c));
923         c.identify.opcode = nvme_admin_identify;
924         c.identify.nsid = cpu_to_le32(nsid);
925         c.identify.prp1 = cpu_to_le64(dma_addr);
926         c.identify.cns = cpu_to_le32(cns);
927
928         return nvme_submit_admin_cmd(dev, &c, NULL);
929 }
930
931 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
932                                         dma_addr_t dma_addr, u32 *result)
933 {
934         struct nvme_command c;
935
936         memset(&c, 0, sizeof(c));
937         c.features.opcode = nvme_admin_get_features;
938         c.features.nsid = cpu_to_le32(nsid);
939         c.features.prp1 = cpu_to_le64(dma_addr);
940         c.features.fid = cpu_to_le32(fid);
941
942         return nvme_submit_admin_cmd(dev, &c, result);
943 }
944
945 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
946                                         dma_addr_t dma_addr, u32 *result)
947 {
948         struct nvme_command c;
949
950         memset(&c, 0, sizeof(c));
951         c.features.opcode = nvme_admin_set_features;
952         c.features.prp1 = cpu_to_le64(dma_addr);
953         c.features.fid = cpu_to_le32(fid);
954         c.features.dword11 = cpu_to_le32(dword11);
955
956         return nvme_submit_admin_cmd(dev, &c, result);
957 }
958
959 /**
960  * nvme_cancel_ios - Cancel outstanding I/Os
961  * @queue: The queue to cancel I/Os on
962  * @timeout: True to only cancel I/Os which have timed out
963  */
964 static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
965 {
966         int depth = nvmeq->q_depth - 1;
967         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
968         unsigned long now = jiffies;
969         int cmdid;
970
971         for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
972                 void *ctx;
973                 nvme_completion_fn fn;
974                 static struct nvme_completion cqe = {
975                         .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
976                 };
977
978                 if (timeout && !time_after(now, info[cmdid].timeout))
979                         continue;
980                 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid);
981                 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
982                 fn(nvmeq->dev, ctx, &cqe);
983         }
984 }
985
986 static void nvme_free_queue_mem(struct nvme_queue *nvmeq)
987 {
988         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
989                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
990         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
991                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
992         kfree(nvmeq);
993 }
994
995 static void nvme_free_queue(struct nvme_dev *dev, int qid)
996 {
997         struct nvme_queue *nvmeq = dev->queues[qid];
998         int vector = dev->entry[nvmeq->cq_vector].vector;
999
1000         spin_lock_irq(&nvmeq->q_lock);
1001         nvme_cancel_ios(nvmeq, false);
1002         while (bio_list_peek(&nvmeq->sq_cong)) {
1003                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1004                 bio_endio(bio, -EIO);
1005         }
1006         spin_unlock_irq(&nvmeq->q_lock);
1007
1008         irq_set_affinity_hint(vector, NULL);
1009         free_irq(vector, nvmeq);
1010
1011         /* Don't tell the adapter to delete the admin queue */
1012         if (qid) {
1013                 adapter_delete_sq(dev, qid);
1014                 adapter_delete_cq(dev, qid);
1015         }
1016
1017         nvme_free_queue_mem(nvmeq);
1018 }
1019
1020 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1021                                                         int depth, int vector)
1022 {
1023         struct device *dmadev = &dev->pci_dev->dev;
1024         unsigned extra = DIV_ROUND_UP(depth, 8) + (depth *
1025                                                 sizeof(struct nvme_cmd_info));
1026         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1027         if (!nvmeq)
1028                 return NULL;
1029
1030         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1031                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
1032         if (!nvmeq->cqes)
1033                 goto free_nvmeq;
1034         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1035
1036         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1037                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1038         if (!nvmeq->sq_cmds)
1039                 goto free_cqdma;
1040
1041         nvmeq->q_dmadev = dmadev;
1042         nvmeq->dev = dev;
1043         spin_lock_init(&nvmeq->q_lock);
1044         nvmeq->cq_head = 0;
1045         nvmeq->cq_phase = 1;
1046         init_waitqueue_head(&nvmeq->sq_full);
1047         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
1048         bio_list_init(&nvmeq->sq_cong);
1049         nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
1050         nvmeq->q_depth = depth;
1051         nvmeq->cq_vector = vector;
1052
1053         return nvmeq;
1054
1055  free_cqdma:
1056         dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1057                                                         nvmeq->cq_dma_addr);
1058  free_nvmeq:
1059         kfree(nvmeq);
1060         return NULL;
1061 }
1062
1063 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1064                                                         const char *name)
1065 {
1066         if (use_threaded_interrupts)
1067                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1068                                         nvme_irq_check, nvme_irq,
1069                                         IRQF_DISABLED | IRQF_SHARED,
1070                                         name, nvmeq);
1071         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1072                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
1073 }
1074
1075 static struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, int qid,
1076                                             int cq_size, int vector)
1077 {
1078         int result;
1079         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
1080
1081         if (!nvmeq)
1082                 return ERR_PTR(-ENOMEM);
1083
1084         result = adapter_alloc_cq(dev, qid, nvmeq);
1085         if (result < 0)
1086                 goto free_nvmeq;
1087
1088         result = adapter_alloc_sq(dev, qid, nvmeq);
1089         if (result < 0)
1090                 goto release_cq;
1091
1092         result = queue_request_irq(dev, nvmeq, "nvme");
1093         if (result < 0)
1094                 goto release_sq;
1095
1096         return nvmeq;
1097
1098  release_sq:
1099         adapter_delete_sq(dev, qid);
1100  release_cq:
1101         adapter_delete_cq(dev, qid);
1102  free_nvmeq:
1103         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1104                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1105         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1106                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1107         kfree(nvmeq);
1108         return ERR_PTR(result);
1109 }
1110
1111 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1112 {
1113         unsigned long timeout;
1114         u32 bit = enabled ? NVME_CSTS_RDY : 0;
1115
1116         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1117
1118         while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1119                 msleep(100);
1120                 if (fatal_signal_pending(current))
1121                         return -EINTR;
1122                 if (time_after(jiffies, timeout)) {
1123                         dev_err(&dev->pci_dev->dev,
1124                                 "Device not ready; aborting initialisation\n");
1125                         return -ENODEV;
1126                 }
1127         }
1128
1129         return 0;
1130 }
1131
1132 /*
1133  * If the device has been passed off to us in an enabled state, just clear
1134  * the enabled bit.  The spec says we should set the 'shutdown notification
1135  * bits', but doing so may cause the device to complete commands to the
1136  * admin queue ... and we don't know what memory that might be pointing at!
1137  */
1138 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1139 {
1140         u32 cc = readl(&dev->bar->cc);
1141
1142         if (cc & NVME_CC_ENABLE)
1143                 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
1144         return nvme_wait_ready(dev, cap, false);
1145 }
1146
1147 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1148 {
1149         return nvme_wait_ready(dev, cap, true);
1150 }
1151
1152 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1153 {
1154         int result;
1155         u32 aqa;
1156         u64 cap = readq(&dev->bar->cap);
1157         struct nvme_queue *nvmeq;
1158
1159         dev->dbs = ((void __iomem *)dev->bar) + 4096;
1160         dev->db_stride = NVME_CAP_STRIDE(cap);
1161
1162         result = nvme_disable_ctrl(dev, cap);
1163         if (result < 0)
1164                 return result;
1165
1166         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1167         if (!nvmeq)
1168                 return -ENOMEM;
1169
1170         aqa = nvmeq->q_depth - 1;
1171         aqa |= aqa << 16;
1172
1173         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1174         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1175         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1176         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1177
1178         writel(aqa, &dev->bar->aqa);
1179         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1180         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1181         writel(dev->ctrl_config, &dev->bar->cc);
1182
1183         result = nvme_enable_ctrl(dev, cap);
1184         if (result)
1185                 goto free_q;
1186
1187         result = queue_request_irq(dev, nvmeq, "nvme admin");
1188         if (result)
1189                 goto free_q;
1190
1191         dev->queues[0] = nvmeq;
1192         return result;
1193
1194  free_q:
1195         nvme_free_queue_mem(nvmeq);
1196         return result;
1197 }
1198
1199 struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1200                                 unsigned long addr, unsigned length)
1201 {
1202         int i, err, count, nents, offset;
1203         struct scatterlist *sg;
1204         struct page **pages;
1205         struct nvme_iod *iod;
1206
1207         if (addr & 3)
1208                 return ERR_PTR(-EINVAL);
1209         if (!length)
1210                 return ERR_PTR(-EINVAL);
1211
1212         offset = offset_in_page(addr);
1213         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1214         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1215         if (!pages)
1216                 return ERR_PTR(-ENOMEM);
1217
1218         err = get_user_pages_fast(addr, count, 1, pages);
1219         if (err < count) {
1220                 count = err;
1221                 err = -EFAULT;
1222                 goto put_pages;
1223         }
1224
1225         iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1226         sg = iod->sg;
1227         sg_init_table(sg, count);
1228         for (i = 0; i < count; i++) {
1229                 sg_set_page(&sg[i], pages[i],
1230                                 min_t(int, length, PAGE_SIZE - offset), offset);
1231                 length -= (PAGE_SIZE - offset);
1232                 offset = 0;
1233         }
1234         sg_mark_end(&sg[i - 1]);
1235         iod->nents = count;
1236
1237         err = -ENOMEM;
1238         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1239                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1240         if (!nents)
1241                 goto free_iod;
1242
1243         kfree(pages);
1244         return iod;
1245
1246  free_iod:
1247         kfree(iod);
1248  put_pages:
1249         for (i = 0; i < count; i++)
1250                 put_page(pages[i]);
1251         kfree(pages);
1252         return ERR_PTR(err);
1253 }
1254
1255 void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1256                         struct nvme_iod *iod)
1257 {
1258         int i;
1259
1260         dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1261                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1262
1263         for (i = 0; i < iod->nents; i++)
1264                 put_page(sg_page(&iod->sg[i]));
1265 }
1266
1267 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1268 {
1269         struct nvme_dev *dev = ns->dev;
1270         struct nvme_queue *nvmeq;
1271         struct nvme_user_io io;
1272         struct nvme_command c;
1273         unsigned length, meta_len;
1274         int status, i;
1275         struct nvme_iod *iod, *meta_iod = NULL;
1276         dma_addr_t meta_dma_addr;
1277         void *meta, *uninitialized_var(meta_mem);
1278
1279         if (copy_from_user(&io, uio, sizeof(io)))
1280                 return -EFAULT;
1281         length = (io.nblocks + 1) << ns->lba_shift;
1282         meta_len = (io.nblocks + 1) * ns->ms;
1283
1284         if (meta_len && ((io.metadata & 3) || !io.metadata))
1285                 return -EINVAL;
1286
1287         switch (io.opcode) {
1288         case nvme_cmd_write:
1289         case nvme_cmd_read:
1290         case nvme_cmd_compare:
1291                 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1292                 break;
1293         default:
1294                 return -EINVAL;
1295         }
1296
1297         if (IS_ERR(iod))
1298                 return PTR_ERR(iod);
1299
1300         memset(&c, 0, sizeof(c));
1301         c.rw.opcode = io.opcode;
1302         c.rw.flags = io.flags;
1303         c.rw.nsid = cpu_to_le32(ns->ns_id);
1304         c.rw.slba = cpu_to_le64(io.slba);
1305         c.rw.length = cpu_to_le16(io.nblocks);
1306         c.rw.control = cpu_to_le16(io.control);
1307         c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1308         c.rw.reftag = cpu_to_le32(io.reftag);
1309         c.rw.apptag = cpu_to_le16(io.apptag);
1310         c.rw.appmask = cpu_to_le16(io.appmask);
1311
1312         if (meta_len) {
1313                 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata, meta_len);
1314                 if (IS_ERR(meta_iod)) {
1315                         status = PTR_ERR(meta_iod);
1316                         meta_iod = NULL;
1317                         goto unmap;
1318                 }
1319
1320                 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1321                                                 &meta_dma_addr, GFP_KERNEL);
1322                 if (!meta_mem) {
1323                         status = -ENOMEM;
1324                         goto unmap;
1325                 }
1326
1327                 if (io.opcode & 1) {
1328                         int meta_offset = 0;
1329
1330                         for (i = 0; i < meta_iod->nents; i++) {
1331                                 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1332                                                 meta_iod->sg[i].offset;
1333                                 memcpy(meta_mem + meta_offset, meta,
1334                                                 meta_iod->sg[i].length);
1335                                 kunmap_atomic(meta);
1336                                 meta_offset += meta_iod->sg[i].length;
1337                         }
1338                 }
1339
1340                 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1341         }
1342
1343         length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
1344
1345         nvmeq = get_nvmeq(dev);
1346         /*
1347          * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1348          * disabled.  We may be preempted at any point, and be rescheduled
1349          * to a different CPU.  That will cause cacheline bouncing, but no
1350          * additional races since q_lock already protects against other CPUs.
1351          */
1352         put_nvmeq(nvmeq);
1353         if (length != (io.nblocks + 1) << ns->lba_shift)
1354                 status = -ENOMEM;
1355         else
1356                 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
1357
1358         if (meta_len) {
1359                 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1360                         int meta_offset = 0;
1361
1362                         for (i = 0; i < meta_iod->nents; i++) {
1363                                 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1364                                                 meta_iod->sg[i].offset;
1365                                 memcpy(meta, meta_mem + meta_offset,
1366                                                 meta_iod->sg[i].length);
1367                                 kunmap_atomic(meta);
1368                                 meta_offset += meta_iod->sg[i].length;
1369                         }
1370                 }
1371
1372                 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1373                                                                 meta_dma_addr);
1374         }
1375
1376  unmap:
1377         nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1378         nvme_free_iod(dev, iod);
1379
1380         if (meta_iod) {
1381                 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1382                 nvme_free_iod(dev, meta_iod);
1383         }
1384
1385         return status;
1386 }
1387
1388 static int nvme_user_admin_cmd(struct nvme_dev *dev,
1389                                         struct nvme_admin_cmd __user *ucmd)
1390 {
1391         struct nvme_admin_cmd cmd;
1392         struct nvme_command c;
1393         int status, length;
1394         struct nvme_iod *uninitialized_var(iod);
1395
1396         if (!capable(CAP_SYS_ADMIN))
1397                 return -EACCES;
1398         if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1399                 return -EFAULT;
1400
1401         memset(&c, 0, sizeof(c));
1402         c.common.opcode = cmd.opcode;
1403         c.common.flags = cmd.flags;
1404         c.common.nsid = cpu_to_le32(cmd.nsid);
1405         c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1406         c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1407         c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1408         c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1409         c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1410         c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1411         c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1412         c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1413
1414         length = cmd.data_len;
1415         if (cmd.data_len) {
1416                 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1417                                                                 length);
1418                 if (IS_ERR(iod))
1419                         return PTR_ERR(iod);
1420                 length = nvme_setup_prps(dev, &c.common, iod, length,
1421                                                                 GFP_KERNEL);
1422         }
1423
1424         if (length != cmd.data_len)
1425                 status = -ENOMEM;
1426         else
1427                 status = nvme_submit_admin_cmd(dev, &c, &cmd.result);
1428
1429         if (cmd.data_len) {
1430                 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1431                 nvme_free_iod(dev, iod);
1432         }
1433
1434         if (!status && copy_to_user(&ucmd->result, &cmd.result,
1435                                                         sizeof(cmd.result)))
1436                 status = -EFAULT;
1437
1438         return status;
1439 }
1440
1441 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1442                                                         unsigned long arg)
1443 {
1444         struct nvme_ns *ns = bdev->bd_disk->private_data;
1445
1446         switch (cmd) {
1447         case NVME_IOCTL_ID:
1448                 return ns->ns_id;
1449         case NVME_IOCTL_ADMIN_CMD:
1450                 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
1451         case NVME_IOCTL_SUBMIT_IO:
1452                 return nvme_submit_io(ns, (void __user *)arg);
1453         case SG_GET_VERSION_NUM:
1454                 return nvme_sg_get_version_num((void __user *)arg);
1455         case SG_IO:
1456                 return nvme_sg_io(ns, (void __user *)arg);
1457         default:
1458                 return -ENOTTY;
1459         }
1460 }
1461
1462 static const struct block_device_operations nvme_fops = {
1463         .owner          = THIS_MODULE,
1464         .ioctl          = nvme_ioctl,
1465         .compat_ioctl   = nvme_ioctl,
1466 };
1467
1468 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1469 {
1470         while (bio_list_peek(&nvmeq->sq_cong)) {
1471                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1472                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1473
1474                 if (bio_list_empty(&nvmeq->sq_cong))
1475                         remove_wait_queue(&nvmeq->sq_full,
1476                                                         &nvmeq->sq_cong_wait);
1477                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1478                         if (bio_list_empty(&nvmeq->sq_cong))
1479                                 add_wait_queue(&nvmeq->sq_full,
1480                                                         &nvmeq->sq_cong_wait);
1481                         bio_list_add_head(&nvmeq->sq_cong, bio);
1482                         break;
1483                 }
1484         }
1485 }
1486
1487 static int nvme_kthread(void *data)
1488 {
1489         struct nvme_dev *dev;
1490
1491         while (!kthread_should_stop()) {
1492                 set_current_state(TASK_INTERRUPTIBLE);
1493                 spin_lock(&dev_list_lock);
1494                 list_for_each_entry(dev, &dev_list, node) {
1495                         int i;
1496                         for (i = 0; i < dev->queue_count; i++) {
1497                                 struct nvme_queue *nvmeq = dev->queues[i];
1498                                 if (!nvmeq)
1499                                         continue;
1500                                 spin_lock_irq(&nvmeq->q_lock);
1501                                 if (nvme_process_cq(nvmeq))
1502                                         printk("process_cq did something\n");
1503                                 nvme_cancel_ios(nvmeq, true);
1504                                 nvme_resubmit_bios(nvmeq);
1505                                 spin_unlock_irq(&nvmeq->q_lock);
1506                         }
1507                 }
1508                 spin_unlock(&dev_list_lock);
1509                 schedule_timeout(round_jiffies_relative(HZ));
1510         }
1511         return 0;
1512 }
1513
1514 static DEFINE_IDA(nvme_index_ida);
1515
1516 static int nvme_get_ns_idx(void)
1517 {
1518         int index, error;
1519
1520         do {
1521                 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1522                         return -1;
1523
1524                 spin_lock(&dev_list_lock);
1525                 error = ida_get_new(&nvme_index_ida, &index);
1526                 spin_unlock(&dev_list_lock);
1527         } while (error == -EAGAIN);
1528
1529         if (error)
1530                 index = -1;
1531         return index;
1532 }
1533
1534 static void nvme_put_ns_idx(int index)
1535 {
1536         spin_lock(&dev_list_lock);
1537         ida_remove(&nvme_index_ida, index);
1538         spin_unlock(&dev_list_lock);
1539 }
1540
1541 static void nvme_config_discard(struct nvme_ns *ns)
1542 {
1543         u32 logical_block_size = queue_logical_block_size(ns->queue);
1544         ns->queue->limits.discard_zeroes_data = 0;
1545         ns->queue->limits.discard_alignment = logical_block_size;
1546         ns->queue->limits.discard_granularity = logical_block_size;
1547         ns->queue->limits.max_discard_sectors = 0xffffffff;
1548         queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1549 }
1550
1551 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
1552                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1553 {
1554         struct nvme_ns *ns;
1555         struct gendisk *disk;
1556         int lbaf;
1557
1558         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1559                 return NULL;
1560
1561         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1562         if (!ns)
1563                 return NULL;
1564         ns->queue = blk_alloc_queue(GFP_KERNEL);
1565         if (!ns->queue)
1566                 goto out_free_ns;
1567         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1568         queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1569         queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1570         blk_queue_make_request(ns->queue, nvme_make_request);
1571         ns->dev = dev;
1572         ns->queue->queuedata = ns;
1573
1574         disk = alloc_disk(NVME_MINORS);
1575         if (!disk)
1576                 goto out_free_queue;
1577         ns->ns_id = nsid;
1578         ns->disk = disk;
1579         lbaf = id->flbas & 0xf;
1580         ns->lba_shift = id->lbaf[lbaf].ds;
1581         ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
1582         blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1583         if (dev->max_hw_sectors)
1584                 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
1585
1586         disk->major = nvme_major;
1587         disk->minors = NVME_MINORS;
1588         disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1589         disk->fops = &nvme_fops;
1590         disk->private_data = ns;
1591         disk->queue = ns->queue;
1592         disk->driverfs_dev = &dev->pci_dev->dev;
1593         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1594         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1595
1596         if (dev->oncs & NVME_CTRL_ONCS_DSM)
1597                 nvme_config_discard(ns);
1598
1599         return ns;
1600
1601  out_free_queue:
1602         blk_cleanup_queue(ns->queue);
1603  out_free_ns:
1604         kfree(ns);
1605         return NULL;
1606 }
1607
1608 static void nvme_ns_free(struct nvme_ns *ns)
1609 {
1610         int index = ns->disk->first_minor / NVME_MINORS;
1611         put_disk(ns->disk);
1612         nvme_put_ns_idx(index);
1613         blk_cleanup_queue(ns->queue);
1614         kfree(ns);
1615 }
1616
1617 static int set_queue_count(struct nvme_dev *dev, int count)
1618 {
1619         int status;
1620         u32 result;
1621         u32 q_count = (count - 1) | ((count - 1) << 16);
1622
1623         status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1624                                                                 &result);
1625         if (status)
1626                 return -EIO;
1627         return min(result & 0xffff, result >> 16) + 1;
1628 }
1629
1630 static int nvme_setup_io_queues(struct nvme_dev *dev)
1631 {
1632         int result, cpu, i, nr_io_queues, db_bar_size, q_depth;
1633
1634         nr_io_queues = num_online_cpus();
1635         result = set_queue_count(dev, nr_io_queues);
1636         if (result < 0)
1637                 return result;
1638         if (result < nr_io_queues)
1639                 nr_io_queues = result;
1640
1641         /* Deregister the admin queue's interrupt */
1642         free_irq(dev->entry[0].vector, dev->queues[0]);
1643
1644         db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1645         if (db_bar_size > 8192) {
1646                 iounmap(dev->bar);
1647                 dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
1648                                                                 db_bar_size);
1649                 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1650                 dev->queues[0]->q_db = dev->dbs;
1651         }
1652
1653         for (i = 0; i < nr_io_queues; i++)
1654                 dev->entry[i].entry = i;
1655         for (;;) {
1656                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1657                                                                 nr_io_queues);
1658                 if (result == 0) {
1659                         break;
1660                 } else if (result > 0) {
1661                         nr_io_queues = result;
1662                         continue;
1663                 } else {
1664                         nr_io_queues = 1;
1665                         break;
1666                 }
1667         }
1668
1669         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1670         /* XXX: handle failure here */
1671
1672         cpu = cpumask_first(cpu_online_mask);
1673         for (i = 0; i < nr_io_queues; i++) {
1674                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1675                 cpu = cpumask_next(cpu, cpu_online_mask);
1676         }
1677
1678         q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1,
1679                                                                 NVME_Q_DEPTH);
1680         for (i = 0; i < nr_io_queues; i++) {
1681                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1, q_depth, i);
1682                 if (IS_ERR(dev->queues[i + 1]))
1683                         return PTR_ERR(dev->queues[i + 1]);
1684                 dev->queue_count++;
1685         }
1686
1687         for (; i < num_possible_cpus(); i++) {
1688                 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1689                 dev->queues[i + 1] = dev->queues[target + 1];
1690         }
1691
1692         return 0;
1693 }
1694
1695 static void nvme_free_queues(struct nvme_dev *dev)
1696 {
1697         int i;
1698
1699         for (i = dev->queue_count - 1; i >= 0; i--)
1700                 nvme_free_queue(dev, i);
1701 }
1702
1703 /*
1704  * Return: error value if an error occurred setting up the queues or calling
1705  * Identify Device.  0 if these succeeded, even if adding some of the
1706  * namespaces failed.  At the moment, these failures are silent.  TBD which
1707  * failures should be reported.
1708  */
1709 static int nvme_dev_add(struct nvme_dev *dev)
1710 {
1711         int res, nn, i;
1712         struct nvme_ns *ns;
1713         struct nvme_id_ctrl *ctrl;
1714         struct nvme_id_ns *id_ns;
1715         void *mem;
1716         dma_addr_t dma_addr;
1717         int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
1718
1719         res = nvme_setup_io_queues(dev);
1720         if (res)
1721                 return res;
1722
1723         mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1724                                                                 GFP_KERNEL);
1725         if (!mem)
1726                 return -ENOMEM;
1727
1728         res = nvme_identify(dev, 0, 1, dma_addr);
1729         if (res) {
1730                 res = -EIO;
1731                 goto out;
1732         }
1733
1734         ctrl = mem;
1735         nn = le32_to_cpup(&ctrl->nn);
1736         dev->oncs = le16_to_cpup(&ctrl->oncs);
1737         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1738         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1739         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1740         if (ctrl->mdts)
1741                 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
1742         if ((dev->pci_dev->vendor == PCI_VENDOR_ID_INTEL) &&
1743                         (dev->pci_dev->device == 0x0953) && ctrl->vs[3])
1744                 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
1745
1746         id_ns = mem;
1747         for (i = 1; i <= nn; i++) {
1748                 res = nvme_identify(dev, i, 0, dma_addr);
1749                 if (res)
1750                         continue;
1751
1752                 if (id_ns->ncap == 0)
1753                         continue;
1754
1755                 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
1756                                                         dma_addr + 4096, NULL);
1757                 if (res)
1758                         memset(mem + 4096, 0, 4096);
1759
1760                 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
1761                 if (ns)
1762                         list_add_tail(&ns->list, &dev->namespaces);
1763         }
1764         list_for_each_entry(ns, &dev->namespaces, list)
1765                 add_disk(ns->disk);
1766         res = 0;
1767
1768  out:
1769         dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1770         return res;
1771 }
1772
1773 static int nvme_dev_remove(struct nvme_dev *dev)
1774 {
1775         struct nvme_ns *ns, *next;
1776
1777         spin_lock(&dev_list_lock);
1778         list_del(&dev->node);
1779         spin_unlock(&dev_list_lock);
1780
1781         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1782                 list_del(&ns->list);
1783                 del_gendisk(ns->disk);
1784                 nvme_ns_free(ns);
1785         }
1786
1787         nvme_free_queues(dev);
1788
1789         return 0;
1790 }
1791
1792 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1793 {
1794         struct device *dmadev = &dev->pci_dev->dev;
1795         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1796                                                 PAGE_SIZE, PAGE_SIZE, 0);
1797         if (!dev->prp_page_pool)
1798                 return -ENOMEM;
1799
1800         /* Optimisation for I/Os between 4k and 128k */
1801         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1802                                                 256, 256, 0);
1803         if (!dev->prp_small_pool) {
1804                 dma_pool_destroy(dev->prp_page_pool);
1805                 return -ENOMEM;
1806         }
1807         return 0;
1808 }
1809
1810 static void nvme_release_prp_pools(struct nvme_dev *dev)
1811 {
1812         dma_pool_destroy(dev->prp_page_pool);
1813         dma_pool_destroy(dev->prp_small_pool);
1814 }
1815
1816 static DEFINE_IDA(nvme_instance_ida);
1817
1818 static int nvme_set_instance(struct nvme_dev *dev)
1819 {
1820         int instance, error;
1821
1822         do {
1823                 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
1824                         return -ENODEV;
1825
1826                 spin_lock(&dev_list_lock);
1827                 error = ida_get_new(&nvme_instance_ida, &instance);
1828                 spin_unlock(&dev_list_lock);
1829         } while (error == -EAGAIN);
1830
1831         if (error)
1832                 return -ENODEV;
1833
1834         dev->instance = instance;
1835         return 0;
1836 }
1837
1838 static void nvme_release_instance(struct nvme_dev *dev)
1839 {
1840         spin_lock(&dev_list_lock);
1841         ida_remove(&nvme_instance_ida, dev->instance);
1842         spin_unlock(&dev_list_lock);
1843 }
1844
1845 static void nvme_free_dev(struct kref *kref)
1846 {
1847         struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
1848         nvme_dev_remove(dev);
1849         pci_disable_msix(dev->pci_dev);
1850         iounmap(dev->bar);
1851         nvme_release_instance(dev);
1852         nvme_release_prp_pools(dev);
1853         pci_disable_device(dev->pci_dev);
1854         pci_release_regions(dev->pci_dev);
1855         kfree(dev->queues);
1856         kfree(dev->entry);
1857         kfree(dev);
1858 }
1859
1860 static int nvme_dev_open(struct inode *inode, struct file *f)
1861 {
1862         struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
1863                                                                 miscdev);
1864         kref_get(&dev->kref);
1865         f->private_data = dev;
1866         return 0;
1867 }
1868
1869 static int nvme_dev_release(struct inode *inode, struct file *f)
1870 {
1871         struct nvme_dev *dev = f->private_data;
1872         kref_put(&dev->kref, nvme_free_dev);
1873         return 0;
1874 }
1875
1876 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1877 {
1878         struct nvme_dev *dev = f->private_data;
1879         switch (cmd) {
1880         case NVME_IOCTL_ADMIN_CMD:
1881                 return nvme_user_admin_cmd(dev, (void __user *)arg);
1882         default:
1883                 return -ENOTTY;
1884         }
1885 }
1886
1887 static const struct file_operations nvme_dev_fops = {
1888         .owner          = THIS_MODULE,
1889         .open           = nvme_dev_open,
1890         .release        = nvme_dev_release,
1891         .unlocked_ioctl = nvme_dev_ioctl,
1892         .compat_ioctl   = nvme_dev_ioctl,
1893 };
1894
1895 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1896 {
1897         int bars, result = -ENOMEM;
1898         struct nvme_dev *dev;
1899
1900         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1901         if (!dev)
1902                 return -ENOMEM;
1903         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1904                                                                 GFP_KERNEL);
1905         if (!dev->entry)
1906                 goto free;
1907         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1908                                                                 GFP_KERNEL);
1909         if (!dev->queues)
1910                 goto free;
1911
1912         if (pci_enable_device_mem(pdev))
1913                 goto free;
1914         pci_set_master(pdev);
1915         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1916         if (pci_request_selected_regions(pdev, bars, "nvme"))
1917                 goto disable;
1918
1919         INIT_LIST_HEAD(&dev->namespaces);
1920         dev->pci_dev = pdev;
1921         pci_set_drvdata(pdev, dev);
1922         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1923         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1924         result = nvme_set_instance(dev);
1925         if (result)
1926                 goto disable;
1927
1928         dev->entry[0].vector = pdev->irq;
1929
1930         result = nvme_setup_prp_pools(dev);
1931         if (result)
1932                 goto disable_msix;
1933
1934         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1935         if (!dev->bar) {
1936                 result = -ENOMEM;
1937                 goto disable_msix;
1938         }
1939
1940         result = nvme_configure_admin_queue(dev);
1941         if (result)
1942                 goto unmap;
1943         dev->queue_count++;
1944
1945         spin_lock(&dev_list_lock);
1946         list_add(&dev->node, &dev_list);
1947         spin_unlock(&dev_list_lock);
1948
1949         result = nvme_dev_add(dev);
1950         if (result)
1951                 goto delete;
1952
1953         scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
1954         dev->miscdev.minor = MISC_DYNAMIC_MINOR;
1955         dev->miscdev.parent = &pdev->dev;
1956         dev->miscdev.name = dev->name;
1957         dev->miscdev.fops = &nvme_dev_fops;
1958         result = misc_register(&dev->miscdev);
1959         if (result)
1960                 goto remove;
1961
1962         kref_init(&dev->kref);
1963         return 0;
1964
1965  remove:
1966         nvme_dev_remove(dev);
1967  delete:
1968         spin_lock(&dev_list_lock);
1969         list_del(&dev->node);
1970         spin_unlock(&dev_list_lock);
1971
1972         nvme_free_queues(dev);
1973  unmap:
1974         iounmap(dev->bar);
1975  disable_msix:
1976         pci_disable_msix(pdev);
1977         nvme_release_instance(dev);
1978         nvme_release_prp_pools(dev);
1979  disable:
1980         pci_disable_device(pdev);
1981         pci_release_regions(pdev);
1982  free:
1983         kfree(dev->queues);
1984         kfree(dev->entry);
1985         kfree(dev);
1986         return result;
1987 }
1988
1989 static void nvme_remove(struct pci_dev *pdev)
1990 {
1991         struct nvme_dev *dev = pci_get_drvdata(pdev);
1992         misc_deregister(&dev->miscdev);
1993         kref_put(&dev->kref, nvme_free_dev);
1994 }
1995
1996 /* These functions are yet to be implemented */
1997 #define nvme_error_detected NULL
1998 #define nvme_dump_registers NULL
1999 #define nvme_link_reset NULL
2000 #define nvme_slot_reset NULL
2001 #define nvme_error_resume NULL
2002 #define nvme_suspend NULL
2003 #define nvme_resume NULL
2004
2005 static const struct pci_error_handlers nvme_err_handler = {
2006         .error_detected = nvme_error_detected,
2007         .mmio_enabled   = nvme_dump_registers,
2008         .link_reset     = nvme_link_reset,
2009         .slot_reset     = nvme_slot_reset,
2010         .resume         = nvme_error_resume,
2011 };
2012
2013 /* Move to pci_ids.h later */
2014 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2015
2016 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
2017         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2018         { 0, }
2019 };
2020 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2021
2022 static struct pci_driver nvme_driver = {
2023         .name           = "nvme",
2024         .id_table       = nvme_id_table,
2025         .probe          = nvme_probe,
2026         .remove         = nvme_remove,
2027         .suspend        = nvme_suspend,
2028         .resume         = nvme_resume,
2029         .err_handler    = &nvme_err_handler,
2030 };
2031
2032 static int __init nvme_init(void)
2033 {
2034         int result;
2035
2036         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2037         if (IS_ERR(nvme_thread))
2038                 return PTR_ERR(nvme_thread);
2039
2040         result = register_blkdev(nvme_major, "nvme");
2041         if (result < 0)
2042                 goto kill_kthread;
2043         else if (result > 0)
2044                 nvme_major = result;
2045
2046         result = pci_register_driver(&nvme_driver);
2047         if (result)
2048                 goto unregister_blkdev;
2049         return 0;
2050
2051  unregister_blkdev:
2052         unregister_blkdev(nvme_major, "nvme");
2053  kill_kthread:
2054         kthread_stop(nvme_thread);
2055         return result;
2056 }
2057
2058 static void __exit nvme_exit(void)
2059 {
2060         pci_unregister_driver(&nvme_driver);
2061         unregister_blkdev(nvme_major, "nvme");
2062         kthread_stop(nvme_thread);
2063 }
2064
2065 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2066 MODULE_LICENSE("GPL");
2067 MODULE_VERSION("0.8");
2068 module_init(nvme_init);
2069 module_exit(nvme_exit);