4 #include <linux/genhd.h>
5 #include <linux/mutex.h>
11 #define MAX_PART (1 << NWD_SHIFT)
15 #define IO_NEEDS_RETRY 3
22 typedef struct ctlr_info ctlr_info_t;
24 struct access_method {
25 void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
26 void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
27 unsigned long (*fifo_full)(ctlr_info_t *h);
28 bool (*intr_pending)(ctlr_info_t *h);
29 unsigned long (*command_completed)(ctlr_info_t *h);
31 typedef struct _drive_info_struct
33 unsigned char LunID[8];
35 struct request_queue *queue;
41 int raid_level; /* set to -1 to indicate that
42 * the drive is not in use/configured
44 int busy_configuring; /* This is set when a drive is being removed
45 * to prevent it from being opened or it's
46 * queue from being started.
49 __u8 serial_no[16]; /* from inquiry page 0x83,
50 * not necc. null terminated.
52 char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */
53 char model[MODEL_LEN + 1]; /* SCSI model string */
54 char rev[REV_LEN + 1]; /* SCSI revision string */
55 char device_initialized; /* indicates whether dev is initialized */
63 char firm_ver[4]; /* Firmware version */
68 int nr_cmds; /* Number of commands allowed on this controller */
69 CfgTable_struct __iomem *cfgtable;
70 int interrupts_enabled;
73 int commands_outstanding;
74 int max_outstanding; /* Debug */
77 int usage_count; /* number of opens all all minor devices */
78 /* Need space for temp sg list
79 * number of scatter/gathers supported
80 * number of scatter/gathers in chained block
82 struct scatterlist **scatter_list;
85 int max_cmd_sgentries;
86 SGDescriptor_struct **cmd_sg_list;
88 # define PERF_MODE_INT 0
89 # define DOORBELL_INT 1
90 # define SIMPLE_MODE_INT 2
91 # define MEMQ_MODE_INT 3
93 unsigned int msix_vector;
94 unsigned int msi_vector;
95 int cciss_max_sectors;
98 BYTE cciss_read_capacity;
100 /* information about each logical volume */
101 drive_info_struct *drv[CISS_MAX_LUN];
103 struct access_method access;
105 /* queue and queue Info */
106 struct hlist_head reqQ;
107 struct hlist_head cmpQ;
109 unsigned int maxQsinceinit;
113 /* pointers to command and error info pool */
114 CommandList_struct *cmd_pool;
115 dma_addr_t cmd_pool_dhandle;
116 ErrorInfo_struct *errinfo_pool;
117 dma_addr_t errinfo_pool_dhandle;
118 unsigned long *cmd_pool_bits;
121 int busy_configuring;
122 int busy_initializing;
124 struct mutex busy_shutting_down;
126 /* This element holds the zero based queue number of the last
127 * queue to be started. It is used for fairness.
131 /* Disk structures we need to pass back */
132 struct gendisk *gendisk[CISS_MAX_LUN];
133 #ifdef CONFIG_CISS_SCSI_TAPE
134 struct cciss_scsi_adapter_data_t *scsi_ctlr;
137 struct list_head scan_list;
138 struct completion scan_wait;
141 * Performant mode tables.
145 struct TransTable_struct *transtable;
146 unsigned long transMethod;
149 * Performant mode completion buffer
152 dma_addr_t reply_pool_dhandle;
153 u64 *reply_pool_head;
154 size_t reply_pool_size;
155 unsigned char reply_pool_wraparound;
156 u32 *blockFetchTable;
159 /* Defining the diffent access_methods
161 * Memory mapped FIFO interface (SMART 53xx cards)
163 #define SA5_DOORBELL 0x20
164 #define SA5_REQUEST_PORT_OFFSET 0x40
165 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
166 #define SA5_REPLY_PORT_OFFSET 0x44
167 #define SA5_INTR_STATUS 0x30
168 #define SA5_SCRATCHPAD_OFFSET 0xB0
170 #define SA5_CTCFG_OFFSET 0xB4
171 #define SA5_CTMEM_OFFSET 0xB8
173 #define SA5_INTR_OFF 0x08
174 #define SA5B_INTR_OFF 0x04
175 #define SA5_INTR_PENDING 0x08
176 #define SA5B_INTR_PENDING 0x04
177 #define FIFO_EMPTY 0xffffffff
178 #define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
179 /* Perf. mode flags */
180 #define SA5_PERF_INTR_PENDING 0x04
181 #define SA5_PERF_INTR_OFF 0x05
182 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
183 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
184 #define SA5_OUTDB_CLEAR 0xA0
185 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
186 #define SA5_OUTDB_STATUS 0x9C
189 #define CISS_ERROR_BIT 0x02
191 #define CCISS_INTR_ON 1
192 #define CCISS_INTR_OFF 0
194 Send the command to the hardware
196 static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
199 printk(KERN_WARNING "cciss%d: Sending %08x - down to controller\n",
200 h->ctlr, c->busaddr);
201 #endif /* CCISS_DEBUG */
202 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
203 h->commands_outstanding++;
204 if ( h->commands_outstanding > h->max_outstanding)
205 h->max_outstanding = h->commands_outstanding;
209 * This card is the opposite of the other cards.
210 * 0 turns interrupts on...
211 * 0x08 turns them off...
213 static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
216 { /* Turn interrupts on */
217 h->interrupts_enabled = 1;
218 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
219 } else /* Turn them off */
221 h->interrupts_enabled = 0;
222 writel( SA5_INTR_OFF,
223 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
227 * This card is the opposite of the other cards.
228 * 0 turns interrupts on...
229 * 0x04 turns them off...
231 static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
234 { /* Turn interrupts on */
235 h->interrupts_enabled = 1;
236 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
237 } else /* Turn them off */
239 h->interrupts_enabled = 0;
240 writel( SA5B_INTR_OFF,
241 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
245 /* Performant mode intr_mask */
246 static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)
248 if (val) { /* turn on interrupts */
249 h->interrupts_enabled = 1;
250 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
252 h->interrupts_enabled = 0;
253 writel(SA5_PERF_INTR_OFF,
254 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
259 * Returns true if fifo is full.
262 static unsigned long SA5_fifo_full(ctlr_info_t *h)
264 if( h->commands_outstanding >= h->max_commands)
271 * returns value read from hardware.
272 * returns FIFO_EMPTY if there is nothing to read
274 static unsigned long SA5_completed(ctlr_info_t *h)
276 unsigned long register_value
277 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
278 if(register_value != FIFO_EMPTY)
280 h->commands_outstanding--;
282 printk("cciss: Read %lx back from board\n", register_value);
283 #endif /* CCISS_DEBUG */
288 printk("cciss: FIFO Empty read\n");
291 return ( register_value);
295 /* Performant mode command completed */
296 static unsigned long SA5_performant_completed(ctlr_info_t *h)
298 unsigned long register_value = FIFO_EMPTY;
300 /* flush the controller write of the reply queue by reading
301 * outbound doorbell status register.
303 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
304 /* msi auto clears the interrupt pending bit. */
305 if (!(h->msi_vector || h->msix_vector)) {
306 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
307 /* Do a read in order to flush the write to the controller
310 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
313 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
314 register_value = *(h->reply_pool_head);
315 (h->reply_pool_head)++;
316 h->commands_outstanding--;
318 register_value = FIFO_EMPTY;
320 /* Check for wraparound */
321 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
322 h->reply_pool_head = h->reply_pool;
323 h->reply_pool_wraparound ^= 1;
326 return register_value;
329 * Returns true if an interrupt is pending..
331 static bool SA5_intr_pending(ctlr_info_t *h)
333 unsigned long register_value =
334 readl(h->vaddr + SA5_INTR_STATUS);
336 printk("cciss: intr_pending %lx\n", register_value);
337 #endif /* CCISS_DEBUG */
338 if( register_value & SA5_INTR_PENDING)
344 * Returns true if an interrupt is pending..
346 static bool SA5B_intr_pending(ctlr_info_t *h)
348 unsigned long register_value =
349 readl(h->vaddr + SA5_INTR_STATUS);
351 printk("cciss: intr_pending %lx\n", register_value);
352 #endif /* CCISS_DEBUG */
353 if( register_value & SA5B_INTR_PENDING)
358 static bool SA5_performant_intr_pending(ctlr_info_t *h)
360 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
365 if (h->msi_vector || h->msix_vector)
368 /* Read outbound doorbell to flush */
369 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
370 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
373 static struct access_method SA5_access = {
381 static struct access_method SA5B_access = {
389 static struct access_method SA5_performant_access = {
391 SA5_performant_intr_mask,
393 SA5_performant_intr_pending,
394 SA5_performant_completed,
400 struct access_method *access;
401 int nr_cmds; /* Max cmds this kind of ctlr can handle. */
404 #define CCISS_LOCK(i) (&hba[i]->lock)