2 * Broadcom specific AMBA
3 * ChipCommon Power Management Unit driver
5 * Copyright 2009, Michael Buesch <m@bues.ch>
6 * Copyright 2007, 2011, Broadcom Corporation
7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
9 * Licensed under the GNU/GPL. See COPYING for details.
12 #include "bcma_private.h"
13 #include <linux/export.h>
14 #include <linux/bcma/bcma.h>
16 static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
18 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
19 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
20 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
23 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
25 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
26 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
27 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
29 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
31 void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
34 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
35 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
36 bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
38 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
40 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
41 u32 offset, u32 mask, u32 set)
43 bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
44 bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
45 bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
47 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
49 void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
52 bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
53 bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
54 bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
56 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
58 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
60 struct bcma_bus *bus = cc->core->bus;
61 u32 min_msk = 0, max_msk = 0;
63 switch (bus->chipinfo.id) {
64 case BCMA_CHIP_ID_BCM4313:
69 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
73 /* Set the resource masks. */
75 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
77 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
80 * Add some delay; allow resources to come up and settle.
81 * Delay is required for SoC (early init).
86 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
87 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
89 struct bcma_bus *bus = cc->core->bus;
92 val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
94 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
95 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
96 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
97 else if (bus->chipinfo.rev > 0)
98 val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
100 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
101 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
102 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
104 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
107 static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
109 struct bcma_bus *bus = cc->core->bus;
111 switch (bus->chipinfo.id) {
112 case BCMA_CHIP_ID_BCM4313:
113 /* enable 12 mA drive strenth for 4313 and set chipControl
115 bcma_chipco_chipctl_maskset(cc, 0,
116 ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
117 BCMA_CCTRL_4313_12MA_LED_DRIVE);
119 case BCMA_CHIP_ID_BCM4331:
120 case BCMA_CHIP_ID_BCM43431:
121 /* Ext PA lines must be enabled for tx on BCM4331 */
122 bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
124 case BCMA_CHIP_ID_BCM43224:
125 case BCMA_CHIP_ID_BCM43421:
126 /* enable 12 mA drive strenth for 43224 and set chipControl
128 if (bus->chipinfo.rev == 0) {
129 bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
130 ~BCMA_CCTRL_43224_GPIO_TOGGLE,
131 BCMA_CCTRL_43224_GPIO_TOGGLE);
132 bcma_chipco_chipctl_maskset(cc, 0,
133 ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
134 BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
136 bcma_chipco_chipctl_maskset(cc, 0,
137 ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
138 BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
142 bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
147 void bcma_pmu_early_init(struct bcma_drv_cc *cc)
151 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
152 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
154 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
155 cc->pmu.rev, pmucap);
158 void bcma_pmu_init(struct bcma_drv_cc *cc)
160 if (cc->pmu.rev == 1)
161 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
162 ~BCMA_CC_PMU_CTL_NOILPONW);
164 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
165 BCMA_CC_PMU_CTL_NOILPONW);
167 bcma_pmu_resources_init(cc);
168 bcma_pmu_workarounds(cc);
171 u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
173 struct bcma_bus *bus = cc->core->bus;
175 switch (bus->chipinfo.id) {
176 case BCMA_CHIP_ID_BCM4716:
177 case BCMA_CHIP_ID_BCM4748:
178 case BCMA_CHIP_ID_BCM47162:
179 case BCMA_CHIP_ID_BCM4313:
180 case BCMA_CHIP_ID_BCM5357:
181 case BCMA_CHIP_ID_BCM4749:
182 case BCMA_CHIP_ID_BCM53572:
185 case BCMA_CHIP_ID_BCM5356:
186 case BCMA_CHIP_ID_BCM4706:
190 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
191 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
193 return BCMA_CC_PMU_ALP_CLOCK;
196 /* Find the output of the "m" pll divider given pll controls that start with
197 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
199 static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
201 u32 tmp, div, ndiv, p1, p2, fc;
202 struct bcma_bus *bus = cc->core->bus;
204 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
208 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
209 bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
210 /* Detect failure in clock setting */
211 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
213 return 133 * 1000000;
216 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
217 p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
218 p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
220 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
221 div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
222 BCMA_CC_PPL_MDIV_MASK;
224 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
225 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
227 /* Do calculation in Mhz */
228 fc = bcma_pmu_alp_clock(cc) / 1000000;
229 fc = (p1 * ndiv * fc) / p2;
231 /* Return clock in Hertz */
232 return (fc / div) * 1000000;
235 static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
237 u32 tmp, ndiv, p1div, p2div;
242 /* Get N, P1 and P2 dividers to determine CPU clock */
243 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
244 ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
245 >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
246 p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
247 >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
248 p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
249 >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
251 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
252 if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
253 /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
254 clock = (25000000 / 4) * ndiv * p2div / p1div;
256 /* Fixed reference clock 25MHz and m = 2 */
257 clock = (25000000 / 2) * ndiv * p2div / p1div;
259 if (m == BCMA_CC_PMU5_MAINPLL_SSB)
265 /* query bus clock frequency for PMU-enabled chipcommon */
266 static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
268 struct bcma_bus *bus = cc->core->bus;
270 switch (bus->chipinfo.id) {
271 case BCMA_CHIP_ID_BCM4716:
272 case BCMA_CHIP_ID_BCM4748:
273 case BCMA_CHIP_ID_BCM47162:
274 return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
275 BCMA_CC_PMU5_MAINPLL_SSB);
276 case BCMA_CHIP_ID_BCM5356:
277 return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
278 BCMA_CC_PMU5_MAINPLL_SSB);
279 case BCMA_CHIP_ID_BCM5357:
280 case BCMA_CHIP_ID_BCM4749:
281 return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
282 BCMA_CC_PMU5_MAINPLL_SSB);
283 case BCMA_CHIP_ID_BCM4706:
284 return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
285 BCMA_CC_PMU5_MAINPLL_SSB);
286 case BCMA_CHIP_ID_BCM53572:
289 bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
290 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
292 return BCMA_CC_PMU_HT_CLOCK;
295 /* query cpu clock frequency for PMU-enabled chipcommon */
296 u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
298 struct bcma_bus *bus = cc->core->bus;
300 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
303 if (cc->pmu.rev >= 5) {
305 switch (bus->chipinfo.id) {
306 case BCMA_CHIP_ID_BCM4706:
307 return bcma_pmu_clock_bcm4706(cc,
308 BCMA_CC_PMU4706_MAINPLL_PLL0,
309 BCMA_CC_PMU5_MAINPLL_CPU);
310 case BCMA_CHIP_ID_BCM5356:
311 pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
313 case BCMA_CHIP_ID_BCM5357:
314 case BCMA_CHIP_ID_BCM4749:
315 pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
318 pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
322 return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
325 return bcma_pmu_get_clockcontrol(cc);
328 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
331 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
332 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
335 void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
338 u8 phypll_offset = 0;
339 u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
340 u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
341 struct bcma_bus *bus = cc->core->bus;
343 switch (bus->chipinfo.id) {
344 case BCMA_CHIP_ID_BCM5357:
345 case BCMA_CHIP_ID_BCM4749:
346 case BCMA_CHIP_ID_BCM53572:
347 /* 5357[ab]0, 43236[ab]0, and 6362b0 */
349 /* BCM5357 needs to touch PLL1_PLLCTL[02],
350 so offset PLL0_PLLCTL[02] by 6 */
351 phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
352 bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
353 bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
355 /* RMW only the P1 divider */
356 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
357 BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
358 tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
359 tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
360 tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
361 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
363 /* RMW only the int feedback divider */
364 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
365 BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
366 tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
367 tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
368 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
369 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
374 case BCMA_CHIP_ID_BCM4331:
375 case BCMA_CHIP_ID_BCM43431:
376 if (spuravoid == 2) {
377 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
379 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
381 } else if (spuravoid == 1) {
382 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
384 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
387 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
389 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
395 case BCMA_CHIP_ID_BCM43224:
396 case BCMA_CHIP_ID_BCM43225:
397 case BCMA_CHIP_ID_BCM43421:
398 if (spuravoid == 1) {
399 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
401 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
403 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
405 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
407 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
409 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
412 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
414 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
416 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
418 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
420 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
422 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
428 case BCMA_CHIP_ID_BCM4716:
429 case BCMA_CHIP_ID_BCM4748:
430 case BCMA_CHIP_ID_BCM47162:
431 if (spuravoid == 1) {
432 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
434 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
436 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
438 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
440 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
442 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
445 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
447 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
449 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
451 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
453 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
455 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
462 case BCMA_CHIP_ID_BCM43227:
463 case BCMA_CHIP_ID_BCM43228:
464 case BCMA_CHIP_ID_BCM43428:
466 /* PLL Settings for spur avoidance on/off mode,
467 no on2 support for 43228A0 */
468 if (spuravoid == 1) {
469 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
471 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
473 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
475 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
477 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
479 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
482 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
484 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
486 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
488 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
490 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
492 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
498 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
503 tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
504 bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
506 EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);