2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
4 * This driver is heavily based upon:
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
15 * Look into engine reset on timeout errors. Should not be
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/blkdev.h>
25 #include <linux/delay.h>
26 #include <scsi/scsi_host.h>
27 #include <linux/libata.h>
29 #define DRV_NAME "pata_hpt366"
30 #define DRV_VERSION "0.6.1"
37 /* key for bus clock timings
39 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
40 * DMA. cycles = value + 1
41 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
42 * DMA. cycles = value + 1
43 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
45 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
47 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
48 * during task file register access.
49 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
51 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
55 * 30 PIO_MST enable. if set, the chip is in bus master mode during
60 static const struct hpt_clock hpt366_40[] = {
61 { XFER_UDMA_4, 0x900fd943 },
62 { XFER_UDMA_3, 0x900ad943 },
63 { XFER_UDMA_2, 0x900bd943 },
64 { XFER_UDMA_1, 0x9008d943 },
65 { XFER_UDMA_0, 0x9008d943 },
67 { XFER_MW_DMA_2, 0xa008d943 },
68 { XFER_MW_DMA_1, 0xa010d955 },
69 { XFER_MW_DMA_0, 0xa010d9fc },
71 { XFER_PIO_4, 0xc008d963 },
72 { XFER_PIO_3, 0xc010d974 },
73 { XFER_PIO_2, 0xc010d997 },
74 { XFER_PIO_1, 0xc010d9c7 },
75 { XFER_PIO_0, 0xc018d9d9 },
79 static const struct hpt_clock hpt366_33[] = {
80 { XFER_UDMA_4, 0x90c9a731 },
81 { XFER_UDMA_3, 0x90cfa731 },
82 { XFER_UDMA_2, 0x90caa731 },
83 { XFER_UDMA_1, 0x90cba731 },
84 { XFER_UDMA_0, 0x90c8a731 },
86 { XFER_MW_DMA_2, 0xa0c8a731 },
87 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
88 { XFER_MW_DMA_0, 0xa0c8a797 },
90 { XFER_PIO_4, 0xc0c8a731 },
91 { XFER_PIO_3, 0xc0c8a742 },
92 { XFER_PIO_2, 0xc0d0a753 },
93 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
94 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
98 static const struct hpt_clock hpt366_25[] = {
99 { XFER_UDMA_4, 0x90c98521 },
100 { XFER_UDMA_3, 0x90cf8521 },
101 { XFER_UDMA_2, 0x90cf8521 },
102 { XFER_UDMA_1, 0x90cb8521 },
103 { XFER_UDMA_0, 0x90cb8521 },
105 { XFER_MW_DMA_2, 0xa0ca8521 },
106 { XFER_MW_DMA_1, 0xa0ca8532 },
107 { XFER_MW_DMA_0, 0xa0ca8575 },
109 { XFER_PIO_4, 0xc0ca8521 },
110 { XFER_PIO_3, 0xc0ca8532 },
111 { XFER_PIO_2, 0xc0ca8542 },
112 { XFER_PIO_1, 0xc0d08572 },
113 { XFER_PIO_0, 0xc0d08585 },
117 static const char *bad_ata33[] = {
118 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
122 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
128 static const char *bad_ata66_4[] = {
147 static const char *bad_ata66_3[] = {
152 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
154 unsigned char model_num[ATA_ID_PROD_LEN + 1];
157 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
159 while (list[i] != NULL) {
160 if (!strcmp(list[i], model_num)) {
161 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
171 * hpt366_filter - mode selection filter
175 * Block UDMA on devices that cause trouble with this controller.
178 static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
180 if (adev->class == ATA_DEV_ATA) {
181 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
182 mask &= ~ATA_MASK_UDMA;
183 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
184 mask &= ~(0x07 << ATA_SHIFT_UDMA);
185 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
186 mask &= ~(0x0F << ATA_SHIFT_UDMA);
188 return ata_pci_default_filter(adev, mask);
192 * hpt36x_find_mode - reset the hpt36x bus
194 * @speed: transfer mode
196 * Return the 32bit register programming information for this channel
197 * that matches the speed provided.
200 static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
202 struct hpt_clock *clocks = ap->host->private_data;
204 while(clocks->xfer_speed) {
205 if (clocks->xfer_speed == speed)
206 return clocks->timing;
210 return 0xffffffffU; /* silence compiler warning */
213 static int hpt36x_cable_detect(struct ata_port *ap)
216 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
218 pci_read_config_byte(pdev, 0x5A, &ata66);
219 if (ata66 & (1 << ap->port_no))
220 return ATA_CBL_PATA40;
221 return ATA_CBL_PATA80;
224 static int hpt36x_pre_reset(struct ata_port *ap)
226 static const struct pci_bits hpt36x_enable_bits[] = {
227 { 0x50, 1, 0x04, 0x04 },
228 { 0x54, 1, 0x04, 0x04 }
230 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
232 if (!pci_test_config_bits(pdev, &hpt36x_enable_bits[ap->port_no]))
235 return ata_std_prereset(ap);
239 * hpt36x_error_handler - reset the hpt36x bus
240 * @ap: ATA port to reset
242 * Perform the reset handling for the 366/368
245 static void hpt36x_error_handler(struct ata_port *ap)
247 ata_bmdma_drive_eh(ap, hpt36x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
251 * hpt366_set_piomode - PIO setup
253 * @adev: device on the interface
255 * Perform PIO mode setup.
258 static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
260 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
266 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
267 addr2 = 0x51 + 4 * ap->port_no;
269 /* Fast interrupt prediction disable, hold off interrupt disable */
270 pci_read_config_byte(pdev, addr2, &fast);
273 pci_write_config_byte(pdev, addr2, fast);
276 pci_read_config_dword(pdev, addr1, ®);
277 mode = hpt36x_find_mode(ap, adev->pio_mode);
278 mode &= ~0x8000000; /* No FIFO in PIO */
279 mode &= ~0x30070000; /* Leave config bits alone */
280 reg &= 0x30070000; /* Strip timing bits */
281 pci_write_config_dword(pdev, addr1, reg | mode);
285 * hpt366_set_dmamode - DMA timing setup
287 * @adev: Device being configured
289 * Set up the channel for MWDMA or UDMA modes. Much the same as with
290 * PIO, load the mode number and then set MWDMA or UDMA flag.
293 static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
295 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
301 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
302 addr2 = 0x51 + 4 * ap->port_no;
304 /* Fast interrupt prediction disable, hold off interrupt disable */
305 pci_read_config_byte(pdev, addr2, &fast);
308 pci_write_config_byte(pdev, addr2, fast);
311 pci_read_config_dword(pdev, addr1, ®);
312 mode = hpt36x_find_mode(ap, adev->dma_mode);
313 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
314 mode &= ~0xC0000000; /* Leave config bits alone */
315 reg &= 0xC0000000; /* Strip timing bits */
316 pci_write_config_dword(pdev, addr1, reg | mode);
319 static struct scsi_host_template hpt36x_sht = {
320 .module = THIS_MODULE,
322 .ioctl = ata_scsi_ioctl,
323 .queuecommand = ata_scsi_queuecmd,
324 .can_queue = ATA_DEF_QUEUE,
325 .this_id = ATA_SHT_THIS_ID,
326 .sg_tablesize = LIBATA_MAX_PRD,
327 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
328 .emulated = ATA_SHT_EMULATED,
329 .use_clustering = ATA_SHT_USE_CLUSTERING,
330 .proc_name = DRV_NAME,
331 .dma_boundary = ATA_DMA_BOUNDARY,
332 .slave_configure = ata_scsi_slave_config,
333 .slave_destroy = ata_scsi_slave_destroy,
334 .bios_param = ata_std_bios_param,
336 .resume = ata_scsi_device_resume,
337 .suspend = ata_scsi_device_suspend,
342 * Configuration for HPT366/68
345 static struct ata_port_operations hpt366_port_ops = {
346 .port_disable = ata_port_disable,
347 .set_piomode = hpt366_set_piomode,
348 .set_dmamode = hpt366_set_dmamode,
349 .mode_filter = hpt366_filter,
351 .tf_load = ata_tf_load,
352 .tf_read = ata_tf_read,
353 .check_status = ata_check_status,
354 .exec_command = ata_exec_command,
355 .dev_select = ata_std_dev_select,
357 .freeze = ata_bmdma_freeze,
358 .thaw = ata_bmdma_thaw,
359 .error_handler = hpt36x_error_handler,
360 .post_internal_cmd = ata_bmdma_post_internal_cmd,
361 .cable_detect = hpt36x_cable_detect,
363 .bmdma_setup = ata_bmdma_setup,
364 .bmdma_start = ata_bmdma_start,
365 .bmdma_stop = ata_bmdma_stop,
366 .bmdma_status = ata_bmdma_status,
368 .qc_prep = ata_qc_prep,
369 .qc_issue = ata_qc_issue_prot,
371 .data_xfer = ata_data_xfer,
373 .irq_handler = ata_interrupt,
374 .irq_clear = ata_bmdma_irq_clear,
375 .irq_on = ata_irq_on,
376 .irq_ack = ata_irq_ack,
378 .port_start = ata_port_start,
382 * hpt36x_init_chipset - common chip setup
385 * Perform the chip setup work that must be done at both init and
389 static void hpt36x_init_chipset(struct pci_dev *dev)
392 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
393 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
394 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
395 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
397 pci_read_config_byte(dev, 0x51, &drive_fast);
398 if (drive_fast & 0x80)
399 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
403 * hpt36x_init_one - Initialise an HPT366/368
405 * @id: Entry in match table
407 * Initialise an HPT36x device. There are some interesting complications
408 * here. Firstly the chip may report 366 and be one of several variants.
409 * Secondly all the timings depend on the clock for the chip which we must
412 * This is the known chip mappings. It may be missing a couple of later
415 * Chip version PCI Rev Notes
416 * HPT366 4 (HPT366) 0 UDMA66
417 * HPT366 4 (HPT366) 1 UDMA66
418 * HPT368 4 (HPT366) 2 UDMA66
419 * HPT37x/30x 4 (HPT366) 3+ Other driver
423 static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
425 static struct ata_port_info info_hpt366 = {
427 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
431 .port_ops = &hpt366_port_ops
433 struct ata_port_info *port_info[2] = {&info_hpt366, &info_hpt366};
438 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
441 /* May be a later chip in disguise. Check */
442 /* Newer chips are not in the HPT36x driver. Ignore them */
446 hpt36x_init_chipset(dev);
448 pci_read_config_dword(dev, 0x40, ®1);
450 /* PCI clocking determines the ATA timing values to use */
451 /* info_hpt366 is safe against re-entry so we can scribble on it */
452 switch((reg1 & 0x700) >> 8) {
454 info_hpt366.private_data = &hpt366_40;
457 info_hpt366.private_data = &hpt366_25;
460 info_hpt366.private_data = &hpt366_33;
463 /* Now kick off ATA set up */
464 return ata_pci_init_one(dev, port_info, 2);
468 static int hpt36x_reinit_one(struct pci_dev *dev)
470 hpt36x_init_chipset(dev);
471 return ata_pci_device_resume(dev);
475 static const struct pci_device_id hpt36x[] = {
476 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
480 static struct pci_driver hpt36x_pci_driver = {
483 .probe = hpt36x_init_one,
484 .remove = ata_pci_remove_one,
486 .suspend = ata_pci_device_suspend,
487 .resume = hpt36x_reinit_one,
491 static int __init hpt36x_init(void)
493 return pci_register_driver(&hpt36x_pci_driver);
496 static void __exit hpt36x_exit(void)
498 pci_unregister_driver(&hpt36x_pci_driver);
501 MODULE_AUTHOR("Alan Cox");
502 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
503 MODULE_LICENSE("GPL");
504 MODULE_DEVICE_TABLE(pci, hpt36x);
505 MODULE_VERSION(DRV_VERSION);
507 module_init(hpt36x_init);
508 module_exit(hpt36x_exit);