2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
59 /* board IDs by feature in alphabetical order */
65 /* board IDs for specific chipsets in alphabetical order */
71 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 static struct scsi_host_template ahci_sht = {
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
107 static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
113 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
115 static const struct ata_port_info ahci_port_info[] = {
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
124 [board_ahci_ign_iferr] =
126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
132 [board_ahci_nosntf] =
134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
140 [board_ahci_yes_fbs] =
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
153 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_sb600_ops,
193 [board_ahci_sb700] = /* for SB700 and SB800 */
195 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_sb600_ops,
201 [board_ahci_vt8251] =
203 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_vt8251_ops,
211 static const struct pci_device_id ahci_pci_tbl[] = {
213 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
214 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
215 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
216 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
217 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
218 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
219 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
223 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
225 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
227 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
228 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
239 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
240 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
241 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
242 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
243 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
244 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
245 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
246 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
248 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
250 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
251 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
252 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
259 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
260 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
262 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
263 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
264 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
265 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
266 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
268 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
269 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
271 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
272 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
273 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
276 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
277 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
285 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
286 /* AMD is using RAID class only for ahci controllers */
287 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
291 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
292 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
295 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
303 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
381 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
382 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
383 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
386 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
387 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
388 { PCI_DEVICE(0x1b4b, 0x9123),
389 .class = PCI_CLASS_STORAGE_SATA_AHCI,
390 .class_mask = 0xffffff,
391 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
392 { PCI_DEVICE(0x1b4b, 0x9125),
393 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
394 { PCI_DEVICE(0x1b4b, 0x91a3),
395 .driver_data = board_ahci_yes_fbs },
398 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
400 /* Generic, PCI class code for AHCI */
401 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
402 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
404 { } /* terminate list */
408 static struct pci_driver ahci_pci_driver = {
410 .id_table = ahci_pci_tbl,
411 .probe = ahci_init_one,
412 .remove = ata_pci_remove_one,
414 .suspend = ahci_pci_device_suspend,
415 .resume = ahci_pci_device_resume,
419 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
420 static int marvell_enable;
422 static int marvell_enable = 1;
424 module_param(marvell_enable, int, 0644);
425 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
428 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
429 struct ahci_host_priv *hpriv)
431 unsigned int force_port_map = 0;
432 unsigned int mask_port_map = 0;
434 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
435 dev_info(&pdev->dev, "JMB361 has only one port\n");
440 * Temporary Marvell 6145 hack: PATA port presence
441 * is asserted through the standard AHCI port
442 * presence register, as bit 4 (counting from 0)
444 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
445 if (pdev->device == 0x6121)
450 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
453 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
457 static int ahci_pci_reset_controller(struct ata_host *host)
459 struct pci_dev *pdev = to_pci_dev(host->dev);
461 ahci_reset_controller(host);
463 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
464 struct ahci_host_priv *hpriv = host->private_data;
468 pci_read_config_word(pdev, 0x92, &tmp16);
469 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
470 tmp16 |= hpriv->port_map;
471 pci_write_config_word(pdev, 0x92, tmp16);
478 static void ahci_pci_init_controller(struct ata_host *host)
480 struct ahci_host_priv *hpriv = host->private_data;
481 struct pci_dev *pdev = to_pci_dev(host->dev);
482 void __iomem *port_mmio;
486 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
487 if (pdev->device == 0x6121)
491 port_mmio = __ahci_port_base(host, mv);
493 writel(0, port_mmio + PORT_IRQ_MASK);
496 tmp = readl(port_mmio + PORT_IRQ_STAT);
497 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
499 writel(tmp, port_mmio + PORT_IRQ_STAT);
502 ahci_init_controller(host);
505 static int ahci_sb600_check_ready(struct ata_link *link)
507 void __iomem *port_mmio = ahci_port_base(link->ap);
508 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
509 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
512 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
513 * which can save timeout delay.
515 if (irq_status & PORT_IRQ_BAD_PMP)
518 return ata_check_ready(status);
521 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
522 unsigned long deadline)
524 struct ata_port *ap = link->ap;
525 void __iomem *port_mmio = ahci_port_base(ap);
526 int pmp = sata_srst_pmp(link);
532 rc = ahci_do_softreset(link, class, pmp, deadline,
533 ahci_sb600_check_ready);
536 * Soft reset fails on some ATI chips with IPMS set when PMP
537 * is enabled but SATA HDD/ODD is connected to SATA port,
538 * do soft reset again to port 0.
541 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
542 if (irq_sts & PORT_IRQ_BAD_PMP) {
543 ata_link_printk(link, KERN_WARNING,
544 "applying SB600 PMP SRST workaround "
546 rc = ahci_do_softreset(link, class, 0, deadline,
554 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
555 unsigned long deadline)
557 struct ata_port *ap = link->ap;
563 ahci_stop_engine(ap);
565 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
566 deadline, &online, NULL);
568 ahci_start_engine(ap);
570 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
572 /* vt8251 doesn't clear BSY on signature FIS reception,
573 * request follow-up softreset.
575 return online ? -EAGAIN : rc;
578 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
579 unsigned long deadline)
581 struct ata_port *ap = link->ap;
582 struct ahci_port_priv *pp = ap->private_data;
583 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
584 struct ata_taskfile tf;
588 ahci_stop_engine(ap);
590 /* clear D2H reception area to properly wait for D2H FIS */
591 ata_tf_init(link->device, &tf);
593 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
595 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
596 deadline, &online, NULL);
598 ahci_start_engine(ap);
600 /* The pseudo configuration device on SIMG4726 attached to
601 * ASUS P5W-DH Deluxe doesn't send signature FIS after
602 * hardreset if no device is attached to the first downstream
603 * port && the pseudo device locks up on SRST w/ PMP==0. To
604 * work around this, wait for !BSY only briefly. If BSY isn't
605 * cleared, perform CLO and proceed to IDENTIFY (achieved by
606 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
608 * Wait for two seconds. Devices attached to downstream port
609 * which can't process the following IDENTIFY after this will
610 * have to be reset again. For most cases, this should
611 * suffice while making probing snappish enough.
614 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
617 ahci_kick_engine(ap);
623 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
625 struct ata_host *host = dev_get_drvdata(&pdev->dev);
626 struct ahci_host_priv *hpriv = host->private_data;
627 void __iomem *mmio = hpriv->mmio;
630 if (mesg.event & PM_EVENT_SUSPEND &&
631 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
633 "BIOS update required for suspend/resume\n");
637 if (mesg.event & PM_EVENT_SLEEP) {
638 /* AHCI spec rev1.1 section 8.3.3:
639 * Software must disable interrupts prior to requesting a
640 * transition of the HBA to D3 state.
642 ctl = readl(mmio + HOST_CTL);
644 writel(ctl, mmio + HOST_CTL);
645 readl(mmio + HOST_CTL); /* flush */
648 return ata_pci_device_suspend(pdev, mesg);
651 static int ahci_pci_device_resume(struct pci_dev *pdev)
653 struct ata_host *host = dev_get_drvdata(&pdev->dev);
656 rc = ata_pci_device_do_resume(pdev);
660 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
661 rc = ahci_pci_reset_controller(host);
665 ahci_pci_init_controller(host);
668 ata_host_resume(host);
674 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
679 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
680 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
682 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
685 "64-bit DMA enable failed\n");
690 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
692 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
695 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
698 "32-bit consistent DMA enable failed\n");
705 static void ahci_pci_print_info(struct ata_host *host)
707 struct pci_dev *pdev = to_pci_dev(host->dev);
711 pci_read_config_word(pdev, 0x0a, &cc);
712 if (cc == PCI_CLASS_STORAGE_IDE)
714 else if (cc == PCI_CLASS_STORAGE_SATA)
716 else if (cc == PCI_CLASS_STORAGE_RAID)
721 ahci_print_info(host, scc_s);
724 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
725 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
726 * support PMP and the 4726 either directly exports the device
727 * attached to the first downstream port or acts as a hardware storage
728 * controller and emulate a single ATA device (can be RAID 0/1 or some
729 * other configuration).
731 * When there's no device attached to the first downstream port of the
732 * 4726, "Config Disk" appears, which is a pseudo ATA device to
733 * configure the 4726. However, ATA emulation of the device is very
734 * lame. It doesn't send signature D2H Reg FIS after the initial
735 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
737 * The following function works around the problem by always using
738 * hardreset on the port and not depending on receiving signature FIS
739 * afterward. If signature FIS isn't received soon, ATA class is
740 * assumed without follow-up softreset.
742 static void ahci_p5wdh_workaround(struct ata_host *host)
744 static struct dmi_system_id sysids[] = {
746 .ident = "P5W DH Deluxe",
748 DMI_MATCH(DMI_SYS_VENDOR,
749 "ASUSTEK COMPUTER INC"),
750 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
755 struct pci_dev *pdev = to_pci_dev(host->dev);
757 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
758 dmi_check_system(sysids)) {
759 struct ata_port *ap = host->ports[1];
762 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
764 ap->ops = &ahci_p5wdh_ops;
765 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
769 /* only some SB600 ahci controllers can do 64bit DMA */
770 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
772 static const struct dmi_system_id sysids[] = {
774 * The oldest version known to be broken is 0901 and
775 * working is 1501 which was released on 2007-10-26.
776 * Enable 64bit DMA on 1501 and anything newer.
778 * Please read bko#9412 for more info.
781 .ident = "ASUS M2A-VM",
783 DMI_MATCH(DMI_BOARD_VENDOR,
784 "ASUSTeK Computer INC."),
785 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
787 .driver_data = "20071026", /* yyyymmdd */
790 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
793 * BIOS versions earlier than 1.5 had the Manufacturer DMI
794 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
795 * This spelling mistake was fixed in BIOS version 1.5, so
796 * 1.5 and later have the Manufacturer as
797 * "MICRO-STAR INTERNATIONAL CO.,LTD".
798 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
800 * BIOS versions earlier than 1.9 had a Board Product Name
801 * DMI field of "MS-7376". This was changed to be
802 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
803 * match on DMI_BOARD_NAME of "MS-7376".
806 .ident = "MSI K9A2 Platinum",
808 DMI_MATCH(DMI_BOARD_VENDOR,
810 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
815 const struct dmi_system_id *match;
816 int year, month, date;
819 match = dmi_first_match(sysids);
820 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
824 if (!match->driver_data)
827 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
828 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
830 if (strcmp(buf, match->driver_data) >= 0)
834 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
840 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
844 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
846 static const struct dmi_system_id broken_systems[] = {
848 .ident = "HP Compaq nx6310",
850 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
851 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
853 /* PCI slot number of the controller */
854 .driver_data = (void *)0x1FUL,
857 .ident = "HP Compaq 6720s",
859 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
860 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
862 /* PCI slot number of the controller */
863 .driver_data = (void *)0x1FUL,
866 { } /* terminate list */
868 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
871 unsigned long slot = (unsigned long)dmi->driver_data;
872 /* apply the quirk only to on-board controllers */
873 return slot == PCI_SLOT(pdev->devfn);
879 static bool ahci_broken_suspend(struct pci_dev *pdev)
881 static const struct dmi_system_id sysids[] = {
883 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
884 * to the harddisk doesn't become online after
885 * resuming from STR. Warn and fail suspend.
887 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
889 * Use dates instead of versions to match as HP is
890 * apparently recycling both product and version
893 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
898 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
899 DMI_MATCH(DMI_PRODUCT_NAME,
900 "HP Pavilion dv4 Notebook PC"),
902 .driver_data = "20090105", /* F.30 */
907 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
908 DMI_MATCH(DMI_PRODUCT_NAME,
909 "HP Pavilion dv5 Notebook PC"),
911 .driver_data = "20090506", /* F.16 */
916 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
917 DMI_MATCH(DMI_PRODUCT_NAME,
918 "HP Pavilion dv6 Notebook PC"),
920 .driver_data = "20090423", /* F.21 */
925 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
926 DMI_MATCH(DMI_PRODUCT_NAME,
927 "HP HDX18 Notebook PC"),
929 .driver_data = "20090430", /* F.23 */
932 * Acer eMachines G725 has the same problem. BIOS
933 * V1.03 is known to be broken. V3.04 is known to
934 * work. Between, there are V1.06, V2.06 and V3.03
935 * that we don't have much idea about. For now,
936 * blacklist anything older than V3.04.
938 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
943 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
944 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
946 .driver_data = "20091216", /* V3.04 */
948 { } /* terminate list */
950 const struct dmi_system_id *dmi = dmi_first_match(sysids);
951 int year, month, date;
954 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
957 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
958 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
960 return strcmp(buf, dmi->driver_data) < 0;
963 static bool ahci_broken_online(struct pci_dev *pdev)
965 #define ENCODE_BUSDEVFN(bus, slot, func) \
966 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
967 static const struct dmi_system_id sysids[] = {
969 * There are several gigabyte boards which use
970 * SIMG5723s configured as hardware RAID. Certain
971 * 5723 firmware revisions shipped there keep the link
972 * online but fail to answer properly to SRST or
973 * IDENTIFY when no device is attached downstream
974 * causing libata to retry quite a few times leading
975 * to excessive detection delay.
977 * As these firmwares respond to the second reset try
978 * with invalid device signature, considering unknown
979 * sig as offline works around the problem acceptably.
984 DMI_MATCH(DMI_BOARD_VENDOR,
985 "Gigabyte Technology Co., Ltd."),
986 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
988 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
993 DMI_MATCH(DMI_BOARD_VENDOR,
994 "Gigabyte Technology Co., Ltd."),
995 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
997 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
999 { } /* terminate list */
1001 #undef ENCODE_BUSDEVFN
1002 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1008 val = (unsigned long)dmi->driver_data;
1010 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1013 #ifdef CONFIG_ATA_ACPI
1014 static void ahci_gtf_filter_workaround(struct ata_host *host)
1016 static const struct dmi_system_id sysids[] = {
1018 * Aspire 3810T issues a bunch of SATA enable commands
1019 * via _GTF including an invalid one and one which is
1020 * rejected by the device. Among the successful ones
1021 * is FPDMA non-zero offset enable which when enabled
1022 * only on the drive side leads to NCQ command
1023 * failures. Filter it out.
1026 .ident = "Aspire 3810T",
1028 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1029 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1031 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1035 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1036 unsigned int filter;
1042 filter = (unsigned long)dmi->driver_data;
1043 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1044 filter, dmi->ident);
1046 for (i = 0; i < host->n_ports; i++) {
1047 struct ata_port *ap = host->ports[i];
1048 struct ata_link *link;
1049 struct ata_device *dev;
1051 ata_for_each_link(link, ap, EDGE)
1052 ata_for_each_dev(dev, link, ALL)
1053 dev->gtf_filter |= filter;
1057 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1061 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1063 static int printed_version;
1064 unsigned int board_id = ent->driver_data;
1065 struct ata_port_info pi = ahci_port_info[board_id];
1066 const struct ata_port_info *ppi[] = { &pi, NULL };
1067 struct device *dev = &pdev->dev;
1068 struct ahci_host_priv *hpriv;
1069 struct ata_host *host;
1074 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1076 if (!printed_version++)
1077 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1079 /* The AHCI driver can only drive the SATA ports, the PATA driver
1080 can drive them all so if both drivers are selected make sure
1081 AHCI stays out of the way */
1082 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1086 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1087 * ahci, use ata_generic instead.
1089 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1090 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1091 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1092 pdev->subsystem_device == 0xcb89)
1095 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1096 * At the moment, we can only use the AHCI mode. Let the users know
1097 * that for SAS drives they're out of luck.
1099 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1100 dev_info(&pdev->dev,
1101 "PDC42819 can only drive SATA devices with this driver\n");
1103 /* acquire resources */
1104 rc = pcim_enable_device(pdev);
1108 /* AHCI controllers often implement SFF compatible interface.
1109 * Grab all PCI BARs just in case.
1111 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1113 pcim_pin_device(pdev);
1117 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1118 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1121 /* ICH6s share the same PCI ID for both piix and ahci
1122 * modes. Enabling ahci mode while MAP indicates
1123 * combined mode is a bad idea. Yield to ata_piix.
1125 pci_read_config_byte(pdev, ICH_MAP, &map);
1127 dev_info(&pdev->dev,
1128 "controller is in combined mode, can't enable AHCI mode\n");
1133 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1136 hpriv->flags |= (unsigned long)pi.private_data;
1138 /* MCP65 revision A1 and A2 can't do MSI */
1139 if (board_id == board_ahci_mcp65 &&
1140 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1141 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1143 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1144 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1145 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1147 /* only some SB600s can do 64bit DMA */
1148 if (ahci_sb600_enable_64bit(pdev))
1149 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1151 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1154 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1156 /* save initial config */
1157 ahci_pci_save_initial_config(pdev, hpriv);
1160 if (hpriv->cap & HOST_CAP_NCQ) {
1161 pi.flags |= ATA_FLAG_NCQ;
1163 * Auto-activate optimization is supposed to be
1164 * supported on all AHCI controllers indicating NCQ
1165 * capability, but it seems to be broken on some
1166 * chipsets including NVIDIAs.
1168 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1169 pi.flags |= ATA_FLAG_FPDMA_AA;
1172 if (hpriv->cap & HOST_CAP_PMP)
1173 pi.flags |= ATA_FLAG_PMP;
1175 ahci_set_em_messages(hpriv, &pi);
1177 if (ahci_broken_system_poweroff(pdev)) {
1178 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1179 dev_info(&pdev->dev,
1180 "quirky BIOS, skipping spindown on poweroff\n");
1183 if (ahci_broken_suspend(pdev)) {
1184 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1185 dev_warn(&pdev->dev,
1186 "BIOS update required for suspend/resume\n");
1189 if (ahci_broken_online(pdev)) {
1190 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1191 dev_info(&pdev->dev,
1192 "online status unreliable, applying workaround\n");
1195 /* CAP.NP sometimes indicate the index of the last enabled
1196 * port, at other times, that of the last possible port, so
1197 * determining the maximum port number requires looking at
1198 * both CAP.NP and port_map.
1200 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1202 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1205 host->private_data = hpriv;
1207 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1208 host->flags |= ATA_HOST_PARALLEL_SCAN;
1210 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1212 if (pi.flags & ATA_FLAG_EM)
1213 ahci_reset_em(host);
1215 for (i = 0; i < host->n_ports; i++) {
1216 struct ata_port *ap = host->ports[i];
1218 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1219 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1220 0x100 + ap->port_no * 0x80, "port");
1222 /* set enclosure management message type */
1223 if (ap->flags & ATA_FLAG_EM)
1224 ap->em_message_type = hpriv->em_msg_type;
1227 /* disabled/not-implemented port */
1228 if (!(hpriv->port_map & (1 << i)))
1229 ap->ops = &ata_dummy_port_ops;
1232 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1233 ahci_p5wdh_workaround(host);
1235 /* apply gtf filter quirk */
1236 ahci_gtf_filter_workaround(host);
1238 /* initialize adapter */
1239 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1243 rc = ahci_pci_reset_controller(host);
1247 ahci_pci_init_controller(host);
1248 ahci_pci_print_info(host);
1250 pci_set_master(pdev);
1251 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1255 static int __init ahci_init(void)
1257 return pci_register_driver(&ahci_pci_driver);
1260 static void __exit ahci_exit(void)
1262 pci_unregister_driver(&ahci_pci_driver);
1266 MODULE_AUTHOR("Jeff Garzik");
1267 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1268 MODULE_LICENSE("GPL");
1269 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1270 MODULE_VERSION(DRV_VERSION);
1272 module_init(ahci_init);
1273 module_exit(ahci_exit);