2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
59 /* board IDs by feature in alphabetical order */
65 /* board IDs for specific chipsets in alphabetical order */
71 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
87 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
88 static int ahci_pci_device_resume(struct pci_dev *pdev);
91 static struct scsi_host_template ahci_sht = {
95 static struct ata_port_operations ahci_vt8251_ops = {
96 .inherits = &ahci_ops,
97 .hardreset = ahci_vt8251_hardreset,
100 static struct ata_port_operations ahci_p5wdh_ops = {
101 .inherits = &ahci_ops,
102 .hardreset = ahci_p5wdh_hardreset,
105 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
107 static const struct ata_port_info ahci_port_info[] = {
111 .flags = AHCI_FLAG_COMMON,
112 .pio_mask = ATA_PIO4,
113 .udma_mask = ATA_UDMA6,
114 .port_ops = &ahci_ops,
116 [board_ahci_ign_iferr] =
118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
124 [board_ahci_nosntf] =
126 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
132 [board_ahci_yes_fbs] =
134 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
143 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
145 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
152 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
169 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
170 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_pmp_retry_srst_ops,
185 [board_ahci_sb700] = /* for SB700 and SB800 */
187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_pmp_retry_srst_ops,
193 [board_ahci_vt8251] =
195 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_vt8251_ops,
203 static const struct pci_device_id ahci_pci_tbl[] = {
205 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
206 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
207 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
208 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
209 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
210 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
211 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
215 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
220 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
234 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
236 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
237 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
239 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
242 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
244 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
252 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
255 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
263 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
264 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
265 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
268 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
269 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
270 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
277 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
278 /* AMD is using RAID class only for ahci controllers */
279 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
280 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
283 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
284 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
287 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
288 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
296 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
308 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
324 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
360 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
374 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
375 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
378 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
379 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
380 { PCI_DEVICE(0x1b4b, 0x9123),
381 .class = PCI_CLASS_STORAGE_SATA_AHCI,
382 .class_mask = 0xffffff,
383 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
384 { PCI_DEVICE(0x1b4b, 0x9125),
385 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
386 { PCI_DEVICE(0x1b4b, 0x91a3),
387 .driver_data = board_ahci_yes_fbs },
390 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
392 /* Generic, PCI class code for AHCI */
393 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
394 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
396 { } /* terminate list */
400 static struct pci_driver ahci_pci_driver = {
402 .id_table = ahci_pci_tbl,
403 .probe = ahci_init_one,
404 .remove = ata_pci_remove_one,
406 .suspend = ahci_pci_device_suspend,
407 .resume = ahci_pci_device_resume,
411 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
412 static int marvell_enable;
414 static int marvell_enable = 1;
416 module_param(marvell_enable, int, 0644);
417 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
420 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
421 struct ahci_host_priv *hpriv)
423 unsigned int force_port_map = 0;
424 unsigned int mask_port_map = 0;
426 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
427 dev_info(&pdev->dev, "JMB361 has only one port\n");
432 * Temporary Marvell 6145 hack: PATA port presence
433 * is asserted through the standard AHCI port
434 * presence register, as bit 4 (counting from 0)
436 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
437 if (pdev->device == 0x6121)
442 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
445 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
449 static int ahci_pci_reset_controller(struct ata_host *host)
451 struct pci_dev *pdev = to_pci_dev(host->dev);
453 ahci_reset_controller(host);
455 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
456 struct ahci_host_priv *hpriv = host->private_data;
460 pci_read_config_word(pdev, 0x92, &tmp16);
461 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
462 tmp16 |= hpriv->port_map;
463 pci_write_config_word(pdev, 0x92, tmp16);
470 static void ahci_pci_init_controller(struct ata_host *host)
472 struct ahci_host_priv *hpriv = host->private_data;
473 struct pci_dev *pdev = to_pci_dev(host->dev);
474 void __iomem *port_mmio;
478 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
479 if (pdev->device == 0x6121)
483 port_mmio = __ahci_port_base(host, mv);
485 writel(0, port_mmio + PORT_IRQ_MASK);
488 tmp = readl(port_mmio + PORT_IRQ_STAT);
489 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
491 writel(tmp, port_mmio + PORT_IRQ_STAT);
494 ahci_init_controller(host);
497 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
498 unsigned long deadline)
500 struct ata_port *ap = link->ap;
506 ahci_stop_engine(ap);
508 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
509 deadline, &online, NULL);
511 ahci_start_engine(ap);
513 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
515 /* vt8251 doesn't clear BSY on signature FIS reception,
516 * request follow-up softreset.
518 return online ? -EAGAIN : rc;
521 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
522 unsigned long deadline)
524 struct ata_port *ap = link->ap;
525 struct ahci_port_priv *pp = ap->private_data;
526 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
527 struct ata_taskfile tf;
531 ahci_stop_engine(ap);
533 /* clear D2H reception area to properly wait for D2H FIS */
534 ata_tf_init(link->device, &tf);
536 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
538 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
539 deadline, &online, NULL);
541 ahci_start_engine(ap);
543 /* The pseudo configuration device on SIMG4726 attached to
544 * ASUS P5W-DH Deluxe doesn't send signature FIS after
545 * hardreset if no device is attached to the first downstream
546 * port && the pseudo device locks up on SRST w/ PMP==0. To
547 * work around this, wait for !BSY only briefly. If BSY isn't
548 * cleared, perform CLO and proceed to IDENTIFY (achieved by
549 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
551 * Wait for two seconds. Devices attached to downstream port
552 * which can't process the following IDENTIFY after this will
553 * have to be reset again. For most cases, this should
554 * suffice while making probing snappish enough.
557 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
560 ahci_kick_engine(ap);
566 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
568 struct ata_host *host = dev_get_drvdata(&pdev->dev);
569 struct ahci_host_priv *hpriv = host->private_data;
570 void __iomem *mmio = hpriv->mmio;
573 if (mesg.event & PM_EVENT_SUSPEND &&
574 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
576 "BIOS update required for suspend/resume\n");
580 if (mesg.event & PM_EVENT_SLEEP) {
581 /* AHCI spec rev1.1 section 8.3.3:
582 * Software must disable interrupts prior to requesting a
583 * transition of the HBA to D3 state.
585 ctl = readl(mmio + HOST_CTL);
587 writel(ctl, mmio + HOST_CTL);
588 readl(mmio + HOST_CTL); /* flush */
591 return ata_pci_device_suspend(pdev, mesg);
594 static int ahci_pci_device_resume(struct pci_dev *pdev)
596 struct ata_host *host = dev_get_drvdata(&pdev->dev);
599 rc = ata_pci_device_do_resume(pdev);
603 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
604 rc = ahci_pci_reset_controller(host);
608 ahci_pci_init_controller(host);
611 ata_host_resume(host);
617 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
622 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
623 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
625 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
628 "64-bit DMA enable failed\n");
633 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
635 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
638 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
641 "32-bit consistent DMA enable failed\n");
648 static void ahci_pci_print_info(struct ata_host *host)
650 struct pci_dev *pdev = to_pci_dev(host->dev);
654 pci_read_config_word(pdev, 0x0a, &cc);
655 if (cc == PCI_CLASS_STORAGE_IDE)
657 else if (cc == PCI_CLASS_STORAGE_SATA)
659 else if (cc == PCI_CLASS_STORAGE_RAID)
664 ahci_print_info(host, scc_s);
667 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
668 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
669 * support PMP and the 4726 either directly exports the device
670 * attached to the first downstream port or acts as a hardware storage
671 * controller and emulate a single ATA device (can be RAID 0/1 or some
672 * other configuration).
674 * When there's no device attached to the first downstream port of the
675 * 4726, "Config Disk" appears, which is a pseudo ATA device to
676 * configure the 4726. However, ATA emulation of the device is very
677 * lame. It doesn't send signature D2H Reg FIS after the initial
678 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
680 * The following function works around the problem by always using
681 * hardreset on the port and not depending on receiving signature FIS
682 * afterward. If signature FIS isn't received soon, ATA class is
683 * assumed without follow-up softreset.
685 static void ahci_p5wdh_workaround(struct ata_host *host)
687 static struct dmi_system_id sysids[] = {
689 .ident = "P5W DH Deluxe",
691 DMI_MATCH(DMI_SYS_VENDOR,
692 "ASUSTEK COMPUTER INC"),
693 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
698 struct pci_dev *pdev = to_pci_dev(host->dev);
700 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
701 dmi_check_system(sysids)) {
702 struct ata_port *ap = host->ports[1];
705 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
707 ap->ops = &ahci_p5wdh_ops;
708 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
712 /* only some SB600 ahci controllers can do 64bit DMA */
713 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
715 static const struct dmi_system_id sysids[] = {
717 * The oldest version known to be broken is 0901 and
718 * working is 1501 which was released on 2007-10-26.
719 * Enable 64bit DMA on 1501 and anything newer.
721 * Please read bko#9412 for more info.
724 .ident = "ASUS M2A-VM",
726 DMI_MATCH(DMI_BOARD_VENDOR,
727 "ASUSTeK Computer INC."),
728 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
730 .driver_data = "20071026", /* yyyymmdd */
733 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
736 * BIOS versions earlier than 1.5 had the Manufacturer DMI
737 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
738 * This spelling mistake was fixed in BIOS version 1.5, so
739 * 1.5 and later have the Manufacturer as
740 * "MICRO-STAR INTERNATIONAL CO.,LTD".
741 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
743 * BIOS versions earlier than 1.9 had a Board Product Name
744 * DMI field of "MS-7376". This was changed to be
745 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
746 * match on DMI_BOARD_NAME of "MS-7376".
749 .ident = "MSI K9A2 Platinum",
751 DMI_MATCH(DMI_BOARD_VENDOR,
753 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
757 * All BIOS versions for the Asus M3A support 64bit DMA.
758 * (all release versions from 0301 to 1206 were tested)
763 DMI_MATCH(DMI_BOARD_VENDOR,
764 "ASUSTeK Computer INC."),
765 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
770 const struct dmi_system_id *match;
771 int year, month, date;
774 match = dmi_first_match(sysids);
775 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
779 if (!match->driver_data)
782 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
783 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
785 if (strcmp(buf, match->driver_data) >= 0)
789 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
795 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
799 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
801 static const struct dmi_system_id broken_systems[] = {
803 .ident = "HP Compaq nx6310",
805 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
806 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
808 /* PCI slot number of the controller */
809 .driver_data = (void *)0x1FUL,
812 .ident = "HP Compaq 6720s",
814 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
815 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
817 /* PCI slot number of the controller */
818 .driver_data = (void *)0x1FUL,
821 { } /* terminate list */
823 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
826 unsigned long slot = (unsigned long)dmi->driver_data;
827 /* apply the quirk only to on-board controllers */
828 return slot == PCI_SLOT(pdev->devfn);
834 static bool ahci_broken_suspend(struct pci_dev *pdev)
836 static const struct dmi_system_id sysids[] = {
838 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
839 * to the harddisk doesn't become online after
840 * resuming from STR. Warn and fail suspend.
842 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
844 * Use dates instead of versions to match as HP is
845 * apparently recycling both product and version
848 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
853 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
854 DMI_MATCH(DMI_PRODUCT_NAME,
855 "HP Pavilion dv4 Notebook PC"),
857 .driver_data = "20090105", /* F.30 */
862 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
863 DMI_MATCH(DMI_PRODUCT_NAME,
864 "HP Pavilion dv5 Notebook PC"),
866 .driver_data = "20090506", /* F.16 */
871 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
872 DMI_MATCH(DMI_PRODUCT_NAME,
873 "HP Pavilion dv6 Notebook PC"),
875 .driver_data = "20090423", /* F.21 */
880 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
881 DMI_MATCH(DMI_PRODUCT_NAME,
882 "HP HDX18 Notebook PC"),
884 .driver_data = "20090430", /* F.23 */
887 * Acer eMachines G725 has the same problem. BIOS
888 * V1.03 is known to be broken. V3.04 is known to
889 * work. Between, there are V1.06, V2.06 and V3.03
890 * that we don't have much idea about. For now,
891 * blacklist anything older than V3.04.
893 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
898 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
899 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
901 .driver_data = "20091216", /* V3.04 */
903 { } /* terminate list */
905 const struct dmi_system_id *dmi = dmi_first_match(sysids);
906 int year, month, date;
909 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
912 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
913 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
915 return strcmp(buf, dmi->driver_data) < 0;
918 static bool ahci_broken_online(struct pci_dev *pdev)
920 #define ENCODE_BUSDEVFN(bus, slot, func) \
921 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
922 static const struct dmi_system_id sysids[] = {
924 * There are several gigabyte boards which use
925 * SIMG5723s configured as hardware RAID. Certain
926 * 5723 firmware revisions shipped there keep the link
927 * online but fail to answer properly to SRST or
928 * IDENTIFY when no device is attached downstream
929 * causing libata to retry quite a few times leading
930 * to excessive detection delay.
932 * As these firmwares respond to the second reset try
933 * with invalid device signature, considering unknown
934 * sig as offline works around the problem acceptably.
939 DMI_MATCH(DMI_BOARD_VENDOR,
940 "Gigabyte Technology Co., Ltd."),
941 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
943 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
948 DMI_MATCH(DMI_BOARD_VENDOR,
949 "Gigabyte Technology Co., Ltd."),
950 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
952 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
954 { } /* terminate list */
956 #undef ENCODE_BUSDEVFN
957 const struct dmi_system_id *dmi = dmi_first_match(sysids);
963 val = (unsigned long)dmi->driver_data;
965 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
968 #ifdef CONFIG_ATA_ACPI
969 static void ahci_gtf_filter_workaround(struct ata_host *host)
971 static const struct dmi_system_id sysids[] = {
973 * Aspire 3810T issues a bunch of SATA enable commands
974 * via _GTF including an invalid one and one which is
975 * rejected by the device. Among the successful ones
976 * is FPDMA non-zero offset enable which when enabled
977 * only on the drive side leads to NCQ command
978 * failures. Filter it out.
981 .ident = "Aspire 3810T",
983 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
984 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
986 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
990 const struct dmi_system_id *dmi = dmi_first_match(sysids);
997 filter = (unsigned long)dmi->driver_data;
998 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1001 for (i = 0; i < host->n_ports; i++) {
1002 struct ata_port *ap = host->ports[i];
1003 struct ata_link *link;
1004 struct ata_device *dev;
1006 ata_for_each_link(link, ap, EDGE)
1007 ata_for_each_dev(dev, link, ALL)
1008 dev->gtf_filter |= filter;
1012 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1016 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1018 unsigned int board_id = ent->driver_data;
1019 struct ata_port_info pi = ahci_port_info[board_id];
1020 const struct ata_port_info *ppi[] = { &pi, NULL };
1021 struct device *dev = &pdev->dev;
1022 struct ahci_host_priv *hpriv;
1023 struct ata_host *host;
1028 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1030 ata_print_version_once(&pdev->dev, DRV_VERSION);
1032 /* The AHCI driver can only drive the SATA ports, the PATA driver
1033 can drive them all so if both drivers are selected make sure
1034 AHCI stays out of the way */
1035 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1039 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1040 * ahci, use ata_generic instead.
1042 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1043 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1044 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1045 pdev->subsystem_device == 0xcb89)
1048 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1049 * At the moment, we can only use the AHCI mode. Let the users know
1050 * that for SAS drives they're out of luck.
1052 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1053 dev_info(&pdev->dev,
1054 "PDC42819 can only drive SATA devices with this driver\n");
1056 /* acquire resources */
1057 rc = pcim_enable_device(pdev);
1061 /* AHCI controllers often implement SFF compatible interface.
1062 * Grab all PCI BARs just in case.
1064 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1066 pcim_pin_device(pdev);
1070 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1071 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1074 /* ICH6s share the same PCI ID for both piix and ahci
1075 * modes. Enabling ahci mode while MAP indicates
1076 * combined mode is a bad idea. Yield to ata_piix.
1078 pci_read_config_byte(pdev, ICH_MAP, &map);
1080 dev_info(&pdev->dev,
1081 "controller is in combined mode, can't enable AHCI mode\n");
1086 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1089 hpriv->flags |= (unsigned long)pi.private_data;
1091 /* MCP65 revision A1 and A2 can't do MSI */
1092 if (board_id == board_ahci_mcp65 &&
1093 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1094 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1096 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1097 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1098 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1100 /* only some SB600s can do 64bit DMA */
1101 if (ahci_sb600_enable_64bit(pdev))
1102 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1104 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1107 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1109 /* save initial config */
1110 ahci_pci_save_initial_config(pdev, hpriv);
1113 if (hpriv->cap & HOST_CAP_NCQ) {
1114 pi.flags |= ATA_FLAG_NCQ;
1116 * Auto-activate optimization is supposed to be
1117 * supported on all AHCI controllers indicating NCQ
1118 * capability, but it seems to be broken on some
1119 * chipsets including NVIDIAs.
1121 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1122 pi.flags |= ATA_FLAG_FPDMA_AA;
1125 if (hpriv->cap & HOST_CAP_PMP)
1126 pi.flags |= ATA_FLAG_PMP;
1128 ahci_set_em_messages(hpriv, &pi);
1130 if (ahci_broken_system_poweroff(pdev)) {
1131 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1132 dev_info(&pdev->dev,
1133 "quirky BIOS, skipping spindown on poweroff\n");
1136 if (ahci_broken_suspend(pdev)) {
1137 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1138 dev_warn(&pdev->dev,
1139 "BIOS update required for suspend/resume\n");
1142 if (ahci_broken_online(pdev)) {
1143 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1144 dev_info(&pdev->dev,
1145 "online status unreliable, applying workaround\n");
1148 /* CAP.NP sometimes indicate the index of the last enabled
1149 * port, at other times, that of the last possible port, so
1150 * determining the maximum port number requires looking at
1151 * both CAP.NP and port_map.
1153 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1155 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1158 host->private_data = hpriv;
1160 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1161 host->flags |= ATA_HOST_PARALLEL_SCAN;
1163 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1165 if (pi.flags & ATA_FLAG_EM)
1166 ahci_reset_em(host);
1168 for (i = 0; i < host->n_ports; i++) {
1169 struct ata_port *ap = host->ports[i];
1171 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1172 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1173 0x100 + ap->port_no * 0x80, "port");
1175 /* set enclosure management message type */
1176 if (ap->flags & ATA_FLAG_EM)
1177 ap->em_message_type = hpriv->em_msg_type;
1180 /* disabled/not-implemented port */
1181 if (!(hpriv->port_map & (1 << i)))
1182 ap->ops = &ata_dummy_port_ops;
1185 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1186 ahci_p5wdh_workaround(host);
1188 /* apply gtf filter quirk */
1189 ahci_gtf_filter_workaround(host);
1191 /* initialize adapter */
1192 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1196 rc = ahci_pci_reset_controller(host);
1200 ahci_pci_init_controller(host);
1201 ahci_pci_print_info(host);
1203 pci_set_master(pdev);
1204 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1208 static int __init ahci_init(void)
1210 return pci_register_driver(&ahci_pci_driver);
1213 static void __exit ahci_exit(void)
1215 pci_unregister_driver(&ahci_pci_driver);
1219 MODULE_AUTHOR("Jeff Garzik");
1220 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1221 MODULE_LICENSE("GPL");
1222 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1223 MODULE_VERSION(DRV_VERSION);
1225 module_init(ahci_init);
1226 module_exit(ahci_exit);