Pileus Git - ~andy/linux/blob - drivers/amba/tegra-ahb.c

   1 /*
   2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3  * Copyright (C) 2011 Google, Inc.
   4  *
   5  * Author:
   6  *      Jay Cheng <jacheng@nvidia.com>
   7  *      James Wylder <james.wylder@motorola.com>
   8  *      Benoit Goby <benoit@android.com>
   9  *      Colin Cross <ccross@android.com>
  10  *      Hiroshi DOYU <hdoyu@nvidia.com>
  11  *
  12  * This software is licensed under the terms of the GNU General Public
  13  * License version 2, as published by the Free Software Foundation, and
  14  * may be copied, distributed, and modified under those terms.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/io.h>
  27 #include <linux/tegra-ahb.h>
  28
  29 #define DRV_NAME "tegra-ahb"
  30
  31 #define AHB_ARBITRATION_DISABLE         0x00
  32 #define AHB_ARBITRATION_PRIORITY_CTRL   0x04
  33 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
  34 #define   PRIORITY_SELECT_USB BIT(6)
  35 #define   PRIORITY_SELECT_USB2 BIT(18)
  36 #define   PRIORITY_SELECT_USB3 BIT(17)
  37
  38 #define AHB_GIZMO_AHB_MEM               0x0c
  39 #define   ENB_FAST_REARBITRATE BIT(2)
  40 #define   DONT_SPLIT_AHB_WR     BIT(7)
  41
  42 #define AHB_GIZMO_APB_DMA               0x10
  43 #define AHB_GIZMO_IDE                   0x18
  44 #define AHB_GIZMO_USB                   0x1c
  45 #define AHB_GIZMO_AHB_XBAR_BRIDGE       0x20
  46 #define AHB_GIZMO_CPU_AHB_BRIDGE        0x24
  47 #define AHB_GIZMO_COP_AHB_BRIDGE        0x28
  48 #define AHB_GIZMO_XBAR_APB_CTLR         0x2c
  49 #define AHB_GIZMO_VCP_AHB_BRIDGE        0x30
  50 #define AHB_GIZMO_NAND                  0x3c
  51 #define AHB_GIZMO_SDMMC4                0x44
  52 #define AHB_GIZMO_XIO                   0x48
  53 #define AHB_GIZMO_BSEV                  0x60
  54 #define AHB_GIZMO_BSEA                  0x70
  55 #define AHB_GIZMO_NOR                   0x74
  56 #define AHB_GIZMO_USB2                  0x78
  57 #define AHB_GIZMO_USB3                  0x7c
  58 #define   IMMEDIATE     BIT(18)
  59
  60 #define AHB_GIZMO_SDMMC1                0x80
  61 #define AHB_GIZMO_SDMMC2                0x84
  62 #define AHB_GIZMO_SDMMC3                0x88
  63 #define AHB_MEM_PREFETCH_CFG_X          0xd8
  64 #define AHB_ARBITRATION_XBAR_CTRL       0xdc
  65 #define AHB_MEM_PREFETCH_CFG3           0xe0
  66 #define AHB_MEM_PREFETCH_CFG4           0xe4
  67 #define AHB_MEM_PREFETCH_CFG1           0xec
  68 #define AHB_MEM_PREFETCH_CFG2           0xf0
  69 #define   PREFETCH_ENB  BIT(31)
  70 #define   MST_ID(x)     (((x) & 0x1f) << 26)
  71 #define   AHBDMA_MST_ID MST_ID(5)
  72 #define   USB_MST_ID    MST_ID(6)
  73 #define   USB2_MST_ID   MST_ID(18)
  74 #define   USB3_MST_ID   MST_ID(17)
  75 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
  76 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
  77
  78 #define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID    0xf8
  79
  80 #define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
  81
  82 static struct platform_driver tegra_ahb_driver;
  83
  84 static const u32 tegra_ahb_gizmo[] = {
  85         AHB_ARBITRATION_DISABLE,
  86         AHB_ARBITRATION_PRIORITY_CTRL,
  87         AHB_GIZMO_AHB_MEM,
  88         AHB_GIZMO_APB_DMA,
  89         AHB_GIZMO_IDE,
  90         AHB_GIZMO_USB,
  91         AHB_GIZMO_AHB_XBAR_BRIDGE,
  92         AHB_GIZMO_CPU_AHB_BRIDGE,
  93         AHB_GIZMO_COP_AHB_BRIDGE,
  94         AHB_GIZMO_XBAR_APB_CTLR,
  95         AHB_GIZMO_VCP_AHB_BRIDGE,
  96         AHB_GIZMO_NAND,
  97         AHB_GIZMO_SDMMC4,
  98         AHB_GIZMO_XIO,
  99         AHB_GIZMO_BSEV,
 100         AHB_GIZMO_BSEA,
 101         AHB_GIZMO_NOR,
 102         AHB_GIZMO_USB2,
 103         AHB_GIZMO_USB3,
 104         AHB_GIZMO_SDMMC1,
 105         AHB_GIZMO_SDMMC2,
 106         AHB_GIZMO_SDMMC3,
 107         AHB_MEM_PREFETCH_CFG_X,
 108         AHB_ARBITRATION_XBAR_CTRL,
 109         AHB_MEM_PREFETCH_CFG3,
 110         AHB_MEM_PREFETCH_CFG4,
 111         AHB_MEM_PREFETCH_CFG1,
 112         AHB_MEM_PREFETCH_CFG2,
 113         AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
 114 };
 115
 116 struct tegra_ahb {
 117         void __iomem    *regs;
 118         struct device   *dev;
 119         u32             ctx[0];
 120 };
 121
 122 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
 123 {
 124         return readl(ahb->regs + offset);
 125 }
 126
 127 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
 128 {
 129         writel(value, ahb->regs + offset);
 130 }
 131
 132 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 133 static int tegra_ahb_match_by_smmu(struct device *dev, void *data)
 134 {
 135         struct tegra_ahb *ahb = dev_get_drvdata(dev);
 136         struct device_node *dn = data;
 137
 138         return (ahb->dev->of_node == dn) ? 1 : 0;
 139 }
 140
 141 int tegra_ahb_enable_smmu(struct device_node *dn)
 142 {
 143         struct device *dev;
 144         u32 val;
 145         struct tegra_ahb *ahb;
 146
 147         dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn,
 148                                  tegra_ahb_match_by_smmu);
 149         if (!dev)
 150                 return -EPROBE_DEFER;
 151         ahb = dev_get_drvdata(dev);
 152         val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
 153         val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
 154         gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
 155         return 0;
 156 }
 157 EXPORT_SYMBOL(tegra_ahb_enable_smmu);
 158 #endif
 159
 160 static int tegra_ahb_suspend(struct device *dev)
 161 {
 162         int i;
 163         struct tegra_ahb *ahb = dev_get_drvdata(dev);
 164
 165         for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
 166                 ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
 167         return 0;
 168 }
 169
 170 static int tegra_ahb_resume(struct device *dev)
 171 {
 172         int i;
 173         struct tegra_ahb *ahb = dev_get_drvdata(dev);
 174
 175         for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
 176                 gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
 177         return 0;
 178 }
 179
 180 static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
 181                             tegra_ahb_suspend,
 182                             tegra_ahb_resume, NULL);
 183
 184 static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
 185 {
 186         u32 val;
 187
 188         val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
 189         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
 190         gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
 191
 192         val = gizmo_readl(ahb, AHB_GIZMO_USB);
 193         val |= IMMEDIATE;
 194         gizmo_writel(ahb, val, AHB_GIZMO_USB);
 195
 196         val = gizmo_readl(ahb, AHB_GIZMO_USB2);
 197         val |= IMMEDIATE;
 198         gizmo_writel(ahb, val, AHB_GIZMO_USB2);
 199
 200         val = gizmo_readl(ahb, AHB_GIZMO_USB3);
 201         val |= IMMEDIATE;
 202         gizmo_writel(ahb, val, AHB_GIZMO_USB3);
 203
 204         val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
 205         val |= PRIORITY_SELECT_USB |
 206                 PRIORITY_SELECT_USB2 |
 207                 PRIORITY_SELECT_USB3 |
 208                 AHB_PRIORITY_WEIGHT(7);
 209         gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
 210
 211         val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
 212         val &= ~MST_ID(~0);
 213         val |= PREFETCH_ENB |
 214                 AHBDMA_MST_ID |
 215                 ADDR_BNDRY(0xc) |
 216                 INACTIVITY_TIMEOUT(0x1000);
 217         gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
 218
 219         val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
 220         val &= ~MST_ID(~0);
 221         val |= PREFETCH_ENB |
 222                 USB_MST_ID |
 223                 ADDR_BNDRY(0xc) |
 224                 INACTIVITY_TIMEOUT(0x1000);
 225         gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
 226
 227         val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
 228         val &= ~MST_ID(~0);
 229         val |= PREFETCH_ENB |
 230                 USB3_MST_ID |
 231                 ADDR_BNDRY(0xc) |
 232                 INACTIVITY_TIMEOUT(0x1000);
 233         gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
 234
 235         val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
 236         val &= ~MST_ID(~0);
 237         val |= PREFETCH_ENB |
 238                 USB2_MST_ID |
 239                 ADDR_BNDRY(0xc) |
 240                 INACTIVITY_TIMEOUT(0x1000);
 241         gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
 242 }
 243
 244 static int __devinit tegra_ahb_probe(struct platform_device *pdev)
 245 {
 246         struct resource *res;
 247         struct tegra_ahb *ahb;
 248         size_t bytes;
 249
 250         bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
 251         ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
 252         if (!ahb)
 253                 return -ENOMEM;
 254
 255         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 256         if (!res)
 257                 return -ENODEV;
 258         ahb->regs = devm_request_and_ioremap(&pdev->dev, res);
 259         if (!ahb->regs)
 260                 return -EBUSY;
 261
 262         ahb->dev = &pdev->dev;
 263         platform_set_drvdata(pdev, ahb);
 264         tegra_ahb_gizmo_init(ahb);
 265         return 0;
 266 }
 267
 268 static const struct of_device_id tegra_ahb_of_match[] __devinitconst = {
 269         { .compatible = "nvidia,tegra30-ahb", },
 270         { .compatible = "nvidia,tegra20-ahb", },
 271         {},
 272 };
 273
 274 static struct platform_driver tegra_ahb_driver = {
 275         .probe = tegra_ahb_probe,
 276         .driver = {
 277                 .name = DRV_NAME,
 278                 .owner = THIS_MODULE,
 279                 .of_match_table = tegra_ahb_of_match,
 280                 .pm = &tegra_ahb_pm,
 281         },
 282 };
 283 module_platform_driver(tegra_ahb_driver);
 284
 285 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
 286 MODULE_DESCRIPTION("Tegra AHB driver");
 287 MODULE_LICENSE("GPL v2");
 288 MODULE_ALIAS("platform:" DRV_NAME);