2 * processor_idle - idle state submodule to the ACPI processor driver
4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
6 * Copyright (C) 2004 Dominik Brodowski <linux@brodo.de>
7 * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
8 * - Added processor hotplug support
9 * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
10 * - Added support for C3 on SMP
12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or (at
17 * your option) any later version.
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 * General Public License for more details.
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/init.h>
34 #include <linux/cpufreq.h>
35 #include <linux/proc_fs.h>
36 #include <linux/seq_file.h>
37 #include <linux/acpi.h>
38 #include <linux/dmi.h>
39 #include <linux/moduleparam.h>
40 #include <linux/sched.h> /* need_resched() */
43 #include <asm/uaccess.h>
45 #include <acpi/acpi_bus.h>
46 #include <acpi/processor.h>
48 #define ACPI_PROCESSOR_COMPONENT 0x01000000
49 #define ACPI_PROCESSOR_CLASS "processor"
50 #define ACPI_PROCESSOR_DRIVER_NAME "ACPI Processor Driver"
51 #define _COMPONENT ACPI_PROCESSOR_COMPONENT
52 ACPI_MODULE_NAME("acpi_processor")
53 #define ACPI_PROCESSOR_FILE_POWER "power"
54 #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000)
55 #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */
56 #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */
57 static void (*pm_idle_save) (void) __read_mostly;
58 module_param(max_cstate, uint, 0644);
60 static unsigned int nocst __read_mostly;
61 module_param(nocst, uint, 0000);
64 * bm_history -- bit-mask with a bit per jiffy of bus-master activity
65 * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms
66 * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms
67 * 100 HZ: 0x0000000F: 4 jiffies = 40ms
68 * reduce history for more aggressive entry into C3
70 static unsigned int bm_history __read_mostly =
71 (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1));
72 module_param(bm_history, uint, 0644);
73 /* --------------------------------------------------------------------------
75 -------------------------------------------------------------------------- */
78 * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
79 * For now disable this. Probably a bug somewhere else.
81 * To skip this limit, boot/load with a large max_cstate limit.
83 static int set_max_cstate(struct dmi_system_id *id)
85 if (max_cstate > ACPI_PROCESSOR_MAX_POWER)
88 printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate."
89 " Override with \"processor.max_cstate=%d\"\n", id->ident,
90 (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1);
92 max_cstate = (long)id->driver_data;
97 /* Actually this shouldn't be __cpuinitdata, would be better to fix the
98 callers to only run once -AK */
99 static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = {
100 { set_max_cstate, "IBM ThinkPad R40e", {
101 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
102 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1},
103 { set_max_cstate, "IBM ThinkPad R40e", {
104 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
105 DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1},
106 { set_max_cstate, "IBM ThinkPad R40e", {
107 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
108 DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1},
109 { set_max_cstate, "IBM ThinkPad R40e", {
110 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
111 DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1},
112 { set_max_cstate, "IBM ThinkPad R40e", {
113 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
114 DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1},
115 { set_max_cstate, "IBM ThinkPad R40e", {
116 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
117 DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1},
118 { set_max_cstate, "IBM ThinkPad R40e", {
119 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
120 DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1},
121 { set_max_cstate, "IBM ThinkPad R40e", {
122 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
123 DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1},
124 { set_max_cstate, "IBM ThinkPad R40e", {
125 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
126 DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1},
127 { set_max_cstate, "IBM ThinkPad R40e", {
128 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
129 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1},
130 { set_max_cstate, "IBM ThinkPad R40e", {
131 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
132 DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1},
133 { set_max_cstate, "IBM ThinkPad R40e", {
134 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
135 DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1},
136 { set_max_cstate, "IBM ThinkPad R40e", {
137 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
138 DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1},
139 { set_max_cstate, "IBM ThinkPad R40e", {
140 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
141 DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1},
142 { set_max_cstate, "IBM ThinkPad R40e", {
143 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
144 DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1},
145 { set_max_cstate, "Medion 41700", {
146 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
147 DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1},
148 { set_max_cstate, "Clevo 5600D", {
149 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
150 DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")},
155 static inline u32 ticks_elapsed(u32 t1, u32 t2)
159 else if (!acpi_fadt.tmr_val_ext)
160 return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
162 return ((0xFFFFFFFF - t1) + t2);
166 acpi_processor_power_activate(struct acpi_processor *pr,
167 struct acpi_processor_cx *new)
169 struct acpi_processor_cx *old;
174 old = pr->power.state;
177 old->promotion.count = 0;
178 new->demotion.count = 0;
180 /* Cleanup from old state. */
184 /* Disable bus master reload */
185 if (new->type != ACPI_STATE_C3 && pr->flags.bm_check)
186 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0,
187 ACPI_MTX_DO_NOT_LOCK);
192 /* Prepare to use new state. */
195 /* Enable bus master reload */
196 if (old->type != ACPI_STATE_C3 && pr->flags.bm_check)
197 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1,
198 ACPI_MTX_DO_NOT_LOCK);
202 pr->power.state = new;
207 static void acpi_safe_halt(void)
209 current_thread_info()->status &= ~TS_POLLING;
210 smp_mb__after_clear_bit();
213 current_thread_info()->status |= TS_POLLING;
216 static atomic_t c3_cpu_count;
218 static void acpi_processor_idle(void)
220 struct acpi_processor *pr = NULL;
221 struct acpi_processor_cx *cx = NULL;
222 struct acpi_processor_cx *next_state = NULL;
226 pr = processors[smp_processor_id()];
231 * Interrupts must be disabled during bus mastering calculations and
232 * for C2/C3 transitions.
237 * Check whether we truly need to go idle, or should
240 if (unlikely(need_resched())) {
245 cx = pr->power.state;
257 * Check for bus mastering activity (if required), record, and check
260 if (pr->flags.bm_check) {
262 unsigned long diff = jiffies - pr->power.bm_check_timestamp;
268 /* if we didn't get called, assume there was busmaster activity */
271 pr->power.bm_activity |= 0x1;
272 pr->power.bm_activity <<= 1;
275 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS,
276 &bm_status, ACPI_MTX_DO_NOT_LOCK);
278 pr->power.bm_activity++;
279 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS,
280 1, ACPI_MTX_DO_NOT_LOCK);
283 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
284 * the true state of bus mastering activity; forcing us to
285 * manually check the BMIDEA bit of each IDE channel.
287 else if (errata.piix4.bmisx) {
288 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
289 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
290 pr->power.bm_activity++;
293 pr->power.bm_check_timestamp = jiffies;
296 * Apply bus mastering demotion policy. Automatically demote
297 * to avoid a faulty transition. Note that the processor
298 * won't enter a low-power state during this call (to this
299 * funciton) but should upon the next.
301 * TBD: A better policy might be to fallback to the demotion
302 * state (use it for this quantum only) istead of
303 * demoting -- and rely on duration as our sole demotion
304 * qualification. This may, however, introduce DMA
305 * issues (e.g. floppy DMA transfer overrun/underrun).
307 if (pr->power.bm_activity & cx->demotion.threshold.bm) {
309 next_state = cx->demotion.state;
314 #ifdef CONFIG_HOTPLUG_CPU
316 * Check for P_LVL2_UP flag before entering C2 and above on
317 * an SMP system. We do it here instead of doing it at _CST/P_LVL
318 * detection phase, to work cleanly with logical CPU hotplug.
320 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
321 !pr->flags.has_cst && !acpi_fadt.plvl2_up)
322 cx = &pr->power.states[ACPI_STATE_C1];
330 * Invoke the current Cx state to put the processor to sleep.
332 if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) {
333 current_thread_info()->status &= ~TS_POLLING;
334 smp_mb__after_clear_bit();
335 if (need_resched()) {
336 current_thread_info()->status |= TS_POLLING;
347 * Use the appropriate idle routine, the one that would
348 * be used without acpi C-states.
356 * TBD: Can't get time duration while in C1, as resumes
357 * go to an ISR rather than here. Need to instrument
358 * base interrupt handler.
360 sleep_ticks = 0xFFFFFFFF;
364 /* Get start time (ticks) */
365 t1 = inl(acpi_fadt.xpm_tmr_blk.address);
368 /* Dummy wait op - must do something useless after P_LVL2 read
369 because chipsets cannot guarantee that STPCLK# signal
370 gets asserted in time to freeze execution properly. */
371 t2 = inl(acpi_fadt.xpm_tmr_blk.address);
372 /* Get end time (ticks) */
373 t2 = inl(acpi_fadt.xpm_tmr_blk.address);
375 #ifdef CONFIG_GENERIC_TIME
376 /* TSC halts in C2, so notify users */
379 /* Re-enable interrupts */
381 current_thread_info()->status |= TS_POLLING;
382 /* Compute time (ticks) that we were actually asleep */
384 ticks_elapsed(t1, t2) - cx->latency_ticks - C2_OVERHEAD;
389 if (pr->flags.bm_check) {
390 if (atomic_inc_return(&c3_cpu_count) ==
393 * All CPUs are trying to go to C3
394 * Disable bus master arbitration
396 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1,
397 ACPI_MTX_DO_NOT_LOCK);
400 /* SMP with no shared cache... Invalidate cache */
401 ACPI_FLUSH_CPU_CACHE();
404 /* Get start time (ticks) */
405 t1 = inl(acpi_fadt.xpm_tmr_blk.address);
408 /* Dummy wait op (see above) */
409 t2 = inl(acpi_fadt.xpm_tmr_blk.address);
410 /* Get end time (ticks) */
411 t2 = inl(acpi_fadt.xpm_tmr_blk.address);
412 if (pr->flags.bm_check) {
413 /* Enable bus master arbitration */
414 atomic_dec(&c3_cpu_count);
415 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0,
416 ACPI_MTX_DO_NOT_LOCK);
419 #ifdef CONFIG_GENERIC_TIME
420 /* TSC halts in C3, so notify users */
423 /* Re-enable interrupts */
425 current_thread_info()->status |= TS_POLLING;
426 /* Compute time (ticks) that we were actually asleep */
428 ticks_elapsed(t1, t2) - cx->latency_ticks - C3_OVERHEAD;
436 next_state = pr->power.state;
438 #ifdef CONFIG_HOTPLUG_CPU
439 /* Don't do promotion/demotion */
440 if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) &&
441 !pr->flags.has_cst && !acpi_fadt.plvl2_up) {
450 * Track the number of longs (time asleep is greater than threshold)
451 * and promote when the count threshold is reached. Note that bus
452 * mastering activity may prevent promotions.
453 * Do not promote above max_cstate.
455 if (cx->promotion.state &&
456 ((cx->promotion.state - pr->power.states) <= max_cstate)) {
457 if (sleep_ticks > cx->promotion.threshold.ticks) {
458 cx->promotion.count++;
459 cx->demotion.count = 0;
460 if (cx->promotion.count >=
461 cx->promotion.threshold.count) {
462 if (pr->flags.bm_check) {
464 (pr->power.bm_activity & cx->
465 promotion.threshold.bm)) {
471 next_state = cx->promotion.state;
481 * Track the number of shorts (time asleep is less than time threshold)
482 * and demote when the usage threshold is reached.
484 if (cx->demotion.state) {
485 if (sleep_ticks < cx->demotion.threshold.ticks) {
486 cx->demotion.count++;
487 cx->promotion.count = 0;
488 if (cx->demotion.count >= cx->demotion.threshold.count) {
489 next_state = cx->demotion.state;
497 * Demote if current state exceeds max_cstate
499 if ((pr->power.state - pr->power.states) > max_cstate) {
500 if (cx->demotion.state)
501 next_state = cx->demotion.state;
507 * If we're going to start using a new Cx state we must clean up
508 * from the previous and prepare to use the new.
510 if (next_state != pr->power.state)
511 acpi_processor_power_activate(pr, next_state);
514 static int acpi_processor_set_power_policy(struct acpi_processor *pr)
517 unsigned int state_is_set = 0;
518 struct acpi_processor_cx *lower = NULL;
519 struct acpi_processor_cx *higher = NULL;
520 struct acpi_processor_cx *cx;
527 * This function sets the default Cx state policy (OS idle handler).
528 * Our scheme is to promote quickly to C2 but more conservatively
529 * to C3. We're favoring C2 for its characteristics of low latency
530 * (quick response), good power savings, and ability to allow bus
531 * mastering activity. Note that the Cx state policy is completely
532 * customizable and can be altered dynamically.
536 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
537 cx = &pr->power.states[i];
542 pr->power.state = cx;
551 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
552 cx = &pr->power.states[i];
557 cx->demotion.state = lower;
558 cx->demotion.threshold.ticks = cx->latency_ticks;
559 cx->demotion.threshold.count = 1;
560 if (cx->type == ACPI_STATE_C3)
561 cx->demotion.threshold.bm = bm_history;
568 for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) {
569 cx = &pr->power.states[i];
574 cx->promotion.state = higher;
575 cx->promotion.threshold.ticks = cx->latency_ticks;
576 if (cx->type >= ACPI_STATE_C2)
577 cx->promotion.threshold.count = 4;
579 cx->promotion.threshold.count = 10;
580 if (higher->type == ACPI_STATE_C3)
581 cx->promotion.threshold.bm = bm_history;
590 static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
599 /* if info is obtained from pblk/fadt, type equals state */
600 pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2;
601 pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3;
603 #ifndef CONFIG_HOTPLUG_CPU
605 * Check for P_LVL2_UP flag before entering C2 and above on
608 if ((num_online_cpus() > 1) && !acpi_fadt.plvl2_up)
612 /* determine C2 and C3 address from pblk */
613 pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4;
614 pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5;
616 /* determine latencies from FADT */
617 pr->power.states[ACPI_STATE_C2].latency = acpi_fadt.plvl2_lat;
618 pr->power.states[ACPI_STATE_C3].latency = acpi_fadt.plvl3_lat;
620 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
621 "lvl2[0x%08x] lvl3[0x%08x]\n",
622 pr->power.states[ACPI_STATE_C2].address,
623 pr->power.states[ACPI_STATE_C3].address));
628 static int acpi_processor_get_power_info_default_c1(struct acpi_processor *pr)
631 /* Zero initialize all the C-states info. */
632 memset(pr->power.states, 0, sizeof(pr->power.states));
634 /* set the first C-State to C1 */
635 pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
637 /* the C0 state only exists as a filler in our array,
638 * and all processors need to support C1 */
639 pr->power.states[ACPI_STATE_C0].valid = 1;
640 pr->power.states[ACPI_STATE_C1].valid = 1;
645 static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
647 acpi_status status = 0;
651 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
652 union acpi_object *cst;
660 /* Zero initialize C2 onwards and prepare for fresh CST lookup */
661 for (i = 2; i < ACPI_PROCESSOR_MAX_POWER; i++)
662 memset(&(pr->power.states[i]), 0,
663 sizeof(struct acpi_processor_cx));
665 status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer);
666 if (ACPI_FAILURE(status)) {
667 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n"));
671 cst = (union acpi_object *)buffer.pointer;
673 /* There must be at least 2 elements */
674 if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) {
675 printk(KERN_ERR PREFIX "not enough elements in _CST\n");
680 count = cst->package.elements[0].integer.value;
682 /* Validate number of power states. */
683 if (count < 1 || count != cst->package.count - 1) {
684 printk(KERN_ERR PREFIX "count given by _CST is not valid\n");
689 /* Tell driver that at least _CST is supported. */
690 pr->flags.has_cst = 1;
692 for (i = 1; i <= count; i++) {
693 union acpi_object *element;
694 union acpi_object *obj;
695 struct acpi_power_register *reg;
696 struct acpi_processor_cx cx;
698 memset(&cx, 0, sizeof(cx));
700 element = (union acpi_object *)&(cst->package.elements[i]);
701 if (element->type != ACPI_TYPE_PACKAGE)
704 if (element->package.count != 4)
707 obj = (union acpi_object *)&(element->package.elements[0]);
709 if (obj->type != ACPI_TYPE_BUFFER)
712 reg = (struct acpi_power_register *)obj->buffer.pointer;
714 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO &&
715 (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE))
718 cx.address = (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) ?
721 /* There should be an easy way to extract an integer... */
722 obj = (union acpi_object *)&(element->package.elements[1]);
723 if (obj->type != ACPI_TYPE_INTEGER)
726 cx.type = obj->integer.value;
728 if ((cx.type != ACPI_STATE_C1) &&
729 (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO))
732 if ((cx.type < ACPI_STATE_C2) || (cx.type > ACPI_STATE_C3))
735 obj = (union acpi_object *)&(element->package.elements[2]);
736 if (obj->type != ACPI_TYPE_INTEGER)
739 cx.latency = obj->integer.value;
741 obj = (union acpi_object *)&(element->package.elements[3]);
742 if (obj->type != ACPI_TYPE_INTEGER)
745 cx.power = obj->integer.value;
748 memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx));
751 * We support total ACPI_PROCESSOR_MAX_POWER - 1
752 * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1)
754 if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) {
756 "Limiting number of power states to max (%d)\n",
757 ACPI_PROCESSOR_MAX_POWER);
759 "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n");
764 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n",
767 /* Validate number of power states discovered */
768 if (current_count < 2)
772 acpi_os_free(buffer.pointer);
777 static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx)
784 * C2 latency must be less than or equal to 100
787 else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) {
788 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
789 "latency too large [%d]\n", cx->latency));
794 * Otherwise we've met all of our C2 requirements.
795 * Normalize the C2 latency to expidite policy
798 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
803 static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
804 struct acpi_processor_cx *cx)
806 static int bm_check_flag;
813 * C3 latency must be less than or equal to 1000
816 else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) {
817 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
818 "latency too large [%d]\n", cx->latency));
823 * PIIX4 Erratum #18: We don't support C3 when Type-F (fast)
824 * DMA transfers are used by any ISA device to avoid livelock.
825 * Note that we could disable Type-F DMA (as recommended by
826 * the erratum), but this is known to disrupt certain ISA
827 * devices thus we take the conservative approach.
829 else if (errata.piix4.fdma) {
830 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
831 "C3 not supported on PIIX4 with Type-F DMA\n"));
835 /* All the logic here assumes flags.bm_check is same across all CPUs */
836 if (!bm_check_flag) {
837 /* Determine whether bm_check is needed based on CPU */
838 acpi_processor_power_init_bm_check(&(pr->flags), pr->id);
839 bm_check_flag = pr->flags.bm_check;
841 pr->flags.bm_check = bm_check_flag;
844 if (pr->flags.bm_check) {
845 /* bus mastering control is necessary */
846 if (!pr->flags.bm_control) {
847 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
848 "C3 support requires bus mastering control\n"));
853 * WBINVD should be set in fadt, for C3 state to be
854 * supported on when bm_check is not required.
856 if (acpi_fadt.wb_invd != 1) {
857 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
858 "Cache invalidation should work properly"
859 " for C3 to be enabled on SMP systems\n"));
862 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD,
863 0, ACPI_MTX_DO_NOT_LOCK);
867 * Otherwise we've met all of our C3 requirements.
868 * Normalize the C3 latency to expidite policy. Enable
869 * checking of bus mastering status (bm_check) so we can
870 * use this in our C3 policy
873 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
878 static int acpi_processor_power_verify(struct acpi_processor *pr)
881 unsigned int working = 0;
883 #ifdef ARCH_APICTIMER_STOPS_ON_C3
884 int timer_broadcast = 0;
885 cpumask_t mask = cpumask_of_cpu(pr->id);
886 on_each_cpu(switch_ipi_to_APIC_timer, &mask, 1, 1);
889 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
890 struct acpi_processor_cx *cx = &pr->power.states[i];
898 acpi_processor_power_verify_c2(cx);
899 #ifdef ARCH_APICTIMER_STOPS_ON_C3
900 /* Some AMD systems fake C3 as C2, but still
901 have timer troubles */
903 boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
909 acpi_processor_power_verify_c3(pr, cx);
910 #ifdef ARCH_APICTIMER_STOPS_ON_C3
921 #ifdef ARCH_APICTIMER_STOPS_ON_C3
923 on_each_cpu(switch_APIC_timer_to_ipi, &mask, 1, 1);
929 static int acpi_processor_get_power_info(struct acpi_processor *pr)
935 /* NOTE: the idle thread may not be running while calling
938 /* Adding C1 state */
939 acpi_processor_get_power_info_default_c1(pr);
940 result = acpi_processor_get_power_info_cst(pr);
941 if (result == -ENODEV)
942 acpi_processor_get_power_info_fadt(pr);
944 pr->power.count = acpi_processor_power_verify(pr);
949 * Now that we know which states are supported, set the default
950 * policy. Note that this policy can be changed dynamically
951 * (e.g. encourage deeper sleeps to conserve battery life when
954 result = acpi_processor_set_power_policy(pr);
959 * if one state of type C2 or C3 is available, mark this
960 * CPU as being "idle manageable"
962 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
963 if (pr->power.states[i].valid) {
965 if (pr->power.states[i].type >= ACPI_STATE_C2)
973 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
985 if (!pr->flags.power_setup_done)
988 /* Fall back to the default idle loop */
989 pm_idle = pm_idle_save;
990 synchronize_sched(); /* Relies on interrupts forcing exit from idle. */
993 result = acpi_processor_get_power_info(pr);
994 if ((pr->flags.power == 1) && (pr->flags.power_setup_done))
995 pm_idle = acpi_processor_idle;
1000 /* proc interface */
1002 static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset)
1004 struct acpi_processor *pr = (struct acpi_processor *)seq->private;
1011 seq_printf(seq, "active state: C%zd\n"
1013 "bus master activity: %08x\n",
1014 pr->power.state ? pr->power.state - pr->power.states : 0,
1015 max_cstate, (unsigned)pr->power.bm_activity);
1017 seq_puts(seq, "states:\n");
1019 for (i = 1; i <= pr->power.count; i++) {
1020 seq_printf(seq, " %cC%d: ",
1021 (&pr->power.states[i] ==
1022 pr->power.state ? '*' : ' '), i);
1024 if (!pr->power.states[i].valid) {
1025 seq_puts(seq, "<not supported>\n");
1029 switch (pr->power.states[i].type) {
1031 seq_printf(seq, "type[C1] ");
1034 seq_printf(seq, "type[C2] ");
1037 seq_printf(seq, "type[C3] ");
1040 seq_printf(seq, "type[--] ");
1044 if (pr->power.states[i].promotion.state)
1045 seq_printf(seq, "promotion[C%zd] ",
1046 (pr->power.states[i].promotion.state -
1049 seq_puts(seq, "promotion[--] ");
1051 if (pr->power.states[i].demotion.state)
1052 seq_printf(seq, "demotion[C%zd] ",
1053 (pr->power.states[i].demotion.state -
1056 seq_puts(seq, "demotion[--] ");
1058 seq_printf(seq, "latency[%03d] usage[%08d]\n",
1059 pr->power.states[i].latency,
1060 pr->power.states[i].usage);
1067 static int acpi_processor_power_open_fs(struct inode *inode, struct file *file)
1069 return single_open(file, acpi_processor_power_seq_show,
1073 static struct file_operations acpi_processor_power_fops = {
1074 .open = acpi_processor_power_open_fs,
1076 .llseek = seq_lseek,
1077 .release = single_release,
1080 int acpi_processor_power_init(struct acpi_processor *pr,
1081 struct acpi_device *device)
1083 acpi_status status = 0;
1084 static int first_run;
1085 struct proc_dir_entry *entry = NULL;
1090 dmi_check_system(processor_power_dmi_table);
1091 if (max_cstate < ACPI_C_STATES_MAX)
1093 "ACPI: processor limited to max C-state %d\n",
1101 if (acpi_fadt.cst_cnt && !nocst) {
1103 acpi_os_write_port(acpi_fadt.smi_cmd, acpi_fadt.cst_cnt, 8);
1104 if (ACPI_FAILURE(status)) {
1105 ACPI_EXCEPTION((AE_INFO, status,
1106 "Notifying BIOS of _CST ability failed"));
1110 acpi_processor_get_power_info(pr);
1113 * Install the idle handler if processor power management is supported.
1114 * Note that we use previously set idle handler will be used on
1115 * platforms that only support C1.
1117 if ((pr->flags.power) && (!boot_option_idle_override)) {
1118 printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id);
1119 for (i = 1; i <= pr->power.count; i++)
1120 if (pr->power.states[i].valid)
1121 printk(" C%d[C%d]", i,
1122 pr->power.states[i].type);
1126 pm_idle_save = pm_idle;
1127 pm_idle = acpi_processor_idle;
1132 entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER,
1133 S_IRUGO, acpi_device_dir(device));
1137 entry->proc_fops = &acpi_processor_power_fops;
1138 entry->data = acpi_driver_data(device);
1139 entry->owner = THIS_MODULE;
1142 pr->flags.power_setup_done = 1;
1147 int acpi_processor_power_exit(struct acpi_processor *pr,
1148 struct acpi_device *device)
1151 pr->flags.power_setup_done = 0;
1153 if (acpi_device_dir(device))
1154 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER,
1155 acpi_device_dir(device));
1157 /* Unregister the idle handler when processor #0 is removed. */
1159 pm_idle = pm_idle_save;
1162 * We are about to unload the current idle thread pm callback
1163 * (pm_idle), Wait for all processors to update cached/local
1164 * copies of pm_idle before proceeding.