2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
62 static bool __read_mostly enable_vpid = 1;
63 module_param_named(vpid, enable_vpid, bool, 0444);
65 static bool __read_mostly flexpriority_enabled = 1;
66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
68 static bool __read_mostly enable_ept = 1;
69 module_param_named(ept, enable_ept, bool, S_IRUGO);
71 static bool __read_mostly enable_unrestricted_guest = 1;
72 module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
75 static bool __read_mostly enable_ept_ad_bits = 1;
76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
78 static bool __read_mostly emulate_invalid_guest_state = true;
79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
81 static bool __read_mostly vmm_exclusive = 1;
82 module_param(vmm_exclusive, bool, S_IRUGO);
84 static bool __read_mostly fasteoi = 1;
85 module_param(fasteoi, bool, S_IRUGO);
87 static bool __read_mostly enable_apicv = 1;
88 module_param(enable_apicv, bool, S_IRUGO);
90 static bool __read_mostly enable_shadow_vmcs = 1;
91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
97 static bool __read_mostly nested = 0;
98 module_param(nested, bool, S_IRUGO);
100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
102 #define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
104 #define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
117 * According to test, this time is usually smaller than 128 cycles.
118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
124 #define KVM_VMX_DEFAULT_PLE_GAP 128
125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127 module_param(ple_gap, int, S_IRUGO);
129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130 module_param(ple_window, int, S_IRUGO);
132 extern const ulong vmx_return;
134 #define NR_AUTOLOAD_MSRS 8
135 #define VMCS02_POOL_SIZE 1
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
152 struct list_head loaded_vmcss_on_cpu_link;
155 struct shared_msr_entry {
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
174 typedef u64 natural_width;
175 struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
200 u64 guest_ia32_perf_global_ctrl;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
288 u32 guest_ldtr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
329 #define VMCS12_REVISION 0x11e57ed0
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
336 #define VMCS12_SIZE 0x1000
338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
340 struct list_head list;
342 struct loaded_vmcs vmcs02;
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
350 /* Has the level1 guest done vmxon? */
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
358 struct vmcs *current_shadow_vmcs;
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
363 bool sync_shadow_vmcs;
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
368 u64 vmcs01_tsc_offset;
369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
375 struct page *apic_access_page;
376 u64 msr_ia32_feature_control;
379 #define POSTED_INTR_ON 0
380 /* Posted-Interrupt Descriptor */
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
387 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
393 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
399 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
405 struct kvm_vcpu vcpu;
406 unsigned long host_rsp;
409 bool nmi_known_unmasked;
411 u32 idt_vectoring_info;
413 struct shared_msr_entry *guest_msrs;
416 unsigned long host_idt_base;
418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
429 struct msr_autoload {
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
436 u16 fs_sel, gs_sel, ldt_sel;
440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
446 struct kvm_segment segs[8];
449 u32 bitmask; /* 4 bits per segment (1 bit per field) */
450 struct kvm_save_segment {
458 bool emulation_required;
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked;
463 s64 vnmi_blocked_time;
468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc;
471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested;
475 enum segment_cache_field {
484 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
486 return container_of(vcpu, struct vcpu_vmx, vcpu);
489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
495 static const unsigned long shadow_read_only_fields[] = {
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
510 VM_EXIT_INSTRUCTION_LEN,
511 IDT_VECTORING_INFO_FIELD,
512 IDT_VECTORING_ERROR_CODE,
513 VM_EXIT_INTR_ERROR_CODE,
515 GUEST_LINEAR_ADDRESS,
516 GUEST_PHYSICAL_ADDRESS
518 static const int max_shadow_read_only_fields =
519 ARRAY_SIZE(shadow_read_only_fields);
521 static const unsigned long shadow_read_write_fields[] = {
527 GUEST_INTERRUPTIBILITY_INFO,
539 CPU_BASED_VM_EXEC_CONTROL,
540 VM_ENTRY_EXCEPTION_ERROR_CODE,
541 VM_ENTRY_INTR_INFO_FIELD,
542 VM_ENTRY_INSTRUCTION_LEN,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
549 static const int max_shadow_read_write_fields =
550 ARRAY_SIZE(shadow_read_write_fields);
552 static const unsigned short vmcs_field_to_offset_table[] = {
553 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
554 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
555 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
556 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
557 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
558 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
559 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
560 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
561 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
562 FIELD(HOST_ES_SELECTOR, host_es_selector),
563 FIELD(HOST_CS_SELECTOR, host_cs_selector),
564 FIELD(HOST_SS_SELECTOR, host_ss_selector),
565 FIELD(HOST_DS_SELECTOR, host_ds_selector),
566 FIELD(HOST_FS_SELECTOR, host_fs_selector),
567 FIELD(HOST_GS_SELECTOR, host_gs_selector),
568 FIELD(HOST_TR_SELECTOR, host_tr_selector),
569 FIELD64(IO_BITMAP_A, io_bitmap_a),
570 FIELD64(IO_BITMAP_B, io_bitmap_b),
571 FIELD64(MSR_BITMAP, msr_bitmap),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
575 FIELD64(TSC_OFFSET, tsc_offset),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
577 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
578 FIELD64(EPT_POINTER, ept_pointer),
579 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
580 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
581 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
582 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
583 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
585 FIELD64(GUEST_PDPTR0, guest_pdptr0),
586 FIELD64(GUEST_PDPTR1, guest_pdptr1),
587 FIELD64(GUEST_PDPTR2, guest_pdptr2),
588 FIELD64(GUEST_PDPTR3, guest_pdptr3),
589 FIELD64(HOST_IA32_PAT, host_ia32_pat),
590 FIELD64(HOST_IA32_EFER, host_ia32_efer),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
594 FIELD(EXCEPTION_BITMAP, exception_bitmap),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
597 FIELD(CR3_TARGET_COUNT, cr3_target_count),
598 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
599 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
601 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
606 FIELD(TPR_THRESHOLD, tpr_threshold),
607 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
608 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
609 FIELD(VM_EXIT_REASON, vm_exit_reason),
610 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
611 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
612 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
613 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
614 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
615 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
616 FIELD(GUEST_ES_LIMIT, guest_es_limit),
617 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
618 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
619 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
620 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
621 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
622 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
623 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
624 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
625 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
626 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
627 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
628 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
629 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
630 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
631 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
632 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
633 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
635 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
636 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
637 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
638 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
639 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
640 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
641 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
642 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
643 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
644 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
645 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
646 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
647 FIELD(EXIT_QUALIFICATION, exit_qualification),
648 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
649 FIELD(GUEST_CR0, guest_cr0),
650 FIELD(GUEST_CR3, guest_cr3),
651 FIELD(GUEST_CR4, guest_cr4),
652 FIELD(GUEST_ES_BASE, guest_es_base),
653 FIELD(GUEST_CS_BASE, guest_cs_base),
654 FIELD(GUEST_SS_BASE, guest_ss_base),
655 FIELD(GUEST_DS_BASE, guest_ds_base),
656 FIELD(GUEST_FS_BASE, guest_fs_base),
657 FIELD(GUEST_GS_BASE, guest_gs_base),
658 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
659 FIELD(GUEST_TR_BASE, guest_tr_base),
660 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
661 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
662 FIELD(GUEST_DR7, guest_dr7),
663 FIELD(GUEST_RSP, guest_rsp),
664 FIELD(GUEST_RIP, guest_rip),
665 FIELD(GUEST_RFLAGS, guest_rflags),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
667 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
668 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
669 FIELD(HOST_CR0, host_cr0),
670 FIELD(HOST_CR3, host_cr3),
671 FIELD(HOST_CR4, host_cr4),
672 FIELD(HOST_FS_BASE, host_fs_base),
673 FIELD(HOST_GS_BASE, host_gs_base),
674 FIELD(HOST_TR_BASE, host_tr_base),
675 FIELD(HOST_GDTR_BASE, host_gdtr_base),
676 FIELD(HOST_IDTR_BASE, host_idtr_base),
677 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
678 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
679 FIELD(HOST_RSP, host_rsp),
680 FIELD(HOST_RIP, host_rip),
682 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
684 static inline short vmcs_field_to_offset(unsigned long field)
686 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
688 return vmcs_field_to_offset_table[field];
691 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
693 return to_vmx(vcpu)->nested.current_vmcs12;
696 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
698 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
699 if (is_error_page(page))
705 static void nested_release_page(struct page *page)
707 kvm_release_page_dirty(page);
710 static void nested_release_page_clean(struct page *page)
712 kvm_release_page_clean(page);
715 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
716 static u64 construct_eptp(unsigned long root_hpa);
717 static void kvm_cpu_vmxon(u64 addr);
718 static void kvm_cpu_vmxoff(void);
719 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
720 static void vmx_set_segment(struct kvm_vcpu *vcpu,
721 struct kvm_segment *var, int seg);
722 static void vmx_get_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
724 static bool guest_state_valid(struct kvm_vcpu *vcpu);
725 static u32 vmx_segment_access_rights(struct kvm_segment *var);
726 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
727 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
728 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
730 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
731 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
736 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
737 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
739 static unsigned long *vmx_io_bitmap_a;
740 static unsigned long *vmx_io_bitmap_b;
741 static unsigned long *vmx_msr_bitmap_legacy;
742 static unsigned long *vmx_msr_bitmap_longmode;
743 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
744 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
745 static unsigned long *vmx_vmread_bitmap;
746 static unsigned long *vmx_vmwrite_bitmap;
748 static bool cpu_has_load_ia32_efer;
749 static bool cpu_has_load_perf_global_ctrl;
751 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
752 static DEFINE_SPINLOCK(vmx_vpid_lock);
754 static struct vmcs_config {
758 u32 pin_based_exec_ctrl;
759 u32 cpu_based_exec_ctrl;
760 u32 cpu_based_2nd_exec_ctrl;
765 static struct vmx_capability {
770 #define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
778 static const struct kvm_vmx_segment_field {
783 } kvm_vmx_segment_fields[] = {
784 VMX_SEGMENT_FIELD(CS),
785 VMX_SEGMENT_FIELD(DS),
786 VMX_SEGMENT_FIELD(ES),
787 VMX_SEGMENT_FIELD(FS),
788 VMX_SEGMENT_FIELD(GS),
789 VMX_SEGMENT_FIELD(SS),
790 VMX_SEGMENT_FIELD(TR),
791 VMX_SEGMENT_FIELD(LDTR),
794 static u64 host_efer;
796 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
800 * away by decrementing the array size.
802 static const u32 vmx_msr_index[] = {
804 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
806 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
808 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
810 static inline bool is_page_fault(u32 intr_info)
812 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
813 INTR_INFO_VALID_MASK)) ==
814 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
817 static inline bool is_no_device(u32 intr_info)
819 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
820 INTR_INFO_VALID_MASK)) ==
821 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
824 static inline bool is_invalid_opcode(u32 intr_info)
826 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
827 INTR_INFO_VALID_MASK)) ==
828 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
831 static inline bool is_external_interrupt(u32 intr_info)
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
834 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
837 static inline bool is_machine_check(u32 intr_info)
839 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
840 INTR_INFO_VALID_MASK)) ==
841 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
844 static inline bool cpu_has_vmx_msr_bitmap(void)
846 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
849 static inline bool cpu_has_vmx_tpr_shadow(void)
851 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
854 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
859 static inline bool cpu_has_secondary_exec_ctrls(void)
861 return vmcs_config.cpu_based_exec_ctrl &
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
865 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
871 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
877 static inline bool cpu_has_vmx_apic_register_virt(void)
879 return vmcs_config.cpu_based_2nd_exec_ctrl &
880 SECONDARY_EXEC_APIC_REGISTER_VIRT;
883 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
885 return vmcs_config.cpu_based_2nd_exec_ctrl &
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
889 static inline bool cpu_has_vmx_posted_intr(void)
891 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
894 static inline bool cpu_has_vmx_apicv(void)
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
901 static inline bool cpu_has_vmx_flexpriority(void)
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
907 static inline bool cpu_has_vmx_ept_execute_only(void)
909 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
912 static inline bool cpu_has_vmx_eptp_uncacheable(void)
914 return vmx_capability.ept & VMX_EPTP_UC_BIT;
917 static inline bool cpu_has_vmx_eptp_writeback(void)
919 return vmx_capability.ept & VMX_EPTP_WB_BIT;
922 static inline bool cpu_has_vmx_ept_2m_page(void)
924 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
927 static inline bool cpu_has_vmx_ept_1g_page(void)
929 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
932 static inline bool cpu_has_vmx_ept_4levels(void)
934 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
937 static inline bool cpu_has_vmx_ept_ad_bits(void)
939 return vmx_capability.ept & VMX_EPT_AD_BIT;
942 static inline bool cpu_has_vmx_invept_context(void)
944 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
947 static inline bool cpu_has_vmx_invept_global(void)
949 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
952 static inline bool cpu_has_vmx_invvpid_single(void)
954 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
957 static inline bool cpu_has_vmx_invvpid_global(void)
959 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
962 static inline bool cpu_has_vmx_ept(void)
964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_ENABLE_EPT;
968 static inline bool cpu_has_vmx_unrestricted_guest(void)
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_UNRESTRICTED_GUEST;
974 static inline bool cpu_has_vmx_ple(void)
976 return vmcs_config.cpu_based_2nd_exec_ctrl &
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
980 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
982 return flexpriority_enabled && irqchip_in_kernel(kvm);
985 static inline bool cpu_has_vmx_vpid(void)
987 return vmcs_config.cpu_based_2nd_exec_ctrl &
988 SECONDARY_EXEC_ENABLE_VPID;
991 static inline bool cpu_has_vmx_rdtscp(void)
993 return vmcs_config.cpu_based_2nd_exec_ctrl &
994 SECONDARY_EXEC_RDTSCP;
997 static inline bool cpu_has_vmx_invpcid(void)
999 return vmcs_config.cpu_based_2nd_exec_ctrl &
1000 SECONDARY_EXEC_ENABLE_INVPCID;
1003 static inline bool cpu_has_virtual_nmis(void)
1005 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1008 static inline bool cpu_has_vmx_wbinvd_exit(void)
1010 return vmcs_config.cpu_based_2nd_exec_ctrl &
1011 SECONDARY_EXEC_WBINVD_EXITING;
1014 static inline bool cpu_has_vmx_shadow_vmcs(void)
1017 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_SHADOW_VMCS;
1026 static inline bool report_flexpriority(void)
1028 return flexpriority_enabled;
1031 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1033 return vmcs12->cpu_based_vm_exec_control & bit;
1036 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1038 return (vmcs12->cpu_based_vm_exec_control &
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040 (vmcs12->secondary_vm_exec_control & bit);
1043 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1045 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1048 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1050 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1053 static inline bool is_exception(u32 intr_info)
1055 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1059 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1060 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061 struct vmcs12 *vmcs12,
1062 u32 reason, unsigned long qualification);
1064 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1068 for (i = 0; i < vmx->nmsrs; ++i)
1069 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1074 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1080 } operand = { vpid, 0, gva };
1082 asm volatile (__ex(ASM_VMX_INVVPID)
1083 /* CF==1 or ZF==1 --> rc = -1 */
1084 "; ja 1f ; ud2 ; 1:"
1085 : : "a"(&operand), "c"(ext) : "cc", "memory");
1088 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1092 } operand = {eptp, gpa};
1094 asm volatile (__ex(ASM_VMX_INVEPT)
1095 /* CF==1 or ZF==1 --> rc = -1 */
1096 "; ja 1f ; ud2 ; 1:\n"
1097 : : "a" (&operand), "c" (ext) : "cc", "memory");
1100 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1104 i = __find_msr_index(vmx, msr);
1106 return &vmx->guest_msrs[i];
1110 static void vmcs_clear(struct vmcs *vmcs)
1112 u64 phys_addr = __pa(vmcs);
1115 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1116 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1119 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1123 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1125 vmcs_clear(loaded_vmcs->vmcs);
1126 loaded_vmcs->cpu = -1;
1127 loaded_vmcs->launched = 0;
1130 static void vmcs_load(struct vmcs *vmcs)
1132 u64 phys_addr = __pa(vmcs);
1135 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1136 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1139 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1145 * This bitmap is used to indicate whether the vmclear
1146 * operation is enabled on all cpus. All disabled by
1149 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1151 static inline void crash_enable_local_vmclear(int cpu)
1153 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1156 static inline void crash_disable_local_vmclear(int cpu)
1158 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1161 static inline int crash_local_vmclear_enabled(int cpu)
1163 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1166 static void crash_vmclear_local_loaded_vmcss(void)
1168 int cpu = raw_smp_processor_id();
1169 struct loaded_vmcs *v;
1171 if (!crash_local_vmclear_enabled(cpu))
1174 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175 loaded_vmcss_on_cpu_link)
1176 vmcs_clear(v->vmcs);
1179 static inline void crash_enable_local_vmclear(int cpu) { }
1180 static inline void crash_disable_local_vmclear(int cpu) { }
1181 #endif /* CONFIG_KEXEC */
1183 static void __loaded_vmcs_clear(void *arg)
1185 struct loaded_vmcs *loaded_vmcs = arg;
1186 int cpu = raw_smp_processor_id();
1188 if (loaded_vmcs->cpu != cpu)
1189 return; /* vcpu migration can race with cpu offline */
1190 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1191 per_cpu(current_vmcs, cpu) = NULL;
1192 crash_disable_local_vmclear(cpu);
1193 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1196 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197 * is before setting loaded_vmcs->vcpu to -1 which is done in
1198 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199 * then adds the vmcs into percpu list before it is deleted.
1203 loaded_vmcs_init(loaded_vmcs);
1204 crash_enable_local_vmclear(cpu);
1207 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1209 int cpu = loaded_vmcs->cpu;
1212 smp_call_function_single(cpu,
1213 __loaded_vmcs_clear, loaded_vmcs, 1);
1216 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1221 if (cpu_has_vmx_invvpid_single())
1222 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1225 static inline void vpid_sync_vcpu_global(void)
1227 if (cpu_has_vmx_invvpid_global())
1228 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1231 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1233 if (cpu_has_vmx_invvpid_single())
1234 vpid_sync_vcpu_single(vmx);
1236 vpid_sync_vcpu_global();
1239 static inline void ept_sync_global(void)
1241 if (cpu_has_vmx_invept_global())
1242 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1245 static inline void ept_sync_context(u64 eptp)
1248 if (cpu_has_vmx_invept_context())
1249 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1255 static __always_inline unsigned long vmcs_readl(unsigned long field)
1257 unsigned long value;
1259 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260 : "=a"(value) : "d"(field) : "cc");
1264 static __always_inline u16 vmcs_read16(unsigned long field)
1266 return vmcs_readl(field);
1269 static __always_inline u32 vmcs_read32(unsigned long field)
1271 return vmcs_readl(field);
1274 static __always_inline u64 vmcs_read64(unsigned long field)
1276 #ifdef CONFIG_X86_64
1277 return vmcs_readl(field);
1279 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1283 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1285 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1290 static void vmcs_writel(unsigned long field, unsigned long value)
1294 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1295 : "=q"(error) : "a"(value), "d"(field) : "cc");
1296 if (unlikely(error))
1297 vmwrite_error(field, value);
1300 static void vmcs_write16(unsigned long field, u16 value)
1302 vmcs_writel(field, value);
1305 static void vmcs_write32(unsigned long field, u32 value)
1307 vmcs_writel(field, value);
1310 static void vmcs_write64(unsigned long field, u64 value)
1312 vmcs_writel(field, value);
1313 #ifndef CONFIG_X86_64
1315 vmcs_writel(field+1, value >> 32);
1319 static void vmcs_clear_bits(unsigned long field, u32 mask)
1321 vmcs_writel(field, vmcs_readl(field) & ~mask);
1324 static void vmcs_set_bits(unsigned long field, u32 mask)
1326 vmcs_writel(field, vmcs_readl(field) | mask);
1329 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1331 vmx->segment_cache.bitmask = 0;
1334 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1338 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1340 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342 vmx->segment_cache.bitmask = 0;
1344 ret = vmx->segment_cache.bitmask & mask;
1345 vmx->segment_cache.bitmask |= mask;
1349 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1351 u16 *p = &vmx->segment_cache.seg[seg].selector;
1353 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1358 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1360 ulong *p = &vmx->segment_cache.seg[seg].base;
1362 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1367 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1369 u32 *p = &vmx->segment_cache.seg[seg].limit;
1371 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1376 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1378 u32 *p = &vmx->segment_cache.seg[seg].ar;
1380 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1385 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1389 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391 if ((vcpu->guest_debug &
1392 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394 eb |= 1u << BP_VECTOR;
1395 if (to_vmx(vcpu)->rmode.vm86_active)
1398 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1399 if (vcpu->fpu_active)
1400 eb &= ~(1u << NM_VECTOR);
1402 /* When we are running a nested L2 guest and L1 specified for it a
1403 * certain exception bitmap, we must trap the same exceptions and pass
1404 * them to L1. When running L2, we will only handle the exceptions
1405 * specified above if L1 did not want them.
1407 if (is_guest_mode(vcpu))
1408 eb |= get_vmcs12(vcpu)->exception_bitmap;
1410 vmcs_write32(EXCEPTION_BITMAP, eb);
1413 static void clear_atomic_switch_msr_special(unsigned long entry,
1416 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1420 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1423 struct msr_autoload *m = &vmx->msr_autoload;
1427 if (cpu_has_load_ia32_efer) {
1428 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429 VM_EXIT_LOAD_IA32_EFER);
1433 case MSR_CORE_PERF_GLOBAL_CTRL:
1434 if (cpu_has_load_perf_global_ctrl) {
1435 clear_atomic_switch_msr_special(
1436 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1443 for (i = 0; i < m->nr; ++i)
1444 if (m->guest[i].index == msr)
1450 m->guest[i] = m->guest[m->nr];
1451 m->host[i] = m->host[m->nr];
1452 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1456 static void add_atomic_switch_msr_special(unsigned long entry,
1457 unsigned long exit, unsigned long guest_val_vmcs,
1458 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1460 vmcs_write64(guest_val_vmcs, guest_val);
1461 vmcs_write64(host_val_vmcs, host_val);
1462 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1466 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467 u64 guest_val, u64 host_val)
1470 struct msr_autoload *m = &vmx->msr_autoload;
1474 if (cpu_has_load_ia32_efer) {
1475 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476 VM_EXIT_LOAD_IA32_EFER,
1479 guest_val, host_val);
1483 case MSR_CORE_PERF_GLOBAL_CTRL:
1484 if (cpu_has_load_perf_global_ctrl) {
1485 add_atomic_switch_msr_special(
1486 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488 GUEST_IA32_PERF_GLOBAL_CTRL,
1489 HOST_IA32_PERF_GLOBAL_CTRL,
1490 guest_val, host_val);
1496 for (i = 0; i < m->nr; ++i)
1497 if (m->guest[i].index == msr)
1500 if (i == NR_AUTOLOAD_MSRS) {
1501 printk_once(KERN_WARNING"Not enough mst switch entries. "
1502 "Can't add msr %x\n", msr);
1504 } else if (i == m->nr) {
1506 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1510 m->guest[i].index = msr;
1511 m->guest[i].value = guest_val;
1512 m->host[i].index = msr;
1513 m->host[i].value = host_val;
1516 static void reload_tss(void)
1519 * VT restores TR but not its size. Useless.
1521 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1522 struct desc_struct *descs;
1524 descs = (void *)gdt->address;
1525 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1529 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1534 guest_efer = vmx->vcpu.arch.efer;
1537 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1540 ignore_bits = EFER_NX | EFER_SCE;
1541 #ifdef CONFIG_X86_64
1542 ignore_bits |= EFER_LMA | EFER_LME;
1543 /* SCE is meaningful only in long mode on Intel */
1544 if (guest_efer & EFER_LMA)
1545 ignore_bits &= ~(u64)EFER_SCE;
1547 guest_efer &= ~ignore_bits;
1548 guest_efer |= host_efer & ignore_bits;
1549 vmx->guest_msrs[efer_offset].data = guest_efer;
1550 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1552 clear_atomic_switch_msr(vmx, MSR_EFER);
1553 /* On ept, can't emulate nx, and must switch nx atomically */
1554 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555 guest_efer = vmx->vcpu.arch.efer;
1556 if (!(guest_efer & EFER_LMA))
1557 guest_efer &= ~EFER_LME;
1558 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1565 static unsigned long segment_base(u16 selector)
1567 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1568 struct desc_struct *d;
1569 unsigned long table_base;
1572 if (!(selector & ~3))
1575 table_base = gdt->address;
1577 if (selector & 4) { /* from ldt */
1578 u16 ldt_selector = kvm_read_ldt();
1580 if (!(ldt_selector & ~3))
1583 table_base = segment_base(ldt_selector);
1585 d = (struct desc_struct *)(table_base + (selector & ~7));
1586 v = get_desc_base(d);
1587 #ifdef CONFIG_X86_64
1588 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1594 static inline unsigned long kvm_read_tr_base(void)
1597 asm("str %0" : "=g"(tr));
1598 return segment_base(tr);
1601 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1603 struct vcpu_vmx *vmx = to_vmx(vcpu);
1606 if (vmx->host_state.loaded)
1609 vmx->host_state.loaded = 1;
1611 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1612 * allow segment selectors with cpl > 0 or ti == 1.
1614 vmx->host_state.ldt_sel = kvm_read_ldt();
1615 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1616 savesegment(fs, vmx->host_state.fs_sel);
1617 if (!(vmx->host_state.fs_sel & 7)) {
1618 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1619 vmx->host_state.fs_reload_needed = 0;
1621 vmcs_write16(HOST_FS_SELECTOR, 0);
1622 vmx->host_state.fs_reload_needed = 1;
1624 savesegment(gs, vmx->host_state.gs_sel);
1625 if (!(vmx->host_state.gs_sel & 7))
1626 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1628 vmcs_write16(HOST_GS_SELECTOR, 0);
1629 vmx->host_state.gs_ldt_reload_needed = 1;
1632 #ifdef CONFIG_X86_64
1633 savesegment(ds, vmx->host_state.ds_sel);
1634 savesegment(es, vmx->host_state.es_sel);
1637 #ifdef CONFIG_X86_64
1638 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1641 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1645 #ifdef CONFIG_X86_64
1646 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647 if (is_long_mode(&vmx->vcpu))
1648 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1650 for (i = 0; i < vmx->save_nmsrs; ++i)
1651 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1652 vmx->guest_msrs[i].data,
1653 vmx->guest_msrs[i].mask);
1656 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1658 if (!vmx->host_state.loaded)
1661 ++vmx->vcpu.stat.host_state_reload;
1662 vmx->host_state.loaded = 0;
1663 #ifdef CONFIG_X86_64
1664 if (is_long_mode(&vmx->vcpu))
1665 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1667 if (vmx->host_state.gs_ldt_reload_needed) {
1668 kvm_load_ldt(vmx->host_state.ldt_sel);
1669 #ifdef CONFIG_X86_64
1670 load_gs_index(vmx->host_state.gs_sel);
1672 loadsegment(gs, vmx->host_state.gs_sel);
1675 if (vmx->host_state.fs_reload_needed)
1676 loadsegment(fs, vmx->host_state.fs_sel);
1677 #ifdef CONFIG_X86_64
1678 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679 loadsegment(ds, vmx->host_state.ds_sel);
1680 loadsegment(es, vmx->host_state.es_sel);
1684 #ifdef CONFIG_X86_64
1685 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1688 * If the FPU is not active (through the host task or
1689 * the guest vcpu), then restore the cr0.TS bit.
1691 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1693 load_gdt(&__get_cpu_var(host_gdt));
1696 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1699 __vmx_load_host_state(vmx);
1704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705 * vcpu mutex is already taken.
1707 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1709 struct vcpu_vmx *vmx = to_vmx(vcpu);
1710 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1713 kvm_cpu_vmxon(phys_addr);
1714 else if (vmx->loaded_vmcs->cpu != cpu)
1715 loaded_vmcs_clear(vmx->loaded_vmcs);
1717 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719 vmcs_load(vmx->loaded_vmcs->vmcs);
1722 if (vmx->loaded_vmcs->cpu != cpu) {
1723 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1724 unsigned long sysenter_esp;
1726 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1727 local_irq_disable();
1728 crash_disable_local_vmclear(cpu);
1731 * Read loaded_vmcs->cpu should be before fetching
1732 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733 * See the comments in __loaded_vmcs_clear().
1737 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738 &per_cpu(loaded_vmcss_on_cpu, cpu));
1739 crash_enable_local_vmclear(cpu);
1743 * Linux uses per-cpu TSS and GDT, so set these when switching
1746 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1747 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1749 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1751 vmx->loaded_vmcs->cpu = cpu;
1755 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1757 __vmx_load_host_state(to_vmx(vcpu));
1758 if (!vmm_exclusive) {
1759 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1765 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1769 if (vcpu->fpu_active)
1771 vcpu->fpu_active = 1;
1772 cr0 = vmcs_readl(GUEST_CR0);
1773 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775 vmcs_writel(GUEST_CR0, cr0);
1776 update_exception_bitmap(vcpu);
1777 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1778 if (is_guest_mode(vcpu))
1779 vcpu->arch.cr0_guest_owned_bits &=
1780 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1781 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1784 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1787 * Return the cr0 value that a nested guest would read. This is a combination
1788 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789 * its hypervisor (cr0_read_shadow).
1791 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1793 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1796 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1798 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1802 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1804 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805 * set this *before* calling this function.
1807 vmx_decache_cr0_guest_bits(vcpu);
1808 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1809 update_exception_bitmap(vcpu);
1810 vcpu->arch.cr0_guest_owned_bits = 0;
1811 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1812 if (is_guest_mode(vcpu)) {
1814 * L1's specified read shadow might not contain the TS bit,
1815 * so now that we turned on shadowing of this bit, we need to
1816 * set this bit of the shadow. Like in nested_vmx_run we need
1817 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818 * up-to-date here because we just decached cr0.TS (and we'll
1819 * only update vmcs12->guest_cr0 on nested exit).
1821 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823 (vcpu->arch.cr0 & X86_CR0_TS);
1824 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1826 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1829 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1831 unsigned long rflags, save_rflags;
1833 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835 rflags = vmcs_readl(GUEST_RFLAGS);
1836 if (to_vmx(vcpu)->rmode.vm86_active) {
1837 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1841 to_vmx(vcpu)->rflags = rflags;
1843 return to_vmx(vcpu)->rflags;
1846 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1848 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849 to_vmx(vcpu)->rflags = rflags;
1850 if (to_vmx(vcpu)->rmode.vm86_active) {
1851 to_vmx(vcpu)->rmode.save_rflags = rflags;
1852 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1854 vmcs_writel(GUEST_RFLAGS, rflags);
1857 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1859 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1862 if (interruptibility & GUEST_INTR_STATE_STI)
1863 ret |= KVM_X86_SHADOW_INT_STI;
1864 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1865 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1870 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1872 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873 u32 interruptibility = interruptibility_old;
1875 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1877 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1878 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1879 else if (mask & KVM_X86_SHADOW_INT_STI)
1880 interruptibility |= GUEST_INTR_STATE_STI;
1882 if ((interruptibility != interruptibility_old))
1883 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1886 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1890 rip = kvm_rip_read(vcpu);
1891 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1892 kvm_rip_write(vcpu, rip);
1894 /* skipping an emulated instruction also counts */
1895 vmx_set_interrupt_shadow(vcpu, 0);
1899 * KVM wants to inject page-faults which it got to the guest. This function
1900 * checks whether in a nested guest, we need to inject them to L1 or L2.
1901 * This function assumes it is called with the exit reason in vmcs02 being
1902 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1905 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1907 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1909 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1910 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1913 nested_vmx_vmexit(vcpu);
1917 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1918 bool has_error_code, u32 error_code,
1921 struct vcpu_vmx *vmx = to_vmx(vcpu);
1922 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1924 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1925 !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1928 if (has_error_code) {
1929 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1930 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1933 if (vmx->rmode.vm86_active) {
1935 if (kvm_exception_is_soft(nr))
1936 inc_eip = vcpu->arch.event_exit_inst_len;
1937 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1938 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1942 if (kvm_exception_is_soft(nr)) {
1943 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1944 vmx->vcpu.arch.event_exit_inst_len);
1945 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1947 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1949 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1952 static bool vmx_rdtscp_supported(void)
1954 return cpu_has_vmx_rdtscp();
1957 static bool vmx_invpcid_supported(void)
1959 return cpu_has_vmx_invpcid() && enable_ept;
1963 * Swap MSR entry in host/guest MSR entry array.
1965 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1967 struct shared_msr_entry tmp;
1969 tmp = vmx->guest_msrs[to];
1970 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1971 vmx->guest_msrs[from] = tmp;
1974 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1976 unsigned long *msr_bitmap;
1978 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1979 if (is_long_mode(vcpu))
1980 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1982 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1984 if (is_long_mode(vcpu))
1985 msr_bitmap = vmx_msr_bitmap_longmode;
1987 msr_bitmap = vmx_msr_bitmap_legacy;
1990 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1994 * Set up the vmcs to automatically save and restore system
1995 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1996 * mode, as fiddling with msrs is very expensive.
1998 static void setup_msrs(struct vcpu_vmx *vmx)
2000 int save_nmsrs, index;
2003 #ifdef CONFIG_X86_64
2004 if (is_long_mode(&vmx->vcpu)) {
2005 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2007 move_msr_up(vmx, index, save_nmsrs++);
2008 index = __find_msr_index(vmx, MSR_LSTAR);
2010 move_msr_up(vmx, index, save_nmsrs++);
2011 index = __find_msr_index(vmx, MSR_CSTAR);
2013 move_msr_up(vmx, index, save_nmsrs++);
2014 index = __find_msr_index(vmx, MSR_TSC_AUX);
2015 if (index >= 0 && vmx->rdtscp_enabled)
2016 move_msr_up(vmx, index, save_nmsrs++);
2018 * MSR_STAR is only needed on long mode guests, and only
2019 * if efer.sce is enabled.
2021 index = __find_msr_index(vmx, MSR_STAR);
2022 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2023 move_msr_up(vmx, index, save_nmsrs++);
2026 index = __find_msr_index(vmx, MSR_EFER);
2027 if (index >= 0 && update_transition_efer(vmx, index))
2028 move_msr_up(vmx, index, save_nmsrs++);
2030 vmx->save_nmsrs = save_nmsrs;
2032 if (cpu_has_vmx_msr_bitmap())
2033 vmx_set_msr_bitmap(&vmx->vcpu);
2037 * reads and returns guest's timestamp counter "register"
2038 * guest_tsc = host_tsc + tsc_offset -- 21.3
2040 static u64 guest_read_tsc(void)
2042 u64 host_tsc, tsc_offset;
2045 tsc_offset = vmcs_read64(TSC_OFFSET);
2046 return host_tsc + tsc_offset;
2050 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2051 * counter, even if a nested guest (L2) is currently running.
2053 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2057 tsc_offset = is_guest_mode(vcpu) ?
2058 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2059 vmcs_read64(TSC_OFFSET);
2060 return host_tsc + tsc_offset;
2064 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2065 * software catchup for faster rates on slower CPUs.
2067 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2072 if (user_tsc_khz > tsc_khz) {
2073 vcpu->arch.tsc_catchup = 1;
2074 vcpu->arch.tsc_always_catchup = 1;
2076 WARN(1, "user requested TSC rate below hardware speed\n");
2079 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2081 return vmcs_read64(TSC_OFFSET);
2085 * writes 'offset' into guest's timestamp counter offset register
2087 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2089 if (is_guest_mode(vcpu)) {
2091 * We're here if L1 chose not to trap WRMSR to TSC. According
2092 * to the spec, this should set L1's TSC; The offset that L1
2093 * set for L2 remains unchanged, and still needs to be added
2094 * to the newly set TSC to get L2's TSC.
2096 struct vmcs12 *vmcs12;
2097 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2098 /* recalculate vmcs02.TSC_OFFSET: */
2099 vmcs12 = get_vmcs12(vcpu);
2100 vmcs_write64(TSC_OFFSET, offset +
2101 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2102 vmcs12->tsc_offset : 0));
2104 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2105 vmcs_read64(TSC_OFFSET), offset);
2106 vmcs_write64(TSC_OFFSET, offset);
2110 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2112 u64 offset = vmcs_read64(TSC_OFFSET);
2114 vmcs_write64(TSC_OFFSET, offset + adjustment);
2115 if (is_guest_mode(vcpu)) {
2116 /* Even when running L2, the adjustment needs to apply to L1 */
2117 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2119 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2120 offset + adjustment);
2123 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2125 return target_tsc - native_read_tsc();
2128 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2130 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2131 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2135 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2136 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2137 * all guests if the "nested" module option is off, and can also be disabled
2138 * for a single guest by disabling its VMX cpuid bit.
2140 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2142 return nested && guest_cpuid_has_vmx(vcpu);
2146 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2147 * returned for the various VMX controls MSRs when nested VMX is enabled.
2148 * The same values should also be used to verify that vmcs12 control fields are
2149 * valid during nested entry from L1 to L2.
2150 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2151 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2152 * bit in the high half is on if the corresponding bit in the control field
2153 * may be on. See also vmx_control_verify().
2154 * TODO: allow these variables to be modified (downgraded) by module options
2157 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2158 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2159 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2160 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2161 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2162 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2163 static u32 nested_vmx_ept_caps;
2164 static __init void nested_vmx_setup_ctls_msrs(void)
2167 * Note that as a general rule, the high half of the MSRs (bits in
2168 * the control fields which may be 1) should be initialized by the
2169 * intersection of the underlying hardware's MSR (i.e., features which
2170 * can be supported) and the list of features we want to expose -
2171 * because they are known to be properly supported in our code.
2172 * Also, usually, the low half of the MSRs (bits which must be 1) can
2173 * be set to 0, meaning that L1 may turn off any of these bits. The
2174 * reason is that if one of these bits is necessary, it will appear
2175 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2176 * fields of vmcs01 and vmcs02, will turn these bits off - and
2177 * nested_vmx_exit_handled() will not pass related exits to L1.
2178 * These rules have exceptions below.
2181 /* pin-based controls */
2182 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2183 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2185 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2186 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2188 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2189 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2190 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2191 PIN_BASED_VMX_PREEMPTION_TIMER;
2192 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2196 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2199 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2200 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2201 #ifdef CONFIG_X86_64
2202 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2204 nested_vmx_exit_ctls_high = 0;
2206 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2207 VM_EXIT_LOAD_IA32_EFER);
2209 /* entry controls */
2210 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2211 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2212 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2213 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2214 nested_vmx_entry_ctls_high &=
2215 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2216 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2217 VM_ENTRY_LOAD_IA32_EFER);
2218 /* cpu-based controls */
2219 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2220 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2221 nested_vmx_procbased_ctls_low = 0;
2222 nested_vmx_procbased_ctls_high &=
2223 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2224 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2225 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2226 CPU_BASED_CR3_STORE_EXITING |
2227 #ifdef CONFIG_X86_64
2228 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2230 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2231 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2232 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2233 CPU_BASED_PAUSE_EXITING |
2234 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2236 * We can allow some features even when not supported by the
2237 * hardware. For example, L1 can specify an MSR bitmap - and we
2238 * can use it to avoid exits to L1 - even when L0 runs L2
2239 * without MSR bitmaps.
2241 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2243 /* secondary cpu-based controls */
2244 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2245 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2246 nested_vmx_secondary_ctls_low = 0;
2247 nested_vmx_secondary_ctls_high &=
2248 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2249 SECONDARY_EXEC_WBINVD_EXITING;
2252 /* nested EPT: emulate EPT also to L1 */
2253 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2254 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT;
2255 nested_vmx_ept_caps |= VMX_EPT_INVEPT_BIT;
2256 nested_vmx_ept_caps &= vmx_capability.ept;
2258 * Since invept is completely emulated we support both global
2259 * and context invalidation independent of what host cpu
2262 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2263 VMX_EPT_EXTENT_CONTEXT_BIT;
2265 nested_vmx_ept_caps = 0;
2267 /* miscellaneous data */
2268 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2269 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2270 VMX_MISC_SAVE_EFER_LMA;
2271 nested_vmx_misc_high = 0;
2274 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2277 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2279 return ((control & high) | low) == control;
2282 static inline u64 vmx_control_msr(u32 low, u32 high)
2284 return low | ((u64)high << 32);
2288 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2289 * also let it use VMX-specific MSRs.
2290 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2291 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2292 * like all other MSRs).
2294 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2296 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2297 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2299 * According to the spec, processors which do not support VMX
2300 * should throw a #GP(0) when VMX capability MSRs are read.
2302 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2306 switch (msr_index) {
2307 case MSR_IA32_FEATURE_CONTROL:
2308 if (nested_vmx_allowed(vcpu)) {
2309 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2313 case MSR_IA32_VMX_BASIC:
2315 * This MSR reports some information about VMX support. We
2316 * should return information about the VMX we emulate for the
2317 * guest, and the VMCS structure we give it - not about the
2318 * VMX support of the underlying hardware.
2320 *pdata = VMCS12_REVISION |
2321 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2322 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2324 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2325 case MSR_IA32_VMX_PINBASED_CTLS:
2326 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2327 nested_vmx_pinbased_ctls_high);
2329 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2330 case MSR_IA32_VMX_PROCBASED_CTLS:
2331 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2332 nested_vmx_procbased_ctls_high);
2334 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2335 case MSR_IA32_VMX_EXIT_CTLS:
2336 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2337 nested_vmx_exit_ctls_high);
2339 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2340 case MSR_IA32_VMX_ENTRY_CTLS:
2341 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2342 nested_vmx_entry_ctls_high);
2344 case MSR_IA32_VMX_MISC:
2345 *pdata = vmx_control_msr(nested_vmx_misc_low,
2346 nested_vmx_misc_high);
2349 * These MSRs specify bits which the guest must keep fixed (on or off)
2350 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2351 * We picked the standard core2 setting.
2353 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2354 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2355 case MSR_IA32_VMX_CR0_FIXED0:
2356 *pdata = VMXON_CR0_ALWAYSON;
2358 case MSR_IA32_VMX_CR0_FIXED1:
2361 case MSR_IA32_VMX_CR4_FIXED0:
2362 *pdata = VMXON_CR4_ALWAYSON;
2364 case MSR_IA32_VMX_CR4_FIXED1:
2367 case MSR_IA32_VMX_VMCS_ENUM:
2370 case MSR_IA32_VMX_PROCBASED_CTLS2:
2371 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2372 nested_vmx_secondary_ctls_high);
2374 case MSR_IA32_VMX_EPT_VPID_CAP:
2375 /* Currently, no nested vpid support */
2376 *pdata = nested_vmx_ept_caps;
2385 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2387 u32 msr_index = msr_info->index;
2388 u64 data = msr_info->data;
2389 bool host_initialized = msr_info->host_initiated;
2391 if (!nested_vmx_allowed(vcpu))
2394 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2395 if (!host_initialized &&
2396 to_vmx(vcpu)->nested.msr_ia32_feature_control
2397 & FEATURE_CONTROL_LOCKED)
2399 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
2404 * No need to treat VMX capability MSRs specially: If we don't handle
2405 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2411 * Reads an msr value (of 'msr_index') into 'pdata'.
2412 * Returns 0 on success, non-0 otherwise.
2413 * Assumes vcpu_load() was already called.
2415 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2418 struct shared_msr_entry *msr;
2421 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2425 switch (msr_index) {
2426 #ifdef CONFIG_X86_64
2428 data = vmcs_readl(GUEST_FS_BASE);
2431 data = vmcs_readl(GUEST_GS_BASE);
2433 case MSR_KERNEL_GS_BASE:
2434 vmx_load_host_state(to_vmx(vcpu));
2435 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2439 return kvm_get_msr_common(vcpu, msr_index, pdata);
2441 data = guest_read_tsc();
2443 case MSR_IA32_SYSENTER_CS:
2444 data = vmcs_read32(GUEST_SYSENTER_CS);
2446 case MSR_IA32_SYSENTER_EIP:
2447 data = vmcs_readl(GUEST_SYSENTER_EIP);
2449 case MSR_IA32_SYSENTER_ESP:
2450 data = vmcs_readl(GUEST_SYSENTER_ESP);
2453 if (!to_vmx(vcpu)->rdtscp_enabled)
2455 /* Otherwise falls through */
2457 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2459 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2464 return kvm_get_msr_common(vcpu, msr_index, pdata);
2472 * Writes msr value into into the appropriate "register".
2473 * Returns 0 on success, non-0 otherwise.
2474 * Assumes vcpu_load() was already called.
2476 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2478 struct vcpu_vmx *vmx = to_vmx(vcpu);
2479 struct shared_msr_entry *msr;
2481 u32 msr_index = msr_info->index;
2482 u64 data = msr_info->data;
2484 switch (msr_index) {
2486 ret = kvm_set_msr_common(vcpu, msr_info);
2488 #ifdef CONFIG_X86_64
2490 vmx_segment_cache_clear(vmx);
2491 vmcs_writel(GUEST_FS_BASE, data);
2494 vmx_segment_cache_clear(vmx);
2495 vmcs_writel(GUEST_GS_BASE, data);
2497 case MSR_KERNEL_GS_BASE:
2498 vmx_load_host_state(vmx);
2499 vmx->msr_guest_kernel_gs_base = data;
2502 case MSR_IA32_SYSENTER_CS:
2503 vmcs_write32(GUEST_SYSENTER_CS, data);
2505 case MSR_IA32_SYSENTER_EIP:
2506 vmcs_writel(GUEST_SYSENTER_EIP, data);
2508 case MSR_IA32_SYSENTER_ESP:
2509 vmcs_writel(GUEST_SYSENTER_ESP, data);
2512 kvm_write_tsc(vcpu, msr_info);
2514 case MSR_IA32_CR_PAT:
2515 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2516 vmcs_write64(GUEST_IA32_PAT, data);
2517 vcpu->arch.pat = data;
2520 ret = kvm_set_msr_common(vcpu, msr_info);
2522 case MSR_IA32_TSC_ADJUST:
2523 ret = kvm_set_msr_common(vcpu, msr_info);
2526 if (!vmx->rdtscp_enabled)
2528 /* Check reserved bit, higher 32 bits should be zero */
2529 if ((data >> 32) != 0)
2531 /* Otherwise falls through */
2533 if (vmx_set_vmx_msr(vcpu, msr_info))
2535 msr = find_msr_entry(vmx, msr_index);
2538 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2540 kvm_set_shared_msr(msr->index, msr->data,
2546 ret = kvm_set_msr_common(vcpu, msr_info);
2552 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2554 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2557 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2560 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2562 case VCPU_EXREG_PDPTR:
2564 ept_save_pdptrs(vcpu);
2571 static __init int cpu_has_kvm_support(void)
2573 return cpu_has_vmx();
2576 static __init int vmx_disabled_by_bios(void)
2580 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2581 if (msr & FEATURE_CONTROL_LOCKED) {
2582 /* launched w/ TXT and VMX disabled */
2583 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2586 /* launched w/o TXT and VMX only enabled w/ TXT */
2587 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2588 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2589 && !tboot_enabled()) {
2590 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2591 "activate TXT before enabling KVM\n");
2594 /* launched w/o TXT and VMX disabled */
2595 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2596 && !tboot_enabled())
2603 static void kvm_cpu_vmxon(u64 addr)
2605 asm volatile (ASM_VMX_VMXON_RAX
2606 : : "a"(&addr), "m"(addr)
2610 static int hardware_enable(void *garbage)
2612 int cpu = raw_smp_processor_id();
2613 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2616 if (read_cr4() & X86_CR4_VMXE)
2619 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2622 * Now we can enable the vmclear operation in kdump
2623 * since the loaded_vmcss_on_cpu list on this cpu
2624 * has been initialized.
2626 * Though the cpu is not in VMX operation now, there
2627 * is no problem to enable the vmclear operation
2628 * for the loaded_vmcss_on_cpu list is empty!
2630 crash_enable_local_vmclear(cpu);
2632 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2634 test_bits = FEATURE_CONTROL_LOCKED;
2635 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2636 if (tboot_enabled())
2637 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2639 if ((old & test_bits) != test_bits) {
2640 /* enable and lock */
2641 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2643 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2645 if (vmm_exclusive) {
2646 kvm_cpu_vmxon(phys_addr);
2650 native_store_gdt(&__get_cpu_var(host_gdt));
2655 static void vmclear_local_loaded_vmcss(void)
2657 int cpu = raw_smp_processor_id();
2658 struct loaded_vmcs *v, *n;
2660 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2661 loaded_vmcss_on_cpu_link)
2662 __loaded_vmcs_clear(v);
2666 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2669 static void kvm_cpu_vmxoff(void)
2671 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2674 static void hardware_disable(void *garbage)
2676 if (vmm_exclusive) {
2677 vmclear_local_loaded_vmcss();
2680 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2683 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2684 u32 msr, u32 *result)
2686 u32 vmx_msr_low, vmx_msr_high;
2687 u32 ctl = ctl_min | ctl_opt;
2689 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2691 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2692 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2694 /* Ensure minimum (required) set of control bits are supported. */
2702 static __init bool allow_1_setting(u32 msr, u32 ctl)
2704 u32 vmx_msr_low, vmx_msr_high;
2706 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2707 return vmx_msr_high & ctl;
2710 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2712 u32 vmx_msr_low, vmx_msr_high;
2713 u32 min, opt, min2, opt2;
2714 u32 _pin_based_exec_control = 0;
2715 u32 _cpu_based_exec_control = 0;
2716 u32 _cpu_based_2nd_exec_control = 0;
2717 u32 _vmexit_control = 0;
2718 u32 _vmentry_control = 0;
2720 min = CPU_BASED_HLT_EXITING |
2721 #ifdef CONFIG_X86_64
2722 CPU_BASED_CR8_LOAD_EXITING |
2723 CPU_BASED_CR8_STORE_EXITING |
2725 CPU_BASED_CR3_LOAD_EXITING |
2726 CPU_BASED_CR3_STORE_EXITING |
2727 CPU_BASED_USE_IO_BITMAPS |
2728 CPU_BASED_MOV_DR_EXITING |
2729 CPU_BASED_USE_TSC_OFFSETING |
2730 CPU_BASED_MWAIT_EXITING |
2731 CPU_BASED_MONITOR_EXITING |
2732 CPU_BASED_INVLPG_EXITING |
2733 CPU_BASED_RDPMC_EXITING;
2735 opt = CPU_BASED_TPR_SHADOW |
2736 CPU_BASED_USE_MSR_BITMAPS |
2737 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2738 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2739 &_cpu_based_exec_control) < 0)
2741 #ifdef CONFIG_X86_64
2742 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2743 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2744 ~CPU_BASED_CR8_STORE_EXITING;
2746 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2748 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2749 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2750 SECONDARY_EXEC_WBINVD_EXITING |
2751 SECONDARY_EXEC_ENABLE_VPID |
2752 SECONDARY_EXEC_ENABLE_EPT |
2753 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2754 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2755 SECONDARY_EXEC_RDTSCP |
2756 SECONDARY_EXEC_ENABLE_INVPCID |
2757 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2758 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2759 SECONDARY_EXEC_SHADOW_VMCS;
2760 if (adjust_vmx_controls(min2, opt2,
2761 MSR_IA32_VMX_PROCBASED_CTLS2,
2762 &_cpu_based_2nd_exec_control) < 0)
2765 #ifndef CONFIG_X86_64
2766 if (!(_cpu_based_2nd_exec_control &
2767 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2768 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2771 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2772 _cpu_based_2nd_exec_control &= ~(
2773 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2774 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2775 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2777 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2778 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2780 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2781 CPU_BASED_CR3_STORE_EXITING |
2782 CPU_BASED_INVLPG_EXITING);
2783 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2784 vmx_capability.ept, vmx_capability.vpid);
2788 #ifdef CONFIG_X86_64
2789 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2791 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2792 VM_EXIT_ACK_INTR_ON_EXIT;
2793 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2794 &_vmexit_control) < 0)
2797 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2798 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2799 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2800 &_pin_based_exec_control) < 0)
2803 if (!(_cpu_based_2nd_exec_control &
2804 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2805 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2806 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2809 opt = VM_ENTRY_LOAD_IA32_PAT;
2810 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2811 &_vmentry_control) < 0)
2814 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2816 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2817 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2820 #ifdef CONFIG_X86_64
2821 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2822 if (vmx_msr_high & (1u<<16))
2826 /* Require Write-Back (WB) memory type for VMCS accesses. */
2827 if (((vmx_msr_high >> 18) & 15) != 6)
2830 vmcs_conf->size = vmx_msr_high & 0x1fff;
2831 vmcs_conf->order = get_order(vmcs_config.size);
2832 vmcs_conf->revision_id = vmx_msr_low;
2834 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2835 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2836 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2837 vmcs_conf->vmexit_ctrl = _vmexit_control;
2838 vmcs_conf->vmentry_ctrl = _vmentry_control;
2840 cpu_has_load_ia32_efer =
2841 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2842 VM_ENTRY_LOAD_IA32_EFER)
2843 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2844 VM_EXIT_LOAD_IA32_EFER);
2846 cpu_has_load_perf_global_ctrl =
2847 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2848 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2849 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2850 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2853 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2854 * but due to arrata below it can't be used. Workaround is to use
2855 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2857 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2862 * BC86,AAY89,BD102 (model 44)
2866 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2867 switch (boot_cpu_data.x86_model) {
2873 cpu_has_load_perf_global_ctrl = false;
2874 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2875 "does not work properly. Using workaround\n");
2885 static struct vmcs *alloc_vmcs_cpu(int cpu)
2887 int node = cpu_to_node(cpu);
2891 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2894 vmcs = page_address(pages);
2895 memset(vmcs, 0, vmcs_config.size);
2896 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2900 static struct vmcs *alloc_vmcs(void)
2902 return alloc_vmcs_cpu(raw_smp_processor_id());
2905 static void free_vmcs(struct vmcs *vmcs)
2907 free_pages((unsigned long)vmcs, vmcs_config.order);
2911 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2913 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2915 if (!loaded_vmcs->vmcs)
2917 loaded_vmcs_clear(loaded_vmcs);
2918 free_vmcs(loaded_vmcs->vmcs);
2919 loaded_vmcs->vmcs = NULL;
2922 static void free_kvm_area(void)
2926 for_each_possible_cpu(cpu) {
2927 free_vmcs(per_cpu(vmxarea, cpu));
2928 per_cpu(vmxarea, cpu) = NULL;
2932 static __init int alloc_kvm_area(void)
2936 for_each_possible_cpu(cpu) {
2939 vmcs = alloc_vmcs_cpu(cpu);
2945 per_cpu(vmxarea, cpu) = vmcs;
2950 static __init int hardware_setup(void)
2952 if (setup_vmcs_config(&vmcs_config) < 0)
2955 if (boot_cpu_has(X86_FEATURE_NX))
2956 kvm_enable_efer_bits(EFER_NX);
2958 if (!cpu_has_vmx_vpid())
2960 if (!cpu_has_vmx_shadow_vmcs())
2961 enable_shadow_vmcs = 0;
2963 if (!cpu_has_vmx_ept() ||
2964 !cpu_has_vmx_ept_4levels()) {
2966 enable_unrestricted_guest = 0;
2967 enable_ept_ad_bits = 0;
2970 if (!cpu_has_vmx_ept_ad_bits())
2971 enable_ept_ad_bits = 0;
2973 if (!cpu_has_vmx_unrestricted_guest())
2974 enable_unrestricted_guest = 0;
2976 if (!cpu_has_vmx_flexpriority())
2977 flexpriority_enabled = 0;
2979 if (!cpu_has_vmx_tpr_shadow())
2980 kvm_x86_ops->update_cr8_intercept = NULL;
2982 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2983 kvm_disable_largepages();
2985 if (!cpu_has_vmx_ple())
2988 if (!cpu_has_vmx_apicv())
2992 kvm_x86_ops->update_cr8_intercept = NULL;
2994 kvm_x86_ops->hwapic_irr_update = NULL;
2995 kvm_x86_ops->deliver_posted_interrupt = NULL;
2996 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3000 nested_vmx_setup_ctls_msrs();
3002 return alloc_kvm_area();
3005 static __exit void hardware_unsetup(void)
3010 static bool emulation_required(struct kvm_vcpu *vcpu)
3012 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3015 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3016 struct kvm_segment *save)
3018 if (!emulate_invalid_guest_state) {
3020 * CS and SS RPL should be equal during guest entry according
3021 * to VMX spec, but in reality it is not always so. Since vcpu
3022 * is in the middle of the transition from real mode to
3023 * protected mode it is safe to assume that RPL 0 is a good
3026 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3027 save->selector &= ~SELECTOR_RPL_MASK;
3028 save->dpl = save->selector & SELECTOR_RPL_MASK;
3031 vmx_set_segment(vcpu, save, seg);
3034 static void enter_pmode(struct kvm_vcpu *vcpu)
3036 unsigned long flags;
3037 struct vcpu_vmx *vmx = to_vmx(vcpu);
3040 * Update real mode segment cache. It may be not up-to-date if sement
3041 * register was written while vcpu was in a guest mode.
3043 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3044 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3045 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3046 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3047 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3048 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3050 vmx->rmode.vm86_active = 0;
3052 vmx_segment_cache_clear(vmx);
3054 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3056 flags = vmcs_readl(GUEST_RFLAGS);
3057 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3058 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3059 vmcs_writel(GUEST_RFLAGS, flags);
3061 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3062 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3064 update_exception_bitmap(vcpu);
3066 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3067 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3068 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3069 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3070 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3071 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3073 /* CPL is always 0 when CPU enters protected mode */
3074 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3078 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3080 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3081 struct kvm_segment var = *save;
3084 if (seg == VCPU_SREG_CS)
3087 if (!emulate_invalid_guest_state) {
3088 var.selector = var.base >> 4;
3089 var.base = var.base & 0xffff0;
3099 if (save->base & 0xf)
3100 printk_once(KERN_WARNING "kvm: segment base is not "
3101 "paragraph aligned when entering "
3102 "protected mode (seg=%d)", seg);
3105 vmcs_write16(sf->selector, var.selector);
3106 vmcs_write32(sf->base, var.base);
3107 vmcs_write32(sf->limit, var.limit);
3108 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3111 static void enter_rmode(struct kvm_vcpu *vcpu)
3113 unsigned long flags;
3114 struct vcpu_vmx *vmx = to_vmx(vcpu);
3116 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3117 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3118 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3119 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3120 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3121 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3122 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3124 vmx->rmode.vm86_active = 1;
3127 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3128 * vcpu. Warn the user that an update is overdue.
3130 if (!vcpu->kvm->arch.tss_addr)
3131 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3132 "called before entering vcpu\n");
3134 vmx_segment_cache_clear(vmx);
3136 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3137 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3138 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3140 flags = vmcs_readl(GUEST_RFLAGS);
3141 vmx->rmode.save_rflags = flags;
3143 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3145 vmcs_writel(GUEST_RFLAGS, flags);
3146 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3147 update_exception_bitmap(vcpu);
3149 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3150 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3151 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3152 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3153 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3154 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3156 kvm_mmu_reset_context(vcpu);
3159 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3161 struct vcpu_vmx *vmx = to_vmx(vcpu);
3162 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3168 * Force kernel_gs_base reloading before EFER changes, as control
3169 * of this msr depends on is_long_mode().
3171 vmx_load_host_state(to_vmx(vcpu));
3172 vcpu->arch.efer = efer;
3173 if (efer & EFER_LMA) {
3174 vmcs_write32(VM_ENTRY_CONTROLS,
3175 vmcs_read32(VM_ENTRY_CONTROLS) |
3176 VM_ENTRY_IA32E_MODE);
3179 vmcs_write32(VM_ENTRY_CONTROLS,
3180 vmcs_read32(VM_ENTRY_CONTROLS) &
3181 ~VM_ENTRY_IA32E_MODE);
3183 msr->data = efer & ~EFER_LME;
3188 #ifdef CONFIG_X86_64
3190 static void enter_lmode(struct kvm_vcpu *vcpu)
3194 vmx_segment_cache_clear(to_vmx(vcpu));
3196 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3197 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3198 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3200 vmcs_write32(GUEST_TR_AR_BYTES,
3201 (guest_tr_ar & ~AR_TYPE_MASK)
3202 | AR_TYPE_BUSY_64_TSS);
3204 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3207 static void exit_lmode(struct kvm_vcpu *vcpu)
3209 vmcs_write32(VM_ENTRY_CONTROLS,
3210 vmcs_read32(VM_ENTRY_CONTROLS)
3211 & ~VM_ENTRY_IA32E_MODE);
3212 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3217 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3219 vpid_sync_context(to_vmx(vcpu));
3221 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3223 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3227 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3229 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3231 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3232 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3235 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3237 if (enable_ept && is_paging(vcpu))
3238 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3239 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3242 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3244 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3246 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3247 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3250 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3252 if (!test_bit(VCPU_EXREG_PDPTR,
3253 (unsigned long *)&vcpu->arch.regs_dirty))
3256 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3257 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3258 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3259 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3260 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3264 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3266 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3267 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3268 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3269 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3270 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3273 __set_bit(VCPU_EXREG_PDPTR,
3274 (unsigned long *)&vcpu->arch.regs_avail);
3275 __set_bit(VCPU_EXREG_PDPTR,
3276 (unsigned long *)&vcpu->arch.regs_dirty);
3279 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3281 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3283 struct kvm_vcpu *vcpu)
3285 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3286 vmx_decache_cr3(vcpu);
3287 if (!(cr0 & X86_CR0_PG)) {
3288 /* From paging/starting to nonpaging */
3289 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3290 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3291 (CPU_BASED_CR3_LOAD_EXITING |
3292 CPU_BASED_CR3_STORE_EXITING));
3293 vcpu->arch.cr0 = cr0;
3294 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3295 } else if (!is_paging(vcpu)) {
3296 /* From nonpaging to paging */
3297 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3298 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3299 ~(CPU_BASED_CR3_LOAD_EXITING |
3300 CPU_BASED_CR3_STORE_EXITING));
3301 vcpu->arch.cr0 = cr0;
3302 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3305 if (!(cr0 & X86_CR0_WP))
3306 *hw_cr0 &= ~X86_CR0_WP;
3309 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3311 struct vcpu_vmx *vmx = to_vmx(vcpu);
3312 unsigned long hw_cr0;
3314 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3315 if (enable_unrestricted_guest)
3316 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3318 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3320 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3323 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3327 #ifdef CONFIG_X86_64
3328 if (vcpu->arch.efer & EFER_LME) {
3329 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3331 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3337 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3339 if (!vcpu->fpu_active)
3340 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3342 vmcs_writel(CR0_READ_SHADOW, cr0);
3343 vmcs_writel(GUEST_CR0, hw_cr0);
3344 vcpu->arch.cr0 = cr0;
3346 /* depends on vcpu->arch.cr0 to be set to a new value */
3347 vmx->emulation_required = emulation_required(vcpu);
3350 static u64 construct_eptp(unsigned long root_hpa)
3354 /* TODO write the value reading from MSR */
3355 eptp = VMX_EPT_DEFAULT_MT |
3356 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3357 if (enable_ept_ad_bits)
3358 eptp |= VMX_EPT_AD_ENABLE_BIT;
3359 eptp |= (root_hpa & PAGE_MASK);
3364 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3366 unsigned long guest_cr3;
3371 eptp = construct_eptp(cr3);
3372 vmcs_write64(EPT_POINTER, eptp);
3373 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3374 vcpu->kvm->arch.ept_identity_map_addr;
3375 ept_load_pdptrs(vcpu);
3378 vmx_flush_tlb(vcpu);
3379 vmcs_writel(GUEST_CR3, guest_cr3);
3382 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3384 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3385 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3387 if (cr4 & X86_CR4_VMXE) {
3389 * To use VMXON (and later other VMX instructions), a guest
3390 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3391 * So basically the check on whether to allow nested VMX
3394 if (!nested_vmx_allowed(vcpu))
3397 if (to_vmx(vcpu)->nested.vmxon &&
3398 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3401 vcpu->arch.cr4 = cr4;
3403 if (!is_paging(vcpu)) {
3404 hw_cr4 &= ~X86_CR4_PAE;
3405 hw_cr4 |= X86_CR4_PSE;
3407 * SMEP is disabled if CPU is in non-paging mode in
3408 * hardware. However KVM always uses paging mode to
3409 * emulate guest non-paging mode with TDP.
3410 * To emulate this behavior, SMEP needs to be manually
3411 * disabled when guest switches to non-paging mode.
3413 hw_cr4 &= ~X86_CR4_SMEP;
3414 } else if (!(cr4 & X86_CR4_PAE)) {
3415 hw_cr4 &= ~X86_CR4_PAE;
3419 vmcs_writel(CR4_READ_SHADOW, cr4);
3420 vmcs_writel(GUEST_CR4, hw_cr4);
3424 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3425 struct kvm_segment *var, int seg)
3427 struct vcpu_vmx *vmx = to_vmx(vcpu);
3430 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3431 *var = vmx->rmode.segs[seg];
3432 if (seg == VCPU_SREG_TR
3433 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3435 var->base = vmx_read_guest_seg_base(vmx, seg);
3436 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3439 var->base = vmx_read_guest_seg_base(vmx, seg);
3440 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3441 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3442 ar = vmx_read_guest_seg_ar(vmx, seg);
3443 var->unusable = (ar >> 16) & 1;
3444 var->type = ar & 15;
3445 var->s = (ar >> 4) & 1;
3446 var->dpl = (ar >> 5) & 3;
3448 * Some userspaces do not preserve unusable property. Since usable
3449 * segment has to be present according to VMX spec we can use present
3450 * property to amend userspace bug by making unusable segment always
3451 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3452 * segment as unusable.
3454 var->present = !var->unusable;
3455 var->avl = (ar >> 12) & 1;
3456 var->l = (ar >> 13) & 1;
3457 var->db = (ar >> 14) & 1;
3458 var->g = (ar >> 15) & 1;
3461 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3463 struct kvm_segment s;
3465 if (to_vmx(vcpu)->rmode.vm86_active) {
3466 vmx_get_segment(vcpu, &s, seg);
3469 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3472 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3474 struct vcpu_vmx *vmx = to_vmx(vcpu);
3476 if (!is_protmode(vcpu))
3479 if (!is_long_mode(vcpu)
3480 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3483 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3484 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3485 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3492 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3496 if (var->unusable || !var->present)
3499 ar = var->type & 15;
3500 ar |= (var->s & 1) << 4;
3501 ar |= (var->dpl & 3) << 5;
3502 ar |= (var->present & 1) << 7;
3503 ar |= (var->avl & 1) << 12;
3504 ar |= (var->l & 1) << 13;
3505 ar |= (var->db & 1) << 14;
3506 ar |= (var->g & 1) << 15;
3512 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3513 struct kvm_segment *var, int seg)
3515 struct vcpu_vmx *vmx = to_vmx(vcpu);
3516 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3518 vmx_segment_cache_clear(vmx);
3519 if (seg == VCPU_SREG_CS)
3520 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3522 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3523 vmx->rmode.segs[seg] = *var;
3524 if (seg == VCPU_SREG_TR)
3525 vmcs_write16(sf->selector, var->selector);
3527 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3531 vmcs_writel(sf->base, var->base);
3532 vmcs_write32(sf->limit, var->limit);
3533 vmcs_write16(sf->selector, var->selector);
3536 * Fix the "Accessed" bit in AR field of segment registers for older
3538 * IA32 arch specifies that at the time of processor reset the
3539 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3540 * is setting it to 0 in the userland code. This causes invalid guest
3541 * state vmexit when "unrestricted guest" mode is turned on.
3542 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3543 * tree. Newer qemu binaries with that qemu fix would not need this
3546 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3547 var->type |= 0x1; /* Accessed */
3549 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3552 vmx->emulation_required |= emulation_required(vcpu);
3555 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3557 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3559 *db = (ar >> 14) & 1;
3560 *l = (ar >> 13) & 1;
3563 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3565 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3566 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3569 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3571 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3572 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3575 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3577 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3578 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3581 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3583 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3584 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3587 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3589 struct kvm_segment var;
3592 vmx_get_segment(vcpu, &var, seg);
3594 if (seg == VCPU_SREG_CS)
3596 ar = vmx_segment_access_rights(&var);
3598 if (var.base != (var.selector << 4))
3600 if (var.limit != 0xffff)
3608 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3610 struct kvm_segment cs;
3611 unsigned int cs_rpl;
3613 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3614 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3618 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3622 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3623 if (cs.dpl > cs_rpl)
3626 if (cs.dpl != cs_rpl)
3632 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3636 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3638 struct kvm_segment ss;
3639 unsigned int ss_rpl;
3641 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3642 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3646 if (ss.type != 3 && ss.type != 7)
3650 if (ss.dpl != ss_rpl) /* DPL != RPL */
3658 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3660 struct kvm_segment var;
3663 vmx_get_segment(vcpu, &var, seg);
3664 rpl = var.selector & SELECTOR_RPL_MASK;
3672 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3673 if (var.dpl < rpl) /* DPL < RPL */
3677 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3683 static bool tr_valid(struct kvm_vcpu *vcpu)
3685 struct kvm_segment tr;
3687 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3691 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3693 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3701 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3703 struct kvm_segment ldtr;
3705 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3709 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3719 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3721 struct kvm_segment cs, ss;
3723 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3724 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3726 return ((cs.selector & SELECTOR_RPL_MASK) ==
3727 (ss.selector & SELECTOR_RPL_MASK));
3731 * Check if guest state is valid. Returns true if valid, false if
3733 * We assume that registers are always usable
3735 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3737 if (enable_unrestricted_guest)
3740 /* real mode guest state checks */
3741 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3742 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3744 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3746 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3748 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3750 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3752 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3755 /* protected mode guest state checks */
3756 if (!cs_ss_rpl_check(vcpu))
3758 if (!code_segment_valid(vcpu))
3760 if (!stack_segment_valid(vcpu))
3762 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3764 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3766 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3768 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3770 if (!tr_valid(vcpu))
3772 if (!ldtr_valid(vcpu))
3776 * - Add checks on RIP
3777 * - Add checks on RFLAGS
3783 static int init_rmode_tss(struct kvm *kvm)
3787 int r, idx, ret = 0;
3789 idx = srcu_read_lock(&kvm->srcu);
3790 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3791 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3794 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3795 r = kvm_write_guest_page(kvm, fn++, &data,
3796 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3799 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3802 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3806 r = kvm_write_guest_page(kvm, fn, &data,
3807 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3814 srcu_read_unlock(&kvm->srcu, idx);
3818 static int init_rmode_identity_map(struct kvm *kvm)
3821 pfn_t identity_map_pfn;
3826 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3827 printk(KERN_ERR "EPT: identity-mapping pagetable "
3828 "haven't been allocated!\n");
3831 if (likely(kvm->arch.ept_identity_pagetable_done))
3834 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3835 idx = srcu_read_lock(&kvm->srcu);
3836 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3839 /* Set up identity-mapping pagetable for EPT in real mode */
3840 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3841 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3842 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3843 r = kvm_write_guest_page(kvm, identity_map_pfn,
3844 &tmp, i * sizeof(tmp), sizeof(tmp));
3848 kvm->arch.ept_identity_pagetable_done = true;
3851 srcu_read_unlock(&kvm->srcu, idx);
3855 static void seg_setup(int seg)
3857 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3860 vmcs_write16(sf->selector, 0);
3861 vmcs_writel(sf->base, 0);
3862 vmcs_write32(sf->limit, 0xffff);
3864 if (seg == VCPU_SREG_CS)
3865 ar |= 0x08; /* code segment */
3867 vmcs_write32(sf->ar_bytes, ar);
3870 static int alloc_apic_access_page(struct kvm *kvm)
3873 struct kvm_userspace_memory_region kvm_userspace_mem;
3876 mutex_lock(&kvm->slots_lock);
3877 if (kvm->arch.apic_access_page)
3879 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3880 kvm_userspace_mem.flags = 0;
3881 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3882 kvm_userspace_mem.memory_size = PAGE_SIZE;
3883 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3887 page = gfn_to_page(kvm, 0xfee00);
3888 if (is_error_page(page)) {
3893 kvm->arch.apic_access_page = page;
3895 mutex_unlock(&kvm->slots_lock);
3899 static int alloc_identity_pagetable(struct kvm *kvm)
3902 struct kvm_userspace_memory_region kvm_userspace_mem;
3905 mutex_lock(&kvm->slots_lock);
3906 if (kvm->arch.ept_identity_pagetable)
3908 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3909 kvm_userspace_mem.flags = 0;
3910 kvm_userspace_mem.guest_phys_addr =
3911 kvm->arch.ept_identity_map_addr;
3912 kvm_userspace_mem.memory_size = PAGE_SIZE;
3913 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3917 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3918 if (is_error_page(page)) {
3923 kvm->arch.ept_identity_pagetable = page;
3925 mutex_unlock(&kvm->slots_lock);
3929 static void allocate_vpid(struct vcpu_vmx *vmx)
3936 spin_lock(&vmx_vpid_lock);
3937 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3938 if (vpid < VMX_NR_VPIDS) {
3940 __set_bit(vpid, vmx_vpid_bitmap);
3942 spin_unlock(&vmx_vpid_lock);
3945 static void free_vpid(struct vcpu_vmx *vmx)
3949 spin_lock(&vmx_vpid_lock);
3951 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3952 spin_unlock(&vmx_vpid_lock);
3955 #define MSR_TYPE_R 1
3956 #define MSR_TYPE_W 2
3957 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3960 int f = sizeof(unsigned long);
3962 if (!cpu_has_vmx_msr_bitmap())
3966 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3967 * have the write-low and read-high bitmap offsets the wrong way round.
3968 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3970 if (msr <= 0x1fff) {
3971 if (type & MSR_TYPE_R)
3973 __clear_bit(msr, msr_bitmap + 0x000 / f);
3975 if (type & MSR_TYPE_W)
3977 __clear_bit(msr, msr_bitmap + 0x800 / f);
3979 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3981 if (type & MSR_TYPE_R)
3983 __clear_bit(msr, msr_bitmap + 0x400 / f);
3985 if (type & MSR_TYPE_W)
3987 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3992 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3995 int f = sizeof(unsigned long);
3997 if (!cpu_has_vmx_msr_bitmap())
4001 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4002 * have the write-low and read-high bitmap offsets the wrong way round.
4003 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4005 if (msr <= 0x1fff) {
4006 if (type & MSR_TYPE_R)
4008 __set_bit(msr, msr_bitmap + 0x000 / f);
4010 if (type & MSR_TYPE_W)
4012 __set_bit(msr, msr_bitmap + 0x800 / f);
4014 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4016 if (type & MSR_TYPE_R)
4018 __set_bit(msr, msr_bitmap + 0x400 / f);
4020 if (type & MSR_TYPE_W)
4022 __set_bit(msr, msr_bitmap + 0xc00 / f);
4027 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4030 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4031 msr, MSR_TYPE_R | MSR_TYPE_W);
4032 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4033 msr, MSR_TYPE_R | MSR_TYPE_W);
4036 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4038 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4040 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4044 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4046 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4048 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4052 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4054 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4056 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4060 static int vmx_vm_has_apicv(struct kvm *kvm)
4062 return enable_apicv && irqchip_in_kernel(kvm);
4066 * Send interrupt to vcpu via posted interrupt way.
4067 * 1. If target vcpu is running(non-root mode), send posted interrupt
4068 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4069 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4070 * interrupt from PIR in next vmentry.
4072 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4074 struct vcpu_vmx *vmx = to_vmx(vcpu);
4077 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4080 r = pi_test_and_set_on(&vmx->pi_desc);
4081 kvm_make_request(KVM_REQ_EVENT, vcpu);
4083 if (!r && (vcpu->mode == IN_GUEST_MODE))
4084 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4085 POSTED_INTR_VECTOR);
4088 kvm_vcpu_kick(vcpu);
4091 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4093 struct vcpu_vmx *vmx = to_vmx(vcpu);
4095 if (!pi_test_and_clear_on(&vmx->pi_desc))
4098 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4101 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4107 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4108 * will not change in the lifetime of the guest.
4109 * Note that host-state that does change is set elsewhere. E.g., host-state
4110 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4112 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4118 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4119 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4120 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4122 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4123 #ifdef CONFIG_X86_64
4125 * Load null selectors, so we can avoid reloading them in
4126 * __vmx_load_host_state(), in case userspace uses the null selectors
4127 * too (the expected case).
4129 vmcs_write16(HOST_DS_SELECTOR, 0);
4130 vmcs_write16(HOST_ES_SELECTOR, 0);
4132 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4133 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4135 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4136 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4138 native_store_idt(&dt);
4139 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4140 vmx->host_idt_base = dt.address;
4142 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4144 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4145 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4146 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4147 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4149 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4150 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4151 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4155 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4157 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4159 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4160 if (is_guest_mode(&vmx->vcpu))
4161 vmx->vcpu.arch.cr4_guest_owned_bits &=
4162 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4163 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4166 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4168 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4170 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4171 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4172 return pin_based_exec_ctrl;
4175 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4177 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4178 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4179 exec_control &= ~CPU_BASED_TPR_SHADOW;
4180 #ifdef CONFIG_X86_64
4181 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4182 CPU_BASED_CR8_LOAD_EXITING;
4186 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4187 CPU_BASED_CR3_LOAD_EXITING |
4188 CPU_BASED_INVLPG_EXITING;
4189 return exec_control;
4192 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4194 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4195 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4196 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4198 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4200 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4201 enable_unrestricted_guest = 0;
4202 /* Enable INVPCID for non-ept guests may cause performance regression. */
4203 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4205 if (!enable_unrestricted_guest)
4206 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4208 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4209 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4210 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4211 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4212 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4213 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4215 We can NOT enable shadow_vmcs here because we don't have yet
4218 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4219 return exec_control;
4222 static void ept_set_mmio_spte_mask(void)
4225 * EPT Misconfigurations can be generated if the value of bits 2:0
4226 * of an EPT paging-structure entry is 110b (write/execute).
4227 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4230 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4234 * Sets up the vmcs for emulated real mode.
4236 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4238 #ifdef CONFIG_X86_64
4244 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4245 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4247 if (enable_shadow_vmcs) {
4248 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4249 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4251 if (cpu_has_vmx_msr_bitmap())
4252 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4254 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4257 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4259 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4261 if (cpu_has_secondary_exec_ctrls()) {
4262 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4263 vmx_secondary_exec_control(vmx));
4266 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4267 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4268 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4269 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4270 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4272 vmcs_write16(GUEST_INTR_STATUS, 0);
4274 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4275 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4279 vmcs_write32(PLE_GAP, ple_gap);
4280 vmcs_write32(PLE_WINDOW, ple_window);
4283 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4284 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4285 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4287 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4288 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4289 vmx_set_constant_host_state(vmx);
4290 #ifdef CONFIG_X86_64
4291 rdmsrl(MSR_FS_BASE, a);
4292 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4293 rdmsrl(MSR_GS_BASE, a);
4294 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4296 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4297 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4300 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4301 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4302 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4303 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4304 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4306 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4307 u32 msr_low, msr_high;
4309 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4310 host_pat = msr_low | ((u64) msr_high << 32);
4311 /* Write the default value follow host pat */
4312 vmcs_write64(GUEST_IA32_PAT, host_pat);
4313 /* Keep arch.pat sync with GUEST_IA32_PAT */
4314 vmx->vcpu.arch.pat = host_pat;
4317 for (i = 0; i < NR_VMX_MSR; ++i) {
4318 u32 index = vmx_msr_index[i];
4319 u32 data_low, data_high;
4322 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4324 if (wrmsr_safe(index, data_low, data_high) < 0)
4326 vmx->guest_msrs[j].index = i;
4327 vmx->guest_msrs[j].data = 0;
4328 vmx->guest_msrs[j].mask = -1ull;
4332 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4334 /* 22.2.1, 20.8.1 */
4335 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4337 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4338 set_cr4_guest_host_mask(vmx);
4343 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4345 struct vcpu_vmx *vmx = to_vmx(vcpu);
4348 vmx->rmode.vm86_active = 0;
4350 vmx->soft_vnmi_blocked = 0;
4352 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4353 kvm_set_cr8(&vmx->vcpu, 0);
4354 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4355 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4356 msr |= MSR_IA32_APICBASE_BSP;
4357 kvm_set_apic_base(&vmx->vcpu, msr);
4359 vmx_segment_cache_clear(vmx);
4361 seg_setup(VCPU_SREG_CS);
4362 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4363 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4365 seg_setup(VCPU_SREG_DS);
4366 seg_setup(VCPU_SREG_ES);
4367 seg_setup(VCPU_SREG_FS);
4368 seg_setup(VCPU_SREG_GS);
4369 seg_setup(VCPU_SREG_SS);
4371 vmcs_write16(GUEST_TR_SELECTOR, 0);
4372 vmcs_writel(GUEST_TR_BASE, 0);
4373 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4374 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4376 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4377 vmcs_writel(GUEST_LDTR_BASE, 0);
4378 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4379 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4381 vmcs_write32(GUEST_SYSENTER_CS, 0);
4382 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4383 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4385 vmcs_writel(GUEST_RFLAGS, 0x02);
4386 kvm_rip_write(vcpu, 0xfff0);
4388 vmcs_writel(GUEST_GDTR_BASE, 0);
4389 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4391 vmcs_writel(GUEST_IDTR_BASE, 0);
4392 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4394 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4395 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4396 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4398 /* Special registers */
4399 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4403 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4405 if (cpu_has_vmx_tpr_shadow()) {
4406 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4407 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4408 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4409 __pa(vmx->vcpu.arch.apic->regs));
4410 vmcs_write32(TPR_THRESHOLD, 0);
4413 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4414 vmcs_write64(APIC_ACCESS_ADDR,
4415 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4417 if (vmx_vm_has_apicv(vcpu->kvm))
4418 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4421 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4423 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4424 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4425 vmx_set_cr4(&vmx->vcpu, 0);
4426 vmx_set_efer(&vmx->vcpu, 0);
4427 vmx_fpu_activate(&vmx->vcpu);
4428 update_exception_bitmap(&vmx->vcpu);
4430 vpid_sync_context(vmx);
4434 * In nested virtualization, check if L1 asked to exit on external interrupts.
4435 * For most existing hypervisors, this will always return true.
4437 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4439 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4440 PIN_BASED_EXT_INTR_MASK;
4443 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4445 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4446 PIN_BASED_NMI_EXITING;
4449 static int enable_irq_window(struct kvm_vcpu *vcpu)
4451 u32 cpu_based_vm_exec_control;
4453 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4455 * We get here if vmx_interrupt_allowed() said we can't
4456 * inject to L1 now because L2 must run. The caller will have
4457 * to make L2 exit right after entry, so we can inject to L1
4462 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4463 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4464 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4468 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4470 u32 cpu_based_vm_exec_control;
4472 if (!cpu_has_virtual_nmis())
4473 return enable_irq_window(vcpu);
4475 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4476 return enable_irq_window(vcpu);
4478 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4479 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4480 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4484 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4486 struct vcpu_vmx *vmx = to_vmx(vcpu);
4488 int irq = vcpu->arch.interrupt.nr;
4490 trace_kvm_inj_virq(irq);
4492 ++vcpu->stat.irq_injections;
4493 if (vmx->rmode.vm86_active) {
4495 if (vcpu->arch.interrupt.soft)
4496 inc_eip = vcpu->arch.event_exit_inst_len;
4497 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4498 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4501 intr = irq | INTR_INFO_VALID_MASK;
4502 if (vcpu->arch.interrupt.soft) {
4503 intr |= INTR_TYPE_SOFT_INTR;
4504 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4505 vmx->vcpu.arch.event_exit_inst_len);
4507 intr |= INTR_TYPE_EXT_INTR;
4508 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4511 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4513 struct vcpu_vmx *vmx = to_vmx(vcpu);
4515 if (is_guest_mode(vcpu))
4518 if (!cpu_has_virtual_nmis()) {
4520 * Tracking the NMI-blocked state in software is built upon
4521 * finding the next open IRQ window. This, in turn, depends on
4522 * well-behaving guests: They have to keep IRQs disabled at
4523 * least as long as the NMI handler runs. Otherwise we may
4524 * cause NMI nesting, maybe breaking the guest. But as this is
4525 * highly unlikely, we can live with the residual risk.
4527 vmx->soft_vnmi_blocked = 1;
4528 vmx->vnmi_blocked_time = 0;
4531 ++vcpu->stat.nmi_injections;
4532 vmx->nmi_known_unmasked = false;
4533 if (vmx->rmode.vm86_active) {
4534 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4535 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4538 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4539 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4542 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4544 if (!cpu_has_virtual_nmis())
4545 return to_vmx(vcpu)->soft_vnmi_blocked;
4546 if (to_vmx(vcpu)->nmi_known_unmasked)
4548 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4551 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4553 struct vcpu_vmx *vmx = to_vmx(vcpu);
4555 if (!cpu_has_virtual_nmis()) {
4556 if (vmx->soft_vnmi_blocked != masked) {
4557 vmx->soft_vnmi_blocked = masked;
4558 vmx->vnmi_blocked_time = 0;
4561 vmx->nmi_known_unmasked = !masked;
4563 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4564 GUEST_INTR_STATE_NMI);
4566 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4567 GUEST_INTR_STATE_NMI);
4571 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4573 if (is_guest_mode(vcpu)) {
4574 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4576 if (to_vmx(vcpu)->nested.nested_run_pending)
4578 if (nested_exit_on_nmi(vcpu)) {
4579 nested_vmx_vmexit(vcpu);
4580 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4581 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4582 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4584 * The NMI-triggered VM exit counts as injection:
4585 * clear this one and block further NMIs.
4587 vcpu->arch.nmi_pending = 0;
4588 vmx_set_nmi_mask(vcpu, true);
4593 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4596 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4597 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4598 | GUEST_INTR_STATE_NMI));
4601 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4603 if (is_guest_mode(vcpu)) {
4604 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4606 if (to_vmx(vcpu)->nested.nested_run_pending)
4608 if (nested_exit_on_intr(vcpu)) {
4609 nested_vmx_vmexit(vcpu);
4610 vmcs12->vm_exit_reason =
4611 EXIT_REASON_EXTERNAL_INTERRUPT;
4612 vmcs12->vm_exit_intr_info = 0;
4614 * fall through to normal code, but now in L1, not L2
4619 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4620 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4621 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4624 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4627 struct kvm_userspace_memory_region tss_mem = {
4628 .slot = TSS_PRIVATE_MEMSLOT,
4629 .guest_phys_addr = addr,
4630 .memory_size = PAGE_SIZE * 3,
4634 ret = kvm_set_memory_region(kvm, &tss_mem);
4637 kvm->arch.tss_addr = addr;
4638 if (!init_rmode_tss(kvm))
4644 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4649 * Update instruction length as we may reinject the exception
4650 * from user space while in guest debugging mode.
4652 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4653 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4654 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4658 if (vcpu->guest_debug &
4659 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4676 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4677 int vec, u32 err_code)
4680 * Instruction with address size override prefix opcode 0x67
4681 * Cause the #SS fault with 0 error code in VM86 mode.
4683 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4684 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4685 if (vcpu->arch.halt_request) {
4686 vcpu->arch.halt_request = 0;
4687 return kvm_emulate_halt(vcpu);
4695 * Forward all other exceptions that are valid in real mode.
4696 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4697 * the required debugging infrastructure rework.
4699 kvm_queue_exception(vcpu, vec);
4704 * Trigger machine check on the host. We assume all the MSRs are already set up
4705 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4706 * We pass a fake environment to the machine check handler because we want
4707 * the guest to be always treated like user space, no matter what context
4708 * it used internally.
4710 static void kvm_machine_check(void)
4712 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4713 struct pt_regs regs = {
4714 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4715 .flags = X86_EFLAGS_IF,
4718 do_machine_check(®s, 0);
4722 static int handle_machine_check(struct kvm_vcpu *vcpu)
4724 /* already handled by vcpu_run */
4728 static int handle_exception(struct kvm_vcpu *vcpu)
4730 struct vcpu_vmx *vmx = to_vmx(vcpu);
4731 struct kvm_run *kvm_run = vcpu->run;
4732 u32 intr_info, ex_no, error_code;
4733 unsigned long cr2, rip, dr6;
4735 enum emulation_result er;
4737 vect_info = vmx->idt_vectoring_info;
4738 intr_info = vmx->exit_intr_info;
4740 if (is_machine_check(intr_info))
4741 return handle_machine_check(vcpu);
4743 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4744 return 1; /* already handled by vmx_vcpu_run() */
4746 if (is_no_device(intr_info)) {
4747 vmx_fpu_activate(vcpu);
4751 if (is_invalid_opcode(intr_info)) {
4752 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4753 if (er != EMULATE_DONE)
4754 kvm_queue_exception(vcpu, UD_VECTOR);
4759 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4760 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4763 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4764 * MMIO, it is better to report an internal error.
4765 * See the comments in vmx_handle_exit.
4767 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4768 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4769 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4770 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4771 vcpu->run->internal.ndata = 2;
4772 vcpu->run->internal.data[0] = vect_info;
4773 vcpu->run->internal.data[1] = intr_info;
4777 if (is_page_fault(intr_info)) {
4778 /* EPT won't cause page fault directly */
4780 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4781 trace_kvm_page_fault(cr2, error_code);
4783 if (kvm_event_needs_reinjection(vcpu))
4784 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4785 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4788 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4790 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4791 return handle_rmode_exception(vcpu, ex_no, error_code);
4795 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4796 if (!(vcpu->guest_debug &
4797 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4798 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4799 kvm_queue_exception(vcpu, DB_VECTOR);
4802 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4803 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4807 * Update instruction length as we may reinject #BP from
4808 * user space while in guest debugging mode. Reading it for
4809 * #DB as well causes no harm, it is not used in that case.
4811 vmx->vcpu.arch.event_exit_inst_len =
4812 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4813 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4814 rip = kvm_rip_read(vcpu);
4815 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4816 kvm_run->debug.arch.exception = ex_no;
4819 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4820 kvm_run->ex.exception = ex_no;
4821 kvm_run->ex.error_code = error_code;
4827 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4829 ++vcpu->stat.irq_exits;
4833 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4835 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4839 static int handle_io(struct kvm_vcpu *vcpu)
4841 unsigned long exit_qualification;
4842 int size, in, string;
4845 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4846 string = (exit_qualification & 16) != 0;
4847 in = (exit_qualification & 8) != 0;
4849 ++vcpu->stat.io_exits;
4852 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4854 port = exit_qualification >> 16;
4855 size = (exit_qualification & 7) + 1;
4856 skip_emulated_instruction(vcpu);
4858 return kvm_fast_pio_out(vcpu, size, port);
4862 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4865 * Patch in the VMCALL instruction:
4867 hypercall[0] = 0x0f;
4868 hypercall[1] = 0x01;
4869 hypercall[2] = 0xc1;
4872 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4873 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4875 if (is_guest_mode(vcpu)) {
4876 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4877 unsigned long orig_val = val;
4880 * We get here when L2 changed cr0 in a way that did not change
4881 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4882 * but did change L0 shadowed bits. So we first calculate the
4883 * effective cr0 value that L1 would like to write into the
4884 * hardware. It consists of the L2-owned bits from the new
4885 * value combined with the L1-owned bits from L1's guest_cr0.
4887 val = (val & ~vmcs12->cr0_guest_host_mask) |
4888 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4890 /* TODO: will have to take unrestricted guest mode into
4892 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4895 if (kvm_set_cr0(vcpu, val))
4897 vmcs_writel(CR0_READ_SHADOW, orig_val);
4900 if (to_vmx(vcpu)->nested.vmxon &&
4901 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4903 return kvm_set_cr0(vcpu, val);
4907 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4909 if (is_guest_mode(vcpu)) {
4910 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4911 unsigned long orig_val = val;
4913 /* analogously to handle_set_cr0 */
4914 val = (val & ~vmcs12->cr4_guest_host_mask) |
4915 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4916 if (kvm_set_cr4(vcpu, val))
4918 vmcs_writel(CR4_READ_SHADOW, orig_val);
4921 return kvm_set_cr4(vcpu, val);
4924 /* called to set cr0 as approriate for clts instruction exit. */
4925 static void handle_clts(struct kvm_vcpu *vcpu)
4927 if (is_guest_mode(vcpu)) {
4929 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4930 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4931 * just pretend it's off (also in arch.cr0 for fpu_activate).
4933 vmcs_writel(CR0_READ_SHADOW,
4934 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4935 vcpu->arch.cr0 &= ~X86_CR0_TS;
4937 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4940 static int handle_cr(struct kvm_vcpu *vcpu)
4942 unsigned long exit_qualification, val;
4947 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4948 cr = exit_qualification & 15;
4949 reg = (exit_qualification >> 8) & 15;
4950 switch ((exit_qualification >> 4) & 3) {
4951 case 0: /* mov to cr */
4952 val = kvm_register_read(vcpu, reg);
4953 trace_kvm_cr_write(cr, val);
4956 err = handle_set_cr0(vcpu, val);
4957 kvm_complete_insn_gp(vcpu, err);
4960 err = kvm_set_cr3(vcpu, val);
4961 kvm_complete_insn_gp(vcpu, err);
4964 err = handle_set_cr4(vcpu, val);
4965 kvm_complete_insn_gp(vcpu, err);
4968 u8 cr8_prev = kvm_get_cr8(vcpu);
4969 u8 cr8 = kvm_register_read(vcpu, reg);
4970 err = kvm_set_cr8(vcpu, cr8);
4971 kvm_complete_insn_gp(vcpu, err);
4972 if (irqchip_in_kernel(vcpu->kvm))
4974 if (cr8_prev <= cr8)
4976 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4983 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4984 skip_emulated_instruction(vcpu);
4985 vmx_fpu_activate(vcpu);
4987 case 1: /*mov from cr*/
4990 val = kvm_read_cr3(vcpu);
4991 kvm_register_write(vcpu, reg, val);
4992 trace_kvm_cr_read(cr, val);
4993 skip_emulated_instruction(vcpu);
4996 val = kvm_get_cr8(vcpu);
4997 kvm_register_write(vcpu, reg, val);
4998 trace_kvm_cr_read(cr, val);
4999 skip_emulated_instruction(vcpu);
5004 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5005 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5006 kvm_lmsw(vcpu, val);
5008 skip_emulated_instruction(vcpu);
5013 vcpu->run->exit_reason = 0;
5014 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5015 (int)(exit_qualification >> 4) & 3, cr);
5019 static int handle_dr(struct kvm_vcpu *vcpu)
5021 unsigned long exit_qualification;
5024 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5025 if (!kvm_require_cpl(vcpu, 0))
5027 dr = vmcs_readl(GUEST_DR7);
5030 * As the vm-exit takes precedence over the debug trap, we
5031 * need to emulate the latter, either for the host or the
5032 * guest debugging itself.
5034 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5035 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5036 vcpu->run->debug.arch.dr7 = dr;
5037 vcpu->run->debug.arch.pc =
5038 vmcs_readl(GUEST_CS_BASE) +
5039 vmcs_readl(GUEST_RIP);
5040 vcpu->run->debug.arch.exception = DB_VECTOR;
5041 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5044 vcpu->arch.dr7 &= ~DR7_GD;
5045 vcpu->arch.dr6 |= DR6_BD;
5046 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5047 kvm_queue_exception(vcpu, DB_VECTOR);
5052 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5053 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5054 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5055 if (exit_qualification & TYPE_MOV_FROM_DR) {
5057 if (!kvm_get_dr(vcpu, dr, &val))
5058 kvm_register_write(vcpu, reg, val);
5060 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5061 skip_emulated_instruction(vcpu);
5065 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5067 vmcs_writel(GUEST_DR7, val);
5070 static int handle_cpuid(struct kvm_vcpu *vcpu)
5072 kvm_emulate_cpuid(vcpu);
5076 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5078 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5081 if (vmx_get_msr(vcpu, ecx, &data)) {
5082 trace_kvm_msr_read_ex(ecx);
5083 kvm_inject_gp(vcpu, 0);
5087 trace_kvm_msr_read(ecx, data);
5089 /* FIXME: handling of bits 32:63 of rax, rdx */
5090 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5091 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5092 skip_emulated_instruction(vcpu);
5096 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5098 struct msr_data msr;
5099 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5100 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5101 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5105 msr.host_initiated = false;
5106 if (vmx_set_msr(vcpu, &msr) != 0) {
5107 trace_kvm_msr_write_ex(ecx, data);
5108 kvm_inject_gp(vcpu, 0);
5112 trace_kvm_msr_write(ecx, data);
5113 skip_emulated_instruction(vcpu);
5117 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5119 kvm_make_request(KVM_REQ_EVENT, vcpu);
5123 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5125 u32 cpu_based_vm_exec_control;
5127 /* clear pending irq */
5128 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5129 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5130 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5132 kvm_make_request(KVM_REQ_EVENT, vcpu);
5134 ++vcpu->stat.irq_window_exits;
5137 * If the user space waits to inject interrupts, exit as soon as
5140 if (!irqchip_in_kernel(vcpu->kvm) &&
5141 vcpu->run->request_interrupt_window &&
5142 !kvm_cpu_has_interrupt(vcpu)) {
5143 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5149 static int handle_halt(struct kvm_vcpu *vcpu)
5151 skip_emulated_instruction(vcpu);
5152 return kvm_emulate_halt(vcpu);
5155 static int handle_vmcall(struct kvm_vcpu *vcpu)
5157 skip_emulated_instruction(vcpu);
5158 kvm_emulate_hypercall(vcpu);
5162 static int handle_invd(struct kvm_vcpu *vcpu)
5164 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5167 static int handle_invlpg(struct kvm_vcpu *vcpu)
5169 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5171 kvm_mmu_invlpg(vcpu, exit_qualification);
5172 skip_emulated_instruction(vcpu);
5176 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5180 err = kvm_rdpmc(vcpu);
5181 kvm_complete_insn_gp(vcpu, err);
5186 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5188 skip_emulated_instruction(vcpu);
5189 kvm_emulate_wbinvd(vcpu);
5193 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5195 u64 new_bv = kvm_read_edx_eax(vcpu);
5196 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5198 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5199 skip_emulated_instruction(vcpu);
5203 static int handle_apic_access(struct kvm_vcpu *vcpu)
5205 if (likely(fasteoi)) {
5206 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5207 int access_type, offset;
5209 access_type = exit_qualification & APIC_ACCESS_TYPE;
5210 offset = exit_qualification & APIC_ACCESS_OFFSET;
5212 * Sane guest uses MOV to write EOI, with written value
5213 * not cared. So make a short-circuit here by avoiding
5214 * heavy instruction emulation.
5216 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5217 (offset == APIC_EOI)) {
5218 kvm_lapic_set_eoi(vcpu);
5219 skip_emulated_instruction(vcpu);
5223 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5226 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5228 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5229 int vector = exit_qualification & 0xff;
5231 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5232 kvm_apic_set_eoi_accelerated(vcpu, vector);
5236 static int handle_apic_write(struct kvm_vcpu *vcpu)
5238 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5239 u32 offset = exit_qualification & 0xfff;
5241 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5242 kvm_apic_write_nodecode(vcpu, offset);
5246 static int handle_task_switch(struct kvm_vcpu *vcpu)
5248 struct vcpu_vmx *vmx = to_vmx(vcpu);
5249 unsigned long exit_qualification;
5250 bool has_error_code = false;
5253 int reason, type, idt_v, idt_index;
5255 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5256 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5257 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5259 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5261 reason = (u32)exit_qualification >> 30;
5262 if (reason == TASK_SWITCH_GATE && idt_v) {
5264 case INTR_TYPE_NMI_INTR:
5265 vcpu->arch.nmi_injected = false;
5266 vmx_set_nmi_mask(vcpu, true);
5268 case INTR_TYPE_EXT_INTR:
5269 case INTR_TYPE_SOFT_INTR:
5270 kvm_clear_interrupt_queue(vcpu);
5272 case INTR_TYPE_HARD_EXCEPTION:
5273 if (vmx->idt_vectoring_info &
5274 VECTORING_INFO_DELIVER_CODE_MASK) {
5275 has_error_code = true;
5277 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5280 case INTR_TYPE_SOFT_EXCEPTION:
5281 kvm_clear_exception_queue(vcpu);
5287 tss_selector = exit_qualification;
5289 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5290 type != INTR_TYPE_EXT_INTR &&
5291 type != INTR_TYPE_NMI_INTR))
5292 skip_emulated_instruction(vcpu);
5294 if (kvm_task_switch(vcpu, tss_selector,
5295 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5296 has_error_code, error_code) == EMULATE_FAIL) {
5297 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5298 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5299 vcpu->run->internal.ndata = 0;
5303 /* clear all local breakpoint enable flags */
5304 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5307 * TODO: What about debug traps on tss switch?
5308 * Are we supposed to inject them and update dr6?
5314 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5316 unsigned long exit_qualification;
5321 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5323 gla_validity = (exit_qualification >> 7) & 0x3;
5324 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5325 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5326 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5327 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5328 vmcs_readl(GUEST_LINEAR_ADDRESS));
5329 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5330 (long unsigned int)exit_qualification);
5331 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5332 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5336 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5337 trace_kvm_page_fault(gpa, exit_qualification);
5339 /* It is a write fault? */
5340 error_code = exit_qualification & (1U << 1);
5341 /* It is a fetch fault? */
5342 error_code |= (exit_qualification & (1U << 2)) << 2;
5343 /* ept page table is present? */
5344 error_code |= (exit_qualification >> 3) & 0x1;
5346 vcpu->arch.exit_qualification = exit_qualification;
5348 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5351 static u64 ept_rsvd_mask(u64 spte, int level)
5356 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5357 mask |= (1ULL << i);
5360 /* bits 7:3 reserved */
5362 else if (level == 2) {
5363 if (spte & (1ULL << 7))
5364 /* 2MB ref, bits 20:12 reserved */
5367 /* bits 6:3 reserved */
5374 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5377 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5379 /* 010b (write-only) */
5380 WARN_ON((spte & 0x7) == 0x2);
5382 /* 110b (write/execute) */
5383 WARN_ON((spte & 0x7) == 0x6);
5385 /* 100b (execute-only) and value not supported by logical processor */
5386 if (!cpu_has_vmx_ept_execute_only())
5387 WARN_ON((spte & 0x7) == 0x4);
5391 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5393 if (rsvd_bits != 0) {
5394 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5395 __func__, rsvd_bits);
5399 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5400 u64 ept_mem_type = (spte & 0x38) >> 3;
5402 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5403 ept_mem_type == 7) {
5404 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5405 __func__, ept_mem_type);
5412 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5415 int nr_sptes, i, ret;
5418 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5420 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5421 if (likely(ret == RET_MMIO_PF_EMULATE))
5422 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5425 if (unlikely(ret == RET_MMIO_PF_INVALID))
5426 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5428 if (unlikely(ret == RET_MMIO_PF_RETRY))
5431 /* It is the real ept misconfig */
5432 printk(KERN_ERR "EPT: Misconfiguration.\n");
5433 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5435 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5437 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5438 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5440 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5441 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5446 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5448 u32 cpu_based_vm_exec_control;
5450 /* clear pending NMI */
5451 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5452 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5453 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5454 ++vcpu->stat.nmi_window_exits;
5455 kvm_make_request(KVM_REQ_EVENT, vcpu);
5460 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5462 struct vcpu_vmx *vmx = to_vmx(vcpu);
5463 enum emulation_result err = EMULATE_DONE;
5466 bool intr_window_requested;
5467 unsigned count = 130;
5469 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5470 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5472 while (!guest_state_valid(vcpu) && count-- != 0) {
5473 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5474 return handle_interrupt_window(&vmx->vcpu);
5476 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5479 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5481 if (err == EMULATE_USER_EXIT) {
5486 if (err != EMULATE_DONE) {
5487 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5488 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5489 vcpu->run->internal.ndata = 0;
5493 if (vcpu->arch.halt_request) {
5494 vcpu->arch.halt_request = 0;
5495 ret = kvm_emulate_halt(vcpu);
5499 if (signal_pending(current))
5505 vmx->emulation_required = emulation_required(vcpu);
5511 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5512 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5514 static int handle_pause(struct kvm_vcpu *vcpu)
5516 skip_emulated_instruction(vcpu);
5517 kvm_vcpu_on_spin(vcpu);
5522 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5524 kvm_queue_exception(vcpu, UD_VECTOR);
5529 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5530 * We could reuse a single VMCS for all the L2 guests, but we also want the
5531 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5532 * allows keeping them loaded on the processor, and in the future will allow
5533 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5534 * every entry if they never change.
5535 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5536 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5538 * The following functions allocate and free a vmcs02 in this pool.
5541 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5542 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5544 struct vmcs02_list *item;
5545 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5546 if (item->vmptr == vmx->nested.current_vmptr) {
5547 list_move(&item->list, &vmx->nested.vmcs02_pool);
5548 return &item->vmcs02;
5551 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5552 /* Recycle the least recently used VMCS. */
5553 item = list_entry(vmx->nested.vmcs02_pool.prev,
5554 struct vmcs02_list, list);
5555 item->vmptr = vmx->nested.current_vmptr;
5556 list_move(&item->list, &vmx->nested.vmcs02_pool);
5557 return &item->vmcs02;
5560 /* Create a new VMCS */
5561 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5564 item->vmcs02.vmcs = alloc_vmcs();
5565 if (!item->vmcs02.vmcs) {
5569 loaded_vmcs_init(&item->vmcs02);
5570 item->vmptr = vmx->nested.current_vmptr;
5571 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5572 vmx->nested.vmcs02_num++;
5573 return &item->vmcs02;
5576 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5577 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5579 struct vmcs02_list *item;
5580 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5581 if (item->vmptr == vmptr) {
5582 free_loaded_vmcs(&item->vmcs02);
5583 list_del(&item->list);
5585 vmx->nested.vmcs02_num--;
5591 * Free all VMCSs saved for this vcpu, except the one pointed by
5592 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5593 * currently used, if running L2), and vmcs01 when running L2.
5595 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5597 struct vmcs02_list *item, *n;
5598 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5599 if (vmx->loaded_vmcs != &item->vmcs02)
5600 free_loaded_vmcs(&item->vmcs02);
5601 list_del(&item->list);
5604 vmx->nested.vmcs02_num = 0;
5606 if (vmx->loaded_vmcs != &vmx->vmcs01)
5607 free_loaded_vmcs(&vmx->vmcs01);
5611 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5612 * set the success or error code of an emulated VMX instruction, as specified
5613 * by Vol 2B, VMX Instruction Reference, "Conventions".
5615 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5617 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5618 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5619 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5622 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5624 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5625 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5626 X86_EFLAGS_SF | X86_EFLAGS_OF))
5630 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5631 u32 vm_instruction_error)
5633 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5635 * failValid writes the error number to the current VMCS, which
5636 * can't be done there isn't a current VMCS.
5638 nested_vmx_failInvalid(vcpu);
5641 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5642 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5643 X86_EFLAGS_SF | X86_EFLAGS_OF))
5645 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5647 * We don't need to force a shadow sync because
5648 * VM_INSTRUCTION_ERROR is not shadowed
5653 * Emulate the VMXON instruction.
5654 * Currently, we just remember that VMX is active, and do not save or even
5655 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5656 * do not currently need to store anything in that guest-allocated memory
5657 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5658 * argument is different from the VMXON pointer (which the spec says they do).
5660 static int handle_vmon(struct kvm_vcpu *vcpu)
5662 struct kvm_segment cs;
5663 struct vcpu_vmx *vmx = to_vmx(vcpu);
5664 struct vmcs *shadow_vmcs;
5665 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5666 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5668 /* The Intel VMX Instruction Reference lists a bunch of bits that
5669 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5670 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5671 * Otherwise, we should fail with #UD. We test these now:
5673 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5674 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5675 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5676 kvm_queue_exception(vcpu, UD_VECTOR);
5680 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5681 if (is_long_mode(vcpu) && !cs.l) {
5682 kvm_queue_exception(vcpu, UD_VECTOR);
5686 if (vmx_get_cpl(vcpu)) {
5687 kvm_inject_gp(vcpu, 0);
5690 if (vmx->nested.vmxon) {
5691 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5692 skip_emulated_instruction(vcpu);
5696 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5697 != VMXON_NEEDED_FEATURES) {
5698 kvm_inject_gp(vcpu, 0);
5702 if (enable_shadow_vmcs) {
5703 shadow_vmcs = alloc_vmcs();
5706 /* mark vmcs as shadow */
5707 shadow_vmcs->revision_id |= (1u << 31);
5708 /* init shadow vmcs */
5709 vmcs_clear(shadow_vmcs);
5710 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5713 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5714 vmx->nested.vmcs02_num = 0;
5716 vmx->nested.vmxon = true;
5718 skip_emulated_instruction(vcpu);
5719 nested_vmx_succeed(vcpu);
5724 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5725 * for running VMX instructions (except VMXON, whose prerequisites are
5726 * slightly different). It also specifies what exception to inject otherwise.
5728 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5730 struct kvm_segment cs;
5731 struct vcpu_vmx *vmx = to_vmx(vcpu);
5733 if (!vmx->nested.vmxon) {
5734 kvm_queue_exception(vcpu, UD_VECTOR);
5738 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5739 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5740 (is_long_mode(vcpu) && !cs.l)) {
5741 kvm_queue_exception(vcpu, UD_VECTOR);
5745 if (vmx_get_cpl(vcpu)) {
5746 kvm_inject_gp(vcpu, 0);
5753 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5756 if (enable_shadow_vmcs) {
5757 if (vmx->nested.current_vmcs12 != NULL) {
5758 /* copy to memory all shadowed fields in case
5759 they were modified */
5760 copy_shadow_to_vmcs12(vmx);
5761 vmx->nested.sync_shadow_vmcs = false;
5762 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5763 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5764 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5765 vmcs_write64(VMCS_LINK_POINTER, -1ull);
5768 kunmap(vmx->nested.current_vmcs12_page);
5769 nested_release_page(vmx->nested.current_vmcs12_page);
5773 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5774 * just stops using VMX.
5776 static void free_nested(struct vcpu_vmx *vmx)
5778 if (!vmx->nested.vmxon)
5780 vmx->nested.vmxon = false;
5781 if (vmx->nested.current_vmptr != -1ull) {
5782 nested_release_vmcs12(vmx);
5783 vmx->nested.current_vmptr = -1ull;
5784 vmx->nested.current_vmcs12 = NULL;
5786 if (enable_shadow_vmcs)
5787 free_vmcs(vmx->nested.current_shadow_vmcs);
5788 /* Unpin physical memory we referred to in current vmcs02 */
5789 if (vmx->nested.apic_access_page) {
5790 nested_release_page(vmx->nested.apic_access_page);
5791 vmx->nested.apic_access_page = 0;
5794 nested_free_all_saved_vmcss(vmx);
5797 /* Emulate the VMXOFF instruction */
5798 static int handle_vmoff(struct kvm_vcpu *vcpu)
5800 if (!nested_vmx_check_permission(vcpu))
5802 free_nested(to_vmx(vcpu));
5803 skip_emulated_instruction(vcpu);
5804 nested_vmx_succeed(vcpu);
5809 * Decode the memory-address operand of a vmx instruction, as recorded on an
5810 * exit caused by such an instruction (run by a guest hypervisor).
5811 * On success, returns 0. When the operand is invalid, returns 1 and throws
5814 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5815 unsigned long exit_qualification,
5816 u32 vmx_instruction_info, gva_t *ret)
5819 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5820 * Execution", on an exit, vmx_instruction_info holds most of the
5821 * addressing components of the operand. Only the displacement part
5822 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5823 * For how an actual address is calculated from all these components,
5824 * refer to Vol. 1, "Operand Addressing".
5826 int scaling = vmx_instruction_info & 3;
5827 int addr_size = (vmx_instruction_info >> 7) & 7;
5828 bool is_reg = vmx_instruction_info & (1u << 10);
5829 int seg_reg = (vmx_instruction_info >> 15) & 7;
5830 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5831 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5832 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5833 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5836 kvm_queue_exception(vcpu, UD_VECTOR);
5840 /* Addr = segment_base + offset */
5841 /* offset = base + [index * scale] + displacement */
5842 *ret = vmx_get_segment_base(vcpu, seg_reg);
5844 *ret += kvm_register_read(vcpu, base_reg);
5846 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5847 *ret += exit_qualification; /* holds the displacement */
5849 if (addr_size == 1) /* 32 bit */
5853 * TODO: throw #GP (and return 1) in various cases that the VM*
5854 * instructions require it - e.g., offset beyond segment limit,
5855 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5856 * address, and so on. Currently these are not checked.
5861 /* Emulate the VMCLEAR instruction */
5862 static int handle_vmclear(struct kvm_vcpu *vcpu)
5864 struct vcpu_vmx *vmx = to_vmx(vcpu);
5867 struct vmcs12 *vmcs12;
5869 struct x86_exception e;
5871 if (!nested_vmx_check_permission(vcpu))
5874 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5875 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5878 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5879 sizeof(vmptr), &e)) {
5880 kvm_inject_page_fault(vcpu, &e);
5884 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5885 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5886 skip_emulated_instruction(vcpu);
5890 if (vmptr == vmx->nested.current_vmptr) {
5891 nested_release_vmcs12(vmx);
5892 vmx->nested.current_vmptr = -1ull;
5893 vmx->nested.current_vmcs12 = NULL;
5896 page = nested_get_page(vcpu, vmptr);
5899 * For accurate processor emulation, VMCLEAR beyond available
5900 * physical memory should do nothing at all. However, it is
5901 * possible that a nested vmx bug, not a guest hypervisor bug,
5902 * resulted in this case, so let's shut down before doing any
5905 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5908 vmcs12 = kmap(page);
5909 vmcs12->launch_state = 0;
5911 nested_release_page(page);
5913 nested_free_vmcs02(vmx, vmptr);
5915 skip_emulated_instruction(vcpu);
5916 nested_vmx_succeed(vcpu);
5920 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5922 /* Emulate the VMLAUNCH instruction */
5923 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5925 return nested_vmx_run(vcpu, true);
5928 /* Emulate the VMRESUME instruction */
5929 static int handle_vmresume(struct kvm_vcpu *vcpu)
5932 return nested_vmx_run(vcpu, false);
5935 enum vmcs_field_type {
5936 VMCS_FIELD_TYPE_U16 = 0,
5937 VMCS_FIELD_TYPE_U64 = 1,
5938 VMCS_FIELD_TYPE_U32 = 2,
5939 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5942 static inline int vmcs_field_type(unsigned long field)
5944 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5945 return VMCS_FIELD_TYPE_U32;
5946 return (field >> 13) & 0x3 ;
5949 static inline int vmcs_field_readonly(unsigned long field)
5951 return (((field >> 10) & 0x3) == 1);
5955 * Read a vmcs12 field. Since these can have varying lengths and we return
5956 * one type, we chose the biggest type (u64) and zero-extend the return value
5957 * to that size. Note that the caller, handle_vmread, might need to use only
5958 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5959 * 64-bit fields are to be returned).
5961 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5962 unsigned long field, u64 *ret)
5964 short offset = vmcs_field_to_offset(field);
5970 p = ((char *)(get_vmcs12(vcpu))) + offset;
5972 switch (vmcs_field_type(field)) {
5973 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5974 *ret = *((natural_width *)p);
5976 case VMCS_FIELD_TYPE_U16:
5979 case VMCS_FIELD_TYPE_U32:
5982 case VMCS_FIELD_TYPE_U64:
5986 return 0; /* can never happen. */
5991 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5992 unsigned long field, u64 field_value){
5993 short offset = vmcs_field_to_offset(field);
5994 char *p = ((char *) get_vmcs12(vcpu)) + offset;
5998 switch (vmcs_field_type(field)) {
5999 case VMCS_FIELD_TYPE_U16:
6000 *(u16 *)p = field_value;
6002 case VMCS_FIELD_TYPE_U32:
6003 *(u32 *)p = field_value;
6005 case VMCS_FIELD_TYPE_U64:
6006 *(u64 *)p = field_value;
6008 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6009 *(natural_width *)p = field_value;
6012 return false; /* can never happen. */
6017 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6020 unsigned long field;
6022 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6023 const unsigned long *fields = shadow_read_write_fields;
6024 const int num_fields = max_shadow_read_write_fields;
6026 vmcs_load(shadow_vmcs);
6028 for (i = 0; i < num_fields; i++) {
6030 switch (vmcs_field_type(field)) {
6031 case VMCS_FIELD_TYPE_U16:
6032 field_value = vmcs_read16(field);
6034 case VMCS_FIELD_TYPE_U32:
6035 field_value = vmcs_read32(field);
6037 case VMCS_FIELD_TYPE_U64:
6038 field_value = vmcs_read64(field);
6040 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6041 field_value = vmcs_readl(field);
6044 vmcs12_write_any(&vmx->vcpu, field, field_value);
6047 vmcs_clear(shadow_vmcs);
6048 vmcs_load(vmx->loaded_vmcs->vmcs);
6051 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6053 const unsigned long *fields[] = {
6054 shadow_read_write_fields,
6055 shadow_read_only_fields
6057 const int max_fields[] = {
6058 max_shadow_read_write_fields,
6059 max_shadow_read_only_fields
6062 unsigned long field;
6063 u64 field_value = 0;
6064 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6066 vmcs_load(shadow_vmcs);
6068 for (q = 0; q < ARRAY_SIZE(fields); q++) {
6069 for (i = 0; i < max_fields[q]; i++) {
6070 field = fields[q][i];
6071 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6073 switch (vmcs_field_type(field)) {
6074 case VMCS_FIELD_TYPE_U16:
6075 vmcs_write16(field, (u16)field_value);
6077 case VMCS_FIELD_TYPE_U32:
6078 vmcs_write32(field, (u32)field_value);
6080 case VMCS_FIELD_TYPE_U64:
6081 vmcs_write64(field, (u64)field_value);
6083 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6084 vmcs_writel(field, (long)field_value);
6090 vmcs_clear(shadow_vmcs);
6091 vmcs_load(vmx->loaded_vmcs->vmcs);
6095 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6096 * used before) all generate the same failure when it is missing.
6098 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6100 struct vcpu_vmx *vmx = to_vmx(vcpu);
6101 if (vmx->nested.current_vmptr == -1ull) {
6102 nested_vmx_failInvalid(vcpu);
6103 skip_emulated_instruction(vcpu);
6109 static int handle_vmread(struct kvm_vcpu *vcpu)
6111 unsigned long field;
6113 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6114 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6117 if (!nested_vmx_check_permission(vcpu) ||
6118 !nested_vmx_check_vmcs12(vcpu))
6121 /* Decode instruction info and find the field to read */
6122 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6123 /* Read the field, zero-extended to a u64 field_value */
6124 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6125 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6126 skip_emulated_instruction(vcpu);
6130 * Now copy part of this value to register or memory, as requested.
6131 * Note that the number of bits actually copied is 32 or 64 depending
6132 * on the guest's mode (32 or 64 bit), not on the given field's length.
6134 if (vmx_instruction_info & (1u << 10)) {
6135 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6138 if (get_vmx_mem_address(vcpu, exit_qualification,
6139 vmx_instruction_info, &gva))
6141 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6142 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6143 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6146 nested_vmx_succeed(vcpu);
6147 skip_emulated_instruction(vcpu);
6152 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6154 unsigned long field;
6156 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6157 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6158 /* The value to write might be 32 or 64 bits, depending on L1's long
6159 * mode, and eventually we need to write that into a field of several
6160 * possible lengths. The code below first zero-extends the value to 64
6161 * bit (field_value), and then copies only the approriate number of
6162 * bits into the vmcs12 field.
6164 u64 field_value = 0;
6165 struct x86_exception e;
6167 if (!nested_vmx_check_permission(vcpu) ||
6168 !nested_vmx_check_vmcs12(vcpu))
6171 if (vmx_instruction_info & (1u << 10))
6172 field_value = kvm_register_read(vcpu,
6173 (((vmx_instruction_info) >> 3) & 0xf));
6175 if (get_vmx_mem_address(vcpu, exit_qualification,
6176 vmx_instruction_info, &gva))
6178 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6179 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6180 kvm_inject_page_fault(vcpu, &e);
6186 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6187 if (vmcs_field_readonly(field)) {
6188 nested_vmx_failValid(vcpu,
6189 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6190 skip_emulated_instruction(vcpu);
6194 if (!vmcs12_write_any(vcpu, field, field_value)) {
6195 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6196 skip_emulated_instruction(vcpu);
6200 nested_vmx_succeed(vcpu);
6201 skip_emulated_instruction(vcpu);
6205 /* Emulate the VMPTRLD instruction */
6206 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6208 struct vcpu_vmx *vmx = to_vmx(vcpu);
6211 struct x86_exception e;
6214 if (!nested_vmx_check_permission(vcpu))
6217 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6218 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6221 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6222 sizeof(vmptr), &e)) {
6223 kvm_inject_page_fault(vcpu, &e);
6227 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6228 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6229 skip_emulated_instruction(vcpu);
6233 if (vmx->nested.current_vmptr != vmptr) {
6234 struct vmcs12 *new_vmcs12;
6236 page = nested_get_page(vcpu, vmptr);
6238 nested_vmx_failInvalid(vcpu);
6239 skip_emulated_instruction(vcpu);
6242 new_vmcs12 = kmap(page);
6243 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6245 nested_release_page_clean(page);
6246 nested_vmx_failValid(vcpu,
6247 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6248 skip_emulated_instruction(vcpu);
6251 if (vmx->nested.current_vmptr != -1ull)
6252 nested_release_vmcs12(vmx);
6254 vmx->nested.current_vmptr = vmptr;
6255 vmx->nested.current_vmcs12 = new_vmcs12;
6256 vmx->nested.current_vmcs12_page = page;
6257 if (enable_shadow_vmcs) {
6258 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6259 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6260 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6261 vmcs_write64(VMCS_LINK_POINTER,
6262 __pa(vmx->nested.current_shadow_vmcs));
6263 vmx->nested.sync_shadow_vmcs = true;
6267 nested_vmx_succeed(vcpu);
6268 skip_emulated_instruction(vcpu);
6272 /* Emulate the VMPTRST instruction */
6273 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6275 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6276 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6278 struct x86_exception e;
6280 if (!nested_vmx_check_permission(vcpu))
6283 if (get_vmx_mem_address(vcpu, exit_qualification,
6284 vmx_instruction_info, &vmcs_gva))
6286 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6287 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6288 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6290 kvm_inject_page_fault(vcpu, &e);
6293 nested_vmx_succeed(vcpu);
6294 skip_emulated_instruction(vcpu);
6298 /* Emulate the INVEPT instruction */
6299 static int handle_invept(struct kvm_vcpu *vcpu)
6301 u32 vmx_instruction_info, types;
6304 struct x86_exception e;
6308 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6310 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6311 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6312 kvm_queue_exception(vcpu, UD_VECTOR);
6316 if (!nested_vmx_check_permission(vcpu))
6319 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6320 kvm_queue_exception(vcpu, UD_VECTOR);
6324 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6325 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6327 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6329 if (!(types & (1UL << type))) {
6330 nested_vmx_failValid(vcpu,
6331 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6335 /* According to the Intel VMX instruction reference, the memory
6336 * operand is read even if it isn't needed (e.g., for type==global)
6338 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6339 vmx_instruction_info, &gva))
6341 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6342 sizeof(operand), &e)) {
6343 kvm_inject_page_fault(vcpu, &e);
6348 case VMX_EPT_EXTENT_CONTEXT:
6349 if ((operand.eptp & eptp_mask) !=
6350 (nested_ept_get_cr3(vcpu) & eptp_mask))
6352 case VMX_EPT_EXTENT_GLOBAL:
6353 kvm_mmu_sync_roots(vcpu);
6354 kvm_mmu_flush_tlb(vcpu);
6355 nested_vmx_succeed(vcpu);
6362 skip_emulated_instruction(vcpu);
6367 * The exit handlers return 1 if the exit was handled fully and guest execution
6368 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6369 * to be done to userspace and return 0.
6371 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6372 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6373 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
6374 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6375 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6376 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6377 [EXIT_REASON_CR_ACCESS] = handle_cr,
6378 [EXIT_REASON_DR_ACCESS] = handle_dr,
6379 [EXIT_REASON_CPUID] = handle_cpuid,
6380 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6381 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6382 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6383 [EXIT_REASON_HLT] = handle_halt,
6384 [EXIT_REASON_INVD] = handle_invd,
6385 [EXIT_REASON_INVLPG] = handle_invlpg,
6386 [EXIT_REASON_RDPMC] = handle_rdpmc,
6387 [EXIT_REASON_VMCALL] = handle_vmcall,
6388 [EXIT_REASON_VMCLEAR] = handle_vmclear,
6389 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
6390 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6391 [EXIT_REASON_VMPTRST] = handle_vmptrst,
6392 [EXIT_REASON_VMREAD] = handle_vmread,
6393 [EXIT_REASON_VMRESUME] = handle_vmresume,
6394 [EXIT_REASON_VMWRITE] = handle_vmwrite,
6395 [EXIT_REASON_VMOFF] = handle_vmoff,
6396 [EXIT_REASON_VMON] = handle_vmon,
6397 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6398 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
6399 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
6400 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
6401 [EXIT_REASON_WBINVD] = handle_wbinvd,
6402 [EXIT_REASON_XSETBV] = handle_xsetbv,
6403 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
6404 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
6405 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6406 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
6407 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
6408 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6409 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6410 [EXIT_REASON_INVEPT] = handle_invept,
6413 static const int kvm_vmx_max_exit_handlers =
6414 ARRAY_SIZE(kvm_vmx_exit_handlers);
6416 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6417 struct vmcs12 *vmcs12)
6419 unsigned long exit_qualification;
6420 gpa_t bitmap, last_bitmap;
6425 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6428 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6431 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6433 port = exit_qualification >> 16;
6434 size = (exit_qualification & 7) + 1;
6436 last_bitmap = (gpa_t)-1;
6441 bitmap = vmcs12->io_bitmap_a;
6442 else if (port < 0x10000)
6443 bitmap = vmcs12->io_bitmap_b;
6446 bitmap += (port & 0x7fff) / 8;
6448 if (last_bitmap != bitmap)
6449 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6451 if (b & (1 << (port & 7)))
6456 last_bitmap = bitmap;
6463 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6464 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6465 * disinterest in the current event (read or write a specific MSR) by using an
6466 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6468 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6469 struct vmcs12 *vmcs12, u32 exit_reason)
6471 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6474 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6478 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6479 * for the four combinations of read/write and low/high MSR numbers.
6480 * First we need to figure out which of the four to use:
6482 bitmap = vmcs12->msr_bitmap;
6483 if (exit_reason == EXIT_REASON_MSR_WRITE)
6485 if (msr_index >= 0xc0000000) {
6486 msr_index -= 0xc0000000;
6490 /* Then read the msr_index'th bit from this bitmap: */
6491 if (msr_index < 1024*8) {
6493 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6495 return 1 & (b >> (msr_index & 7));
6497 return 1; /* let L1 handle the wrong parameter */
6501 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6502 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6503 * intercept (via guest_host_mask etc.) the current event.
6505 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6506 struct vmcs12 *vmcs12)
6508 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6509 int cr = exit_qualification & 15;
6510 int reg = (exit_qualification >> 8) & 15;
6511 unsigned long val = kvm_register_read(vcpu, reg);
6513 switch ((exit_qualification >> 4) & 3) {
6514 case 0: /* mov to cr */
6517 if (vmcs12->cr0_guest_host_mask &
6518 (val ^ vmcs12->cr0_read_shadow))
6522 if ((vmcs12->cr3_target_count >= 1 &&
6523 vmcs12->cr3_target_value0 == val) ||
6524 (vmcs12->cr3_target_count >= 2 &&
6525 vmcs12->cr3_target_value1 == val) ||
6526 (vmcs12->cr3_target_count >= 3 &&
6527 vmcs12->cr3_target_value2 == val) ||
6528 (vmcs12->cr3_target_count >= 4 &&
6529 vmcs12->cr3_target_value3 == val))
6531 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6535 if (vmcs12->cr4_guest_host_mask &
6536 (vmcs12->cr4_read_shadow ^ val))
6540 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6546 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6547 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6550 case 1: /* mov from cr */
6553 if (vmcs12->cpu_based_vm_exec_control &
6554 CPU_BASED_CR3_STORE_EXITING)
6558 if (vmcs12->cpu_based_vm_exec_control &
6559 CPU_BASED_CR8_STORE_EXITING)
6566 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6567 * cr0. Other attempted changes are ignored, with no exit.
6569 if (vmcs12->cr0_guest_host_mask & 0xe &
6570 (val ^ vmcs12->cr0_read_shadow))
6572 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6573 !(vmcs12->cr0_read_shadow & 0x1) &&
6582 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6583 * should handle it ourselves in L0 (and then continue L2). Only call this
6584 * when in is_guest_mode (L2).
6586 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6588 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6589 struct vcpu_vmx *vmx = to_vmx(vcpu);
6590 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6591 u32 exit_reason = vmx->exit_reason;
6593 if (vmx->nested.nested_run_pending)
6596 if (unlikely(vmx->fail)) {
6597 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6598 vmcs_read32(VM_INSTRUCTION_ERROR));
6602 switch (exit_reason) {
6603 case EXIT_REASON_EXCEPTION_NMI:
6604 if (!is_exception(intr_info))
6606 else if (is_page_fault(intr_info))
6608 return vmcs12->exception_bitmap &
6609 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6610 case EXIT_REASON_EXTERNAL_INTERRUPT:
6612 case EXIT_REASON_TRIPLE_FAULT:
6614 case EXIT_REASON_PENDING_INTERRUPT:
6615 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6616 case EXIT_REASON_NMI_WINDOW:
6617 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6618 case EXIT_REASON_TASK_SWITCH:
6620 case EXIT_REASON_CPUID:
6622 case EXIT_REASON_HLT:
6623 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6624 case EXIT_REASON_INVD:
6626 case EXIT_REASON_INVLPG:
6627 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6628 case EXIT_REASON_RDPMC:
6629 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6630 case EXIT_REASON_RDTSC:
6631 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6632 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6633 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6634 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6635 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6636 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6637 case EXIT_REASON_INVEPT:
6639 * VMX instructions trap unconditionally. This allows L1 to
6640 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6643 case EXIT_REASON_CR_ACCESS:
6644 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6645 case EXIT_REASON_DR_ACCESS:
6646 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6647 case EXIT_REASON_IO_INSTRUCTION:
6648 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6649 case EXIT_REASON_MSR_READ:
6650 case EXIT_REASON_MSR_WRITE:
6651 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6652 case EXIT_REASON_INVALID_STATE:
6654 case EXIT_REASON_MWAIT_INSTRUCTION:
6655 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6656 case EXIT_REASON_MONITOR_INSTRUCTION:
6657 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6658 case EXIT_REASON_PAUSE_INSTRUCTION:
6659 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6660 nested_cpu_has2(vmcs12,
6661 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6662 case EXIT_REASON_MCE_DURING_VMENTRY:
6664 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6666 case EXIT_REASON_APIC_ACCESS:
6667 return nested_cpu_has2(vmcs12,
6668 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6669 case EXIT_REASON_EPT_VIOLATION:
6671 * L0 always deals with the EPT violation. If nested EPT is
6672 * used, and the nested mmu code discovers that the address is
6673 * missing in the guest EPT table (EPT12), the EPT violation
6674 * will be injected with nested_ept_inject_page_fault()
6677 case EXIT_REASON_EPT_MISCONFIG:
6679 * L2 never uses directly L1's EPT, but rather L0's own EPT
6680 * table (shadow on EPT) or a merged EPT table that L0 built
6681 * (EPT on EPT). So any problems with the structure of the
6682 * table is L0's fault.
6685 case EXIT_REASON_PREEMPTION_TIMER:
6686 return vmcs12->pin_based_vm_exec_control &
6687 PIN_BASED_VMX_PREEMPTION_TIMER;
6688 case EXIT_REASON_WBINVD:
6689 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6690 case EXIT_REASON_XSETBV:
6697 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6699 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6700 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6704 * The guest has exited. See if we can fix it or if we need userspace
6707 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6709 struct vcpu_vmx *vmx = to_vmx(vcpu);
6710 u32 exit_reason = vmx->exit_reason;
6711 u32 vectoring_info = vmx->idt_vectoring_info;
6713 /* If guest state is invalid, start emulating */
6714 if (vmx->emulation_required)
6715 return handle_invalid_guest_state(vcpu);
6718 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6719 * we did not inject a still-pending event to L1 now because of
6720 * nested_run_pending, we need to re-enable this bit.
6722 if (vmx->nested.nested_run_pending)
6723 kvm_make_request(KVM_REQ_EVENT, vcpu);
6725 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6726 exit_reason == EXIT_REASON_VMRESUME))
6727 vmx->nested.nested_run_pending = 1;
6729 vmx->nested.nested_run_pending = 0;
6731 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6732 nested_vmx_vmexit(vcpu);
6736 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6737 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6738 vcpu->run->fail_entry.hardware_entry_failure_reason
6743 if (unlikely(vmx->fail)) {
6744 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6745 vcpu->run->fail_entry.hardware_entry_failure_reason
6746 = vmcs_read32(VM_INSTRUCTION_ERROR);
6752 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6753 * delivery event since it indicates guest is accessing MMIO.
6754 * The vm-exit can be triggered again after return to guest that
6755 * will cause infinite loop.
6757 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6758 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6759 exit_reason != EXIT_REASON_EPT_VIOLATION &&
6760 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6761 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6762 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6763 vcpu->run->internal.ndata = 2;
6764 vcpu->run->internal.data[0] = vectoring_info;
6765 vcpu->run->internal.data[1] = exit_reason;
6769 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6770 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6771 get_vmcs12(vcpu))))) {
6772 if (vmx_interrupt_allowed(vcpu)) {
6773 vmx->soft_vnmi_blocked = 0;
6774 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6775 vcpu->arch.nmi_pending) {
6777 * This CPU don't support us in finding the end of an
6778 * NMI-blocked window if the guest runs with IRQs
6779 * disabled. So we pull the trigger after 1 s of
6780 * futile waiting, but inform the user about this.
6782 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6783 "state on VCPU %d after 1 s timeout\n",
6784 __func__, vcpu->vcpu_id);
6785 vmx->soft_vnmi_blocked = 0;
6789 if (exit_reason < kvm_vmx_max_exit_handlers
6790 && kvm_vmx_exit_handlers[exit_reason])
6791 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6793 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6794 vcpu->run->hw.hardware_exit_reason = exit_reason;
6799 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6801 if (irr == -1 || tpr < irr) {
6802 vmcs_write32(TPR_THRESHOLD, 0);
6806 vmcs_write32(TPR_THRESHOLD, irr);
6809 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6811 u32 sec_exec_control;
6814 * There is not point to enable virtualize x2apic without enable
6817 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6818 !vmx_vm_has_apicv(vcpu->kvm))
6821 if (!vm_need_tpr_shadow(vcpu->kvm))
6824 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6827 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6828 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6830 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6831 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6833 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6835 vmx_set_msr_bitmap(vcpu);
6838 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6843 if (!vmx_vm_has_apicv(kvm))
6849 status = vmcs_read16(GUEST_INTR_STATUS);
6854 vmcs_write16(GUEST_INTR_STATUS, status);
6858 static void vmx_set_rvi(int vector)
6863 status = vmcs_read16(GUEST_INTR_STATUS);
6864 old = (u8)status & 0xff;
6865 if ((u8)vector != old) {
6867 status |= (u8)vector;
6868 vmcs_write16(GUEST_INTR_STATUS, status);
6872 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6877 vmx_set_rvi(max_irr);
6880 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6882 if (!vmx_vm_has_apicv(vcpu->kvm))
6885 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6886 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6887 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6888 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6891 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6895 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6896 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6899 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6900 exit_intr_info = vmx->exit_intr_info;
6902 /* Handle machine checks before interrupts are enabled */
6903 if (is_machine_check(exit_intr_info))
6904 kvm_machine_check();
6906 /* We need to handle NMIs before interrupts are enabled */
6907 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6908 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6909 kvm_before_handle_nmi(&vmx->vcpu);
6911 kvm_after_handle_nmi(&vmx->vcpu);
6915 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6917 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6920 * If external interrupt exists, IF bit is set in rflags/eflags on the
6921 * interrupt stack frame, and interrupt will be enabled on a return
6922 * from interrupt handler.
6924 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6925 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6926 unsigned int vector;
6927 unsigned long entry;
6929 struct vcpu_vmx *vmx = to_vmx(vcpu);
6930 #ifdef CONFIG_X86_64
6934 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6935 desc = (gate_desc *)vmx->host_idt_base + vector;
6936 entry = gate_offset(*desc);
6938 #ifdef CONFIG_X86_64
6939 "mov %%" _ASM_SP ", %[sp]\n\t"
6940 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6945 "orl $0x200, (%%" _ASM_SP ")\n\t"
6946 __ASM_SIZE(push) " $%c[cs]\n\t"
6947 "call *%[entry]\n\t"
6949 #ifdef CONFIG_X86_64
6954 [ss]"i"(__KERNEL_DS),
6955 [cs]"i"(__KERNEL_CS)
6961 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6966 bool idtv_info_valid;
6968 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6970 if (cpu_has_virtual_nmis()) {
6971 if (vmx->nmi_known_unmasked)
6974 * Can't use vmx->exit_intr_info since we're not sure what
6975 * the exit reason is.
6977 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6978 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6979 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6981 * SDM 3: 27.7.1.2 (September 2008)
6982 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6983 * a guest IRET fault.
6984 * SDM 3: 23.2.2 (September 2008)
6985 * Bit 12 is undefined in any of the following cases:
6986 * If the VM exit sets the valid bit in the IDT-vectoring
6987 * information field.
6988 * If the VM exit is due to a double fault.
6990 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6991 vector != DF_VECTOR && !idtv_info_valid)
6992 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6993 GUEST_INTR_STATE_NMI);
6995 vmx->nmi_known_unmasked =
6996 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6997 & GUEST_INTR_STATE_NMI);
6998 } else if (unlikely(vmx->soft_vnmi_blocked))
6999 vmx->vnmi_blocked_time +=
7000 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7003 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7004 u32 idt_vectoring_info,
7005 int instr_len_field,
7006 int error_code_field)
7010 bool idtv_info_valid;
7012 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7014 vcpu->arch.nmi_injected = false;
7015 kvm_clear_exception_queue(vcpu);
7016 kvm_clear_interrupt_queue(vcpu);
7018 if (!idtv_info_valid)
7021 kvm_make_request(KVM_REQ_EVENT, vcpu);
7023 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7024 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7027 case INTR_TYPE_NMI_INTR:
7028 vcpu->arch.nmi_injected = true;
7030 * SDM 3: 27.7.1.2 (September 2008)
7031 * Clear bit "block by NMI" before VM entry if a NMI
7034 vmx_set_nmi_mask(vcpu, false);
7036 case INTR_TYPE_SOFT_EXCEPTION:
7037 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7039 case INTR_TYPE_HARD_EXCEPTION:
7040 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7041 u32 err = vmcs_read32(error_code_field);
7042 kvm_queue_exception_e(vcpu, vector, err);
7044 kvm_queue_exception(vcpu, vector);
7046 case INTR_TYPE_SOFT_INTR:
7047 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7049 case INTR_TYPE_EXT_INTR:
7050 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7057 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7059 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7060 VM_EXIT_INSTRUCTION_LEN,
7061 IDT_VECTORING_ERROR_CODE);
7064 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7066 __vmx_complete_interrupts(vcpu,
7067 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7068 VM_ENTRY_INSTRUCTION_LEN,
7069 VM_ENTRY_EXCEPTION_ERROR_CODE);
7071 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7074 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7077 struct perf_guest_switch_msr *msrs;
7079 msrs = perf_guest_get_msrs(&nr_msrs);
7084 for (i = 0; i < nr_msrs; i++)
7085 if (msrs[i].host == msrs[i].guest)
7086 clear_atomic_switch_msr(vmx, msrs[i].msr);
7088 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7092 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7094 struct vcpu_vmx *vmx = to_vmx(vcpu);
7095 unsigned long debugctlmsr;
7097 /* Record the guest's net vcpu time for enforced NMI injections. */
7098 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7099 vmx->entry_time = ktime_get();
7101 /* Don't enter VMX if guest state is invalid, let the exit handler
7102 start emulation until we arrive back to a valid state */
7103 if (vmx->emulation_required)
7106 if (vmx->nested.sync_shadow_vmcs) {
7107 copy_vmcs12_to_shadow(vmx);
7108 vmx->nested.sync_shadow_vmcs = false;
7111 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7112 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7113 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7114 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7116 /* When single-stepping over STI and MOV SS, we must clear the
7117 * corresponding interruptibility bits in the guest state. Otherwise
7118 * vmentry fails as it then expects bit 14 (BS) in pending debug
7119 * exceptions being set, but that's not correct for the guest debugging
7121 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7122 vmx_set_interrupt_shadow(vcpu, 0);
7124 atomic_switch_perf_msrs(vmx);
7125 debugctlmsr = get_debugctlmsr();
7127 vmx->__launched = vmx->loaded_vmcs->launched;
7129 /* Store host registers */
7130 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7131 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7132 "push %%" _ASM_CX " \n\t"
7133 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7135 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7136 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7138 /* Reload cr2 if changed */
7139 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7140 "mov %%cr2, %%" _ASM_DX " \n\t"
7141 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7143 "mov %%" _ASM_AX", %%cr2 \n\t"
7145 /* Check if vmlaunch of vmresume is needed */
7146 "cmpl $0, %c[launched](%0) \n\t"
7147 /* Load guest registers. Don't clobber flags. */
7148 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7149 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7150 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7151 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7152 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7153 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7154 #ifdef CONFIG_X86_64
7155 "mov %c[r8](%0), %%r8 \n\t"
7156 "mov %c[r9](%0), %%r9 \n\t"
7157 "mov %c[r10](%0), %%r10 \n\t"
7158 "mov %c[r11](%0), %%r11 \n\t"
7159 "mov %c[r12](%0), %%r12 \n\t"
7160 "mov %c[r13](%0), %%r13 \n\t"
7161 "mov %c[r14](%0), %%r14 \n\t"
7162 "mov %c[r15](%0), %%r15 \n\t"
7164 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7166 /* Enter guest mode */
7168 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7170 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7172 /* Save guest registers, load host registers, keep flags */
7173 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7175 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7176 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7177 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7178 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7179 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7180 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7181 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7182 #ifdef CONFIG_X86_64
7183 "mov %%r8, %c[r8](%0) \n\t"
7184 "mov %%r9, %c[r9](%0) \n\t"
7185 "mov %%r10, %c[r10](%0) \n\t"
7186 "mov %%r11, %c[r11](%0) \n\t"
7187 "mov %%r12, %c[r12](%0) \n\t"
7188 "mov %%r13, %c[r13](%0) \n\t"
7189 "mov %%r14, %c[r14](%0) \n\t"
7190 "mov %%r15, %c[r15](%0) \n\t"
7192 "mov %%cr2, %%" _ASM_AX " \n\t"
7193 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7195 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
7196 "setbe %c[fail](%0) \n\t"
7197 ".pushsection .rodata \n\t"
7198 ".global vmx_return \n\t"
7199 "vmx_return: " _ASM_PTR " 2b \n\t"
7201 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7202 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7203 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7204 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7205 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7206 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7207 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7208 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7209 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7210 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7211 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7212 #ifdef CONFIG_X86_64
7213 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7214 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7215 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7216 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7217 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7218 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7219 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7220 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7222 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7223 [wordsize]"i"(sizeof(ulong))
7225 #ifdef CONFIG_X86_64
7226 , "rax", "rbx", "rdi", "rsi"
7227 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7229 , "eax", "ebx", "edi", "esi"
7233 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7235 update_debugctlmsr(debugctlmsr);
7237 #ifndef CONFIG_X86_64
7239 * The sysexit path does not restore ds/es, so we must set them to
7240 * a reasonable value ourselves.
7242 * We can't defer this to vmx_load_host_state() since that function
7243 * may be executed in interrupt context, which saves and restore segments
7244 * around it, nullifying its effect.
7246 loadsegment(ds, __USER_DS);
7247 loadsegment(es, __USER_DS);
7250 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7251 | (1 << VCPU_EXREG_RFLAGS)
7252 | (1 << VCPU_EXREG_CPL)
7253 | (1 << VCPU_EXREG_PDPTR)
7254 | (1 << VCPU_EXREG_SEGMENTS)
7255 | (1 << VCPU_EXREG_CR3));
7256 vcpu->arch.regs_dirty = 0;
7258 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7260 vmx->loaded_vmcs->launched = 1;
7262 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7263 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7265 vmx_complete_atomic_exit(vmx);
7266 vmx_recover_nmi_blocking(vmx);
7267 vmx_complete_interrupts(vmx);
7270 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7272 struct vcpu_vmx *vmx = to_vmx(vcpu);
7276 free_loaded_vmcs(vmx->loaded_vmcs);
7277 kfree(vmx->guest_msrs);
7278 kvm_vcpu_uninit(vcpu);
7279 kmem_cache_free(kvm_vcpu_cache, vmx);
7282 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7285 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7289 return ERR_PTR(-ENOMEM);
7293 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7297 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7299 if (!vmx->guest_msrs) {
7303 vmx->loaded_vmcs = &vmx->vmcs01;
7304 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7305 if (!vmx->loaded_vmcs->vmcs)
7308 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7309 loaded_vmcs_init(vmx->loaded_vmcs);
7314 vmx_vcpu_load(&vmx->vcpu, cpu);
7315 vmx->vcpu.cpu = cpu;
7316 err = vmx_vcpu_setup(vmx);
7317 vmx_vcpu_put(&vmx->vcpu);
7321 if (vm_need_virtualize_apic_accesses(kvm)) {
7322 err = alloc_apic_access_page(kvm);
7328 if (!kvm->arch.ept_identity_map_addr)
7329 kvm->arch.ept_identity_map_addr =
7330 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7332 if (alloc_identity_pagetable(kvm) != 0)
7334 if (!init_rmode_identity_map(kvm))
7338 vmx->nested.current_vmptr = -1ull;
7339 vmx->nested.current_vmcs12 = NULL;
7344 free_loaded_vmcs(vmx->loaded_vmcs);
7346 kfree(vmx->guest_msrs);
7348 kvm_vcpu_uninit(&vmx->vcpu);
7351 kmem_cache_free(kvm_vcpu_cache, vmx);
7352 return ERR_PTR(err);
7355 static void __init vmx_check_processor_compat(void *rtn)
7357 struct vmcs_config vmcs_conf;
7360 if (setup_vmcs_config(&vmcs_conf) < 0)
7362 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7363 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7364 smp_processor_id());
7369 static int get_ept_level(void)
7371 return VMX_EPT_DEFAULT_GAW + 1;
7374 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7378 /* For VT-d and EPT combination
7379 * 1. MMIO: always map as UC
7381 * a. VT-d without snooping control feature: can't guarantee the
7382 * result, try to trust guest.
7383 * b. VT-d with snooping control feature: snooping control feature of
7384 * VT-d engine can guarantee the cache correctness. Just set it
7385 * to WB to keep consistent with host. So the same as item 3.
7386 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7387 * consistent with host MTRR
7390 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7391 else if (vcpu->kvm->arch.iommu_domain &&
7392 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7393 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7394 VMX_EPT_MT_EPTE_SHIFT;
7396 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7402 static int vmx_get_lpage_level(void)
7404 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7405 return PT_DIRECTORY_LEVEL;
7407 /* For shadow and EPT supported 1GB page */
7408 return PT_PDPE_LEVEL;
7411 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7413 struct kvm_cpuid_entry2 *best;
7414 struct vcpu_vmx *vmx = to_vmx(vcpu);
7417 vmx->rdtscp_enabled = false;
7418 if (vmx_rdtscp_supported()) {
7419 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7420 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7421 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7422 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7423 vmx->rdtscp_enabled = true;
7425 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7426 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7432 /* Exposing INVPCID only when PCID is exposed */
7433 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7434 if (vmx_invpcid_supported() &&
7435 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7436 guest_cpuid_has_pcid(vcpu)) {
7437 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7438 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7439 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7442 if (cpu_has_secondary_exec_ctrls()) {
7443 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7444 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7445 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7449 best->ebx &= ~bit(X86_FEATURE_INVPCID);
7453 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7455 if (func == 1 && nested)
7456 entry->ecx |= bit(X86_FEATURE_VMX);
7459 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7460 struct x86_exception *fault)
7462 struct vmcs12 *vmcs12;
7463 nested_vmx_vmexit(vcpu);
7464 vmcs12 = get_vmcs12(vcpu);
7466 if (fault->error_code & PFERR_RSVD_MASK)
7467 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7469 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7470 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7471 vmcs12->guest_physical_address = fault->address;
7474 /* Callbacks for nested_ept_init_mmu_context: */
7476 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7478 /* return the page table to be shadowed - in our case, EPT12 */
7479 return get_vmcs12(vcpu)->ept_pointer;
7482 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7484 int r = kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7485 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7487 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7488 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7489 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7491 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
7496 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7498 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7502 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7503 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7504 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7505 * guest in a way that will both be appropriate to L1's requests, and our
7506 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7507 * function also has additional necessary side-effects, like setting various
7508 * vcpu->arch fields.
7510 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7512 struct vcpu_vmx *vmx = to_vmx(vcpu);
7515 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7516 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7517 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7518 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7519 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7520 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7521 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7522 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7523 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7524 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7525 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7526 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7527 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7528 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7529 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7530 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7531 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7532 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7533 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7534 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7535 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7536 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7537 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7538 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7539 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7540 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7541 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7542 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7543 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7544 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7545 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7546 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7547 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7548 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7549 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7550 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7552 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7553 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7554 vmcs12->vm_entry_intr_info_field);
7555 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7556 vmcs12->vm_entry_exception_error_code);
7557 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7558 vmcs12->vm_entry_instruction_len);
7559 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7560 vmcs12->guest_interruptibility_info);
7561 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7562 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7563 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7564 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7565 vmcs12->guest_pending_dbg_exceptions);
7566 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7567 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7569 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7571 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7572 (vmcs_config.pin_based_exec_ctrl |
7573 vmcs12->pin_based_vm_exec_control));
7575 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7576 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7577 vmcs12->vmx_preemption_timer_value);
7580 * Whether page-faults are trapped is determined by a combination of
7581 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7582 * If enable_ept, L0 doesn't care about page faults and we should
7583 * set all of these to L1's desires. However, if !enable_ept, L0 does
7584 * care about (at least some) page faults, and because it is not easy
7585 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7586 * to exit on each and every L2 page fault. This is done by setting
7587 * MASK=MATCH=0 and (see below) EB.PF=1.
7588 * Note that below we don't need special code to set EB.PF beyond the
7589 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7590 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7591 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7593 * A problem with this approach (when !enable_ept) is that L1 may be
7594 * injected with more page faults than it asked for. This could have
7595 * caused problems, but in practice existing hypervisors don't care.
7596 * To fix this, we will need to emulate the PFEC checking (on the L1
7597 * page tables), using walk_addr(), when injecting PFs to L1.
7599 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7600 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7601 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7602 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7604 if (cpu_has_secondary_exec_ctrls()) {
7605 u32 exec_control = vmx_secondary_exec_control(vmx);
7606 if (!vmx->rdtscp_enabled)
7607 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7608 /* Take the following fields only from vmcs12 */
7609 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7610 if (nested_cpu_has(vmcs12,
7611 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7612 exec_control |= vmcs12->secondary_vm_exec_control;
7614 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7616 * Translate L1 physical address to host physical
7617 * address for vmcs02. Keep the page pinned, so this
7618 * physical address remains valid. We keep a reference
7619 * to it so we can release it later.
7621 if (vmx->nested.apic_access_page) /* shouldn't happen */
7622 nested_release_page(vmx->nested.apic_access_page);
7623 vmx->nested.apic_access_page =
7624 nested_get_page(vcpu, vmcs12->apic_access_addr);
7626 * If translation failed, no matter: This feature asks
7627 * to exit when accessing the given address, and if it
7628 * can never be accessed, this feature won't do
7631 if (!vmx->nested.apic_access_page)
7633 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7635 vmcs_write64(APIC_ACCESS_ADDR,
7636 page_to_phys(vmx->nested.apic_access_page));
7639 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7644 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7645 * Some constant fields are set here by vmx_set_constant_host_state().
7646 * Other fields are different per CPU, and will be set later when
7647 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7649 vmx_set_constant_host_state(vmx);
7652 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7653 * entry, but only if the current (host) sp changed from the value
7654 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7655 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7656 * here we just force the write to happen on entry.
7660 exec_control = vmx_exec_control(vmx); /* L0's desires */
7661 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7662 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7663 exec_control &= ~CPU_BASED_TPR_SHADOW;
7664 exec_control |= vmcs12->cpu_based_vm_exec_control;
7666 * Merging of IO and MSR bitmaps not currently supported.
7667 * Rather, exit every time.
7669 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7670 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7671 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7673 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7675 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7676 * bitwise-or of what L1 wants to trap for L2, and what we want to
7677 * trap. Note that CR0.TS also needs updating - we do this later.
7679 update_exception_bitmap(vcpu);
7680 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7681 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7683 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7684 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7685 * bits are further modified by vmx_set_efer() below.
7687 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7689 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7690 * emulated by vmx_set_efer(), below.
7692 vmcs_write32(VM_ENTRY_CONTROLS,
7693 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7694 ~VM_ENTRY_IA32E_MODE) |
7695 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7697 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7698 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7699 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7700 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7703 set_cr4_guest_host_mask(vmx);
7705 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7706 vmcs_write64(TSC_OFFSET,
7707 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7709 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7713 * Trivially support vpid by letting L2s share their parent
7714 * L1's vpid. TODO: move to a more elaborate solution, giving
7715 * each L2 its own vpid and exposing the vpid feature to L1.
7717 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7718 vmx_flush_tlb(vcpu);
7721 if (nested_cpu_has_ept(vmcs12)) {
7722 kvm_mmu_unload(vcpu);
7723 nested_ept_init_mmu_context(vcpu);
7726 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7727 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7728 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7729 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7731 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7732 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7733 vmx_set_efer(vcpu, vcpu->arch.efer);
7736 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7737 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7738 * The CR0_READ_SHADOW is what L2 should have expected to read given
7739 * the specifications by L1; It's not enough to take
7740 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7741 * have more bits than L1 expected.
7743 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7744 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7746 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7747 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7749 /* shadow page tables on either EPT or shadow page tables */
7750 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7751 kvm_mmu_reset_context(vcpu);
7754 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7757 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7758 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7759 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7760 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7763 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7764 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7768 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7769 * for running an L2 nested guest.
7771 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7773 struct vmcs12 *vmcs12;
7774 struct vcpu_vmx *vmx = to_vmx(vcpu);
7776 struct loaded_vmcs *vmcs02;
7779 if (!nested_vmx_check_permission(vcpu) ||
7780 !nested_vmx_check_vmcs12(vcpu))
7783 skip_emulated_instruction(vcpu);
7784 vmcs12 = get_vmcs12(vcpu);
7786 if (enable_shadow_vmcs)
7787 copy_shadow_to_vmcs12(vmx);
7790 * The nested entry process starts with enforcing various prerequisites
7791 * on vmcs12 as required by the Intel SDM, and act appropriately when
7792 * they fail: As the SDM explains, some conditions should cause the
7793 * instruction to fail, while others will cause the instruction to seem
7794 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7795 * To speed up the normal (success) code path, we should avoid checking
7796 * for misconfigurations which will anyway be caught by the processor
7797 * when using the merged vmcs02.
7799 if (vmcs12->launch_state == launch) {
7800 nested_vmx_failValid(vcpu,
7801 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7802 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7806 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7807 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7811 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7812 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7813 /*TODO: Also verify bits beyond physical address width are 0*/
7814 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7818 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7819 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7820 /*TODO: Also verify bits beyond physical address width are 0*/
7821 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7825 if (vmcs12->vm_entry_msr_load_count > 0 ||
7826 vmcs12->vm_exit_msr_load_count > 0 ||
7827 vmcs12->vm_exit_msr_store_count > 0) {
7828 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7830 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7834 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7835 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7836 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7837 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7838 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7839 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7840 !vmx_control_verify(vmcs12->vm_exit_controls,
7841 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7842 !vmx_control_verify(vmcs12->vm_entry_controls,
7843 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7845 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7849 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7850 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7851 nested_vmx_failValid(vcpu,
7852 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7856 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7857 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7858 nested_vmx_entry_failure(vcpu, vmcs12,
7859 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7862 if (vmcs12->vmcs_link_pointer != -1ull) {
7863 nested_vmx_entry_failure(vcpu, vmcs12,
7864 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7869 * If the load IA32_EFER VM-entry control is 1, the following checks
7870 * are performed on the field for the IA32_EFER MSR:
7871 * - Bits reserved in the IA32_EFER MSR must be 0.
7872 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7873 * the IA-32e mode guest VM-exit control. It must also be identical
7874 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7877 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7878 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7879 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7880 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7881 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7882 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7883 nested_vmx_entry_failure(vcpu, vmcs12,
7884 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7890 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7891 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7892 * the values of the LMA and LME bits in the field must each be that of
7893 * the host address-space size VM-exit control.
7895 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7896 ia32e = (vmcs12->vm_exit_controls &
7897 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7898 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7899 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7900 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7901 nested_vmx_entry_failure(vcpu, vmcs12,
7902 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7908 * We're finally done with prerequisite checking, and can start with
7912 vmcs02 = nested_get_current_vmcs02(vmx);
7916 enter_guest_mode(vcpu);
7918 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7921 vmx->loaded_vmcs = vmcs02;
7923 vmx_vcpu_load(vcpu, cpu);
7927 vmx_segment_cache_clear(vmx);
7929 vmcs12->launch_state = 1;
7931 prepare_vmcs02(vcpu, vmcs12);
7934 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7935 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7936 * returned as far as L1 is concerned. It will only return (and set
7937 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7943 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7944 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7945 * This function returns the new value we should put in vmcs12.guest_cr0.
7946 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7947 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7948 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7949 * didn't trap the bit, because if L1 did, so would L0).
7950 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7951 * been modified by L2, and L1 knows it. So just leave the old value of
7952 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7953 * isn't relevant, because if L0 traps this bit it can set it to anything.
7954 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7955 * changed these bits, and therefore they need to be updated, but L0
7956 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7957 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7959 static inline unsigned long
7960 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7963 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7964 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7965 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7966 vcpu->arch.cr0_guest_owned_bits));
7969 static inline unsigned long
7970 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7973 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7974 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7975 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7976 vcpu->arch.cr4_guest_owned_bits));
7979 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7980 struct vmcs12 *vmcs12)
7985 if (vcpu->arch.exception.pending) {
7986 nr = vcpu->arch.exception.nr;
7987 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7989 if (kvm_exception_is_soft(nr)) {
7990 vmcs12->vm_exit_instruction_len =
7991 vcpu->arch.event_exit_inst_len;
7992 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7994 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7996 if (vcpu->arch.exception.has_error_code) {
7997 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7998 vmcs12->idt_vectoring_error_code =
7999 vcpu->arch.exception.error_code;
8002 vmcs12->idt_vectoring_info_field = idt_vectoring;
8003 } else if (vcpu->arch.nmi_pending) {
8004 vmcs12->idt_vectoring_info_field =
8005 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8006 } else if (vcpu->arch.interrupt.pending) {
8007 nr = vcpu->arch.interrupt.nr;
8008 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8010 if (vcpu->arch.interrupt.soft) {
8011 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8012 vmcs12->vm_entry_instruction_len =
8013 vcpu->arch.event_exit_inst_len;
8015 idt_vectoring |= INTR_TYPE_EXT_INTR;
8017 vmcs12->idt_vectoring_info_field = idt_vectoring;
8022 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8023 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8024 * and this function updates it to reflect the changes to the guest state while
8025 * L2 was running (and perhaps made some exits which were handled directly by L0
8026 * without going back to L1), and to reflect the exit reason.
8027 * Note that we do not have to copy here all VMCS fields, just those that
8028 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8029 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8030 * which already writes to vmcs12 directly.
8032 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8034 /* update guest state fields: */
8035 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8036 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8038 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8039 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8040 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8041 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8043 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8044 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8045 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8046 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8047 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8048 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8049 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8050 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8051 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8052 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8053 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8054 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8055 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8056 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8057 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8058 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8059 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8060 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8061 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8062 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8063 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8064 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8065 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8066 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8067 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8068 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8069 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8070 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8071 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8072 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8073 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8074 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8075 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8076 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8077 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8078 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8080 vmcs12->guest_interruptibility_info =
8081 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8082 vmcs12->guest_pending_dbg_exceptions =
8083 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8086 * In some cases (usually, nested EPT), L2 is allowed to change its
8087 * own CR3 without exiting. If it has changed it, we must keep it.
8088 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8089 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8091 * Additionally, restore L2's PDPTR to vmcs12.
8094 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8095 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8096 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8097 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8098 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8101 vmcs12->vm_entry_controls =
8102 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8103 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8105 /* TODO: These cannot have changed unless we have MSR bitmaps and
8106 * the relevant bit asks not to trap the change */
8107 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8108 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8109 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8110 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8111 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8112 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8114 /* update exit information fields: */
8116 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
8117 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8119 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8120 if ((vmcs12->vm_exit_intr_info &
8121 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8122 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8123 vmcs12->vm_exit_intr_error_code =
8124 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8125 vmcs12->idt_vectoring_info_field = 0;
8126 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8127 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8129 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8130 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8131 * instead of reading the real value. */
8132 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8135 * Transfer the event that L0 or L1 may wanted to inject into
8136 * L2 to IDT_VECTORING_INFO_FIELD.
8138 vmcs12_save_pending_event(vcpu, vmcs12);
8142 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8143 * preserved above and would only end up incorrectly in L1.
8145 vcpu->arch.nmi_injected = false;
8146 kvm_clear_exception_queue(vcpu);
8147 kvm_clear_interrupt_queue(vcpu);
8151 * A part of what we need to when the nested L2 guest exits and we want to
8152 * run its L1 parent, is to reset L1's guest state to the host state specified
8154 * This function is to be called not only on normal nested exit, but also on
8155 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8156 * Failures During or After Loading Guest State").
8157 * This function should be called when the active VMCS is L1's (vmcs01).
8159 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8160 struct vmcs12 *vmcs12)
8162 struct kvm_segment seg;
8164 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8165 vcpu->arch.efer = vmcs12->host_ia32_efer;
8166 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8167 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8169 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8170 vmx_set_efer(vcpu, vcpu->arch.efer);
8172 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8173 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8174 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8176 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8177 * actually changed, because it depends on the current state of
8178 * fpu_active (which may have changed).
8179 * Note that vmx_set_cr0 refers to efer set above.
8181 kvm_set_cr0(vcpu, vmcs12->host_cr0);
8183 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8184 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8185 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8187 update_exception_bitmap(vcpu);
8188 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8189 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8192 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8193 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8195 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8196 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8198 if (nested_cpu_has_ept(vmcs12))
8199 nested_ept_uninit_mmu_context(vcpu);
8201 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8202 kvm_mmu_reset_context(vcpu);
8206 * Trivially support vpid by letting L2s share their parent
8207 * L1's vpid. TODO: move to a more elaborate solution, giving
8208 * each L2 its own vpid and exposing the vpid feature to L1.
8210 vmx_flush_tlb(vcpu);
8214 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8215 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8216 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8217 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8218 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8220 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8221 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8222 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8223 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8224 vmcs12->host_ia32_perf_global_ctrl);
8226 /* Set L1 segment info according to Intel SDM
8227 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8228 seg = (struct kvm_segment) {
8230 .limit = 0xFFFFFFFF,
8231 .selector = vmcs12->host_cs_selector,
8237 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8241 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8242 seg = (struct kvm_segment) {
8244 .limit = 0xFFFFFFFF,
8251 seg.selector = vmcs12->host_ds_selector;
8252 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8253 seg.selector = vmcs12->host_es_selector;
8254 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8255 seg.selector = vmcs12->host_ss_selector;
8256 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8257 seg.selector = vmcs12->host_fs_selector;
8258 seg.base = vmcs12->host_fs_base;
8259 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8260 seg.selector = vmcs12->host_gs_selector;
8261 seg.base = vmcs12->host_gs_base;
8262 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8263 seg = (struct kvm_segment) {
8264 .base = vmcs12->host_tr_base,
8266 .selector = vmcs12->host_tr_selector,
8270 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8272 kvm_set_dr(vcpu, 7, 0x400);
8273 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8277 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8278 * and modify vmcs12 to make it see what it would expect to see there if
8279 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8281 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8283 struct vcpu_vmx *vmx = to_vmx(vcpu);
8285 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8287 /* trying to cancel vmlaunch/vmresume is a bug */
8288 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8290 leave_guest_mode(vcpu);
8291 prepare_vmcs12(vcpu, vmcs12);
8294 vmx->loaded_vmcs = &vmx->vmcs01;
8296 vmx_vcpu_load(vcpu, cpu);
8300 vmx_segment_cache_clear(vmx);
8302 /* if no vmcs02 cache requested, remove the one we used */
8303 if (VMCS02_POOL_SIZE == 0)
8304 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8306 load_vmcs12_host_state(vcpu, vmcs12);
8308 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8309 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8311 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8314 /* Unpin physical memory we referred to in vmcs02 */
8315 if (vmx->nested.apic_access_page) {
8316 nested_release_page(vmx->nested.apic_access_page);
8317 vmx->nested.apic_access_page = 0;
8321 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8322 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8323 * success or failure flag accordingly.
8325 if (unlikely(vmx->fail)) {
8327 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8329 nested_vmx_succeed(vcpu);
8330 if (enable_shadow_vmcs)
8331 vmx->nested.sync_shadow_vmcs = true;
8335 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8336 * 23.7 "VM-entry failures during or after loading guest state" (this also
8337 * lists the acceptable exit-reason and exit-qualification parameters).
8338 * It should only be called before L2 actually succeeded to run, and when
8339 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8341 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8342 struct vmcs12 *vmcs12,
8343 u32 reason, unsigned long qualification)
8345 load_vmcs12_host_state(vcpu, vmcs12);
8346 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8347 vmcs12->exit_qualification = qualification;
8348 nested_vmx_succeed(vcpu);
8349 if (enable_shadow_vmcs)
8350 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8353 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8354 struct x86_instruction_info *info,
8355 enum x86_intercept_stage stage)
8357 return X86EMUL_CONTINUE;
8360 static struct kvm_x86_ops vmx_x86_ops = {
8361 .cpu_has_kvm_support = cpu_has_kvm_support,
8362 .disabled_by_bios = vmx_disabled_by_bios,
8363 .hardware_setup = hardware_setup,
8364 .hardware_unsetup = hardware_unsetup,
8365 .check_processor_compatibility = vmx_check_processor_compat,
8366 .hardware_enable = hardware_enable,
8367 .hardware_disable = hardware_disable,
8368 .cpu_has_accelerated_tpr = report_flexpriority,
8370 .vcpu_create = vmx_create_vcpu,
8371 .vcpu_free = vmx_free_vcpu,
8372 .vcpu_reset = vmx_vcpu_reset,
8374 .prepare_guest_switch = vmx_save_host_state,
8375 .vcpu_load = vmx_vcpu_load,
8376 .vcpu_put = vmx_vcpu_put,
8378 .update_db_bp_intercept = update_exception_bitmap,
8379 .get_msr = vmx_get_msr,
8380 .set_msr = vmx_set_msr,
8381 .get_segment_base = vmx_get_segment_base,
8382 .get_segment = vmx_get_segment,
8383 .set_segment = vmx_set_segment,
8384 .get_cpl = vmx_get_cpl,
8385 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8386 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8387 .decache_cr3 = vmx_decache_cr3,
8388 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8389 .set_cr0 = vmx_set_cr0,
8390 .set_cr3 = vmx_set_cr3,
8391 .set_cr4 = vmx_set_cr4,
8392 .set_efer = vmx_set_efer,
8393 .get_idt = vmx_get_idt,
8394 .set_idt = vmx_set_idt,
8395 .get_gdt = vmx_get_gdt,
8396 .set_gdt = vmx_set_gdt,
8397 .set_dr7 = vmx_set_dr7,
8398 .cache_reg = vmx_cache_reg,
8399 .get_rflags = vmx_get_rflags,
8400 .set_rflags = vmx_set_rflags,
8401 .fpu_activate = vmx_fpu_activate,
8402 .fpu_deactivate = vmx_fpu_deactivate,
8404 .tlb_flush = vmx_flush_tlb,
8406 .run = vmx_vcpu_run,
8407 .handle_exit = vmx_handle_exit,
8408 .skip_emulated_instruction = skip_emulated_instruction,
8409 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8410 .get_interrupt_shadow = vmx_get_interrupt_shadow,
8411 .patch_hypercall = vmx_patch_hypercall,
8412 .set_irq = vmx_inject_irq,
8413 .set_nmi = vmx_inject_nmi,
8414 .queue_exception = vmx_queue_exception,
8415 .cancel_injection = vmx_cancel_injection,
8416 .interrupt_allowed = vmx_interrupt_allowed,
8417 .nmi_allowed = vmx_nmi_allowed,
8418 .get_nmi_mask = vmx_get_nmi_mask,
8419 .set_nmi_mask = vmx_set_nmi_mask,
8420 .enable_nmi_window = enable_nmi_window,
8421 .enable_irq_window = enable_irq_window,
8422 .update_cr8_intercept = update_cr8_intercept,
8423 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8424 .vm_has_apicv = vmx_vm_has_apicv,
8425 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8426 .hwapic_irr_update = vmx_hwapic_irr_update,
8427 .hwapic_isr_update = vmx_hwapic_isr_update,
8428 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8429 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8431 .set_tss_addr = vmx_set_tss_addr,
8432 .get_tdp_level = get_ept_level,
8433 .get_mt_mask = vmx_get_mt_mask,
8435 .get_exit_info = vmx_get_exit_info,
8437 .get_lpage_level = vmx_get_lpage_level,
8439 .cpuid_update = vmx_cpuid_update,
8441 .rdtscp_supported = vmx_rdtscp_supported,
8442 .invpcid_supported = vmx_invpcid_supported,
8444 .set_supported_cpuid = vmx_set_supported_cpuid,
8446 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8448 .set_tsc_khz = vmx_set_tsc_khz,
8449 .read_tsc_offset = vmx_read_tsc_offset,
8450 .write_tsc_offset = vmx_write_tsc_offset,
8451 .adjust_tsc_offset = vmx_adjust_tsc_offset,
8452 .compute_tsc_offset = vmx_compute_tsc_offset,
8453 .read_l1_tsc = vmx_read_l1_tsc,
8455 .set_tdp_cr3 = vmx_set_cr3,
8457 .check_intercept = vmx_check_intercept,
8458 .handle_external_intr = vmx_handle_external_intr,
8461 static int __init vmx_init(void)
8465 rdmsrl_safe(MSR_EFER, &host_efer);
8467 for (i = 0; i < NR_VMX_MSR; ++i)
8468 kvm_define_shared_msr(i, vmx_msr_index[i]);
8470 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8471 if (!vmx_io_bitmap_a)
8476 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8477 if (!vmx_io_bitmap_b)
8480 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8481 if (!vmx_msr_bitmap_legacy)
8484 vmx_msr_bitmap_legacy_x2apic =
8485 (unsigned long *)__get_free_page(GFP_KERNEL);
8486 if (!vmx_msr_bitmap_legacy_x2apic)
8489 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8490 if (!vmx_msr_bitmap_longmode)
8493 vmx_msr_bitmap_longmode_x2apic =
8494 (unsigned long *)__get_free_page(GFP_KERNEL);
8495 if (!vmx_msr_bitmap_longmode_x2apic)
8497 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8498 if (!vmx_vmread_bitmap)
8501 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8502 if (!vmx_vmwrite_bitmap)
8505 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8506 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8507 /* shadowed read/write fields */
8508 for (i = 0; i < max_shadow_read_write_fields; i++) {
8509 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8510 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8512 /* shadowed read only fields */
8513 for (i = 0; i < max_shadow_read_only_fields; i++)
8514 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8517 * Allow direct access to the PC debug port (it is often used for I/O
8518 * delays, but the vmexits simply slow things down).
8520 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8521 clear_bit(0x80, vmx_io_bitmap_a);
8523 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8525 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8526 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8528 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8530 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8531 __alignof__(struct vcpu_vmx), THIS_MODULE);
8536 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8537 crash_vmclear_local_loaded_vmcss);
8540 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8541 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8542 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8543 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8544 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8545 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8546 memcpy(vmx_msr_bitmap_legacy_x2apic,
8547 vmx_msr_bitmap_legacy, PAGE_SIZE);
8548 memcpy(vmx_msr_bitmap_longmode_x2apic,
8549 vmx_msr_bitmap_longmode, PAGE_SIZE);
8552 for (msr = 0x800; msr <= 0x8ff; msr++)
8553 vmx_disable_intercept_msr_read_x2apic(msr);
8555 /* According SDM, in x2apic mode, the whole id reg is used.
8556 * But in KVM, it only use the highest eight bits. Need to
8558 vmx_enable_intercept_msr_read_x2apic(0x802);
8560 vmx_enable_intercept_msr_read_x2apic(0x839);
8562 vmx_disable_intercept_msr_write_x2apic(0x808);
8564 vmx_disable_intercept_msr_write_x2apic(0x80b);
8566 vmx_disable_intercept_msr_write_x2apic(0x83f);
8570 kvm_mmu_set_mask_ptes(0ull,
8571 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8572 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8573 0ull, VMX_EPT_EXECUTABLE_MASK);
8574 ept_set_mmio_spte_mask();
8582 free_page((unsigned long)vmx_vmwrite_bitmap);
8584 free_page((unsigned long)vmx_vmread_bitmap);
8586 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8588 free_page((unsigned long)vmx_msr_bitmap_longmode);
8590 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8592 free_page((unsigned long)vmx_msr_bitmap_legacy);
8594 free_page((unsigned long)vmx_io_bitmap_b);
8596 free_page((unsigned long)vmx_io_bitmap_a);
8600 static void __exit vmx_exit(void)
8602 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8603 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8604 free_page((unsigned long)vmx_msr_bitmap_legacy);
8605 free_page((unsigned long)vmx_msr_bitmap_longmode);
8606 free_page((unsigned long)vmx_io_bitmap_b);
8607 free_page((unsigned long)vmx_io_bitmap_a);
8608 free_page((unsigned long)vmx_vmwrite_bitmap);
8609 free_page((unsigned long)vmx_vmread_bitmap);
8612 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8619 module_init(vmx_init)
8620 module_exit(vmx_exit)