Pileus Git - ~andy/linux/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376         u64 msr_ia32_feature_control;
 377 };
 378
 379 #define POSTED_INTR_ON  0
 380 /* Posted-Interrupt Descriptor */
 381 struct pi_desc {
 382         u32 pir[8];     /* Posted interrupt requested */
 383         u32 control;    /* bit 0 of control is outstanding notification bit */
 384         u32 rsvd[7];
 385 } __aligned(64);
 386
 387 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 388 {
 389         return test_and_set_bit(POSTED_INTR_ON,
 390                         (unsigned long *)&pi_desc->control);
 391 }
 392
 393 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 394 {
 395         return test_and_clear_bit(POSTED_INTR_ON,
 396                         (unsigned long *)&pi_desc->control);
 397 }
 398
 399 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 400 {
 401         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 402 }
 403
 404 struct vcpu_vmx {
 405         struct kvm_vcpu       vcpu;
 406         unsigned long         host_rsp;
 407         u8                    fail;
 408         u8                    cpl;
 409         bool                  nmi_known_unmasked;
 410         u32                   exit_intr_info;
 411         u32                   idt_vectoring_info;
 412         ulong                 rflags;
 413         struct shared_msr_entry *guest_msrs;
 414         int                   nmsrs;
 415         int                   save_nmsrs;
 416         unsigned long         host_idt_base;
 417 #ifdef CONFIG_X86_64
 418         u64                   msr_host_kernel_gs_base;
 419         u64                   msr_guest_kernel_gs_base;
 420 #endif
 421         /*
 422          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 423          * non-nested (L1) guest, it always points to vmcs01. For a nested
 424          * guest (L2), it points to a different VMCS.
 425          */
 426         struct loaded_vmcs    vmcs01;
 427         struct loaded_vmcs   *loaded_vmcs;
 428         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 429         struct msr_autoload {
 430                 unsigned nr;
 431                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 432                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 433         } msr_autoload;
 434         struct {
 435                 int           loaded;
 436                 u16           fs_sel, gs_sel, ldt_sel;
 437 #ifdef CONFIG_X86_64
 438                 u16           ds_sel, es_sel;
 439 #endif
 440                 int           gs_ldt_reload_needed;
 441                 int           fs_reload_needed;
 442         } host_state;
 443         struct {
 444                 int vm86_active;
 445                 ulong save_rflags;
 446                 struct kvm_segment segs[8];
 447         } rmode;
 448         struct {
 449                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 450                 struct kvm_save_segment {
 451                         u16 selector;
 452                         unsigned long base;
 453                         u32 limit;
 454                         u32 ar;
 455                 } seg[8];
 456         } segment_cache;
 457         int vpid;
 458         bool emulation_required;
 459
 460         /* Support for vnmi-less CPUs */
 461         int soft_vnmi_blocked;
 462         ktime_t entry_time;
 463         s64 vnmi_blocked_time;
 464         u32 exit_reason;
 465
 466         bool rdtscp_enabled;
 467
 468         /* Posted interrupt descriptor */
 469         struct pi_desc pi_desc;
 470
 471         /* Support for a guest hypervisor (nested VMX) */
 472         struct nested_vmx nested;
 473 };
 474
 475 enum segment_cache_field {
 476         SEG_FIELD_SEL = 0,
 477         SEG_FIELD_BASE = 1,
 478         SEG_FIELD_LIMIT = 2,
 479         SEG_FIELD_AR = 3,
 480
 481         SEG_FIELD_NR = 4
 482 };
 483
 484 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 485 {
 486         return container_of(vcpu, struct vcpu_vmx, vcpu);
 487 }
 488
 489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 490 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 491 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 492                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 493
 494
 495 static const unsigned long shadow_read_only_fields[] = {
 496         /*
 497          * We do NOT shadow fields that are modified when L0
 498          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 499          * VMXON...) executed by L1.
 500          * For example, VM_INSTRUCTION_ERROR is read
 501          * by L1 if a vmx instruction fails (part of the error path).
 502          * Note the code assumes this logic. If for some reason
 503          * we start shadowing these fields then we need to
 504          * force a shadow sync when L0 emulates vmx instructions
 505          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 506          * by nested_vmx_failValid)
 507          */
 508         VM_EXIT_REASON,
 509         VM_EXIT_INTR_INFO,
 510         VM_EXIT_INSTRUCTION_LEN,
 511         IDT_VECTORING_INFO_FIELD,
 512         IDT_VECTORING_ERROR_CODE,
 513         VM_EXIT_INTR_ERROR_CODE,
 514         EXIT_QUALIFICATION,
 515         GUEST_LINEAR_ADDRESS,
 516         GUEST_PHYSICAL_ADDRESS
 517 };
 518 static const int max_shadow_read_only_fields =
 519         ARRAY_SIZE(shadow_read_only_fields);
 520
 521 static const unsigned long shadow_read_write_fields[] = {
 522         GUEST_RIP,
 523         GUEST_RSP,
 524         GUEST_CR0,
 525         GUEST_CR3,
 526         GUEST_CR4,
 527         GUEST_INTERRUPTIBILITY_INFO,
 528         GUEST_RFLAGS,
 529         GUEST_CS_SELECTOR,
 530         GUEST_CS_AR_BYTES,
 531         GUEST_CS_LIMIT,
 532         GUEST_CS_BASE,
 533         GUEST_ES_BASE,
 534         CR0_GUEST_HOST_MASK,
 535         CR0_READ_SHADOW,
 536         CR4_READ_SHADOW,
 537         TSC_OFFSET,
 538         EXCEPTION_BITMAP,
 539         CPU_BASED_VM_EXEC_CONTROL,
 540         VM_ENTRY_EXCEPTION_ERROR_CODE,
 541         VM_ENTRY_INTR_INFO_FIELD,
 542         VM_ENTRY_INSTRUCTION_LEN,
 543         VM_ENTRY_EXCEPTION_ERROR_CODE,
 544         HOST_FS_BASE,
 545         HOST_GS_BASE,
 546         HOST_FS_SELECTOR,
 547         HOST_GS_SELECTOR
 548 };
 549 static const int max_shadow_read_write_fields =
 550         ARRAY_SIZE(shadow_read_write_fields);
 551
 552 static const unsigned short vmcs_field_to_offset_table[] = {
 553         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 554         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 555         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 556         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 557         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 558         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 559         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 560         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 561         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 562         FIELD(HOST_ES_SELECTOR, host_es_selector),
 563         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 564         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 565         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 566         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 567         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 568         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 569         FIELD64(IO_BITMAP_A, io_bitmap_a),
 570         FIELD64(IO_BITMAP_B, io_bitmap_b),
 571         FIELD64(MSR_BITMAP, msr_bitmap),
 572         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 573         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 574         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 575         FIELD64(TSC_OFFSET, tsc_offset),
 576         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 577         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 578         FIELD64(EPT_POINTER, ept_pointer),
 579         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 580         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 581         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 582         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 583         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 584         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 585         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 586         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 587         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 588         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 589         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 590         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 591         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 592         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 593         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 594         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 595         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 596         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 597         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 598         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 599         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 600         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 601         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 602         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 603         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 604         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 605         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 606         FIELD(TPR_THRESHOLD, tpr_threshold),
 607         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 608         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 609         FIELD(VM_EXIT_REASON, vm_exit_reason),
 610         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 611         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 612         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 613         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 614         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 615         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 616         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 617         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 618         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 619         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 620         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 621         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 622         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 623         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 624         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 625         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 626         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 627         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 628         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 629         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 630         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 631         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 632         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 633         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 634         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 635         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 636         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 637         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 638         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 639         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 640         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 641         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 642         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 643         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 644         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 645         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 646         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 647         FIELD(EXIT_QUALIFICATION, exit_qualification),
 648         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 649         FIELD(GUEST_CR0, guest_cr0),
 650         FIELD(GUEST_CR3, guest_cr3),
 651         FIELD(GUEST_CR4, guest_cr4),
 652         FIELD(GUEST_ES_BASE, guest_es_base),
 653         FIELD(GUEST_CS_BASE, guest_cs_base),
 654         FIELD(GUEST_SS_BASE, guest_ss_base),
 655         FIELD(GUEST_DS_BASE, guest_ds_base),
 656         FIELD(GUEST_FS_BASE, guest_fs_base),
 657         FIELD(GUEST_GS_BASE, guest_gs_base),
 658         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 659         FIELD(GUEST_TR_BASE, guest_tr_base),
 660         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 661         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 662         FIELD(GUEST_DR7, guest_dr7),
 663         FIELD(GUEST_RSP, guest_rsp),
 664         FIELD(GUEST_RIP, guest_rip),
 665         FIELD(GUEST_RFLAGS, guest_rflags),
 666         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 667         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 668         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 669         FIELD(HOST_CR0, host_cr0),
 670         FIELD(HOST_CR3, host_cr3),
 671         FIELD(HOST_CR4, host_cr4),
 672         FIELD(HOST_FS_BASE, host_fs_base),
 673         FIELD(HOST_GS_BASE, host_gs_base),
 674         FIELD(HOST_TR_BASE, host_tr_base),
 675         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 676         FIELD(HOST_IDTR_BASE, host_idtr_base),
 677         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 678         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 679         FIELD(HOST_RSP, host_rsp),
 680         FIELD(HOST_RIP, host_rip),
 681 };
 682 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 683
 684 static inline short vmcs_field_to_offset(unsigned long field)
 685 {
 686         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 687                 return -1;
 688         return vmcs_field_to_offset_table[field];
 689 }
 690
 691 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 692 {
 693         return to_vmx(vcpu)->nested.current_vmcs12;
 694 }
 695
 696 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 697 {
 698         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 699         if (is_error_page(page))
 700                 return NULL;
 701
 702         return page;
 703 }
 704
 705 static void nested_release_page(struct page *page)
 706 {
 707         kvm_release_page_dirty(page);
 708 }
 709
 710 static void nested_release_page_clean(struct page *page)
 711 {
 712         kvm_release_page_clean(page);
 713 }
 714
 715 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 716 static u64 construct_eptp(unsigned long root_hpa);
 717 static void kvm_cpu_vmxon(u64 addr);
 718 static void kvm_cpu_vmxoff(void);
 719 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 720 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 721 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 722                             struct kvm_segment *var, int seg);
 723 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 724                             struct kvm_segment *var, int seg);
 725 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 726 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 727 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 728 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 729 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 730
 731 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 732 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 733 /*
 734  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 735  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 736  */
 737 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 738 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 739
 740 static unsigned long *vmx_io_bitmap_a;
 741 static unsigned long *vmx_io_bitmap_b;
 742 static unsigned long *vmx_msr_bitmap_legacy;
 743 static unsigned long *vmx_msr_bitmap_longmode;
 744 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 745 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 746 static unsigned long *vmx_vmread_bitmap;
 747 static unsigned long *vmx_vmwrite_bitmap;
 748
 749 static bool cpu_has_load_ia32_efer;
 750 static bool cpu_has_load_perf_global_ctrl;
 751
 752 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 753 static DEFINE_SPINLOCK(vmx_vpid_lock);
 754
 755 static struct vmcs_config {
 756         int size;
 757         int order;
 758         u32 revision_id;
 759         u32 pin_based_exec_ctrl;
 760         u32 cpu_based_exec_ctrl;
 761         u32 cpu_based_2nd_exec_ctrl;
 762         u32 vmexit_ctrl;
 763         u32 vmentry_ctrl;
 764 } vmcs_config;
 765
 766 static struct vmx_capability {
 767         u32 ept;
 768         u32 vpid;
 769 } vmx_capability;
 770
 771 #define VMX_SEGMENT_FIELD(seg)                                  \
 772         [VCPU_SREG_##seg] = {                                   \
 773                 .selector = GUEST_##seg##_SELECTOR,             \
 774                 .base = GUEST_##seg##_BASE,                     \
 775                 .limit = GUEST_##seg##_LIMIT,                   \
 776                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 777         }
 778
 779 static const struct kvm_vmx_segment_field {
 780         unsigned selector;
 781         unsigned base;
 782         unsigned limit;
 783         unsigned ar_bytes;
 784 } kvm_vmx_segment_fields[] = {
 785         VMX_SEGMENT_FIELD(CS),
 786         VMX_SEGMENT_FIELD(DS),
 787         VMX_SEGMENT_FIELD(ES),
 788         VMX_SEGMENT_FIELD(FS),
 789         VMX_SEGMENT_FIELD(GS),
 790         VMX_SEGMENT_FIELD(SS),
 791         VMX_SEGMENT_FIELD(TR),
 792         VMX_SEGMENT_FIELD(LDTR),
 793 };
 794
 795 static u64 host_efer;
 796
 797 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 798
 799 /*
 800  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 801  * away by decrementing the array size.
 802  */
 803 static const u32 vmx_msr_index[] = {
 804 #ifdef CONFIG_X86_64
 805         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 806 #endif
 807         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 808 };
 809 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 810
 811 static inline bool is_page_fault(u32 intr_info)
 812 {
 813         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 814                              INTR_INFO_VALID_MASK)) ==
 815                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 816 }
 817
 818 static inline bool is_no_device(u32 intr_info)
 819 {
 820         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 821                              INTR_INFO_VALID_MASK)) ==
 822                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 823 }
 824
 825 static inline bool is_invalid_opcode(u32 intr_info)
 826 {
 827         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 828                              INTR_INFO_VALID_MASK)) ==
 829                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 830 }
 831
 832 static inline bool is_external_interrupt(u32 intr_info)
 833 {
 834         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 835                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 836 }
 837
 838 static inline bool is_machine_check(u32 intr_info)
 839 {
 840         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 841                              INTR_INFO_VALID_MASK)) ==
 842                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 843 }
 844
 845 static inline bool cpu_has_vmx_msr_bitmap(void)
 846 {
 847         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 848 }
 849
 850 static inline bool cpu_has_vmx_tpr_shadow(void)
 851 {
 852         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 853 }
 854
 855 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 856 {
 857         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 858 }
 859
 860 static inline bool cpu_has_secondary_exec_ctrls(void)
 861 {
 862         return vmcs_config.cpu_based_exec_ctrl &
 863                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 864 }
 865
 866 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 867 {
 868         return vmcs_config.cpu_based_2nd_exec_ctrl &
 869                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 870 }
 871
 872 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 873 {
 874         return vmcs_config.cpu_based_2nd_exec_ctrl &
 875                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 876 }
 877
 878 static inline bool cpu_has_vmx_apic_register_virt(void)
 879 {
 880         return vmcs_config.cpu_based_2nd_exec_ctrl &
 881                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 882 }
 883
 884 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 885 {
 886         return vmcs_config.cpu_based_2nd_exec_ctrl &
 887                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 888 }
 889
 890 static inline bool cpu_has_vmx_posted_intr(void)
 891 {
 892         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 893 }
 894
 895 static inline bool cpu_has_vmx_apicv(void)
 896 {
 897         return cpu_has_vmx_apic_register_virt() &&
 898                 cpu_has_vmx_virtual_intr_delivery() &&
 899                 cpu_has_vmx_posted_intr();
 900 }
 901
 902 static inline bool cpu_has_vmx_flexpriority(void)
 903 {
 904         return cpu_has_vmx_tpr_shadow() &&
 905                 cpu_has_vmx_virtualize_apic_accesses();
 906 }
 907
 908 static inline bool cpu_has_vmx_ept_execute_only(void)
 909 {
 910         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 911 }
 912
 913 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 914 {
 915         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 916 }
 917
 918 static inline bool cpu_has_vmx_eptp_writeback(void)
 919 {
 920         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 921 }
 922
 923 static inline bool cpu_has_vmx_ept_2m_page(void)
 924 {
 925         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 926 }
 927
 928 static inline bool cpu_has_vmx_ept_1g_page(void)
 929 {
 930         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 931 }
 932
 933 static inline bool cpu_has_vmx_ept_4levels(void)
 934 {
 935         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 936 }
 937
 938 static inline bool cpu_has_vmx_ept_ad_bits(void)
 939 {
 940         return vmx_capability.ept & VMX_EPT_AD_BIT;
 941 }
 942
 943 static inline bool cpu_has_vmx_invept_context(void)
 944 {
 945         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 946 }
 947
 948 static inline bool cpu_has_vmx_invept_global(void)
 949 {
 950         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 951 }
 952
 953 static inline bool cpu_has_vmx_invvpid_single(void)
 954 {
 955         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 956 }
 957
 958 static inline bool cpu_has_vmx_invvpid_global(void)
 959 {
 960         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 961 }
 962
 963 static inline bool cpu_has_vmx_ept(void)
 964 {
 965         return vmcs_config.cpu_based_2nd_exec_ctrl &
 966                 SECONDARY_EXEC_ENABLE_EPT;
 967 }
 968
 969 static inline bool cpu_has_vmx_unrestricted_guest(void)
 970 {
 971         return vmcs_config.cpu_based_2nd_exec_ctrl &
 972                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 973 }
 974
 975 static inline bool cpu_has_vmx_ple(void)
 976 {
 977         return vmcs_config.cpu_based_2nd_exec_ctrl &
 978                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 979 }
 980
 981 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 982 {
 983         return flexpriority_enabled && irqchip_in_kernel(kvm);
 984 }
 985
 986 static inline bool cpu_has_vmx_vpid(void)
 987 {
 988         return vmcs_config.cpu_based_2nd_exec_ctrl &
 989                 SECONDARY_EXEC_ENABLE_VPID;
 990 }
 991
 992 static inline bool cpu_has_vmx_rdtscp(void)
 993 {
 994         return vmcs_config.cpu_based_2nd_exec_ctrl &
 995                 SECONDARY_EXEC_RDTSCP;
 996 }
 997
 998 static inline bool cpu_has_vmx_invpcid(void)
 999 {
1000         return vmcs_config.cpu_based_2nd_exec_ctrl &
1001                 SECONDARY_EXEC_ENABLE_INVPCID;
1002 }
1003
1004 static inline bool cpu_has_virtual_nmis(void)
1005 {
1006         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1007 }
1008
1009 static inline bool cpu_has_vmx_wbinvd_exit(void)
1010 {
1011         return vmcs_config.cpu_based_2nd_exec_ctrl &
1012                 SECONDARY_EXEC_WBINVD_EXITING;
1013 }
1014
1015 static inline bool cpu_has_vmx_shadow_vmcs(void)
1016 {
1017         u64 vmx_msr;
1018         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1019         /* check if the cpu supports writing r/o exit information fields */
1020         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1021                 return false;
1022
1023         return vmcs_config.cpu_based_2nd_exec_ctrl &
1024                 SECONDARY_EXEC_SHADOW_VMCS;
1025 }
1026
1027 static inline bool report_flexpriority(void)
1028 {
1029         return flexpriority_enabled;
1030 }
1031
1032 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1033 {
1034         return vmcs12->cpu_based_vm_exec_control & bit;
1035 }
1036
1037 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1038 {
1039         return (vmcs12->cpu_based_vm_exec_control &
1040                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1041                 (vmcs12->secondary_vm_exec_control & bit);
1042 }
1043
1044 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1045         struct kvm_vcpu *vcpu)
1046 {
1047         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1048 }
1049
1050 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1051 {
1052         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1053 }
1054
1055 static inline bool is_exception(u32 intr_info)
1056 {
1057         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1058                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1059 }
1060
1061 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1062 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1063                         struct vmcs12 *vmcs12,
1064                         u32 reason, unsigned long qualification);
1065
1066 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1067 {
1068         int i;
1069
1070         for (i = 0; i < vmx->nmsrs; ++i)
1071                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1072                         return i;
1073         return -1;
1074 }
1075
1076 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1077 {
1078     struct {
1079         u64 vpid : 16;
1080         u64 rsvd : 48;
1081         u64 gva;
1082     } operand = { vpid, 0, gva };
1083
1084     asm volatile (__ex(ASM_VMX_INVVPID)
1085                   /* CF==1 or ZF==1 --> rc = -1 */
1086                   "; ja 1f ; ud2 ; 1:"
1087                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1088 }
1089
1090 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1091 {
1092         struct {
1093                 u64 eptp, gpa;
1094         } operand = {eptp, gpa};
1095
1096         asm volatile (__ex(ASM_VMX_INVEPT)
1097                         /* CF==1 or ZF==1 --> rc = -1 */
1098                         "; ja 1f ; ud2 ; 1:\n"
1099                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1100 }
1101
1102 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1103 {
1104         int i;
1105
1106         i = __find_msr_index(vmx, msr);
1107         if (i >= 0)
1108                 return &vmx->guest_msrs[i];
1109         return NULL;
1110 }
1111
1112 static void vmcs_clear(struct vmcs *vmcs)
1113 {
1114         u64 phys_addr = __pa(vmcs);
1115         u8 error;
1116
1117         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1118                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1119                       : "cc", "memory");
1120         if (error)
1121                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1122                        vmcs, phys_addr);
1123 }
1124
1125 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1126 {
1127         vmcs_clear(loaded_vmcs->vmcs);
1128         loaded_vmcs->cpu = -1;
1129         loaded_vmcs->launched = 0;
1130 }
1131
1132 static void vmcs_load(struct vmcs *vmcs)
1133 {
1134         u64 phys_addr = __pa(vmcs);
1135         u8 error;
1136
1137         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1138                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1139                         : "cc", "memory");
1140         if (error)
1141                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1142                        vmcs, phys_addr);
1143 }
1144
1145 #ifdef CONFIG_KEXEC
1146 /*
1147  * This bitmap is used to indicate whether the vmclear
1148  * operation is enabled on all cpus. All disabled by
1149  * default.
1150  */
1151 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1152
1153 static inline void crash_enable_local_vmclear(int cpu)
1154 {
1155         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1156 }
1157
1158 static inline void crash_disable_local_vmclear(int cpu)
1159 {
1160         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1161 }
1162
1163 static inline int crash_local_vmclear_enabled(int cpu)
1164 {
1165         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1166 }
1167
1168 static void crash_vmclear_local_loaded_vmcss(void)
1169 {
1170         int cpu = raw_smp_processor_id();
1171         struct loaded_vmcs *v;
1172
1173         if (!crash_local_vmclear_enabled(cpu))
1174                 return;
1175
1176         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1177                             loaded_vmcss_on_cpu_link)
1178                 vmcs_clear(v->vmcs);
1179 }
1180 #else
1181 static inline void crash_enable_local_vmclear(int cpu) { }
1182 static inline void crash_disable_local_vmclear(int cpu) { }
1183 #endif /* CONFIG_KEXEC */
1184
1185 static void __loaded_vmcs_clear(void *arg)
1186 {
1187         struct loaded_vmcs *loaded_vmcs = arg;
1188         int cpu = raw_smp_processor_id();
1189
1190         if (loaded_vmcs->cpu != cpu)
1191                 return; /* vcpu migration can race with cpu offline */
1192         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1193                 per_cpu(current_vmcs, cpu) = NULL;
1194         crash_disable_local_vmclear(cpu);
1195         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1196
1197         /*
1198          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1199          * is before setting loaded_vmcs->vcpu to -1 which is done in
1200          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1201          * then adds the vmcs into percpu list before it is deleted.
1202          */
1203         smp_wmb();
1204
1205         loaded_vmcs_init(loaded_vmcs);
1206         crash_enable_local_vmclear(cpu);
1207 }
1208
1209 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1210 {
1211         int cpu = loaded_vmcs->cpu;
1212
1213         if (cpu != -1)
1214                 smp_call_function_single(cpu,
1215                          __loaded_vmcs_clear, loaded_vmcs, 1);
1216 }
1217
1218 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1219 {
1220         if (vmx->vpid == 0)
1221                 return;
1222
1223         if (cpu_has_vmx_invvpid_single())
1224                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1225 }
1226
1227 static inline void vpid_sync_vcpu_global(void)
1228 {
1229         if (cpu_has_vmx_invvpid_global())
1230                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1231 }
1232
1233 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1234 {
1235         if (cpu_has_vmx_invvpid_single())
1236                 vpid_sync_vcpu_single(vmx);
1237         else
1238                 vpid_sync_vcpu_global();
1239 }
1240
1241 static inline void ept_sync_global(void)
1242 {
1243         if (cpu_has_vmx_invept_global())
1244                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1245 }
1246
1247 static inline void ept_sync_context(u64 eptp)
1248 {
1249         if (enable_ept) {
1250                 if (cpu_has_vmx_invept_context())
1251                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1252                 else
1253                         ept_sync_global();
1254         }
1255 }
1256
1257 static __always_inline unsigned long vmcs_readl(unsigned long field)
1258 {
1259         unsigned long value;
1260
1261         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1262                       : "=a"(value) : "d"(field) : "cc");
1263         return value;
1264 }
1265
1266 static __always_inline u16 vmcs_read16(unsigned long field)
1267 {
1268         return vmcs_readl(field);
1269 }
1270
1271 static __always_inline u32 vmcs_read32(unsigned long field)
1272 {
1273         return vmcs_readl(field);
1274 }
1275
1276 static __always_inline u64 vmcs_read64(unsigned long field)
1277 {
1278 #ifdef CONFIG_X86_64
1279         return vmcs_readl(field);
1280 #else
1281         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1282 #endif
1283 }
1284
1285 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1286 {
1287         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1288                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1289         dump_stack();
1290 }
1291
1292 static void vmcs_writel(unsigned long field, unsigned long value)
1293 {
1294         u8 error;
1295
1296         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1297                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1298         if (unlikely(error))
1299                 vmwrite_error(field, value);
1300 }
1301
1302 static void vmcs_write16(unsigned long field, u16 value)
1303 {
1304         vmcs_writel(field, value);
1305 }
1306
1307 static void vmcs_write32(unsigned long field, u32 value)
1308 {
1309         vmcs_writel(field, value);
1310 }
1311
1312 static void vmcs_write64(unsigned long field, u64 value)
1313 {
1314         vmcs_writel(field, value);
1315 #ifndef CONFIG_X86_64
1316         asm volatile ("");
1317         vmcs_writel(field+1, value >> 32);
1318 #endif
1319 }
1320
1321 static void vmcs_clear_bits(unsigned long field, u32 mask)
1322 {
1323         vmcs_writel(field, vmcs_readl(field) & ~mask);
1324 }
1325
1326 static void vmcs_set_bits(unsigned long field, u32 mask)
1327 {
1328         vmcs_writel(field, vmcs_readl(field) | mask);
1329 }
1330
1331 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1332 {
1333         vmx->segment_cache.bitmask = 0;
1334 }
1335
1336 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1337                                        unsigned field)
1338 {
1339         bool ret;
1340         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1341
1342         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1343                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1344                 vmx->segment_cache.bitmask = 0;
1345         }
1346         ret = vmx->segment_cache.bitmask & mask;
1347         vmx->segment_cache.bitmask |= mask;
1348         return ret;
1349 }
1350
1351 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1352 {
1353         u16 *p = &vmx->segment_cache.seg[seg].selector;
1354
1355         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1356                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1357         return *p;
1358 }
1359
1360 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1361 {
1362         ulong *p = &vmx->segment_cache.seg[seg].base;
1363
1364         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1365                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1366         return *p;
1367 }
1368
1369 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1370 {
1371         u32 *p = &vmx->segment_cache.seg[seg].limit;
1372
1373         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1374                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1375         return *p;
1376 }
1377
1378 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1379 {
1380         u32 *p = &vmx->segment_cache.seg[seg].ar;
1381
1382         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1383                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1384         return *p;
1385 }
1386
1387 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1388 {
1389         u32 eb;
1390
1391         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1392              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1393         if ((vcpu->guest_debug &
1394              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1395             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1396                 eb |= 1u << BP_VECTOR;
1397         if (to_vmx(vcpu)->rmode.vm86_active)
1398                 eb = ~0;
1399         if (enable_ept)
1400                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1401         if (vcpu->fpu_active)
1402                 eb &= ~(1u << NM_VECTOR);
1403
1404         /* When we are running a nested L2 guest and L1 specified for it a
1405          * certain exception bitmap, we must trap the same exceptions and pass
1406          * them to L1. When running L2, we will only handle the exceptions
1407          * specified above if L1 did not want them.
1408          */
1409         if (is_guest_mode(vcpu))
1410                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1411
1412         vmcs_write32(EXCEPTION_BITMAP, eb);
1413 }
1414
1415 static void clear_atomic_switch_msr_special(unsigned long entry,
1416                 unsigned long exit)
1417 {
1418         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1419         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1420 }
1421
1422 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1423 {
1424         unsigned i;
1425         struct msr_autoload *m = &vmx->msr_autoload;
1426
1427         switch (msr) {
1428         case MSR_EFER:
1429                 if (cpu_has_load_ia32_efer) {
1430                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1431                                         VM_EXIT_LOAD_IA32_EFER);
1432                         return;
1433                 }
1434                 break;
1435         case MSR_CORE_PERF_GLOBAL_CTRL:
1436                 if (cpu_has_load_perf_global_ctrl) {
1437                         clear_atomic_switch_msr_special(
1438                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1439                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1440                         return;
1441                 }
1442                 break;
1443         }
1444
1445         for (i = 0; i < m->nr; ++i)
1446                 if (m->guest[i].index == msr)
1447                         break;
1448
1449         if (i == m->nr)
1450                 return;
1451         --m->nr;
1452         m->guest[i] = m->guest[m->nr];
1453         m->host[i] = m->host[m->nr];
1454         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1455         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1456 }
1457
1458 static void add_atomic_switch_msr_special(unsigned long entry,
1459                 unsigned long exit, unsigned long guest_val_vmcs,
1460                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1461 {
1462         vmcs_write64(guest_val_vmcs, guest_val);
1463         vmcs_write64(host_val_vmcs, host_val);
1464         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1465         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1466 }
1467
1468 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1469                                   u64 guest_val, u64 host_val)
1470 {
1471         unsigned i;
1472         struct msr_autoload *m = &vmx->msr_autoload;
1473
1474         switch (msr) {
1475         case MSR_EFER:
1476                 if (cpu_has_load_ia32_efer) {
1477                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1478                                         VM_EXIT_LOAD_IA32_EFER,
1479                                         GUEST_IA32_EFER,
1480                                         HOST_IA32_EFER,
1481                                         guest_val, host_val);
1482                         return;
1483                 }
1484                 break;
1485         case MSR_CORE_PERF_GLOBAL_CTRL:
1486                 if (cpu_has_load_perf_global_ctrl) {
1487                         add_atomic_switch_msr_special(
1488                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1489                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1490                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1491                                         HOST_IA32_PERF_GLOBAL_CTRL,
1492                                         guest_val, host_val);
1493                         return;
1494                 }
1495                 break;
1496         }
1497
1498         for (i = 0; i < m->nr; ++i)
1499                 if (m->guest[i].index == msr)
1500                         break;
1501
1502         if (i == NR_AUTOLOAD_MSRS) {
1503                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1504                                 "Can't add msr %x\n", msr);
1505                 return;
1506         } else if (i == m->nr) {
1507                 ++m->nr;
1508                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1509                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1510         }
1511
1512         m->guest[i].index = msr;
1513         m->guest[i].value = guest_val;
1514         m->host[i].index = msr;
1515         m->host[i].value = host_val;
1516 }
1517
1518 static void reload_tss(void)
1519 {
1520         /*
1521          * VT restores TR but not its size.  Useless.
1522          */
1523         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1524         struct desc_struct *descs;
1525
1526         descs = (void *)gdt->address;
1527         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1528         load_TR_desc();
1529 }
1530
1531 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1532 {
1533         u64 guest_efer;
1534         u64 ignore_bits;
1535
1536         guest_efer = vmx->vcpu.arch.efer;
1537
1538         /*
1539          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1540          * outside long mode
1541          */
1542         ignore_bits = EFER_NX | EFER_SCE;
1543 #ifdef CONFIG_X86_64
1544         ignore_bits |= EFER_LMA | EFER_LME;
1545         /* SCE is meaningful only in long mode on Intel */
1546         if (guest_efer & EFER_LMA)
1547                 ignore_bits &= ~(u64)EFER_SCE;
1548 #endif
1549         guest_efer &= ~ignore_bits;
1550         guest_efer |= host_efer & ignore_bits;
1551         vmx->guest_msrs[efer_offset].data = guest_efer;
1552         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1553
1554         clear_atomic_switch_msr(vmx, MSR_EFER);
1555         /* On ept, can't emulate nx, and must switch nx atomically */
1556         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1557                 guest_efer = vmx->vcpu.arch.efer;
1558                 if (!(guest_efer & EFER_LMA))
1559                         guest_efer &= ~EFER_LME;
1560                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1561                 return false;
1562         }
1563
1564         return true;
1565 }
1566
1567 static unsigned long segment_base(u16 selector)
1568 {
1569         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1570         struct desc_struct *d;
1571         unsigned long table_base;
1572         unsigned long v;
1573
1574         if (!(selector & ~3))
1575                 return 0;
1576
1577         table_base = gdt->address;
1578
1579         if (selector & 4) {           /* from ldt */
1580                 u16 ldt_selector = kvm_read_ldt();
1581
1582                 if (!(ldt_selector & ~3))
1583                         return 0;
1584
1585                 table_base = segment_base(ldt_selector);
1586         }
1587         d = (struct desc_struct *)(table_base + (selector & ~7));
1588         v = get_desc_base(d);
1589 #ifdef CONFIG_X86_64
1590        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1591                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1592 #endif
1593         return v;
1594 }
1595
1596 static inline unsigned long kvm_read_tr_base(void)
1597 {
1598         u16 tr;
1599         asm("str %0" : "=g"(tr));
1600         return segment_base(tr);
1601 }
1602
1603 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1604 {
1605         struct vcpu_vmx *vmx = to_vmx(vcpu);
1606         int i;
1607
1608         if (vmx->host_state.loaded)
1609                 return;
1610
1611         vmx->host_state.loaded = 1;
1612         /*
1613          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1614          * allow segment selectors with cpl > 0 or ti == 1.
1615          */
1616         vmx->host_state.ldt_sel = kvm_read_ldt();
1617         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1618         savesegment(fs, vmx->host_state.fs_sel);
1619         if (!(vmx->host_state.fs_sel & 7)) {
1620                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1621                 vmx->host_state.fs_reload_needed = 0;
1622         } else {
1623                 vmcs_write16(HOST_FS_SELECTOR, 0);
1624                 vmx->host_state.fs_reload_needed = 1;
1625         }
1626         savesegment(gs, vmx->host_state.gs_sel);
1627         if (!(vmx->host_state.gs_sel & 7))
1628                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1629         else {
1630                 vmcs_write16(HOST_GS_SELECTOR, 0);
1631                 vmx->host_state.gs_ldt_reload_needed = 1;
1632         }
1633
1634 #ifdef CONFIG_X86_64
1635         savesegment(ds, vmx->host_state.ds_sel);
1636         savesegment(es, vmx->host_state.es_sel);
1637 #endif
1638
1639 #ifdef CONFIG_X86_64
1640         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1641         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1642 #else
1643         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1644         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1645 #endif
1646
1647 #ifdef CONFIG_X86_64
1648         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1649         if (is_long_mode(&vmx->vcpu))
1650                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1651 #endif
1652         for (i = 0; i < vmx->save_nmsrs; ++i)
1653                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1654                                    vmx->guest_msrs[i].data,
1655                                    vmx->guest_msrs[i].mask);
1656 }
1657
1658 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1659 {
1660         if (!vmx->host_state.loaded)
1661                 return;
1662
1663         ++vmx->vcpu.stat.host_state_reload;
1664         vmx->host_state.loaded = 0;
1665 #ifdef CONFIG_X86_64
1666         if (is_long_mode(&vmx->vcpu))
1667                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1668 #endif
1669         if (vmx->host_state.gs_ldt_reload_needed) {
1670                 kvm_load_ldt(vmx->host_state.ldt_sel);
1671 #ifdef CONFIG_X86_64
1672                 load_gs_index(vmx->host_state.gs_sel);
1673 #else
1674                 loadsegment(gs, vmx->host_state.gs_sel);
1675 #endif
1676         }
1677         if (vmx->host_state.fs_reload_needed)
1678                 loadsegment(fs, vmx->host_state.fs_sel);
1679 #ifdef CONFIG_X86_64
1680         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1681                 loadsegment(ds, vmx->host_state.ds_sel);
1682                 loadsegment(es, vmx->host_state.es_sel);
1683         }
1684 #endif
1685         reload_tss();
1686 #ifdef CONFIG_X86_64
1687         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1688 #endif
1689         /*
1690          * If the FPU is not active (through the host task or
1691          * the guest vcpu), then restore the cr0.TS bit.
1692          */
1693         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1694                 stts();
1695         load_gdt(&__get_cpu_var(host_gdt));
1696 }
1697
1698 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1699 {
1700         preempt_disable();
1701         __vmx_load_host_state(vmx);
1702         preempt_enable();
1703 }
1704
1705 /*
1706  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1707  * vcpu mutex is already taken.
1708  */
1709 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1710 {
1711         struct vcpu_vmx *vmx = to_vmx(vcpu);
1712         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1713
1714         if (!vmm_exclusive)
1715                 kvm_cpu_vmxon(phys_addr);
1716         else if (vmx->loaded_vmcs->cpu != cpu)
1717                 loaded_vmcs_clear(vmx->loaded_vmcs);
1718
1719         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1720                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1721                 vmcs_load(vmx->loaded_vmcs->vmcs);
1722         }
1723
1724         if (vmx->loaded_vmcs->cpu != cpu) {
1725                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1726                 unsigned long sysenter_esp;
1727
1728                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1729                 local_irq_disable();
1730                 crash_disable_local_vmclear(cpu);
1731
1732                 /*
1733                  * Read loaded_vmcs->cpu should be before fetching
1734                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1735                  * See the comments in __loaded_vmcs_clear().
1736                  */
1737                 smp_rmb();
1738
1739                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1740                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1741                 crash_enable_local_vmclear(cpu);
1742                 local_irq_enable();
1743
1744                 /*
1745                  * Linux uses per-cpu TSS and GDT, so set these when switching
1746                  * processors.
1747                  */
1748                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1749                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1750
1751                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1752                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1753                 vmx->loaded_vmcs->cpu = cpu;
1754         }
1755 }
1756
1757 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1758 {
1759         __vmx_load_host_state(to_vmx(vcpu));
1760         if (!vmm_exclusive) {
1761                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1762                 vcpu->cpu = -1;
1763                 kvm_cpu_vmxoff();
1764         }
1765 }
1766
1767 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1768 {
1769         ulong cr0;
1770
1771         if (vcpu->fpu_active)
1772                 return;
1773         vcpu->fpu_active = 1;
1774         cr0 = vmcs_readl(GUEST_CR0);
1775         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1776         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1777         vmcs_writel(GUEST_CR0, cr0);
1778         update_exception_bitmap(vcpu);
1779         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1780         if (is_guest_mode(vcpu))
1781                 vcpu->arch.cr0_guest_owned_bits &=
1782                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1783         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1784 }
1785
1786 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1787
1788 /*
1789  * Return the cr0 value that a nested guest would read. This is a combination
1790  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1791  * its hypervisor (cr0_read_shadow).
1792  */
1793 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1794 {
1795         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1796                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1797 }
1798 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1799 {
1800         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1801                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1802 }
1803
1804 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1805 {
1806         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1807          * set this *before* calling this function.
1808          */
1809         vmx_decache_cr0_guest_bits(vcpu);
1810         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1811         update_exception_bitmap(vcpu);
1812         vcpu->arch.cr0_guest_owned_bits = 0;
1813         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1814         if (is_guest_mode(vcpu)) {
1815                 /*
1816                  * L1's specified read shadow might not contain the TS bit,
1817                  * so now that we turned on shadowing of this bit, we need to
1818                  * set this bit of the shadow. Like in nested_vmx_run we need
1819                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1820                  * up-to-date here because we just decached cr0.TS (and we'll
1821                  * only update vmcs12->guest_cr0 on nested exit).
1822                  */
1823                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1824                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1825                         (vcpu->arch.cr0 & X86_CR0_TS);
1826                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1827         } else
1828                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1829 }
1830
1831 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1832 {
1833         unsigned long rflags, save_rflags;
1834
1835         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1836                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1837                 rflags = vmcs_readl(GUEST_RFLAGS);
1838                 if (to_vmx(vcpu)->rmode.vm86_active) {
1839                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1840                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1841                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1842                 }
1843                 to_vmx(vcpu)->rflags = rflags;
1844         }
1845         return to_vmx(vcpu)->rflags;
1846 }
1847
1848 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1849 {
1850         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1851         to_vmx(vcpu)->rflags = rflags;
1852         if (to_vmx(vcpu)->rmode.vm86_active) {
1853                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1854                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1855         }
1856         vmcs_writel(GUEST_RFLAGS, rflags);
1857 }
1858
1859 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1860 {
1861         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1862         int ret = 0;
1863
1864         if (interruptibility & GUEST_INTR_STATE_STI)
1865                 ret |= KVM_X86_SHADOW_INT_STI;
1866         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1867                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1868
1869         return ret & mask;
1870 }
1871
1872 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1873 {
1874         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1875         u32 interruptibility = interruptibility_old;
1876
1877         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1878
1879         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1880                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1881         else if (mask & KVM_X86_SHADOW_INT_STI)
1882                 interruptibility |= GUEST_INTR_STATE_STI;
1883
1884         if ((interruptibility != interruptibility_old))
1885                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1886 }
1887
1888 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1889 {
1890         unsigned long rip;
1891
1892         rip = kvm_rip_read(vcpu);
1893         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1894         kvm_rip_write(vcpu, rip);
1895
1896         /* skipping an emulated instruction also counts */
1897         vmx_set_interrupt_shadow(vcpu, 0);
1898 }
1899
1900 /*
1901  * KVM wants to inject page-faults which it got to the guest. This function
1902  * checks whether in a nested guest, we need to inject them to L1 or L2.
1903  * This function assumes it is called with the exit reason in vmcs02 being
1904  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1905  * is running).
1906  */
1907 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1908 {
1909         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1910
1911         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1912         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1913                 return 0;
1914
1915         nested_vmx_vmexit(vcpu);
1916         return 1;
1917 }
1918
1919 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1920                                 bool has_error_code, u32 error_code,
1921                                 bool reinject)
1922 {
1923         struct vcpu_vmx *vmx = to_vmx(vcpu);
1924         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1925
1926         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1927             !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1928                 return;
1929
1930         if (has_error_code) {
1931                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1932                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1933         }
1934
1935         if (vmx->rmode.vm86_active) {
1936                 int inc_eip = 0;
1937                 if (kvm_exception_is_soft(nr))
1938                         inc_eip = vcpu->arch.event_exit_inst_len;
1939                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1940                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1941                 return;
1942         }
1943
1944         if (kvm_exception_is_soft(nr)) {
1945                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1946                              vmx->vcpu.arch.event_exit_inst_len);
1947                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1948         } else
1949                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1950
1951         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1952 }
1953
1954 static bool vmx_rdtscp_supported(void)
1955 {
1956         return cpu_has_vmx_rdtscp();
1957 }
1958
1959 static bool vmx_invpcid_supported(void)
1960 {
1961         return cpu_has_vmx_invpcid() && enable_ept;
1962 }
1963
1964 /*
1965  * Swap MSR entry in host/guest MSR entry array.
1966  */
1967 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1968 {
1969         struct shared_msr_entry tmp;
1970
1971         tmp = vmx->guest_msrs[to];
1972         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1973         vmx->guest_msrs[from] = tmp;
1974 }
1975
1976 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1977 {
1978         unsigned long *msr_bitmap;
1979
1980         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1981                 if (is_long_mode(vcpu))
1982                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1983                 else
1984                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1985         } else {
1986                 if (is_long_mode(vcpu))
1987                         msr_bitmap = vmx_msr_bitmap_longmode;
1988                 else
1989                         msr_bitmap = vmx_msr_bitmap_legacy;
1990         }
1991
1992         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1993 }
1994
1995 /*
1996  * Set up the vmcs to automatically save and restore system
1997  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1998  * mode, as fiddling with msrs is very expensive.
1999  */
2000 static void setup_msrs(struct vcpu_vmx *vmx)
2001 {
2002         int save_nmsrs, index;
2003
2004         save_nmsrs = 0;
2005 #ifdef CONFIG_X86_64
2006         if (is_long_mode(&vmx->vcpu)) {
2007                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2008                 if (index >= 0)
2009                         move_msr_up(vmx, index, save_nmsrs++);
2010                 index = __find_msr_index(vmx, MSR_LSTAR);
2011                 if (index >= 0)
2012                         move_msr_up(vmx, index, save_nmsrs++);
2013                 index = __find_msr_index(vmx, MSR_CSTAR);
2014                 if (index >= 0)
2015                         move_msr_up(vmx, index, save_nmsrs++);
2016                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2017                 if (index >= 0 && vmx->rdtscp_enabled)
2018                         move_msr_up(vmx, index, save_nmsrs++);
2019                 /*
2020                  * MSR_STAR is only needed on long mode guests, and only
2021                  * if efer.sce is enabled.
2022                  */
2023                 index = __find_msr_index(vmx, MSR_STAR);
2024                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2025                         move_msr_up(vmx, index, save_nmsrs++);
2026         }
2027 #endif
2028         index = __find_msr_index(vmx, MSR_EFER);
2029         if (index >= 0 && update_transition_efer(vmx, index))
2030                 move_msr_up(vmx, index, save_nmsrs++);
2031
2032         vmx->save_nmsrs = save_nmsrs;
2033
2034         if (cpu_has_vmx_msr_bitmap())
2035                 vmx_set_msr_bitmap(&vmx->vcpu);
2036 }
2037
2038 /*
2039  * reads and returns guest's timestamp counter "register"
2040  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2041  */
2042 static u64 guest_read_tsc(void)
2043 {
2044         u64 host_tsc, tsc_offset;
2045
2046         rdtscll(host_tsc);
2047         tsc_offset = vmcs_read64(TSC_OFFSET);
2048         return host_tsc + tsc_offset;
2049 }
2050
2051 /*
2052  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2053  * counter, even if a nested guest (L2) is currently running.
2054  */
2055 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2056 {
2057         u64 tsc_offset;
2058
2059         tsc_offset = is_guest_mode(vcpu) ?
2060                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2061                 vmcs_read64(TSC_OFFSET);
2062         return host_tsc + tsc_offset;
2063 }
2064
2065 /*
2066  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2067  * software catchup for faster rates on slower CPUs.
2068  */
2069 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2070 {
2071         if (!scale)
2072                 return;
2073
2074         if (user_tsc_khz > tsc_khz) {
2075                 vcpu->arch.tsc_catchup = 1;
2076                 vcpu->arch.tsc_always_catchup = 1;
2077         } else
2078                 WARN(1, "user requested TSC rate below hardware speed\n");
2079 }
2080
2081 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2082 {
2083         return vmcs_read64(TSC_OFFSET);
2084 }
2085
2086 /*
2087  * writes 'offset' into guest's timestamp counter offset register
2088  */
2089 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2090 {
2091         if (is_guest_mode(vcpu)) {
2092                 /*
2093                  * We're here if L1 chose not to trap WRMSR to TSC. According
2094                  * to the spec, this should set L1's TSC; The offset that L1
2095                  * set for L2 remains unchanged, and still needs to be added
2096                  * to the newly set TSC to get L2's TSC.
2097                  */
2098                 struct vmcs12 *vmcs12;
2099                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2100                 /* recalculate vmcs02.TSC_OFFSET: */
2101                 vmcs12 = get_vmcs12(vcpu);
2102                 vmcs_write64(TSC_OFFSET, offset +
2103                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2104                          vmcs12->tsc_offset : 0));
2105         } else {
2106                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2107                                            vmcs_read64(TSC_OFFSET), offset);
2108                 vmcs_write64(TSC_OFFSET, offset);
2109         }
2110 }
2111
2112 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2113 {
2114         u64 offset = vmcs_read64(TSC_OFFSET);
2115
2116         vmcs_write64(TSC_OFFSET, offset + adjustment);
2117         if (is_guest_mode(vcpu)) {
2118                 /* Even when running L2, the adjustment needs to apply to L1 */
2119                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2120         } else
2121                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2122                                            offset + adjustment);
2123 }
2124
2125 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2126 {
2127         return target_tsc - native_read_tsc();
2128 }
2129
2130 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2131 {
2132         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2133         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2134 }
2135
2136 /*
2137  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2138  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2139  * all guests if the "nested" module option is off, and can also be disabled
2140  * for a single guest by disabling its VMX cpuid bit.
2141  */
2142 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2143 {
2144         return nested && guest_cpuid_has_vmx(vcpu);
2145 }
2146
2147 /*
2148  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2149  * returned for the various VMX controls MSRs when nested VMX is enabled.
2150  * The same values should also be used to verify that vmcs12 control fields are
2151  * valid during nested entry from L1 to L2.
2152  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2153  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2154  * bit in the high half is on if the corresponding bit in the control field
2155  * may be on. See also vmx_control_verify().
2156  * TODO: allow these variables to be modified (downgraded) by module options
2157  * or other means.
2158  */
2159 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2160 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2161 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2162 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2163 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2164 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2165 static u32 nested_vmx_ept_caps;
2166 static __init void nested_vmx_setup_ctls_msrs(void)
2167 {
2168         /*
2169          * Note that as a general rule, the high half of the MSRs (bits in
2170          * the control fields which may be 1) should be initialized by the
2171          * intersection of the underlying hardware's MSR (i.e., features which
2172          * can be supported) and the list of features we want to expose -
2173          * because they are known to be properly supported in our code.
2174          * Also, usually, the low half of the MSRs (bits which must be 1) can
2175          * be set to 0, meaning that L1 may turn off any of these bits. The
2176          * reason is that if one of these bits is necessary, it will appear
2177          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2178          * fields of vmcs01 and vmcs02, will turn these bits off - and
2179          * nested_vmx_exit_handled() will not pass related exits to L1.
2180          * These rules have exceptions below.
2181          */
2182
2183         /* pin-based controls */
2184         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2185               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2186         /*
2187          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2188          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2189          */
2190         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2191         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2192                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2193                 PIN_BASED_VMX_PREEMPTION_TIMER;
2194         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2195
2196         /*
2197          * Exit controls
2198          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2199          * 17 must be 1.
2200          */
2201         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2202         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2203 #ifdef CONFIG_X86_64
2204         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2205 #else
2206         nested_vmx_exit_ctls_high = 0;
2207 #endif
2208         nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2209                                       VM_EXIT_LOAD_IA32_EFER);
2210
2211         /* entry controls */
2212         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2213                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2214         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2215         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2216         nested_vmx_entry_ctls_high &=
2217                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2218         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2219                                        VM_ENTRY_LOAD_IA32_EFER);
2220         /* cpu-based controls */
2221         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2222                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2223         nested_vmx_procbased_ctls_low = 0;
2224         nested_vmx_procbased_ctls_high &=
2225                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2226                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2227                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2228                 CPU_BASED_CR3_STORE_EXITING |
2229 #ifdef CONFIG_X86_64
2230                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2231 #endif
2232                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2233                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2234                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2235                 CPU_BASED_PAUSE_EXITING |
2236                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2237         /*
2238          * We can allow some features even when not supported by the
2239          * hardware. For example, L1 can specify an MSR bitmap - and we
2240          * can use it to avoid exits to L1 - even when L0 runs L2
2241          * without MSR bitmaps.
2242          */
2243         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2244
2245         /* secondary cpu-based controls */
2246         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2247                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2248         nested_vmx_secondary_ctls_low = 0;
2249         nested_vmx_secondary_ctls_high &=
2250                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2251                 SECONDARY_EXEC_WBINVD_EXITING;
2252
2253         /* miscellaneous data */
2254         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2255         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2256                 VMX_MISC_SAVE_EFER_LMA;
2257         nested_vmx_misc_high = 0;
2258 }
2259
2260 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2261 {
2262         /*
2263          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2264          */
2265         return ((control & high) | low) == control;
2266 }
2267
2268 static inline u64 vmx_control_msr(u32 low, u32 high)
2269 {
2270         return low | ((u64)high << 32);
2271 }
2272
2273 /*
2274  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2275  * also let it use VMX-specific MSRs.
2276  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2277  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2278  * like all other MSRs).
2279  */
2280 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2281 {
2282         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2283                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2284                 /*
2285                  * According to the spec, processors which do not support VMX
2286                  * should throw a #GP(0) when VMX capability MSRs are read.
2287                  */
2288                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2289                 return 1;
2290         }
2291
2292         switch (msr_index) {
2293         case MSR_IA32_FEATURE_CONTROL:
2294                 if (nested_vmx_allowed(vcpu)) {
2295                         *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2296                         break;
2297                 }
2298                 return 0;
2299         case MSR_IA32_VMX_BASIC:
2300                 /*
2301                  * This MSR reports some information about VMX support. We
2302                  * should return information about the VMX we emulate for the
2303                  * guest, and the VMCS structure we give it - not about the
2304                  * VMX support of the underlying hardware.
2305                  */
2306                 *pdata = VMCS12_REVISION |
2307                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2308                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2309                 break;
2310         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2311         case MSR_IA32_VMX_PINBASED_CTLS:
2312                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2313                                         nested_vmx_pinbased_ctls_high);
2314                 break;
2315         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2316         case MSR_IA32_VMX_PROCBASED_CTLS:
2317                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2318                                         nested_vmx_procbased_ctls_high);
2319                 break;
2320         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2321         case MSR_IA32_VMX_EXIT_CTLS:
2322                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2323                                         nested_vmx_exit_ctls_high);
2324                 break;
2325         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2326         case MSR_IA32_VMX_ENTRY_CTLS:
2327                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2328                                         nested_vmx_entry_ctls_high);
2329                 break;
2330         case MSR_IA32_VMX_MISC:
2331                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2332                                          nested_vmx_misc_high);
2333                 break;
2334         /*
2335          * These MSRs specify bits which the guest must keep fixed (on or off)
2336          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2337          * We picked the standard core2 setting.
2338          */
2339 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2340 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2341         case MSR_IA32_VMX_CR0_FIXED0:
2342                 *pdata = VMXON_CR0_ALWAYSON;
2343                 break;
2344         case MSR_IA32_VMX_CR0_FIXED1:
2345                 *pdata = -1ULL;
2346                 break;
2347         case MSR_IA32_VMX_CR4_FIXED0:
2348                 *pdata = VMXON_CR4_ALWAYSON;
2349                 break;
2350         case MSR_IA32_VMX_CR4_FIXED1:
2351                 *pdata = -1ULL;
2352                 break;
2353         case MSR_IA32_VMX_VMCS_ENUM:
2354                 *pdata = 0x1f;
2355                 break;
2356         case MSR_IA32_VMX_PROCBASED_CTLS2:
2357                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2358                                         nested_vmx_secondary_ctls_high);
2359                 break;
2360         case MSR_IA32_VMX_EPT_VPID_CAP:
2361                 /* Currently, no nested ept or nested vpid */
2362                 *pdata = 0;
2363                 break;
2364         default:
2365                 return 0;
2366         }
2367
2368         return 1;
2369 }
2370
2371 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2372 {
2373         u32 msr_index = msr_info->index;
2374         u64 data = msr_info->data;
2375         bool host_initialized = msr_info->host_initiated;
2376
2377         if (!nested_vmx_allowed(vcpu))
2378                 return 0;
2379
2380         if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2381                 if (!host_initialized &&
2382                                 to_vmx(vcpu)->nested.msr_ia32_feature_control
2383                                 & FEATURE_CONTROL_LOCKED)
2384                         return 0;
2385                 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
2386                 return 1;
2387         }
2388
2389         /*
2390          * No need to treat VMX capability MSRs specially: If we don't handle
2391          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2392          */
2393         return 0;
2394 }
2395
2396 /*
2397  * Reads an msr value (of 'msr_index') into 'pdata'.
2398  * Returns 0 on success, non-0 otherwise.
2399  * Assumes vcpu_load() was already called.
2400  */
2401 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2402 {
2403         u64 data;
2404         struct shared_msr_entry *msr;
2405
2406         if (!pdata) {
2407                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2408                 return -EINVAL;
2409         }
2410
2411         switch (msr_index) {
2412 #ifdef CONFIG_X86_64
2413         case MSR_FS_BASE:
2414                 data = vmcs_readl(GUEST_FS_BASE);
2415                 break;
2416         case MSR_GS_BASE:
2417                 data = vmcs_readl(GUEST_GS_BASE);
2418                 break;
2419         case MSR_KERNEL_GS_BASE:
2420                 vmx_load_host_state(to_vmx(vcpu));
2421                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2422                 break;
2423 #endif
2424         case MSR_EFER:
2425                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2426         case MSR_IA32_TSC:
2427                 data = guest_read_tsc();
2428                 break;
2429         case MSR_IA32_SYSENTER_CS:
2430                 data = vmcs_read32(GUEST_SYSENTER_CS);
2431                 break;
2432         case MSR_IA32_SYSENTER_EIP:
2433                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2434                 break;
2435         case MSR_IA32_SYSENTER_ESP:
2436                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2437                 break;
2438         case MSR_TSC_AUX:
2439                 if (!to_vmx(vcpu)->rdtscp_enabled)
2440                         return 1;
2441                 /* Otherwise falls through */
2442         default:
2443                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2444                         return 0;
2445                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2446                 if (msr) {
2447                         data = msr->data;
2448                         break;
2449                 }
2450                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2451         }
2452
2453         *pdata = data;
2454         return 0;
2455 }
2456
2457 /*
2458  * Writes msr value into into the appropriate "register".
2459  * Returns 0 on success, non-0 otherwise.
2460  * Assumes vcpu_load() was already called.
2461  */
2462 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2463 {
2464         struct vcpu_vmx *vmx = to_vmx(vcpu);
2465         struct shared_msr_entry *msr;
2466         int ret = 0;
2467         u32 msr_index = msr_info->index;
2468         u64 data = msr_info->data;
2469
2470         switch (msr_index) {
2471         case MSR_EFER:
2472                 ret = kvm_set_msr_common(vcpu, msr_info);
2473                 break;
2474 #ifdef CONFIG_X86_64
2475         case MSR_FS_BASE:
2476                 vmx_segment_cache_clear(vmx);
2477                 vmcs_writel(GUEST_FS_BASE, data);
2478                 break;
2479         case MSR_GS_BASE:
2480                 vmx_segment_cache_clear(vmx);
2481                 vmcs_writel(GUEST_GS_BASE, data);
2482                 break;
2483         case MSR_KERNEL_GS_BASE:
2484                 vmx_load_host_state(vmx);
2485                 vmx->msr_guest_kernel_gs_base = data;
2486                 break;
2487 #endif
2488         case MSR_IA32_SYSENTER_CS:
2489                 vmcs_write32(GUEST_SYSENTER_CS, data);
2490                 break;
2491         case MSR_IA32_SYSENTER_EIP:
2492                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2493                 break;
2494         case MSR_IA32_SYSENTER_ESP:
2495                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2496                 break;
2497         case MSR_IA32_TSC:
2498                 kvm_write_tsc(vcpu, msr_info);
2499                 break;
2500         case MSR_IA32_CR_PAT:
2501                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2502                         vmcs_write64(GUEST_IA32_PAT, data);
2503                         vcpu->arch.pat = data;
2504                         break;
2505                 }
2506                 ret = kvm_set_msr_common(vcpu, msr_info);
2507                 break;
2508         case MSR_IA32_TSC_ADJUST:
2509                 ret = kvm_set_msr_common(vcpu, msr_info);
2510                 break;
2511         case MSR_TSC_AUX:
2512                 if (!vmx->rdtscp_enabled)
2513                         return 1;
2514                 /* Check reserved bit, higher 32 bits should be zero */
2515                 if ((data >> 32) != 0)
2516                         return 1;
2517                 /* Otherwise falls through */
2518         default:
2519                 if (vmx_set_vmx_msr(vcpu, msr_info))
2520                         break;
2521                 msr = find_msr_entry(vmx, msr_index);
2522                 if (msr) {
2523                         msr->data = data;
2524                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2525                                 preempt_disable();
2526                                 kvm_set_shared_msr(msr->index, msr->data,
2527                                                    msr->mask);
2528                                 preempt_enable();
2529                         }
2530                         break;
2531                 }
2532                 ret = kvm_set_msr_common(vcpu, msr_info);
2533         }
2534
2535         return ret;
2536 }
2537
2538 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2539 {
2540         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2541         switch (reg) {
2542         case VCPU_REGS_RSP:
2543                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2544                 break;
2545         case VCPU_REGS_RIP:
2546                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2547                 break;
2548         case VCPU_EXREG_PDPTR:
2549                 if (enable_ept)
2550                         ept_save_pdptrs(vcpu);
2551                 break;
2552         default:
2553                 break;
2554         }
2555 }
2556
2557 static __init int cpu_has_kvm_support(void)
2558 {
2559         return cpu_has_vmx();
2560 }
2561
2562 static __init int vmx_disabled_by_bios(void)
2563 {
2564         u64 msr;
2565
2566         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2567         if (msr & FEATURE_CONTROL_LOCKED) {
2568                 /* launched w/ TXT and VMX disabled */
2569                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2570                         && tboot_enabled())
2571                         return 1;
2572                 /* launched w/o TXT and VMX only enabled w/ TXT */
2573                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2574                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2575                         && !tboot_enabled()) {
2576                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2577                                 "activate TXT before enabling KVM\n");
2578                         return 1;
2579                 }
2580                 /* launched w/o TXT and VMX disabled */
2581                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2582                         && !tboot_enabled())
2583                         return 1;
2584         }
2585
2586         return 0;
2587 }
2588
2589 static void kvm_cpu_vmxon(u64 addr)
2590 {
2591         asm volatile (ASM_VMX_VMXON_RAX
2592                         : : "a"(&addr), "m"(addr)
2593                         : "memory", "cc");
2594 }
2595
2596 static int hardware_enable(void *garbage)
2597 {
2598         int cpu = raw_smp_processor_id();
2599         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2600         u64 old, test_bits;
2601
2602         if (read_cr4() & X86_CR4_VMXE)
2603                 return -EBUSY;
2604
2605         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2606
2607         /*
2608          * Now we can enable the vmclear operation in kdump
2609          * since the loaded_vmcss_on_cpu list on this cpu
2610          * has been initialized.
2611          *
2612          * Though the cpu is not in VMX operation now, there
2613          * is no problem to enable the vmclear operation
2614          * for the loaded_vmcss_on_cpu list is empty!
2615          */
2616         crash_enable_local_vmclear(cpu);
2617
2618         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2619
2620         test_bits = FEATURE_CONTROL_LOCKED;
2621         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2622         if (tboot_enabled())
2623                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2624
2625         if ((old & test_bits) != test_bits) {
2626                 /* enable and lock */
2627                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2628         }
2629         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2630
2631         if (vmm_exclusive) {
2632                 kvm_cpu_vmxon(phys_addr);
2633                 ept_sync_global();
2634         }
2635
2636         native_store_gdt(&__get_cpu_var(host_gdt));
2637
2638         return 0;
2639 }
2640
2641 static void vmclear_local_loaded_vmcss(void)
2642 {
2643         int cpu = raw_smp_processor_id();
2644         struct loaded_vmcs *v, *n;
2645
2646         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2647                                  loaded_vmcss_on_cpu_link)
2648                 __loaded_vmcs_clear(v);
2649 }
2650
2651
2652 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2653  * tricks.
2654  */
2655 static void kvm_cpu_vmxoff(void)
2656 {
2657         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2658 }
2659
2660 static void hardware_disable(void *garbage)
2661 {
2662         if (vmm_exclusive) {
2663                 vmclear_local_loaded_vmcss();
2664                 kvm_cpu_vmxoff();
2665         }
2666         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2667 }
2668
2669 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2670                                       u32 msr, u32 *result)
2671 {
2672         u32 vmx_msr_low, vmx_msr_high;
2673         u32 ctl = ctl_min | ctl_opt;
2674
2675         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2676
2677         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2678         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2679
2680         /* Ensure minimum (required) set of control bits are supported. */
2681         if (ctl_min & ~ctl)
2682                 return -EIO;
2683
2684         *result = ctl;
2685         return 0;
2686 }
2687
2688 static __init bool allow_1_setting(u32 msr, u32 ctl)
2689 {
2690         u32 vmx_msr_low, vmx_msr_high;
2691
2692         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2693         return vmx_msr_high & ctl;
2694 }
2695
2696 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2697 {
2698         u32 vmx_msr_low, vmx_msr_high;
2699         u32 min, opt, min2, opt2;
2700         u32 _pin_based_exec_control = 0;
2701         u32 _cpu_based_exec_control = 0;
2702         u32 _cpu_based_2nd_exec_control = 0;
2703         u32 _vmexit_control = 0;
2704         u32 _vmentry_control = 0;
2705
2706         min = CPU_BASED_HLT_EXITING |
2707 #ifdef CONFIG_X86_64
2708               CPU_BASED_CR8_LOAD_EXITING |
2709               CPU_BASED_CR8_STORE_EXITING |
2710 #endif
2711               CPU_BASED_CR3_LOAD_EXITING |
2712               CPU_BASED_CR3_STORE_EXITING |
2713               CPU_BASED_USE_IO_BITMAPS |
2714               CPU_BASED_MOV_DR_EXITING |
2715               CPU_BASED_USE_TSC_OFFSETING |
2716               CPU_BASED_MWAIT_EXITING |
2717               CPU_BASED_MONITOR_EXITING |
2718               CPU_BASED_INVLPG_EXITING |
2719               CPU_BASED_RDPMC_EXITING;
2720
2721         opt = CPU_BASED_TPR_SHADOW |
2722               CPU_BASED_USE_MSR_BITMAPS |
2723               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2724         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2725                                 &_cpu_based_exec_control) < 0)
2726                 return -EIO;
2727 #ifdef CONFIG_X86_64
2728         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2729                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2730                                            ~CPU_BASED_CR8_STORE_EXITING;
2731 #endif
2732         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2733                 min2 = 0;
2734                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2735                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2736                         SECONDARY_EXEC_WBINVD_EXITING |
2737                         SECONDARY_EXEC_ENABLE_VPID |
2738                         SECONDARY_EXEC_ENABLE_EPT |
2739                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2740                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2741                         SECONDARY_EXEC_RDTSCP |
2742                         SECONDARY_EXEC_ENABLE_INVPCID |
2743                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2744                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2745                         SECONDARY_EXEC_SHADOW_VMCS;
2746                 if (adjust_vmx_controls(min2, opt2,
2747                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2748                                         &_cpu_based_2nd_exec_control) < 0)
2749                         return -EIO;
2750         }
2751 #ifndef CONFIG_X86_64
2752         if (!(_cpu_based_2nd_exec_control &
2753                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2754                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2755 #endif
2756
2757         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2758                 _cpu_based_2nd_exec_control &= ~(
2759                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2760                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2761                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2762
2763         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2764                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2765                    enabled */
2766                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2767                                              CPU_BASED_CR3_STORE_EXITING |
2768                                              CPU_BASED_INVLPG_EXITING);
2769                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2770                       vmx_capability.ept, vmx_capability.vpid);
2771         }
2772
2773         min = 0;
2774 #ifdef CONFIG_X86_64
2775         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2776 #endif
2777         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2778                 VM_EXIT_ACK_INTR_ON_EXIT;
2779         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2780                                 &_vmexit_control) < 0)
2781                 return -EIO;
2782
2783         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2784         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2785         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2786                                 &_pin_based_exec_control) < 0)
2787                 return -EIO;
2788
2789         if (!(_cpu_based_2nd_exec_control &
2790                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2791                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2792                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2793
2794         min = 0;
2795         opt = VM_ENTRY_LOAD_IA32_PAT;
2796         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2797                                 &_vmentry_control) < 0)
2798                 return -EIO;
2799
2800         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2801
2802         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2803         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2804                 return -EIO;
2805
2806 #ifdef CONFIG_X86_64
2807         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2808         if (vmx_msr_high & (1u<<16))
2809                 return -EIO;
2810 #endif
2811
2812         /* Require Write-Back (WB) memory type for VMCS accesses. */
2813         if (((vmx_msr_high >> 18) & 15) != 6)
2814                 return -EIO;
2815
2816         vmcs_conf->size = vmx_msr_high & 0x1fff;
2817         vmcs_conf->order = get_order(vmcs_config.size);
2818         vmcs_conf->revision_id = vmx_msr_low;
2819
2820         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2821         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2822         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2823         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2824         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2825
2826         cpu_has_load_ia32_efer =
2827                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2828                                 VM_ENTRY_LOAD_IA32_EFER)
2829                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2830                                    VM_EXIT_LOAD_IA32_EFER);
2831
2832         cpu_has_load_perf_global_ctrl =
2833                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2834                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2835                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2836                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2837
2838         /*
2839          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2840          * but due to arrata below it can't be used. Workaround is to use
2841          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2842          *
2843          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2844          *
2845          * AAK155             (model 26)
2846          * AAP115             (model 30)
2847          * AAT100             (model 37)
2848          * BC86,AAY89,BD102   (model 44)
2849          * BA97               (model 46)
2850          *
2851          */
2852         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2853                 switch (boot_cpu_data.x86_model) {
2854                 case 26:
2855                 case 30:
2856                 case 37:
2857                 case 44:
2858                 case 46:
2859                         cpu_has_load_perf_global_ctrl = false;
2860                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2861                                         "does not work properly. Using workaround\n");
2862                         break;
2863                 default:
2864                         break;
2865                 }
2866         }
2867
2868         return 0;
2869 }
2870
2871 static struct vmcs *alloc_vmcs_cpu(int cpu)
2872 {
2873         int node = cpu_to_node(cpu);
2874         struct page *pages;
2875         struct vmcs *vmcs;
2876
2877         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2878         if (!pages)
2879                 return NULL;
2880         vmcs = page_address(pages);
2881         memset(vmcs, 0, vmcs_config.size);
2882         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2883         return vmcs;
2884 }
2885
2886 static struct vmcs *alloc_vmcs(void)
2887 {
2888         return alloc_vmcs_cpu(raw_smp_processor_id());
2889 }
2890
2891 static void free_vmcs(struct vmcs *vmcs)
2892 {
2893         free_pages((unsigned long)vmcs, vmcs_config.order);
2894 }
2895
2896 /*
2897  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2898  */
2899 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2900 {
2901         if (!loaded_vmcs->vmcs)
2902                 return;
2903         loaded_vmcs_clear(loaded_vmcs);
2904         free_vmcs(loaded_vmcs->vmcs);
2905         loaded_vmcs->vmcs = NULL;
2906 }
2907
2908 static void free_kvm_area(void)
2909 {
2910         int cpu;
2911
2912         for_each_possible_cpu(cpu) {
2913                 free_vmcs(per_cpu(vmxarea, cpu));
2914                 per_cpu(vmxarea, cpu) = NULL;
2915         }
2916 }
2917
2918 static __init int alloc_kvm_area(void)
2919 {
2920         int cpu;
2921
2922         for_each_possible_cpu(cpu) {
2923                 struct vmcs *vmcs;
2924
2925                 vmcs = alloc_vmcs_cpu(cpu);
2926                 if (!vmcs) {
2927                         free_kvm_area();
2928                         return -ENOMEM;
2929                 }
2930
2931                 per_cpu(vmxarea, cpu) = vmcs;
2932         }
2933         return 0;
2934 }
2935
2936 static __init int hardware_setup(void)
2937 {
2938         if (setup_vmcs_config(&vmcs_config) < 0)
2939                 return -EIO;
2940
2941         if (boot_cpu_has(X86_FEATURE_NX))
2942                 kvm_enable_efer_bits(EFER_NX);
2943
2944         if (!cpu_has_vmx_vpid())
2945                 enable_vpid = 0;
2946         if (!cpu_has_vmx_shadow_vmcs())
2947                 enable_shadow_vmcs = 0;
2948
2949         if (!cpu_has_vmx_ept() ||
2950             !cpu_has_vmx_ept_4levels()) {
2951                 enable_ept = 0;
2952                 enable_unrestricted_guest = 0;
2953                 enable_ept_ad_bits = 0;
2954         }
2955
2956         if (!cpu_has_vmx_ept_ad_bits())
2957                 enable_ept_ad_bits = 0;
2958
2959         if (!cpu_has_vmx_unrestricted_guest())
2960                 enable_unrestricted_guest = 0;
2961
2962         if (!cpu_has_vmx_flexpriority())
2963                 flexpriority_enabled = 0;
2964
2965         if (!cpu_has_vmx_tpr_shadow())
2966                 kvm_x86_ops->update_cr8_intercept = NULL;
2967
2968         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2969                 kvm_disable_largepages();
2970
2971         if (!cpu_has_vmx_ple())
2972                 ple_gap = 0;
2973
2974         if (!cpu_has_vmx_apicv())
2975                 enable_apicv = 0;
2976
2977         if (enable_apicv)
2978                 kvm_x86_ops->update_cr8_intercept = NULL;
2979         else {
2980                 kvm_x86_ops->hwapic_irr_update = NULL;
2981                 kvm_x86_ops->deliver_posted_interrupt = NULL;
2982                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2983         }
2984
2985         if (nested)
2986                 nested_vmx_setup_ctls_msrs();
2987
2988         return alloc_kvm_area();
2989 }
2990
2991 static __exit void hardware_unsetup(void)
2992 {
2993         free_kvm_area();
2994 }
2995
2996 static bool emulation_required(struct kvm_vcpu *vcpu)
2997 {
2998         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2999 }
3000
3001 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3002                 struct kvm_segment *save)
3003 {
3004         if (!emulate_invalid_guest_state) {
3005                 /*
3006                  * CS and SS RPL should be equal during guest entry according
3007                  * to VMX spec, but in reality it is not always so. Since vcpu
3008                  * is in the middle of the transition from real mode to
3009                  * protected mode it is safe to assume that RPL 0 is a good
3010                  * default value.
3011                  */
3012                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3013                         save->selector &= ~SELECTOR_RPL_MASK;
3014                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3015                 save->s = 1;
3016         }
3017         vmx_set_segment(vcpu, save, seg);
3018 }
3019
3020 static void enter_pmode(struct kvm_vcpu *vcpu)
3021 {
3022         unsigned long flags;
3023         struct vcpu_vmx *vmx = to_vmx(vcpu);
3024
3025         /*
3026          * Update real mode segment cache. It may be not up-to-date if sement
3027          * register was written while vcpu was in a guest mode.
3028          */
3029         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3030         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3031         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3032         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3033         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3034         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3035
3036         vmx->rmode.vm86_active = 0;
3037
3038         vmx_segment_cache_clear(vmx);
3039
3040         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3041
3042         flags = vmcs_readl(GUEST_RFLAGS);
3043         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3044         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3045         vmcs_writel(GUEST_RFLAGS, flags);
3046
3047         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3048                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3049
3050         update_exception_bitmap(vcpu);
3051
3052         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3053         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3054         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3055         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3056         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3057         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3058
3059         /* CPL is always 0 when CPU enters protected mode */
3060         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3061         vmx->cpl = 0;
3062 }
3063
3064 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3065 {
3066         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3067         struct kvm_segment var = *save;
3068
3069         var.dpl = 0x3;
3070         if (seg == VCPU_SREG_CS)
3071                 var.type = 0x3;
3072
3073         if (!emulate_invalid_guest_state) {
3074                 var.selector = var.base >> 4;
3075                 var.base = var.base & 0xffff0;
3076                 var.limit = 0xffff;
3077                 var.g = 0;
3078                 var.db = 0;
3079                 var.present = 1;
3080                 var.s = 1;
3081                 var.l = 0;
3082                 var.unusable = 0;
3083                 var.type = 0x3;
3084                 var.avl = 0;
3085                 if (save->base & 0xf)
3086                         printk_once(KERN_WARNING "kvm: segment base is not "
3087                                         "paragraph aligned when entering "
3088                                         "protected mode (seg=%d)", seg);
3089         }
3090
3091         vmcs_write16(sf->selector, var.selector);
3092         vmcs_write32(sf->base, var.base);
3093         vmcs_write32(sf->limit, var.limit);
3094         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3095 }
3096
3097 static void enter_rmode(struct kvm_vcpu *vcpu)
3098 {
3099         unsigned long flags;
3100         struct vcpu_vmx *vmx = to_vmx(vcpu);
3101
3102         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3103         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3104         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3105         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3106         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3107         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3108         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3109
3110         vmx->rmode.vm86_active = 1;
3111
3112         /*
3113          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3114          * vcpu. Warn the user that an update is overdue.
3115          */
3116         if (!vcpu->kvm->arch.tss_addr)
3117                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3118                              "called before entering vcpu\n");
3119
3120         vmx_segment_cache_clear(vmx);
3121
3122         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3123         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3124         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3125
3126         flags = vmcs_readl(GUEST_RFLAGS);
3127         vmx->rmode.save_rflags = flags;
3128
3129         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3130
3131         vmcs_writel(GUEST_RFLAGS, flags);
3132         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3133         update_exception_bitmap(vcpu);
3134
3135         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3136         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3137         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3138         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3139         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3140         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3141
3142         kvm_mmu_reset_context(vcpu);
3143 }
3144
3145 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3146 {
3147         struct vcpu_vmx *vmx = to_vmx(vcpu);
3148         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3149
3150         if (!msr)
3151                 return;
3152
3153         /*
3154          * Force kernel_gs_base reloading before EFER changes, as control
3155          * of this msr depends on is_long_mode().
3156          */
3157         vmx_load_host_state(to_vmx(vcpu));
3158         vcpu->arch.efer = efer;
3159         if (efer & EFER_LMA) {
3160                 vmcs_write32(VM_ENTRY_CONTROLS,
3161                              vmcs_read32(VM_ENTRY_CONTROLS) |
3162                              VM_ENTRY_IA32E_MODE);
3163                 msr->data = efer;
3164         } else {
3165                 vmcs_write32(VM_ENTRY_CONTROLS,
3166                              vmcs_read32(VM_ENTRY_CONTROLS) &
3167                              ~VM_ENTRY_IA32E_MODE);
3168
3169                 msr->data = efer & ~EFER_LME;
3170         }
3171         setup_msrs(vmx);
3172 }
3173
3174 #ifdef CONFIG_X86_64
3175
3176 static void enter_lmode(struct kvm_vcpu *vcpu)
3177 {
3178         u32 guest_tr_ar;
3179
3180         vmx_segment_cache_clear(to_vmx(vcpu));
3181
3182         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3183         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3184                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3185                                      __func__);
3186                 vmcs_write32(GUEST_TR_AR_BYTES,
3187                              (guest_tr_ar & ~AR_TYPE_MASK)
3188                              | AR_TYPE_BUSY_64_TSS);
3189         }
3190         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3191 }
3192
3193 static void exit_lmode(struct kvm_vcpu *vcpu)
3194 {
3195         vmcs_write32(VM_ENTRY_CONTROLS,
3196                      vmcs_read32(VM_ENTRY_CONTROLS)
3197                      & ~VM_ENTRY_IA32E_MODE);
3198         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3199 }
3200
3201 #endif
3202
3203 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3204 {
3205         vpid_sync_context(to_vmx(vcpu));
3206         if (enable_ept) {
3207                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3208                         return;
3209                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3210         }
3211 }
3212
3213 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3214 {
3215         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3216
3217         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3218         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3219 }
3220
3221 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3222 {
3223         if (enable_ept && is_paging(vcpu))
3224                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3225         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3226 }
3227
3228 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3229 {
3230         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3231
3232         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3233         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3234 }
3235
3236 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3237 {
3238         if (!test_bit(VCPU_EXREG_PDPTR,
3239                       (unsigned long *)&vcpu->arch.regs_dirty))
3240                 return;
3241
3242         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3243                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3244                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3245                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3246                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3247         }
3248 }
3249
3250 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3251 {
3252         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3253                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3254                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3255                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3256                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3257         }
3258
3259         __set_bit(VCPU_EXREG_PDPTR,
3260                   (unsigned long *)&vcpu->arch.regs_avail);
3261         __set_bit(VCPU_EXREG_PDPTR,
3262                   (unsigned long *)&vcpu->arch.regs_dirty);
3263 }
3264
3265 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3266
3267 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3268                                         unsigned long cr0,
3269                                         struct kvm_vcpu *vcpu)
3270 {
3271         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3272                 vmx_decache_cr3(vcpu);
3273         if (!(cr0 & X86_CR0_PG)) {
3274                 /* From paging/starting to nonpaging */
3275                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3276                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3277                              (CPU_BASED_CR3_LOAD_EXITING |
3278                               CPU_BASED_CR3_STORE_EXITING));
3279                 vcpu->arch.cr0 = cr0;
3280                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3281         } else if (!is_paging(vcpu)) {
3282                 /* From nonpaging to paging */
3283                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3284                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3285                              ~(CPU_BASED_CR3_LOAD_EXITING |
3286                                CPU_BASED_CR3_STORE_EXITING));
3287                 vcpu->arch.cr0 = cr0;
3288                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3289         }
3290
3291         if (!(cr0 & X86_CR0_WP))
3292                 *hw_cr0 &= ~X86_CR0_WP;
3293 }
3294
3295 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3296 {
3297         struct vcpu_vmx *vmx = to_vmx(vcpu);
3298         unsigned long hw_cr0;
3299
3300         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3301         if (enable_unrestricted_guest)
3302                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3303         else {
3304                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3305
3306                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3307                         enter_pmode(vcpu);
3308
3309                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3310                         enter_rmode(vcpu);
3311         }
3312
3313 #ifdef CONFIG_X86_64
3314         if (vcpu->arch.efer & EFER_LME) {
3315                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3316                         enter_lmode(vcpu);
3317                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3318                         exit_lmode(vcpu);
3319         }
3320 #endif
3321
3322         if (enable_ept)
3323                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3324
3325         if (!vcpu->fpu_active)
3326                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3327
3328         vmcs_writel(CR0_READ_SHADOW, cr0);
3329         vmcs_writel(GUEST_CR0, hw_cr0);
3330         vcpu->arch.cr0 = cr0;
3331
3332         /* depends on vcpu->arch.cr0 to be set to a new value */
3333         vmx->emulation_required = emulation_required(vcpu);
3334 }
3335
3336 static u64 construct_eptp(unsigned long root_hpa)
3337 {
3338         u64 eptp;
3339
3340         /* TODO write the value reading from MSR */
3341         eptp = VMX_EPT_DEFAULT_MT |
3342                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3343         if (enable_ept_ad_bits)
3344                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3345         eptp |= (root_hpa & PAGE_MASK);
3346
3347         return eptp;
3348 }
3349
3350 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3351 {
3352         unsigned long guest_cr3;
3353         u64 eptp;
3354
3355         guest_cr3 = cr3;
3356         if (enable_ept) {
3357                 eptp = construct_eptp(cr3);
3358                 vmcs_write64(EPT_POINTER, eptp);
3359                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3360                         vcpu->kvm->arch.ept_identity_map_addr;
3361                 ept_load_pdptrs(vcpu);
3362         }
3363
3364         vmx_flush_tlb(vcpu);
3365         vmcs_writel(GUEST_CR3, guest_cr3);
3366 }
3367
3368 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3369 {
3370         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3371                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3372
3373         if (cr4 & X86_CR4_VMXE) {
3374                 /*
3375                  * To use VMXON (and later other VMX instructions), a guest
3376                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3377                  * So basically the check on whether to allow nested VMX
3378                  * is here.
3379                  */
3380                 if (!nested_vmx_allowed(vcpu))
3381                         return 1;
3382         }
3383         if (to_vmx(vcpu)->nested.vmxon &&
3384             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3385                 return 1;
3386
3387         vcpu->arch.cr4 = cr4;
3388         if (enable_ept) {
3389                 if (!is_paging(vcpu)) {
3390                         hw_cr4 &= ~X86_CR4_PAE;
3391                         hw_cr4 |= X86_CR4_PSE;
3392                         /*
3393                          * SMEP is disabled if CPU is in non-paging mode in
3394                          * hardware. However KVM always uses paging mode to
3395                          * emulate guest non-paging mode with TDP.
3396                          * To emulate this behavior, SMEP needs to be manually
3397                          * disabled when guest switches to non-paging mode.
3398                          */
3399                         hw_cr4 &= ~X86_CR4_SMEP;
3400                 } else if (!(cr4 & X86_CR4_PAE)) {
3401                         hw_cr4 &= ~X86_CR4_PAE;
3402                 }
3403         }
3404
3405         vmcs_writel(CR4_READ_SHADOW, cr4);
3406         vmcs_writel(GUEST_CR4, hw_cr4);
3407         return 0;
3408 }
3409
3410 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3411                             struct kvm_segment *var, int seg)
3412 {
3413         struct vcpu_vmx *vmx = to_vmx(vcpu);
3414         u32 ar;
3415
3416         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3417                 *var = vmx->rmode.segs[seg];
3418                 if (seg == VCPU_SREG_TR
3419                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3420                         return;
3421                 var->base = vmx_read_guest_seg_base(vmx, seg);
3422                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3423                 return;
3424         }
3425         var->base = vmx_read_guest_seg_base(vmx, seg);
3426         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3427         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3428         ar = vmx_read_guest_seg_ar(vmx, seg);
3429         var->unusable = (ar >> 16) & 1;
3430         var->type = ar & 15;
3431         var->s = (ar >> 4) & 1;
3432         var->dpl = (ar >> 5) & 3;
3433         /*
3434          * Some userspaces do not preserve unusable property. Since usable
3435          * segment has to be present according to VMX spec we can use present
3436          * property to amend userspace bug by making unusable segment always
3437          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3438          * segment as unusable.
3439          */
3440         var->present = !var->unusable;
3441         var->avl = (ar >> 12) & 1;
3442         var->l = (ar >> 13) & 1;
3443         var->db = (ar >> 14) & 1;
3444         var->g = (ar >> 15) & 1;
3445 }
3446
3447 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3448 {
3449         struct kvm_segment s;
3450
3451         if (to_vmx(vcpu)->rmode.vm86_active) {
3452                 vmx_get_segment(vcpu, &s, seg);
3453                 return s.base;
3454         }
3455         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3456 }
3457
3458 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3459 {
3460         struct vcpu_vmx *vmx = to_vmx(vcpu);
3461
3462         if (!is_protmode(vcpu))
3463                 return 0;
3464
3465         if (!is_long_mode(vcpu)
3466             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3467                 return 3;
3468
3469         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3470                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3471                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3472         }
3473
3474         return vmx->cpl;
3475 }
3476
3477
3478 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3479 {
3480         u32 ar;
3481
3482         if (var->unusable || !var->present)
3483                 ar = 1 << 16;
3484         else {
3485                 ar = var->type & 15;
3486                 ar |= (var->s & 1) << 4;
3487                 ar |= (var->dpl & 3) << 5;
3488                 ar |= (var->present & 1) << 7;
3489                 ar |= (var->avl & 1) << 12;
3490                 ar |= (var->l & 1) << 13;
3491                 ar |= (var->db & 1) << 14;
3492                 ar |= (var->g & 1) << 15;
3493         }
3494
3495         return ar;
3496 }
3497
3498 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3499                             struct kvm_segment *var, int seg)
3500 {
3501         struct vcpu_vmx *vmx = to_vmx(vcpu);
3502         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3503
3504         vmx_segment_cache_clear(vmx);
3505         if (seg == VCPU_SREG_CS)
3506                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3507
3508         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3509                 vmx->rmode.segs[seg] = *var;
3510                 if (seg == VCPU_SREG_TR)
3511                         vmcs_write16(sf->selector, var->selector);
3512                 else if (var->s)
3513                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3514                 goto out;
3515         }
3516
3517         vmcs_writel(sf->base, var->base);
3518         vmcs_write32(sf->limit, var->limit);
3519         vmcs_write16(sf->selector, var->selector);
3520
3521         /*
3522          *   Fix the "Accessed" bit in AR field of segment registers for older
3523          * qemu binaries.
3524          *   IA32 arch specifies that at the time of processor reset the
3525          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3526          * is setting it to 0 in the userland code. This causes invalid guest
3527          * state vmexit when "unrestricted guest" mode is turned on.
3528          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3529          * tree. Newer qemu binaries with that qemu fix would not need this
3530          * kvm hack.
3531          */
3532         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3533                 var->type |= 0x1; /* Accessed */
3534
3535         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3536
3537 out:
3538         vmx->emulation_required |= emulation_required(vcpu);
3539 }
3540
3541 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3542 {
3543         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3544
3545         *db = (ar >> 14) & 1;
3546         *l = (ar >> 13) & 1;
3547 }
3548
3549 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3550 {
3551         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3552         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3553 }
3554
3555 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3556 {
3557         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3558         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3559 }
3560
3561 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3562 {
3563         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3564         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3565 }
3566
3567 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3568 {
3569         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3570         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3571 }
3572
3573 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3574 {
3575         struct kvm_segment var;
3576         u32 ar;
3577
3578         vmx_get_segment(vcpu, &var, seg);
3579         var.dpl = 0x3;
3580         if (seg == VCPU_SREG_CS)
3581                 var.type = 0x3;
3582         ar = vmx_segment_access_rights(&var);
3583
3584         if (var.base != (var.selector << 4))
3585                 return false;
3586         if (var.limit != 0xffff)
3587                 return false;
3588         if (ar != 0xf3)
3589                 return false;
3590
3591         return true;
3592 }
3593
3594 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3595 {
3596         struct kvm_segment cs;
3597         unsigned int cs_rpl;
3598
3599         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3600         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3601
3602         if (cs.unusable)
3603                 return false;
3604         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3605                 return false;
3606         if (!cs.s)
3607                 return false;
3608         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3609                 if (cs.dpl > cs_rpl)
3610                         return false;
3611         } else {
3612                 if (cs.dpl != cs_rpl)
3613                         return false;
3614         }
3615         if (!cs.present)
3616                 return false;
3617
3618         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3619         return true;
3620 }
3621
3622 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3623 {
3624         struct kvm_segment ss;
3625         unsigned int ss_rpl;
3626
3627         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3628         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3629
3630         if (ss.unusable)
3631                 return true;
3632         if (ss.type != 3 && ss.type != 7)
3633                 return false;
3634         if (!ss.s)
3635                 return false;
3636         if (ss.dpl != ss_rpl) /* DPL != RPL */
3637                 return false;
3638         if (!ss.present)
3639                 return false;
3640
3641         return true;
3642 }
3643
3644 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3645 {
3646         struct kvm_segment var;
3647         unsigned int rpl;
3648
3649         vmx_get_segment(vcpu, &var, seg);
3650         rpl = var.selector & SELECTOR_RPL_MASK;
3651
3652         if (var.unusable)
3653                 return true;
3654         if (!var.s)
3655                 return false;
3656         if (!var.present)
3657                 return false;
3658         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3659                 if (var.dpl < rpl) /* DPL < RPL */
3660                         return false;
3661         }
3662
3663         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3664          * rights flags
3665          */
3666         return true;
3667 }
3668
3669 static bool tr_valid(struct kvm_vcpu *vcpu)
3670 {
3671         struct kvm_segment tr;
3672
3673         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3674
3675         if (tr.unusable)
3676                 return false;
3677         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3678                 return false;
3679         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3680                 return false;
3681         if (!tr.present)
3682                 return false;
3683
3684         return true;
3685 }
3686
3687 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3688 {
3689         struct kvm_segment ldtr;
3690
3691         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3692
3693         if (ldtr.unusable)
3694                 return true;
3695         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3696                 return false;
3697         if (ldtr.type != 2)
3698                 return false;
3699         if (!ldtr.present)
3700                 return false;
3701
3702         return true;
3703 }
3704
3705 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3706 {
3707         struct kvm_segment cs, ss;
3708
3709         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3710         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3711
3712         return ((cs.selector & SELECTOR_RPL_MASK) ==
3713                  (ss.selector & SELECTOR_RPL_MASK));
3714 }
3715
3716 /*
3717  * Check if guest state is valid. Returns true if valid, false if
3718  * not.
3719  * We assume that registers are always usable
3720  */
3721 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3722 {
3723         if (enable_unrestricted_guest)
3724                 return true;
3725
3726         /* real mode guest state checks */
3727         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3728                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3729                         return false;
3730                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3731                         return false;
3732                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3733                         return false;
3734                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3735                         return false;
3736                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3737                         return false;
3738                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3739                         return false;
3740         } else {
3741         /* protected mode guest state checks */
3742                 if (!cs_ss_rpl_check(vcpu))
3743                         return false;
3744                 if (!code_segment_valid(vcpu))
3745                         return false;
3746                 if (!stack_segment_valid(vcpu))
3747                         return false;
3748                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3749                         return false;
3750                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3751                         return false;
3752                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3753                         return false;
3754                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3755                         return false;
3756                 if (!tr_valid(vcpu))
3757                         return false;
3758                 if (!ldtr_valid(vcpu))
3759                         return false;
3760         }
3761         /* TODO:
3762          * - Add checks on RIP
3763          * - Add checks on RFLAGS
3764          */
3765
3766         return true;
3767 }
3768
3769 static int init_rmode_tss(struct kvm *kvm)
3770 {
3771         gfn_t fn;
3772         u16 data = 0;
3773         int r, idx, ret = 0;
3774
3775         idx = srcu_read_lock(&kvm->srcu);
3776         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3777         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3778         if (r < 0)
3779                 goto out;
3780         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3781         r = kvm_write_guest_page(kvm, fn++, &data,
3782                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3783         if (r < 0)
3784                 goto out;
3785         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3786         if (r < 0)
3787                 goto out;
3788         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3789         if (r < 0)
3790                 goto out;
3791         data = ~0;
3792         r = kvm_write_guest_page(kvm, fn, &data,
3793                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3794                                  sizeof(u8));
3795         if (r < 0)
3796                 goto out;
3797
3798         ret = 1;
3799 out:
3800         srcu_read_unlock(&kvm->srcu, idx);
3801         return ret;
3802 }
3803
3804 static int init_rmode_identity_map(struct kvm *kvm)
3805 {
3806         int i, idx, r, ret;
3807         pfn_t identity_map_pfn;
3808         u32 tmp;
3809
3810         if (!enable_ept)
3811                 return 1;
3812         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3813                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3814                         "haven't been allocated!\n");
3815                 return 0;
3816         }
3817         if (likely(kvm->arch.ept_identity_pagetable_done))
3818                 return 1;
3819         ret = 0;
3820         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3821         idx = srcu_read_lock(&kvm->srcu);
3822         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3823         if (r < 0)
3824                 goto out;
3825         /* Set up identity-mapping pagetable for EPT in real mode */
3826         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3827                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3828                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3829                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3830                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3831                 if (r < 0)
3832                         goto out;
3833         }
3834         kvm->arch.ept_identity_pagetable_done = true;
3835         ret = 1;
3836 out:
3837         srcu_read_unlock(&kvm->srcu, idx);
3838         return ret;
3839 }
3840
3841 static void seg_setup(int seg)
3842 {
3843         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3844         unsigned int ar;
3845
3846         vmcs_write16(sf->selector, 0);
3847         vmcs_writel(sf->base, 0);
3848         vmcs_write32(sf->limit, 0xffff);
3849         ar = 0x93;
3850         if (seg == VCPU_SREG_CS)
3851                 ar |= 0x08; /* code segment */
3852
3853         vmcs_write32(sf->ar_bytes, ar);
3854 }
3855
3856 static int alloc_apic_access_page(struct kvm *kvm)
3857 {
3858         struct page *page;
3859         struct kvm_userspace_memory_region kvm_userspace_mem;
3860         int r = 0;
3861
3862         mutex_lock(&kvm->slots_lock);
3863         if (kvm->arch.apic_access_page)
3864                 goto out;
3865         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3866         kvm_userspace_mem.flags = 0;
3867         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3868         kvm_userspace_mem.memory_size = PAGE_SIZE;
3869         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3870         if (r)
3871                 goto out;
3872
3873         page = gfn_to_page(kvm, 0xfee00);
3874         if (is_error_page(page)) {
3875                 r = -EFAULT;
3876                 goto out;
3877         }
3878
3879         kvm->arch.apic_access_page = page;
3880 out:
3881         mutex_unlock(&kvm->slots_lock);
3882         return r;
3883 }
3884
3885 static int alloc_identity_pagetable(struct kvm *kvm)
3886 {
3887         struct page *page;
3888         struct kvm_userspace_memory_region kvm_userspace_mem;
3889         int r = 0;
3890
3891         mutex_lock(&kvm->slots_lock);
3892         if (kvm->arch.ept_identity_pagetable)
3893                 goto out;
3894         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3895         kvm_userspace_mem.flags = 0;
3896         kvm_userspace_mem.guest_phys_addr =
3897                 kvm->arch.ept_identity_map_addr;
3898         kvm_userspace_mem.memory_size = PAGE_SIZE;
3899         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3900         if (r)
3901                 goto out;
3902
3903         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3904         if (is_error_page(page)) {
3905                 r = -EFAULT;
3906                 goto out;
3907         }
3908
3909         kvm->arch.ept_identity_pagetable = page;
3910 out:
3911         mutex_unlock(&kvm->slots_lock);
3912         return r;
3913 }
3914
3915 static void allocate_vpid(struct vcpu_vmx *vmx)
3916 {
3917         int vpid;
3918
3919         vmx->vpid = 0;
3920         if (!enable_vpid)
3921                 return;
3922         spin_lock(&vmx_vpid_lock);
3923         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3924         if (vpid < VMX_NR_VPIDS) {
3925                 vmx->vpid = vpid;
3926                 __set_bit(vpid, vmx_vpid_bitmap);
3927         }
3928         spin_unlock(&vmx_vpid_lock);
3929 }
3930
3931 static void free_vpid(struct vcpu_vmx *vmx)
3932 {
3933         if (!enable_vpid)
3934                 return;
3935         spin_lock(&vmx_vpid_lock);
3936         if (vmx->vpid != 0)
3937                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3938         spin_unlock(&vmx_vpid_lock);
3939 }
3940
3941 #define MSR_TYPE_R      1
3942 #define MSR_TYPE_W      2
3943 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3944                                                 u32 msr, int type)
3945 {
3946         int f = sizeof(unsigned long);
3947
3948         if (!cpu_has_vmx_msr_bitmap())
3949                 return;
3950
3951         /*
3952          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3953          * have the write-low and read-high bitmap offsets the wrong way round.
3954          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3955          */
3956         if (msr <= 0x1fff) {
3957                 if (type & MSR_TYPE_R)
3958                         /* read-low */
3959                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3960
3961                 if (type & MSR_TYPE_W)
3962                         /* write-low */
3963                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3964
3965         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3966                 msr &= 0x1fff;
3967                 if (type & MSR_TYPE_R)
3968                         /* read-high */
3969                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3970
3971                 if (type & MSR_TYPE_W)
3972                         /* write-high */
3973                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3974
3975         }
3976 }
3977
3978 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3979                                                 u32 msr, int type)
3980 {
3981         int f = sizeof(unsigned long);
3982
3983         if (!cpu_has_vmx_msr_bitmap())
3984                 return;
3985
3986         /*
3987          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3988          * have the write-low and read-high bitmap offsets the wrong way round.
3989          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3990          */
3991         if (msr <= 0x1fff) {
3992                 if (type & MSR_TYPE_R)
3993                         /* read-low */
3994                         __set_bit(msr, msr_bitmap + 0x000 / f);
3995
3996                 if (type & MSR_TYPE_W)
3997                         /* write-low */
3998                         __set_bit(msr, msr_bitmap + 0x800 / f);
3999
4000         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4001                 msr &= 0x1fff;
4002                 if (type & MSR_TYPE_R)
4003                         /* read-high */
4004                         __set_bit(msr, msr_bitmap + 0x400 / f);
4005
4006                 if (type & MSR_TYPE_W)
4007                         /* write-high */
4008                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4009
4010         }
4011 }
4012
4013 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4014 {
4015         if (!longmode_only)
4016                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4017                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4018         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4019                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4020 }
4021
4022 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4023 {
4024         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4025                         msr, MSR_TYPE_R);
4026         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4027                         msr, MSR_TYPE_R);
4028 }
4029
4030 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4031 {
4032         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4033                         msr, MSR_TYPE_R);
4034         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4035                         msr, MSR_TYPE_R);
4036 }
4037
4038 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4039 {
4040         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4041                         msr, MSR_TYPE_W);
4042         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4043                         msr, MSR_TYPE_W);
4044 }
4045
4046 static int vmx_vm_has_apicv(struct kvm *kvm)
4047 {
4048         return enable_apicv && irqchip_in_kernel(kvm);
4049 }
4050
4051 /*
4052  * Send interrupt to vcpu via posted interrupt way.
4053  * 1. If target vcpu is running(non-root mode), send posted interrupt
4054  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4055  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4056  * interrupt from PIR in next vmentry.
4057  */
4058 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4059 {
4060         struct vcpu_vmx *vmx = to_vmx(vcpu);
4061         int r;
4062
4063         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4064                 return;
4065
4066         r = pi_test_and_set_on(&vmx->pi_desc);
4067         kvm_make_request(KVM_REQ_EVENT, vcpu);
4068 #ifdef CONFIG_SMP
4069         if (!r && (vcpu->mode == IN_GUEST_MODE))
4070                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4071                                 POSTED_INTR_VECTOR);
4072         else
4073 #endif
4074                 kvm_vcpu_kick(vcpu);
4075 }
4076
4077 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4078 {
4079         struct vcpu_vmx *vmx = to_vmx(vcpu);
4080
4081         if (!pi_test_and_clear_on(&vmx->pi_desc))
4082                 return;
4083
4084         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4085 }
4086
4087 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4088 {
4089         return;
4090 }
4091
4092 /*
4093  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4094  * will not change in the lifetime of the guest.
4095  * Note that host-state that does change is set elsewhere. E.g., host-state
4096  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4097  */
4098 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4099 {
4100         u32 low32, high32;
4101         unsigned long tmpl;
4102         struct desc_ptr dt;
4103
4104         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4105         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4106         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4107
4108         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4109 #ifdef CONFIG_X86_64
4110         /*
4111          * Load null selectors, so we can avoid reloading them in
4112          * __vmx_load_host_state(), in case userspace uses the null selectors
4113          * too (the expected case).
4114          */
4115         vmcs_write16(HOST_DS_SELECTOR, 0);
4116         vmcs_write16(HOST_ES_SELECTOR, 0);
4117 #else
4118         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4119         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4120 #endif
4121         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4122         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4123
4124         native_store_idt(&dt);
4125         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4126         vmx->host_idt_base = dt.address;
4127
4128         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4129
4130         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4131         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4132         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4133         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4134
4135         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4136                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4137                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4138         }
4139 }
4140
4141 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4142 {
4143         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4144         if (enable_ept)
4145                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4146         if (is_guest_mode(&vmx->vcpu))
4147                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4148                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4149         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4150 }
4151
4152 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4153 {
4154         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4155
4156         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4157                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4158         return pin_based_exec_ctrl;
4159 }
4160
4161 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4162 {
4163         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4164         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4165                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4166 #ifdef CONFIG_X86_64
4167                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4168                                 CPU_BASED_CR8_LOAD_EXITING;
4169 #endif
4170         }
4171         if (!enable_ept)
4172                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4173                                 CPU_BASED_CR3_LOAD_EXITING  |
4174                                 CPU_BASED_INVLPG_EXITING;
4175         return exec_control;
4176 }
4177
4178 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4179 {
4180         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4181         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4182                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4183         if (vmx->vpid == 0)
4184                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4185         if (!enable_ept) {
4186                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4187                 enable_unrestricted_guest = 0;
4188                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4189                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4190         }
4191         if (!enable_unrestricted_guest)
4192                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4193         if (!ple_gap)
4194                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4195         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4196                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4197                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4198         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4199         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4200            (handle_vmptrld).
4201            We can NOT enable shadow_vmcs here because we don't have yet
4202            a current VMCS12
4203         */
4204         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4205         return exec_control;
4206 }
4207
4208 static void ept_set_mmio_spte_mask(void)
4209 {
4210         /*
4211          * EPT Misconfigurations can be generated if the value of bits 2:0
4212          * of an EPT paging-structure entry is 110b (write/execute).
4213          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4214          * spte.
4215          */
4216         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4217 }
4218
4219 /*
4220  * Sets up the vmcs for emulated real mode.
4221  */
4222 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4223 {
4224 #ifdef CONFIG_X86_64
4225         unsigned long a;
4226 #endif
4227         int i;
4228
4229         /* I/O */
4230         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4231         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4232
4233         if (enable_shadow_vmcs) {
4234                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4235                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4236         }
4237         if (cpu_has_vmx_msr_bitmap())
4238                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4239
4240         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4241
4242         /* Control */
4243         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4244
4245         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4246
4247         if (cpu_has_secondary_exec_ctrls()) {
4248                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4249                                 vmx_secondary_exec_control(vmx));
4250         }
4251
4252         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4253                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4254                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4255                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4256                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4257
4258                 vmcs_write16(GUEST_INTR_STATUS, 0);
4259
4260                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4261                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4262         }
4263
4264         if (ple_gap) {
4265                 vmcs_write32(PLE_GAP, ple_gap);
4266                 vmcs_write32(PLE_WINDOW, ple_window);
4267         }
4268
4269         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4270         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4271         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4272
4273         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4274         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4275         vmx_set_constant_host_state(vmx);
4276 #ifdef CONFIG_X86_64
4277         rdmsrl(MSR_FS_BASE, a);
4278         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4279         rdmsrl(MSR_GS_BASE, a);
4280         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4281 #else
4282         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4283         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4284 #endif
4285
4286         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4287         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4288         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4289         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4290         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4291
4292         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4293                 u32 msr_low, msr_high;
4294                 u64 host_pat;
4295                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4296                 host_pat = msr_low | ((u64) msr_high << 32);
4297                 /* Write the default value follow host pat */
4298                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4299                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4300                 vmx->vcpu.arch.pat = host_pat;
4301         }
4302
4303         for (i = 0; i < NR_VMX_MSR; ++i) {
4304                 u32 index = vmx_msr_index[i];
4305                 u32 data_low, data_high;
4306                 int j = vmx->nmsrs;
4307
4308                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4309                         continue;
4310                 if (wrmsr_safe(index, data_low, data_high) < 0)
4311                         continue;
4312                 vmx->guest_msrs[j].index = i;
4313                 vmx->guest_msrs[j].data = 0;
4314                 vmx->guest_msrs[j].mask = -1ull;
4315                 ++vmx->nmsrs;
4316         }
4317
4318         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4319
4320         /* 22.2.1, 20.8.1 */
4321         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4322
4323         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4324         set_cr4_guest_host_mask(vmx);
4325
4326         return 0;
4327 }
4328
4329 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4330 {
4331         struct vcpu_vmx *vmx = to_vmx(vcpu);
4332         u64 msr;
4333
4334         vmx->rmode.vm86_active = 0;
4335
4336         vmx->soft_vnmi_blocked = 0;
4337
4338         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4339         kvm_set_cr8(&vmx->vcpu, 0);
4340         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4341         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4342                 msr |= MSR_IA32_APICBASE_BSP;
4343         kvm_set_apic_base(&vmx->vcpu, msr);
4344
4345         vmx_segment_cache_clear(vmx);
4346
4347         seg_setup(VCPU_SREG_CS);
4348         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4349         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4350
4351         seg_setup(VCPU_SREG_DS);
4352         seg_setup(VCPU_SREG_ES);
4353         seg_setup(VCPU_SREG_FS);
4354         seg_setup(VCPU_SREG_GS);
4355         seg_setup(VCPU_SREG_SS);
4356
4357         vmcs_write16(GUEST_TR_SELECTOR, 0);
4358         vmcs_writel(GUEST_TR_BASE, 0);
4359         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4360         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4361
4362         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4363         vmcs_writel(GUEST_LDTR_BASE, 0);
4364         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4365         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4366
4367         vmcs_write32(GUEST_SYSENTER_CS, 0);
4368         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4369         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4370
4371         vmcs_writel(GUEST_RFLAGS, 0x02);
4372         kvm_rip_write(vcpu, 0xfff0);
4373
4374         vmcs_writel(GUEST_GDTR_BASE, 0);
4375         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4376
4377         vmcs_writel(GUEST_IDTR_BASE, 0);
4378         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4379
4380         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4381         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4382         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4383
4384         /* Special registers */
4385         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4386
4387         setup_msrs(vmx);
4388
4389         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4390
4391         if (cpu_has_vmx_tpr_shadow()) {
4392                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4393                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4394                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4395                                      __pa(vmx->vcpu.arch.apic->regs));
4396                 vmcs_write32(TPR_THRESHOLD, 0);
4397         }
4398
4399         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4400                 vmcs_write64(APIC_ACCESS_ADDR,
4401                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4402
4403         if (vmx_vm_has_apicv(vcpu->kvm))
4404                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4405
4406         if (vmx->vpid != 0)
4407                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4408
4409         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4410         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4411         vmx_set_cr4(&vmx->vcpu, 0);
4412         vmx_set_efer(&vmx->vcpu, 0);
4413         vmx_fpu_activate(&vmx->vcpu);
4414         update_exception_bitmap(&vmx->vcpu);
4415
4416         vpid_sync_context(vmx);
4417 }
4418
4419 /*
4420  * In nested virtualization, check if L1 asked to exit on external interrupts.
4421  * For most existing hypervisors, this will always return true.
4422  */
4423 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4424 {
4425         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4426                 PIN_BASED_EXT_INTR_MASK;
4427 }
4428
4429 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4430 {
4431         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4432                 PIN_BASED_NMI_EXITING;
4433 }
4434
4435 static int enable_irq_window(struct kvm_vcpu *vcpu)
4436 {
4437         u32 cpu_based_vm_exec_control;
4438
4439         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4440                 /*
4441                  * We get here if vmx_interrupt_allowed() said we can't
4442                  * inject to L1 now because L2 must run. The caller will have
4443                  * to make L2 exit right after entry, so we can inject to L1
4444                  * more promptly.
4445                  */
4446                 return -EBUSY;
4447
4448         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4449         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4450         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4451         return 0;
4452 }
4453
4454 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4455 {
4456         u32 cpu_based_vm_exec_control;
4457
4458         if (!cpu_has_virtual_nmis())
4459                 return enable_irq_window(vcpu);
4460
4461         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4462                 return enable_irq_window(vcpu);
4463
4464         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4465         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4466         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4467         return 0;
4468 }
4469
4470 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4471 {
4472         struct vcpu_vmx *vmx = to_vmx(vcpu);
4473         uint32_t intr;
4474         int irq = vcpu->arch.interrupt.nr;
4475
4476         trace_kvm_inj_virq(irq);
4477
4478         ++vcpu->stat.irq_injections;
4479         if (vmx->rmode.vm86_active) {
4480                 int inc_eip = 0;
4481                 if (vcpu->arch.interrupt.soft)
4482                         inc_eip = vcpu->arch.event_exit_inst_len;
4483                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4484                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4485                 return;
4486         }
4487         intr = irq | INTR_INFO_VALID_MASK;
4488         if (vcpu->arch.interrupt.soft) {
4489                 intr |= INTR_TYPE_SOFT_INTR;
4490                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4491                              vmx->vcpu.arch.event_exit_inst_len);
4492         } else
4493                 intr |= INTR_TYPE_EXT_INTR;
4494         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4495 }
4496
4497 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4498 {
4499         struct vcpu_vmx *vmx = to_vmx(vcpu);
4500
4501         if (is_guest_mode(vcpu))
4502                 return;
4503
4504         if (!cpu_has_virtual_nmis()) {
4505                 /*
4506                  * Tracking the NMI-blocked state in software is built upon
4507                  * finding the next open IRQ window. This, in turn, depends on
4508                  * well-behaving guests: They have to keep IRQs disabled at
4509                  * least as long as the NMI handler runs. Otherwise we may
4510                  * cause NMI nesting, maybe breaking the guest. But as this is
4511                  * highly unlikely, we can live with the residual risk.
4512                  */
4513                 vmx->soft_vnmi_blocked = 1;
4514                 vmx->vnmi_blocked_time = 0;
4515         }
4516
4517         ++vcpu->stat.nmi_injections;
4518         vmx->nmi_known_unmasked = false;
4519         if (vmx->rmode.vm86_active) {
4520                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4521                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4522                 return;
4523         }
4524         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4525                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4526 }
4527
4528 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4529 {
4530         if (!cpu_has_virtual_nmis())
4531                 return to_vmx(vcpu)->soft_vnmi_blocked;
4532         if (to_vmx(vcpu)->nmi_known_unmasked)
4533                 return false;
4534         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4535 }
4536
4537 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4538 {
4539         struct vcpu_vmx *vmx = to_vmx(vcpu);
4540
4541         if (!cpu_has_virtual_nmis()) {
4542                 if (vmx->soft_vnmi_blocked != masked) {
4543                         vmx->soft_vnmi_blocked = masked;
4544                         vmx->vnmi_blocked_time = 0;
4545                 }
4546         } else {
4547                 vmx->nmi_known_unmasked = !masked;
4548                 if (masked)
4549                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4550                                       GUEST_INTR_STATE_NMI);
4551                 else
4552                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4553                                         GUEST_INTR_STATE_NMI);
4554         }
4555 }
4556
4557 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4558 {
4559         if (is_guest_mode(vcpu)) {
4560                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4561
4562                 if (to_vmx(vcpu)->nested.nested_run_pending)
4563                         return 0;
4564                 if (nested_exit_on_nmi(vcpu)) {
4565                         nested_vmx_vmexit(vcpu);
4566                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4567                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4568                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4569                         /*
4570                          * The NMI-triggered VM exit counts as injection:
4571                          * clear this one and block further NMIs.
4572                          */
4573                         vcpu->arch.nmi_pending = 0;
4574                         vmx_set_nmi_mask(vcpu, true);
4575                         return 0;
4576                 }
4577         }
4578
4579         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4580                 return 0;
4581
4582         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4583                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4584                    | GUEST_INTR_STATE_NMI));
4585 }
4586
4587 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4588 {
4589         if (is_guest_mode(vcpu)) {
4590                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4591
4592                 if (to_vmx(vcpu)->nested.nested_run_pending)
4593                         return 0;
4594                 if (nested_exit_on_intr(vcpu)) {
4595                         nested_vmx_vmexit(vcpu);
4596                         vmcs12->vm_exit_reason =
4597                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4598                         vmcs12->vm_exit_intr_info = 0;
4599                         /*
4600                          * fall through to normal code, but now in L1, not L2
4601                          */
4602                 }
4603         }
4604
4605         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4606                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4607                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4608 }
4609
4610 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4611 {
4612         int ret;
4613         struct kvm_userspace_memory_region tss_mem = {
4614                 .slot = TSS_PRIVATE_MEMSLOT,
4615                 .guest_phys_addr = addr,
4616                 .memory_size = PAGE_SIZE * 3,
4617                 .flags = 0,
4618         };
4619
4620         ret = kvm_set_memory_region(kvm, &tss_mem);
4621         if (ret)
4622                 return ret;
4623         kvm->arch.tss_addr = addr;
4624         if (!init_rmode_tss(kvm))
4625                 return  -ENOMEM;
4626
4627         return 0;
4628 }
4629
4630 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4631 {
4632         switch (vec) {
4633         case BP_VECTOR:
4634                 /*
4635                  * Update instruction length as we may reinject the exception
4636                  * from user space while in guest debugging mode.
4637                  */
4638                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4639                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4640                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4641                         return false;
4642                 /* fall through */
4643         case DB_VECTOR:
4644                 if (vcpu->guest_debug &
4645                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4646                         return false;
4647                 /* fall through */
4648         case DE_VECTOR:
4649         case OF_VECTOR:
4650         case BR_VECTOR:
4651         case UD_VECTOR:
4652         case DF_VECTOR:
4653         case SS_VECTOR:
4654         case GP_VECTOR:
4655         case MF_VECTOR:
4656                 return true;
4657         break;
4658         }
4659         return false;
4660 }
4661
4662 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4663                                   int vec, u32 err_code)
4664 {
4665         /*
4666          * Instruction with address size override prefix opcode 0x67
4667          * Cause the #SS fault with 0 error code in VM86 mode.
4668          */
4669         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4670                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4671                         if (vcpu->arch.halt_request) {
4672                                 vcpu->arch.halt_request = 0;
4673                                 return kvm_emulate_halt(vcpu);
4674                         }
4675                         return 1;
4676                 }
4677                 return 0;
4678         }
4679
4680         /*
4681          * Forward all other exceptions that are valid in real mode.
4682          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4683          *        the required debugging infrastructure rework.
4684          */
4685         kvm_queue_exception(vcpu, vec);
4686         return 1;
4687 }
4688
4689 /*
4690  * Trigger machine check on the host. We assume all the MSRs are already set up
4691  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4692  * We pass a fake environment to the machine check handler because we want
4693  * the guest to be always treated like user space, no matter what context
4694  * it used internally.
4695  */
4696 static void kvm_machine_check(void)
4697 {
4698 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4699         struct pt_regs regs = {
4700                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4701                 .flags = X86_EFLAGS_IF,
4702         };
4703
4704         do_machine_check(&regs, 0);
4705 #endif
4706 }
4707
4708 static int handle_machine_check(struct kvm_vcpu *vcpu)
4709 {
4710         /* already handled by vcpu_run */
4711         return 1;
4712 }
4713
4714 static int handle_exception(struct kvm_vcpu *vcpu)
4715 {
4716         struct vcpu_vmx *vmx = to_vmx(vcpu);
4717         struct kvm_run *kvm_run = vcpu->run;
4718         u32 intr_info, ex_no, error_code;
4719         unsigned long cr2, rip, dr6;
4720         u32 vect_info;
4721         enum emulation_result er;
4722
4723         vect_info = vmx->idt_vectoring_info;
4724         intr_info = vmx->exit_intr_info;
4725
4726         if (is_machine_check(intr_info))
4727                 return handle_machine_check(vcpu);
4728
4729         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4730                 return 1;  /* already handled by vmx_vcpu_run() */
4731
4732         if (is_no_device(intr_info)) {
4733                 vmx_fpu_activate(vcpu);
4734                 return 1;
4735         }
4736
4737         if (is_invalid_opcode(intr_info)) {
4738                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4739                 if (er != EMULATE_DONE)
4740                         kvm_queue_exception(vcpu, UD_VECTOR);
4741                 return 1;
4742         }
4743
4744         error_code = 0;
4745         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4746                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4747
4748         /*
4749          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4750          * MMIO, it is better to report an internal error.
4751          * See the comments in vmx_handle_exit.
4752          */
4753         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4754             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4755                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4756                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4757                 vcpu->run->internal.ndata = 2;
4758                 vcpu->run->internal.data[0] = vect_info;
4759                 vcpu->run->internal.data[1] = intr_info;
4760                 return 0;
4761         }
4762
4763         if (is_page_fault(intr_info)) {
4764                 /* EPT won't cause page fault directly */
4765                 BUG_ON(enable_ept);
4766                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4767                 trace_kvm_page_fault(cr2, error_code);
4768
4769                 if (kvm_event_needs_reinjection(vcpu))
4770                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4771                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4772         }
4773
4774         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4775
4776         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4777                 return handle_rmode_exception(vcpu, ex_no, error_code);
4778
4779         switch (ex_no) {
4780         case DB_VECTOR:
4781                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4782                 if (!(vcpu->guest_debug &
4783                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4784                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4785                         kvm_queue_exception(vcpu, DB_VECTOR);
4786                         return 1;
4787                 }
4788                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4789                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4790                 /* fall through */
4791         case BP_VECTOR:
4792                 /*
4793                  * Update instruction length as we may reinject #BP from
4794                  * user space while in guest debugging mode. Reading it for
4795                  * #DB as well causes no harm, it is not used in that case.
4796                  */
4797                 vmx->vcpu.arch.event_exit_inst_len =
4798                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4799                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4800                 rip = kvm_rip_read(vcpu);
4801                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4802                 kvm_run->debug.arch.exception = ex_no;
4803                 break;
4804         default:
4805                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4806                 kvm_run->ex.exception = ex_no;
4807                 kvm_run->ex.error_code = error_code;
4808                 break;
4809         }
4810         return 0;
4811 }
4812
4813 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4814 {
4815         ++vcpu->stat.irq_exits;
4816         return 1;
4817 }
4818
4819 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4820 {
4821         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4822         return 0;
4823 }
4824
4825 static int handle_io(struct kvm_vcpu *vcpu)
4826 {
4827         unsigned long exit_qualification;
4828         int size, in, string;
4829         unsigned port;
4830
4831         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4832         string = (exit_qualification & 16) != 0;
4833         in = (exit_qualification & 8) != 0;
4834
4835         ++vcpu->stat.io_exits;
4836
4837         if (string || in)
4838                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4839
4840         port = exit_qualification >> 16;
4841         size = (exit_qualification & 7) + 1;
4842         skip_emulated_instruction(vcpu);
4843
4844         return kvm_fast_pio_out(vcpu, size, port);
4845 }
4846
4847 static void
4848 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4849 {
4850         /*
4851          * Patch in the VMCALL instruction:
4852          */
4853         hypercall[0] = 0x0f;
4854         hypercall[1] = 0x01;
4855         hypercall[2] = 0xc1;
4856 }
4857
4858 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4859 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4860 {
4861         if (is_guest_mode(vcpu)) {
4862                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4863                 unsigned long orig_val = val;
4864
4865                 /*
4866                  * We get here when L2 changed cr0 in a way that did not change
4867                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4868                  * but did change L0 shadowed bits. So we first calculate the
4869                  * effective cr0 value that L1 would like to write into the
4870                  * hardware. It consists of the L2-owned bits from the new
4871                  * value combined with the L1-owned bits from L1's guest_cr0.
4872                  */
4873                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4874                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4875
4876                 /* TODO: will have to take unrestricted guest mode into
4877                  * account */
4878                 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4879                         return 1;
4880
4881                 if (kvm_set_cr0(vcpu, val))
4882                         return 1;
4883                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4884                 return 0;
4885         } else {
4886                 if (to_vmx(vcpu)->nested.vmxon &&
4887                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4888                         return 1;
4889                 return kvm_set_cr0(vcpu, val);
4890         }
4891 }
4892
4893 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4894 {
4895         if (is_guest_mode(vcpu)) {
4896                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4897                 unsigned long orig_val = val;
4898
4899                 /* analogously to handle_set_cr0 */
4900                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4901                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4902                 if (kvm_set_cr4(vcpu, val))
4903                         return 1;
4904                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4905                 return 0;
4906         } else
4907                 return kvm_set_cr4(vcpu, val);
4908 }
4909
4910 /* called to set cr0 as approriate for clts instruction exit. */
4911 static void handle_clts(struct kvm_vcpu *vcpu)
4912 {
4913         if (is_guest_mode(vcpu)) {
4914                 /*
4915                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4916                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4917                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4918                  */
4919                 vmcs_writel(CR0_READ_SHADOW,
4920                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4921                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4922         } else
4923                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4924 }
4925
4926 static int handle_cr(struct kvm_vcpu *vcpu)
4927 {
4928         unsigned long exit_qualification, val;
4929         int cr;
4930         int reg;
4931         int err;
4932
4933         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4934         cr = exit_qualification & 15;
4935         reg = (exit_qualification >> 8) & 15;
4936         switch ((exit_qualification >> 4) & 3) {
4937         case 0: /* mov to cr */
4938                 val = kvm_register_read(vcpu, reg);
4939                 trace_kvm_cr_write(cr, val);
4940                 switch (cr) {
4941                 case 0:
4942                         err = handle_set_cr0(vcpu, val);
4943                         kvm_complete_insn_gp(vcpu, err);
4944                         return 1;
4945                 case 3:
4946                         err = kvm_set_cr3(vcpu, val);
4947                         kvm_complete_insn_gp(vcpu, err);
4948                         return 1;
4949                 case 4:
4950                         err = handle_set_cr4(vcpu, val);
4951                         kvm_complete_insn_gp(vcpu, err);
4952                         return 1;
4953                 case 8: {
4954                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4955                                 u8 cr8 = kvm_register_read(vcpu, reg);
4956                                 err = kvm_set_cr8(vcpu, cr8);
4957                                 kvm_complete_insn_gp(vcpu, err);
4958                                 if (irqchip_in_kernel(vcpu->kvm))
4959                                         return 1;
4960                                 if (cr8_prev <= cr8)
4961                                         return 1;
4962                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4963                                 return 0;
4964                         }
4965                 }
4966                 break;
4967         case 2: /* clts */
4968                 handle_clts(vcpu);
4969                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4970                 skip_emulated_instruction(vcpu);
4971                 vmx_fpu_activate(vcpu);
4972                 return 1;
4973         case 1: /*mov from cr*/
4974                 switch (cr) {
4975                 case 3:
4976                         val = kvm_read_cr3(vcpu);
4977                         kvm_register_write(vcpu, reg, val);
4978                         trace_kvm_cr_read(cr, val);
4979                         skip_emulated_instruction(vcpu);
4980                         return 1;
4981                 case 8:
4982                         val = kvm_get_cr8(vcpu);
4983                         kvm_register_write(vcpu, reg, val);
4984                         trace_kvm_cr_read(cr, val);
4985                         skip_emulated_instruction(vcpu);
4986                         return 1;
4987                 }
4988                 break;
4989         case 3: /* lmsw */
4990                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4991                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4992                 kvm_lmsw(vcpu, val);
4993
4994                 skip_emulated_instruction(vcpu);
4995                 return 1;
4996         default:
4997                 break;
4998         }
4999         vcpu->run->exit_reason = 0;
5000         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5001                (int)(exit_qualification >> 4) & 3, cr);
5002         return 0;
5003 }
5004
5005 static int handle_dr(struct kvm_vcpu *vcpu)
5006 {
5007         unsigned long exit_qualification;
5008         int dr, reg;
5009
5010         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5011         if (!kvm_require_cpl(vcpu, 0))
5012                 return 1;
5013         dr = vmcs_readl(GUEST_DR7);
5014         if (dr & DR7_GD) {
5015                 /*
5016                  * As the vm-exit takes precedence over the debug trap, we
5017                  * need to emulate the latter, either for the host or the
5018                  * guest debugging itself.
5019                  */
5020                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5021                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5022                         vcpu->run->debug.arch.dr7 = dr;
5023                         vcpu->run->debug.arch.pc =
5024                                 vmcs_readl(GUEST_CS_BASE) +
5025                                 vmcs_readl(GUEST_RIP);
5026                         vcpu->run->debug.arch.exception = DB_VECTOR;
5027                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5028                         return 0;
5029                 } else {
5030                         vcpu->arch.dr7 &= ~DR7_GD;
5031                         vcpu->arch.dr6 |= DR6_BD;
5032                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5033                         kvm_queue_exception(vcpu, DB_VECTOR);
5034                         return 1;
5035                 }
5036         }
5037
5038         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5039         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5040         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5041         if (exit_qualification & TYPE_MOV_FROM_DR) {
5042                 unsigned long val;
5043                 if (!kvm_get_dr(vcpu, dr, &val))
5044                         kvm_register_write(vcpu, reg, val);
5045         } else
5046                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5047         skip_emulated_instruction(vcpu);
5048         return 1;
5049 }
5050
5051 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5052 {
5053         vmcs_writel(GUEST_DR7, val);
5054 }
5055
5056 static int handle_cpuid(struct kvm_vcpu *vcpu)
5057 {
5058         kvm_emulate_cpuid(vcpu);
5059         return 1;
5060 }
5061
5062 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5063 {
5064         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5065         u64 data;
5066
5067         if (vmx_get_msr(vcpu, ecx, &data)) {
5068                 trace_kvm_msr_read_ex(ecx);
5069                 kvm_inject_gp(vcpu, 0);
5070                 return 1;
5071         }
5072
5073         trace_kvm_msr_read(ecx, data);
5074
5075         /* FIXME: handling of bits 32:63 of rax, rdx */
5076         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5077         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5078         skip_emulated_instruction(vcpu);
5079         return 1;
5080 }
5081
5082 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5083 {
5084         struct msr_data msr;
5085         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5086         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5087                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5088
5089         msr.data = data;
5090         msr.index = ecx;
5091         msr.host_initiated = false;
5092         if (vmx_set_msr(vcpu, &msr) != 0) {
5093                 trace_kvm_msr_write_ex(ecx, data);
5094                 kvm_inject_gp(vcpu, 0);
5095                 return 1;
5096         }
5097
5098         trace_kvm_msr_write(ecx, data);
5099         skip_emulated_instruction(vcpu);
5100         return 1;
5101 }
5102
5103 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5104 {
5105         kvm_make_request(KVM_REQ_EVENT, vcpu);
5106         return 1;
5107 }
5108
5109 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5110 {
5111         u32 cpu_based_vm_exec_control;
5112
5113         /* clear pending irq */
5114         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5115         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5116         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5117
5118         kvm_make_request(KVM_REQ_EVENT, vcpu);
5119
5120         ++vcpu->stat.irq_window_exits;
5121
5122         /*
5123          * If the user space waits to inject interrupts, exit as soon as
5124          * possible
5125          */
5126         if (!irqchip_in_kernel(vcpu->kvm) &&
5127             vcpu->run->request_interrupt_window &&
5128             !kvm_cpu_has_interrupt(vcpu)) {
5129                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5130                 return 0;
5131         }
5132         return 1;
5133 }
5134
5135 static int handle_halt(struct kvm_vcpu *vcpu)
5136 {
5137         skip_emulated_instruction(vcpu);
5138         return kvm_emulate_halt(vcpu);
5139 }
5140
5141 static int handle_vmcall(struct kvm_vcpu *vcpu)
5142 {
5143         skip_emulated_instruction(vcpu);
5144         kvm_emulate_hypercall(vcpu);
5145         return 1;
5146 }
5147
5148 static int handle_invd(struct kvm_vcpu *vcpu)
5149 {
5150         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5151 }
5152
5153 static int handle_invlpg(struct kvm_vcpu *vcpu)
5154 {
5155         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5156
5157         kvm_mmu_invlpg(vcpu, exit_qualification);
5158         skip_emulated_instruction(vcpu);
5159         return 1;
5160 }
5161
5162 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5163 {
5164         int err;
5165
5166         err = kvm_rdpmc(vcpu);
5167         kvm_complete_insn_gp(vcpu, err);
5168
5169         return 1;
5170 }
5171
5172 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5173 {
5174         skip_emulated_instruction(vcpu);
5175         kvm_emulate_wbinvd(vcpu);
5176         return 1;
5177 }
5178
5179 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5180 {
5181         u64 new_bv = kvm_read_edx_eax(vcpu);
5182         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5183
5184         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5185                 skip_emulated_instruction(vcpu);
5186         return 1;
5187 }
5188
5189 static int handle_apic_access(struct kvm_vcpu *vcpu)
5190 {
5191         if (likely(fasteoi)) {
5192                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5193                 int access_type, offset;
5194
5195                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5196                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5197                 /*
5198                  * Sane guest uses MOV to write EOI, with written value
5199                  * not cared. So make a short-circuit here by avoiding
5200                  * heavy instruction emulation.
5201                  */
5202                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5203                     (offset == APIC_EOI)) {
5204                         kvm_lapic_set_eoi(vcpu);
5205                         skip_emulated_instruction(vcpu);
5206                         return 1;
5207                 }
5208         }
5209         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5210 }
5211
5212 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5213 {
5214         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5215         int vector = exit_qualification & 0xff;
5216
5217         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5218         kvm_apic_set_eoi_accelerated(vcpu, vector);
5219         return 1;
5220 }
5221
5222 static int handle_apic_write(struct kvm_vcpu *vcpu)
5223 {
5224         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5225         u32 offset = exit_qualification & 0xfff;
5226
5227         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5228         kvm_apic_write_nodecode(vcpu, offset);
5229         return 1;
5230 }
5231
5232 static int handle_task_switch(struct kvm_vcpu *vcpu)
5233 {
5234         struct vcpu_vmx *vmx = to_vmx(vcpu);
5235         unsigned long exit_qualification;
5236         bool has_error_code = false;
5237         u32 error_code = 0;
5238         u16 tss_selector;
5239         int reason, type, idt_v, idt_index;
5240
5241         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5242         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5243         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5244
5245         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5246
5247         reason = (u32)exit_qualification >> 30;
5248         if (reason == TASK_SWITCH_GATE && idt_v) {
5249                 switch (type) {
5250                 case INTR_TYPE_NMI_INTR:
5251                         vcpu->arch.nmi_injected = false;
5252                         vmx_set_nmi_mask(vcpu, true);
5253                         break;
5254                 case INTR_TYPE_EXT_INTR:
5255                 case INTR_TYPE_SOFT_INTR:
5256                         kvm_clear_interrupt_queue(vcpu);
5257                         break;
5258                 case INTR_TYPE_HARD_EXCEPTION:
5259                         if (vmx->idt_vectoring_info &
5260                             VECTORING_INFO_DELIVER_CODE_MASK) {
5261                                 has_error_code = true;
5262                                 error_code =
5263                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5264                         }
5265                         /* fall through */
5266                 case INTR_TYPE_SOFT_EXCEPTION:
5267                         kvm_clear_exception_queue(vcpu);
5268                         break;
5269                 default:
5270                         break;
5271                 }
5272         }
5273         tss_selector = exit_qualification;
5274
5275         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5276                        type != INTR_TYPE_EXT_INTR &&
5277                        type != INTR_TYPE_NMI_INTR))
5278                 skip_emulated_instruction(vcpu);
5279
5280         if (kvm_task_switch(vcpu, tss_selector,
5281                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5282                             has_error_code, error_code) == EMULATE_FAIL) {
5283                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5284                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5285                 vcpu->run->internal.ndata = 0;
5286                 return 0;
5287         }
5288
5289         /* clear all local breakpoint enable flags */
5290         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5291
5292         /*
5293          * TODO: What about debug traps on tss switch?
5294          *       Are we supposed to inject them and update dr6?
5295          */
5296
5297         return 1;
5298 }
5299
5300 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5301 {
5302         unsigned long exit_qualification;
5303         gpa_t gpa;
5304         u32 error_code;
5305         int gla_validity;
5306
5307         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5308
5309         gla_validity = (exit_qualification >> 7) & 0x3;
5310         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5311                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5312                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5313                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5314                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5315                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5316                         (long unsigned int)exit_qualification);
5317                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5318                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5319                 return 0;
5320         }
5321
5322         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5323         trace_kvm_page_fault(gpa, exit_qualification);
5324
5325         /* It is a write fault? */
5326         error_code = exit_qualification & (1U << 1);
5327         /* It is a fetch fault? */
5328         error_code |= (exit_qualification & (1U << 2)) << 2;
5329         /* ept page table is present? */
5330         error_code |= (exit_qualification >> 3) & 0x1;
5331
5332         vcpu->arch.exit_qualification = exit_qualification;
5333
5334         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5335 }
5336
5337 static u64 ept_rsvd_mask(u64 spte, int level)
5338 {
5339         int i;
5340         u64 mask = 0;
5341
5342         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5343                 mask |= (1ULL << i);
5344
5345         if (level > 2)
5346                 /* bits 7:3 reserved */
5347                 mask |= 0xf8;
5348         else if (level == 2) {
5349                 if (spte & (1ULL << 7))
5350                         /* 2MB ref, bits 20:12 reserved */
5351                         mask |= 0x1ff000;
5352                 else
5353                         /* bits 6:3 reserved */
5354                         mask |= 0x78;
5355         }
5356
5357         return mask;
5358 }
5359
5360 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5361                                        int level)
5362 {
5363         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5364
5365         /* 010b (write-only) */
5366         WARN_ON((spte & 0x7) == 0x2);
5367
5368         /* 110b (write/execute) */
5369         WARN_ON((spte & 0x7) == 0x6);
5370
5371         /* 100b (execute-only) and value not supported by logical processor */
5372         if (!cpu_has_vmx_ept_execute_only())
5373                 WARN_ON((spte & 0x7) == 0x4);
5374
5375         /* not 000b */
5376         if ((spte & 0x7)) {
5377                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5378
5379                 if (rsvd_bits != 0) {
5380                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5381                                          __func__, rsvd_bits);
5382                         WARN_ON(1);
5383                 }
5384
5385                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5386                         u64 ept_mem_type = (spte & 0x38) >> 3;
5387
5388                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5389                             ept_mem_type == 7) {
5390                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5391                                                 __func__, ept_mem_type);
5392                                 WARN_ON(1);
5393                         }
5394                 }
5395         }
5396 }
5397
5398 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5399 {
5400         u64 sptes[4];
5401         int nr_sptes, i, ret;
5402         gpa_t gpa;
5403
5404         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5405
5406         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5407         if (likely(ret == RET_MMIO_PF_EMULATE))
5408                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5409                                               EMULATE_DONE;
5410
5411         if (unlikely(ret == RET_MMIO_PF_INVALID))
5412                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5413
5414         if (unlikely(ret == RET_MMIO_PF_RETRY))
5415                 return 1;
5416
5417         /* It is the real ept misconfig */
5418         printk(KERN_ERR "EPT: Misconfiguration.\n");
5419         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5420
5421         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5422
5423         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5424                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5425
5426         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5427         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5428
5429         return 0;
5430 }
5431
5432 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5433 {
5434         u32 cpu_based_vm_exec_control;
5435
5436         /* clear pending NMI */
5437         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5438         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5439         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5440         ++vcpu->stat.nmi_window_exits;
5441         kvm_make_request(KVM_REQ_EVENT, vcpu);
5442
5443         return 1;
5444 }
5445
5446 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5447 {
5448         struct vcpu_vmx *vmx = to_vmx(vcpu);
5449         enum emulation_result err = EMULATE_DONE;
5450         int ret = 1;
5451         u32 cpu_exec_ctrl;
5452         bool intr_window_requested;
5453         unsigned count = 130;
5454
5455         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5456         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5457
5458         while (!guest_state_valid(vcpu) && count-- != 0) {
5459                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5460                         return handle_interrupt_window(&vmx->vcpu);
5461
5462                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5463                         return 1;
5464
5465                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5466
5467                 if (err == EMULATE_USER_EXIT) {
5468                         ret = 0;
5469                         goto out;
5470                 }
5471
5472                 if (err != EMULATE_DONE) {
5473                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5474                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5475                         vcpu->run->internal.ndata = 0;
5476                         return 0;
5477                 }
5478
5479                 if (vcpu->arch.halt_request) {
5480                         vcpu->arch.halt_request = 0;
5481                         ret = kvm_emulate_halt(vcpu);
5482                         goto out;
5483                 }
5484
5485                 if (signal_pending(current))
5486                         goto out;
5487                 if (need_resched())
5488                         schedule();
5489         }
5490
5491         vmx->emulation_required = emulation_required(vcpu);
5492 out:
5493         return ret;
5494 }
5495
5496 /*
5497  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5498  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5499  */
5500 static int handle_pause(struct kvm_vcpu *vcpu)
5501 {
5502         skip_emulated_instruction(vcpu);
5503         kvm_vcpu_on_spin(vcpu);
5504
5505         return 1;
5506 }
5507
5508 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5509 {
5510         kvm_queue_exception(vcpu, UD_VECTOR);
5511         return 1;
5512 }
5513
5514 /*
5515  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5516  * We could reuse a single VMCS for all the L2 guests, but we also want the
5517  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5518  * allows keeping them loaded on the processor, and in the future will allow
5519  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5520  * every entry if they never change.
5521  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5522  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5523  *
5524  * The following functions allocate and free a vmcs02 in this pool.
5525  */
5526
5527 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5528 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5529 {
5530         struct vmcs02_list *item;
5531         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5532                 if (item->vmptr == vmx->nested.current_vmptr) {
5533                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5534                         return &item->vmcs02;
5535                 }
5536
5537         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5538                 /* Recycle the least recently used VMCS. */
5539                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5540                         struct vmcs02_list, list);
5541                 item->vmptr = vmx->nested.current_vmptr;
5542                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5543                 return &item->vmcs02;
5544         }
5545
5546         /* Create a new VMCS */
5547         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5548         if (!item)
5549                 return NULL;
5550         item->vmcs02.vmcs = alloc_vmcs();
5551         if (!item->vmcs02.vmcs) {
5552                 kfree(item);
5553                 return NULL;
5554         }
5555         loaded_vmcs_init(&item->vmcs02);
5556         item->vmptr = vmx->nested.current_vmptr;
5557         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5558         vmx->nested.vmcs02_num++;
5559         return &item->vmcs02;
5560 }
5561
5562 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5563 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5564 {
5565         struct vmcs02_list *item;
5566         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5567                 if (item->vmptr == vmptr) {
5568                         free_loaded_vmcs(&item->vmcs02);
5569                         list_del(&item->list);
5570                         kfree(item);
5571                         vmx->nested.vmcs02_num--;
5572                         return;
5573                 }
5574 }
5575
5576 /*
5577  * Free all VMCSs saved for this vcpu, except the one pointed by
5578  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5579  * currently used, if running L2), and vmcs01 when running L2.
5580  */
5581 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5582 {
5583         struct vmcs02_list *item, *n;
5584         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5585                 if (vmx->loaded_vmcs != &item->vmcs02)
5586                         free_loaded_vmcs(&item->vmcs02);
5587                 list_del(&item->list);
5588                 kfree(item);
5589         }
5590         vmx->nested.vmcs02_num = 0;
5591
5592         if (vmx->loaded_vmcs != &vmx->vmcs01)
5593                 free_loaded_vmcs(&vmx->vmcs01);
5594 }
5595
5596 /*
5597  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5598  * set the success or error code of an emulated VMX instruction, as specified
5599  * by Vol 2B, VMX Instruction Reference, "Conventions".
5600  */
5601 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5602 {
5603         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5604                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5605                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5606 }
5607
5608 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5609 {
5610         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5611                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5612                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5613                         | X86_EFLAGS_CF);
5614 }
5615
5616 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5617                                         u32 vm_instruction_error)
5618 {
5619         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5620                 /*
5621                  * failValid writes the error number to the current VMCS, which
5622                  * can't be done there isn't a current VMCS.
5623                  */
5624                 nested_vmx_failInvalid(vcpu);
5625                 return;
5626         }
5627         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5628                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5629                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5630                         | X86_EFLAGS_ZF);
5631         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5632         /*
5633          * We don't need to force a shadow sync because
5634          * VM_INSTRUCTION_ERROR is not shadowed
5635          */
5636 }
5637
5638 /*
5639  * Emulate the VMXON instruction.
5640  * Currently, we just remember that VMX is active, and do not save or even
5641  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5642  * do not currently need to store anything in that guest-allocated memory
5643  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5644  * argument is different from the VMXON pointer (which the spec says they do).
5645  */
5646 static int handle_vmon(struct kvm_vcpu *vcpu)
5647 {
5648         struct kvm_segment cs;
5649         struct vcpu_vmx *vmx = to_vmx(vcpu);
5650         struct vmcs *shadow_vmcs;
5651         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5652                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5653
5654         /* The Intel VMX Instruction Reference lists a bunch of bits that
5655          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5656          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5657          * Otherwise, we should fail with #UD. We test these now:
5658          */
5659         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5660             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5661             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5662                 kvm_queue_exception(vcpu, UD_VECTOR);
5663                 return 1;
5664         }
5665
5666         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5667         if (is_long_mode(vcpu) && !cs.l) {
5668                 kvm_queue_exception(vcpu, UD_VECTOR);
5669                 return 1;
5670         }
5671
5672         if (vmx_get_cpl(vcpu)) {
5673                 kvm_inject_gp(vcpu, 0);
5674                 return 1;
5675         }
5676         if (vmx->nested.vmxon) {
5677                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5678                 skip_emulated_instruction(vcpu);
5679                 return 1;
5680         }
5681
5682         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5683                         != VMXON_NEEDED_FEATURES) {
5684                 kvm_inject_gp(vcpu, 0);
5685                 return 1;
5686         }
5687
5688         if (enable_shadow_vmcs) {
5689                 shadow_vmcs = alloc_vmcs();
5690                 if (!shadow_vmcs)
5691                         return -ENOMEM;
5692                 /* mark vmcs as shadow */
5693                 shadow_vmcs->revision_id |= (1u << 31);
5694                 /* init shadow vmcs */
5695                 vmcs_clear(shadow_vmcs);
5696                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5697         }
5698
5699         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5700         vmx->nested.vmcs02_num = 0;
5701
5702         vmx->nested.vmxon = true;
5703
5704         skip_emulated_instruction(vcpu);
5705         nested_vmx_succeed(vcpu);
5706         return 1;
5707 }
5708
5709 /*
5710  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5711  * for running VMX instructions (except VMXON, whose prerequisites are
5712  * slightly different). It also specifies what exception to inject otherwise.
5713  */
5714 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5715 {
5716         struct kvm_segment cs;
5717         struct vcpu_vmx *vmx = to_vmx(vcpu);
5718
5719         if (!vmx->nested.vmxon) {
5720                 kvm_queue_exception(vcpu, UD_VECTOR);
5721                 return 0;
5722         }
5723
5724         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5725         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5726             (is_long_mode(vcpu) && !cs.l)) {
5727                 kvm_queue_exception(vcpu, UD_VECTOR);
5728                 return 0;
5729         }
5730
5731         if (vmx_get_cpl(vcpu)) {
5732                 kvm_inject_gp(vcpu, 0);
5733                 return 0;
5734         }
5735
5736         return 1;
5737 }
5738
5739 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5740 {
5741         u32 exec_control;
5742         if (enable_shadow_vmcs) {
5743                 if (vmx->nested.current_vmcs12 != NULL) {
5744                         /* copy to memory all shadowed fields in case
5745                            they were modified */
5746                         copy_shadow_to_vmcs12(vmx);
5747                         vmx->nested.sync_shadow_vmcs = false;
5748                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5749                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5750                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5751                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5752                 }
5753         }
5754         kunmap(vmx->nested.current_vmcs12_page);
5755         nested_release_page(vmx->nested.current_vmcs12_page);
5756 }
5757
5758 /*
5759  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5760  * just stops using VMX.
5761  */
5762 static void free_nested(struct vcpu_vmx *vmx)
5763 {
5764         if (!vmx->nested.vmxon)
5765                 return;
5766         vmx->nested.vmxon = false;
5767         if (vmx->nested.current_vmptr != -1ull) {
5768                 nested_release_vmcs12(vmx);
5769                 vmx->nested.current_vmptr = -1ull;
5770                 vmx->nested.current_vmcs12 = NULL;
5771         }
5772         if (enable_shadow_vmcs)
5773                 free_vmcs(vmx->nested.current_shadow_vmcs);
5774         /* Unpin physical memory we referred to in current vmcs02 */
5775         if (vmx->nested.apic_access_page) {
5776                 nested_release_page(vmx->nested.apic_access_page);
5777                 vmx->nested.apic_access_page = 0;
5778         }
5779
5780         nested_free_all_saved_vmcss(vmx);
5781 }
5782
5783 /* Emulate the VMXOFF instruction */
5784 static int handle_vmoff(struct kvm_vcpu *vcpu)
5785 {
5786         if (!nested_vmx_check_permission(vcpu))
5787                 return 1;
5788         free_nested(to_vmx(vcpu));
5789         skip_emulated_instruction(vcpu);
5790         nested_vmx_succeed(vcpu);
5791         return 1;
5792 }
5793
5794 /*
5795  * Decode the memory-address operand of a vmx instruction, as recorded on an
5796  * exit caused by such an instruction (run by a guest hypervisor).
5797  * On success, returns 0. When the operand is invalid, returns 1 and throws
5798  * #UD or #GP.
5799  */
5800 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5801                                  unsigned long exit_qualification,
5802                                  u32 vmx_instruction_info, gva_t *ret)
5803 {
5804         /*
5805          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5806          * Execution", on an exit, vmx_instruction_info holds most of the
5807          * addressing components of the operand. Only the displacement part
5808          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5809          * For how an actual address is calculated from all these components,
5810          * refer to Vol. 1, "Operand Addressing".
5811          */
5812         int  scaling = vmx_instruction_info & 3;
5813         int  addr_size = (vmx_instruction_info >> 7) & 7;
5814         bool is_reg = vmx_instruction_info & (1u << 10);
5815         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5816         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5817         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5818         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5819         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5820
5821         if (is_reg) {
5822                 kvm_queue_exception(vcpu, UD_VECTOR);
5823                 return 1;
5824         }
5825
5826         /* Addr = segment_base + offset */
5827         /* offset = base + [index * scale] + displacement */
5828         *ret = vmx_get_segment_base(vcpu, seg_reg);
5829         if (base_is_valid)
5830                 *ret += kvm_register_read(vcpu, base_reg);
5831         if (index_is_valid)
5832                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5833         *ret += exit_qualification; /* holds the displacement */
5834
5835         if (addr_size == 1) /* 32 bit */
5836                 *ret &= 0xffffffff;
5837
5838         /*
5839          * TODO: throw #GP (and return 1) in various cases that the VM*
5840          * instructions require it - e.g., offset beyond segment limit,
5841          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5842          * address, and so on. Currently these are not checked.
5843          */
5844         return 0;
5845 }
5846
5847 /* Emulate the VMCLEAR instruction */
5848 static int handle_vmclear(struct kvm_vcpu *vcpu)
5849 {
5850         struct vcpu_vmx *vmx = to_vmx(vcpu);
5851         gva_t gva;
5852         gpa_t vmptr;
5853         struct vmcs12 *vmcs12;
5854         struct page *page;
5855         struct x86_exception e;
5856
5857         if (!nested_vmx_check_permission(vcpu))
5858                 return 1;
5859
5860         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5861                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5862                 return 1;
5863
5864         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5865                                 sizeof(vmptr), &e)) {
5866                 kvm_inject_page_fault(vcpu, &e);
5867                 return 1;
5868         }
5869
5870         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5871                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5872                 skip_emulated_instruction(vcpu);
5873                 return 1;
5874         }
5875
5876         if (vmptr == vmx->nested.current_vmptr) {
5877                 nested_release_vmcs12(vmx);
5878                 vmx->nested.current_vmptr = -1ull;
5879                 vmx->nested.current_vmcs12 = NULL;
5880         }
5881
5882         page = nested_get_page(vcpu, vmptr);
5883         if (page == NULL) {
5884                 /*
5885                  * For accurate processor emulation, VMCLEAR beyond available
5886                  * physical memory should do nothing at all. However, it is
5887                  * possible that a nested vmx bug, not a guest hypervisor bug,
5888                  * resulted in this case, so let's shut down before doing any
5889                  * more damage:
5890                  */
5891                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5892                 return 1;
5893         }
5894         vmcs12 = kmap(page);
5895         vmcs12->launch_state = 0;
5896         kunmap(page);
5897         nested_release_page(page);
5898
5899         nested_free_vmcs02(vmx, vmptr);
5900
5901         skip_emulated_instruction(vcpu);
5902         nested_vmx_succeed(vcpu);
5903         return 1;
5904 }
5905
5906 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5907
5908 /* Emulate the VMLAUNCH instruction */
5909 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5910 {
5911         return nested_vmx_run(vcpu, true);
5912 }
5913
5914 /* Emulate the VMRESUME instruction */
5915 static int handle_vmresume(struct kvm_vcpu *vcpu)
5916 {
5917
5918         return nested_vmx_run(vcpu, false);
5919 }
5920
5921 enum vmcs_field_type {
5922         VMCS_FIELD_TYPE_U16 = 0,
5923         VMCS_FIELD_TYPE_U64 = 1,
5924         VMCS_FIELD_TYPE_U32 = 2,
5925         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5926 };
5927
5928 static inline int vmcs_field_type(unsigned long field)
5929 {
5930         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5931                 return VMCS_FIELD_TYPE_U32;
5932         return (field >> 13) & 0x3 ;
5933 }
5934
5935 static inline int vmcs_field_readonly(unsigned long field)
5936 {
5937         return (((field >> 10) & 0x3) == 1);
5938 }
5939
5940 /*
5941  * Read a vmcs12 field. Since these can have varying lengths and we return
5942  * one type, we chose the biggest type (u64) and zero-extend the return value
5943  * to that size. Note that the caller, handle_vmread, might need to use only
5944  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5945  * 64-bit fields are to be returned).
5946  */
5947 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5948                                         unsigned long field, u64 *ret)
5949 {
5950         short offset = vmcs_field_to_offset(field);
5951         char *p;
5952
5953         if (offset < 0)
5954                 return 0;
5955
5956         p = ((char *)(get_vmcs12(vcpu))) + offset;
5957
5958         switch (vmcs_field_type(field)) {
5959         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5960                 *ret = *((natural_width *)p);
5961                 return 1;
5962         case VMCS_FIELD_TYPE_U16:
5963                 *ret = *((u16 *)p);
5964                 return 1;
5965         case VMCS_FIELD_TYPE_U32:
5966                 *ret = *((u32 *)p);
5967                 return 1;
5968         case VMCS_FIELD_TYPE_U64:
5969                 *ret = *((u64 *)p);
5970                 return 1;
5971         default:
5972                 return 0; /* can never happen. */
5973         }
5974 }
5975
5976
5977 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5978                                     unsigned long field, u64 field_value){
5979         short offset = vmcs_field_to_offset(field);
5980         char *p = ((char *) get_vmcs12(vcpu)) + offset;
5981         if (offset < 0)
5982                 return false;
5983
5984         switch (vmcs_field_type(field)) {
5985         case VMCS_FIELD_TYPE_U16:
5986                 *(u16 *)p = field_value;
5987                 return true;
5988         case VMCS_FIELD_TYPE_U32:
5989                 *(u32 *)p = field_value;
5990                 return true;
5991         case VMCS_FIELD_TYPE_U64:
5992                 *(u64 *)p = field_value;
5993                 return true;
5994         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5995                 *(natural_width *)p = field_value;
5996                 return true;
5997         default:
5998                 return false; /* can never happen. */
5999         }
6000
6001 }
6002
6003 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6004 {
6005         int i;
6006         unsigned long field;
6007         u64 field_value;
6008         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6009         const unsigned long *fields = shadow_read_write_fields;
6010         const int num_fields = max_shadow_read_write_fields;
6011
6012         vmcs_load(shadow_vmcs);
6013
6014         for (i = 0; i < num_fields; i++) {
6015                 field = fields[i];
6016                 switch (vmcs_field_type(field)) {
6017                 case VMCS_FIELD_TYPE_U16:
6018                         field_value = vmcs_read16(field);
6019                         break;
6020                 case VMCS_FIELD_TYPE_U32:
6021                         field_value = vmcs_read32(field);
6022                         break;
6023                 case VMCS_FIELD_TYPE_U64:
6024                         field_value = vmcs_read64(field);
6025                         break;
6026                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6027                         field_value = vmcs_readl(field);
6028                         break;
6029                 }
6030                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6031         }
6032
6033         vmcs_clear(shadow_vmcs);
6034         vmcs_load(vmx->loaded_vmcs->vmcs);
6035 }
6036
6037 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6038 {
6039         const unsigned long *fields[] = {
6040                 shadow_read_write_fields,
6041                 shadow_read_only_fields
6042         };
6043         const int max_fields[] = {
6044                 max_shadow_read_write_fields,
6045                 max_shadow_read_only_fields
6046         };
6047         int i, q;
6048         unsigned long field;
6049         u64 field_value = 0;
6050         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6051
6052         vmcs_load(shadow_vmcs);
6053
6054         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6055                 for (i = 0; i < max_fields[q]; i++) {
6056                         field = fields[q][i];
6057                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6058
6059                         switch (vmcs_field_type(field)) {
6060                         case VMCS_FIELD_TYPE_U16:
6061                                 vmcs_write16(field, (u16)field_value);
6062                                 break;
6063                         case VMCS_FIELD_TYPE_U32:
6064                                 vmcs_write32(field, (u32)field_value);
6065                                 break;
6066                         case VMCS_FIELD_TYPE_U64:
6067                                 vmcs_write64(field, (u64)field_value);
6068                                 break;
6069                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6070                                 vmcs_writel(field, (long)field_value);
6071                                 break;
6072                         }
6073                 }
6074         }
6075
6076         vmcs_clear(shadow_vmcs);
6077         vmcs_load(vmx->loaded_vmcs->vmcs);
6078 }
6079
6080 /*
6081  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6082  * used before) all generate the same failure when it is missing.
6083  */
6084 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6085 {
6086         struct vcpu_vmx *vmx = to_vmx(vcpu);
6087         if (vmx->nested.current_vmptr == -1ull) {
6088                 nested_vmx_failInvalid(vcpu);
6089                 skip_emulated_instruction(vcpu);
6090                 return 0;
6091         }
6092         return 1;
6093 }
6094
6095 static int handle_vmread(struct kvm_vcpu *vcpu)
6096 {
6097         unsigned long field;
6098         u64 field_value;
6099         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6100         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6101         gva_t gva = 0;
6102
6103         if (!nested_vmx_check_permission(vcpu) ||
6104             !nested_vmx_check_vmcs12(vcpu))
6105                 return 1;
6106
6107         /* Decode instruction info and find the field to read */
6108         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6109         /* Read the field, zero-extended to a u64 field_value */
6110         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6111                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6112                 skip_emulated_instruction(vcpu);
6113                 return 1;
6114         }
6115         /*
6116          * Now copy part of this value to register or memory, as requested.
6117          * Note that the number of bits actually copied is 32 or 64 depending
6118          * on the guest's mode (32 or 64 bit), not on the given field's length.
6119          */
6120         if (vmx_instruction_info & (1u << 10)) {
6121                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6122                         field_value);
6123         } else {
6124                 if (get_vmx_mem_address(vcpu, exit_qualification,
6125                                 vmx_instruction_info, &gva))
6126                         return 1;
6127                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6128                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6129                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6130         }
6131
6132         nested_vmx_succeed(vcpu);
6133         skip_emulated_instruction(vcpu);
6134         return 1;
6135 }
6136
6137
6138 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6139 {
6140         unsigned long field;
6141         gva_t gva;
6142         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6143         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6144         /* The value to write might be 32 or 64 bits, depending on L1's long
6145          * mode, and eventually we need to write that into a field of several
6146          * possible lengths. The code below first zero-extends the value to 64
6147          * bit (field_value), and then copies only the approriate number of
6148          * bits into the vmcs12 field.
6149          */
6150         u64 field_value = 0;
6151         struct x86_exception e;
6152
6153         if (!nested_vmx_check_permission(vcpu) ||
6154             !nested_vmx_check_vmcs12(vcpu))
6155                 return 1;
6156
6157         if (vmx_instruction_info & (1u << 10))
6158                 field_value = kvm_register_read(vcpu,
6159                         (((vmx_instruction_info) >> 3) & 0xf));
6160         else {
6161                 if (get_vmx_mem_address(vcpu, exit_qualification,
6162                                 vmx_instruction_info, &gva))
6163                         return 1;
6164                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6165                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6166                         kvm_inject_page_fault(vcpu, &e);
6167                         return 1;
6168                 }
6169         }
6170
6171
6172         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6173         if (vmcs_field_readonly(field)) {
6174                 nested_vmx_failValid(vcpu,
6175                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6176                 skip_emulated_instruction(vcpu);
6177                 return 1;
6178         }
6179
6180         if (!vmcs12_write_any(vcpu, field, field_value)) {
6181                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6182                 skip_emulated_instruction(vcpu);
6183                 return 1;
6184         }
6185
6186         nested_vmx_succeed(vcpu);
6187         skip_emulated_instruction(vcpu);
6188         return 1;
6189 }
6190
6191 /* Emulate the VMPTRLD instruction */
6192 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6193 {
6194         struct vcpu_vmx *vmx = to_vmx(vcpu);
6195         gva_t gva;
6196         gpa_t vmptr;
6197         struct x86_exception e;
6198         u32 exec_control;
6199
6200         if (!nested_vmx_check_permission(vcpu))
6201                 return 1;
6202
6203         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6204                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6205                 return 1;
6206
6207         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6208                                 sizeof(vmptr), &e)) {
6209                 kvm_inject_page_fault(vcpu, &e);
6210                 return 1;
6211         }
6212
6213         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6214                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6215                 skip_emulated_instruction(vcpu);
6216                 return 1;
6217         }
6218
6219         if (vmx->nested.current_vmptr != vmptr) {
6220                 struct vmcs12 *new_vmcs12;
6221                 struct page *page;
6222                 page = nested_get_page(vcpu, vmptr);
6223                 if (page == NULL) {
6224                         nested_vmx_failInvalid(vcpu);
6225                         skip_emulated_instruction(vcpu);
6226                         return 1;
6227                 }
6228                 new_vmcs12 = kmap(page);
6229                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6230                         kunmap(page);
6231                         nested_release_page_clean(page);
6232                         nested_vmx_failValid(vcpu,
6233                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6234                         skip_emulated_instruction(vcpu);
6235                         return 1;
6236                 }
6237                 if (vmx->nested.current_vmptr != -1ull)
6238                         nested_release_vmcs12(vmx);
6239
6240                 vmx->nested.current_vmptr = vmptr;
6241                 vmx->nested.current_vmcs12 = new_vmcs12;
6242                 vmx->nested.current_vmcs12_page = page;
6243                 if (enable_shadow_vmcs) {
6244                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6245                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6246                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6247                         vmcs_write64(VMCS_LINK_POINTER,
6248                                      __pa(vmx->nested.current_shadow_vmcs));
6249                         vmx->nested.sync_shadow_vmcs = true;
6250                 }
6251         }
6252
6253         nested_vmx_succeed(vcpu);
6254         skip_emulated_instruction(vcpu);
6255         return 1;
6256 }
6257
6258 /* Emulate the VMPTRST instruction */
6259 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6260 {
6261         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6262         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6263         gva_t vmcs_gva;
6264         struct x86_exception e;
6265
6266         if (!nested_vmx_check_permission(vcpu))
6267                 return 1;
6268
6269         if (get_vmx_mem_address(vcpu, exit_qualification,
6270                         vmx_instruction_info, &vmcs_gva))
6271                 return 1;
6272         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6273         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6274                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6275                                  sizeof(u64), &e)) {
6276                 kvm_inject_page_fault(vcpu, &e);
6277                 return 1;
6278         }
6279         nested_vmx_succeed(vcpu);
6280         skip_emulated_instruction(vcpu);
6281         return 1;
6282 }
6283
6284 /* Emulate the INVEPT instruction */
6285 static int handle_invept(struct kvm_vcpu *vcpu)
6286 {
6287         u32 vmx_instruction_info, types;
6288         unsigned long type;
6289         gva_t gva;
6290         struct x86_exception e;
6291         struct {
6292                 u64 eptp, gpa;
6293         } operand;
6294         u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6295
6296         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6297             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6298                 kvm_queue_exception(vcpu, UD_VECTOR);
6299                 return 1;
6300         }
6301
6302         if (!nested_vmx_check_permission(vcpu))
6303                 return 1;
6304
6305         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6306                 kvm_queue_exception(vcpu, UD_VECTOR);
6307                 return 1;
6308         }
6309
6310         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6311         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6312
6313         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6314
6315         if (!(types & (1UL << type))) {
6316                 nested_vmx_failValid(vcpu,
6317                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6318                 return 1;
6319         }
6320
6321         /* According to the Intel VMX instruction reference, the memory
6322          * operand is read even if it isn't needed (e.g., for type==global)
6323          */
6324         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6325                         vmx_instruction_info, &gva))
6326                 return 1;
6327         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6328                                 sizeof(operand), &e)) {
6329                 kvm_inject_page_fault(vcpu, &e);
6330                 return 1;
6331         }
6332
6333         switch (type) {
6334         case VMX_EPT_EXTENT_CONTEXT:
6335                 if ((operand.eptp & eptp_mask) !=
6336                                 (nested_ept_get_cr3(vcpu) & eptp_mask))
6337                         break;
6338         case VMX_EPT_EXTENT_GLOBAL:
6339                 kvm_mmu_sync_roots(vcpu);
6340                 kvm_mmu_flush_tlb(vcpu);
6341                 nested_vmx_succeed(vcpu);
6342                 break;
6343         default:
6344                 BUG_ON(1);
6345                 break;
6346         }
6347
6348         skip_emulated_instruction(vcpu);
6349         return 1;
6350 }
6351
6352 /*
6353  * The exit handlers return 1 if the exit was handled fully and guest execution
6354  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6355  * to be done to userspace and return 0.
6356  */
6357 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6358         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6359         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6360         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6361         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6362         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6363         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6364         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6365         [EXIT_REASON_CPUID]                   = handle_cpuid,
6366         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6367         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6368         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6369         [EXIT_REASON_HLT]                     = handle_halt,
6370         [EXIT_REASON_INVD]                    = handle_invd,
6371         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6372         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6373         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6374         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6375         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6376         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6377         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6378         [EXIT_REASON_VMREAD]                  = handle_vmread,
6379         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6380         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6381         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6382         [EXIT_REASON_VMON]                    = handle_vmon,
6383         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6384         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6385         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6386         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6387         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6388         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6389         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6390         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6391         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6392         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6393         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6394         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6395         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6396         [EXIT_REASON_INVEPT]                  = handle_invept,
6397 };
6398
6399 static const int kvm_vmx_max_exit_handlers =
6400         ARRAY_SIZE(kvm_vmx_exit_handlers);
6401
6402 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6403                                        struct vmcs12 *vmcs12)
6404 {
6405         unsigned long exit_qualification;
6406         gpa_t bitmap, last_bitmap;
6407         unsigned int port;
6408         int size;
6409         u8 b;
6410
6411         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6412                 return 1;
6413
6414         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6415                 return 0;
6416
6417         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6418
6419         port = exit_qualification >> 16;
6420         size = (exit_qualification & 7) + 1;
6421
6422         last_bitmap = (gpa_t)-1;
6423         b = -1;
6424
6425         while (size > 0) {
6426                 if (port < 0x8000)
6427                         bitmap = vmcs12->io_bitmap_a;
6428                 else if (port < 0x10000)
6429                         bitmap = vmcs12->io_bitmap_b;
6430                 else
6431                         return 1;
6432                 bitmap += (port & 0x7fff) / 8;
6433
6434                 if (last_bitmap != bitmap)
6435                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6436                                 return 1;
6437                 if (b & (1 << (port & 7)))
6438                         return 1;
6439
6440                 port++;
6441                 size--;
6442                 last_bitmap = bitmap;
6443         }
6444
6445         return 0;
6446 }
6447
6448 /*
6449  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6450  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6451  * disinterest in the current event (read or write a specific MSR) by using an
6452  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6453  */
6454 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6455         struct vmcs12 *vmcs12, u32 exit_reason)
6456 {
6457         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6458         gpa_t bitmap;
6459
6460         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6461                 return 1;
6462
6463         /*
6464          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6465          * for the four combinations of read/write and low/high MSR numbers.
6466          * First we need to figure out which of the four to use:
6467          */
6468         bitmap = vmcs12->msr_bitmap;
6469         if (exit_reason == EXIT_REASON_MSR_WRITE)
6470                 bitmap += 2048;
6471         if (msr_index >= 0xc0000000) {
6472                 msr_index -= 0xc0000000;
6473                 bitmap += 1024;
6474         }
6475
6476         /* Then read the msr_index'th bit from this bitmap: */
6477         if (msr_index < 1024*8) {
6478                 unsigned char b;
6479                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6480                         return 1;
6481                 return 1 & (b >> (msr_index & 7));
6482         } else
6483                 return 1; /* let L1 handle the wrong parameter */
6484 }
6485
6486 /*
6487  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6488  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6489  * intercept (via guest_host_mask etc.) the current event.
6490  */
6491 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6492         struct vmcs12 *vmcs12)
6493 {
6494         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6495         int cr = exit_qualification & 15;
6496         int reg = (exit_qualification >> 8) & 15;
6497         unsigned long val = kvm_register_read(vcpu, reg);
6498
6499         switch ((exit_qualification >> 4) & 3) {
6500         case 0: /* mov to cr */
6501                 switch (cr) {
6502                 case 0:
6503                         if (vmcs12->cr0_guest_host_mask &
6504                             (val ^ vmcs12->cr0_read_shadow))
6505                                 return 1;
6506                         break;
6507                 case 3:
6508                         if ((vmcs12->cr3_target_count >= 1 &&
6509                                         vmcs12->cr3_target_value0 == val) ||
6510                                 (vmcs12->cr3_target_count >= 2 &&
6511                                         vmcs12->cr3_target_value1 == val) ||
6512                                 (vmcs12->cr3_target_count >= 3 &&
6513                                         vmcs12->cr3_target_value2 == val) ||
6514                                 (vmcs12->cr3_target_count >= 4 &&
6515                                         vmcs12->cr3_target_value3 == val))
6516                                 return 0;
6517                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6518                                 return 1;
6519                         break;
6520                 case 4:
6521                         if (vmcs12->cr4_guest_host_mask &
6522                             (vmcs12->cr4_read_shadow ^ val))
6523                                 return 1;
6524                         break;
6525                 case 8:
6526                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6527                                 return 1;
6528                         break;
6529                 }
6530                 break;
6531         case 2: /* clts */
6532                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6533                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6534                         return 1;
6535                 break;
6536         case 1: /* mov from cr */
6537                 switch (cr) {
6538                 case 3:
6539                         if (vmcs12->cpu_based_vm_exec_control &
6540                             CPU_BASED_CR3_STORE_EXITING)
6541                                 return 1;
6542                         break;
6543                 case 8:
6544                         if (vmcs12->cpu_based_vm_exec_control &
6545                             CPU_BASED_CR8_STORE_EXITING)
6546                                 return 1;
6547                         break;
6548                 }
6549                 break;
6550         case 3: /* lmsw */
6551                 /*
6552                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6553                  * cr0. Other attempted changes are ignored, with no exit.
6554                  */
6555                 if (vmcs12->cr0_guest_host_mask & 0xe &
6556                     (val ^ vmcs12->cr0_read_shadow))
6557                         return 1;
6558                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6559                     !(vmcs12->cr0_read_shadow & 0x1) &&
6560                     (val & 0x1))
6561                         return 1;
6562                 break;
6563         }
6564         return 0;
6565 }
6566
6567 /*
6568  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6569  * should handle it ourselves in L0 (and then continue L2). Only call this
6570  * when in is_guest_mode (L2).
6571  */
6572 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6573 {
6574         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6575         struct vcpu_vmx *vmx = to_vmx(vcpu);
6576         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6577         u32 exit_reason = vmx->exit_reason;
6578
6579         if (vmx->nested.nested_run_pending)
6580                 return 0;
6581
6582         if (unlikely(vmx->fail)) {
6583                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6584                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6585                 return 1;
6586         }
6587
6588         switch (exit_reason) {
6589         case EXIT_REASON_EXCEPTION_NMI:
6590                 if (!is_exception(intr_info))
6591                         return 0;
6592                 else if (is_page_fault(intr_info))
6593                         return enable_ept;
6594                 return vmcs12->exception_bitmap &
6595                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6596         case EXIT_REASON_EXTERNAL_INTERRUPT:
6597                 return 0;
6598         case EXIT_REASON_TRIPLE_FAULT:
6599                 return 1;
6600         case EXIT_REASON_PENDING_INTERRUPT:
6601                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6602         case EXIT_REASON_NMI_WINDOW:
6603                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6604         case EXIT_REASON_TASK_SWITCH:
6605                 return 1;
6606         case EXIT_REASON_CPUID:
6607                 return 1;
6608         case EXIT_REASON_HLT:
6609                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6610         case EXIT_REASON_INVD:
6611                 return 1;
6612         case EXIT_REASON_INVLPG:
6613                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6614         case EXIT_REASON_RDPMC:
6615                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6616         case EXIT_REASON_RDTSC:
6617                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6618         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6619         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6620         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6621         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6622         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6623         case EXIT_REASON_INVEPT:
6624                 /*
6625                  * VMX instructions trap unconditionally. This allows L1 to
6626                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6627                  */
6628                 return 1;
6629         case EXIT_REASON_CR_ACCESS:
6630                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6631         case EXIT_REASON_DR_ACCESS:
6632                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6633         case EXIT_REASON_IO_INSTRUCTION:
6634                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6635         case EXIT_REASON_MSR_READ:
6636         case EXIT_REASON_MSR_WRITE:
6637                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6638         case EXIT_REASON_INVALID_STATE:
6639                 return 1;
6640         case EXIT_REASON_MWAIT_INSTRUCTION:
6641                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6642         case EXIT_REASON_MONITOR_INSTRUCTION:
6643                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6644         case EXIT_REASON_PAUSE_INSTRUCTION:
6645                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6646                         nested_cpu_has2(vmcs12,
6647                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6648         case EXIT_REASON_MCE_DURING_VMENTRY:
6649                 return 0;
6650         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6651                 return 1;
6652         case EXIT_REASON_APIC_ACCESS:
6653                 return nested_cpu_has2(vmcs12,
6654                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6655         case EXIT_REASON_EPT_VIOLATION:
6656         case EXIT_REASON_EPT_MISCONFIG:
6657                 return 0;
6658         case EXIT_REASON_PREEMPTION_TIMER:
6659                 return vmcs12->pin_based_vm_exec_control &
6660                         PIN_BASED_VMX_PREEMPTION_TIMER;
6661         case EXIT_REASON_WBINVD:
6662                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6663         case EXIT_REASON_XSETBV:
6664                 return 1;
6665         default:
6666                 return 1;
6667         }
6668 }
6669
6670 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6671 {
6672         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6673         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6674 }
6675
6676 /*
6677  * The guest has exited.  See if we can fix it or if we need userspace
6678  * assistance.
6679  */
6680 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6681 {
6682         struct vcpu_vmx *vmx = to_vmx(vcpu);
6683         u32 exit_reason = vmx->exit_reason;
6684         u32 vectoring_info = vmx->idt_vectoring_info;
6685
6686         /* If guest state is invalid, start emulating */
6687         if (vmx->emulation_required)
6688                 return handle_invalid_guest_state(vcpu);
6689
6690         /*
6691          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6692          * we did not inject a still-pending event to L1 now because of
6693          * nested_run_pending, we need to re-enable this bit.
6694          */
6695         if (vmx->nested.nested_run_pending)
6696                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6697
6698         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6699             exit_reason == EXIT_REASON_VMRESUME))
6700                 vmx->nested.nested_run_pending = 1;
6701         else
6702                 vmx->nested.nested_run_pending = 0;
6703
6704         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6705                 nested_vmx_vmexit(vcpu);
6706                 return 1;
6707         }
6708
6709         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6710                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6711                 vcpu->run->fail_entry.hardware_entry_failure_reason
6712                         = exit_reason;
6713                 return 0;
6714         }
6715
6716         if (unlikely(vmx->fail)) {
6717                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6718                 vcpu->run->fail_entry.hardware_entry_failure_reason
6719                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6720                 return 0;
6721         }
6722
6723         /*
6724          * Note:
6725          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6726          * delivery event since it indicates guest is accessing MMIO.
6727          * The vm-exit can be triggered again after return to guest that
6728          * will cause infinite loop.
6729          */
6730         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6731                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6732                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6733                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6734                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6735                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6736                 vcpu->run->internal.ndata = 2;
6737                 vcpu->run->internal.data[0] = vectoring_info;
6738                 vcpu->run->internal.data[1] = exit_reason;
6739                 return 0;
6740         }
6741
6742         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6743             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6744                                         get_vmcs12(vcpu), vcpu)))) {
6745                 if (vmx_interrupt_allowed(vcpu)) {
6746                         vmx->soft_vnmi_blocked = 0;
6747                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6748                            vcpu->arch.nmi_pending) {
6749                         /*
6750                          * This CPU don't support us in finding the end of an
6751                          * NMI-blocked window if the guest runs with IRQs
6752                          * disabled. So we pull the trigger after 1 s of
6753                          * futile waiting, but inform the user about this.
6754                          */
6755                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6756                                "state on VCPU %d after 1 s timeout\n",
6757                                __func__, vcpu->vcpu_id);
6758                         vmx->soft_vnmi_blocked = 0;
6759                 }
6760         }
6761
6762         if (exit_reason < kvm_vmx_max_exit_handlers
6763             && kvm_vmx_exit_handlers[exit_reason])
6764                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6765         else {
6766                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6767                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6768         }
6769         return 0;
6770 }
6771
6772 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6773 {
6774         if (irr == -1 || tpr < irr) {
6775                 vmcs_write32(TPR_THRESHOLD, 0);
6776                 return;
6777         }
6778
6779         vmcs_write32(TPR_THRESHOLD, irr);
6780 }
6781
6782 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6783 {
6784         u32 sec_exec_control;
6785
6786         /*
6787          * There is not point to enable virtualize x2apic without enable
6788          * apicv
6789          */
6790         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6791                                 !vmx_vm_has_apicv(vcpu->kvm))
6792                 return;
6793
6794         if (!vm_need_tpr_shadow(vcpu->kvm))
6795                 return;
6796
6797         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6798
6799         if (set) {
6800                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6801                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6802         } else {
6803                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6804                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6805         }
6806         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6807
6808         vmx_set_msr_bitmap(vcpu);
6809 }
6810
6811 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6812 {
6813         u16 status;
6814         u8 old;
6815
6816         if (!vmx_vm_has_apicv(kvm))
6817                 return;
6818
6819         if (isr == -1)
6820                 isr = 0;
6821
6822         status = vmcs_read16(GUEST_INTR_STATUS);
6823         old = status >> 8;
6824         if (isr != old) {
6825                 status &= 0xff;
6826                 status |= isr << 8;
6827                 vmcs_write16(GUEST_INTR_STATUS, status);
6828         }
6829 }
6830
6831 static void vmx_set_rvi(int vector)
6832 {
6833         u16 status;
6834         u8 old;
6835
6836         status = vmcs_read16(GUEST_INTR_STATUS);
6837         old = (u8)status & 0xff;
6838         if ((u8)vector != old) {
6839                 status &= ~0xff;
6840                 status |= (u8)vector;
6841                 vmcs_write16(GUEST_INTR_STATUS, status);
6842         }
6843 }
6844
6845 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6846 {
6847         if (max_irr == -1)
6848                 return;
6849
6850         vmx_set_rvi(max_irr);
6851 }
6852
6853 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6854 {
6855         if (!vmx_vm_has_apicv(vcpu->kvm))
6856                 return;
6857
6858         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6859         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6860         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6861         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6862 }
6863
6864 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6865 {
6866         u32 exit_intr_info;
6867
6868         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6869               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6870                 return;
6871
6872         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6873         exit_intr_info = vmx->exit_intr_info;
6874
6875         /* Handle machine checks before interrupts are enabled */
6876         if (is_machine_check(exit_intr_info))
6877                 kvm_machine_check();
6878
6879         /* We need to handle NMIs before interrupts are enabled */
6880         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6881             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6882                 kvm_before_handle_nmi(&vmx->vcpu);
6883                 asm("int $2");
6884                 kvm_after_handle_nmi(&vmx->vcpu);
6885         }
6886 }
6887
6888 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6889 {
6890         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6891
6892         /*
6893          * If external interrupt exists, IF bit is set in rflags/eflags on the
6894          * interrupt stack frame, and interrupt will be enabled on a return
6895          * from interrupt handler.
6896          */
6897         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6898                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6899                 unsigned int vector;
6900                 unsigned long entry;
6901                 gate_desc *desc;
6902                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6903 #ifdef CONFIG_X86_64
6904                 unsigned long tmp;
6905 #endif
6906
6907                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6908                 desc = (gate_desc *)vmx->host_idt_base + vector;
6909                 entry = gate_offset(*desc);
6910                 asm volatile(
6911 #ifdef CONFIG_X86_64
6912                         "mov %%" _ASM_SP ", %[sp]\n\t"
6913                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6914                         "push $%c[ss]\n\t"
6915                         "push %[sp]\n\t"
6916 #endif
6917                         "pushf\n\t"
6918                         "orl $0x200, (%%" _ASM_SP ")\n\t"
6919                         __ASM_SIZE(push) " $%c[cs]\n\t"
6920                         "call *%[entry]\n\t"
6921                         :
6922 #ifdef CONFIG_X86_64
6923                         [sp]"=&r"(tmp)
6924 #endif
6925                         :
6926                         [entry]"r"(entry),
6927                         [ss]"i"(__KERNEL_DS),
6928                         [cs]"i"(__KERNEL_CS)
6929                         );
6930         } else
6931                 local_irq_enable();
6932 }
6933
6934 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6935 {
6936         u32 exit_intr_info;
6937         bool unblock_nmi;
6938         u8 vector;
6939         bool idtv_info_valid;
6940
6941         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6942
6943         if (cpu_has_virtual_nmis()) {
6944                 if (vmx->nmi_known_unmasked)
6945                         return;
6946                 /*
6947                  * Can't use vmx->exit_intr_info since we're not sure what
6948                  * the exit reason is.
6949                  */
6950                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6951                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6952                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6953                 /*
6954                  * SDM 3: 27.7.1.2 (September 2008)
6955                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6956                  * a guest IRET fault.
6957                  * SDM 3: 23.2.2 (September 2008)
6958                  * Bit 12 is undefined in any of the following cases:
6959                  *  If the VM exit sets the valid bit in the IDT-vectoring
6960                  *   information field.
6961                  *  If the VM exit is due to a double fault.
6962                  */
6963                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6964                     vector != DF_VECTOR && !idtv_info_valid)
6965                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6966                                       GUEST_INTR_STATE_NMI);
6967                 else
6968                         vmx->nmi_known_unmasked =
6969                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6970                                   & GUEST_INTR_STATE_NMI);
6971         } else if (unlikely(vmx->soft_vnmi_blocked))
6972                 vmx->vnmi_blocked_time +=
6973                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6974 }
6975
6976 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6977                                       u32 idt_vectoring_info,
6978                                       int instr_len_field,
6979                                       int error_code_field)
6980 {
6981         u8 vector;
6982         int type;
6983         bool idtv_info_valid;
6984
6985         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6986
6987         vcpu->arch.nmi_injected = false;
6988         kvm_clear_exception_queue(vcpu);
6989         kvm_clear_interrupt_queue(vcpu);
6990
6991         if (!idtv_info_valid)
6992                 return;
6993
6994         kvm_make_request(KVM_REQ_EVENT, vcpu);
6995
6996         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6997         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6998
6999         switch (type) {
7000         case INTR_TYPE_NMI_INTR:
7001                 vcpu->arch.nmi_injected = true;
7002                 /*
7003                  * SDM 3: 27.7.1.2 (September 2008)
7004                  * Clear bit "block by NMI" before VM entry if a NMI
7005                  * delivery faulted.
7006                  */
7007                 vmx_set_nmi_mask(vcpu, false);
7008                 break;
7009         case INTR_TYPE_SOFT_EXCEPTION:
7010                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7011                 /* fall through */
7012         case INTR_TYPE_HARD_EXCEPTION:
7013                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7014                         u32 err = vmcs_read32(error_code_field);
7015                         kvm_queue_exception_e(vcpu, vector, err);
7016                 } else
7017                         kvm_queue_exception(vcpu, vector);
7018                 break;
7019         case INTR_TYPE_SOFT_INTR:
7020                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7021                 /* fall through */
7022         case INTR_TYPE_EXT_INTR:
7023                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7024                 break;
7025         default:
7026                 break;
7027         }
7028 }
7029
7030 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7031 {
7032         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7033                                   VM_EXIT_INSTRUCTION_LEN,
7034                                   IDT_VECTORING_ERROR_CODE);
7035 }
7036
7037 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7038 {
7039         __vmx_complete_interrupts(vcpu,
7040                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7041                                   VM_ENTRY_INSTRUCTION_LEN,
7042                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7043
7044         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7045 }
7046
7047 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7048 {
7049         int i, nr_msrs;
7050         struct perf_guest_switch_msr *msrs;
7051
7052         msrs = perf_guest_get_msrs(&nr_msrs);
7053
7054         if (!msrs)
7055                 return;
7056
7057         for (i = 0; i < nr_msrs; i++)
7058                 if (msrs[i].host == msrs[i].guest)
7059                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7060                 else
7061                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7062                                         msrs[i].host);
7063 }
7064
7065 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7066 {
7067         struct vcpu_vmx *vmx = to_vmx(vcpu);
7068         unsigned long debugctlmsr;
7069
7070         /* Record the guest's net vcpu time for enforced NMI injections. */
7071         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7072                 vmx->entry_time = ktime_get();
7073
7074         /* Don't enter VMX if guest state is invalid, let the exit handler
7075            start emulation until we arrive back to a valid state */
7076         if (vmx->emulation_required)
7077                 return;
7078
7079         if (vmx->nested.sync_shadow_vmcs) {
7080                 copy_vmcs12_to_shadow(vmx);
7081                 vmx->nested.sync_shadow_vmcs = false;
7082         }
7083
7084         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7085                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7086         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7087                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7088
7089         /* When single-stepping over STI and MOV SS, we must clear the
7090          * corresponding interruptibility bits in the guest state. Otherwise
7091          * vmentry fails as it then expects bit 14 (BS) in pending debug
7092          * exceptions being set, but that's not correct for the guest debugging
7093          * case. */
7094         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7095                 vmx_set_interrupt_shadow(vcpu, 0);
7096
7097         atomic_switch_perf_msrs(vmx);
7098         debugctlmsr = get_debugctlmsr();
7099
7100         vmx->__launched = vmx->loaded_vmcs->launched;
7101         asm(
7102                 /* Store host registers */
7103                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7104                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7105                 "push %%" _ASM_CX " \n\t"
7106                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7107                 "je 1f \n\t"
7108                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7109                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7110                 "1: \n\t"
7111                 /* Reload cr2 if changed */
7112                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7113                 "mov %%cr2, %%" _ASM_DX " \n\t"
7114                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7115                 "je 2f \n\t"
7116                 "mov %%" _ASM_AX", %%cr2 \n\t"
7117                 "2: \n\t"
7118                 /* Check if vmlaunch of vmresume is needed */
7119                 "cmpl $0, %c[launched](%0) \n\t"
7120                 /* Load guest registers.  Don't clobber flags. */
7121                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7122                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7123                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7124                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7125                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7126                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7127 #ifdef CONFIG_X86_64
7128                 "mov %c[r8](%0),  %%r8  \n\t"
7129                 "mov %c[r9](%0),  %%r9  \n\t"
7130                 "mov %c[r10](%0), %%r10 \n\t"
7131                 "mov %c[r11](%0), %%r11 \n\t"
7132                 "mov %c[r12](%0), %%r12 \n\t"
7133                 "mov %c[r13](%0), %%r13 \n\t"
7134                 "mov %c[r14](%0), %%r14 \n\t"
7135                 "mov %c[r15](%0), %%r15 \n\t"
7136 #endif
7137                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7138
7139                 /* Enter guest mode */
7140                 "jne 1f \n\t"
7141                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7142                 "jmp 2f \n\t"
7143                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7144                 "2: "
7145                 /* Save guest registers, load host registers, keep flags */
7146                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7147                 "pop %0 \n\t"
7148                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7149                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7150                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7151                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7152                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7153                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7154                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7155 #ifdef CONFIG_X86_64
7156                 "mov %%r8,  %c[r8](%0) \n\t"
7157                 "mov %%r9,  %c[r9](%0) \n\t"
7158                 "mov %%r10, %c[r10](%0) \n\t"
7159                 "mov %%r11, %c[r11](%0) \n\t"
7160                 "mov %%r12, %c[r12](%0) \n\t"
7161                 "mov %%r13, %c[r13](%0) \n\t"
7162                 "mov %%r14, %c[r14](%0) \n\t"
7163                 "mov %%r15, %c[r15](%0) \n\t"
7164 #endif
7165                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7166                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7167
7168                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7169                 "setbe %c[fail](%0) \n\t"
7170                 ".pushsection .rodata \n\t"
7171                 ".global vmx_return \n\t"
7172                 "vmx_return: " _ASM_PTR " 2b \n\t"
7173                 ".popsection"
7174               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7175                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7176                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7177                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7178                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7179                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7180                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7181                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7182                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7183                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7184                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7185 #ifdef CONFIG_X86_64
7186                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7187                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7188                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7189                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7190                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7191                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7192                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7193                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7194 #endif
7195                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7196                 [wordsize]"i"(sizeof(ulong))
7197               : "cc", "memory"
7198 #ifdef CONFIG_X86_64
7199                 , "rax", "rbx", "rdi", "rsi"
7200                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7201 #else
7202                 , "eax", "ebx", "edi", "esi"
7203 #endif
7204               );
7205
7206         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7207         if (debugctlmsr)
7208                 update_debugctlmsr(debugctlmsr);
7209
7210 #ifndef CONFIG_X86_64
7211         /*
7212          * The sysexit path does not restore ds/es, so we must set them to
7213          * a reasonable value ourselves.
7214          *
7215          * We can't defer this to vmx_load_host_state() since that function
7216          * may be executed in interrupt context, which saves and restore segments
7217          * around it, nullifying its effect.
7218          */
7219         loadsegment(ds, __USER_DS);
7220         loadsegment(es, __USER_DS);
7221 #endif
7222
7223         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7224                                   | (1 << VCPU_EXREG_RFLAGS)
7225                                   | (1 << VCPU_EXREG_CPL)
7226                                   | (1 << VCPU_EXREG_PDPTR)
7227                                   | (1 << VCPU_EXREG_SEGMENTS)
7228                                   | (1 << VCPU_EXREG_CR3));
7229         vcpu->arch.regs_dirty = 0;
7230
7231         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7232
7233         vmx->loaded_vmcs->launched = 1;
7234
7235         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7236         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7237
7238         vmx_complete_atomic_exit(vmx);
7239         vmx_recover_nmi_blocking(vmx);
7240         vmx_complete_interrupts(vmx);
7241 }
7242
7243 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7244 {
7245         struct vcpu_vmx *vmx = to_vmx(vcpu);
7246
7247         free_vpid(vmx);
7248         free_nested(vmx);
7249         free_loaded_vmcs(vmx->loaded_vmcs);
7250         kfree(vmx->guest_msrs);
7251         kvm_vcpu_uninit(vcpu);
7252         kmem_cache_free(kvm_vcpu_cache, vmx);
7253 }
7254
7255 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7256 {
7257         int err;
7258         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7259         int cpu;
7260
7261         if (!vmx)
7262                 return ERR_PTR(-ENOMEM);
7263
7264         allocate_vpid(vmx);
7265
7266         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7267         if (err)
7268                 goto free_vcpu;
7269
7270         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7271         err = -ENOMEM;
7272         if (!vmx->guest_msrs) {
7273                 goto uninit_vcpu;
7274         }
7275
7276         vmx->loaded_vmcs = &vmx->vmcs01;
7277         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7278         if (!vmx->loaded_vmcs->vmcs)
7279                 goto free_msrs;
7280         if (!vmm_exclusive)
7281                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7282         loaded_vmcs_init(vmx->loaded_vmcs);
7283         if (!vmm_exclusive)
7284                 kvm_cpu_vmxoff();
7285
7286         cpu = get_cpu();
7287         vmx_vcpu_load(&vmx->vcpu, cpu);
7288         vmx->vcpu.cpu = cpu;
7289         err = vmx_vcpu_setup(vmx);
7290         vmx_vcpu_put(&vmx->vcpu);
7291         put_cpu();
7292         if (err)
7293                 goto free_vmcs;
7294         if (vm_need_virtualize_apic_accesses(kvm)) {
7295                 err = alloc_apic_access_page(kvm);
7296                 if (err)
7297                         goto free_vmcs;
7298         }
7299
7300         if (enable_ept) {
7301                 if (!kvm->arch.ept_identity_map_addr)
7302                         kvm->arch.ept_identity_map_addr =
7303                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7304                 err = -ENOMEM;
7305                 if (alloc_identity_pagetable(kvm) != 0)
7306                         goto free_vmcs;
7307                 if (!init_rmode_identity_map(kvm))
7308                         goto free_vmcs;
7309         }
7310
7311         vmx->nested.current_vmptr = -1ull;
7312         vmx->nested.current_vmcs12 = NULL;
7313
7314         return &vmx->vcpu;
7315
7316 free_vmcs:
7317         free_loaded_vmcs(vmx->loaded_vmcs);
7318 free_msrs:
7319         kfree(vmx->guest_msrs);
7320 uninit_vcpu:
7321         kvm_vcpu_uninit(&vmx->vcpu);
7322 free_vcpu:
7323         free_vpid(vmx);
7324         kmem_cache_free(kvm_vcpu_cache, vmx);
7325         return ERR_PTR(err);
7326 }
7327
7328 static void __init vmx_check_processor_compat(void *rtn)
7329 {
7330         struct vmcs_config vmcs_conf;
7331
7332         *(int *)rtn = 0;
7333         if (setup_vmcs_config(&vmcs_conf) < 0)
7334                 *(int *)rtn = -EIO;
7335         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7336                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7337                                 smp_processor_id());
7338                 *(int *)rtn = -EIO;
7339         }
7340 }
7341
7342 static int get_ept_level(void)
7343 {
7344         return VMX_EPT_DEFAULT_GAW + 1;
7345 }
7346
7347 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7348 {
7349         u64 ret;
7350
7351         /* For VT-d and EPT combination
7352          * 1. MMIO: always map as UC
7353          * 2. EPT with VT-d:
7354          *   a. VT-d without snooping control feature: can't guarantee the
7355          *      result, try to trust guest.
7356          *   b. VT-d with snooping control feature: snooping control feature of
7357          *      VT-d engine can guarantee the cache correctness. Just set it
7358          *      to WB to keep consistent with host. So the same as item 3.
7359          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7360          *    consistent with host MTRR
7361          */
7362         if (is_mmio)
7363                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7364         else if (vcpu->kvm->arch.iommu_domain &&
7365                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7366                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7367                       VMX_EPT_MT_EPTE_SHIFT;
7368         else
7369                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7370                         | VMX_EPT_IPAT_BIT;
7371
7372         return ret;
7373 }
7374
7375 static int vmx_get_lpage_level(void)
7376 {
7377         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7378                 return PT_DIRECTORY_LEVEL;
7379         else
7380                 /* For shadow and EPT supported 1GB page */
7381                 return PT_PDPE_LEVEL;
7382 }
7383
7384 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7385 {
7386         struct kvm_cpuid_entry2 *best;
7387         struct vcpu_vmx *vmx = to_vmx(vcpu);
7388         u32 exec_control;
7389
7390         vmx->rdtscp_enabled = false;
7391         if (vmx_rdtscp_supported()) {
7392                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7393                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7394                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7395                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7396                                 vmx->rdtscp_enabled = true;
7397                         else {
7398                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7399                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7400                                                 exec_control);
7401                         }
7402                 }
7403         }
7404
7405         /* Exposing INVPCID only when PCID is exposed */
7406         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7407         if (vmx_invpcid_supported() &&
7408             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7409             guest_cpuid_has_pcid(vcpu)) {
7410                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7411                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7412                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7413                              exec_control);
7414         } else {
7415                 if (cpu_has_secondary_exec_ctrls()) {
7416                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7417                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7418                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7419                                      exec_control);
7420                 }
7421                 if (best)
7422                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7423         }
7424 }
7425
7426 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7427 {
7428         if (func == 1 && nested)
7429                 entry->ecx |= bit(X86_FEATURE_VMX);
7430 }
7431
7432 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7433                 struct x86_exception *fault)
7434 {
7435         struct vmcs12 *vmcs12;
7436         nested_vmx_vmexit(vcpu);
7437         vmcs12 = get_vmcs12(vcpu);
7438
7439         if (fault->error_code & PFERR_RSVD_MASK)
7440                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7441         else
7442                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7443         vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7444         vmcs12->guest_physical_address = fault->address;
7445 }
7446
7447 /* Callbacks for nested_ept_init_mmu_context: */
7448
7449 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7450 {
7451         /* return the page table to be shadowed - in our case, EPT12 */
7452         return get_vmcs12(vcpu)->ept_pointer;
7453 }
7454
7455 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7456 {
7457         int r = kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7458                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7459
7460         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7461         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7462         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7463
7464         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7465
7466         return r;
7467 }
7468
7469 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7470 {
7471         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7472 }
7473
7474 /*
7475  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7476  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7477  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7478  * guest in a way that will both be appropriate to L1's requests, and our
7479  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7480  * function also has additional necessary side-effects, like setting various
7481  * vcpu->arch fields.
7482  */
7483 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7484 {
7485         struct vcpu_vmx *vmx = to_vmx(vcpu);
7486         u32 exec_control;
7487
7488         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7489         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7490         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7491         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7492         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7493         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7494         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7495         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7496         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7497         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7498         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7499         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7500         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7501         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7502         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7503         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7504         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7505         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7506         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7507         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7508         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7509         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7510         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7511         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7512         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7513         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7514         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7515         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7516         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7517         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7518         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7519         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7520         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7521         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7522         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7523         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7524
7525         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7526         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7527                 vmcs12->vm_entry_intr_info_field);
7528         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7529                 vmcs12->vm_entry_exception_error_code);
7530         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7531                 vmcs12->vm_entry_instruction_len);
7532         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7533                 vmcs12->guest_interruptibility_info);
7534         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7535         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7536         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7537         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7538                 vmcs12->guest_pending_dbg_exceptions);
7539         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7540         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7541
7542         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7543
7544         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7545                 (vmcs_config.pin_based_exec_ctrl |
7546                  vmcs12->pin_based_vm_exec_control));
7547
7548         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7549                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7550                              vmcs12->vmx_preemption_timer_value);
7551
7552         /*
7553          * Whether page-faults are trapped is determined by a combination of
7554          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7555          * If enable_ept, L0 doesn't care about page faults and we should
7556          * set all of these to L1's desires. However, if !enable_ept, L0 does
7557          * care about (at least some) page faults, and because it is not easy
7558          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7559          * to exit on each and every L2 page fault. This is done by setting
7560          * MASK=MATCH=0 and (see below) EB.PF=1.
7561          * Note that below we don't need special code to set EB.PF beyond the
7562          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7563          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7564          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7565          *
7566          * A problem with this approach (when !enable_ept) is that L1 may be
7567          * injected with more page faults than it asked for. This could have
7568          * caused problems, but in practice existing hypervisors don't care.
7569          * To fix this, we will need to emulate the PFEC checking (on the L1
7570          * page tables), using walk_addr(), when injecting PFs to L1.
7571          */
7572         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7573                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7574         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7575                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7576
7577         if (cpu_has_secondary_exec_ctrls()) {
7578                 u32 exec_control = vmx_secondary_exec_control(vmx);
7579                 if (!vmx->rdtscp_enabled)
7580                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7581                 /* Take the following fields only from vmcs12 */
7582                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7583                 if (nested_cpu_has(vmcs12,
7584                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7585                         exec_control |= vmcs12->secondary_vm_exec_control;
7586
7587                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7588                         /*
7589                          * Translate L1 physical address to host physical
7590                          * address for vmcs02. Keep the page pinned, so this
7591                          * physical address remains valid. We keep a reference
7592                          * to it so we can release it later.
7593                          */
7594                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7595                                 nested_release_page(vmx->nested.apic_access_page);
7596                         vmx->nested.apic_access_page =
7597                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7598                         /*
7599                          * If translation failed, no matter: This feature asks
7600                          * to exit when accessing the given address, and if it
7601                          * can never be accessed, this feature won't do
7602                          * anything anyway.
7603                          */
7604                         if (!vmx->nested.apic_access_page)
7605                                 exec_control &=
7606                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7607                         else
7608                                 vmcs_write64(APIC_ACCESS_ADDR,
7609                                   page_to_phys(vmx->nested.apic_access_page));
7610                 }
7611
7612                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7613         }
7614
7615
7616         /*
7617          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7618          * Some constant fields are set here by vmx_set_constant_host_state().
7619          * Other fields are different per CPU, and will be set later when
7620          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7621          */
7622         vmx_set_constant_host_state(vmx);
7623
7624         /*
7625          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7626          * entry, but only if the current (host) sp changed from the value
7627          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7628          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7629          * here we just force the write to happen on entry.
7630          */
7631         vmx->host_rsp = 0;
7632
7633         exec_control = vmx_exec_control(vmx); /* L0's desires */
7634         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7635         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7636         exec_control &= ~CPU_BASED_TPR_SHADOW;
7637         exec_control |= vmcs12->cpu_based_vm_exec_control;
7638         /*
7639          * Merging of IO and MSR bitmaps not currently supported.
7640          * Rather, exit every time.
7641          */
7642         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7643         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7644         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7645
7646         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7647
7648         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7649          * bitwise-or of what L1 wants to trap for L2, and what we want to
7650          * trap. Note that CR0.TS also needs updating - we do this later.
7651          */
7652         update_exception_bitmap(vcpu);
7653         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7654         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7655
7656         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7657          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7658          * bits are further modified by vmx_set_efer() below.
7659          */
7660         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7661
7662         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7663          * emulated by vmx_set_efer(), below.
7664          */
7665         vmcs_write32(VM_ENTRY_CONTROLS,
7666                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7667                         ~VM_ENTRY_IA32E_MODE) |
7668                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7669
7670         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7671                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7672         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7673                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7674
7675
7676         set_cr4_guest_host_mask(vmx);
7677
7678         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7679                 vmcs_write64(TSC_OFFSET,
7680                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7681         else
7682                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7683
7684         if (enable_vpid) {
7685                 /*
7686                  * Trivially support vpid by letting L2s share their parent
7687                  * L1's vpid. TODO: move to a more elaborate solution, giving
7688                  * each L2 its own vpid and exposing the vpid feature to L1.
7689                  */
7690                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7691                 vmx_flush_tlb(vcpu);
7692         }
7693
7694         if (nested_cpu_has_ept(vmcs12)) {
7695                 kvm_mmu_unload(vcpu);
7696                 nested_ept_init_mmu_context(vcpu);
7697         }
7698
7699         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7700                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7701         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7702                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7703         else
7704                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7705         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7706         vmx_set_efer(vcpu, vcpu->arch.efer);
7707
7708         /*
7709          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7710          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7711          * The CR0_READ_SHADOW is what L2 should have expected to read given
7712          * the specifications by L1; It's not enough to take
7713          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7714          * have more bits than L1 expected.
7715          */
7716         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7717         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7718
7719         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7720         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7721
7722         /* shadow page tables on either EPT or shadow page tables */
7723         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7724         kvm_mmu_reset_context(vcpu);
7725
7726         /*
7727          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7728          */
7729         if (enable_ept) {
7730                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7731                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7732                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7733                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7734         }
7735
7736         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7737         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7738 }
7739
7740 /*
7741  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7742  * for running an L2 nested guest.
7743  */
7744 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7745 {
7746         struct vmcs12 *vmcs12;
7747         struct vcpu_vmx *vmx = to_vmx(vcpu);
7748         int cpu;
7749         struct loaded_vmcs *vmcs02;
7750         bool ia32e;
7751
7752         if (!nested_vmx_check_permission(vcpu) ||
7753             !nested_vmx_check_vmcs12(vcpu))
7754                 return 1;
7755
7756         skip_emulated_instruction(vcpu);
7757         vmcs12 = get_vmcs12(vcpu);
7758
7759         if (enable_shadow_vmcs)
7760                 copy_shadow_to_vmcs12(vmx);
7761
7762         /*
7763          * The nested entry process starts with enforcing various prerequisites
7764          * on vmcs12 as required by the Intel SDM, and act appropriately when
7765          * they fail: As the SDM explains, some conditions should cause the
7766          * instruction to fail, while others will cause the instruction to seem
7767          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7768          * To speed up the normal (success) code path, we should avoid checking
7769          * for misconfigurations which will anyway be caught by the processor
7770          * when using the merged vmcs02.
7771          */
7772         if (vmcs12->launch_state == launch) {
7773                 nested_vmx_failValid(vcpu,
7774                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7775                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7776                 return 1;
7777         }
7778
7779         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7780                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7781                 return 1;
7782         }
7783
7784         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7785                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7786                 /*TODO: Also verify bits beyond physical address width are 0*/
7787                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7788                 return 1;
7789         }
7790
7791         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7792                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7793                 /*TODO: Also verify bits beyond physical address width are 0*/
7794                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7795                 return 1;
7796         }
7797
7798         if (vmcs12->vm_entry_msr_load_count > 0 ||
7799             vmcs12->vm_exit_msr_load_count > 0 ||
7800             vmcs12->vm_exit_msr_store_count > 0) {
7801                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7802                                     __func__);
7803                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7804                 return 1;
7805         }
7806
7807         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7808               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7809             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7810               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7811             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7812               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7813             !vmx_control_verify(vmcs12->vm_exit_controls,
7814               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7815             !vmx_control_verify(vmcs12->vm_entry_controls,
7816               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7817         {
7818                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7819                 return 1;
7820         }
7821
7822         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7823             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7824                 nested_vmx_failValid(vcpu,
7825                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7826                 return 1;
7827         }
7828
7829         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7830             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7831                 nested_vmx_entry_failure(vcpu, vmcs12,
7832                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7833                 return 1;
7834         }
7835         if (vmcs12->vmcs_link_pointer != -1ull) {
7836                 nested_vmx_entry_failure(vcpu, vmcs12,
7837                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7838                 return 1;
7839         }
7840
7841         /*
7842          * If the load IA32_EFER VM-entry control is 1, the following checks
7843          * are performed on the field for the IA32_EFER MSR:
7844          * - Bits reserved in the IA32_EFER MSR must be 0.
7845          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7846          *   the IA-32e mode guest VM-exit control. It must also be identical
7847          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7848          *   CR0.PG) is 1.
7849          */
7850         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7851                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7852                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7853                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7854                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7855                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7856                         nested_vmx_entry_failure(vcpu, vmcs12,
7857                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7858                         return 1;
7859                 }
7860         }
7861
7862         /*
7863          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7864          * IA32_EFER MSR must be 0 in the field for that register. In addition,
7865          * the values of the LMA and LME bits in the field must each be that of
7866          * the host address-space size VM-exit control.
7867          */
7868         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7869                 ia32e = (vmcs12->vm_exit_controls &
7870                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7871                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7872                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7873                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7874                         nested_vmx_entry_failure(vcpu, vmcs12,
7875                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7876                         return 1;
7877                 }
7878         }
7879
7880         /*
7881          * We're finally done with prerequisite checking, and can start with
7882          * the nested entry.
7883          */
7884
7885         vmcs02 = nested_get_current_vmcs02(vmx);
7886         if (!vmcs02)
7887                 return -ENOMEM;
7888
7889         enter_guest_mode(vcpu);
7890
7891         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7892
7893         cpu = get_cpu();
7894         vmx->loaded_vmcs = vmcs02;
7895         vmx_vcpu_put(vcpu);
7896         vmx_vcpu_load(vcpu, cpu);
7897         vcpu->cpu = cpu;
7898         put_cpu();
7899
7900         vmx_segment_cache_clear(vmx);
7901
7902         vmcs12->launch_state = 1;
7903
7904         prepare_vmcs02(vcpu, vmcs12);
7905
7906         /*
7907          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7908          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7909          * returned as far as L1 is concerned. It will only return (and set
7910          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7911          */
7912         return 1;
7913 }
7914
7915 /*
7916  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7917  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7918  * This function returns the new value we should put in vmcs12.guest_cr0.
7919  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7920  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7921  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7922  *     didn't trap the bit, because if L1 did, so would L0).
7923  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7924  *     been modified by L2, and L1 knows it. So just leave the old value of
7925  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7926  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7927  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7928  *     changed these bits, and therefore they need to be updated, but L0
7929  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7930  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7931  */
7932 static inline unsigned long
7933 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7934 {
7935         return
7936         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7937         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7938         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7939                         vcpu->arch.cr0_guest_owned_bits));
7940 }
7941
7942 static inline unsigned long
7943 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7944 {
7945         return
7946         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7947         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7948         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7949                         vcpu->arch.cr4_guest_owned_bits));
7950 }
7951
7952 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7953                                        struct vmcs12 *vmcs12)
7954 {
7955         u32 idt_vectoring;
7956         unsigned int nr;
7957
7958         if (vcpu->arch.exception.pending) {
7959                 nr = vcpu->arch.exception.nr;
7960                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7961
7962                 if (kvm_exception_is_soft(nr)) {
7963                         vmcs12->vm_exit_instruction_len =
7964                                 vcpu->arch.event_exit_inst_len;
7965                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7966                 } else
7967                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7968
7969                 if (vcpu->arch.exception.has_error_code) {
7970                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7971                         vmcs12->idt_vectoring_error_code =
7972                                 vcpu->arch.exception.error_code;
7973                 }
7974
7975                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7976         } else if (vcpu->arch.nmi_pending) {
7977                 vmcs12->idt_vectoring_info_field =
7978                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7979         } else if (vcpu->arch.interrupt.pending) {
7980                 nr = vcpu->arch.interrupt.nr;
7981                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7982
7983                 if (vcpu->arch.interrupt.soft) {
7984                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
7985                         vmcs12->vm_entry_instruction_len =
7986                                 vcpu->arch.event_exit_inst_len;
7987                 } else
7988                         idt_vectoring |= INTR_TYPE_EXT_INTR;
7989
7990                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7991         }
7992 }
7993
7994 /*
7995  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7996  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7997  * and this function updates it to reflect the changes to the guest state while
7998  * L2 was running (and perhaps made some exits which were handled directly by L0
7999  * without going back to L1), and to reflect the exit reason.
8000  * Note that we do not have to copy here all VMCS fields, just those that
8001  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8002  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8003  * which already writes to vmcs12 directly.
8004  */
8005 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8006 {
8007         /* update guest state fields: */
8008         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8009         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8010
8011         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8012         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8013         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8014         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8015
8016         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8017         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8018         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8019         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8020         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8021         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8022         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8023         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8024         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8025         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8026         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8027         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8028         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8029         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8030         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8031         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8032         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8033         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8034         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8035         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8036         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8037         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8038         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8039         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8040         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8041         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8042         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8043         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8044         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8045         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8046         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8047         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8048         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8049         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8050         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8051         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8052
8053         vmcs12->guest_interruptibility_info =
8054                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8055         vmcs12->guest_pending_dbg_exceptions =
8056                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8057
8058         /*
8059          * In some cases (usually, nested EPT), L2 is allowed to change its
8060          * own CR3 without exiting. If it has changed it, we must keep it.
8061          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8062          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8063          *
8064          * Additionally, restore L2's PDPTR to vmcs12.
8065          */
8066         if (enable_ept) {
8067                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8068                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8069                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8070                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8071                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8072         }
8073
8074         vmcs12->vm_entry_controls =
8075                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8076                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8077
8078         /* TODO: These cannot have changed unless we have MSR bitmaps and
8079          * the relevant bit asks not to trap the change */
8080         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8081         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8082                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8083         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8084         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8085         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8086
8087         /* update exit information fields: */
8088
8089         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
8090         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8091
8092         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8093         if ((vmcs12->vm_exit_intr_info &
8094              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8095             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8096                 vmcs12->vm_exit_intr_error_code =
8097                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8098         vmcs12->idt_vectoring_info_field = 0;
8099         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8100         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8101
8102         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8103                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8104                  * instead of reading the real value. */
8105                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8106
8107                 /*
8108                  * Transfer the event that L0 or L1 may wanted to inject into
8109                  * L2 to IDT_VECTORING_INFO_FIELD.
8110                  */
8111                 vmcs12_save_pending_event(vcpu, vmcs12);
8112         }
8113
8114         /*
8115          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8116          * preserved above and would only end up incorrectly in L1.
8117          */
8118         vcpu->arch.nmi_injected = false;
8119         kvm_clear_exception_queue(vcpu);
8120         kvm_clear_interrupt_queue(vcpu);
8121 }
8122
8123 /*
8124  * A part of what we need to when the nested L2 guest exits and we want to
8125  * run its L1 parent, is to reset L1's guest state to the host state specified
8126  * in vmcs12.
8127  * This function is to be called not only on normal nested exit, but also on
8128  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8129  * Failures During or After Loading Guest State").
8130  * This function should be called when the active VMCS is L1's (vmcs01).
8131  */
8132 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8133                                    struct vmcs12 *vmcs12)
8134 {
8135         struct kvm_segment seg;
8136
8137         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8138                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8139         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8140                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8141         else
8142                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8143         vmx_set_efer(vcpu, vcpu->arch.efer);
8144
8145         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8146         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8147         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8148         /*
8149          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8150          * actually changed, because it depends on the current state of
8151          * fpu_active (which may have changed).
8152          * Note that vmx_set_cr0 refers to efer set above.
8153          */
8154         kvm_set_cr0(vcpu, vmcs12->host_cr0);
8155         /*
8156          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8157          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8158          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8159          */
8160         update_exception_bitmap(vcpu);
8161         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8162         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8163
8164         /*
8165          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8166          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8167          */
8168         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8169         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8170
8171         if (nested_cpu_has_ept(vmcs12))
8172                 nested_ept_uninit_mmu_context(vcpu);
8173
8174         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8175         kvm_mmu_reset_context(vcpu);
8176
8177         if (enable_vpid) {
8178                 /*
8179                  * Trivially support vpid by letting L2s share their parent
8180                  * L1's vpid. TODO: move to a more elaborate solution, giving
8181                  * each L2 its own vpid and exposing the vpid feature to L1.
8182                  */
8183                 vmx_flush_tlb(vcpu);
8184         }
8185
8186
8187         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8188         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8189         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8190         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8191         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8192
8193         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8194                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8195         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8196                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8197                         vmcs12->host_ia32_perf_global_ctrl);
8198
8199         /* Set L1 segment info according to Intel SDM
8200             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8201         seg = (struct kvm_segment) {
8202                 .base = 0,
8203                 .limit = 0xFFFFFFFF,
8204                 .selector = vmcs12->host_cs_selector,
8205                 .type = 11,
8206                 .present = 1,
8207                 .s = 1,
8208                 .g = 1
8209         };
8210         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8211                 seg.l = 1;
8212         else
8213                 seg.db = 1;
8214         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8215         seg = (struct kvm_segment) {
8216                 .base = 0,
8217                 .limit = 0xFFFFFFFF,
8218                 .type = 3,
8219                 .present = 1,
8220                 .s = 1,
8221                 .db = 1,
8222                 .g = 1
8223         };
8224         seg.selector = vmcs12->host_ds_selector;
8225         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8226         seg.selector = vmcs12->host_es_selector;
8227         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8228         seg.selector = vmcs12->host_ss_selector;
8229         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8230         seg.selector = vmcs12->host_fs_selector;
8231         seg.base = vmcs12->host_fs_base;
8232         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8233         seg.selector = vmcs12->host_gs_selector;
8234         seg.base = vmcs12->host_gs_base;
8235         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8236         seg = (struct kvm_segment) {
8237                 .base = vmcs12->host_tr_base,
8238                 .limit = 0x67,
8239                 .selector = vmcs12->host_tr_selector,
8240                 .type = 11,
8241                 .present = 1
8242         };
8243         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8244
8245         kvm_set_dr(vcpu, 7, 0x400);
8246         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8247 }
8248
8249 /*
8250  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8251  * and modify vmcs12 to make it see what it would expect to see there if
8252  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8253  */
8254 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8255 {
8256         struct vcpu_vmx *vmx = to_vmx(vcpu);
8257         int cpu;
8258         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8259
8260         /* trying to cancel vmlaunch/vmresume is a bug */
8261         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8262
8263         leave_guest_mode(vcpu);
8264         prepare_vmcs12(vcpu, vmcs12);
8265
8266         cpu = get_cpu();
8267         vmx->loaded_vmcs = &vmx->vmcs01;
8268         vmx_vcpu_put(vcpu);
8269         vmx_vcpu_load(vcpu, cpu);
8270         vcpu->cpu = cpu;
8271         put_cpu();
8272
8273         vmx_segment_cache_clear(vmx);
8274
8275         /* if no vmcs02 cache requested, remove the one we used */
8276         if (VMCS02_POOL_SIZE == 0)
8277                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8278
8279         load_vmcs12_host_state(vcpu, vmcs12);
8280
8281         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8282         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8283
8284         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8285         vmx->host_rsp = 0;
8286
8287         /* Unpin physical memory we referred to in vmcs02 */
8288         if (vmx->nested.apic_access_page) {
8289                 nested_release_page(vmx->nested.apic_access_page);
8290                 vmx->nested.apic_access_page = 0;
8291         }
8292
8293         /*
8294          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8295          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8296          * success or failure flag accordingly.
8297          */
8298         if (unlikely(vmx->fail)) {
8299                 vmx->fail = 0;
8300                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8301         } else
8302                 nested_vmx_succeed(vcpu);
8303         if (enable_shadow_vmcs)
8304                 vmx->nested.sync_shadow_vmcs = true;
8305 }
8306
8307 /*
8308  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8309  * 23.7 "VM-entry failures during or after loading guest state" (this also
8310  * lists the acceptable exit-reason and exit-qualification parameters).
8311  * It should only be called before L2 actually succeeded to run, and when
8312  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8313  */
8314 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8315                         struct vmcs12 *vmcs12,
8316                         u32 reason, unsigned long qualification)
8317 {
8318         load_vmcs12_host_state(vcpu, vmcs12);
8319         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8320         vmcs12->exit_qualification = qualification;
8321         nested_vmx_succeed(vcpu);
8322         if (enable_shadow_vmcs)
8323                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8324 }
8325
8326 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8327                                struct x86_instruction_info *info,
8328                                enum x86_intercept_stage stage)
8329 {
8330         return X86EMUL_CONTINUE;
8331 }
8332
8333 static struct kvm_x86_ops vmx_x86_ops = {
8334         .cpu_has_kvm_support = cpu_has_kvm_support,
8335         .disabled_by_bios = vmx_disabled_by_bios,
8336         .hardware_setup = hardware_setup,
8337         .hardware_unsetup = hardware_unsetup,
8338         .check_processor_compatibility = vmx_check_processor_compat,
8339         .hardware_enable = hardware_enable,
8340         .hardware_disable = hardware_disable,
8341         .cpu_has_accelerated_tpr = report_flexpriority,
8342
8343         .vcpu_create = vmx_create_vcpu,
8344         .vcpu_free = vmx_free_vcpu,
8345         .vcpu_reset = vmx_vcpu_reset,
8346
8347         .prepare_guest_switch = vmx_save_host_state,
8348         .vcpu_load = vmx_vcpu_load,
8349         .vcpu_put = vmx_vcpu_put,
8350
8351         .update_db_bp_intercept = update_exception_bitmap,
8352         .get_msr = vmx_get_msr,
8353         .set_msr = vmx_set_msr,
8354         .get_segment_base = vmx_get_segment_base,
8355         .get_segment = vmx_get_segment,
8356         .set_segment = vmx_set_segment,
8357         .get_cpl = vmx_get_cpl,
8358         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8359         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8360         .decache_cr3 = vmx_decache_cr3,
8361         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8362         .set_cr0 = vmx_set_cr0,
8363         .set_cr3 = vmx_set_cr3,
8364         .set_cr4 = vmx_set_cr4,
8365         .set_efer = vmx_set_efer,
8366         .get_idt = vmx_get_idt,
8367         .set_idt = vmx_set_idt,
8368         .get_gdt = vmx_get_gdt,
8369         .set_gdt = vmx_set_gdt,
8370         .set_dr7 = vmx_set_dr7,
8371         .cache_reg = vmx_cache_reg,
8372         .get_rflags = vmx_get_rflags,
8373         .set_rflags = vmx_set_rflags,
8374         .fpu_activate = vmx_fpu_activate,
8375         .fpu_deactivate = vmx_fpu_deactivate,
8376
8377         .tlb_flush = vmx_flush_tlb,
8378
8379         .run = vmx_vcpu_run,
8380         .handle_exit = vmx_handle_exit,
8381         .skip_emulated_instruction = skip_emulated_instruction,
8382         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8383         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8384         .patch_hypercall = vmx_patch_hypercall,
8385         .set_irq = vmx_inject_irq,
8386         .set_nmi = vmx_inject_nmi,
8387         .queue_exception = vmx_queue_exception,
8388         .cancel_injection = vmx_cancel_injection,
8389         .interrupt_allowed = vmx_interrupt_allowed,
8390         .nmi_allowed = vmx_nmi_allowed,
8391         .get_nmi_mask = vmx_get_nmi_mask,
8392         .set_nmi_mask = vmx_set_nmi_mask,
8393         .enable_nmi_window = enable_nmi_window,
8394         .enable_irq_window = enable_irq_window,
8395         .update_cr8_intercept = update_cr8_intercept,
8396         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8397         .vm_has_apicv = vmx_vm_has_apicv,
8398         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8399         .hwapic_irr_update = vmx_hwapic_irr_update,
8400         .hwapic_isr_update = vmx_hwapic_isr_update,
8401         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8402         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8403
8404         .set_tss_addr = vmx_set_tss_addr,
8405         .get_tdp_level = get_ept_level,
8406         .get_mt_mask = vmx_get_mt_mask,
8407
8408         .get_exit_info = vmx_get_exit_info,
8409
8410         .get_lpage_level = vmx_get_lpage_level,
8411
8412         .cpuid_update = vmx_cpuid_update,
8413
8414         .rdtscp_supported = vmx_rdtscp_supported,
8415         .invpcid_supported = vmx_invpcid_supported,
8416
8417         .set_supported_cpuid = vmx_set_supported_cpuid,
8418
8419         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8420
8421         .set_tsc_khz = vmx_set_tsc_khz,
8422         .read_tsc_offset = vmx_read_tsc_offset,
8423         .write_tsc_offset = vmx_write_tsc_offset,
8424         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8425         .compute_tsc_offset = vmx_compute_tsc_offset,
8426         .read_l1_tsc = vmx_read_l1_tsc,
8427
8428         .set_tdp_cr3 = vmx_set_cr3,
8429
8430         .check_intercept = vmx_check_intercept,
8431         .handle_external_intr = vmx_handle_external_intr,
8432 };
8433
8434 static int __init vmx_init(void)
8435 {
8436         int r, i, msr;
8437
8438         rdmsrl_safe(MSR_EFER, &host_efer);
8439
8440         for (i = 0; i < NR_VMX_MSR; ++i)
8441                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8442
8443         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8444         if (!vmx_io_bitmap_a)
8445                 return -ENOMEM;
8446
8447         r = -ENOMEM;
8448
8449         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8450         if (!vmx_io_bitmap_b)
8451                 goto out;
8452
8453         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8454         if (!vmx_msr_bitmap_legacy)
8455                 goto out1;
8456
8457         vmx_msr_bitmap_legacy_x2apic =
8458                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8459         if (!vmx_msr_bitmap_legacy_x2apic)
8460                 goto out2;
8461
8462         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8463         if (!vmx_msr_bitmap_longmode)
8464                 goto out3;
8465
8466         vmx_msr_bitmap_longmode_x2apic =
8467                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8468         if (!vmx_msr_bitmap_longmode_x2apic)
8469                 goto out4;
8470         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8471         if (!vmx_vmread_bitmap)
8472                 goto out5;
8473
8474         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8475         if (!vmx_vmwrite_bitmap)
8476                 goto out6;
8477
8478         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8479         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8480         /* shadowed read/write fields */
8481         for (i = 0; i < max_shadow_read_write_fields; i++) {
8482                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8483                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8484         }
8485         /* shadowed read only fields */
8486         for (i = 0; i < max_shadow_read_only_fields; i++)
8487                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8488
8489         /*
8490          * Allow direct access to the PC debug port (it is often used for I/O
8491          * delays, but the vmexits simply slow things down).
8492          */
8493         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8494         clear_bit(0x80, vmx_io_bitmap_a);
8495
8496         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8497
8498         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8499         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8500
8501         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8502
8503         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8504                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8505         if (r)
8506                 goto out7;
8507
8508 #ifdef CONFIG_KEXEC
8509         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8510                            crash_vmclear_local_loaded_vmcss);
8511 #endif
8512
8513         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8514         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8515         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8516         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8517         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8518         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8519         memcpy(vmx_msr_bitmap_legacy_x2apic,
8520                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8521         memcpy(vmx_msr_bitmap_longmode_x2apic,
8522                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8523
8524         if (enable_apicv) {
8525                 for (msr = 0x800; msr <= 0x8ff; msr++)
8526                         vmx_disable_intercept_msr_read_x2apic(msr);
8527
8528                 /* According SDM, in x2apic mode, the whole id reg is used.
8529                  * But in KVM, it only use the highest eight bits. Need to
8530                  * intercept it */
8531                 vmx_enable_intercept_msr_read_x2apic(0x802);
8532                 /* TMCCT */
8533                 vmx_enable_intercept_msr_read_x2apic(0x839);
8534                 /* TPR */
8535                 vmx_disable_intercept_msr_write_x2apic(0x808);
8536                 /* EOI */
8537                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8538                 /* SELF-IPI */
8539                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8540         }
8541
8542         if (enable_ept) {
8543                 kvm_mmu_set_mask_ptes(0ull,
8544                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8545                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8546                         0ull, VMX_EPT_EXECUTABLE_MASK);
8547                 ept_set_mmio_spte_mask();
8548                 kvm_enable_tdp();
8549         } else
8550                 kvm_disable_tdp();
8551
8552         return 0;
8553
8554 out7:
8555         free_page((unsigned long)vmx_vmwrite_bitmap);
8556 out6:
8557         free_page((unsigned long)vmx_vmread_bitmap);
8558 out5:
8559         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8560 out4:
8561         free_page((unsigned long)vmx_msr_bitmap_longmode);
8562 out3:
8563         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8564 out2:
8565         free_page((unsigned long)vmx_msr_bitmap_legacy);
8566 out1:
8567         free_page((unsigned long)vmx_io_bitmap_b);
8568 out:
8569         free_page((unsigned long)vmx_io_bitmap_a);
8570         return r;
8571 }
8572
8573 static void __exit vmx_exit(void)
8574 {
8575         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8576         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8577         free_page((unsigned long)vmx_msr_bitmap_legacy);
8578         free_page((unsigned long)vmx_msr_bitmap_longmode);
8579         free_page((unsigned long)vmx_io_bitmap_b);
8580         free_page((unsigned long)vmx_io_bitmap_a);
8581         free_page((unsigned long)vmx_vmwrite_bitmap);
8582         free_page((unsigned long)vmx_vmread_bitmap);
8583
8584 #ifdef CONFIG_KEXEC
8585         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8586         synchronize_rcu();
8587 #endif
8588
8589         kvm_exit();
8590 }
8591
8592 module_init(vmx_init)
8593 module_exit(vmx_exit)