Pileus Git - ~andy/linux/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376         u64 msr_ia32_feature_control;
 377 };
 378
 379 #define POSTED_INTR_ON  0
 380 /* Posted-Interrupt Descriptor */
 381 struct pi_desc {
 382         u32 pir[8];     /* Posted interrupt requested */
 383         u32 control;    /* bit 0 of control is outstanding notification bit */
 384         u32 rsvd[7];
 385 } __aligned(64);
 386
 387 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 388 {
 389         return test_and_set_bit(POSTED_INTR_ON,
 390                         (unsigned long *)&pi_desc->control);
 391 }
 392
 393 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 394 {
 395         return test_and_clear_bit(POSTED_INTR_ON,
 396                         (unsigned long *)&pi_desc->control);
 397 }
 398
 399 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 400 {
 401         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 402 }
 403
 404 struct vcpu_vmx {
 405         struct kvm_vcpu       vcpu;
 406         unsigned long         host_rsp;
 407         u8                    fail;
 408         u8                    cpl;
 409         bool                  nmi_known_unmasked;
 410         u32                   exit_intr_info;
 411         u32                   idt_vectoring_info;
 412         ulong                 rflags;
 413         struct shared_msr_entry *guest_msrs;
 414         int                   nmsrs;
 415         int                   save_nmsrs;
 416         unsigned long         host_idt_base;
 417 #ifdef CONFIG_X86_64
 418         u64                   msr_host_kernel_gs_base;
 419         u64                   msr_guest_kernel_gs_base;
 420 #endif
 421         /*
 422          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 423          * non-nested (L1) guest, it always points to vmcs01. For a nested
 424          * guest (L2), it points to a different VMCS.
 425          */
 426         struct loaded_vmcs    vmcs01;
 427         struct loaded_vmcs   *loaded_vmcs;
 428         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 429         struct msr_autoload {
 430                 unsigned nr;
 431                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 432                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 433         } msr_autoload;
 434         struct {
 435                 int           loaded;
 436                 u16           fs_sel, gs_sel, ldt_sel;
 437 #ifdef CONFIG_X86_64
 438                 u16           ds_sel, es_sel;
 439 #endif
 440                 int           gs_ldt_reload_needed;
 441                 int           fs_reload_needed;
 442         } host_state;
 443         struct {
 444                 int vm86_active;
 445                 ulong save_rflags;
 446                 struct kvm_segment segs[8];
 447         } rmode;
 448         struct {
 449                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 450                 struct kvm_save_segment {
 451                         u16 selector;
 452                         unsigned long base;
 453                         u32 limit;
 454                         u32 ar;
 455                 } seg[8];
 456         } segment_cache;
 457         int vpid;
 458         bool emulation_required;
 459
 460         /* Support for vnmi-less CPUs */
 461         int soft_vnmi_blocked;
 462         ktime_t entry_time;
 463         s64 vnmi_blocked_time;
 464         u32 exit_reason;
 465
 466         bool rdtscp_enabled;
 467
 468         /* Posted interrupt descriptor */
 469         struct pi_desc pi_desc;
 470
 471         /* Support for a guest hypervisor (nested VMX) */
 472         struct nested_vmx nested;
 473 };
 474
 475 enum segment_cache_field {
 476         SEG_FIELD_SEL = 0,
 477         SEG_FIELD_BASE = 1,
 478         SEG_FIELD_LIMIT = 2,
 479         SEG_FIELD_AR = 3,
 480
 481         SEG_FIELD_NR = 4
 482 };
 483
 484 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 485 {
 486         return container_of(vcpu, struct vcpu_vmx, vcpu);
 487 }
 488
 489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 490 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 491 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 492                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 493
 494
 495 static const unsigned long shadow_read_only_fields[] = {
 496         /*
 497          * We do NOT shadow fields that are modified when L0
 498          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 499          * VMXON...) executed by L1.
 500          * For example, VM_INSTRUCTION_ERROR is read
 501          * by L1 if a vmx instruction fails (part of the error path).
 502          * Note the code assumes this logic. If for some reason
 503          * we start shadowing these fields then we need to
 504          * force a shadow sync when L0 emulates vmx instructions
 505          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 506          * by nested_vmx_failValid)
 507          */
 508         VM_EXIT_REASON,
 509         VM_EXIT_INTR_INFO,
 510         VM_EXIT_INSTRUCTION_LEN,
 511         IDT_VECTORING_INFO_FIELD,
 512         IDT_VECTORING_ERROR_CODE,
 513         VM_EXIT_INTR_ERROR_CODE,
 514         EXIT_QUALIFICATION,
 515         GUEST_LINEAR_ADDRESS,
 516         GUEST_PHYSICAL_ADDRESS
 517 };
 518 static const int max_shadow_read_only_fields =
 519         ARRAY_SIZE(shadow_read_only_fields);
 520
 521 static const unsigned long shadow_read_write_fields[] = {
 522         GUEST_RIP,
 523         GUEST_RSP,
 524         GUEST_CR0,
 525         GUEST_CR3,
 526         GUEST_CR4,
 527         GUEST_INTERRUPTIBILITY_INFO,
 528         GUEST_RFLAGS,
 529         GUEST_CS_SELECTOR,
 530         GUEST_CS_AR_BYTES,
 531         GUEST_CS_LIMIT,
 532         GUEST_CS_BASE,
 533         GUEST_ES_BASE,
 534         CR0_GUEST_HOST_MASK,
 535         CR0_READ_SHADOW,
 536         CR4_READ_SHADOW,
 537         TSC_OFFSET,
 538         EXCEPTION_BITMAP,
 539         CPU_BASED_VM_EXEC_CONTROL,
 540         VM_ENTRY_EXCEPTION_ERROR_CODE,
 541         VM_ENTRY_INTR_INFO_FIELD,
 542         VM_ENTRY_INSTRUCTION_LEN,
 543         VM_ENTRY_EXCEPTION_ERROR_CODE,
 544         HOST_FS_BASE,
 545         HOST_GS_BASE,
 546         HOST_FS_SELECTOR,
 547         HOST_GS_SELECTOR
 548 };
 549 static const int max_shadow_read_write_fields =
 550         ARRAY_SIZE(shadow_read_write_fields);
 551
 552 static const unsigned short vmcs_field_to_offset_table[] = {
 553         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 554         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 555         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 556         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 557         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 558         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 559         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 560         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 561         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 562         FIELD(HOST_ES_SELECTOR, host_es_selector),
 563         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 564         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 565         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 566         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 567         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 568         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 569         FIELD64(IO_BITMAP_A, io_bitmap_a),
 570         FIELD64(IO_BITMAP_B, io_bitmap_b),
 571         FIELD64(MSR_BITMAP, msr_bitmap),
 572         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 573         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 574         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 575         FIELD64(TSC_OFFSET, tsc_offset),
 576         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 577         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 578         FIELD64(EPT_POINTER, ept_pointer),
 579         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 580         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 581         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 582         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 583         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 584         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 585         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 586         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 587         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 588         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 589         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 590         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 591         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 592         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 593         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 594         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 595         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 596         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 597         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 598         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 599         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 600         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 601         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 602         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 603         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 604         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 605         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 606         FIELD(TPR_THRESHOLD, tpr_threshold),
 607         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 608         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 609         FIELD(VM_EXIT_REASON, vm_exit_reason),
 610         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 611         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 612         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 613         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 614         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 615         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 616         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 617         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 618         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 619         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 620         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 621         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 622         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 623         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 624         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 625         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 626         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 627         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 628         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 629         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 630         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 631         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 632         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 633         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 634         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 635         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 636         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 637         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 638         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 639         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 640         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 641         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 642         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 643         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 644         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 645         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 646         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 647         FIELD(EXIT_QUALIFICATION, exit_qualification),
 648         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 649         FIELD(GUEST_CR0, guest_cr0),
 650         FIELD(GUEST_CR3, guest_cr3),
 651         FIELD(GUEST_CR4, guest_cr4),
 652         FIELD(GUEST_ES_BASE, guest_es_base),
 653         FIELD(GUEST_CS_BASE, guest_cs_base),
 654         FIELD(GUEST_SS_BASE, guest_ss_base),
 655         FIELD(GUEST_DS_BASE, guest_ds_base),
 656         FIELD(GUEST_FS_BASE, guest_fs_base),
 657         FIELD(GUEST_GS_BASE, guest_gs_base),
 658         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 659         FIELD(GUEST_TR_BASE, guest_tr_base),
 660         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 661         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 662         FIELD(GUEST_DR7, guest_dr7),
 663         FIELD(GUEST_RSP, guest_rsp),
 664         FIELD(GUEST_RIP, guest_rip),
 665         FIELD(GUEST_RFLAGS, guest_rflags),
 666         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 667         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 668         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 669         FIELD(HOST_CR0, host_cr0),
 670         FIELD(HOST_CR3, host_cr3),
 671         FIELD(HOST_CR4, host_cr4),
 672         FIELD(HOST_FS_BASE, host_fs_base),
 673         FIELD(HOST_GS_BASE, host_gs_base),
 674         FIELD(HOST_TR_BASE, host_tr_base),
 675         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 676         FIELD(HOST_IDTR_BASE, host_idtr_base),
 677         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 678         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 679         FIELD(HOST_RSP, host_rsp),
 680         FIELD(HOST_RIP, host_rip),
 681 };
 682 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 683
 684 static inline short vmcs_field_to_offset(unsigned long field)
 685 {
 686         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 687                 return -1;
 688         return vmcs_field_to_offset_table[field];
 689 }
 690
 691 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 692 {
 693         return to_vmx(vcpu)->nested.current_vmcs12;
 694 }
 695
 696 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 697 {
 698         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 699         if (is_error_page(page))
 700                 return NULL;
 701
 702         return page;
 703 }
 704
 705 static void nested_release_page(struct page *page)
 706 {
 707         kvm_release_page_dirty(page);
 708 }
 709
 710 static void nested_release_page_clean(struct page *page)
 711 {
 712         kvm_release_page_clean(page);
 713 }
 714
 715 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 716 static u64 construct_eptp(unsigned long root_hpa);
 717 static void kvm_cpu_vmxon(u64 addr);
 718 static void kvm_cpu_vmxoff(void);
 719 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 720 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 721 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 722                             struct kvm_segment *var, int seg);
 723 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 724                             struct kvm_segment *var, int seg);
 725 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 726 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 727 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 728 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 729 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 730
 731 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 732 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 733 /*
 734  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 735  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 736  */
 737 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 738 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 739
 740 static unsigned long *vmx_io_bitmap_a;
 741 static unsigned long *vmx_io_bitmap_b;
 742 static unsigned long *vmx_msr_bitmap_legacy;
 743 static unsigned long *vmx_msr_bitmap_longmode;
 744 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 745 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 746 static unsigned long *vmx_vmread_bitmap;
 747 static unsigned long *vmx_vmwrite_bitmap;
 748
 749 static bool cpu_has_load_ia32_efer;
 750 static bool cpu_has_load_perf_global_ctrl;
 751
 752 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 753 static DEFINE_SPINLOCK(vmx_vpid_lock);
 754
 755 static struct vmcs_config {
 756         int size;
 757         int order;
 758         u32 revision_id;
 759         u32 pin_based_exec_ctrl;
 760         u32 cpu_based_exec_ctrl;
 761         u32 cpu_based_2nd_exec_ctrl;
 762         u32 vmexit_ctrl;
 763         u32 vmentry_ctrl;
 764 } vmcs_config;
 765
 766 static struct vmx_capability {
 767         u32 ept;
 768         u32 vpid;
 769 } vmx_capability;
 770
 771 #define VMX_SEGMENT_FIELD(seg)                                  \
 772         [VCPU_SREG_##seg] = {                                   \
 773                 .selector = GUEST_##seg##_SELECTOR,             \
 774                 .base = GUEST_##seg##_BASE,                     \
 775                 .limit = GUEST_##seg##_LIMIT,                   \
 776                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 777         }
 778
 779 static const struct kvm_vmx_segment_field {
 780         unsigned selector;
 781         unsigned base;
 782         unsigned limit;
 783         unsigned ar_bytes;
 784 } kvm_vmx_segment_fields[] = {
 785         VMX_SEGMENT_FIELD(CS),
 786         VMX_SEGMENT_FIELD(DS),
 787         VMX_SEGMENT_FIELD(ES),
 788         VMX_SEGMENT_FIELD(FS),
 789         VMX_SEGMENT_FIELD(GS),
 790         VMX_SEGMENT_FIELD(SS),
 791         VMX_SEGMENT_FIELD(TR),
 792         VMX_SEGMENT_FIELD(LDTR),
 793 };
 794
 795 static u64 host_efer;
 796
 797 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 798
 799 /*
 800  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 801  * away by decrementing the array size.
 802  */
 803 static const u32 vmx_msr_index[] = {
 804 #ifdef CONFIG_X86_64
 805         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 806 #endif
 807         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 808 };
 809 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 810
 811 static inline bool is_page_fault(u32 intr_info)
 812 {
 813         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 814                              INTR_INFO_VALID_MASK)) ==
 815                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 816 }
 817
 818 static inline bool is_no_device(u32 intr_info)
 819 {
 820         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 821                              INTR_INFO_VALID_MASK)) ==
 822                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 823 }
 824
 825 static inline bool is_invalid_opcode(u32 intr_info)
 826 {
 827         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 828                              INTR_INFO_VALID_MASK)) ==
 829                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 830 }
 831
 832 static inline bool is_external_interrupt(u32 intr_info)
 833 {
 834         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 835                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 836 }
 837
 838 static inline bool is_machine_check(u32 intr_info)
 839 {
 840         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 841                              INTR_INFO_VALID_MASK)) ==
 842                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 843 }
 844
 845 static inline bool cpu_has_vmx_msr_bitmap(void)
 846 {
 847         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 848 }
 849
 850 static inline bool cpu_has_vmx_tpr_shadow(void)
 851 {
 852         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 853 }
 854
 855 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 856 {
 857         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 858 }
 859
 860 static inline bool cpu_has_secondary_exec_ctrls(void)
 861 {
 862         return vmcs_config.cpu_based_exec_ctrl &
 863                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 864 }
 865
 866 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 867 {
 868         return vmcs_config.cpu_based_2nd_exec_ctrl &
 869                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 870 }
 871
 872 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 873 {
 874         return vmcs_config.cpu_based_2nd_exec_ctrl &
 875                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 876 }
 877
 878 static inline bool cpu_has_vmx_apic_register_virt(void)
 879 {
 880         return vmcs_config.cpu_based_2nd_exec_ctrl &
 881                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 882 }
 883
 884 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 885 {
 886         return vmcs_config.cpu_based_2nd_exec_ctrl &
 887                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 888 }
 889
 890 static inline bool cpu_has_vmx_posted_intr(void)
 891 {
 892         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 893 }
 894
 895 static inline bool cpu_has_vmx_apicv(void)
 896 {
 897         return cpu_has_vmx_apic_register_virt() &&
 898                 cpu_has_vmx_virtual_intr_delivery() &&
 899                 cpu_has_vmx_posted_intr();
 900 }
 901
 902 static inline bool cpu_has_vmx_flexpriority(void)
 903 {
 904         return cpu_has_vmx_tpr_shadow() &&
 905                 cpu_has_vmx_virtualize_apic_accesses();
 906 }
 907
 908 static inline bool cpu_has_vmx_ept_execute_only(void)
 909 {
 910         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 911 }
 912
 913 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 914 {
 915         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 916 }
 917
 918 static inline bool cpu_has_vmx_eptp_writeback(void)
 919 {
 920         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 921 }
 922
 923 static inline bool cpu_has_vmx_ept_2m_page(void)
 924 {
 925         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 926 }
 927
 928 static inline bool cpu_has_vmx_ept_1g_page(void)
 929 {
 930         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 931 }
 932
 933 static inline bool cpu_has_vmx_ept_4levels(void)
 934 {
 935         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 936 }
 937
 938 static inline bool cpu_has_vmx_ept_ad_bits(void)
 939 {
 940         return vmx_capability.ept & VMX_EPT_AD_BIT;
 941 }
 942
 943 static inline bool cpu_has_vmx_invept_context(void)
 944 {
 945         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 946 }
 947
 948 static inline bool cpu_has_vmx_invept_global(void)
 949 {
 950         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 951 }
 952
 953 static inline bool cpu_has_vmx_invvpid_single(void)
 954 {
 955         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 956 }
 957
 958 static inline bool cpu_has_vmx_invvpid_global(void)
 959 {
 960         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 961 }
 962
 963 static inline bool cpu_has_vmx_ept(void)
 964 {
 965         return vmcs_config.cpu_based_2nd_exec_ctrl &
 966                 SECONDARY_EXEC_ENABLE_EPT;
 967 }
 968
 969 static inline bool cpu_has_vmx_unrestricted_guest(void)
 970 {
 971         return vmcs_config.cpu_based_2nd_exec_ctrl &
 972                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 973 }
 974
 975 static inline bool cpu_has_vmx_ple(void)
 976 {
 977         return vmcs_config.cpu_based_2nd_exec_ctrl &
 978                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 979 }
 980
 981 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 982 {
 983         return flexpriority_enabled && irqchip_in_kernel(kvm);
 984 }
 985
 986 static inline bool cpu_has_vmx_vpid(void)
 987 {
 988         return vmcs_config.cpu_based_2nd_exec_ctrl &
 989                 SECONDARY_EXEC_ENABLE_VPID;
 990 }
 991
 992 static inline bool cpu_has_vmx_rdtscp(void)
 993 {
 994         return vmcs_config.cpu_based_2nd_exec_ctrl &
 995                 SECONDARY_EXEC_RDTSCP;
 996 }
 997
 998 static inline bool cpu_has_vmx_invpcid(void)
 999 {
1000         return vmcs_config.cpu_based_2nd_exec_ctrl &
1001                 SECONDARY_EXEC_ENABLE_INVPCID;
1002 }
1003
1004 static inline bool cpu_has_virtual_nmis(void)
1005 {
1006         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1007 }
1008
1009 static inline bool cpu_has_vmx_wbinvd_exit(void)
1010 {
1011         return vmcs_config.cpu_based_2nd_exec_ctrl &
1012                 SECONDARY_EXEC_WBINVD_EXITING;
1013 }
1014
1015 static inline bool cpu_has_vmx_shadow_vmcs(void)
1016 {
1017         u64 vmx_msr;
1018         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1019         /* check if the cpu supports writing r/o exit information fields */
1020         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1021                 return false;
1022
1023         return vmcs_config.cpu_based_2nd_exec_ctrl &
1024                 SECONDARY_EXEC_SHADOW_VMCS;
1025 }
1026
1027 static inline bool report_flexpriority(void)
1028 {
1029         return flexpriority_enabled;
1030 }
1031
1032 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1033 {
1034         return vmcs12->cpu_based_vm_exec_control & bit;
1035 }
1036
1037 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1038 {
1039         return (vmcs12->cpu_based_vm_exec_control &
1040                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1041                 (vmcs12->secondary_vm_exec_control & bit);
1042 }
1043
1044 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1045         struct kvm_vcpu *vcpu)
1046 {
1047         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1048 }
1049
1050 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1051 {
1052         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1053 }
1054
1055 static inline bool is_exception(u32 intr_info)
1056 {
1057         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1058                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1059 }
1060
1061 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1062 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1063                         struct vmcs12 *vmcs12,
1064                         u32 reason, unsigned long qualification);
1065
1066 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1067 {
1068         int i;
1069
1070         for (i = 0; i < vmx->nmsrs; ++i)
1071                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1072                         return i;
1073         return -1;
1074 }
1075
1076 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1077 {
1078     struct {
1079         u64 vpid : 16;
1080         u64 rsvd : 48;
1081         u64 gva;
1082     } operand = { vpid, 0, gva };
1083
1084     asm volatile (__ex(ASM_VMX_INVVPID)
1085                   /* CF==1 or ZF==1 --> rc = -1 */
1086                   "; ja 1f ; ud2 ; 1:"
1087                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1088 }
1089
1090 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1091 {
1092         struct {
1093                 u64 eptp, gpa;
1094         } operand = {eptp, gpa};
1095
1096         asm volatile (__ex(ASM_VMX_INVEPT)
1097                         /* CF==1 or ZF==1 --> rc = -1 */
1098                         "; ja 1f ; ud2 ; 1:\n"
1099                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1100 }
1101
1102 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1103 {
1104         int i;
1105
1106         i = __find_msr_index(vmx, msr);
1107         if (i >= 0)
1108                 return &vmx->guest_msrs[i];
1109         return NULL;
1110 }
1111
1112 static void vmcs_clear(struct vmcs *vmcs)
1113 {
1114         u64 phys_addr = __pa(vmcs);
1115         u8 error;
1116
1117         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1118                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1119                       : "cc", "memory");
1120         if (error)
1121                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1122                        vmcs, phys_addr);
1123 }
1124
1125 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1126 {
1127         vmcs_clear(loaded_vmcs->vmcs);
1128         loaded_vmcs->cpu = -1;
1129         loaded_vmcs->launched = 0;
1130 }
1131
1132 static void vmcs_load(struct vmcs *vmcs)
1133 {
1134         u64 phys_addr = __pa(vmcs);
1135         u8 error;
1136
1137         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1138                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1139                         : "cc", "memory");
1140         if (error)
1141                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1142                        vmcs, phys_addr);
1143 }
1144
1145 #ifdef CONFIG_KEXEC
1146 /*
1147  * This bitmap is used to indicate whether the vmclear
1148  * operation is enabled on all cpus. All disabled by
1149  * default.
1150  */
1151 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1152
1153 static inline void crash_enable_local_vmclear(int cpu)
1154 {
1155         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1156 }
1157
1158 static inline void crash_disable_local_vmclear(int cpu)
1159 {
1160         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1161 }
1162
1163 static inline int crash_local_vmclear_enabled(int cpu)
1164 {
1165         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1166 }
1167
1168 static void crash_vmclear_local_loaded_vmcss(void)
1169 {
1170         int cpu = raw_smp_processor_id();
1171         struct loaded_vmcs *v;
1172
1173         if (!crash_local_vmclear_enabled(cpu))
1174                 return;
1175
1176         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1177                             loaded_vmcss_on_cpu_link)
1178                 vmcs_clear(v->vmcs);
1179 }
1180 #else
1181 static inline void crash_enable_local_vmclear(int cpu) { }
1182 static inline void crash_disable_local_vmclear(int cpu) { }
1183 #endif /* CONFIG_KEXEC */
1184
1185 static void __loaded_vmcs_clear(void *arg)
1186 {
1187         struct loaded_vmcs *loaded_vmcs = arg;
1188         int cpu = raw_smp_processor_id();
1189
1190         if (loaded_vmcs->cpu != cpu)
1191                 return; /* vcpu migration can race with cpu offline */
1192         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1193                 per_cpu(current_vmcs, cpu) = NULL;
1194         crash_disable_local_vmclear(cpu);
1195         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1196
1197         /*
1198          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1199          * is before setting loaded_vmcs->vcpu to -1 which is done in
1200          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1201          * then adds the vmcs into percpu list before it is deleted.
1202          */
1203         smp_wmb();
1204
1205         loaded_vmcs_init(loaded_vmcs);
1206         crash_enable_local_vmclear(cpu);
1207 }
1208
1209 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1210 {
1211         int cpu = loaded_vmcs->cpu;
1212
1213         if (cpu != -1)
1214                 smp_call_function_single(cpu,
1215                          __loaded_vmcs_clear, loaded_vmcs, 1);
1216 }
1217
1218 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1219 {
1220         if (vmx->vpid == 0)
1221                 return;
1222
1223         if (cpu_has_vmx_invvpid_single())
1224                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1225 }
1226
1227 static inline void vpid_sync_vcpu_global(void)
1228 {
1229         if (cpu_has_vmx_invvpid_global())
1230                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1231 }
1232
1233 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1234 {
1235         if (cpu_has_vmx_invvpid_single())
1236                 vpid_sync_vcpu_single(vmx);
1237         else
1238                 vpid_sync_vcpu_global();
1239 }
1240
1241 static inline void ept_sync_global(void)
1242 {
1243         if (cpu_has_vmx_invept_global())
1244                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1245 }
1246
1247 static inline void ept_sync_context(u64 eptp)
1248 {
1249         if (enable_ept) {
1250                 if (cpu_has_vmx_invept_context())
1251                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1252                 else
1253                         ept_sync_global();
1254         }
1255 }
1256
1257 static __always_inline unsigned long vmcs_readl(unsigned long field)
1258 {
1259         unsigned long value;
1260
1261         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1262                       : "=a"(value) : "d"(field) : "cc");
1263         return value;
1264 }
1265
1266 static __always_inline u16 vmcs_read16(unsigned long field)
1267 {
1268         return vmcs_readl(field);
1269 }
1270
1271 static __always_inline u32 vmcs_read32(unsigned long field)
1272 {
1273         return vmcs_readl(field);
1274 }
1275
1276 static __always_inline u64 vmcs_read64(unsigned long field)
1277 {
1278 #ifdef CONFIG_X86_64
1279         return vmcs_readl(field);
1280 #else
1281         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1282 #endif
1283 }
1284
1285 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1286 {
1287         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1288                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1289         dump_stack();
1290 }
1291
1292 static void vmcs_writel(unsigned long field, unsigned long value)
1293 {
1294         u8 error;
1295
1296         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1297                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1298         if (unlikely(error))
1299                 vmwrite_error(field, value);
1300 }
1301
1302 static void vmcs_write16(unsigned long field, u16 value)
1303 {
1304         vmcs_writel(field, value);
1305 }
1306
1307 static void vmcs_write32(unsigned long field, u32 value)
1308 {
1309         vmcs_writel(field, value);
1310 }
1311
1312 static void vmcs_write64(unsigned long field, u64 value)
1313 {
1314         vmcs_writel(field, value);
1315 #ifndef CONFIG_X86_64
1316         asm volatile ("");
1317         vmcs_writel(field+1, value >> 32);
1318 #endif
1319 }
1320
1321 static void vmcs_clear_bits(unsigned long field, u32 mask)
1322 {
1323         vmcs_writel(field, vmcs_readl(field) & ~mask);
1324 }
1325
1326 static void vmcs_set_bits(unsigned long field, u32 mask)
1327 {
1328         vmcs_writel(field, vmcs_readl(field) | mask);
1329 }
1330
1331 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1332 {
1333         vmx->segment_cache.bitmask = 0;
1334 }
1335
1336 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1337                                        unsigned field)
1338 {
1339         bool ret;
1340         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1341
1342         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1343                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1344                 vmx->segment_cache.bitmask = 0;
1345         }
1346         ret = vmx->segment_cache.bitmask & mask;
1347         vmx->segment_cache.bitmask |= mask;
1348         return ret;
1349 }
1350
1351 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1352 {
1353         u16 *p = &vmx->segment_cache.seg[seg].selector;
1354
1355         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1356                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1357         return *p;
1358 }
1359
1360 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1361 {
1362         ulong *p = &vmx->segment_cache.seg[seg].base;
1363
1364         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1365                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1366         return *p;
1367 }
1368
1369 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1370 {
1371         u32 *p = &vmx->segment_cache.seg[seg].limit;
1372
1373         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1374                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1375         return *p;
1376 }
1377
1378 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1379 {
1380         u32 *p = &vmx->segment_cache.seg[seg].ar;
1381
1382         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1383                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1384         return *p;
1385 }
1386
1387 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1388 {
1389         u32 eb;
1390
1391         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1392              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1393         if ((vcpu->guest_debug &
1394              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1395             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1396                 eb |= 1u << BP_VECTOR;
1397         if (to_vmx(vcpu)->rmode.vm86_active)
1398                 eb = ~0;
1399         if (enable_ept)
1400                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1401         if (vcpu->fpu_active)
1402                 eb &= ~(1u << NM_VECTOR);
1403
1404         /* When we are running a nested L2 guest and L1 specified for it a
1405          * certain exception bitmap, we must trap the same exceptions and pass
1406          * them to L1. When running L2, we will only handle the exceptions
1407          * specified above if L1 did not want them.
1408          */
1409         if (is_guest_mode(vcpu))
1410                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1411
1412         vmcs_write32(EXCEPTION_BITMAP, eb);
1413 }
1414
1415 static void clear_atomic_switch_msr_special(unsigned long entry,
1416                 unsigned long exit)
1417 {
1418         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1419         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1420 }
1421
1422 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1423 {
1424         unsigned i;
1425         struct msr_autoload *m = &vmx->msr_autoload;
1426
1427         switch (msr) {
1428         case MSR_EFER:
1429                 if (cpu_has_load_ia32_efer) {
1430                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1431                                         VM_EXIT_LOAD_IA32_EFER);
1432                         return;
1433                 }
1434                 break;
1435         case MSR_CORE_PERF_GLOBAL_CTRL:
1436                 if (cpu_has_load_perf_global_ctrl) {
1437                         clear_atomic_switch_msr_special(
1438                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1439                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1440                         return;
1441                 }
1442                 break;
1443         }
1444
1445         for (i = 0; i < m->nr; ++i)
1446                 if (m->guest[i].index == msr)
1447                         break;
1448
1449         if (i == m->nr)
1450                 return;
1451         --m->nr;
1452         m->guest[i] = m->guest[m->nr];
1453         m->host[i] = m->host[m->nr];
1454         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1455         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1456 }
1457
1458 static void add_atomic_switch_msr_special(unsigned long entry,
1459                 unsigned long exit, unsigned long guest_val_vmcs,
1460                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1461 {
1462         vmcs_write64(guest_val_vmcs, guest_val);
1463         vmcs_write64(host_val_vmcs, host_val);
1464         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1465         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1466 }
1467
1468 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1469                                   u64 guest_val, u64 host_val)
1470 {
1471         unsigned i;
1472         struct msr_autoload *m = &vmx->msr_autoload;
1473
1474         switch (msr) {
1475         case MSR_EFER:
1476                 if (cpu_has_load_ia32_efer) {
1477                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1478                                         VM_EXIT_LOAD_IA32_EFER,
1479                                         GUEST_IA32_EFER,
1480                                         HOST_IA32_EFER,
1481                                         guest_val, host_val);
1482                         return;
1483                 }
1484                 break;
1485         case MSR_CORE_PERF_GLOBAL_CTRL:
1486                 if (cpu_has_load_perf_global_ctrl) {
1487                         add_atomic_switch_msr_special(
1488                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1489                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1490                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1491                                         HOST_IA32_PERF_GLOBAL_CTRL,
1492                                         guest_val, host_val);
1493                         return;
1494                 }
1495                 break;
1496         }
1497
1498         for (i = 0; i < m->nr; ++i)
1499                 if (m->guest[i].index == msr)
1500                         break;
1501
1502         if (i == NR_AUTOLOAD_MSRS) {
1503                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1504                                 "Can't add msr %x\n", msr);
1505                 return;
1506         } else if (i == m->nr) {
1507                 ++m->nr;
1508                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1509                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1510         }
1511
1512         m->guest[i].index = msr;
1513         m->guest[i].value = guest_val;
1514         m->host[i].index = msr;
1515         m->host[i].value = host_val;
1516 }
1517
1518 static void reload_tss(void)
1519 {
1520         /*
1521          * VT restores TR but not its size.  Useless.
1522          */
1523         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1524         struct desc_struct *descs;
1525
1526         descs = (void *)gdt->address;
1527         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1528         load_TR_desc();
1529 }
1530
1531 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1532 {
1533         u64 guest_efer;
1534         u64 ignore_bits;
1535
1536         guest_efer = vmx->vcpu.arch.efer;
1537
1538         /*
1539          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1540          * outside long mode
1541          */
1542         ignore_bits = EFER_NX | EFER_SCE;
1543 #ifdef CONFIG_X86_64
1544         ignore_bits |= EFER_LMA | EFER_LME;
1545         /* SCE is meaningful only in long mode on Intel */
1546         if (guest_efer & EFER_LMA)
1547                 ignore_bits &= ~(u64)EFER_SCE;
1548 #endif
1549         guest_efer &= ~ignore_bits;
1550         guest_efer |= host_efer & ignore_bits;
1551         vmx->guest_msrs[efer_offset].data = guest_efer;
1552         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1553
1554         clear_atomic_switch_msr(vmx, MSR_EFER);
1555         /* On ept, can't emulate nx, and must switch nx atomically */
1556         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1557                 guest_efer = vmx->vcpu.arch.efer;
1558                 if (!(guest_efer & EFER_LMA))
1559                         guest_efer &= ~EFER_LME;
1560                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1561                 return false;
1562         }
1563
1564         return true;
1565 }
1566
1567 static unsigned long segment_base(u16 selector)
1568 {
1569         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1570         struct desc_struct *d;
1571         unsigned long table_base;
1572         unsigned long v;
1573
1574         if (!(selector & ~3))
1575                 return 0;
1576
1577         table_base = gdt->address;
1578
1579         if (selector & 4) {           /* from ldt */
1580                 u16 ldt_selector = kvm_read_ldt();
1581
1582                 if (!(ldt_selector & ~3))
1583                         return 0;
1584
1585                 table_base = segment_base(ldt_selector);
1586         }
1587         d = (struct desc_struct *)(table_base + (selector & ~7));
1588         v = get_desc_base(d);
1589 #ifdef CONFIG_X86_64
1590        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1591                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1592 #endif
1593         return v;
1594 }
1595
1596 static inline unsigned long kvm_read_tr_base(void)
1597 {
1598         u16 tr;
1599         asm("str %0" : "=g"(tr));
1600         return segment_base(tr);
1601 }
1602
1603 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1604 {
1605         struct vcpu_vmx *vmx = to_vmx(vcpu);
1606         int i;
1607
1608         if (vmx->host_state.loaded)
1609                 return;
1610
1611         vmx->host_state.loaded = 1;
1612         /*
1613          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1614          * allow segment selectors with cpl > 0 or ti == 1.
1615          */
1616         vmx->host_state.ldt_sel = kvm_read_ldt();
1617         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1618         savesegment(fs, vmx->host_state.fs_sel);
1619         if (!(vmx->host_state.fs_sel & 7)) {
1620                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1621                 vmx->host_state.fs_reload_needed = 0;
1622         } else {
1623                 vmcs_write16(HOST_FS_SELECTOR, 0);
1624                 vmx->host_state.fs_reload_needed = 1;
1625         }
1626         savesegment(gs, vmx->host_state.gs_sel);
1627         if (!(vmx->host_state.gs_sel & 7))
1628                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1629         else {
1630                 vmcs_write16(HOST_GS_SELECTOR, 0);
1631                 vmx->host_state.gs_ldt_reload_needed = 1;
1632         }
1633
1634 #ifdef CONFIG_X86_64
1635         savesegment(ds, vmx->host_state.ds_sel);
1636         savesegment(es, vmx->host_state.es_sel);
1637 #endif
1638
1639 #ifdef CONFIG_X86_64
1640         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1641         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1642 #else
1643         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1644         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1645 #endif
1646
1647 #ifdef CONFIG_X86_64
1648         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1649         if (is_long_mode(&vmx->vcpu))
1650                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1651 #endif
1652         for (i = 0; i < vmx->save_nmsrs; ++i)
1653                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1654                                    vmx->guest_msrs[i].data,
1655                                    vmx->guest_msrs[i].mask);
1656 }
1657
1658 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1659 {
1660         if (!vmx->host_state.loaded)
1661                 return;
1662
1663         ++vmx->vcpu.stat.host_state_reload;
1664         vmx->host_state.loaded = 0;
1665 #ifdef CONFIG_X86_64
1666         if (is_long_mode(&vmx->vcpu))
1667                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1668 #endif
1669         if (vmx->host_state.gs_ldt_reload_needed) {
1670                 kvm_load_ldt(vmx->host_state.ldt_sel);
1671 #ifdef CONFIG_X86_64
1672                 load_gs_index(vmx->host_state.gs_sel);
1673 #else
1674                 loadsegment(gs, vmx->host_state.gs_sel);
1675 #endif
1676         }
1677         if (vmx->host_state.fs_reload_needed)
1678                 loadsegment(fs, vmx->host_state.fs_sel);
1679 #ifdef CONFIG_X86_64
1680         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1681                 loadsegment(ds, vmx->host_state.ds_sel);
1682                 loadsegment(es, vmx->host_state.es_sel);
1683         }
1684 #endif
1685         reload_tss();
1686 #ifdef CONFIG_X86_64
1687         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1688 #endif
1689         /*
1690          * If the FPU is not active (through the host task or
1691          * the guest vcpu), then restore the cr0.TS bit.
1692          */
1693         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1694                 stts();
1695         load_gdt(&__get_cpu_var(host_gdt));
1696 }
1697
1698 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1699 {
1700         preempt_disable();
1701         __vmx_load_host_state(vmx);
1702         preempt_enable();
1703 }
1704
1705 /*
1706  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1707  * vcpu mutex is already taken.
1708  */
1709 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1710 {
1711         struct vcpu_vmx *vmx = to_vmx(vcpu);
1712         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1713
1714         if (!vmm_exclusive)
1715                 kvm_cpu_vmxon(phys_addr);
1716         else if (vmx->loaded_vmcs->cpu != cpu)
1717                 loaded_vmcs_clear(vmx->loaded_vmcs);
1718
1719         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1720                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1721                 vmcs_load(vmx->loaded_vmcs->vmcs);
1722         }
1723
1724         if (vmx->loaded_vmcs->cpu != cpu) {
1725                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1726                 unsigned long sysenter_esp;
1727
1728                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1729                 local_irq_disable();
1730                 crash_disable_local_vmclear(cpu);
1731
1732                 /*
1733                  * Read loaded_vmcs->cpu should be before fetching
1734                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1735                  * See the comments in __loaded_vmcs_clear().
1736                  */
1737                 smp_rmb();
1738
1739                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1740                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1741                 crash_enable_local_vmclear(cpu);
1742                 local_irq_enable();
1743
1744                 /*
1745                  * Linux uses per-cpu TSS and GDT, so set these when switching
1746                  * processors.
1747                  */
1748                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1749                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1750
1751                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1752                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1753                 vmx->loaded_vmcs->cpu = cpu;
1754         }
1755 }
1756
1757 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1758 {
1759         __vmx_load_host_state(to_vmx(vcpu));
1760         if (!vmm_exclusive) {
1761                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1762                 vcpu->cpu = -1;
1763                 kvm_cpu_vmxoff();
1764         }
1765 }
1766
1767 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1768 {
1769         ulong cr0;
1770
1771         if (vcpu->fpu_active)
1772                 return;
1773         vcpu->fpu_active = 1;
1774         cr0 = vmcs_readl(GUEST_CR0);
1775         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1776         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1777         vmcs_writel(GUEST_CR0, cr0);
1778         update_exception_bitmap(vcpu);
1779         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1780         if (is_guest_mode(vcpu))
1781                 vcpu->arch.cr0_guest_owned_bits &=
1782                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1783         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1784 }
1785
1786 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1787
1788 /*
1789  * Return the cr0 value that a nested guest would read. This is a combination
1790  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1791  * its hypervisor (cr0_read_shadow).
1792  */
1793 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1794 {
1795         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1796                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1797 }
1798 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1799 {
1800         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1801                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1802 }
1803
1804 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1805 {
1806         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1807          * set this *before* calling this function.
1808          */
1809         vmx_decache_cr0_guest_bits(vcpu);
1810         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1811         update_exception_bitmap(vcpu);
1812         vcpu->arch.cr0_guest_owned_bits = 0;
1813         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1814         if (is_guest_mode(vcpu)) {
1815                 /*
1816                  * L1's specified read shadow might not contain the TS bit,
1817                  * so now that we turned on shadowing of this bit, we need to
1818                  * set this bit of the shadow. Like in nested_vmx_run we need
1819                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1820                  * up-to-date here because we just decached cr0.TS (and we'll
1821                  * only update vmcs12->guest_cr0 on nested exit).
1822                  */
1823                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1824                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1825                         (vcpu->arch.cr0 & X86_CR0_TS);
1826                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1827         } else
1828                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1829 }
1830
1831 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1832 {
1833         unsigned long rflags, save_rflags;
1834
1835         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1836                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1837                 rflags = vmcs_readl(GUEST_RFLAGS);
1838                 if (to_vmx(vcpu)->rmode.vm86_active) {
1839                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1840                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1841                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1842                 }
1843                 to_vmx(vcpu)->rflags = rflags;
1844         }
1845         return to_vmx(vcpu)->rflags;
1846 }
1847
1848 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1849 {
1850         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1851         to_vmx(vcpu)->rflags = rflags;
1852         if (to_vmx(vcpu)->rmode.vm86_active) {
1853                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1854                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1855         }
1856         vmcs_writel(GUEST_RFLAGS, rflags);
1857 }
1858
1859 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1860 {
1861         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1862         int ret = 0;
1863
1864         if (interruptibility & GUEST_INTR_STATE_STI)
1865                 ret |= KVM_X86_SHADOW_INT_STI;
1866         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1867                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1868
1869         return ret & mask;
1870 }
1871
1872 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1873 {
1874         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1875         u32 interruptibility = interruptibility_old;
1876
1877         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1878
1879         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1880                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1881         else if (mask & KVM_X86_SHADOW_INT_STI)
1882                 interruptibility |= GUEST_INTR_STATE_STI;
1883
1884         if ((interruptibility != interruptibility_old))
1885                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1886 }
1887
1888 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1889 {
1890         unsigned long rip;
1891
1892         rip = kvm_rip_read(vcpu);
1893         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1894         kvm_rip_write(vcpu, rip);
1895
1896         /* skipping an emulated instruction also counts */
1897         vmx_set_interrupt_shadow(vcpu, 0);
1898 }
1899
1900 /*
1901  * KVM wants to inject page-faults which it got to the guest. This function
1902  * checks whether in a nested guest, we need to inject them to L1 or L2.
1903  * This function assumes it is called with the exit reason in vmcs02 being
1904  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1905  * is running).
1906  */
1907 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1908 {
1909         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1910
1911         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1912         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1913                 return 0;
1914
1915         nested_vmx_vmexit(vcpu);
1916         return 1;
1917 }
1918
1919 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1920                                 bool has_error_code, u32 error_code,
1921                                 bool reinject)
1922 {
1923         struct vcpu_vmx *vmx = to_vmx(vcpu);
1924         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1925
1926         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1927             !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1928                 return;
1929
1930         if (has_error_code) {
1931                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1932                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1933         }
1934
1935         if (vmx->rmode.vm86_active) {
1936                 int inc_eip = 0;
1937                 if (kvm_exception_is_soft(nr))
1938                         inc_eip = vcpu->arch.event_exit_inst_len;
1939                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1940                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1941                 return;
1942         }
1943
1944         if (kvm_exception_is_soft(nr)) {
1945                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1946                              vmx->vcpu.arch.event_exit_inst_len);
1947                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1948         } else
1949                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1950
1951         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1952 }
1953
1954 static bool vmx_rdtscp_supported(void)
1955 {
1956         return cpu_has_vmx_rdtscp();
1957 }
1958
1959 static bool vmx_invpcid_supported(void)
1960 {
1961         return cpu_has_vmx_invpcid() && enable_ept;
1962 }
1963
1964 /*
1965  * Swap MSR entry in host/guest MSR entry array.
1966  */
1967 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1968 {
1969         struct shared_msr_entry tmp;
1970
1971         tmp = vmx->guest_msrs[to];
1972         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1973         vmx->guest_msrs[from] = tmp;
1974 }
1975
1976 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1977 {
1978         unsigned long *msr_bitmap;
1979
1980         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1981                 if (is_long_mode(vcpu))
1982                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1983                 else
1984                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1985         } else {
1986                 if (is_long_mode(vcpu))
1987                         msr_bitmap = vmx_msr_bitmap_longmode;
1988                 else
1989                         msr_bitmap = vmx_msr_bitmap_legacy;
1990         }
1991
1992         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1993 }
1994
1995 /*
1996  * Set up the vmcs to automatically save and restore system
1997  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1998  * mode, as fiddling with msrs is very expensive.
1999  */
2000 static void setup_msrs(struct vcpu_vmx *vmx)
2001 {
2002         int save_nmsrs, index;
2003
2004         save_nmsrs = 0;
2005 #ifdef CONFIG_X86_64
2006         if (is_long_mode(&vmx->vcpu)) {
2007                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2008                 if (index >= 0)
2009                         move_msr_up(vmx, index, save_nmsrs++);
2010                 index = __find_msr_index(vmx, MSR_LSTAR);
2011                 if (index >= 0)
2012                         move_msr_up(vmx, index, save_nmsrs++);
2013                 index = __find_msr_index(vmx, MSR_CSTAR);
2014                 if (index >= 0)
2015                         move_msr_up(vmx, index, save_nmsrs++);
2016                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2017                 if (index >= 0 && vmx->rdtscp_enabled)
2018                         move_msr_up(vmx, index, save_nmsrs++);
2019                 /*
2020                  * MSR_STAR is only needed on long mode guests, and only
2021                  * if efer.sce is enabled.
2022                  */
2023                 index = __find_msr_index(vmx, MSR_STAR);
2024                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2025                         move_msr_up(vmx, index, save_nmsrs++);
2026         }
2027 #endif
2028         index = __find_msr_index(vmx, MSR_EFER);
2029         if (index >= 0 && update_transition_efer(vmx, index))
2030                 move_msr_up(vmx, index, save_nmsrs++);
2031
2032         vmx->save_nmsrs = save_nmsrs;
2033
2034         if (cpu_has_vmx_msr_bitmap())
2035                 vmx_set_msr_bitmap(&vmx->vcpu);
2036 }
2037
2038 /*
2039  * reads and returns guest's timestamp counter "register"
2040  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2041  */
2042 static u64 guest_read_tsc(void)
2043 {
2044         u64 host_tsc, tsc_offset;
2045
2046         rdtscll(host_tsc);
2047         tsc_offset = vmcs_read64(TSC_OFFSET);
2048         return host_tsc + tsc_offset;
2049 }
2050
2051 /*
2052  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2053  * counter, even if a nested guest (L2) is currently running.
2054  */
2055 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2056 {
2057         u64 tsc_offset;
2058
2059         tsc_offset = is_guest_mode(vcpu) ?
2060                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2061                 vmcs_read64(TSC_OFFSET);
2062         return host_tsc + tsc_offset;
2063 }
2064
2065 /*
2066  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2067  * software catchup for faster rates on slower CPUs.
2068  */
2069 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2070 {
2071         if (!scale)
2072                 return;
2073
2074         if (user_tsc_khz > tsc_khz) {
2075                 vcpu->arch.tsc_catchup = 1;
2076                 vcpu->arch.tsc_always_catchup = 1;
2077         } else
2078                 WARN(1, "user requested TSC rate below hardware speed\n");
2079 }
2080
2081 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2082 {
2083         return vmcs_read64(TSC_OFFSET);
2084 }
2085
2086 /*
2087  * writes 'offset' into guest's timestamp counter offset register
2088  */
2089 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2090 {
2091         if (is_guest_mode(vcpu)) {
2092                 /*
2093                  * We're here if L1 chose not to trap WRMSR to TSC. According
2094                  * to the spec, this should set L1's TSC; The offset that L1
2095                  * set for L2 remains unchanged, and still needs to be added
2096                  * to the newly set TSC to get L2's TSC.
2097                  */
2098                 struct vmcs12 *vmcs12;
2099                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2100                 /* recalculate vmcs02.TSC_OFFSET: */
2101                 vmcs12 = get_vmcs12(vcpu);
2102                 vmcs_write64(TSC_OFFSET, offset +
2103                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2104                          vmcs12->tsc_offset : 0));
2105         } else {
2106                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2107                                            vmcs_read64(TSC_OFFSET), offset);
2108                 vmcs_write64(TSC_OFFSET, offset);
2109         }
2110 }
2111
2112 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2113 {
2114         u64 offset = vmcs_read64(TSC_OFFSET);
2115
2116         vmcs_write64(TSC_OFFSET, offset + adjustment);
2117         if (is_guest_mode(vcpu)) {
2118                 /* Even when running L2, the adjustment needs to apply to L1 */
2119                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2120         } else
2121                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2122                                            offset + adjustment);
2123 }
2124
2125 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2126 {
2127         return target_tsc - native_read_tsc();
2128 }
2129
2130 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2131 {
2132         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2133         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2134 }
2135
2136 /*
2137  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2138  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2139  * all guests if the "nested" module option is off, and can also be disabled
2140  * for a single guest by disabling its VMX cpuid bit.
2141  */
2142 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2143 {
2144         return nested && guest_cpuid_has_vmx(vcpu);
2145 }
2146
2147 /*
2148  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2149  * returned for the various VMX controls MSRs when nested VMX is enabled.
2150  * The same values should also be used to verify that vmcs12 control fields are
2151  * valid during nested entry from L1 to L2.
2152  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2153  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2154  * bit in the high half is on if the corresponding bit in the control field
2155  * may be on. See also vmx_control_verify().
2156  * TODO: allow these variables to be modified (downgraded) by module options
2157  * or other means.
2158  */
2159 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2160 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2161 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2162 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2163 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2164 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2165 static u32 nested_vmx_ept_caps;
2166 static __init void nested_vmx_setup_ctls_msrs(void)
2167 {
2168         /*
2169          * Note that as a general rule, the high half of the MSRs (bits in
2170          * the control fields which may be 1) should be initialized by the
2171          * intersection of the underlying hardware's MSR (i.e., features which
2172          * can be supported) and the list of features we want to expose -
2173          * because they are known to be properly supported in our code.
2174          * Also, usually, the low half of the MSRs (bits which must be 1) can
2175          * be set to 0, meaning that L1 may turn off any of these bits. The
2176          * reason is that if one of these bits is necessary, it will appear
2177          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2178          * fields of vmcs01 and vmcs02, will turn these bits off - and
2179          * nested_vmx_exit_handled() will not pass related exits to L1.
2180          * These rules have exceptions below.
2181          */
2182
2183         /* pin-based controls */
2184         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2185               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2186         /*
2187          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2188          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2189          */
2190         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2191         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2192                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2193                 PIN_BASED_VMX_PREEMPTION_TIMER;
2194         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2195
2196         /*
2197          * Exit controls
2198          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2199          * 17 must be 1.
2200          */
2201         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2202         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2203 #ifdef CONFIG_X86_64
2204         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2205 #else
2206         nested_vmx_exit_ctls_high = 0;
2207 #endif
2208         nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2209                                       VM_EXIT_LOAD_IA32_EFER);
2210
2211         /* entry controls */
2212         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2213                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2214         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2215         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2216         nested_vmx_entry_ctls_high &=
2217                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2218         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2219                                        VM_ENTRY_LOAD_IA32_EFER);
2220         /* cpu-based controls */
2221         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2222                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2223         nested_vmx_procbased_ctls_low = 0;
2224         nested_vmx_procbased_ctls_high &=
2225                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2226                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2227                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2228                 CPU_BASED_CR3_STORE_EXITING |
2229 #ifdef CONFIG_X86_64
2230                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2231 #endif
2232                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2233                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2234                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2235                 CPU_BASED_PAUSE_EXITING |
2236                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2237         /*
2238          * We can allow some features even when not supported by the
2239          * hardware. For example, L1 can specify an MSR bitmap - and we
2240          * can use it to avoid exits to L1 - even when L0 runs L2
2241          * without MSR bitmaps.
2242          */
2243         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2244
2245         /* secondary cpu-based controls */
2246         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2247                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2248         nested_vmx_secondary_ctls_low = 0;
2249         nested_vmx_secondary_ctls_high &=
2250                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2251                 SECONDARY_EXEC_WBINVD_EXITING;
2252
2253         if (enable_ept) {
2254                 /* nested EPT: emulate EPT also to L1 */
2255                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2256                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT;
2257                 nested_vmx_ept_caps |= VMX_EPT_INVEPT_BIT;
2258                 nested_vmx_ept_caps &= vmx_capability.ept;
2259                 /*
2260                  * Since invept is completely emulated we support both global
2261                  * and context invalidation independent of what host cpu
2262                  * supports
2263                  */
2264                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2265                         VMX_EPT_EXTENT_CONTEXT_BIT;
2266         } else
2267                 nested_vmx_ept_caps = 0;
2268
2269         /* miscellaneous data */
2270         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2271         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2272                 VMX_MISC_SAVE_EFER_LMA;
2273         nested_vmx_misc_high = 0;
2274 }
2275
2276 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2277 {
2278         /*
2279          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2280          */
2281         return ((control & high) | low) == control;
2282 }
2283
2284 static inline u64 vmx_control_msr(u32 low, u32 high)
2285 {
2286         return low | ((u64)high << 32);
2287 }
2288
2289 /*
2290  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2291  * also let it use VMX-specific MSRs.
2292  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2293  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2294  * like all other MSRs).
2295  */
2296 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2297 {
2298         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2299                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2300                 /*
2301                  * According to the spec, processors which do not support VMX
2302                  * should throw a #GP(0) when VMX capability MSRs are read.
2303                  */
2304                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2305                 return 1;
2306         }
2307
2308         switch (msr_index) {
2309         case MSR_IA32_FEATURE_CONTROL:
2310                 if (nested_vmx_allowed(vcpu)) {
2311                         *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2312                         break;
2313                 }
2314                 return 0;
2315         case MSR_IA32_VMX_BASIC:
2316                 /*
2317                  * This MSR reports some information about VMX support. We
2318                  * should return information about the VMX we emulate for the
2319                  * guest, and the VMCS structure we give it - not about the
2320                  * VMX support of the underlying hardware.
2321                  */
2322                 *pdata = VMCS12_REVISION |
2323                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2324                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2325                 break;
2326         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2327         case MSR_IA32_VMX_PINBASED_CTLS:
2328                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2329                                         nested_vmx_pinbased_ctls_high);
2330                 break;
2331         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2332         case MSR_IA32_VMX_PROCBASED_CTLS:
2333                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2334                                         nested_vmx_procbased_ctls_high);
2335                 break;
2336         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2337         case MSR_IA32_VMX_EXIT_CTLS:
2338                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2339                                         nested_vmx_exit_ctls_high);
2340                 break;
2341         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2342         case MSR_IA32_VMX_ENTRY_CTLS:
2343                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2344                                         nested_vmx_entry_ctls_high);
2345                 break;
2346         case MSR_IA32_VMX_MISC:
2347                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2348                                          nested_vmx_misc_high);
2349                 break;
2350         /*
2351          * These MSRs specify bits which the guest must keep fixed (on or off)
2352          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2353          * We picked the standard core2 setting.
2354          */
2355 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2356 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2357         case MSR_IA32_VMX_CR0_FIXED0:
2358                 *pdata = VMXON_CR0_ALWAYSON;
2359                 break;
2360         case MSR_IA32_VMX_CR0_FIXED1:
2361                 *pdata = -1ULL;
2362                 break;
2363         case MSR_IA32_VMX_CR4_FIXED0:
2364                 *pdata = VMXON_CR4_ALWAYSON;
2365                 break;
2366         case MSR_IA32_VMX_CR4_FIXED1:
2367                 *pdata = -1ULL;
2368                 break;
2369         case MSR_IA32_VMX_VMCS_ENUM:
2370                 *pdata = 0x1f;
2371                 break;
2372         case MSR_IA32_VMX_PROCBASED_CTLS2:
2373                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2374                                         nested_vmx_secondary_ctls_high);
2375                 break;
2376         case MSR_IA32_VMX_EPT_VPID_CAP:
2377                 /* Currently, no nested vpid support */
2378                 *pdata = nested_vmx_ept_caps;
2379                 break;
2380         default:
2381                 return 0;
2382         }
2383
2384         return 1;
2385 }
2386
2387 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2388 {
2389         u32 msr_index = msr_info->index;
2390         u64 data = msr_info->data;
2391         bool host_initialized = msr_info->host_initiated;
2392
2393         if (!nested_vmx_allowed(vcpu))
2394                 return 0;
2395
2396         if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2397                 if (!host_initialized &&
2398                                 to_vmx(vcpu)->nested.msr_ia32_feature_control
2399                                 & FEATURE_CONTROL_LOCKED)
2400                         return 0;
2401                 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
2402                 return 1;
2403         }
2404
2405         /*
2406          * No need to treat VMX capability MSRs specially: If we don't handle
2407          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2408          */
2409         return 0;
2410 }
2411
2412 /*
2413  * Reads an msr value (of 'msr_index') into 'pdata'.
2414  * Returns 0 on success, non-0 otherwise.
2415  * Assumes vcpu_load() was already called.
2416  */
2417 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2418 {
2419         u64 data;
2420         struct shared_msr_entry *msr;
2421
2422         if (!pdata) {
2423                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2424                 return -EINVAL;
2425         }
2426
2427         switch (msr_index) {
2428 #ifdef CONFIG_X86_64
2429         case MSR_FS_BASE:
2430                 data = vmcs_readl(GUEST_FS_BASE);
2431                 break;
2432         case MSR_GS_BASE:
2433                 data = vmcs_readl(GUEST_GS_BASE);
2434                 break;
2435         case MSR_KERNEL_GS_BASE:
2436                 vmx_load_host_state(to_vmx(vcpu));
2437                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2438                 break;
2439 #endif
2440         case MSR_EFER:
2441                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2442         case MSR_IA32_TSC:
2443                 data = guest_read_tsc();
2444                 break;
2445         case MSR_IA32_SYSENTER_CS:
2446                 data = vmcs_read32(GUEST_SYSENTER_CS);
2447                 break;
2448         case MSR_IA32_SYSENTER_EIP:
2449                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2450                 break;
2451         case MSR_IA32_SYSENTER_ESP:
2452                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2453                 break;
2454         case MSR_TSC_AUX:
2455                 if (!to_vmx(vcpu)->rdtscp_enabled)
2456                         return 1;
2457                 /* Otherwise falls through */
2458         default:
2459                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2460                         return 0;
2461                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2462                 if (msr) {
2463                         data = msr->data;
2464                         break;
2465                 }
2466                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2467         }
2468
2469         *pdata = data;
2470         return 0;
2471 }
2472
2473 /*
2474  * Writes msr value into into the appropriate "register".
2475  * Returns 0 on success, non-0 otherwise.
2476  * Assumes vcpu_load() was already called.
2477  */
2478 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2479 {
2480         struct vcpu_vmx *vmx = to_vmx(vcpu);
2481         struct shared_msr_entry *msr;
2482         int ret = 0;
2483         u32 msr_index = msr_info->index;
2484         u64 data = msr_info->data;
2485
2486         switch (msr_index) {
2487         case MSR_EFER:
2488                 ret = kvm_set_msr_common(vcpu, msr_info);
2489                 break;
2490 #ifdef CONFIG_X86_64
2491         case MSR_FS_BASE:
2492                 vmx_segment_cache_clear(vmx);
2493                 vmcs_writel(GUEST_FS_BASE, data);
2494                 break;
2495         case MSR_GS_BASE:
2496                 vmx_segment_cache_clear(vmx);
2497                 vmcs_writel(GUEST_GS_BASE, data);
2498                 break;
2499         case MSR_KERNEL_GS_BASE:
2500                 vmx_load_host_state(vmx);
2501                 vmx->msr_guest_kernel_gs_base = data;
2502                 break;
2503 #endif
2504         case MSR_IA32_SYSENTER_CS:
2505                 vmcs_write32(GUEST_SYSENTER_CS, data);
2506                 break;
2507         case MSR_IA32_SYSENTER_EIP:
2508                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2509                 break;
2510         case MSR_IA32_SYSENTER_ESP:
2511                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2512                 break;
2513         case MSR_IA32_TSC:
2514                 kvm_write_tsc(vcpu, msr_info);
2515                 break;
2516         case MSR_IA32_CR_PAT:
2517                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2518                         vmcs_write64(GUEST_IA32_PAT, data);
2519                         vcpu->arch.pat = data;
2520                         break;
2521                 }
2522                 ret = kvm_set_msr_common(vcpu, msr_info);
2523                 break;
2524         case MSR_IA32_TSC_ADJUST:
2525                 ret = kvm_set_msr_common(vcpu, msr_info);
2526                 break;
2527         case MSR_TSC_AUX:
2528                 if (!vmx->rdtscp_enabled)
2529                         return 1;
2530                 /* Check reserved bit, higher 32 bits should be zero */
2531                 if ((data >> 32) != 0)
2532                         return 1;
2533                 /* Otherwise falls through */
2534         default:
2535                 if (vmx_set_vmx_msr(vcpu, msr_info))
2536                         break;
2537                 msr = find_msr_entry(vmx, msr_index);
2538                 if (msr) {
2539                         msr->data = data;
2540                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2541                                 preempt_disable();
2542                                 kvm_set_shared_msr(msr->index, msr->data,
2543                                                    msr->mask);
2544                                 preempt_enable();
2545                         }
2546                         break;
2547                 }
2548                 ret = kvm_set_msr_common(vcpu, msr_info);
2549         }
2550
2551         return ret;
2552 }
2553
2554 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2555 {
2556         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2557         switch (reg) {
2558         case VCPU_REGS_RSP:
2559                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2560                 break;
2561         case VCPU_REGS_RIP:
2562                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2563                 break;
2564         case VCPU_EXREG_PDPTR:
2565                 if (enable_ept)
2566                         ept_save_pdptrs(vcpu);
2567                 break;
2568         default:
2569                 break;
2570         }
2571 }
2572
2573 static __init int cpu_has_kvm_support(void)
2574 {
2575         return cpu_has_vmx();
2576 }
2577
2578 static __init int vmx_disabled_by_bios(void)
2579 {
2580         u64 msr;
2581
2582         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2583         if (msr & FEATURE_CONTROL_LOCKED) {
2584                 /* launched w/ TXT and VMX disabled */
2585                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2586                         && tboot_enabled())
2587                         return 1;
2588                 /* launched w/o TXT and VMX only enabled w/ TXT */
2589                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2590                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2591                         && !tboot_enabled()) {
2592                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2593                                 "activate TXT before enabling KVM\n");
2594                         return 1;
2595                 }
2596                 /* launched w/o TXT and VMX disabled */
2597                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2598                         && !tboot_enabled())
2599                         return 1;
2600         }
2601
2602         return 0;
2603 }
2604
2605 static void kvm_cpu_vmxon(u64 addr)
2606 {
2607         asm volatile (ASM_VMX_VMXON_RAX
2608                         : : "a"(&addr), "m"(addr)
2609                         : "memory", "cc");
2610 }
2611
2612 static int hardware_enable(void *garbage)
2613 {
2614         int cpu = raw_smp_processor_id();
2615         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2616         u64 old, test_bits;
2617
2618         if (read_cr4() & X86_CR4_VMXE)
2619                 return -EBUSY;
2620
2621         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2622
2623         /*
2624          * Now we can enable the vmclear operation in kdump
2625          * since the loaded_vmcss_on_cpu list on this cpu
2626          * has been initialized.
2627          *
2628          * Though the cpu is not in VMX operation now, there
2629          * is no problem to enable the vmclear operation
2630          * for the loaded_vmcss_on_cpu list is empty!
2631          */
2632         crash_enable_local_vmclear(cpu);
2633
2634         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2635
2636         test_bits = FEATURE_CONTROL_LOCKED;
2637         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2638         if (tboot_enabled())
2639                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2640
2641         if ((old & test_bits) != test_bits) {
2642                 /* enable and lock */
2643                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2644         }
2645         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2646
2647         if (vmm_exclusive) {
2648                 kvm_cpu_vmxon(phys_addr);
2649                 ept_sync_global();
2650         }
2651
2652         native_store_gdt(&__get_cpu_var(host_gdt));
2653
2654         return 0;
2655 }
2656
2657 static void vmclear_local_loaded_vmcss(void)
2658 {
2659         int cpu = raw_smp_processor_id();
2660         struct loaded_vmcs *v, *n;
2661
2662         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2663                                  loaded_vmcss_on_cpu_link)
2664                 __loaded_vmcs_clear(v);
2665 }
2666
2667
2668 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2669  * tricks.
2670  */
2671 static void kvm_cpu_vmxoff(void)
2672 {
2673         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2674 }
2675
2676 static void hardware_disable(void *garbage)
2677 {
2678         if (vmm_exclusive) {
2679                 vmclear_local_loaded_vmcss();
2680                 kvm_cpu_vmxoff();
2681         }
2682         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2683 }
2684
2685 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2686                                       u32 msr, u32 *result)
2687 {
2688         u32 vmx_msr_low, vmx_msr_high;
2689         u32 ctl = ctl_min | ctl_opt;
2690
2691         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2692
2693         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2694         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2695
2696         /* Ensure minimum (required) set of control bits are supported. */
2697         if (ctl_min & ~ctl)
2698                 return -EIO;
2699
2700         *result = ctl;
2701         return 0;
2702 }
2703
2704 static __init bool allow_1_setting(u32 msr, u32 ctl)
2705 {
2706         u32 vmx_msr_low, vmx_msr_high;
2707
2708         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2709         return vmx_msr_high & ctl;
2710 }
2711
2712 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2713 {
2714         u32 vmx_msr_low, vmx_msr_high;
2715         u32 min, opt, min2, opt2;
2716         u32 _pin_based_exec_control = 0;
2717         u32 _cpu_based_exec_control = 0;
2718         u32 _cpu_based_2nd_exec_control = 0;
2719         u32 _vmexit_control = 0;
2720         u32 _vmentry_control = 0;
2721
2722         min = CPU_BASED_HLT_EXITING |
2723 #ifdef CONFIG_X86_64
2724               CPU_BASED_CR8_LOAD_EXITING |
2725               CPU_BASED_CR8_STORE_EXITING |
2726 #endif
2727               CPU_BASED_CR3_LOAD_EXITING |
2728               CPU_BASED_CR3_STORE_EXITING |
2729               CPU_BASED_USE_IO_BITMAPS |
2730               CPU_BASED_MOV_DR_EXITING |
2731               CPU_BASED_USE_TSC_OFFSETING |
2732               CPU_BASED_MWAIT_EXITING |
2733               CPU_BASED_MONITOR_EXITING |
2734               CPU_BASED_INVLPG_EXITING |
2735               CPU_BASED_RDPMC_EXITING;
2736
2737         opt = CPU_BASED_TPR_SHADOW |
2738               CPU_BASED_USE_MSR_BITMAPS |
2739               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2740         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2741                                 &_cpu_based_exec_control) < 0)
2742                 return -EIO;
2743 #ifdef CONFIG_X86_64
2744         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2745                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2746                                            ~CPU_BASED_CR8_STORE_EXITING;
2747 #endif
2748         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2749                 min2 = 0;
2750                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2751                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2752                         SECONDARY_EXEC_WBINVD_EXITING |
2753                         SECONDARY_EXEC_ENABLE_VPID |
2754                         SECONDARY_EXEC_ENABLE_EPT |
2755                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2756                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2757                         SECONDARY_EXEC_RDTSCP |
2758                         SECONDARY_EXEC_ENABLE_INVPCID |
2759                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2760                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2761                         SECONDARY_EXEC_SHADOW_VMCS;
2762                 if (adjust_vmx_controls(min2, opt2,
2763                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2764                                         &_cpu_based_2nd_exec_control) < 0)
2765                         return -EIO;
2766         }
2767 #ifndef CONFIG_X86_64
2768         if (!(_cpu_based_2nd_exec_control &
2769                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2770                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2771 #endif
2772
2773         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2774                 _cpu_based_2nd_exec_control &= ~(
2775                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2776                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2777                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2778
2779         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2780                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2781                    enabled */
2782                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2783                                              CPU_BASED_CR3_STORE_EXITING |
2784                                              CPU_BASED_INVLPG_EXITING);
2785                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2786                       vmx_capability.ept, vmx_capability.vpid);
2787         }
2788
2789         min = 0;
2790 #ifdef CONFIG_X86_64
2791         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2792 #endif
2793         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2794                 VM_EXIT_ACK_INTR_ON_EXIT;
2795         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2796                                 &_vmexit_control) < 0)
2797                 return -EIO;
2798
2799         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2800         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2801         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2802                                 &_pin_based_exec_control) < 0)
2803                 return -EIO;
2804
2805         if (!(_cpu_based_2nd_exec_control &
2806                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2807                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2808                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2809
2810         min = 0;
2811         opt = VM_ENTRY_LOAD_IA32_PAT;
2812         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2813                                 &_vmentry_control) < 0)
2814                 return -EIO;
2815
2816         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2817
2818         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2819         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2820                 return -EIO;
2821
2822 #ifdef CONFIG_X86_64
2823         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2824         if (vmx_msr_high & (1u<<16))
2825                 return -EIO;
2826 #endif
2827
2828         /* Require Write-Back (WB) memory type for VMCS accesses. */
2829         if (((vmx_msr_high >> 18) & 15) != 6)
2830                 return -EIO;
2831
2832         vmcs_conf->size = vmx_msr_high & 0x1fff;
2833         vmcs_conf->order = get_order(vmcs_config.size);
2834         vmcs_conf->revision_id = vmx_msr_low;
2835
2836         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2837         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2838         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2839         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2840         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2841
2842         cpu_has_load_ia32_efer =
2843                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2844                                 VM_ENTRY_LOAD_IA32_EFER)
2845                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2846                                    VM_EXIT_LOAD_IA32_EFER);
2847
2848         cpu_has_load_perf_global_ctrl =
2849                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2850                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2851                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2852                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2853
2854         /*
2855          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2856          * but due to arrata below it can't be used. Workaround is to use
2857          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2858          *
2859          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2860          *
2861          * AAK155             (model 26)
2862          * AAP115             (model 30)
2863          * AAT100             (model 37)
2864          * BC86,AAY89,BD102   (model 44)
2865          * BA97               (model 46)
2866          *
2867          */
2868         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2869                 switch (boot_cpu_data.x86_model) {
2870                 case 26:
2871                 case 30:
2872                 case 37:
2873                 case 44:
2874                 case 46:
2875                         cpu_has_load_perf_global_ctrl = false;
2876                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2877                                         "does not work properly. Using workaround\n");
2878                         break;
2879                 default:
2880                         break;
2881                 }
2882         }
2883
2884         return 0;
2885 }
2886
2887 static struct vmcs *alloc_vmcs_cpu(int cpu)
2888 {
2889         int node = cpu_to_node(cpu);
2890         struct page *pages;
2891         struct vmcs *vmcs;
2892
2893         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2894         if (!pages)
2895                 return NULL;
2896         vmcs = page_address(pages);
2897         memset(vmcs, 0, vmcs_config.size);
2898         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2899         return vmcs;
2900 }
2901
2902 static struct vmcs *alloc_vmcs(void)
2903 {
2904         return alloc_vmcs_cpu(raw_smp_processor_id());
2905 }
2906
2907 static void free_vmcs(struct vmcs *vmcs)
2908 {
2909         free_pages((unsigned long)vmcs, vmcs_config.order);
2910 }
2911
2912 /*
2913  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2914  */
2915 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2916 {
2917         if (!loaded_vmcs->vmcs)
2918                 return;
2919         loaded_vmcs_clear(loaded_vmcs);
2920         free_vmcs(loaded_vmcs->vmcs);
2921         loaded_vmcs->vmcs = NULL;
2922 }
2923
2924 static void free_kvm_area(void)
2925 {
2926         int cpu;
2927
2928         for_each_possible_cpu(cpu) {
2929                 free_vmcs(per_cpu(vmxarea, cpu));
2930                 per_cpu(vmxarea, cpu) = NULL;
2931         }
2932 }
2933
2934 static __init int alloc_kvm_area(void)
2935 {
2936         int cpu;
2937
2938         for_each_possible_cpu(cpu) {
2939                 struct vmcs *vmcs;
2940
2941                 vmcs = alloc_vmcs_cpu(cpu);
2942                 if (!vmcs) {
2943                         free_kvm_area();
2944                         return -ENOMEM;
2945                 }
2946
2947                 per_cpu(vmxarea, cpu) = vmcs;
2948         }
2949         return 0;
2950 }
2951
2952 static __init int hardware_setup(void)
2953 {
2954         if (setup_vmcs_config(&vmcs_config) < 0)
2955                 return -EIO;
2956
2957         if (boot_cpu_has(X86_FEATURE_NX))
2958                 kvm_enable_efer_bits(EFER_NX);
2959
2960         if (!cpu_has_vmx_vpid())
2961                 enable_vpid = 0;
2962         if (!cpu_has_vmx_shadow_vmcs())
2963                 enable_shadow_vmcs = 0;
2964
2965         if (!cpu_has_vmx_ept() ||
2966             !cpu_has_vmx_ept_4levels()) {
2967                 enable_ept = 0;
2968                 enable_unrestricted_guest = 0;
2969                 enable_ept_ad_bits = 0;
2970         }
2971
2972         if (!cpu_has_vmx_ept_ad_bits())
2973                 enable_ept_ad_bits = 0;
2974
2975         if (!cpu_has_vmx_unrestricted_guest())
2976                 enable_unrestricted_guest = 0;
2977
2978         if (!cpu_has_vmx_flexpriority())
2979                 flexpriority_enabled = 0;
2980
2981         if (!cpu_has_vmx_tpr_shadow())
2982                 kvm_x86_ops->update_cr8_intercept = NULL;
2983
2984         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2985                 kvm_disable_largepages();
2986
2987         if (!cpu_has_vmx_ple())
2988                 ple_gap = 0;
2989
2990         if (!cpu_has_vmx_apicv())
2991                 enable_apicv = 0;
2992
2993         if (enable_apicv)
2994                 kvm_x86_ops->update_cr8_intercept = NULL;
2995         else {
2996                 kvm_x86_ops->hwapic_irr_update = NULL;
2997                 kvm_x86_ops->deliver_posted_interrupt = NULL;
2998                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2999         }
3000
3001         if (nested)
3002                 nested_vmx_setup_ctls_msrs();
3003
3004         return alloc_kvm_area();
3005 }
3006
3007 static __exit void hardware_unsetup(void)
3008 {
3009         free_kvm_area();
3010 }
3011
3012 static bool emulation_required(struct kvm_vcpu *vcpu)
3013 {
3014         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3015 }
3016
3017 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3018                 struct kvm_segment *save)
3019 {
3020         if (!emulate_invalid_guest_state) {
3021                 /*
3022                  * CS and SS RPL should be equal during guest entry according
3023                  * to VMX spec, but in reality it is not always so. Since vcpu
3024                  * is in the middle of the transition from real mode to
3025                  * protected mode it is safe to assume that RPL 0 is a good
3026                  * default value.
3027                  */
3028                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3029                         save->selector &= ~SELECTOR_RPL_MASK;
3030                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3031                 save->s = 1;
3032         }
3033         vmx_set_segment(vcpu, save, seg);
3034 }
3035
3036 static void enter_pmode(struct kvm_vcpu *vcpu)
3037 {
3038         unsigned long flags;
3039         struct vcpu_vmx *vmx = to_vmx(vcpu);
3040
3041         /*
3042          * Update real mode segment cache. It may be not up-to-date if sement
3043          * register was written while vcpu was in a guest mode.
3044          */
3045         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3046         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3047         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3048         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3049         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3050         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3051
3052         vmx->rmode.vm86_active = 0;
3053
3054         vmx_segment_cache_clear(vmx);
3055
3056         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3057
3058         flags = vmcs_readl(GUEST_RFLAGS);
3059         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3060         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3061         vmcs_writel(GUEST_RFLAGS, flags);
3062
3063         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3064                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3065
3066         update_exception_bitmap(vcpu);
3067
3068         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3069         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3070         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3071         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3072         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3073         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3074
3075         /* CPL is always 0 when CPU enters protected mode */
3076         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3077         vmx->cpl = 0;
3078 }
3079
3080 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3081 {
3082         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3083         struct kvm_segment var = *save;
3084
3085         var.dpl = 0x3;
3086         if (seg == VCPU_SREG_CS)
3087                 var.type = 0x3;
3088
3089         if (!emulate_invalid_guest_state) {
3090                 var.selector = var.base >> 4;
3091                 var.base = var.base & 0xffff0;
3092                 var.limit = 0xffff;
3093                 var.g = 0;
3094                 var.db = 0;
3095                 var.present = 1;
3096                 var.s = 1;
3097                 var.l = 0;
3098                 var.unusable = 0;
3099                 var.type = 0x3;
3100                 var.avl = 0;
3101                 if (save->base & 0xf)
3102                         printk_once(KERN_WARNING "kvm: segment base is not "
3103                                         "paragraph aligned when entering "
3104                                         "protected mode (seg=%d)", seg);
3105         }
3106
3107         vmcs_write16(sf->selector, var.selector);
3108         vmcs_write32(sf->base, var.base);
3109         vmcs_write32(sf->limit, var.limit);
3110         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3111 }
3112
3113 static void enter_rmode(struct kvm_vcpu *vcpu)
3114 {
3115         unsigned long flags;
3116         struct vcpu_vmx *vmx = to_vmx(vcpu);
3117
3118         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3119         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3120         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3121         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3122         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3123         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3124         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3125
3126         vmx->rmode.vm86_active = 1;
3127
3128         /*
3129          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3130          * vcpu. Warn the user that an update is overdue.
3131          */
3132         if (!vcpu->kvm->arch.tss_addr)
3133                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3134                              "called before entering vcpu\n");
3135
3136         vmx_segment_cache_clear(vmx);
3137
3138         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3139         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3140         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3141
3142         flags = vmcs_readl(GUEST_RFLAGS);
3143         vmx->rmode.save_rflags = flags;
3144
3145         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3146
3147         vmcs_writel(GUEST_RFLAGS, flags);
3148         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3149         update_exception_bitmap(vcpu);
3150
3151         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3152         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3153         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3154         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3155         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3156         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3157
3158         kvm_mmu_reset_context(vcpu);
3159 }
3160
3161 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3162 {
3163         struct vcpu_vmx *vmx = to_vmx(vcpu);
3164         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3165
3166         if (!msr)
3167                 return;
3168
3169         /*
3170          * Force kernel_gs_base reloading before EFER changes, as control
3171          * of this msr depends on is_long_mode().
3172          */
3173         vmx_load_host_state(to_vmx(vcpu));
3174         vcpu->arch.efer = efer;
3175         if (efer & EFER_LMA) {
3176                 vmcs_write32(VM_ENTRY_CONTROLS,
3177                              vmcs_read32(VM_ENTRY_CONTROLS) |
3178                              VM_ENTRY_IA32E_MODE);
3179                 msr->data = efer;
3180         } else {
3181                 vmcs_write32(VM_ENTRY_CONTROLS,
3182                              vmcs_read32(VM_ENTRY_CONTROLS) &
3183                              ~VM_ENTRY_IA32E_MODE);
3184
3185                 msr->data = efer & ~EFER_LME;
3186         }
3187         setup_msrs(vmx);
3188 }
3189
3190 #ifdef CONFIG_X86_64
3191
3192 static void enter_lmode(struct kvm_vcpu *vcpu)
3193 {
3194         u32 guest_tr_ar;
3195
3196         vmx_segment_cache_clear(to_vmx(vcpu));
3197
3198         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3199         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3200                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3201                                      __func__);
3202                 vmcs_write32(GUEST_TR_AR_BYTES,
3203                              (guest_tr_ar & ~AR_TYPE_MASK)
3204                              | AR_TYPE_BUSY_64_TSS);
3205         }
3206         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3207 }
3208
3209 static void exit_lmode(struct kvm_vcpu *vcpu)
3210 {
3211         vmcs_write32(VM_ENTRY_CONTROLS,
3212                      vmcs_read32(VM_ENTRY_CONTROLS)
3213                      & ~VM_ENTRY_IA32E_MODE);
3214         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3215 }
3216
3217 #endif
3218
3219 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3220 {
3221         vpid_sync_context(to_vmx(vcpu));
3222         if (enable_ept) {
3223                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3224                         return;
3225                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3226         }
3227 }
3228
3229 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3230 {
3231         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3232
3233         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3234         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3235 }
3236
3237 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3238 {
3239         if (enable_ept && is_paging(vcpu))
3240                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3241         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3242 }
3243
3244 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3245 {
3246         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3247
3248         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3249         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3250 }
3251
3252 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3253 {
3254         if (!test_bit(VCPU_EXREG_PDPTR,
3255                       (unsigned long *)&vcpu->arch.regs_dirty))
3256                 return;
3257
3258         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3259                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3260                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3261                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3262                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3263         }
3264 }
3265
3266 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3267 {
3268         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3269                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3270                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3271                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3272                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3273         }
3274
3275         __set_bit(VCPU_EXREG_PDPTR,
3276                   (unsigned long *)&vcpu->arch.regs_avail);
3277         __set_bit(VCPU_EXREG_PDPTR,
3278                   (unsigned long *)&vcpu->arch.regs_dirty);
3279 }
3280
3281 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3282
3283 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3284                                         unsigned long cr0,
3285                                         struct kvm_vcpu *vcpu)
3286 {
3287         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3288                 vmx_decache_cr3(vcpu);
3289         if (!(cr0 & X86_CR0_PG)) {
3290                 /* From paging/starting to nonpaging */
3291                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3292                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3293                              (CPU_BASED_CR3_LOAD_EXITING |
3294                               CPU_BASED_CR3_STORE_EXITING));
3295                 vcpu->arch.cr0 = cr0;
3296                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3297         } else if (!is_paging(vcpu)) {
3298                 /* From nonpaging to paging */
3299                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3300                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3301                              ~(CPU_BASED_CR3_LOAD_EXITING |
3302                                CPU_BASED_CR3_STORE_EXITING));
3303                 vcpu->arch.cr0 = cr0;
3304                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3305         }
3306
3307         if (!(cr0 & X86_CR0_WP))
3308                 *hw_cr0 &= ~X86_CR0_WP;
3309 }
3310
3311 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3312 {
3313         struct vcpu_vmx *vmx = to_vmx(vcpu);
3314         unsigned long hw_cr0;
3315
3316         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3317         if (enable_unrestricted_guest)
3318                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3319         else {
3320                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3321
3322                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3323                         enter_pmode(vcpu);
3324
3325                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3326                         enter_rmode(vcpu);
3327         }
3328
3329 #ifdef CONFIG_X86_64
3330         if (vcpu->arch.efer & EFER_LME) {
3331                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3332                         enter_lmode(vcpu);
3333                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3334                         exit_lmode(vcpu);
3335         }
3336 #endif
3337
3338         if (enable_ept)
3339                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3340
3341         if (!vcpu->fpu_active)
3342                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3343
3344         vmcs_writel(CR0_READ_SHADOW, cr0);
3345         vmcs_writel(GUEST_CR0, hw_cr0);
3346         vcpu->arch.cr0 = cr0;
3347
3348         /* depends on vcpu->arch.cr0 to be set to a new value */
3349         vmx->emulation_required = emulation_required(vcpu);
3350 }
3351
3352 static u64 construct_eptp(unsigned long root_hpa)
3353 {
3354         u64 eptp;
3355
3356         /* TODO write the value reading from MSR */
3357         eptp = VMX_EPT_DEFAULT_MT |
3358                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3359         if (enable_ept_ad_bits)
3360                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3361         eptp |= (root_hpa & PAGE_MASK);
3362
3363         return eptp;
3364 }
3365
3366 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3367 {
3368         unsigned long guest_cr3;
3369         u64 eptp;
3370
3371         guest_cr3 = cr3;
3372         if (enable_ept) {
3373                 eptp = construct_eptp(cr3);
3374                 vmcs_write64(EPT_POINTER, eptp);
3375                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3376                         vcpu->kvm->arch.ept_identity_map_addr;
3377                 ept_load_pdptrs(vcpu);
3378         }
3379
3380         vmx_flush_tlb(vcpu);
3381         vmcs_writel(GUEST_CR3, guest_cr3);
3382 }
3383
3384 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3385 {
3386         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3387                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3388
3389         if (cr4 & X86_CR4_VMXE) {
3390                 /*
3391                  * To use VMXON (and later other VMX instructions), a guest
3392                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3393                  * So basically the check on whether to allow nested VMX
3394                  * is here.
3395                  */
3396                 if (!nested_vmx_allowed(vcpu))
3397                         return 1;
3398         }
3399         if (to_vmx(vcpu)->nested.vmxon &&
3400             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3401                 return 1;
3402
3403         vcpu->arch.cr4 = cr4;
3404         if (enable_ept) {
3405                 if (!is_paging(vcpu)) {
3406                         hw_cr4 &= ~X86_CR4_PAE;
3407                         hw_cr4 |= X86_CR4_PSE;
3408                         /*
3409                          * SMEP is disabled if CPU is in non-paging mode in
3410                          * hardware. However KVM always uses paging mode to
3411                          * emulate guest non-paging mode with TDP.
3412                          * To emulate this behavior, SMEP needs to be manually
3413                          * disabled when guest switches to non-paging mode.
3414                          */
3415                         hw_cr4 &= ~X86_CR4_SMEP;
3416                 } else if (!(cr4 & X86_CR4_PAE)) {
3417                         hw_cr4 &= ~X86_CR4_PAE;
3418                 }
3419         }
3420
3421         vmcs_writel(CR4_READ_SHADOW, cr4);
3422         vmcs_writel(GUEST_CR4, hw_cr4);
3423         return 0;
3424 }
3425
3426 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3427                             struct kvm_segment *var, int seg)
3428 {
3429         struct vcpu_vmx *vmx = to_vmx(vcpu);
3430         u32 ar;
3431
3432         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3433                 *var = vmx->rmode.segs[seg];
3434                 if (seg == VCPU_SREG_TR
3435                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3436                         return;
3437                 var->base = vmx_read_guest_seg_base(vmx, seg);
3438                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3439                 return;
3440         }
3441         var->base = vmx_read_guest_seg_base(vmx, seg);
3442         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3443         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3444         ar = vmx_read_guest_seg_ar(vmx, seg);
3445         var->unusable = (ar >> 16) & 1;
3446         var->type = ar & 15;
3447         var->s = (ar >> 4) & 1;
3448         var->dpl = (ar >> 5) & 3;
3449         /*
3450          * Some userspaces do not preserve unusable property. Since usable
3451          * segment has to be present according to VMX spec we can use present
3452          * property to amend userspace bug by making unusable segment always
3453          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3454          * segment as unusable.
3455          */
3456         var->present = !var->unusable;
3457         var->avl = (ar >> 12) & 1;
3458         var->l = (ar >> 13) & 1;
3459         var->db = (ar >> 14) & 1;
3460         var->g = (ar >> 15) & 1;
3461 }
3462
3463 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3464 {
3465         struct kvm_segment s;
3466
3467         if (to_vmx(vcpu)->rmode.vm86_active) {
3468                 vmx_get_segment(vcpu, &s, seg);
3469                 return s.base;
3470         }
3471         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3472 }
3473
3474 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3475 {
3476         struct vcpu_vmx *vmx = to_vmx(vcpu);
3477
3478         if (!is_protmode(vcpu))
3479                 return 0;
3480
3481         if (!is_long_mode(vcpu)
3482             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3483                 return 3;
3484
3485         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3486                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3487                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3488         }
3489
3490         return vmx->cpl;
3491 }
3492
3493
3494 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3495 {
3496         u32 ar;
3497
3498         if (var->unusable || !var->present)
3499                 ar = 1 << 16;
3500         else {
3501                 ar = var->type & 15;
3502                 ar |= (var->s & 1) << 4;
3503                 ar |= (var->dpl & 3) << 5;
3504                 ar |= (var->present & 1) << 7;
3505                 ar |= (var->avl & 1) << 12;
3506                 ar |= (var->l & 1) << 13;
3507                 ar |= (var->db & 1) << 14;
3508                 ar |= (var->g & 1) << 15;
3509         }
3510
3511         return ar;
3512 }
3513
3514 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3515                             struct kvm_segment *var, int seg)
3516 {
3517         struct vcpu_vmx *vmx = to_vmx(vcpu);
3518         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3519
3520         vmx_segment_cache_clear(vmx);
3521         if (seg == VCPU_SREG_CS)
3522                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3523
3524         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3525                 vmx->rmode.segs[seg] = *var;
3526                 if (seg == VCPU_SREG_TR)
3527                         vmcs_write16(sf->selector, var->selector);
3528                 else if (var->s)
3529                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3530                 goto out;
3531         }
3532
3533         vmcs_writel(sf->base, var->base);
3534         vmcs_write32(sf->limit, var->limit);
3535         vmcs_write16(sf->selector, var->selector);
3536
3537         /*
3538          *   Fix the "Accessed" bit in AR field of segment registers for older
3539          * qemu binaries.
3540          *   IA32 arch specifies that at the time of processor reset the
3541          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3542          * is setting it to 0 in the userland code. This causes invalid guest
3543          * state vmexit when "unrestricted guest" mode is turned on.
3544          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3545          * tree. Newer qemu binaries with that qemu fix would not need this
3546          * kvm hack.
3547          */
3548         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3549                 var->type |= 0x1; /* Accessed */
3550
3551         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3552
3553 out:
3554         vmx->emulation_required |= emulation_required(vcpu);
3555 }
3556
3557 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3558 {
3559         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3560
3561         *db = (ar >> 14) & 1;
3562         *l = (ar >> 13) & 1;
3563 }
3564
3565 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3566 {
3567         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3568         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3569 }
3570
3571 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3572 {
3573         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3574         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3575 }
3576
3577 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3578 {
3579         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3580         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3581 }
3582
3583 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3584 {
3585         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3586         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3587 }
3588
3589 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3590 {
3591         struct kvm_segment var;
3592         u32 ar;
3593
3594         vmx_get_segment(vcpu, &var, seg);
3595         var.dpl = 0x3;
3596         if (seg == VCPU_SREG_CS)
3597                 var.type = 0x3;
3598         ar = vmx_segment_access_rights(&var);
3599
3600         if (var.base != (var.selector << 4))
3601                 return false;
3602         if (var.limit != 0xffff)
3603                 return false;
3604         if (ar != 0xf3)
3605                 return false;
3606
3607         return true;
3608 }
3609
3610 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3611 {
3612         struct kvm_segment cs;
3613         unsigned int cs_rpl;
3614
3615         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3616         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3617
3618         if (cs.unusable)
3619                 return false;
3620         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3621                 return false;
3622         if (!cs.s)
3623                 return false;
3624         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3625                 if (cs.dpl > cs_rpl)
3626                         return false;
3627         } else {
3628                 if (cs.dpl != cs_rpl)
3629                         return false;
3630         }
3631         if (!cs.present)
3632                 return false;
3633
3634         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3635         return true;
3636 }
3637
3638 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3639 {
3640         struct kvm_segment ss;
3641         unsigned int ss_rpl;
3642
3643         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3644         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3645
3646         if (ss.unusable)
3647                 return true;
3648         if (ss.type != 3 && ss.type != 7)
3649                 return false;
3650         if (!ss.s)
3651                 return false;
3652         if (ss.dpl != ss_rpl) /* DPL != RPL */
3653                 return false;
3654         if (!ss.present)
3655                 return false;
3656
3657         return true;
3658 }
3659
3660 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3661 {
3662         struct kvm_segment var;
3663         unsigned int rpl;
3664
3665         vmx_get_segment(vcpu, &var, seg);
3666         rpl = var.selector & SELECTOR_RPL_MASK;
3667
3668         if (var.unusable)
3669                 return true;
3670         if (!var.s)
3671                 return false;
3672         if (!var.present)
3673                 return false;
3674         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3675                 if (var.dpl < rpl) /* DPL < RPL */
3676                         return false;
3677         }
3678
3679         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3680          * rights flags
3681          */
3682         return true;
3683 }
3684
3685 static bool tr_valid(struct kvm_vcpu *vcpu)
3686 {
3687         struct kvm_segment tr;
3688
3689         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3690
3691         if (tr.unusable)
3692                 return false;
3693         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3694                 return false;
3695         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3696                 return false;
3697         if (!tr.present)
3698                 return false;
3699
3700         return true;
3701 }
3702
3703 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3704 {
3705         struct kvm_segment ldtr;
3706
3707         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3708
3709         if (ldtr.unusable)
3710                 return true;
3711         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3712                 return false;
3713         if (ldtr.type != 2)
3714                 return false;
3715         if (!ldtr.present)
3716                 return false;
3717
3718         return true;
3719 }
3720
3721 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3722 {
3723         struct kvm_segment cs, ss;
3724
3725         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3726         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3727
3728         return ((cs.selector & SELECTOR_RPL_MASK) ==
3729                  (ss.selector & SELECTOR_RPL_MASK));
3730 }
3731
3732 /*
3733  * Check if guest state is valid. Returns true if valid, false if
3734  * not.
3735  * We assume that registers are always usable
3736  */
3737 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3738 {
3739         if (enable_unrestricted_guest)
3740                 return true;
3741
3742         /* real mode guest state checks */
3743         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3744                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3745                         return false;
3746                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3747                         return false;
3748                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3749                         return false;
3750                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3751                         return false;
3752                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3753                         return false;
3754                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3755                         return false;
3756         } else {
3757         /* protected mode guest state checks */
3758                 if (!cs_ss_rpl_check(vcpu))
3759                         return false;
3760                 if (!code_segment_valid(vcpu))
3761                         return false;
3762                 if (!stack_segment_valid(vcpu))
3763                         return false;
3764                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3765                         return false;
3766                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3767                         return false;
3768                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3769                         return false;
3770                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3771                         return false;
3772                 if (!tr_valid(vcpu))
3773                         return false;
3774                 if (!ldtr_valid(vcpu))
3775                         return false;
3776         }
3777         /* TODO:
3778          * - Add checks on RIP
3779          * - Add checks on RFLAGS
3780          */
3781
3782         return true;
3783 }
3784
3785 static int init_rmode_tss(struct kvm *kvm)
3786 {
3787         gfn_t fn;
3788         u16 data = 0;
3789         int r, idx, ret = 0;
3790
3791         idx = srcu_read_lock(&kvm->srcu);
3792         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3793         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3794         if (r < 0)
3795                 goto out;
3796         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3797         r = kvm_write_guest_page(kvm, fn++, &data,
3798                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3799         if (r < 0)
3800                 goto out;
3801         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3802         if (r < 0)
3803                 goto out;
3804         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3805         if (r < 0)
3806                 goto out;
3807         data = ~0;
3808         r = kvm_write_guest_page(kvm, fn, &data,
3809                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3810                                  sizeof(u8));
3811         if (r < 0)
3812                 goto out;
3813
3814         ret = 1;
3815 out:
3816         srcu_read_unlock(&kvm->srcu, idx);
3817         return ret;
3818 }
3819
3820 static int init_rmode_identity_map(struct kvm *kvm)
3821 {
3822         int i, idx, r, ret;
3823         pfn_t identity_map_pfn;
3824         u32 tmp;
3825
3826         if (!enable_ept)
3827                 return 1;
3828         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3829                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3830                         "haven't been allocated!\n");
3831                 return 0;
3832         }
3833         if (likely(kvm->arch.ept_identity_pagetable_done))
3834                 return 1;
3835         ret = 0;
3836         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3837         idx = srcu_read_lock(&kvm->srcu);
3838         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3839         if (r < 0)
3840                 goto out;
3841         /* Set up identity-mapping pagetable for EPT in real mode */
3842         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3843                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3844                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3845                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3846                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3847                 if (r < 0)
3848                         goto out;
3849         }
3850         kvm->arch.ept_identity_pagetable_done = true;
3851         ret = 1;
3852 out:
3853         srcu_read_unlock(&kvm->srcu, idx);
3854         return ret;
3855 }
3856
3857 static void seg_setup(int seg)
3858 {
3859         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3860         unsigned int ar;
3861
3862         vmcs_write16(sf->selector, 0);
3863         vmcs_writel(sf->base, 0);
3864         vmcs_write32(sf->limit, 0xffff);
3865         ar = 0x93;
3866         if (seg == VCPU_SREG_CS)
3867                 ar |= 0x08; /* code segment */
3868
3869         vmcs_write32(sf->ar_bytes, ar);
3870 }
3871
3872 static int alloc_apic_access_page(struct kvm *kvm)
3873 {
3874         struct page *page;
3875         struct kvm_userspace_memory_region kvm_userspace_mem;
3876         int r = 0;
3877
3878         mutex_lock(&kvm->slots_lock);
3879         if (kvm->arch.apic_access_page)
3880                 goto out;
3881         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3882         kvm_userspace_mem.flags = 0;
3883         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3884         kvm_userspace_mem.memory_size = PAGE_SIZE;
3885         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3886         if (r)
3887                 goto out;
3888
3889         page = gfn_to_page(kvm, 0xfee00);
3890         if (is_error_page(page)) {
3891                 r = -EFAULT;
3892                 goto out;
3893         }
3894
3895         kvm->arch.apic_access_page = page;
3896 out:
3897         mutex_unlock(&kvm->slots_lock);
3898         return r;
3899 }
3900
3901 static int alloc_identity_pagetable(struct kvm *kvm)
3902 {
3903         struct page *page;
3904         struct kvm_userspace_memory_region kvm_userspace_mem;
3905         int r = 0;
3906
3907         mutex_lock(&kvm->slots_lock);
3908         if (kvm->arch.ept_identity_pagetable)
3909                 goto out;
3910         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3911         kvm_userspace_mem.flags = 0;
3912         kvm_userspace_mem.guest_phys_addr =
3913                 kvm->arch.ept_identity_map_addr;
3914         kvm_userspace_mem.memory_size = PAGE_SIZE;
3915         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3916         if (r)
3917                 goto out;
3918
3919         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3920         if (is_error_page(page)) {
3921                 r = -EFAULT;
3922                 goto out;
3923         }
3924
3925         kvm->arch.ept_identity_pagetable = page;
3926 out:
3927         mutex_unlock(&kvm->slots_lock);
3928         return r;
3929 }
3930
3931 static void allocate_vpid(struct vcpu_vmx *vmx)
3932 {
3933         int vpid;
3934
3935         vmx->vpid = 0;
3936         if (!enable_vpid)
3937                 return;
3938         spin_lock(&vmx_vpid_lock);
3939         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3940         if (vpid < VMX_NR_VPIDS) {
3941                 vmx->vpid = vpid;
3942                 __set_bit(vpid, vmx_vpid_bitmap);
3943         }
3944         spin_unlock(&vmx_vpid_lock);
3945 }
3946
3947 static void free_vpid(struct vcpu_vmx *vmx)
3948 {
3949         if (!enable_vpid)
3950                 return;
3951         spin_lock(&vmx_vpid_lock);
3952         if (vmx->vpid != 0)
3953                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3954         spin_unlock(&vmx_vpid_lock);
3955 }
3956
3957 #define MSR_TYPE_R      1
3958 #define MSR_TYPE_W      2
3959 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3960                                                 u32 msr, int type)
3961 {
3962         int f = sizeof(unsigned long);
3963
3964         if (!cpu_has_vmx_msr_bitmap())
3965                 return;
3966
3967         /*
3968          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3969          * have the write-low and read-high bitmap offsets the wrong way round.
3970          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3971          */
3972         if (msr <= 0x1fff) {
3973                 if (type & MSR_TYPE_R)
3974                         /* read-low */
3975                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3976
3977                 if (type & MSR_TYPE_W)
3978                         /* write-low */
3979                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3980
3981         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3982                 msr &= 0x1fff;
3983                 if (type & MSR_TYPE_R)
3984                         /* read-high */
3985                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3986
3987                 if (type & MSR_TYPE_W)
3988                         /* write-high */
3989                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3990
3991         }
3992 }
3993
3994 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3995                                                 u32 msr, int type)
3996 {
3997         int f = sizeof(unsigned long);
3998
3999         if (!cpu_has_vmx_msr_bitmap())
4000                 return;
4001
4002         /*
4003          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4004          * have the write-low and read-high bitmap offsets the wrong way round.
4005          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4006          */
4007         if (msr <= 0x1fff) {
4008                 if (type & MSR_TYPE_R)
4009                         /* read-low */
4010                         __set_bit(msr, msr_bitmap + 0x000 / f);
4011
4012                 if (type & MSR_TYPE_W)
4013                         /* write-low */
4014                         __set_bit(msr, msr_bitmap + 0x800 / f);
4015
4016         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4017                 msr &= 0x1fff;
4018                 if (type & MSR_TYPE_R)
4019                         /* read-high */
4020                         __set_bit(msr, msr_bitmap + 0x400 / f);
4021
4022                 if (type & MSR_TYPE_W)
4023                         /* write-high */
4024                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4025
4026         }
4027 }
4028
4029 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4030 {
4031         if (!longmode_only)
4032                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4033                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4034         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4035                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4036 }
4037
4038 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4039 {
4040         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4041                         msr, MSR_TYPE_R);
4042         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4043                         msr, MSR_TYPE_R);
4044 }
4045
4046 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4047 {
4048         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4049                         msr, MSR_TYPE_R);
4050         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4051                         msr, MSR_TYPE_R);
4052 }
4053
4054 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4055 {
4056         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4057                         msr, MSR_TYPE_W);
4058         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4059                         msr, MSR_TYPE_W);
4060 }
4061
4062 static int vmx_vm_has_apicv(struct kvm *kvm)
4063 {
4064         return enable_apicv && irqchip_in_kernel(kvm);
4065 }
4066
4067 /*
4068  * Send interrupt to vcpu via posted interrupt way.
4069  * 1. If target vcpu is running(non-root mode), send posted interrupt
4070  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4071  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4072  * interrupt from PIR in next vmentry.
4073  */
4074 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4075 {
4076         struct vcpu_vmx *vmx = to_vmx(vcpu);
4077         int r;
4078
4079         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4080                 return;
4081
4082         r = pi_test_and_set_on(&vmx->pi_desc);
4083         kvm_make_request(KVM_REQ_EVENT, vcpu);
4084 #ifdef CONFIG_SMP
4085         if (!r && (vcpu->mode == IN_GUEST_MODE))
4086                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4087                                 POSTED_INTR_VECTOR);
4088         else
4089 #endif
4090                 kvm_vcpu_kick(vcpu);
4091 }
4092
4093 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4094 {
4095         struct vcpu_vmx *vmx = to_vmx(vcpu);
4096
4097         if (!pi_test_and_clear_on(&vmx->pi_desc))
4098                 return;
4099
4100         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4101 }
4102
4103 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4104 {
4105         return;
4106 }
4107
4108 /*
4109  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4110  * will not change in the lifetime of the guest.
4111  * Note that host-state that does change is set elsewhere. E.g., host-state
4112  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4113  */
4114 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4115 {
4116         u32 low32, high32;
4117         unsigned long tmpl;
4118         struct desc_ptr dt;
4119
4120         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4121         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4122         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4123
4124         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4125 #ifdef CONFIG_X86_64
4126         /*
4127          * Load null selectors, so we can avoid reloading them in
4128          * __vmx_load_host_state(), in case userspace uses the null selectors
4129          * too (the expected case).
4130          */
4131         vmcs_write16(HOST_DS_SELECTOR, 0);
4132         vmcs_write16(HOST_ES_SELECTOR, 0);
4133 #else
4134         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4135         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4136 #endif
4137         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4138         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4139
4140         native_store_idt(&dt);
4141         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4142         vmx->host_idt_base = dt.address;
4143
4144         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4145
4146         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4147         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4148         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4149         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4150
4151         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4152                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4153                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4154         }
4155 }
4156
4157 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4158 {
4159         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4160         if (enable_ept)
4161                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4162         if (is_guest_mode(&vmx->vcpu))
4163                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4164                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4165         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4166 }
4167
4168 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4169 {
4170         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4171
4172         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4173                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4174         return pin_based_exec_ctrl;
4175 }
4176
4177 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4178 {
4179         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4180         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4181                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4182 #ifdef CONFIG_X86_64
4183                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4184                                 CPU_BASED_CR8_LOAD_EXITING;
4185 #endif
4186         }
4187         if (!enable_ept)
4188                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4189                                 CPU_BASED_CR3_LOAD_EXITING  |
4190                                 CPU_BASED_INVLPG_EXITING;
4191         return exec_control;
4192 }
4193
4194 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4195 {
4196         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4197         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4198                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4199         if (vmx->vpid == 0)
4200                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4201         if (!enable_ept) {
4202                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4203                 enable_unrestricted_guest = 0;
4204                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4205                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4206         }
4207         if (!enable_unrestricted_guest)
4208                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4209         if (!ple_gap)
4210                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4211         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4212                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4213                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4214         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4215         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4216            (handle_vmptrld).
4217            We can NOT enable shadow_vmcs here because we don't have yet
4218            a current VMCS12
4219         */
4220         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4221         return exec_control;
4222 }
4223
4224 static void ept_set_mmio_spte_mask(void)
4225 {
4226         /*
4227          * EPT Misconfigurations can be generated if the value of bits 2:0
4228          * of an EPT paging-structure entry is 110b (write/execute).
4229          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4230          * spte.
4231          */
4232         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4233 }
4234
4235 /*
4236  * Sets up the vmcs for emulated real mode.
4237  */
4238 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4239 {
4240 #ifdef CONFIG_X86_64
4241         unsigned long a;
4242 #endif
4243         int i;
4244
4245         /* I/O */
4246         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4247         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4248
4249         if (enable_shadow_vmcs) {
4250                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4251                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4252         }
4253         if (cpu_has_vmx_msr_bitmap())
4254                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4255
4256         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4257
4258         /* Control */
4259         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4260
4261         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4262
4263         if (cpu_has_secondary_exec_ctrls()) {
4264                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4265                                 vmx_secondary_exec_control(vmx));
4266         }
4267
4268         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4269                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4270                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4271                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4272                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4273
4274                 vmcs_write16(GUEST_INTR_STATUS, 0);
4275
4276                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4277                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4278         }
4279
4280         if (ple_gap) {
4281                 vmcs_write32(PLE_GAP, ple_gap);
4282                 vmcs_write32(PLE_WINDOW, ple_window);
4283         }
4284
4285         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4286         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4287         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4288
4289         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4290         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4291         vmx_set_constant_host_state(vmx);
4292 #ifdef CONFIG_X86_64
4293         rdmsrl(MSR_FS_BASE, a);
4294         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4295         rdmsrl(MSR_GS_BASE, a);
4296         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4297 #else
4298         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4299         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4300 #endif
4301
4302         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4303         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4304         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4305         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4306         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4307
4308         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4309                 u32 msr_low, msr_high;
4310                 u64 host_pat;
4311                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4312                 host_pat = msr_low | ((u64) msr_high << 32);
4313                 /* Write the default value follow host pat */
4314                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4315                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4316                 vmx->vcpu.arch.pat = host_pat;
4317         }
4318
4319         for (i = 0; i < NR_VMX_MSR; ++i) {
4320                 u32 index = vmx_msr_index[i];
4321                 u32 data_low, data_high;
4322                 int j = vmx->nmsrs;
4323
4324                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4325                         continue;
4326                 if (wrmsr_safe(index, data_low, data_high) < 0)
4327                         continue;
4328                 vmx->guest_msrs[j].index = i;
4329                 vmx->guest_msrs[j].data = 0;
4330                 vmx->guest_msrs[j].mask = -1ull;
4331                 ++vmx->nmsrs;
4332         }
4333
4334         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4335
4336         /* 22.2.1, 20.8.1 */
4337         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4338
4339         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4340         set_cr4_guest_host_mask(vmx);
4341
4342         return 0;
4343 }
4344
4345 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4346 {
4347         struct vcpu_vmx *vmx = to_vmx(vcpu);
4348         u64 msr;
4349
4350         vmx->rmode.vm86_active = 0;
4351
4352         vmx->soft_vnmi_blocked = 0;
4353
4354         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4355         kvm_set_cr8(&vmx->vcpu, 0);
4356         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4357         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4358                 msr |= MSR_IA32_APICBASE_BSP;
4359         kvm_set_apic_base(&vmx->vcpu, msr);
4360
4361         vmx_segment_cache_clear(vmx);
4362
4363         seg_setup(VCPU_SREG_CS);
4364         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4365         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4366
4367         seg_setup(VCPU_SREG_DS);
4368         seg_setup(VCPU_SREG_ES);
4369         seg_setup(VCPU_SREG_FS);
4370         seg_setup(VCPU_SREG_GS);
4371         seg_setup(VCPU_SREG_SS);
4372
4373         vmcs_write16(GUEST_TR_SELECTOR, 0);
4374         vmcs_writel(GUEST_TR_BASE, 0);
4375         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4376         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4377
4378         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4379         vmcs_writel(GUEST_LDTR_BASE, 0);
4380         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4381         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4382
4383         vmcs_write32(GUEST_SYSENTER_CS, 0);
4384         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4385         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4386
4387         vmcs_writel(GUEST_RFLAGS, 0x02);
4388         kvm_rip_write(vcpu, 0xfff0);
4389
4390         vmcs_writel(GUEST_GDTR_BASE, 0);
4391         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4392
4393         vmcs_writel(GUEST_IDTR_BASE, 0);
4394         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4395
4396         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4397         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4398         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4399
4400         /* Special registers */
4401         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4402
4403         setup_msrs(vmx);
4404
4405         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4406
4407         if (cpu_has_vmx_tpr_shadow()) {
4408                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4409                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4410                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4411                                      __pa(vmx->vcpu.arch.apic->regs));
4412                 vmcs_write32(TPR_THRESHOLD, 0);
4413         }
4414
4415         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4416                 vmcs_write64(APIC_ACCESS_ADDR,
4417                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4418
4419         if (vmx_vm_has_apicv(vcpu->kvm))
4420                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4421
4422         if (vmx->vpid != 0)
4423                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4424
4425         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4426         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4427         vmx_set_cr4(&vmx->vcpu, 0);
4428         vmx_set_efer(&vmx->vcpu, 0);
4429         vmx_fpu_activate(&vmx->vcpu);
4430         update_exception_bitmap(&vmx->vcpu);
4431
4432         vpid_sync_context(vmx);
4433 }
4434
4435 /*
4436  * In nested virtualization, check if L1 asked to exit on external interrupts.
4437  * For most existing hypervisors, this will always return true.
4438  */
4439 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4440 {
4441         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4442                 PIN_BASED_EXT_INTR_MASK;
4443 }
4444
4445 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4446 {
4447         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4448                 PIN_BASED_NMI_EXITING;
4449 }
4450
4451 static int enable_irq_window(struct kvm_vcpu *vcpu)
4452 {
4453         u32 cpu_based_vm_exec_control;
4454
4455         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4456                 /*
4457                  * We get here if vmx_interrupt_allowed() said we can't
4458                  * inject to L1 now because L2 must run. The caller will have
4459                  * to make L2 exit right after entry, so we can inject to L1
4460                  * more promptly.
4461                  */
4462                 return -EBUSY;
4463
4464         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4465         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4466         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4467         return 0;
4468 }
4469
4470 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4471 {
4472         u32 cpu_based_vm_exec_control;
4473
4474         if (!cpu_has_virtual_nmis())
4475                 return enable_irq_window(vcpu);
4476
4477         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4478                 return enable_irq_window(vcpu);
4479
4480         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4481         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4482         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4483         return 0;
4484 }
4485
4486 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4487 {
4488         struct vcpu_vmx *vmx = to_vmx(vcpu);
4489         uint32_t intr;
4490         int irq = vcpu->arch.interrupt.nr;
4491
4492         trace_kvm_inj_virq(irq);
4493
4494         ++vcpu->stat.irq_injections;
4495         if (vmx->rmode.vm86_active) {
4496                 int inc_eip = 0;
4497                 if (vcpu->arch.interrupt.soft)
4498                         inc_eip = vcpu->arch.event_exit_inst_len;
4499                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4500                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4501                 return;
4502         }
4503         intr = irq | INTR_INFO_VALID_MASK;
4504         if (vcpu->arch.interrupt.soft) {
4505                 intr |= INTR_TYPE_SOFT_INTR;
4506                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4507                              vmx->vcpu.arch.event_exit_inst_len);
4508         } else
4509                 intr |= INTR_TYPE_EXT_INTR;
4510         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4511 }
4512
4513 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4514 {
4515         struct vcpu_vmx *vmx = to_vmx(vcpu);
4516
4517         if (is_guest_mode(vcpu))
4518                 return;
4519
4520         if (!cpu_has_virtual_nmis()) {
4521                 /*
4522                  * Tracking the NMI-blocked state in software is built upon
4523                  * finding the next open IRQ window. This, in turn, depends on
4524                  * well-behaving guests: They have to keep IRQs disabled at
4525                  * least as long as the NMI handler runs. Otherwise we may
4526                  * cause NMI nesting, maybe breaking the guest. But as this is
4527                  * highly unlikely, we can live with the residual risk.
4528                  */
4529                 vmx->soft_vnmi_blocked = 1;
4530                 vmx->vnmi_blocked_time = 0;
4531         }
4532
4533         ++vcpu->stat.nmi_injections;
4534         vmx->nmi_known_unmasked = false;
4535         if (vmx->rmode.vm86_active) {
4536                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4537                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4538                 return;
4539         }
4540         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4541                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4542 }
4543
4544 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4545 {
4546         if (!cpu_has_virtual_nmis())
4547                 return to_vmx(vcpu)->soft_vnmi_blocked;
4548         if (to_vmx(vcpu)->nmi_known_unmasked)
4549                 return false;
4550         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4551 }
4552
4553 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4554 {
4555         struct vcpu_vmx *vmx = to_vmx(vcpu);
4556
4557         if (!cpu_has_virtual_nmis()) {
4558                 if (vmx->soft_vnmi_blocked != masked) {
4559                         vmx->soft_vnmi_blocked = masked;
4560                         vmx->vnmi_blocked_time = 0;
4561                 }
4562         } else {
4563                 vmx->nmi_known_unmasked = !masked;
4564                 if (masked)
4565                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4566                                       GUEST_INTR_STATE_NMI);
4567                 else
4568                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4569                                         GUEST_INTR_STATE_NMI);
4570         }
4571 }
4572
4573 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4574 {
4575         if (is_guest_mode(vcpu)) {
4576                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4577
4578                 if (to_vmx(vcpu)->nested.nested_run_pending)
4579                         return 0;
4580                 if (nested_exit_on_nmi(vcpu)) {
4581                         nested_vmx_vmexit(vcpu);
4582                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4583                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4584                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4585                         /*
4586                          * The NMI-triggered VM exit counts as injection:
4587                          * clear this one and block further NMIs.
4588                          */
4589                         vcpu->arch.nmi_pending = 0;
4590                         vmx_set_nmi_mask(vcpu, true);
4591                         return 0;
4592                 }
4593         }
4594
4595         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4596                 return 0;
4597
4598         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4599                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4600                    | GUEST_INTR_STATE_NMI));
4601 }
4602
4603 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4604 {
4605         if (is_guest_mode(vcpu)) {
4606                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4607
4608                 if (to_vmx(vcpu)->nested.nested_run_pending)
4609                         return 0;
4610                 if (nested_exit_on_intr(vcpu)) {
4611                         nested_vmx_vmexit(vcpu);
4612                         vmcs12->vm_exit_reason =
4613                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4614                         vmcs12->vm_exit_intr_info = 0;
4615                         /*
4616                          * fall through to normal code, but now in L1, not L2
4617                          */
4618                 }
4619         }
4620
4621         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4622                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4623                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4624 }
4625
4626 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4627 {
4628         int ret;
4629         struct kvm_userspace_memory_region tss_mem = {
4630                 .slot = TSS_PRIVATE_MEMSLOT,
4631                 .guest_phys_addr = addr,
4632                 .memory_size = PAGE_SIZE * 3,
4633                 .flags = 0,
4634         };
4635
4636         ret = kvm_set_memory_region(kvm, &tss_mem);
4637         if (ret)
4638                 return ret;
4639         kvm->arch.tss_addr = addr;
4640         if (!init_rmode_tss(kvm))
4641                 return  -ENOMEM;
4642
4643         return 0;
4644 }
4645
4646 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4647 {
4648         switch (vec) {
4649         case BP_VECTOR:
4650                 /*
4651                  * Update instruction length as we may reinject the exception
4652                  * from user space while in guest debugging mode.
4653                  */
4654                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4655                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4656                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4657                         return false;
4658                 /* fall through */
4659         case DB_VECTOR:
4660                 if (vcpu->guest_debug &
4661                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4662                         return false;
4663                 /* fall through */
4664         case DE_VECTOR:
4665         case OF_VECTOR:
4666         case BR_VECTOR:
4667         case UD_VECTOR:
4668         case DF_VECTOR:
4669         case SS_VECTOR:
4670         case GP_VECTOR:
4671         case MF_VECTOR:
4672                 return true;
4673         break;
4674         }
4675         return false;
4676 }
4677
4678 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4679                                   int vec, u32 err_code)
4680 {
4681         /*
4682          * Instruction with address size override prefix opcode 0x67
4683          * Cause the #SS fault with 0 error code in VM86 mode.
4684          */
4685         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4686                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4687                         if (vcpu->arch.halt_request) {
4688                                 vcpu->arch.halt_request = 0;
4689                                 return kvm_emulate_halt(vcpu);
4690                         }
4691                         return 1;
4692                 }
4693                 return 0;
4694         }
4695
4696         /*
4697          * Forward all other exceptions that are valid in real mode.
4698          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4699          *        the required debugging infrastructure rework.
4700          */
4701         kvm_queue_exception(vcpu, vec);
4702         return 1;
4703 }
4704
4705 /*
4706  * Trigger machine check on the host. We assume all the MSRs are already set up
4707  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4708  * We pass a fake environment to the machine check handler because we want
4709  * the guest to be always treated like user space, no matter what context
4710  * it used internally.
4711  */
4712 static void kvm_machine_check(void)
4713 {
4714 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4715         struct pt_regs regs = {
4716                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4717                 .flags = X86_EFLAGS_IF,
4718         };
4719
4720         do_machine_check(&regs, 0);
4721 #endif
4722 }
4723
4724 static int handle_machine_check(struct kvm_vcpu *vcpu)
4725 {
4726         /* already handled by vcpu_run */
4727         return 1;
4728 }
4729
4730 static int handle_exception(struct kvm_vcpu *vcpu)
4731 {
4732         struct vcpu_vmx *vmx = to_vmx(vcpu);
4733         struct kvm_run *kvm_run = vcpu->run;
4734         u32 intr_info, ex_no, error_code;
4735         unsigned long cr2, rip, dr6;
4736         u32 vect_info;
4737         enum emulation_result er;
4738
4739         vect_info = vmx->idt_vectoring_info;
4740         intr_info = vmx->exit_intr_info;
4741
4742         if (is_machine_check(intr_info))
4743                 return handle_machine_check(vcpu);
4744
4745         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4746                 return 1;  /* already handled by vmx_vcpu_run() */
4747
4748         if (is_no_device(intr_info)) {
4749                 vmx_fpu_activate(vcpu);
4750                 return 1;
4751         }
4752
4753         if (is_invalid_opcode(intr_info)) {
4754                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4755                 if (er != EMULATE_DONE)
4756                         kvm_queue_exception(vcpu, UD_VECTOR);
4757                 return 1;
4758         }
4759
4760         error_code = 0;
4761         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4762                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4763
4764         /*
4765          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4766          * MMIO, it is better to report an internal error.
4767          * See the comments in vmx_handle_exit.
4768          */
4769         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4770             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4771                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4772                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4773                 vcpu->run->internal.ndata = 2;
4774                 vcpu->run->internal.data[0] = vect_info;
4775                 vcpu->run->internal.data[1] = intr_info;
4776                 return 0;
4777         }
4778
4779         if (is_page_fault(intr_info)) {
4780                 /* EPT won't cause page fault directly */
4781                 BUG_ON(enable_ept);
4782                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4783                 trace_kvm_page_fault(cr2, error_code);
4784
4785                 if (kvm_event_needs_reinjection(vcpu))
4786                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4787                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4788         }
4789
4790         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4791
4792         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4793                 return handle_rmode_exception(vcpu, ex_no, error_code);
4794
4795         switch (ex_no) {
4796         case DB_VECTOR:
4797                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4798                 if (!(vcpu->guest_debug &
4799                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4800                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4801                         kvm_queue_exception(vcpu, DB_VECTOR);
4802                         return 1;
4803                 }
4804                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4805                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4806                 /* fall through */
4807         case BP_VECTOR:
4808                 /*
4809                  * Update instruction length as we may reinject #BP from
4810                  * user space while in guest debugging mode. Reading it for
4811                  * #DB as well causes no harm, it is not used in that case.
4812                  */
4813                 vmx->vcpu.arch.event_exit_inst_len =
4814                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4815                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4816                 rip = kvm_rip_read(vcpu);
4817                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4818                 kvm_run->debug.arch.exception = ex_no;
4819                 break;
4820         default:
4821                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4822                 kvm_run->ex.exception = ex_no;
4823                 kvm_run->ex.error_code = error_code;
4824                 break;
4825         }
4826         return 0;
4827 }
4828
4829 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4830 {
4831         ++vcpu->stat.irq_exits;
4832         return 1;
4833 }
4834
4835 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4836 {
4837         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4838         return 0;
4839 }
4840
4841 static int handle_io(struct kvm_vcpu *vcpu)
4842 {
4843         unsigned long exit_qualification;
4844         int size, in, string;
4845         unsigned port;
4846
4847         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4848         string = (exit_qualification & 16) != 0;
4849         in = (exit_qualification & 8) != 0;
4850
4851         ++vcpu->stat.io_exits;
4852
4853         if (string || in)
4854                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4855
4856         port = exit_qualification >> 16;
4857         size = (exit_qualification & 7) + 1;
4858         skip_emulated_instruction(vcpu);
4859
4860         return kvm_fast_pio_out(vcpu, size, port);
4861 }
4862
4863 static void
4864 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4865 {
4866         /*
4867          * Patch in the VMCALL instruction:
4868          */
4869         hypercall[0] = 0x0f;
4870         hypercall[1] = 0x01;
4871         hypercall[2] = 0xc1;
4872 }
4873
4874 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4875 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4876 {
4877         if (is_guest_mode(vcpu)) {
4878                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4879                 unsigned long orig_val = val;
4880
4881                 /*
4882                  * We get here when L2 changed cr0 in a way that did not change
4883                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4884                  * but did change L0 shadowed bits. So we first calculate the
4885                  * effective cr0 value that L1 would like to write into the
4886                  * hardware. It consists of the L2-owned bits from the new
4887                  * value combined with the L1-owned bits from L1's guest_cr0.
4888                  */
4889                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4890                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4891
4892                 /* TODO: will have to take unrestricted guest mode into
4893                  * account */
4894                 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4895                         return 1;
4896
4897                 if (kvm_set_cr0(vcpu, val))
4898                         return 1;
4899                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4900                 return 0;
4901         } else {
4902                 if (to_vmx(vcpu)->nested.vmxon &&
4903                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4904                         return 1;
4905                 return kvm_set_cr0(vcpu, val);
4906         }
4907 }
4908
4909 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4910 {
4911         if (is_guest_mode(vcpu)) {
4912                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4913                 unsigned long orig_val = val;
4914
4915                 /* analogously to handle_set_cr0 */
4916                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4917                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4918                 if (kvm_set_cr4(vcpu, val))
4919                         return 1;
4920                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4921                 return 0;
4922         } else
4923                 return kvm_set_cr4(vcpu, val);
4924 }
4925
4926 /* called to set cr0 as approriate for clts instruction exit. */
4927 static void handle_clts(struct kvm_vcpu *vcpu)
4928 {
4929         if (is_guest_mode(vcpu)) {
4930                 /*
4931                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4932                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4933                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4934                  */
4935                 vmcs_writel(CR0_READ_SHADOW,
4936                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4937                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4938         } else
4939                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4940 }
4941
4942 static int handle_cr(struct kvm_vcpu *vcpu)
4943 {
4944         unsigned long exit_qualification, val;
4945         int cr;
4946         int reg;
4947         int err;
4948
4949         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4950         cr = exit_qualification & 15;
4951         reg = (exit_qualification >> 8) & 15;
4952         switch ((exit_qualification >> 4) & 3) {
4953         case 0: /* mov to cr */
4954                 val = kvm_register_read(vcpu, reg);
4955                 trace_kvm_cr_write(cr, val);
4956                 switch (cr) {
4957                 case 0:
4958                         err = handle_set_cr0(vcpu, val);
4959                         kvm_complete_insn_gp(vcpu, err);
4960                         return 1;
4961                 case 3:
4962                         err = kvm_set_cr3(vcpu, val);
4963                         kvm_complete_insn_gp(vcpu, err);
4964                         return 1;
4965                 case 4:
4966                         err = handle_set_cr4(vcpu, val);
4967                         kvm_complete_insn_gp(vcpu, err);
4968                         return 1;
4969                 case 8: {
4970                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4971                                 u8 cr8 = kvm_register_read(vcpu, reg);
4972                                 err = kvm_set_cr8(vcpu, cr8);
4973                                 kvm_complete_insn_gp(vcpu, err);
4974                                 if (irqchip_in_kernel(vcpu->kvm))
4975                                         return 1;
4976                                 if (cr8_prev <= cr8)
4977                                         return 1;
4978                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4979                                 return 0;
4980                         }
4981                 }
4982                 break;
4983         case 2: /* clts */
4984                 handle_clts(vcpu);
4985                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4986                 skip_emulated_instruction(vcpu);
4987                 vmx_fpu_activate(vcpu);
4988                 return 1;
4989         case 1: /*mov from cr*/
4990                 switch (cr) {
4991                 case 3:
4992                         val = kvm_read_cr3(vcpu);
4993                         kvm_register_write(vcpu, reg, val);
4994                         trace_kvm_cr_read(cr, val);
4995                         skip_emulated_instruction(vcpu);
4996                         return 1;
4997                 case 8:
4998                         val = kvm_get_cr8(vcpu);
4999                         kvm_register_write(vcpu, reg, val);
5000                         trace_kvm_cr_read(cr, val);
5001                         skip_emulated_instruction(vcpu);
5002                         return 1;
5003                 }
5004                 break;
5005         case 3: /* lmsw */
5006                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5007                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5008                 kvm_lmsw(vcpu, val);
5009
5010                 skip_emulated_instruction(vcpu);
5011                 return 1;
5012         default:
5013                 break;
5014         }
5015         vcpu->run->exit_reason = 0;
5016         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5017                (int)(exit_qualification >> 4) & 3, cr);
5018         return 0;
5019 }
5020
5021 static int handle_dr(struct kvm_vcpu *vcpu)
5022 {
5023         unsigned long exit_qualification;
5024         int dr, reg;
5025
5026         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5027         if (!kvm_require_cpl(vcpu, 0))
5028                 return 1;
5029         dr = vmcs_readl(GUEST_DR7);
5030         if (dr & DR7_GD) {
5031                 /*
5032                  * As the vm-exit takes precedence over the debug trap, we
5033                  * need to emulate the latter, either for the host or the
5034                  * guest debugging itself.
5035                  */
5036                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5037                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5038                         vcpu->run->debug.arch.dr7 = dr;
5039                         vcpu->run->debug.arch.pc =
5040                                 vmcs_readl(GUEST_CS_BASE) +
5041                                 vmcs_readl(GUEST_RIP);
5042                         vcpu->run->debug.arch.exception = DB_VECTOR;
5043                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5044                         return 0;
5045                 } else {
5046                         vcpu->arch.dr7 &= ~DR7_GD;
5047                         vcpu->arch.dr6 |= DR6_BD;
5048                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5049                         kvm_queue_exception(vcpu, DB_VECTOR);
5050                         return 1;
5051                 }
5052         }
5053
5054         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5055         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5056         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5057         if (exit_qualification & TYPE_MOV_FROM_DR) {
5058                 unsigned long val;
5059                 if (!kvm_get_dr(vcpu, dr, &val))
5060                         kvm_register_write(vcpu, reg, val);
5061         } else
5062                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5063         skip_emulated_instruction(vcpu);
5064         return 1;
5065 }
5066
5067 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5068 {
5069         vmcs_writel(GUEST_DR7, val);
5070 }
5071
5072 static int handle_cpuid(struct kvm_vcpu *vcpu)
5073 {
5074         kvm_emulate_cpuid(vcpu);
5075         return 1;
5076 }
5077
5078 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5079 {
5080         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5081         u64 data;
5082
5083         if (vmx_get_msr(vcpu, ecx, &data)) {
5084                 trace_kvm_msr_read_ex(ecx);
5085                 kvm_inject_gp(vcpu, 0);
5086                 return 1;
5087         }
5088
5089         trace_kvm_msr_read(ecx, data);
5090
5091         /* FIXME: handling of bits 32:63 of rax, rdx */
5092         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5093         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5094         skip_emulated_instruction(vcpu);
5095         return 1;
5096 }
5097
5098 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5099 {
5100         struct msr_data msr;
5101         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5102         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5103                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5104
5105         msr.data = data;
5106         msr.index = ecx;
5107         msr.host_initiated = false;
5108         if (vmx_set_msr(vcpu, &msr) != 0) {
5109                 trace_kvm_msr_write_ex(ecx, data);
5110                 kvm_inject_gp(vcpu, 0);
5111                 return 1;
5112         }
5113
5114         trace_kvm_msr_write(ecx, data);
5115         skip_emulated_instruction(vcpu);
5116         return 1;
5117 }
5118
5119 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5120 {
5121         kvm_make_request(KVM_REQ_EVENT, vcpu);
5122         return 1;
5123 }
5124
5125 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5126 {
5127         u32 cpu_based_vm_exec_control;
5128
5129         /* clear pending irq */
5130         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5131         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5132         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5133
5134         kvm_make_request(KVM_REQ_EVENT, vcpu);
5135
5136         ++vcpu->stat.irq_window_exits;
5137
5138         /*
5139          * If the user space waits to inject interrupts, exit as soon as
5140          * possible
5141          */
5142         if (!irqchip_in_kernel(vcpu->kvm) &&
5143             vcpu->run->request_interrupt_window &&
5144             !kvm_cpu_has_interrupt(vcpu)) {
5145                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5146                 return 0;
5147         }
5148         return 1;
5149 }
5150
5151 static int handle_halt(struct kvm_vcpu *vcpu)
5152 {
5153         skip_emulated_instruction(vcpu);
5154         return kvm_emulate_halt(vcpu);
5155 }
5156
5157 static int handle_vmcall(struct kvm_vcpu *vcpu)
5158 {
5159         skip_emulated_instruction(vcpu);
5160         kvm_emulate_hypercall(vcpu);
5161         return 1;
5162 }
5163
5164 static int handle_invd(struct kvm_vcpu *vcpu)
5165 {
5166         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5167 }
5168
5169 static int handle_invlpg(struct kvm_vcpu *vcpu)
5170 {
5171         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5172
5173         kvm_mmu_invlpg(vcpu, exit_qualification);
5174         skip_emulated_instruction(vcpu);
5175         return 1;
5176 }
5177
5178 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5179 {
5180         int err;
5181
5182         err = kvm_rdpmc(vcpu);
5183         kvm_complete_insn_gp(vcpu, err);
5184
5185         return 1;
5186 }
5187
5188 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5189 {
5190         skip_emulated_instruction(vcpu);
5191         kvm_emulate_wbinvd(vcpu);
5192         return 1;
5193 }
5194
5195 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5196 {
5197         u64 new_bv = kvm_read_edx_eax(vcpu);
5198         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5199
5200         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5201                 skip_emulated_instruction(vcpu);
5202         return 1;
5203 }
5204
5205 static int handle_apic_access(struct kvm_vcpu *vcpu)
5206 {
5207         if (likely(fasteoi)) {
5208                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5209                 int access_type, offset;
5210
5211                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5212                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5213                 /*
5214                  * Sane guest uses MOV to write EOI, with written value
5215                  * not cared. So make a short-circuit here by avoiding
5216                  * heavy instruction emulation.
5217                  */
5218                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5219                     (offset == APIC_EOI)) {
5220                         kvm_lapic_set_eoi(vcpu);
5221                         skip_emulated_instruction(vcpu);
5222                         return 1;
5223                 }
5224         }
5225         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5226 }
5227
5228 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5229 {
5230         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5231         int vector = exit_qualification & 0xff;
5232
5233         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5234         kvm_apic_set_eoi_accelerated(vcpu, vector);
5235         return 1;
5236 }
5237
5238 static int handle_apic_write(struct kvm_vcpu *vcpu)
5239 {
5240         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5241         u32 offset = exit_qualification & 0xfff;
5242
5243         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5244         kvm_apic_write_nodecode(vcpu, offset);
5245         return 1;
5246 }
5247
5248 static int handle_task_switch(struct kvm_vcpu *vcpu)
5249 {
5250         struct vcpu_vmx *vmx = to_vmx(vcpu);
5251         unsigned long exit_qualification;
5252         bool has_error_code = false;
5253         u32 error_code = 0;
5254         u16 tss_selector;
5255         int reason, type, idt_v, idt_index;
5256
5257         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5258         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5259         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5260
5261         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5262
5263         reason = (u32)exit_qualification >> 30;
5264         if (reason == TASK_SWITCH_GATE && idt_v) {
5265                 switch (type) {
5266                 case INTR_TYPE_NMI_INTR:
5267                         vcpu->arch.nmi_injected = false;
5268                         vmx_set_nmi_mask(vcpu, true);
5269                         break;
5270                 case INTR_TYPE_EXT_INTR:
5271                 case INTR_TYPE_SOFT_INTR:
5272                         kvm_clear_interrupt_queue(vcpu);
5273                         break;
5274                 case INTR_TYPE_HARD_EXCEPTION:
5275                         if (vmx->idt_vectoring_info &
5276                             VECTORING_INFO_DELIVER_CODE_MASK) {
5277                                 has_error_code = true;
5278                                 error_code =
5279                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5280                         }
5281                         /* fall through */
5282                 case INTR_TYPE_SOFT_EXCEPTION:
5283                         kvm_clear_exception_queue(vcpu);
5284                         break;
5285                 default:
5286                         break;
5287                 }
5288         }
5289         tss_selector = exit_qualification;
5290
5291         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5292                        type != INTR_TYPE_EXT_INTR &&
5293                        type != INTR_TYPE_NMI_INTR))
5294                 skip_emulated_instruction(vcpu);
5295
5296         if (kvm_task_switch(vcpu, tss_selector,
5297                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5298                             has_error_code, error_code) == EMULATE_FAIL) {
5299                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5300                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5301                 vcpu->run->internal.ndata = 0;
5302                 return 0;
5303         }
5304
5305         /* clear all local breakpoint enable flags */
5306         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5307
5308         /*
5309          * TODO: What about debug traps on tss switch?
5310          *       Are we supposed to inject them and update dr6?
5311          */
5312
5313         return 1;
5314 }
5315
5316 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5317 {
5318         unsigned long exit_qualification;
5319         gpa_t gpa;
5320         u32 error_code;
5321         int gla_validity;
5322
5323         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5324
5325         gla_validity = (exit_qualification >> 7) & 0x3;
5326         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5327                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5328                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5329                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5330                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5331                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5332                         (long unsigned int)exit_qualification);
5333                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5334                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5335                 return 0;
5336         }
5337
5338         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5339         trace_kvm_page_fault(gpa, exit_qualification);
5340
5341         /* It is a write fault? */
5342         error_code = exit_qualification & (1U << 1);
5343         /* It is a fetch fault? */
5344         error_code |= (exit_qualification & (1U << 2)) << 2;
5345         /* ept page table is present? */
5346         error_code |= (exit_qualification >> 3) & 0x1;
5347
5348         vcpu->arch.exit_qualification = exit_qualification;
5349
5350         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5351 }
5352
5353 static u64 ept_rsvd_mask(u64 spte, int level)
5354 {
5355         int i;
5356         u64 mask = 0;
5357
5358         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5359                 mask |= (1ULL << i);
5360
5361         if (level > 2)
5362                 /* bits 7:3 reserved */
5363                 mask |= 0xf8;
5364         else if (level == 2) {
5365                 if (spte & (1ULL << 7))
5366                         /* 2MB ref, bits 20:12 reserved */
5367                         mask |= 0x1ff000;
5368                 else
5369                         /* bits 6:3 reserved */
5370                         mask |= 0x78;
5371         }
5372
5373         return mask;
5374 }
5375
5376 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5377                                        int level)
5378 {
5379         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5380
5381         /* 010b (write-only) */
5382         WARN_ON((spte & 0x7) == 0x2);
5383
5384         /* 110b (write/execute) */
5385         WARN_ON((spte & 0x7) == 0x6);
5386
5387         /* 100b (execute-only) and value not supported by logical processor */
5388         if (!cpu_has_vmx_ept_execute_only())
5389                 WARN_ON((spte & 0x7) == 0x4);
5390
5391         /* not 000b */
5392         if ((spte & 0x7)) {
5393                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5394
5395                 if (rsvd_bits != 0) {
5396                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5397                                          __func__, rsvd_bits);
5398                         WARN_ON(1);
5399                 }
5400
5401                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5402                         u64 ept_mem_type = (spte & 0x38) >> 3;
5403
5404                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5405                             ept_mem_type == 7) {
5406                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5407                                                 __func__, ept_mem_type);
5408                                 WARN_ON(1);
5409                         }
5410                 }
5411         }
5412 }
5413
5414 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5415 {
5416         u64 sptes[4];
5417         int nr_sptes, i, ret;
5418         gpa_t gpa;
5419
5420         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5421
5422         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5423         if (likely(ret == RET_MMIO_PF_EMULATE))
5424                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5425                                               EMULATE_DONE;
5426
5427         if (unlikely(ret == RET_MMIO_PF_INVALID))
5428                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5429
5430         if (unlikely(ret == RET_MMIO_PF_RETRY))
5431                 return 1;
5432
5433         /* It is the real ept misconfig */
5434         printk(KERN_ERR "EPT: Misconfiguration.\n");
5435         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5436
5437         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5438
5439         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5440                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5441
5442         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5443         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5444
5445         return 0;
5446 }
5447
5448 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5449 {
5450         u32 cpu_based_vm_exec_control;
5451
5452         /* clear pending NMI */
5453         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5454         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5455         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5456         ++vcpu->stat.nmi_window_exits;
5457         kvm_make_request(KVM_REQ_EVENT, vcpu);
5458
5459         return 1;
5460 }
5461
5462 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5463 {
5464         struct vcpu_vmx *vmx = to_vmx(vcpu);
5465         enum emulation_result err = EMULATE_DONE;
5466         int ret = 1;
5467         u32 cpu_exec_ctrl;
5468         bool intr_window_requested;
5469         unsigned count = 130;
5470
5471         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5472         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5473
5474         while (!guest_state_valid(vcpu) && count-- != 0) {
5475                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5476                         return handle_interrupt_window(&vmx->vcpu);
5477
5478                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5479                         return 1;
5480
5481                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5482
5483                 if (err == EMULATE_USER_EXIT) {
5484                         ret = 0;
5485                         goto out;
5486                 }
5487
5488                 if (err != EMULATE_DONE) {
5489                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5490                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5491                         vcpu->run->internal.ndata = 0;
5492                         return 0;
5493                 }
5494
5495                 if (vcpu->arch.halt_request) {
5496                         vcpu->arch.halt_request = 0;
5497                         ret = kvm_emulate_halt(vcpu);
5498                         goto out;
5499                 }
5500
5501                 if (signal_pending(current))
5502                         goto out;
5503                 if (need_resched())
5504                         schedule();
5505         }
5506
5507         vmx->emulation_required = emulation_required(vcpu);
5508 out:
5509         return ret;
5510 }
5511
5512 /*
5513  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5514  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5515  */
5516 static int handle_pause(struct kvm_vcpu *vcpu)
5517 {
5518         skip_emulated_instruction(vcpu);
5519         kvm_vcpu_on_spin(vcpu);
5520
5521         return 1;
5522 }
5523
5524 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5525 {
5526         kvm_queue_exception(vcpu, UD_VECTOR);
5527         return 1;
5528 }
5529
5530 /*
5531  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5532  * We could reuse a single VMCS for all the L2 guests, but we also want the
5533  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5534  * allows keeping them loaded on the processor, and in the future will allow
5535  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5536  * every entry if they never change.
5537  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5538  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5539  *
5540  * The following functions allocate and free a vmcs02 in this pool.
5541  */
5542
5543 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5544 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5545 {
5546         struct vmcs02_list *item;
5547         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5548                 if (item->vmptr == vmx->nested.current_vmptr) {
5549                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5550                         return &item->vmcs02;
5551                 }
5552
5553         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5554                 /* Recycle the least recently used VMCS. */
5555                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5556                         struct vmcs02_list, list);
5557                 item->vmptr = vmx->nested.current_vmptr;
5558                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5559                 return &item->vmcs02;
5560         }
5561
5562         /* Create a new VMCS */
5563         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5564         if (!item)
5565                 return NULL;
5566         item->vmcs02.vmcs = alloc_vmcs();
5567         if (!item->vmcs02.vmcs) {
5568                 kfree(item);
5569                 return NULL;
5570         }
5571         loaded_vmcs_init(&item->vmcs02);
5572         item->vmptr = vmx->nested.current_vmptr;
5573         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5574         vmx->nested.vmcs02_num++;
5575         return &item->vmcs02;
5576 }
5577
5578 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5579 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5580 {
5581         struct vmcs02_list *item;
5582         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5583                 if (item->vmptr == vmptr) {
5584                         free_loaded_vmcs(&item->vmcs02);
5585                         list_del(&item->list);
5586                         kfree(item);
5587                         vmx->nested.vmcs02_num--;
5588                         return;
5589                 }
5590 }
5591
5592 /*
5593  * Free all VMCSs saved for this vcpu, except the one pointed by
5594  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5595  * currently used, if running L2), and vmcs01 when running L2.
5596  */
5597 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5598 {
5599         struct vmcs02_list *item, *n;
5600         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5601                 if (vmx->loaded_vmcs != &item->vmcs02)
5602                         free_loaded_vmcs(&item->vmcs02);
5603                 list_del(&item->list);
5604                 kfree(item);
5605         }
5606         vmx->nested.vmcs02_num = 0;
5607
5608         if (vmx->loaded_vmcs != &vmx->vmcs01)
5609                 free_loaded_vmcs(&vmx->vmcs01);
5610 }
5611
5612 /*
5613  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5614  * set the success or error code of an emulated VMX instruction, as specified
5615  * by Vol 2B, VMX Instruction Reference, "Conventions".
5616  */
5617 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5618 {
5619         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5620                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5621                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5622 }
5623
5624 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5625 {
5626         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5627                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5628                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5629                         | X86_EFLAGS_CF);
5630 }
5631
5632 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5633                                         u32 vm_instruction_error)
5634 {
5635         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5636                 /*
5637                  * failValid writes the error number to the current VMCS, which
5638                  * can't be done there isn't a current VMCS.
5639                  */
5640                 nested_vmx_failInvalid(vcpu);
5641                 return;
5642         }
5643         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5644                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5645                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5646                         | X86_EFLAGS_ZF);
5647         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5648         /*
5649          * We don't need to force a shadow sync because
5650          * VM_INSTRUCTION_ERROR is not shadowed
5651          */
5652 }
5653
5654 /*
5655  * Emulate the VMXON instruction.
5656  * Currently, we just remember that VMX is active, and do not save or even
5657  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5658  * do not currently need to store anything in that guest-allocated memory
5659  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5660  * argument is different from the VMXON pointer (which the spec says they do).
5661  */
5662 static int handle_vmon(struct kvm_vcpu *vcpu)
5663 {
5664         struct kvm_segment cs;
5665         struct vcpu_vmx *vmx = to_vmx(vcpu);
5666         struct vmcs *shadow_vmcs;
5667         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5668                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5669
5670         /* The Intel VMX Instruction Reference lists a bunch of bits that
5671          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5672          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5673          * Otherwise, we should fail with #UD. We test these now:
5674          */
5675         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5676             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5677             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5678                 kvm_queue_exception(vcpu, UD_VECTOR);
5679                 return 1;
5680         }
5681
5682         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5683         if (is_long_mode(vcpu) && !cs.l) {
5684                 kvm_queue_exception(vcpu, UD_VECTOR);
5685                 return 1;
5686         }
5687
5688         if (vmx_get_cpl(vcpu)) {
5689                 kvm_inject_gp(vcpu, 0);
5690                 return 1;
5691         }
5692         if (vmx->nested.vmxon) {
5693                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5694                 skip_emulated_instruction(vcpu);
5695                 return 1;
5696         }
5697
5698         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5699                         != VMXON_NEEDED_FEATURES) {
5700                 kvm_inject_gp(vcpu, 0);
5701                 return 1;
5702         }
5703
5704         if (enable_shadow_vmcs) {
5705                 shadow_vmcs = alloc_vmcs();
5706                 if (!shadow_vmcs)
5707                         return -ENOMEM;
5708                 /* mark vmcs as shadow */
5709                 shadow_vmcs->revision_id |= (1u << 31);
5710                 /* init shadow vmcs */
5711                 vmcs_clear(shadow_vmcs);
5712                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5713         }
5714
5715         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5716         vmx->nested.vmcs02_num = 0;
5717
5718         vmx->nested.vmxon = true;
5719
5720         skip_emulated_instruction(vcpu);
5721         nested_vmx_succeed(vcpu);
5722         return 1;
5723 }
5724
5725 /*
5726  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5727  * for running VMX instructions (except VMXON, whose prerequisites are
5728  * slightly different). It also specifies what exception to inject otherwise.
5729  */
5730 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5731 {
5732         struct kvm_segment cs;
5733         struct vcpu_vmx *vmx = to_vmx(vcpu);
5734
5735         if (!vmx->nested.vmxon) {
5736                 kvm_queue_exception(vcpu, UD_VECTOR);
5737                 return 0;
5738         }
5739
5740         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5741         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5742             (is_long_mode(vcpu) && !cs.l)) {
5743                 kvm_queue_exception(vcpu, UD_VECTOR);
5744                 return 0;
5745         }
5746
5747         if (vmx_get_cpl(vcpu)) {
5748                 kvm_inject_gp(vcpu, 0);
5749                 return 0;
5750         }
5751
5752         return 1;
5753 }
5754
5755 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5756 {
5757         u32 exec_control;
5758         if (enable_shadow_vmcs) {
5759                 if (vmx->nested.current_vmcs12 != NULL) {
5760                         /* copy to memory all shadowed fields in case
5761                            they were modified */
5762                         copy_shadow_to_vmcs12(vmx);
5763                         vmx->nested.sync_shadow_vmcs = false;
5764                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5765                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5766                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5767                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5768                 }
5769         }
5770         kunmap(vmx->nested.current_vmcs12_page);
5771         nested_release_page(vmx->nested.current_vmcs12_page);
5772 }
5773
5774 /*
5775  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5776  * just stops using VMX.
5777  */
5778 static void free_nested(struct vcpu_vmx *vmx)
5779 {
5780         if (!vmx->nested.vmxon)
5781                 return;
5782         vmx->nested.vmxon = false;
5783         if (vmx->nested.current_vmptr != -1ull) {
5784                 nested_release_vmcs12(vmx);
5785                 vmx->nested.current_vmptr = -1ull;
5786                 vmx->nested.current_vmcs12 = NULL;
5787         }
5788         if (enable_shadow_vmcs)
5789                 free_vmcs(vmx->nested.current_shadow_vmcs);
5790         /* Unpin physical memory we referred to in current vmcs02 */
5791         if (vmx->nested.apic_access_page) {
5792                 nested_release_page(vmx->nested.apic_access_page);
5793                 vmx->nested.apic_access_page = 0;
5794         }
5795
5796         nested_free_all_saved_vmcss(vmx);
5797 }
5798
5799 /* Emulate the VMXOFF instruction */
5800 static int handle_vmoff(struct kvm_vcpu *vcpu)
5801 {
5802         if (!nested_vmx_check_permission(vcpu))
5803                 return 1;
5804         free_nested(to_vmx(vcpu));
5805         skip_emulated_instruction(vcpu);
5806         nested_vmx_succeed(vcpu);
5807         return 1;
5808 }
5809
5810 /*
5811  * Decode the memory-address operand of a vmx instruction, as recorded on an
5812  * exit caused by such an instruction (run by a guest hypervisor).
5813  * On success, returns 0. When the operand is invalid, returns 1 and throws
5814  * #UD or #GP.
5815  */
5816 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5817                                  unsigned long exit_qualification,
5818                                  u32 vmx_instruction_info, gva_t *ret)
5819 {
5820         /*
5821          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5822          * Execution", on an exit, vmx_instruction_info holds most of the
5823          * addressing components of the operand. Only the displacement part
5824          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5825          * For how an actual address is calculated from all these components,
5826          * refer to Vol. 1, "Operand Addressing".
5827          */
5828         int  scaling = vmx_instruction_info & 3;
5829         int  addr_size = (vmx_instruction_info >> 7) & 7;
5830         bool is_reg = vmx_instruction_info & (1u << 10);
5831         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5832         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5833         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5834         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5835         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5836
5837         if (is_reg) {
5838                 kvm_queue_exception(vcpu, UD_VECTOR);
5839                 return 1;
5840         }
5841
5842         /* Addr = segment_base + offset */
5843         /* offset = base + [index * scale] + displacement */
5844         *ret = vmx_get_segment_base(vcpu, seg_reg);
5845         if (base_is_valid)
5846                 *ret += kvm_register_read(vcpu, base_reg);
5847         if (index_is_valid)
5848                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5849         *ret += exit_qualification; /* holds the displacement */
5850
5851         if (addr_size == 1) /* 32 bit */
5852                 *ret &= 0xffffffff;
5853
5854         /*
5855          * TODO: throw #GP (and return 1) in various cases that the VM*
5856          * instructions require it - e.g., offset beyond segment limit,
5857          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5858          * address, and so on. Currently these are not checked.
5859          */
5860         return 0;
5861 }
5862
5863 /* Emulate the VMCLEAR instruction */
5864 static int handle_vmclear(struct kvm_vcpu *vcpu)
5865 {
5866         struct vcpu_vmx *vmx = to_vmx(vcpu);
5867         gva_t gva;
5868         gpa_t vmptr;
5869         struct vmcs12 *vmcs12;
5870         struct page *page;
5871         struct x86_exception e;
5872
5873         if (!nested_vmx_check_permission(vcpu))
5874                 return 1;
5875
5876         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5877                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5878                 return 1;
5879
5880         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5881                                 sizeof(vmptr), &e)) {
5882                 kvm_inject_page_fault(vcpu, &e);
5883                 return 1;
5884         }
5885
5886         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5887                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5888                 skip_emulated_instruction(vcpu);
5889                 return 1;
5890         }
5891
5892         if (vmptr == vmx->nested.current_vmptr) {
5893                 nested_release_vmcs12(vmx);
5894                 vmx->nested.current_vmptr = -1ull;
5895                 vmx->nested.current_vmcs12 = NULL;
5896         }
5897
5898         page = nested_get_page(vcpu, vmptr);
5899         if (page == NULL) {
5900                 /*
5901                  * For accurate processor emulation, VMCLEAR beyond available
5902                  * physical memory should do nothing at all. However, it is
5903                  * possible that a nested vmx bug, not a guest hypervisor bug,
5904                  * resulted in this case, so let's shut down before doing any
5905                  * more damage:
5906                  */
5907                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5908                 return 1;
5909         }
5910         vmcs12 = kmap(page);
5911         vmcs12->launch_state = 0;
5912         kunmap(page);
5913         nested_release_page(page);
5914
5915         nested_free_vmcs02(vmx, vmptr);
5916
5917         skip_emulated_instruction(vcpu);
5918         nested_vmx_succeed(vcpu);
5919         return 1;
5920 }
5921
5922 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5923
5924 /* Emulate the VMLAUNCH instruction */
5925 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5926 {
5927         return nested_vmx_run(vcpu, true);
5928 }
5929
5930 /* Emulate the VMRESUME instruction */
5931 static int handle_vmresume(struct kvm_vcpu *vcpu)
5932 {
5933
5934         return nested_vmx_run(vcpu, false);
5935 }
5936
5937 enum vmcs_field_type {
5938         VMCS_FIELD_TYPE_U16 = 0,
5939         VMCS_FIELD_TYPE_U64 = 1,
5940         VMCS_FIELD_TYPE_U32 = 2,
5941         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5942 };
5943
5944 static inline int vmcs_field_type(unsigned long field)
5945 {
5946         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5947                 return VMCS_FIELD_TYPE_U32;
5948         return (field >> 13) & 0x3 ;
5949 }
5950
5951 static inline int vmcs_field_readonly(unsigned long field)
5952 {
5953         return (((field >> 10) & 0x3) == 1);
5954 }
5955
5956 /*
5957  * Read a vmcs12 field. Since these can have varying lengths and we return
5958  * one type, we chose the biggest type (u64) and zero-extend the return value
5959  * to that size. Note that the caller, handle_vmread, might need to use only
5960  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5961  * 64-bit fields are to be returned).
5962  */
5963 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5964                                         unsigned long field, u64 *ret)
5965 {
5966         short offset = vmcs_field_to_offset(field);
5967         char *p;
5968
5969         if (offset < 0)
5970                 return 0;
5971
5972         p = ((char *)(get_vmcs12(vcpu))) + offset;
5973
5974         switch (vmcs_field_type(field)) {
5975         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5976                 *ret = *((natural_width *)p);
5977                 return 1;
5978         case VMCS_FIELD_TYPE_U16:
5979                 *ret = *((u16 *)p);
5980                 return 1;
5981         case VMCS_FIELD_TYPE_U32:
5982                 *ret = *((u32 *)p);
5983                 return 1;
5984         case VMCS_FIELD_TYPE_U64:
5985                 *ret = *((u64 *)p);
5986                 return 1;
5987         default:
5988                 return 0; /* can never happen. */
5989         }
5990 }
5991
5992
5993 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5994                                     unsigned long field, u64 field_value){
5995         short offset = vmcs_field_to_offset(field);
5996         char *p = ((char *) get_vmcs12(vcpu)) + offset;
5997         if (offset < 0)
5998                 return false;
5999
6000         switch (vmcs_field_type(field)) {
6001         case VMCS_FIELD_TYPE_U16:
6002                 *(u16 *)p = field_value;
6003                 return true;
6004         case VMCS_FIELD_TYPE_U32:
6005                 *(u32 *)p = field_value;
6006                 return true;
6007         case VMCS_FIELD_TYPE_U64:
6008                 *(u64 *)p = field_value;
6009                 return true;
6010         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6011                 *(natural_width *)p = field_value;
6012                 return true;
6013         default:
6014                 return false; /* can never happen. */
6015         }
6016
6017 }
6018
6019 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6020 {
6021         int i;
6022         unsigned long field;
6023         u64 field_value;
6024         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6025         const unsigned long *fields = shadow_read_write_fields;
6026         const int num_fields = max_shadow_read_write_fields;
6027
6028         vmcs_load(shadow_vmcs);
6029
6030         for (i = 0; i < num_fields; i++) {
6031                 field = fields[i];
6032                 switch (vmcs_field_type(field)) {
6033                 case VMCS_FIELD_TYPE_U16:
6034                         field_value = vmcs_read16(field);
6035                         break;
6036                 case VMCS_FIELD_TYPE_U32:
6037                         field_value = vmcs_read32(field);
6038                         break;
6039                 case VMCS_FIELD_TYPE_U64:
6040                         field_value = vmcs_read64(field);
6041                         break;
6042                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6043                         field_value = vmcs_readl(field);
6044                         break;
6045                 }
6046                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6047         }
6048
6049         vmcs_clear(shadow_vmcs);
6050         vmcs_load(vmx->loaded_vmcs->vmcs);
6051 }
6052
6053 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6054 {
6055         const unsigned long *fields[] = {
6056                 shadow_read_write_fields,
6057                 shadow_read_only_fields
6058         };
6059         const int max_fields[] = {
6060                 max_shadow_read_write_fields,
6061                 max_shadow_read_only_fields
6062         };
6063         int i, q;
6064         unsigned long field;
6065         u64 field_value = 0;
6066         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6067
6068         vmcs_load(shadow_vmcs);
6069
6070         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6071                 for (i = 0; i < max_fields[q]; i++) {
6072                         field = fields[q][i];
6073                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6074
6075                         switch (vmcs_field_type(field)) {
6076                         case VMCS_FIELD_TYPE_U16:
6077                                 vmcs_write16(field, (u16)field_value);
6078                                 break;
6079                         case VMCS_FIELD_TYPE_U32:
6080                                 vmcs_write32(field, (u32)field_value);
6081                                 break;
6082                         case VMCS_FIELD_TYPE_U64:
6083                                 vmcs_write64(field, (u64)field_value);
6084                                 break;
6085                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6086                                 vmcs_writel(field, (long)field_value);
6087                                 break;
6088                         }
6089                 }
6090         }
6091
6092         vmcs_clear(shadow_vmcs);
6093         vmcs_load(vmx->loaded_vmcs->vmcs);
6094 }
6095
6096 /*
6097  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6098  * used before) all generate the same failure when it is missing.
6099  */
6100 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6101 {
6102         struct vcpu_vmx *vmx = to_vmx(vcpu);
6103         if (vmx->nested.current_vmptr == -1ull) {
6104                 nested_vmx_failInvalid(vcpu);
6105                 skip_emulated_instruction(vcpu);
6106                 return 0;
6107         }
6108         return 1;
6109 }
6110
6111 static int handle_vmread(struct kvm_vcpu *vcpu)
6112 {
6113         unsigned long field;
6114         u64 field_value;
6115         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6116         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6117         gva_t gva = 0;
6118
6119         if (!nested_vmx_check_permission(vcpu) ||
6120             !nested_vmx_check_vmcs12(vcpu))
6121                 return 1;
6122
6123         /* Decode instruction info and find the field to read */
6124         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6125         /* Read the field, zero-extended to a u64 field_value */
6126         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6127                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6128                 skip_emulated_instruction(vcpu);
6129                 return 1;
6130         }
6131         /*
6132          * Now copy part of this value to register or memory, as requested.
6133          * Note that the number of bits actually copied is 32 or 64 depending
6134          * on the guest's mode (32 or 64 bit), not on the given field's length.
6135          */
6136         if (vmx_instruction_info & (1u << 10)) {
6137                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6138                         field_value);
6139         } else {
6140                 if (get_vmx_mem_address(vcpu, exit_qualification,
6141                                 vmx_instruction_info, &gva))
6142                         return 1;
6143                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6144                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6145                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6146         }
6147
6148         nested_vmx_succeed(vcpu);
6149         skip_emulated_instruction(vcpu);
6150         return 1;
6151 }
6152
6153
6154 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6155 {
6156         unsigned long field;
6157         gva_t gva;
6158         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6159         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6160         /* The value to write might be 32 or 64 bits, depending on L1's long
6161          * mode, and eventually we need to write that into a field of several
6162          * possible lengths. The code below first zero-extends the value to 64
6163          * bit (field_value), and then copies only the approriate number of
6164          * bits into the vmcs12 field.
6165          */
6166         u64 field_value = 0;
6167         struct x86_exception e;
6168
6169         if (!nested_vmx_check_permission(vcpu) ||
6170             !nested_vmx_check_vmcs12(vcpu))
6171                 return 1;
6172
6173         if (vmx_instruction_info & (1u << 10))
6174                 field_value = kvm_register_read(vcpu,
6175                         (((vmx_instruction_info) >> 3) & 0xf));
6176         else {
6177                 if (get_vmx_mem_address(vcpu, exit_qualification,
6178                                 vmx_instruction_info, &gva))
6179                         return 1;
6180                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6181                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6182                         kvm_inject_page_fault(vcpu, &e);
6183                         return 1;
6184                 }
6185         }
6186
6187
6188         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6189         if (vmcs_field_readonly(field)) {
6190                 nested_vmx_failValid(vcpu,
6191                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6192                 skip_emulated_instruction(vcpu);
6193                 return 1;
6194         }
6195
6196         if (!vmcs12_write_any(vcpu, field, field_value)) {
6197                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6198                 skip_emulated_instruction(vcpu);
6199                 return 1;
6200         }
6201
6202         nested_vmx_succeed(vcpu);
6203         skip_emulated_instruction(vcpu);
6204         return 1;
6205 }
6206
6207 /* Emulate the VMPTRLD instruction */
6208 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6209 {
6210         struct vcpu_vmx *vmx = to_vmx(vcpu);
6211         gva_t gva;
6212         gpa_t vmptr;
6213         struct x86_exception e;
6214         u32 exec_control;
6215
6216         if (!nested_vmx_check_permission(vcpu))
6217                 return 1;
6218
6219         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6220                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6221                 return 1;
6222
6223         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6224                                 sizeof(vmptr), &e)) {
6225                 kvm_inject_page_fault(vcpu, &e);
6226                 return 1;
6227         }
6228
6229         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6230                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6231                 skip_emulated_instruction(vcpu);
6232                 return 1;
6233         }
6234
6235         if (vmx->nested.current_vmptr != vmptr) {
6236                 struct vmcs12 *new_vmcs12;
6237                 struct page *page;
6238                 page = nested_get_page(vcpu, vmptr);
6239                 if (page == NULL) {
6240                         nested_vmx_failInvalid(vcpu);
6241                         skip_emulated_instruction(vcpu);
6242                         return 1;
6243                 }
6244                 new_vmcs12 = kmap(page);
6245                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6246                         kunmap(page);
6247                         nested_release_page_clean(page);
6248                         nested_vmx_failValid(vcpu,
6249                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6250                         skip_emulated_instruction(vcpu);
6251                         return 1;
6252                 }
6253                 if (vmx->nested.current_vmptr != -1ull)
6254                         nested_release_vmcs12(vmx);
6255
6256                 vmx->nested.current_vmptr = vmptr;
6257                 vmx->nested.current_vmcs12 = new_vmcs12;
6258                 vmx->nested.current_vmcs12_page = page;
6259                 if (enable_shadow_vmcs) {
6260                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6261                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6262                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6263                         vmcs_write64(VMCS_LINK_POINTER,
6264                                      __pa(vmx->nested.current_shadow_vmcs));
6265                         vmx->nested.sync_shadow_vmcs = true;
6266                 }
6267         }
6268
6269         nested_vmx_succeed(vcpu);
6270         skip_emulated_instruction(vcpu);
6271         return 1;
6272 }
6273
6274 /* Emulate the VMPTRST instruction */
6275 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6276 {
6277         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6278         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6279         gva_t vmcs_gva;
6280         struct x86_exception e;
6281
6282         if (!nested_vmx_check_permission(vcpu))
6283                 return 1;
6284
6285         if (get_vmx_mem_address(vcpu, exit_qualification,
6286                         vmx_instruction_info, &vmcs_gva))
6287                 return 1;
6288         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6289         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6290                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6291                                  sizeof(u64), &e)) {
6292                 kvm_inject_page_fault(vcpu, &e);
6293                 return 1;
6294         }
6295         nested_vmx_succeed(vcpu);
6296         skip_emulated_instruction(vcpu);
6297         return 1;
6298 }
6299
6300 /* Emulate the INVEPT instruction */
6301 static int handle_invept(struct kvm_vcpu *vcpu)
6302 {
6303         u32 vmx_instruction_info, types;
6304         unsigned long type;
6305         gva_t gva;
6306         struct x86_exception e;
6307         struct {
6308                 u64 eptp, gpa;
6309         } operand;
6310         u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6311
6312         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6313             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6314                 kvm_queue_exception(vcpu, UD_VECTOR);
6315                 return 1;
6316         }
6317
6318         if (!nested_vmx_check_permission(vcpu))
6319                 return 1;
6320
6321         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6322                 kvm_queue_exception(vcpu, UD_VECTOR);
6323                 return 1;
6324         }
6325
6326         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6327         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6328
6329         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6330
6331         if (!(types & (1UL << type))) {
6332                 nested_vmx_failValid(vcpu,
6333                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6334                 return 1;
6335         }
6336
6337         /* According to the Intel VMX instruction reference, the memory
6338          * operand is read even if it isn't needed (e.g., for type==global)
6339          */
6340         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6341                         vmx_instruction_info, &gva))
6342                 return 1;
6343         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6344                                 sizeof(operand), &e)) {
6345                 kvm_inject_page_fault(vcpu, &e);
6346                 return 1;
6347         }
6348
6349         switch (type) {
6350         case VMX_EPT_EXTENT_CONTEXT:
6351                 if ((operand.eptp & eptp_mask) !=
6352                                 (nested_ept_get_cr3(vcpu) & eptp_mask))
6353                         break;
6354         case VMX_EPT_EXTENT_GLOBAL:
6355                 kvm_mmu_sync_roots(vcpu);
6356                 kvm_mmu_flush_tlb(vcpu);
6357                 nested_vmx_succeed(vcpu);
6358                 break;
6359         default:
6360                 BUG_ON(1);
6361                 break;
6362         }
6363
6364         skip_emulated_instruction(vcpu);
6365         return 1;
6366 }
6367
6368 /*
6369  * The exit handlers return 1 if the exit was handled fully and guest execution
6370  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6371  * to be done to userspace and return 0.
6372  */
6373 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6374         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6375         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6376         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6377         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6378         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6379         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6380         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6381         [EXIT_REASON_CPUID]                   = handle_cpuid,
6382         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6383         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6384         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6385         [EXIT_REASON_HLT]                     = handle_halt,
6386         [EXIT_REASON_INVD]                    = handle_invd,
6387         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6388         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6389         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6390         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6391         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6392         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6393         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6394         [EXIT_REASON_VMREAD]                  = handle_vmread,
6395         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6396         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6397         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6398         [EXIT_REASON_VMON]                    = handle_vmon,
6399         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6400         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6401         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6402         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6403         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6404         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6405         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6406         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6407         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6408         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6409         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6410         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6411         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6412         [EXIT_REASON_INVEPT]                  = handle_invept,
6413 };
6414
6415 static const int kvm_vmx_max_exit_handlers =
6416         ARRAY_SIZE(kvm_vmx_exit_handlers);
6417
6418 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6419                                        struct vmcs12 *vmcs12)
6420 {
6421         unsigned long exit_qualification;
6422         gpa_t bitmap, last_bitmap;
6423         unsigned int port;
6424         int size;
6425         u8 b;
6426
6427         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6428                 return 1;
6429
6430         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6431                 return 0;
6432
6433         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6434
6435         port = exit_qualification >> 16;
6436         size = (exit_qualification & 7) + 1;
6437
6438         last_bitmap = (gpa_t)-1;
6439         b = -1;
6440
6441         while (size > 0) {
6442                 if (port < 0x8000)
6443                         bitmap = vmcs12->io_bitmap_a;
6444                 else if (port < 0x10000)
6445                         bitmap = vmcs12->io_bitmap_b;
6446                 else
6447                         return 1;
6448                 bitmap += (port & 0x7fff) / 8;
6449
6450                 if (last_bitmap != bitmap)
6451                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6452                                 return 1;
6453                 if (b & (1 << (port & 7)))
6454                         return 1;
6455
6456                 port++;
6457                 size--;
6458                 last_bitmap = bitmap;
6459         }
6460
6461         return 0;
6462 }
6463
6464 /*
6465  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6466  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6467  * disinterest in the current event (read or write a specific MSR) by using an
6468  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6469  */
6470 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6471         struct vmcs12 *vmcs12, u32 exit_reason)
6472 {
6473         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6474         gpa_t bitmap;
6475
6476         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6477                 return 1;
6478
6479         /*
6480          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6481          * for the four combinations of read/write and low/high MSR numbers.
6482          * First we need to figure out which of the four to use:
6483          */
6484         bitmap = vmcs12->msr_bitmap;
6485         if (exit_reason == EXIT_REASON_MSR_WRITE)
6486                 bitmap += 2048;
6487         if (msr_index >= 0xc0000000) {
6488                 msr_index -= 0xc0000000;
6489                 bitmap += 1024;
6490         }
6491
6492         /* Then read the msr_index'th bit from this bitmap: */
6493         if (msr_index < 1024*8) {
6494                 unsigned char b;
6495                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6496                         return 1;
6497                 return 1 & (b >> (msr_index & 7));
6498         } else
6499                 return 1; /* let L1 handle the wrong parameter */
6500 }
6501
6502 /*
6503  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6504  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6505  * intercept (via guest_host_mask etc.) the current event.
6506  */
6507 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6508         struct vmcs12 *vmcs12)
6509 {
6510         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6511         int cr = exit_qualification & 15;
6512         int reg = (exit_qualification >> 8) & 15;
6513         unsigned long val = kvm_register_read(vcpu, reg);
6514
6515         switch ((exit_qualification >> 4) & 3) {
6516         case 0: /* mov to cr */
6517                 switch (cr) {
6518                 case 0:
6519                         if (vmcs12->cr0_guest_host_mask &
6520                             (val ^ vmcs12->cr0_read_shadow))
6521                                 return 1;
6522                         break;
6523                 case 3:
6524                         if ((vmcs12->cr3_target_count >= 1 &&
6525                                         vmcs12->cr3_target_value0 == val) ||
6526                                 (vmcs12->cr3_target_count >= 2 &&
6527                                         vmcs12->cr3_target_value1 == val) ||
6528                                 (vmcs12->cr3_target_count >= 3 &&
6529                                         vmcs12->cr3_target_value2 == val) ||
6530                                 (vmcs12->cr3_target_count >= 4 &&
6531                                         vmcs12->cr3_target_value3 == val))
6532                                 return 0;
6533                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6534                                 return 1;
6535                         break;
6536                 case 4:
6537                         if (vmcs12->cr4_guest_host_mask &
6538                             (vmcs12->cr4_read_shadow ^ val))
6539                                 return 1;
6540                         break;
6541                 case 8:
6542                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6543                                 return 1;
6544                         break;
6545                 }
6546                 break;
6547         case 2: /* clts */
6548                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6549                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6550                         return 1;
6551                 break;
6552         case 1: /* mov from cr */
6553                 switch (cr) {
6554                 case 3:
6555                         if (vmcs12->cpu_based_vm_exec_control &
6556                             CPU_BASED_CR3_STORE_EXITING)
6557                                 return 1;
6558                         break;
6559                 case 8:
6560                         if (vmcs12->cpu_based_vm_exec_control &
6561                             CPU_BASED_CR8_STORE_EXITING)
6562                                 return 1;
6563                         break;
6564                 }
6565                 break;
6566         case 3: /* lmsw */
6567                 /*
6568                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6569                  * cr0. Other attempted changes are ignored, with no exit.
6570                  */
6571                 if (vmcs12->cr0_guest_host_mask & 0xe &
6572                     (val ^ vmcs12->cr0_read_shadow))
6573                         return 1;
6574                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6575                     !(vmcs12->cr0_read_shadow & 0x1) &&
6576                     (val & 0x1))
6577                         return 1;
6578                 break;
6579         }
6580         return 0;
6581 }
6582
6583 /*
6584  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6585  * should handle it ourselves in L0 (and then continue L2). Only call this
6586  * when in is_guest_mode (L2).
6587  */
6588 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6589 {
6590         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6591         struct vcpu_vmx *vmx = to_vmx(vcpu);
6592         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6593         u32 exit_reason = vmx->exit_reason;
6594
6595         if (vmx->nested.nested_run_pending)
6596                 return 0;
6597
6598         if (unlikely(vmx->fail)) {
6599                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6600                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6601                 return 1;
6602         }
6603
6604         switch (exit_reason) {
6605         case EXIT_REASON_EXCEPTION_NMI:
6606                 if (!is_exception(intr_info))
6607                         return 0;
6608                 else if (is_page_fault(intr_info))
6609                         return enable_ept;
6610                 return vmcs12->exception_bitmap &
6611                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6612         case EXIT_REASON_EXTERNAL_INTERRUPT:
6613                 return 0;
6614         case EXIT_REASON_TRIPLE_FAULT:
6615                 return 1;
6616         case EXIT_REASON_PENDING_INTERRUPT:
6617                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6618         case EXIT_REASON_NMI_WINDOW:
6619                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6620         case EXIT_REASON_TASK_SWITCH:
6621                 return 1;
6622         case EXIT_REASON_CPUID:
6623                 return 1;
6624         case EXIT_REASON_HLT:
6625                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6626         case EXIT_REASON_INVD:
6627                 return 1;
6628         case EXIT_REASON_INVLPG:
6629                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6630         case EXIT_REASON_RDPMC:
6631                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6632         case EXIT_REASON_RDTSC:
6633                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6634         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6635         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6636         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6637         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6638         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6639         case EXIT_REASON_INVEPT:
6640                 /*
6641                  * VMX instructions trap unconditionally. This allows L1 to
6642                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6643                  */
6644                 return 1;
6645         case EXIT_REASON_CR_ACCESS:
6646                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6647         case EXIT_REASON_DR_ACCESS:
6648                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6649         case EXIT_REASON_IO_INSTRUCTION:
6650                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6651         case EXIT_REASON_MSR_READ:
6652         case EXIT_REASON_MSR_WRITE:
6653                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6654         case EXIT_REASON_INVALID_STATE:
6655                 return 1;
6656         case EXIT_REASON_MWAIT_INSTRUCTION:
6657                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6658         case EXIT_REASON_MONITOR_INSTRUCTION:
6659                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6660         case EXIT_REASON_PAUSE_INSTRUCTION:
6661                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6662                         nested_cpu_has2(vmcs12,
6663                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6664         case EXIT_REASON_MCE_DURING_VMENTRY:
6665                 return 0;
6666         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6667                 return 1;
6668         case EXIT_REASON_APIC_ACCESS:
6669                 return nested_cpu_has2(vmcs12,
6670                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6671         case EXIT_REASON_EPT_VIOLATION:
6672         case EXIT_REASON_EPT_MISCONFIG:
6673                 return 0;
6674         case EXIT_REASON_PREEMPTION_TIMER:
6675                 return vmcs12->pin_based_vm_exec_control &
6676                         PIN_BASED_VMX_PREEMPTION_TIMER;
6677         case EXIT_REASON_WBINVD:
6678                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6679         case EXIT_REASON_XSETBV:
6680                 return 1;
6681         default:
6682                 return 1;
6683         }
6684 }
6685
6686 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6687 {
6688         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6689         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6690 }
6691
6692 /*
6693  * The guest has exited.  See if we can fix it or if we need userspace
6694  * assistance.
6695  */
6696 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6697 {
6698         struct vcpu_vmx *vmx = to_vmx(vcpu);
6699         u32 exit_reason = vmx->exit_reason;
6700         u32 vectoring_info = vmx->idt_vectoring_info;
6701
6702         /* If guest state is invalid, start emulating */
6703         if (vmx->emulation_required)
6704                 return handle_invalid_guest_state(vcpu);
6705
6706         /*
6707          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6708          * we did not inject a still-pending event to L1 now because of
6709          * nested_run_pending, we need to re-enable this bit.
6710          */
6711         if (vmx->nested.nested_run_pending)
6712                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6713
6714         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6715             exit_reason == EXIT_REASON_VMRESUME))
6716                 vmx->nested.nested_run_pending = 1;
6717         else
6718                 vmx->nested.nested_run_pending = 0;
6719
6720         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6721                 nested_vmx_vmexit(vcpu);
6722                 return 1;
6723         }
6724
6725         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6726                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6727                 vcpu->run->fail_entry.hardware_entry_failure_reason
6728                         = exit_reason;
6729                 return 0;
6730         }
6731
6732         if (unlikely(vmx->fail)) {
6733                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6734                 vcpu->run->fail_entry.hardware_entry_failure_reason
6735                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6736                 return 0;
6737         }
6738
6739         /*
6740          * Note:
6741          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6742          * delivery event since it indicates guest is accessing MMIO.
6743          * The vm-exit can be triggered again after return to guest that
6744          * will cause infinite loop.
6745          */
6746         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6747                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6748                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6749                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6750                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6751                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6752                 vcpu->run->internal.ndata = 2;
6753                 vcpu->run->internal.data[0] = vectoring_info;
6754                 vcpu->run->internal.data[1] = exit_reason;
6755                 return 0;
6756         }
6757
6758         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6759             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6760                                         get_vmcs12(vcpu), vcpu)))) {
6761                 if (vmx_interrupt_allowed(vcpu)) {
6762                         vmx->soft_vnmi_blocked = 0;
6763                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6764                            vcpu->arch.nmi_pending) {
6765                         /*
6766                          * This CPU don't support us in finding the end of an
6767                          * NMI-blocked window if the guest runs with IRQs
6768                          * disabled. So we pull the trigger after 1 s of
6769                          * futile waiting, but inform the user about this.
6770                          */
6771                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6772                                "state on VCPU %d after 1 s timeout\n",
6773                                __func__, vcpu->vcpu_id);
6774                         vmx->soft_vnmi_blocked = 0;
6775                 }
6776         }
6777
6778         if (exit_reason < kvm_vmx_max_exit_handlers
6779             && kvm_vmx_exit_handlers[exit_reason])
6780                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6781         else {
6782                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6783                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6784         }
6785         return 0;
6786 }
6787
6788 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6789 {
6790         if (irr == -1 || tpr < irr) {
6791                 vmcs_write32(TPR_THRESHOLD, 0);
6792                 return;
6793         }
6794
6795         vmcs_write32(TPR_THRESHOLD, irr);
6796 }
6797
6798 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6799 {
6800         u32 sec_exec_control;
6801
6802         /*
6803          * There is not point to enable virtualize x2apic without enable
6804          * apicv
6805          */
6806         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6807                                 !vmx_vm_has_apicv(vcpu->kvm))
6808                 return;
6809
6810         if (!vm_need_tpr_shadow(vcpu->kvm))
6811                 return;
6812
6813         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6814
6815         if (set) {
6816                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6817                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6818         } else {
6819                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6820                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6821         }
6822         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6823
6824         vmx_set_msr_bitmap(vcpu);
6825 }
6826
6827 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6828 {
6829         u16 status;
6830         u8 old;
6831
6832         if (!vmx_vm_has_apicv(kvm))
6833                 return;
6834
6835         if (isr == -1)
6836                 isr = 0;
6837
6838         status = vmcs_read16(GUEST_INTR_STATUS);
6839         old = status >> 8;
6840         if (isr != old) {
6841                 status &= 0xff;
6842                 status |= isr << 8;
6843                 vmcs_write16(GUEST_INTR_STATUS, status);
6844         }
6845 }
6846
6847 static void vmx_set_rvi(int vector)
6848 {
6849         u16 status;
6850         u8 old;
6851
6852         status = vmcs_read16(GUEST_INTR_STATUS);
6853         old = (u8)status & 0xff;
6854         if ((u8)vector != old) {
6855                 status &= ~0xff;
6856                 status |= (u8)vector;
6857                 vmcs_write16(GUEST_INTR_STATUS, status);
6858         }
6859 }
6860
6861 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6862 {
6863         if (max_irr == -1)
6864                 return;
6865
6866         vmx_set_rvi(max_irr);
6867 }
6868
6869 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6870 {
6871         if (!vmx_vm_has_apicv(vcpu->kvm))
6872                 return;
6873
6874         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6875         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6876         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6877         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6878 }
6879
6880 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6881 {
6882         u32 exit_intr_info;
6883
6884         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6885               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6886                 return;
6887
6888         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6889         exit_intr_info = vmx->exit_intr_info;
6890
6891         /* Handle machine checks before interrupts are enabled */
6892         if (is_machine_check(exit_intr_info))
6893                 kvm_machine_check();
6894
6895         /* We need to handle NMIs before interrupts are enabled */
6896         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6897             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6898                 kvm_before_handle_nmi(&vmx->vcpu);
6899                 asm("int $2");
6900                 kvm_after_handle_nmi(&vmx->vcpu);
6901         }
6902 }
6903
6904 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6905 {
6906         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6907
6908         /*
6909          * If external interrupt exists, IF bit is set in rflags/eflags on the
6910          * interrupt stack frame, and interrupt will be enabled on a return
6911          * from interrupt handler.
6912          */
6913         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6914                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6915                 unsigned int vector;
6916                 unsigned long entry;
6917                 gate_desc *desc;
6918                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6919 #ifdef CONFIG_X86_64
6920                 unsigned long tmp;
6921 #endif
6922
6923                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6924                 desc = (gate_desc *)vmx->host_idt_base + vector;
6925                 entry = gate_offset(*desc);
6926                 asm volatile(
6927 #ifdef CONFIG_X86_64
6928                         "mov %%" _ASM_SP ", %[sp]\n\t"
6929                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6930                         "push $%c[ss]\n\t"
6931                         "push %[sp]\n\t"
6932 #endif
6933                         "pushf\n\t"
6934                         "orl $0x200, (%%" _ASM_SP ")\n\t"
6935                         __ASM_SIZE(push) " $%c[cs]\n\t"
6936                         "call *%[entry]\n\t"
6937                         :
6938 #ifdef CONFIG_X86_64
6939                         [sp]"=&r"(tmp)
6940 #endif
6941                         :
6942                         [entry]"r"(entry),
6943                         [ss]"i"(__KERNEL_DS),
6944                         [cs]"i"(__KERNEL_CS)
6945                         );
6946         } else
6947                 local_irq_enable();
6948 }
6949
6950 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6951 {
6952         u32 exit_intr_info;
6953         bool unblock_nmi;
6954         u8 vector;
6955         bool idtv_info_valid;
6956
6957         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6958
6959         if (cpu_has_virtual_nmis()) {
6960                 if (vmx->nmi_known_unmasked)
6961                         return;
6962                 /*
6963                  * Can't use vmx->exit_intr_info since we're not sure what
6964                  * the exit reason is.
6965                  */
6966                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6967                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6968                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6969                 /*
6970                  * SDM 3: 27.7.1.2 (September 2008)
6971                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6972                  * a guest IRET fault.
6973                  * SDM 3: 23.2.2 (September 2008)
6974                  * Bit 12 is undefined in any of the following cases:
6975                  *  If the VM exit sets the valid bit in the IDT-vectoring
6976                  *   information field.
6977                  *  If the VM exit is due to a double fault.
6978                  */
6979                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6980                     vector != DF_VECTOR && !idtv_info_valid)
6981                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6982                                       GUEST_INTR_STATE_NMI);
6983                 else
6984                         vmx->nmi_known_unmasked =
6985                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6986                                   & GUEST_INTR_STATE_NMI);
6987         } else if (unlikely(vmx->soft_vnmi_blocked))
6988                 vmx->vnmi_blocked_time +=
6989                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6990 }
6991
6992 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6993                                       u32 idt_vectoring_info,
6994                                       int instr_len_field,
6995                                       int error_code_field)
6996 {
6997         u8 vector;
6998         int type;
6999         bool idtv_info_valid;
7000
7001         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7002
7003         vcpu->arch.nmi_injected = false;
7004         kvm_clear_exception_queue(vcpu);
7005         kvm_clear_interrupt_queue(vcpu);
7006
7007         if (!idtv_info_valid)
7008                 return;
7009
7010         kvm_make_request(KVM_REQ_EVENT, vcpu);
7011
7012         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7013         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7014
7015         switch (type) {
7016         case INTR_TYPE_NMI_INTR:
7017                 vcpu->arch.nmi_injected = true;
7018                 /*
7019                  * SDM 3: 27.7.1.2 (September 2008)
7020                  * Clear bit "block by NMI" before VM entry if a NMI
7021                  * delivery faulted.
7022                  */
7023                 vmx_set_nmi_mask(vcpu, false);
7024                 break;
7025         case INTR_TYPE_SOFT_EXCEPTION:
7026                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7027                 /* fall through */
7028         case INTR_TYPE_HARD_EXCEPTION:
7029                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7030                         u32 err = vmcs_read32(error_code_field);
7031                         kvm_queue_exception_e(vcpu, vector, err);
7032                 } else
7033                         kvm_queue_exception(vcpu, vector);
7034                 break;
7035         case INTR_TYPE_SOFT_INTR:
7036                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7037                 /* fall through */
7038         case INTR_TYPE_EXT_INTR:
7039                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7040                 break;
7041         default:
7042                 break;
7043         }
7044 }
7045
7046 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7047 {
7048         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7049                                   VM_EXIT_INSTRUCTION_LEN,
7050                                   IDT_VECTORING_ERROR_CODE);
7051 }
7052
7053 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7054 {
7055         __vmx_complete_interrupts(vcpu,
7056                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7057                                   VM_ENTRY_INSTRUCTION_LEN,
7058                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7059
7060         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7061 }
7062
7063 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7064 {
7065         int i, nr_msrs;
7066         struct perf_guest_switch_msr *msrs;
7067
7068         msrs = perf_guest_get_msrs(&nr_msrs);
7069
7070         if (!msrs)
7071                 return;
7072
7073         for (i = 0; i < nr_msrs; i++)
7074                 if (msrs[i].host == msrs[i].guest)
7075                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7076                 else
7077                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7078                                         msrs[i].host);
7079 }
7080
7081 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7082 {
7083         struct vcpu_vmx *vmx = to_vmx(vcpu);
7084         unsigned long debugctlmsr;
7085
7086         /* Record the guest's net vcpu time for enforced NMI injections. */
7087         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7088                 vmx->entry_time = ktime_get();
7089
7090         /* Don't enter VMX if guest state is invalid, let the exit handler
7091            start emulation until we arrive back to a valid state */
7092         if (vmx->emulation_required)
7093                 return;
7094
7095         if (vmx->nested.sync_shadow_vmcs) {
7096                 copy_vmcs12_to_shadow(vmx);
7097                 vmx->nested.sync_shadow_vmcs = false;
7098         }
7099
7100         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7101                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7102         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7103                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7104
7105         /* When single-stepping over STI and MOV SS, we must clear the
7106          * corresponding interruptibility bits in the guest state. Otherwise
7107          * vmentry fails as it then expects bit 14 (BS) in pending debug
7108          * exceptions being set, but that's not correct for the guest debugging
7109          * case. */
7110         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7111                 vmx_set_interrupt_shadow(vcpu, 0);
7112
7113         atomic_switch_perf_msrs(vmx);
7114         debugctlmsr = get_debugctlmsr();
7115
7116         vmx->__launched = vmx->loaded_vmcs->launched;
7117         asm(
7118                 /* Store host registers */
7119                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7120                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7121                 "push %%" _ASM_CX " \n\t"
7122                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7123                 "je 1f \n\t"
7124                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7125                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7126                 "1: \n\t"
7127                 /* Reload cr2 if changed */
7128                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7129                 "mov %%cr2, %%" _ASM_DX " \n\t"
7130                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7131                 "je 2f \n\t"
7132                 "mov %%" _ASM_AX", %%cr2 \n\t"
7133                 "2: \n\t"
7134                 /* Check if vmlaunch of vmresume is needed */
7135                 "cmpl $0, %c[launched](%0) \n\t"
7136                 /* Load guest registers.  Don't clobber flags. */
7137                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7138                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7139                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7140                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7141                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7142                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7143 #ifdef CONFIG_X86_64
7144                 "mov %c[r8](%0),  %%r8  \n\t"
7145                 "mov %c[r9](%0),  %%r9  \n\t"
7146                 "mov %c[r10](%0), %%r10 \n\t"
7147                 "mov %c[r11](%0), %%r11 \n\t"
7148                 "mov %c[r12](%0), %%r12 \n\t"
7149                 "mov %c[r13](%0), %%r13 \n\t"
7150                 "mov %c[r14](%0), %%r14 \n\t"
7151                 "mov %c[r15](%0), %%r15 \n\t"
7152 #endif
7153                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7154
7155                 /* Enter guest mode */
7156                 "jne 1f \n\t"
7157                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7158                 "jmp 2f \n\t"
7159                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7160                 "2: "
7161                 /* Save guest registers, load host registers, keep flags */
7162                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7163                 "pop %0 \n\t"
7164                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7165                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7166                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7167                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7168                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7169                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7170                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7171 #ifdef CONFIG_X86_64
7172                 "mov %%r8,  %c[r8](%0) \n\t"
7173                 "mov %%r9,  %c[r9](%0) \n\t"
7174                 "mov %%r10, %c[r10](%0) \n\t"
7175                 "mov %%r11, %c[r11](%0) \n\t"
7176                 "mov %%r12, %c[r12](%0) \n\t"
7177                 "mov %%r13, %c[r13](%0) \n\t"
7178                 "mov %%r14, %c[r14](%0) \n\t"
7179                 "mov %%r15, %c[r15](%0) \n\t"
7180 #endif
7181                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7182                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7183
7184                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7185                 "setbe %c[fail](%0) \n\t"
7186                 ".pushsection .rodata \n\t"
7187                 ".global vmx_return \n\t"
7188                 "vmx_return: " _ASM_PTR " 2b \n\t"
7189                 ".popsection"
7190               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7191                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7192                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7193                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7194                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7195                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7196                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7197                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7198                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7199                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7200                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7201 #ifdef CONFIG_X86_64
7202                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7203                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7204                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7205                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7206                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7207                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7208                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7209                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7210 #endif
7211                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7212                 [wordsize]"i"(sizeof(ulong))
7213               : "cc", "memory"
7214 #ifdef CONFIG_X86_64
7215                 , "rax", "rbx", "rdi", "rsi"
7216                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7217 #else
7218                 , "eax", "ebx", "edi", "esi"
7219 #endif
7220               );
7221
7222         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7223         if (debugctlmsr)
7224                 update_debugctlmsr(debugctlmsr);
7225
7226 #ifndef CONFIG_X86_64
7227         /*
7228          * The sysexit path does not restore ds/es, so we must set them to
7229          * a reasonable value ourselves.
7230          *
7231          * We can't defer this to vmx_load_host_state() since that function
7232          * may be executed in interrupt context, which saves and restore segments
7233          * around it, nullifying its effect.
7234          */
7235         loadsegment(ds, __USER_DS);
7236         loadsegment(es, __USER_DS);
7237 #endif
7238
7239         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7240                                   | (1 << VCPU_EXREG_RFLAGS)
7241                                   | (1 << VCPU_EXREG_CPL)
7242                                   | (1 << VCPU_EXREG_PDPTR)
7243                                   | (1 << VCPU_EXREG_SEGMENTS)
7244                                   | (1 << VCPU_EXREG_CR3));
7245         vcpu->arch.regs_dirty = 0;
7246
7247         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7248
7249         vmx->loaded_vmcs->launched = 1;
7250
7251         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7252         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7253
7254         vmx_complete_atomic_exit(vmx);
7255         vmx_recover_nmi_blocking(vmx);
7256         vmx_complete_interrupts(vmx);
7257 }
7258
7259 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7260 {
7261         struct vcpu_vmx *vmx = to_vmx(vcpu);
7262
7263         free_vpid(vmx);
7264         free_nested(vmx);
7265         free_loaded_vmcs(vmx->loaded_vmcs);
7266         kfree(vmx->guest_msrs);
7267         kvm_vcpu_uninit(vcpu);
7268         kmem_cache_free(kvm_vcpu_cache, vmx);
7269 }
7270
7271 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7272 {
7273         int err;
7274         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7275         int cpu;
7276
7277         if (!vmx)
7278                 return ERR_PTR(-ENOMEM);
7279
7280         allocate_vpid(vmx);
7281
7282         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7283         if (err)
7284                 goto free_vcpu;
7285
7286         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7287         err = -ENOMEM;
7288         if (!vmx->guest_msrs) {
7289                 goto uninit_vcpu;
7290         }
7291
7292         vmx->loaded_vmcs = &vmx->vmcs01;
7293         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7294         if (!vmx->loaded_vmcs->vmcs)
7295                 goto free_msrs;
7296         if (!vmm_exclusive)
7297                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7298         loaded_vmcs_init(vmx->loaded_vmcs);
7299         if (!vmm_exclusive)
7300                 kvm_cpu_vmxoff();
7301
7302         cpu = get_cpu();
7303         vmx_vcpu_load(&vmx->vcpu, cpu);
7304         vmx->vcpu.cpu = cpu;
7305         err = vmx_vcpu_setup(vmx);
7306         vmx_vcpu_put(&vmx->vcpu);
7307         put_cpu();
7308         if (err)
7309                 goto free_vmcs;
7310         if (vm_need_virtualize_apic_accesses(kvm)) {
7311                 err = alloc_apic_access_page(kvm);
7312                 if (err)
7313                         goto free_vmcs;
7314         }
7315
7316         if (enable_ept) {
7317                 if (!kvm->arch.ept_identity_map_addr)
7318                         kvm->arch.ept_identity_map_addr =
7319                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7320                 err = -ENOMEM;
7321                 if (alloc_identity_pagetable(kvm) != 0)
7322                         goto free_vmcs;
7323                 if (!init_rmode_identity_map(kvm))
7324                         goto free_vmcs;
7325         }
7326
7327         vmx->nested.current_vmptr = -1ull;
7328         vmx->nested.current_vmcs12 = NULL;
7329
7330         return &vmx->vcpu;
7331
7332 free_vmcs:
7333         free_loaded_vmcs(vmx->loaded_vmcs);
7334 free_msrs:
7335         kfree(vmx->guest_msrs);
7336 uninit_vcpu:
7337         kvm_vcpu_uninit(&vmx->vcpu);
7338 free_vcpu:
7339         free_vpid(vmx);
7340         kmem_cache_free(kvm_vcpu_cache, vmx);
7341         return ERR_PTR(err);
7342 }
7343
7344 static void __init vmx_check_processor_compat(void *rtn)
7345 {
7346         struct vmcs_config vmcs_conf;
7347
7348         *(int *)rtn = 0;
7349         if (setup_vmcs_config(&vmcs_conf) < 0)
7350                 *(int *)rtn = -EIO;
7351         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7352                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7353                                 smp_processor_id());
7354                 *(int *)rtn = -EIO;
7355         }
7356 }
7357
7358 static int get_ept_level(void)
7359 {
7360         return VMX_EPT_DEFAULT_GAW + 1;
7361 }
7362
7363 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7364 {
7365         u64 ret;
7366
7367         /* For VT-d and EPT combination
7368          * 1. MMIO: always map as UC
7369          * 2. EPT with VT-d:
7370          *   a. VT-d without snooping control feature: can't guarantee the
7371          *      result, try to trust guest.
7372          *   b. VT-d with snooping control feature: snooping control feature of
7373          *      VT-d engine can guarantee the cache correctness. Just set it
7374          *      to WB to keep consistent with host. So the same as item 3.
7375          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7376          *    consistent with host MTRR
7377          */
7378         if (is_mmio)
7379                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7380         else if (vcpu->kvm->arch.iommu_domain &&
7381                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7382                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7383                       VMX_EPT_MT_EPTE_SHIFT;
7384         else
7385                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7386                         | VMX_EPT_IPAT_BIT;
7387
7388         return ret;
7389 }
7390
7391 static int vmx_get_lpage_level(void)
7392 {
7393         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7394                 return PT_DIRECTORY_LEVEL;
7395         else
7396                 /* For shadow and EPT supported 1GB page */
7397                 return PT_PDPE_LEVEL;
7398 }
7399
7400 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7401 {
7402         struct kvm_cpuid_entry2 *best;
7403         struct vcpu_vmx *vmx = to_vmx(vcpu);
7404         u32 exec_control;
7405
7406         vmx->rdtscp_enabled = false;
7407         if (vmx_rdtscp_supported()) {
7408                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7409                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7410                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7411                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7412                                 vmx->rdtscp_enabled = true;
7413                         else {
7414                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7415                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7416                                                 exec_control);
7417                         }
7418                 }
7419         }
7420
7421         /* Exposing INVPCID only when PCID is exposed */
7422         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7423         if (vmx_invpcid_supported() &&
7424             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7425             guest_cpuid_has_pcid(vcpu)) {
7426                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7427                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7428                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7429                              exec_control);
7430         } else {
7431                 if (cpu_has_secondary_exec_ctrls()) {
7432                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7433                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7434                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7435                                      exec_control);
7436                 }
7437                 if (best)
7438                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7439         }
7440 }
7441
7442 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7443 {
7444         if (func == 1 && nested)
7445                 entry->ecx |= bit(X86_FEATURE_VMX);
7446 }
7447
7448 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7449                 struct x86_exception *fault)
7450 {
7451         struct vmcs12 *vmcs12;
7452         nested_vmx_vmexit(vcpu);
7453         vmcs12 = get_vmcs12(vcpu);
7454
7455         if (fault->error_code & PFERR_RSVD_MASK)
7456                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7457         else
7458                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7459         vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7460         vmcs12->guest_physical_address = fault->address;
7461 }
7462
7463 /* Callbacks for nested_ept_init_mmu_context: */
7464
7465 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7466 {
7467         /* return the page table to be shadowed - in our case, EPT12 */
7468         return get_vmcs12(vcpu)->ept_pointer;
7469 }
7470
7471 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7472 {
7473         int r = kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7474                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7475
7476         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7477         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7478         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7479
7480         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7481
7482         return r;
7483 }
7484
7485 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7486 {
7487         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7488 }
7489
7490 /*
7491  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7492  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7493  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7494  * guest in a way that will both be appropriate to L1's requests, and our
7495  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7496  * function also has additional necessary side-effects, like setting various
7497  * vcpu->arch fields.
7498  */
7499 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7500 {
7501         struct vcpu_vmx *vmx = to_vmx(vcpu);
7502         u32 exec_control;
7503
7504         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7505         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7506         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7507         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7508         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7509         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7510         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7511         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7512         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7513         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7514         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7515         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7516         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7517         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7518         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7519         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7520         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7521         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7522         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7523         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7524         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7525         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7526         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7527         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7528         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7529         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7530         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7531         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7532         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7533         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7534         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7535         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7536         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7537         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7538         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7539         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7540
7541         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7542         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7543                 vmcs12->vm_entry_intr_info_field);
7544         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7545                 vmcs12->vm_entry_exception_error_code);
7546         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7547                 vmcs12->vm_entry_instruction_len);
7548         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7549                 vmcs12->guest_interruptibility_info);
7550         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7551         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7552         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7553         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7554                 vmcs12->guest_pending_dbg_exceptions);
7555         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7556         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7557
7558         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7559
7560         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7561                 (vmcs_config.pin_based_exec_ctrl |
7562                  vmcs12->pin_based_vm_exec_control));
7563
7564         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7565                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7566                              vmcs12->vmx_preemption_timer_value);
7567
7568         /*
7569          * Whether page-faults are trapped is determined by a combination of
7570          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7571          * If enable_ept, L0 doesn't care about page faults and we should
7572          * set all of these to L1's desires. However, if !enable_ept, L0 does
7573          * care about (at least some) page faults, and because it is not easy
7574          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7575          * to exit on each and every L2 page fault. This is done by setting
7576          * MASK=MATCH=0 and (see below) EB.PF=1.
7577          * Note that below we don't need special code to set EB.PF beyond the
7578          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7579          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7580          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7581          *
7582          * A problem with this approach (when !enable_ept) is that L1 may be
7583          * injected with more page faults than it asked for. This could have
7584          * caused problems, but in practice existing hypervisors don't care.
7585          * To fix this, we will need to emulate the PFEC checking (on the L1
7586          * page tables), using walk_addr(), when injecting PFs to L1.
7587          */
7588         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7589                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7590         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7591                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7592
7593         if (cpu_has_secondary_exec_ctrls()) {
7594                 u32 exec_control = vmx_secondary_exec_control(vmx);
7595                 if (!vmx->rdtscp_enabled)
7596                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7597                 /* Take the following fields only from vmcs12 */
7598                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7599                 if (nested_cpu_has(vmcs12,
7600                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7601                         exec_control |= vmcs12->secondary_vm_exec_control;
7602
7603                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7604                         /*
7605                          * Translate L1 physical address to host physical
7606                          * address for vmcs02. Keep the page pinned, so this
7607                          * physical address remains valid. We keep a reference
7608                          * to it so we can release it later.
7609                          */
7610                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7611                                 nested_release_page(vmx->nested.apic_access_page);
7612                         vmx->nested.apic_access_page =
7613                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7614                         /*
7615                          * If translation failed, no matter: This feature asks
7616                          * to exit when accessing the given address, and if it
7617                          * can never be accessed, this feature won't do
7618                          * anything anyway.
7619                          */
7620                         if (!vmx->nested.apic_access_page)
7621                                 exec_control &=
7622                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7623                         else
7624                                 vmcs_write64(APIC_ACCESS_ADDR,
7625                                   page_to_phys(vmx->nested.apic_access_page));
7626                 }
7627
7628                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7629         }
7630
7631
7632         /*
7633          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7634          * Some constant fields are set here by vmx_set_constant_host_state().
7635          * Other fields are different per CPU, and will be set later when
7636          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7637          */
7638         vmx_set_constant_host_state(vmx);
7639
7640         /*
7641          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7642          * entry, but only if the current (host) sp changed from the value
7643          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7644          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7645          * here we just force the write to happen on entry.
7646          */
7647         vmx->host_rsp = 0;
7648
7649         exec_control = vmx_exec_control(vmx); /* L0's desires */
7650         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7651         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7652         exec_control &= ~CPU_BASED_TPR_SHADOW;
7653         exec_control |= vmcs12->cpu_based_vm_exec_control;
7654         /*
7655          * Merging of IO and MSR bitmaps not currently supported.
7656          * Rather, exit every time.
7657          */
7658         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7659         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7660         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7661
7662         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7663
7664         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7665          * bitwise-or of what L1 wants to trap for L2, and what we want to
7666          * trap. Note that CR0.TS also needs updating - we do this later.
7667          */
7668         update_exception_bitmap(vcpu);
7669         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7670         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7671
7672         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7673          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7674          * bits are further modified by vmx_set_efer() below.
7675          */
7676         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7677
7678         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7679          * emulated by vmx_set_efer(), below.
7680          */
7681         vmcs_write32(VM_ENTRY_CONTROLS,
7682                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7683                         ~VM_ENTRY_IA32E_MODE) |
7684                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7685
7686         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7687                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7688         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7689                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7690
7691
7692         set_cr4_guest_host_mask(vmx);
7693
7694         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7695                 vmcs_write64(TSC_OFFSET,
7696                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7697         else
7698                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7699
7700         if (enable_vpid) {
7701                 /*
7702                  * Trivially support vpid by letting L2s share their parent
7703                  * L1's vpid. TODO: move to a more elaborate solution, giving
7704                  * each L2 its own vpid and exposing the vpid feature to L1.
7705                  */
7706                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7707                 vmx_flush_tlb(vcpu);
7708         }
7709
7710         if (nested_cpu_has_ept(vmcs12)) {
7711                 kvm_mmu_unload(vcpu);
7712                 nested_ept_init_mmu_context(vcpu);
7713         }
7714
7715         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7716                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7717         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7718                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7719         else
7720                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7721         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7722         vmx_set_efer(vcpu, vcpu->arch.efer);
7723
7724         /*
7725          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7726          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7727          * The CR0_READ_SHADOW is what L2 should have expected to read given
7728          * the specifications by L1; It's not enough to take
7729          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7730          * have more bits than L1 expected.
7731          */
7732         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7733         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7734
7735         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7736         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7737
7738         /* shadow page tables on either EPT or shadow page tables */
7739         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7740         kvm_mmu_reset_context(vcpu);
7741
7742         /*
7743          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7744          */
7745         if (enable_ept) {
7746                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7747                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7748                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7749                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7750         }
7751
7752         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7753         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7754 }
7755
7756 /*
7757  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7758  * for running an L2 nested guest.
7759  */
7760 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7761 {
7762         struct vmcs12 *vmcs12;
7763         struct vcpu_vmx *vmx = to_vmx(vcpu);
7764         int cpu;
7765         struct loaded_vmcs *vmcs02;
7766         bool ia32e;
7767
7768         if (!nested_vmx_check_permission(vcpu) ||
7769             !nested_vmx_check_vmcs12(vcpu))
7770                 return 1;
7771
7772         skip_emulated_instruction(vcpu);
7773         vmcs12 = get_vmcs12(vcpu);
7774
7775         if (enable_shadow_vmcs)
7776                 copy_shadow_to_vmcs12(vmx);
7777
7778         /*
7779          * The nested entry process starts with enforcing various prerequisites
7780          * on vmcs12 as required by the Intel SDM, and act appropriately when
7781          * they fail: As the SDM explains, some conditions should cause the
7782          * instruction to fail, while others will cause the instruction to seem
7783          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7784          * To speed up the normal (success) code path, we should avoid checking
7785          * for misconfigurations which will anyway be caught by the processor
7786          * when using the merged vmcs02.
7787          */
7788         if (vmcs12->launch_state == launch) {
7789                 nested_vmx_failValid(vcpu,
7790                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7791                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7792                 return 1;
7793         }
7794
7795         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7796                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7797                 return 1;
7798         }
7799
7800         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7801                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7802                 /*TODO: Also verify bits beyond physical address width are 0*/
7803                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7804                 return 1;
7805         }
7806
7807         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7808                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7809                 /*TODO: Also verify bits beyond physical address width are 0*/
7810                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7811                 return 1;
7812         }
7813
7814         if (vmcs12->vm_entry_msr_load_count > 0 ||
7815             vmcs12->vm_exit_msr_load_count > 0 ||
7816             vmcs12->vm_exit_msr_store_count > 0) {
7817                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7818                                     __func__);
7819                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7820                 return 1;
7821         }
7822
7823         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7824               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7825             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7826               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7827             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7828               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7829             !vmx_control_verify(vmcs12->vm_exit_controls,
7830               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7831             !vmx_control_verify(vmcs12->vm_entry_controls,
7832               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7833         {
7834                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7835                 return 1;
7836         }
7837
7838         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7839             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7840                 nested_vmx_failValid(vcpu,
7841                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7842                 return 1;
7843         }
7844
7845         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7846             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7847                 nested_vmx_entry_failure(vcpu, vmcs12,
7848                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7849                 return 1;
7850         }
7851         if (vmcs12->vmcs_link_pointer != -1ull) {
7852                 nested_vmx_entry_failure(vcpu, vmcs12,
7853                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7854                 return 1;
7855         }
7856
7857         /*
7858          * If the load IA32_EFER VM-entry control is 1, the following checks
7859          * are performed on the field for the IA32_EFER MSR:
7860          * - Bits reserved in the IA32_EFER MSR must be 0.
7861          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7862          *   the IA-32e mode guest VM-exit control. It must also be identical
7863          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7864          *   CR0.PG) is 1.
7865          */
7866         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7867                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7868                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7869                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7870                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7871                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7872                         nested_vmx_entry_failure(vcpu, vmcs12,
7873                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7874                         return 1;
7875                 }
7876         }
7877
7878         /*
7879          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7880          * IA32_EFER MSR must be 0 in the field for that register. In addition,
7881          * the values of the LMA and LME bits in the field must each be that of
7882          * the host address-space size VM-exit control.
7883          */
7884         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7885                 ia32e = (vmcs12->vm_exit_controls &
7886                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7887                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7888                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7889                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7890                         nested_vmx_entry_failure(vcpu, vmcs12,
7891                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7892                         return 1;
7893                 }
7894         }
7895
7896         /*
7897          * We're finally done with prerequisite checking, and can start with
7898          * the nested entry.
7899          */
7900
7901         vmcs02 = nested_get_current_vmcs02(vmx);
7902         if (!vmcs02)
7903                 return -ENOMEM;
7904
7905         enter_guest_mode(vcpu);
7906
7907         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7908
7909         cpu = get_cpu();
7910         vmx->loaded_vmcs = vmcs02;
7911         vmx_vcpu_put(vcpu);
7912         vmx_vcpu_load(vcpu, cpu);
7913         vcpu->cpu = cpu;
7914         put_cpu();
7915
7916         vmx_segment_cache_clear(vmx);
7917
7918         vmcs12->launch_state = 1;
7919
7920         prepare_vmcs02(vcpu, vmcs12);
7921
7922         /*
7923          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7924          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7925          * returned as far as L1 is concerned. It will only return (and set
7926          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7927          */
7928         return 1;
7929 }
7930
7931 /*
7932  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7933  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7934  * This function returns the new value we should put in vmcs12.guest_cr0.
7935  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7936  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7937  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7938  *     didn't trap the bit, because if L1 did, so would L0).
7939  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7940  *     been modified by L2, and L1 knows it. So just leave the old value of
7941  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7942  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7943  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7944  *     changed these bits, and therefore they need to be updated, but L0
7945  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7946  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7947  */
7948 static inline unsigned long
7949 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7950 {
7951         return
7952         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7953         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7954         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7955                         vcpu->arch.cr0_guest_owned_bits));
7956 }
7957
7958 static inline unsigned long
7959 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7960 {
7961         return
7962         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7963         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7964         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7965                         vcpu->arch.cr4_guest_owned_bits));
7966 }
7967
7968 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7969                                        struct vmcs12 *vmcs12)
7970 {
7971         u32 idt_vectoring;
7972         unsigned int nr;
7973
7974         if (vcpu->arch.exception.pending) {
7975                 nr = vcpu->arch.exception.nr;
7976                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7977
7978                 if (kvm_exception_is_soft(nr)) {
7979                         vmcs12->vm_exit_instruction_len =
7980                                 vcpu->arch.event_exit_inst_len;
7981                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7982                 } else
7983                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7984
7985                 if (vcpu->arch.exception.has_error_code) {
7986                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7987                         vmcs12->idt_vectoring_error_code =
7988                                 vcpu->arch.exception.error_code;
7989                 }
7990
7991                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7992         } else if (vcpu->arch.nmi_pending) {
7993                 vmcs12->idt_vectoring_info_field =
7994                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7995         } else if (vcpu->arch.interrupt.pending) {
7996                 nr = vcpu->arch.interrupt.nr;
7997                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7998
7999                 if (vcpu->arch.interrupt.soft) {
8000                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8001                         vmcs12->vm_entry_instruction_len =
8002                                 vcpu->arch.event_exit_inst_len;
8003                 } else
8004                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8005
8006                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8007         }
8008 }
8009
8010 /*
8011  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8012  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8013  * and this function updates it to reflect the changes to the guest state while
8014  * L2 was running (and perhaps made some exits which were handled directly by L0
8015  * without going back to L1), and to reflect the exit reason.
8016  * Note that we do not have to copy here all VMCS fields, just those that
8017  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8018  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8019  * which already writes to vmcs12 directly.
8020  */
8021 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8022 {
8023         /* update guest state fields: */
8024         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8025         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8026
8027         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8028         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8029         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8030         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8031
8032         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8033         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8034         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8035         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8036         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8037         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8038         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8039         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8040         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8041         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8042         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8043         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8044         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8045         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8046         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8047         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8048         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8049         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8050         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8051         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8052         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8053         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8054         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8055         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8056         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8057         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8058         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8059         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8060         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8061         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8062         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8063         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8064         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8065         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8066         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8067         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8068
8069         vmcs12->guest_interruptibility_info =
8070                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8071         vmcs12->guest_pending_dbg_exceptions =
8072                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8073
8074         /*
8075          * In some cases (usually, nested EPT), L2 is allowed to change its
8076          * own CR3 without exiting. If it has changed it, we must keep it.
8077          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8078          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8079          *
8080          * Additionally, restore L2's PDPTR to vmcs12.
8081          */
8082         if (enable_ept) {
8083                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8084                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8085                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8086                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8087                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8088         }
8089
8090         vmcs12->vm_entry_controls =
8091                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8092                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8093
8094         /* TODO: These cannot have changed unless we have MSR bitmaps and
8095          * the relevant bit asks not to trap the change */
8096         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8097         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8098                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8099         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8100         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8101         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8102
8103         /* update exit information fields: */
8104
8105         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
8106         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8107
8108         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8109         if ((vmcs12->vm_exit_intr_info &
8110              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8111             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8112                 vmcs12->vm_exit_intr_error_code =
8113                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8114         vmcs12->idt_vectoring_info_field = 0;
8115         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8116         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8117
8118         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8119                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8120                  * instead of reading the real value. */
8121                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8122
8123                 /*
8124                  * Transfer the event that L0 or L1 may wanted to inject into
8125                  * L2 to IDT_VECTORING_INFO_FIELD.
8126                  */
8127                 vmcs12_save_pending_event(vcpu, vmcs12);
8128         }
8129
8130         /*
8131          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8132          * preserved above and would only end up incorrectly in L1.
8133          */
8134         vcpu->arch.nmi_injected = false;
8135         kvm_clear_exception_queue(vcpu);
8136         kvm_clear_interrupt_queue(vcpu);
8137 }
8138
8139 /*
8140  * A part of what we need to when the nested L2 guest exits and we want to
8141  * run its L1 parent, is to reset L1's guest state to the host state specified
8142  * in vmcs12.
8143  * This function is to be called not only on normal nested exit, but also on
8144  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8145  * Failures During or After Loading Guest State").
8146  * This function should be called when the active VMCS is L1's (vmcs01).
8147  */
8148 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8149                                    struct vmcs12 *vmcs12)
8150 {
8151         struct kvm_segment seg;
8152
8153         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8154                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8155         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8156                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8157         else
8158                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8159         vmx_set_efer(vcpu, vcpu->arch.efer);
8160
8161         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8162         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8163         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8164         /*
8165          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8166          * actually changed, because it depends on the current state of
8167          * fpu_active (which may have changed).
8168          * Note that vmx_set_cr0 refers to efer set above.
8169          */
8170         kvm_set_cr0(vcpu, vmcs12->host_cr0);
8171         /*
8172          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8173          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8174          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8175          */
8176         update_exception_bitmap(vcpu);
8177         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8178         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8179
8180         /*
8181          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8182          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8183          */
8184         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8185         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8186
8187         if (nested_cpu_has_ept(vmcs12))
8188                 nested_ept_uninit_mmu_context(vcpu);
8189
8190         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8191         kvm_mmu_reset_context(vcpu);
8192
8193         if (enable_vpid) {
8194                 /*
8195                  * Trivially support vpid by letting L2s share their parent
8196                  * L1's vpid. TODO: move to a more elaborate solution, giving
8197                  * each L2 its own vpid and exposing the vpid feature to L1.
8198                  */
8199                 vmx_flush_tlb(vcpu);
8200         }
8201
8202
8203         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8204         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8205         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8206         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8207         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8208
8209         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8210                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8211         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8212                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8213                         vmcs12->host_ia32_perf_global_ctrl);
8214
8215         /* Set L1 segment info according to Intel SDM
8216             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8217         seg = (struct kvm_segment) {
8218                 .base = 0,
8219                 .limit = 0xFFFFFFFF,
8220                 .selector = vmcs12->host_cs_selector,
8221                 .type = 11,
8222                 .present = 1,
8223                 .s = 1,
8224                 .g = 1
8225         };
8226         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8227                 seg.l = 1;
8228         else
8229                 seg.db = 1;
8230         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8231         seg = (struct kvm_segment) {
8232                 .base = 0,
8233                 .limit = 0xFFFFFFFF,
8234                 .type = 3,
8235                 .present = 1,
8236                 .s = 1,
8237                 .db = 1,
8238                 .g = 1
8239         };
8240         seg.selector = vmcs12->host_ds_selector;
8241         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8242         seg.selector = vmcs12->host_es_selector;
8243         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8244         seg.selector = vmcs12->host_ss_selector;
8245         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8246         seg.selector = vmcs12->host_fs_selector;
8247         seg.base = vmcs12->host_fs_base;
8248         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8249         seg.selector = vmcs12->host_gs_selector;
8250         seg.base = vmcs12->host_gs_base;
8251         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8252         seg = (struct kvm_segment) {
8253                 .base = vmcs12->host_tr_base,
8254                 .limit = 0x67,
8255                 .selector = vmcs12->host_tr_selector,
8256                 .type = 11,
8257                 .present = 1
8258         };
8259         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8260
8261         kvm_set_dr(vcpu, 7, 0x400);
8262         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8263 }
8264
8265 /*
8266  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8267  * and modify vmcs12 to make it see what it would expect to see there if
8268  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8269  */
8270 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8271 {
8272         struct vcpu_vmx *vmx = to_vmx(vcpu);
8273         int cpu;
8274         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8275
8276         /* trying to cancel vmlaunch/vmresume is a bug */
8277         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8278
8279         leave_guest_mode(vcpu);
8280         prepare_vmcs12(vcpu, vmcs12);
8281
8282         cpu = get_cpu();
8283         vmx->loaded_vmcs = &vmx->vmcs01;
8284         vmx_vcpu_put(vcpu);
8285         vmx_vcpu_load(vcpu, cpu);
8286         vcpu->cpu = cpu;
8287         put_cpu();
8288
8289         vmx_segment_cache_clear(vmx);
8290
8291         /* if no vmcs02 cache requested, remove the one we used */
8292         if (VMCS02_POOL_SIZE == 0)
8293                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8294
8295         load_vmcs12_host_state(vcpu, vmcs12);
8296
8297         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8298         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8299
8300         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8301         vmx->host_rsp = 0;
8302
8303         /* Unpin physical memory we referred to in vmcs02 */
8304         if (vmx->nested.apic_access_page) {
8305                 nested_release_page(vmx->nested.apic_access_page);
8306                 vmx->nested.apic_access_page = 0;
8307         }
8308
8309         /*
8310          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8311          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8312          * success or failure flag accordingly.
8313          */
8314         if (unlikely(vmx->fail)) {
8315                 vmx->fail = 0;
8316                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8317         } else
8318                 nested_vmx_succeed(vcpu);
8319         if (enable_shadow_vmcs)
8320                 vmx->nested.sync_shadow_vmcs = true;
8321 }
8322
8323 /*
8324  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8325  * 23.7 "VM-entry failures during or after loading guest state" (this also
8326  * lists the acceptable exit-reason and exit-qualification parameters).
8327  * It should only be called before L2 actually succeeded to run, and when
8328  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8329  */
8330 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8331                         struct vmcs12 *vmcs12,
8332                         u32 reason, unsigned long qualification)
8333 {
8334         load_vmcs12_host_state(vcpu, vmcs12);
8335         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8336         vmcs12->exit_qualification = qualification;
8337         nested_vmx_succeed(vcpu);
8338         if (enable_shadow_vmcs)
8339                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8340 }
8341
8342 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8343                                struct x86_instruction_info *info,
8344                                enum x86_intercept_stage stage)
8345 {
8346         return X86EMUL_CONTINUE;
8347 }
8348
8349 static struct kvm_x86_ops vmx_x86_ops = {
8350         .cpu_has_kvm_support = cpu_has_kvm_support,
8351         .disabled_by_bios = vmx_disabled_by_bios,
8352         .hardware_setup = hardware_setup,
8353         .hardware_unsetup = hardware_unsetup,
8354         .check_processor_compatibility = vmx_check_processor_compat,
8355         .hardware_enable = hardware_enable,
8356         .hardware_disable = hardware_disable,
8357         .cpu_has_accelerated_tpr = report_flexpriority,
8358
8359         .vcpu_create = vmx_create_vcpu,
8360         .vcpu_free = vmx_free_vcpu,
8361         .vcpu_reset = vmx_vcpu_reset,
8362
8363         .prepare_guest_switch = vmx_save_host_state,
8364         .vcpu_load = vmx_vcpu_load,
8365         .vcpu_put = vmx_vcpu_put,
8366
8367         .update_db_bp_intercept = update_exception_bitmap,
8368         .get_msr = vmx_get_msr,
8369         .set_msr = vmx_set_msr,
8370         .get_segment_base = vmx_get_segment_base,
8371         .get_segment = vmx_get_segment,
8372         .set_segment = vmx_set_segment,
8373         .get_cpl = vmx_get_cpl,
8374         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8375         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8376         .decache_cr3 = vmx_decache_cr3,
8377         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8378         .set_cr0 = vmx_set_cr0,
8379         .set_cr3 = vmx_set_cr3,
8380         .set_cr4 = vmx_set_cr4,
8381         .set_efer = vmx_set_efer,
8382         .get_idt = vmx_get_idt,
8383         .set_idt = vmx_set_idt,
8384         .get_gdt = vmx_get_gdt,
8385         .set_gdt = vmx_set_gdt,
8386         .set_dr7 = vmx_set_dr7,
8387         .cache_reg = vmx_cache_reg,
8388         .get_rflags = vmx_get_rflags,
8389         .set_rflags = vmx_set_rflags,
8390         .fpu_activate = vmx_fpu_activate,
8391         .fpu_deactivate = vmx_fpu_deactivate,
8392
8393         .tlb_flush = vmx_flush_tlb,
8394
8395         .run = vmx_vcpu_run,
8396         .handle_exit = vmx_handle_exit,
8397         .skip_emulated_instruction = skip_emulated_instruction,
8398         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8399         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8400         .patch_hypercall = vmx_patch_hypercall,
8401         .set_irq = vmx_inject_irq,
8402         .set_nmi = vmx_inject_nmi,
8403         .queue_exception = vmx_queue_exception,
8404         .cancel_injection = vmx_cancel_injection,
8405         .interrupt_allowed = vmx_interrupt_allowed,
8406         .nmi_allowed = vmx_nmi_allowed,
8407         .get_nmi_mask = vmx_get_nmi_mask,
8408         .set_nmi_mask = vmx_set_nmi_mask,
8409         .enable_nmi_window = enable_nmi_window,
8410         .enable_irq_window = enable_irq_window,
8411         .update_cr8_intercept = update_cr8_intercept,
8412         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8413         .vm_has_apicv = vmx_vm_has_apicv,
8414         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8415         .hwapic_irr_update = vmx_hwapic_irr_update,
8416         .hwapic_isr_update = vmx_hwapic_isr_update,
8417         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8418         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8419
8420         .set_tss_addr = vmx_set_tss_addr,
8421         .get_tdp_level = get_ept_level,
8422         .get_mt_mask = vmx_get_mt_mask,
8423
8424         .get_exit_info = vmx_get_exit_info,
8425
8426         .get_lpage_level = vmx_get_lpage_level,
8427
8428         .cpuid_update = vmx_cpuid_update,
8429
8430         .rdtscp_supported = vmx_rdtscp_supported,
8431         .invpcid_supported = vmx_invpcid_supported,
8432
8433         .set_supported_cpuid = vmx_set_supported_cpuid,
8434
8435         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8436
8437         .set_tsc_khz = vmx_set_tsc_khz,
8438         .read_tsc_offset = vmx_read_tsc_offset,
8439         .write_tsc_offset = vmx_write_tsc_offset,
8440         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8441         .compute_tsc_offset = vmx_compute_tsc_offset,
8442         .read_l1_tsc = vmx_read_l1_tsc,
8443
8444         .set_tdp_cr3 = vmx_set_cr3,
8445
8446         .check_intercept = vmx_check_intercept,
8447         .handle_external_intr = vmx_handle_external_intr,
8448 };
8449
8450 static int __init vmx_init(void)
8451 {
8452         int r, i, msr;
8453
8454         rdmsrl_safe(MSR_EFER, &host_efer);
8455
8456         for (i = 0; i < NR_VMX_MSR; ++i)
8457                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8458
8459         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8460         if (!vmx_io_bitmap_a)
8461                 return -ENOMEM;
8462
8463         r = -ENOMEM;
8464
8465         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8466         if (!vmx_io_bitmap_b)
8467                 goto out;
8468
8469         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8470         if (!vmx_msr_bitmap_legacy)
8471                 goto out1;
8472
8473         vmx_msr_bitmap_legacy_x2apic =
8474                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8475         if (!vmx_msr_bitmap_legacy_x2apic)
8476                 goto out2;
8477
8478         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8479         if (!vmx_msr_bitmap_longmode)
8480                 goto out3;
8481
8482         vmx_msr_bitmap_longmode_x2apic =
8483                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8484         if (!vmx_msr_bitmap_longmode_x2apic)
8485                 goto out4;
8486         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8487         if (!vmx_vmread_bitmap)
8488                 goto out5;
8489
8490         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8491         if (!vmx_vmwrite_bitmap)
8492                 goto out6;
8493
8494         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8495         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8496         /* shadowed read/write fields */
8497         for (i = 0; i < max_shadow_read_write_fields; i++) {
8498                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8499                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8500         }
8501         /* shadowed read only fields */
8502         for (i = 0; i < max_shadow_read_only_fields; i++)
8503                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8504
8505         /*
8506          * Allow direct access to the PC debug port (it is often used for I/O
8507          * delays, but the vmexits simply slow things down).
8508          */
8509         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8510         clear_bit(0x80, vmx_io_bitmap_a);
8511
8512         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8513
8514         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8515         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8516
8517         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8518
8519         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8520                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8521         if (r)
8522                 goto out7;
8523
8524 #ifdef CONFIG_KEXEC
8525         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8526                            crash_vmclear_local_loaded_vmcss);
8527 #endif
8528
8529         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8530         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8531         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8532         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8533         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8534         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8535         memcpy(vmx_msr_bitmap_legacy_x2apic,
8536                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8537         memcpy(vmx_msr_bitmap_longmode_x2apic,
8538                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8539
8540         if (enable_apicv) {
8541                 for (msr = 0x800; msr <= 0x8ff; msr++)
8542                         vmx_disable_intercept_msr_read_x2apic(msr);
8543
8544                 /* According SDM, in x2apic mode, the whole id reg is used.
8545                  * But in KVM, it only use the highest eight bits. Need to
8546                  * intercept it */
8547                 vmx_enable_intercept_msr_read_x2apic(0x802);
8548                 /* TMCCT */
8549                 vmx_enable_intercept_msr_read_x2apic(0x839);
8550                 /* TPR */
8551                 vmx_disable_intercept_msr_write_x2apic(0x808);
8552                 /* EOI */
8553                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8554                 /* SELF-IPI */
8555                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8556         }
8557
8558         if (enable_ept) {
8559                 kvm_mmu_set_mask_ptes(0ull,
8560                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8561                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8562                         0ull, VMX_EPT_EXECUTABLE_MASK);
8563                 ept_set_mmio_spte_mask();
8564                 kvm_enable_tdp();
8565         } else
8566                 kvm_disable_tdp();
8567
8568         return 0;
8569
8570 out7:
8571         free_page((unsigned long)vmx_vmwrite_bitmap);
8572 out6:
8573         free_page((unsigned long)vmx_vmread_bitmap);
8574 out5:
8575         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8576 out4:
8577         free_page((unsigned long)vmx_msr_bitmap_longmode);
8578 out3:
8579         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8580 out2:
8581         free_page((unsigned long)vmx_msr_bitmap_legacy);
8582 out1:
8583         free_page((unsigned long)vmx_io_bitmap_b);
8584 out:
8585         free_page((unsigned long)vmx_io_bitmap_a);
8586         return r;
8587 }
8588
8589 static void __exit vmx_exit(void)
8590 {
8591         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8592         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8593         free_page((unsigned long)vmx_msr_bitmap_legacy);
8594         free_page((unsigned long)vmx_msr_bitmap_longmode);
8595         free_page((unsigned long)vmx_io_bitmap_b);
8596         free_page((unsigned long)vmx_io_bitmap_a);
8597         free_page((unsigned long)vmx_vmwrite_bitmap);
8598         free_page((unsigned long)vmx_vmread_bitmap);
8599
8600 #ifdef CONFIG_KEXEC
8601         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8602         synchronize_rcu();
8603 #endif
8604
8605         kvm_exit();
8606 }
8607
8608 module_init(vmx_init)
8609 module_exit(vmx_exit)