Pileus Git - ~andy/linux/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376         u64 msr_ia32_feature_control;
 377 };
 378
 379 #define POSTED_INTR_ON  0
 380 /* Posted-Interrupt Descriptor */
 381 struct pi_desc {
 382         u32 pir[8];     /* Posted interrupt requested */
 383         u32 control;    /* bit 0 of control is outstanding notification bit */
 384         u32 rsvd[7];
 385 } __aligned(64);
 386
 387 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 388 {
 389         return test_and_set_bit(POSTED_INTR_ON,
 390                         (unsigned long *)&pi_desc->control);
 391 }
 392
 393 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 394 {
 395         return test_and_clear_bit(POSTED_INTR_ON,
 396                         (unsigned long *)&pi_desc->control);
 397 }
 398
 399 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 400 {
 401         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 402 }
 403
 404 struct vcpu_vmx {
 405         struct kvm_vcpu       vcpu;
 406         unsigned long         host_rsp;
 407         u8                    fail;
 408         u8                    cpl;
 409         bool                  nmi_known_unmasked;
 410         u32                   exit_intr_info;
 411         u32                   idt_vectoring_info;
 412         ulong                 rflags;
 413         struct shared_msr_entry *guest_msrs;
 414         int                   nmsrs;
 415         int                   save_nmsrs;
 416         unsigned long         host_idt_base;
 417 #ifdef CONFIG_X86_64
 418         u64                   msr_host_kernel_gs_base;
 419         u64                   msr_guest_kernel_gs_base;
 420 #endif
 421         /*
 422          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 423          * non-nested (L1) guest, it always points to vmcs01. For a nested
 424          * guest (L2), it points to a different VMCS.
 425          */
 426         struct loaded_vmcs    vmcs01;
 427         struct loaded_vmcs   *loaded_vmcs;
 428         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 429         struct msr_autoload {
 430                 unsigned nr;
 431                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 432                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 433         } msr_autoload;
 434         struct {
 435                 int           loaded;
 436                 u16           fs_sel, gs_sel, ldt_sel;
 437 #ifdef CONFIG_X86_64
 438                 u16           ds_sel, es_sel;
 439 #endif
 440                 int           gs_ldt_reload_needed;
 441                 int           fs_reload_needed;
 442         } host_state;
 443         struct {
 444                 int vm86_active;
 445                 ulong save_rflags;
 446                 struct kvm_segment segs[8];
 447         } rmode;
 448         struct {
 449                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 450                 struct kvm_save_segment {
 451                         u16 selector;
 452                         unsigned long base;
 453                         u32 limit;
 454                         u32 ar;
 455                 } seg[8];
 456         } segment_cache;
 457         int vpid;
 458         bool emulation_required;
 459
 460         /* Support for vnmi-less CPUs */
 461         int soft_vnmi_blocked;
 462         ktime_t entry_time;
 463         s64 vnmi_blocked_time;
 464         u32 exit_reason;
 465
 466         bool rdtscp_enabled;
 467
 468         /* Posted interrupt descriptor */
 469         struct pi_desc pi_desc;
 470
 471         /* Support for a guest hypervisor (nested VMX) */
 472         struct nested_vmx nested;
 473 };
 474
 475 enum segment_cache_field {
 476         SEG_FIELD_SEL = 0,
 477         SEG_FIELD_BASE = 1,
 478         SEG_FIELD_LIMIT = 2,
 479         SEG_FIELD_AR = 3,
 480
 481         SEG_FIELD_NR = 4
 482 };
 483
 484 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 485 {
 486         return container_of(vcpu, struct vcpu_vmx, vcpu);
 487 }
 488
 489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 490 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 491 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 492                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 493
 494
 495 static const unsigned long shadow_read_only_fields[] = {
 496         /*
 497          * We do NOT shadow fields that are modified when L0
 498          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 499          * VMXON...) executed by L1.
 500          * For example, VM_INSTRUCTION_ERROR is read
 501          * by L1 if a vmx instruction fails (part of the error path).
 502          * Note the code assumes this logic. If for some reason
 503          * we start shadowing these fields then we need to
 504          * force a shadow sync when L0 emulates vmx instructions
 505          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 506          * by nested_vmx_failValid)
 507          */
 508         VM_EXIT_REASON,
 509         VM_EXIT_INTR_INFO,
 510         VM_EXIT_INSTRUCTION_LEN,
 511         IDT_VECTORING_INFO_FIELD,
 512         IDT_VECTORING_ERROR_CODE,
 513         VM_EXIT_INTR_ERROR_CODE,
 514         EXIT_QUALIFICATION,
 515         GUEST_LINEAR_ADDRESS,
 516         GUEST_PHYSICAL_ADDRESS
 517 };
 518 static const int max_shadow_read_only_fields =
 519         ARRAY_SIZE(shadow_read_only_fields);
 520
 521 static const unsigned long shadow_read_write_fields[] = {
 522         GUEST_RIP,
 523         GUEST_RSP,
 524         GUEST_CR0,
 525         GUEST_CR3,
 526         GUEST_CR4,
 527         GUEST_INTERRUPTIBILITY_INFO,
 528         GUEST_RFLAGS,
 529         GUEST_CS_SELECTOR,
 530         GUEST_CS_AR_BYTES,
 531         GUEST_CS_LIMIT,
 532         GUEST_CS_BASE,
 533         GUEST_ES_BASE,
 534         CR0_GUEST_HOST_MASK,
 535         CR0_READ_SHADOW,
 536         CR4_READ_SHADOW,
 537         TSC_OFFSET,
 538         EXCEPTION_BITMAP,
 539         CPU_BASED_VM_EXEC_CONTROL,
 540         VM_ENTRY_EXCEPTION_ERROR_CODE,
 541         VM_ENTRY_INTR_INFO_FIELD,
 542         VM_ENTRY_INSTRUCTION_LEN,
 543         VM_ENTRY_EXCEPTION_ERROR_CODE,
 544         HOST_FS_BASE,
 545         HOST_GS_BASE,
 546         HOST_FS_SELECTOR,
 547         HOST_GS_SELECTOR
 548 };
 549 static const int max_shadow_read_write_fields =
 550         ARRAY_SIZE(shadow_read_write_fields);
 551
 552 static const unsigned short vmcs_field_to_offset_table[] = {
 553         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 554         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 555         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 556         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 557         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 558         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 559         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 560         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 561         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 562         FIELD(HOST_ES_SELECTOR, host_es_selector),
 563         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 564         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 565         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 566         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 567         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 568         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 569         FIELD64(IO_BITMAP_A, io_bitmap_a),
 570         FIELD64(IO_BITMAP_B, io_bitmap_b),
 571         FIELD64(MSR_BITMAP, msr_bitmap),
 572         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 573         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 574         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 575         FIELD64(TSC_OFFSET, tsc_offset),
 576         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 577         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 578         FIELD64(EPT_POINTER, ept_pointer),
 579         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 580         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 581         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 582         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 583         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 584         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 585         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 586         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 587         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 588         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 589         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 590         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 591         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 592         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 593         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 594         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 595         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 596         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 597         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 598         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 599         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 600         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 601         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 602         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 603         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 604         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 605         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 606         FIELD(TPR_THRESHOLD, tpr_threshold),
 607         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 608         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 609         FIELD(VM_EXIT_REASON, vm_exit_reason),
 610         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 611         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 612         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 613         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 614         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 615         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 616         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 617         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 618         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 619         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 620         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 621         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 622         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 623         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 624         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 625         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 626         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 627         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 628         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 629         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 630         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 631         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 632         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 633         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 634         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 635         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 636         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 637         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 638         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 639         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 640         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 641         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 642         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 643         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 644         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 645         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 646         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 647         FIELD(EXIT_QUALIFICATION, exit_qualification),
 648         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 649         FIELD(GUEST_CR0, guest_cr0),
 650         FIELD(GUEST_CR3, guest_cr3),
 651         FIELD(GUEST_CR4, guest_cr4),
 652         FIELD(GUEST_ES_BASE, guest_es_base),
 653         FIELD(GUEST_CS_BASE, guest_cs_base),
 654         FIELD(GUEST_SS_BASE, guest_ss_base),
 655         FIELD(GUEST_DS_BASE, guest_ds_base),
 656         FIELD(GUEST_FS_BASE, guest_fs_base),
 657         FIELD(GUEST_GS_BASE, guest_gs_base),
 658         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 659         FIELD(GUEST_TR_BASE, guest_tr_base),
 660         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 661         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 662         FIELD(GUEST_DR7, guest_dr7),
 663         FIELD(GUEST_RSP, guest_rsp),
 664         FIELD(GUEST_RIP, guest_rip),
 665         FIELD(GUEST_RFLAGS, guest_rflags),
 666         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 667         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 668         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 669         FIELD(HOST_CR0, host_cr0),
 670         FIELD(HOST_CR3, host_cr3),
 671         FIELD(HOST_CR4, host_cr4),
 672         FIELD(HOST_FS_BASE, host_fs_base),
 673         FIELD(HOST_GS_BASE, host_gs_base),
 674         FIELD(HOST_TR_BASE, host_tr_base),
 675         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 676         FIELD(HOST_IDTR_BASE, host_idtr_base),
 677         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 678         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 679         FIELD(HOST_RSP, host_rsp),
 680         FIELD(HOST_RIP, host_rip),
 681 };
 682 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 683
 684 static inline short vmcs_field_to_offset(unsigned long field)
 685 {
 686         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 687                 return -1;
 688         return vmcs_field_to_offset_table[field];
 689 }
 690
 691 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 692 {
 693         return to_vmx(vcpu)->nested.current_vmcs12;
 694 }
 695
 696 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 697 {
 698         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 699         if (is_error_page(page))
 700                 return NULL;
 701
 702         return page;
 703 }
 704
 705 static void nested_release_page(struct page *page)
 706 {
 707         kvm_release_page_dirty(page);
 708 }
 709
 710 static void nested_release_page_clean(struct page *page)
 711 {
 712         kvm_release_page_clean(page);
 713 }
 714
 715 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 716 static u64 construct_eptp(unsigned long root_hpa);
 717 static void kvm_cpu_vmxon(u64 addr);
 718 static void kvm_cpu_vmxoff(void);
 719 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 720 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 721                             struct kvm_segment *var, int seg);
 722 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 723                             struct kvm_segment *var, int seg);
 724 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 725 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 726 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 727 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 728 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 729
 730 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 731 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 732 /*
 733  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 734  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 735  */
 736 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 737 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 738
 739 static unsigned long *vmx_io_bitmap_a;
 740 static unsigned long *vmx_io_bitmap_b;
 741 static unsigned long *vmx_msr_bitmap_legacy;
 742 static unsigned long *vmx_msr_bitmap_longmode;
 743 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 744 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 745 static unsigned long *vmx_vmread_bitmap;
 746 static unsigned long *vmx_vmwrite_bitmap;
 747
 748 static bool cpu_has_load_ia32_efer;
 749 static bool cpu_has_load_perf_global_ctrl;
 750
 751 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 752 static DEFINE_SPINLOCK(vmx_vpid_lock);
 753
 754 static struct vmcs_config {
 755         int size;
 756         int order;
 757         u32 revision_id;
 758         u32 pin_based_exec_ctrl;
 759         u32 cpu_based_exec_ctrl;
 760         u32 cpu_based_2nd_exec_ctrl;
 761         u32 vmexit_ctrl;
 762         u32 vmentry_ctrl;
 763 } vmcs_config;
 764
 765 static struct vmx_capability {
 766         u32 ept;
 767         u32 vpid;
 768 } vmx_capability;
 769
 770 #define VMX_SEGMENT_FIELD(seg)                                  \
 771         [VCPU_SREG_##seg] = {                                   \
 772                 .selector = GUEST_##seg##_SELECTOR,             \
 773                 .base = GUEST_##seg##_BASE,                     \
 774                 .limit = GUEST_##seg##_LIMIT,                   \
 775                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 776         }
 777
 778 static const struct kvm_vmx_segment_field {
 779         unsigned selector;
 780         unsigned base;
 781         unsigned limit;
 782         unsigned ar_bytes;
 783 } kvm_vmx_segment_fields[] = {
 784         VMX_SEGMENT_FIELD(CS),
 785         VMX_SEGMENT_FIELD(DS),
 786         VMX_SEGMENT_FIELD(ES),
 787         VMX_SEGMENT_FIELD(FS),
 788         VMX_SEGMENT_FIELD(GS),
 789         VMX_SEGMENT_FIELD(SS),
 790         VMX_SEGMENT_FIELD(TR),
 791         VMX_SEGMENT_FIELD(LDTR),
 792 };
 793
 794 static u64 host_efer;
 795
 796 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 797
 798 /*
 799  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 800  * away by decrementing the array size.
 801  */
 802 static const u32 vmx_msr_index[] = {
 803 #ifdef CONFIG_X86_64
 804         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 805 #endif
 806         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 807 };
 808 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 809
 810 static inline bool is_page_fault(u32 intr_info)
 811 {
 812         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 813                              INTR_INFO_VALID_MASK)) ==
 814                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 815 }
 816
 817 static inline bool is_no_device(u32 intr_info)
 818 {
 819         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 820                              INTR_INFO_VALID_MASK)) ==
 821                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 822 }
 823
 824 static inline bool is_invalid_opcode(u32 intr_info)
 825 {
 826         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 827                              INTR_INFO_VALID_MASK)) ==
 828                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 829 }
 830
 831 static inline bool is_external_interrupt(u32 intr_info)
 832 {
 833         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 834                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 835 }
 836
 837 static inline bool is_machine_check(u32 intr_info)
 838 {
 839         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 840                              INTR_INFO_VALID_MASK)) ==
 841                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 842 }
 843
 844 static inline bool cpu_has_vmx_msr_bitmap(void)
 845 {
 846         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 847 }
 848
 849 static inline bool cpu_has_vmx_tpr_shadow(void)
 850 {
 851         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 852 }
 853
 854 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 855 {
 856         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 857 }
 858
 859 static inline bool cpu_has_secondary_exec_ctrls(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl &
 862                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 863 }
 864
 865 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 866 {
 867         return vmcs_config.cpu_based_2nd_exec_ctrl &
 868                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 869 }
 870
 871 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 872 {
 873         return vmcs_config.cpu_based_2nd_exec_ctrl &
 874                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 875 }
 876
 877 static inline bool cpu_has_vmx_apic_register_virt(void)
 878 {
 879         return vmcs_config.cpu_based_2nd_exec_ctrl &
 880                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 881 }
 882
 883 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 884 {
 885         return vmcs_config.cpu_based_2nd_exec_ctrl &
 886                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 887 }
 888
 889 static inline bool cpu_has_vmx_posted_intr(void)
 890 {
 891         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 892 }
 893
 894 static inline bool cpu_has_vmx_apicv(void)
 895 {
 896         return cpu_has_vmx_apic_register_virt() &&
 897                 cpu_has_vmx_virtual_intr_delivery() &&
 898                 cpu_has_vmx_posted_intr();
 899 }
 900
 901 static inline bool cpu_has_vmx_flexpriority(void)
 902 {
 903         return cpu_has_vmx_tpr_shadow() &&
 904                 cpu_has_vmx_virtualize_apic_accesses();
 905 }
 906
 907 static inline bool cpu_has_vmx_ept_execute_only(void)
 908 {
 909         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 910 }
 911
 912 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 913 {
 914         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 915 }
 916
 917 static inline bool cpu_has_vmx_eptp_writeback(void)
 918 {
 919         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_2m_page(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_ept_1g_page(void)
 928 {
 929         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_ept_4levels(void)
 933 {
 934         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_ad_bits(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_AD_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_invept_context(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_invept_global(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_invvpid_single(void)
 953 {
 954         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invvpid_global(void)
 958 {
 959         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_ept(void)
 963 {
 964         return vmcs_config.cpu_based_2nd_exec_ctrl &
 965                 SECONDARY_EXEC_ENABLE_EPT;
 966 }
 967
 968 static inline bool cpu_has_vmx_unrestricted_guest(void)
 969 {
 970         return vmcs_config.cpu_based_2nd_exec_ctrl &
 971                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 972 }
 973
 974 static inline bool cpu_has_vmx_ple(void)
 975 {
 976         return vmcs_config.cpu_based_2nd_exec_ctrl &
 977                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 978 }
 979
 980 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 981 {
 982         return flexpriority_enabled && irqchip_in_kernel(kvm);
 983 }
 984
 985 static inline bool cpu_has_vmx_vpid(void)
 986 {
 987         return vmcs_config.cpu_based_2nd_exec_ctrl &
 988                 SECONDARY_EXEC_ENABLE_VPID;
 989 }
 990
 991 static inline bool cpu_has_vmx_rdtscp(void)
 992 {
 993         return vmcs_config.cpu_based_2nd_exec_ctrl &
 994                 SECONDARY_EXEC_RDTSCP;
 995 }
 996
 997 static inline bool cpu_has_vmx_invpcid(void)
 998 {
 999         return vmcs_config.cpu_based_2nd_exec_ctrl &
1000                 SECONDARY_EXEC_ENABLE_INVPCID;
1001 }
1002
1003 static inline bool cpu_has_virtual_nmis(void)
1004 {
1005         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006 }
1007
1008 static inline bool cpu_has_vmx_wbinvd_exit(void)
1009 {
1010         return vmcs_config.cpu_based_2nd_exec_ctrl &
1011                 SECONDARY_EXEC_WBINVD_EXITING;
1012 }
1013
1014 static inline bool cpu_has_vmx_shadow_vmcs(void)
1015 {
1016         u64 vmx_msr;
1017         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018         /* check if the cpu supports writing r/o exit information fields */
1019         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020                 return false;
1021
1022         return vmcs_config.cpu_based_2nd_exec_ctrl &
1023                 SECONDARY_EXEC_SHADOW_VMCS;
1024 }
1025
1026 static inline bool report_flexpriority(void)
1027 {
1028         return flexpriority_enabled;
1029 }
1030
1031 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032 {
1033         return vmcs12->cpu_based_vm_exec_control & bit;
1034 }
1035
1036 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037 {
1038         return (vmcs12->cpu_based_vm_exec_control &
1039                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040                 (vmcs12->secondary_vm_exec_control & bit);
1041 }
1042
1043 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1044 {
1045         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046 }
1047
1048 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1049 {
1050         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1051 }
1052
1053 static inline bool is_exception(u32 intr_info)
1054 {
1055         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1057 }
1058
1059 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1060 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061                         struct vmcs12 *vmcs12,
1062                         u32 reason, unsigned long qualification);
1063
1064 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1065 {
1066         int i;
1067
1068         for (i = 0; i < vmx->nmsrs; ++i)
1069                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1070                         return i;
1071         return -1;
1072 }
1073
1074 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1075 {
1076     struct {
1077         u64 vpid : 16;
1078         u64 rsvd : 48;
1079         u64 gva;
1080     } operand = { vpid, 0, gva };
1081
1082     asm volatile (__ex(ASM_VMX_INVVPID)
1083                   /* CF==1 or ZF==1 --> rc = -1 */
1084                   "; ja 1f ; ud2 ; 1:"
1085                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1086 }
1087
1088 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1089 {
1090         struct {
1091                 u64 eptp, gpa;
1092         } operand = {eptp, gpa};
1093
1094         asm volatile (__ex(ASM_VMX_INVEPT)
1095                         /* CF==1 or ZF==1 --> rc = -1 */
1096                         "; ja 1f ; ud2 ; 1:\n"
1097                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1098 }
1099
1100 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1101 {
1102         int i;
1103
1104         i = __find_msr_index(vmx, msr);
1105         if (i >= 0)
1106                 return &vmx->guest_msrs[i];
1107         return NULL;
1108 }
1109
1110 static void vmcs_clear(struct vmcs *vmcs)
1111 {
1112         u64 phys_addr = __pa(vmcs);
1113         u8 error;
1114
1115         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1116                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1117                       : "cc", "memory");
1118         if (error)
1119                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1120                        vmcs, phys_addr);
1121 }
1122
1123 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1124 {
1125         vmcs_clear(loaded_vmcs->vmcs);
1126         loaded_vmcs->cpu = -1;
1127         loaded_vmcs->launched = 0;
1128 }
1129
1130 static void vmcs_load(struct vmcs *vmcs)
1131 {
1132         u64 phys_addr = __pa(vmcs);
1133         u8 error;
1134
1135         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1136                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1137                         : "cc", "memory");
1138         if (error)
1139                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1140                        vmcs, phys_addr);
1141 }
1142
1143 #ifdef CONFIG_KEXEC
1144 /*
1145  * This bitmap is used to indicate whether the vmclear
1146  * operation is enabled on all cpus. All disabled by
1147  * default.
1148  */
1149 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1150
1151 static inline void crash_enable_local_vmclear(int cpu)
1152 {
1153         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154 }
1155
1156 static inline void crash_disable_local_vmclear(int cpu)
1157 {
1158         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159 }
1160
1161 static inline int crash_local_vmclear_enabled(int cpu)
1162 {
1163         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164 }
1165
1166 static void crash_vmclear_local_loaded_vmcss(void)
1167 {
1168         int cpu = raw_smp_processor_id();
1169         struct loaded_vmcs *v;
1170
1171         if (!crash_local_vmclear_enabled(cpu))
1172                 return;
1173
1174         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175                             loaded_vmcss_on_cpu_link)
1176                 vmcs_clear(v->vmcs);
1177 }
1178 #else
1179 static inline void crash_enable_local_vmclear(int cpu) { }
1180 static inline void crash_disable_local_vmclear(int cpu) { }
1181 #endif /* CONFIG_KEXEC */
1182
1183 static void __loaded_vmcs_clear(void *arg)
1184 {
1185         struct loaded_vmcs *loaded_vmcs = arg;
1186         int cpu = raw_smp_processor_id();
1187
1188         if (loaded_vmcs->cpu != cpu)
1189                 return; /* vcpu migration can race with cpu offline */
1190         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1191                 per_cpu(current_vmcs, cpu) = NULL;
1192         crash_disable_local_vmclear(cpu);
1193         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1194
1195         /*
1196          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197          * is before setting loaded_vmcs->vcpu to -1 which is done in
1198          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199          * then adds the vmcs into percpu list before it is deleted.
1200          */
1201         smp_wmb();
1202
1203         loaded_vmcs_init(loaded_vmcs);
1204         crash_enable_local_vmclear(cpu);
1205 }
1206
1207 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1208 {
1209         int cpu = loaded_vmcs->cpu;
1210
1211         if (cpu != -1)
1212                 smp_call_function_single(cpu,
1213                          __loaded_vmcs_clear, loaded_vmcs, 1);
1214 }
1215
1216 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1217 {
1218         if (vmx->vpid == 0)
1219                 return;
1220
1221         if (cpu_has_vmx_invvpid_single())
1222                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1223 }
1224
1225 static inline void vpid_sync_vcpu_global(void)
1226 {
1227         if (cpu_has_vmx_invvpid_global())
1228                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1229 }
1230
1231 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1232 {
1233         if (cpu_has_vmx_invvpid_single())
1234                 vpid_sync_vcpu_single(vmx);
1235         else
1236                 vpid_sync_vcpu_global();
1237 }
1238
1239 static inline void ept_sync_global(void)
1240 {
1241         if (cpu_has_vmx_invept_global())
1242                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1243 }
1244
1245 static inline void ept_sync_context(u64 eptp)
1246 {
1247         if (enable_ept) {
1248                 if (cpu_has_vmx_invept_context())
1249                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1250                 else
1251                         ept_sync_global();
1252         }
1253 }
1254
1255 static __always_inline unsigned long vmcs_readl(unsigned long field)
1256 {
1257         unsigned long value;
1258
1259         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260                       : "=a"(value) : "d"(field) : "cc");
1261         return value;
1262 }
1263
1264 static __always_inline u16 vmcs_read16(unsigned long field)
1265 {
1266         return vmcs_readl(field);
1267 }
1268
1269 static __always_inline u32 vmcs_read32(unsigned long field)
1270 {
1271         return vmcs_readl(field);
1272 }
1273
1274 static __always_inline u64 vmcs_read64(unsigned long field)
1275 {
1276 #ifdef CONFIG_X86_64
1277         return vmcs_readl(field);
1278 #else
1279         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1280 #endif
1281 }
1282
1283 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1284 {
1285         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1287         dump_stack();
1288 }
1289
1290 static void vmcs_writel(unsigned long field, unsigned long value)
1291 {
1292         u8 error;
1293
1294         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1295                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1296         if (unlikely(error))
1297                 vmwrite_error(field, value);
1298 }
1299
1300 static void vmcs_write16(unsigned long field, u16 value)
1301 {
1302         vmcs_writel(field, value);
1303 }
1304
1305 static void vmcs_write32(unsigned long field, u32 value)
1306 {
1307         vmcs_writel(field, value);
1308 }
1309
1310 static void vmcs_write64(unsigned long field, u64 value)
1311 {
1312         vmcs_writel(field, value);
1313 #ifndef CONFIG_X86_64
1314         asm volatile ("");
1315         vmcs_writel(field+1, value >> 32);
1316 #endif
1317 }
1318
1319 static void vmcs_clear_bits(unsigned long field, u32 mask)
1320 {
1321         vmcs_writel(field, vmcs_readl(field) & ~mask);
1322 }
1323
1324 static void vmcs_set_bits(unsigned long field, u32 mask)
1325 {
1326         vmcs_writel(field, vmcs_readl(field) | mask);
1327 }
1328
1329 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1330 {
1331         vmx->segment_cache.bitmask = 0;
1332 }
1333
1334 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1335                                        unsigned field)
1336 {
1337         bool ret;
1338         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1339
1340         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342                 vmx->segment_cache.bitmask = 0;
1343         }
1344         ret = vmx->segment_cache.bitmask & mask;
1345         vmx->segment_cache.bitmask |= mask;
1346         return ret;
1347 }
1348
1349 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1350 {
1351         u16 *p = &vmx->segment_cache.seg[seg].selector;
1352
1353         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1355         return *p;
1356 }
1357
1358 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1359 {
1360         ulong *p = &vmx->segment_cache.seg[seg].base;
1361
1362         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1364         return *p;
1365 }
1366
1367 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1368 {
1369         u32 *p = &vmx->segment_cache.seg[seg].limit;
1370
1371         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1373         return *p;
1374 }
1375
1376 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1377 {
1378         u32 *p = &vmx->segment_cache.seg[seg].ar;
1379
1380         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1382         return *p;
1383 }
1384
1385 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1386 {
1387         u32 eb;
1388
1389         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391         if ((vcpu->guest_debug &
1392              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394                 eb |= 1u << BP_VECTOR;
1395         if (to_vmx(vcpu)->rmode.vm86_active)
1396                 eb = ~0;
1397         if (enable_ept)
1398                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1399         if (vcpu->fpu_active)
1400                 eb &= ~(1u << NM_VECTOR);
1401
1402         /* When we are running a nested L2 guest and L1 specified for it a
1403          * certain exception bitmap, we must trap the same exceptions and pass
1404          * them to L1. When running L2, we will only handle the exceptions
1405          * specified above if L1 did not want them.
1406          */
1407         if (is_guest_mode(vcpu))
1408                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1409
1410         vmcs_write32(EXCEPTION_BITMAP, eb);
1411 }
1412
1413 static void clear_atomic_switch_msr_special(unsigned long entry,
1414                 unsigned long exit)
1415 {
1416         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1418 }
1419
1420 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1421 {
1422         unsigned i;
1423         struct msr_autoload *m = &vmx->msr_autoload;
1424
1425         switch (msr) {
1426         case MSR_EFER:
1427                 if (cpu_has_load_ia32_efer) {
1428                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429                                         VM_EXIT_LOAD_IA32_EFER);
1430                         return;
1431                 }
1432                 break;
1433         case MSR_CORE_PERF_GLOBAL_CTRL:
1434                 if (cpu_has_load_perf_global_ctrl) {
1435                         clear_atomic_switch_msr_special(
1436                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1438                         return;
1439                 }
1440                 break;
1441         }
1442
1443         for (i = 0; i < m->nr; ++i)
1444                 if (m->guest[i].index == msr)
1445                         break;
1446
1447         if (i == m->nr)
1448                 return;
1449         --m->nr;
1450         m->guest[i] = m->guest[m->nr];
1451         m->host[i] = m->host[m->nr];
1452         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1454 }
1455
1456 static void add_atomic_switch_msr_special(unsigned long entry,
1457                 unsigned long exit, unsigned long guest_val_vmcs,
1458                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1459 {
1460         vmcs_write64(guest_val_vmcs, guest_val);
1461         vmcs_write64(host_val_vmcs, host_val);
1462         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1464 }
1465
1466 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467                                   u64 guest_val, u64 host_val)
1468 {
1469         unsigned i;
1470         struct msr_autoload *m = &vmx->msr_autoload;
1471
1472         switch (msr) {
1473         case MSR_EFER:
1474                 if (cpu_has_load_ia32_efer) {
1475                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476                                         VM_EXIT_LOAD_IA32_EFER,
1477                                         GUEST_IA32_EFER,
1478                                         HOST_IA32_EFER,
1479                                         guest_val, host_val);
1480                         return;
1481                 }
1482                 break;
1483         case MSR_CORE_PERF_GLOBAL_CTRL:
1484                 if (cpu_has_load_perf_global_ctrl) {
1485                         add_atomic_switch_msr_special(
1486                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1489                                         HOST_IA32_PERF_GLOBAL_CTRL,
1490                                         guest_val, host_val);
1491                         return;
1492                 }
1493                 break;
1494         }
1495
1496         for (i = 0; i < m->nr; ++i)
1497                 if (m->guest[i].index == msr)
1498                         break;
1499
1500         if (i == NR_AUTOLOAD_MSRS) {
1501                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1502                                 "Can't add msr %x\n", msr);
1503                 return;
1504         } else if (i == m->nr) {
1505                 ++m->nr;
1506                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1508         }
1509
1510         m->guest[i].index = msr;
1511         m->guest[i].value = guest_val;
1512         m->host[i].index = msr;
1513         m->host[i].value = host_val;
1514 }
1515
1516 static void reload_tss(void)
1517 {
1518         /*
1519          * VT restores TR but not its size.  Useless.
1520          */
1521         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1522         struct desc_struct *descs;
1523
1524         descs = (void *)gdt->address;
1525         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1526         load_TR_desc();
1527 }
1528
1529 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1530 {
1531         u64 guest_efer;
1532         u64 ignore_bits;
1533
1534         guest_efer = vmx->vcpu.arch.efer;
1535
1536         /*
1537          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1538          * outside long mode
1539          */
1540         ignore_bits = EFER_NX | EFER_SCE;
1541 #ifdef CONFIG_X86_64
1542         ignore_bits |= EFER_LMA | EFER_LME;
1543         /* SCE is meaningful only in long mode on Intel */
1544         if (guest_efer & EFER_LMA)
1545                 ignore_bits &= ~(u64)EFER_SCE;
1546 #endif
1547         guest_efer &= ~ignore_bits;
1548         guest_efer |= host_efer & ignore_bits;
1549         vmx->guest_msrs[efer_offset].data = guest_efer;
1550         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1551
1552         clear_atomic_switch_msr(vmx, MSR_EFER);
1553         /* On ept, can't emulate nx, and must switch nx atomically */
1554         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555                 guest_efer = vmx->vcpu.arch.efer;
1556                 if (!(guest_efer & EFER_LMA))
1557                         guest_efer &= ~EFER_LME;
1558                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1559                 return false;
1560         }
1561
1562         return true;
1563 }
1564
1565 static unsigned long segment_base(u16 selector)
1566 {
1567         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1568         struct desc_struct *d;
1569         unsigned long table_base;
1570         unsigned long v;
1571
1572         if (!(selector & ~3))
1573                 return 0;
1574
1575         table_base = gdt->address;
1576
1577         if (selector & 4) {           /* from ldt */
1578                 u16 ldt_selector = kvm_read_ldt();
1579
1580                 if (!(ldt_selector & ~3))
1581                         return 0;
1582
1583                 table_base = segment_base(ldt_selector);
1584         }
1585         d = (struct desc_struct *)(table_base + (selector & ~7));
1586         v = get_desc_base(d);
1587 #ifdef CONFIG_X86_64
1588        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1590 #endif
1591         return v;
1592 }
1593
1594 static inline unsigned long kvm_read_tr_base(void)
1595 {
1596         u16 tr;
1597         asm("str %0" : "=g"(tr));
1598         return segment_base(tr);
1599 }
1600
1601 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1602 {
1603         struct vcpu_vmx *vmx = to_vmx(vcpu);
1604         int i;
1605
1606         if (vmx->host_state.loaded)
1607                 return;
1608
1609         vmx->host_state.loaded = 1;
1610         /*
1611          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1612          * allow segment selectors with cpl > 0 or ti == 1.
1613          */
1614         vmx->host_state.ldt_sel = kvm_read_ldt();
1615         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1616         savesegment(fs, vmx->host_state.fs_sel);
1617         if (!(vmx->host_state.fs_sel & 7)) {
1618                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1619                 vmx->host_state.fs_reload_needed = 0;
1620         } else {
1621                 vmcs_write16(HOST_FS_SELECTOR, 0);
1622                 vmx->host_state.fs_reload_needed = 1;
1623         }
1624         savesegment(gs, vmx->host_state.gs_sel);
1625         if (!(vmx->host_state.gs_sel & 7))
1626                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1627         else {
1628                 vmcs_write16(HOST_GS_SELECTOR, 0);
1629                 vmx->host_state.gs_ldt_reload_needed = 1;
1630         }
1631
1632 #ifdef CONFIG_X86_64
1633         savesegment(ds, vmx->host_state.ds_sel);
1634         savesegment(es, vmx->host_state.es_sel);
1635 #endif
1636
1637 #ifdef CONFIG_X86_64
1638         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1640 #else
1641         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1643 #endif
1644
1645 #ifdef CONFIG_X86_64
1646         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647         if (is_long_mode(&vmx->vcpu))
1648                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1649 #endif
1650         for (i = 0; i < vmx->save_nmsrs; ++i)
1651                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1652                                    vmx->guest_msrs[i].data,
1653                                    vmx->guest_msrs[i].mask);
1654 }
1655
1656 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1657 {
1658         if (!vmx->host_state.loaded)
1659                 return;
1660
1661         ++vmx->vcpu.stat.host_state_reload;
1662         vmx->host_state.loaded = 0;
1663 #ifdef CONFIG_X86_64
1664         if (is_long_mode(&vmx->vcpu))
1665                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1666 #endif
1667         if (vmx->host_state.gs_ldt_reload_needed) {
1668                 kvm_load_ldt(vmx->host_state.ldt_sel);
1669 #ifdef CONFIG_X86_64
1670                 load_gs_index(vmx->host_state.gs_sel);
1671 #else
1672                 loadsegment(gs, vmx->host_state.gs_sel);
1673 #endif
1674         }
1675         if (vmx->host_state.fs_reload_needed)
1676                 loadsegment(fs, vmx->host_state.fs_sel);
1677 #ifdef CONFIG_X86_64
1678         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679                 loadsegment(ds, vmx->host_state.ds_sel);
1680                 loadsegment(es, vmx->host_state.es_sel);
1681         }
1682 #endif
1683         reload_tss();
1684 #ifdef CONFIG_X86_64
1685         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1686 #endif
1687         /*
1688          * If the FPU is not active (through the host task or
1689          * the guest vcpu), then restore the cr0.TS bit.
1690          */
1691         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1692                 stts();
1693         load_gdt(&__get_cpu_var(host_gdt));
1694 }
1695
1696 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1697 {
1698         preempt_disable();
1699         __vmx_load_host_state(vmx);
1700         preempt_enable();
1701 }
1702
1703 /*
1704  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705  * vcpu mutex is already taken.
1706  */
1707 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1708 {
1709         struct vcpu_vmx *vmx = to_vmx(vcpu);
1710         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1711
1712         if (!vmm_exclusive)
1713                 kvm_cpu_vmxon(phys_addr);
1714         else if (vmx->loaded_vmcs->cpu != cpu)
1715                 loaded_vmcs_clear(vmx->loaded_vmcs);
1716
1717         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719                 vmcs_load(vmx->loaded_vmcs->vmcs);
1720         }
1721
1722         if (vmx->loaded_vmcs->cpu != cpu) {
1723                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1724                 unsigned long sysenter_esp;
1725
1726                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1727                 local_irq_disable();
1728                 crash_disable_local_vmclear(cpu);
1729
1730                 /*
1731                  * Read loaded_vmcs->cpu should be before fetching
1732                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733                  * See the comments in __loaded_vmcs_clear().
1734                  */
1735                 smp_rmb();
1736
1737                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1739                 crash_enable_local_vmclear(cpu);
1740                 local_irq_enable();
1741
1742                 /*
1743                  * Linux uses per-cpu TSS and GDT, so set these when switching
1744                  * processors.
1745                  */
1746                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1747                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1748
1749                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1751                 vmx->loaded_vmcs->cpu = cpu;
1752         }
1753 }
1754
1755 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1756 {
1757         __vmx_load_host_state(to_vmx(vcpu));
1758         if (!vmm_exclusive) {
1759                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1760                 vcpu->cpu = -1;
1761                 kvm_cpu_vmxoff();
1762         }
1763 }
1764
1765 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1766 {
1767         ulong cr0;
1768
1769         if (vcpu->fpu_active)
1770                 return;
1771         vcpu->fpu_active = 1;
1772         cr0 = vmcs_readl(GUEST_CR0);
1773         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775         vmcs_writel(GUEST_CR0, cr0);
1776         update_exception_bitmap(vcpu);
1777         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1778         if (is_guest_mode(vcpu))
1779                 vcpu->arch.cr0_guest_owned_bits &=
1780                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1781         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1782 }
1783
1784 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1785
1786 /*
1787  * Return the cr0 value that a nested guest would read. This is a combination
1788  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789  * its hypervisor (cr0_read_shadow).
1790  */
1791 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1792 {
1793         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1795 }
1796 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1797 {
1798         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1800 }
1801
1802 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1803 {
1804         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805          * set this *before* calling this function.
1806          */
1807         vmx_decache_cr0_guest_bits(vcpu);
1808         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1809         update_exception_bitmap(vcpu);
1810         vcpu->arch.cr0_guest_owned_bits = 0;
1811         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1812         if (is_guest_mode(vcpu)) {
1813                 /*
1814                  * L1's specified read shadow might not contain the TS bit,
1815                  * so now that we turned on shadowing of this bit, we need to
1816                  * set this bit of the shadow. Like in nested_vmx_run we need
1817                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818                  * up-to-date here because we just decached cr0.TS (and we'll
1819                  * only update vmcs12->guest_cr0 on nested exit).
1820                  */
1821                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823                         (vcpu->arch.cr0 & X86_CR0_TS);
1824                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1825         } else
1826                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1827 }
1828
1829 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1830 {
1831         unsigned long rflags, save_rflags;
1832
1833         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835                 rflags = vmcs_readl(GUEST_RFLAGS);
1836                 if (to_vmx(vcpu)->rmode.vm86_active) {
1837                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1840                 }
1841                 to_vmx(vcpu)->rflags = rflags;
1842         }
1843         return to_vmx(vcpu)->rflags;
1844 }
1845
1846 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1847 {
1848         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849         to_vmx(vcpu)->rflags = rflags;
1850         if (to_vmx(vcpu)->rmode.vm86_active) {
1851                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1852                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1853         }
1854         vmcs_writel(GUEST_RFLAGS, rflags);
1855 }
1856
1857 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858 {
1859         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860         int ret = 0;
1861
1862         if (interruptibility & GUEST_INTR_STATE_STI)
1863                 ret |= KVM_X86_SHADOW_INT_STI;
1864         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1865                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1866
1867         return ret & mask;
1868 }
1869
1870 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1871 {
1872         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873         u32 interruptibility = interruptibility_old;
1874
1875         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1876
1877         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1878                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1879         else if (mask & KVM_X86_SHADOW_INT_STI)
1880                 interruptibility |= GUEST_INTR_STATE_STI;
1881
1882         if ((interruptibility != interruptibility_old))
1883                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1884 }
1885
1886 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1887 {
1888         unsigned long rip;
1889
1890         rip = kvm_rip_read(vcpu);
1891         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1892         kvm_rip_write(vcpu, rip);
1893
1894         /* skipping an emulated instruction also counts */
1895         vmx_set_interrupt_shadow(vcpu, 0);
1896 }
1897
1898 /*
1899  * KVM wants to inject page-faults which it got to the guest. This function
1900  * checks whether in a nested guest, we need to inject them to L1 or L2.
1901  * This function assumes it is called with the exit reason in vmcs02 being
1902  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1903  * is running).
1904  */
1905 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1906 {
1907         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908
1909         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1910         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1911                 return 0;
1912
1913         nested_vmx_vmexit(vcpu);
1914         return 1;
1915 }
1916
1917 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1918                                 bool has_error_code, u32 error_code,
1919                                 bool reinject)
1920 {
1921         struct vcpu_vmx *vmx = to_vmx(vcpu);
1922         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1923
1924         if (!reinject && nr == PF_VECTOR && is_guest_mode(vcpu) &&
1925             !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1926                 return;
1927
1928         if (has_error_code) {
1929                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1930                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1931         }
1932
1933         if (vmx->rmode.vm86_active) {
1934                 int inc_eip = 0;
1935                 if (kvm_exception_is_soft(nr))
1936                         inc_eip = vcpu->arch.event_exit_inst_len;
1937                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1938                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1939                 return;
1940         }
1941
1942         if (kvm_exception_is_soft(nr)) {
1943                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1944                              vmx->vcpu.arch.event_exit_inst_len);
1945                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1946         } else
1947                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1948
1949         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1950 }
1951
1952 static bool vmx_rdtscp_supported(void)
1953 {
1954         return cpu_has_vmx_rdtscp();
1955 }
1956
1957 static bool vmx_invpcid_supported(void)
1958 {
1959         return cpu_has_vmx_invpcid() && enable_ept;
1960 }
1961
1962 /*
1963  * Swap MSR entry in host/guest MSR entry array.
1964  */
1965 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1966 {
1967         struct shared_msr_entry tmp;
1968
1969         tmp = vmx->guest_msrs[to];
1970         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1971         vmx->guest_msrs[from] = tmp;
1972 }
1973
1974 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1975 {
1976         unsigned long *msr_bitmap;
1977
1978         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1979                 if (is_long_mode(vcpu))
1980                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1981                 else
1982                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1983         } else {
1984                 if (is_long_mode(vcpu))
1985                         msr_bitmap = vmx_msr_bitmap_longmode;
1986                 else
1987                         msr_bitmap = vmx_msr_bitmap_legacy;
1988         }
1989
1990         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1991 }
1992
1993 /*
1994  * Set up the vmcs to automatically save and restore system
1995  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1996  * mode, as fiddling with msrs is very expensive.
1997  */
1998 static void setup_msrs(struct vcpu_vmx *vmx)
1999 {
2000         int save_nmsrs, index;
2001
2002         save_nmsrs = 0;
2003 #ifdef CONFIG_X86_64
2004         if (is_long_mode(&vmx->vcpu)) {
2005                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2006                 if (index >= 0)
2007                         move_msr_up(vmx, index, save_nmsrs++);
2008                 index = __find_msr_index(vmx, MSR_LSTAR);
2009                 if (index >= 0)
2010                         move_msr_up(vmx, index, save_nmsrs++);
2011                 index = __find_msr_index(vmx, MSR_CSTAR);
2012                 if (index >= 0)
2013                         move_msr_up(vmx, index, save_nmsrs++);
2014                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2015                 if (index >= 0 && vmx->rdtscp_enabled)
2016                         move_msr_up(vmx, index, save_nmsrs++);
2017                 /*
2018                  * MSR_STAR is only needed on long mode guests, and only
2019                  * if efer.sce is enabled.
2020                  */
2021                 index = __find_msr_index(vmx, MSR_STAR);
2022                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2023                         move_msr_up(vmx, index, save_nmsrs++);
2024         }
2025 #endif
2026         index = __find_msr_index(vmx, MSR_EFER);
2027         if (index >= 0 && update_transition_efer(vmx, index))
2028                 move_msr_up(vmx, index, save_nmsrs++);
2029
2030         vmx->save_nmsrs = save_nmsrs;
2031
2032         if (cpu_has_vmx_msr_bitmap())
2033                 vmx_set_msr_bitmap(&vmx->vcpu);
2034 }
2035
2036 /*
2037  * reads and returns guest's timestamp counter "register"
2038  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2039  */
2040 static u64 guest_read_tsc(void)
2041 {
2042         u64 host_tsc, tsc_offset;
2043
2044         rdtscll(host_tsc);
2045         tsc_offset = vmcs_read64(TSC_OFFSET);
2046         return host_tsc + tsc_offset;
2047 }
2048
2049 /*
2050  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2051  * counter, even if a nested guest (L2) is currently running.
2052  */
2053 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2054 {
2055         u64 tsc_offset;
2056
2057         tsc_offset = is_guest_mode(vcpu) ?
2058                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2059                 vmcs_read64(TSC_OFFSET);
2060         return host_tsc + tsc_offset;
2061 }
2062
2063 /*
2064  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2065  * software catchup for faster rates on slower CPUs.
2066  */
2067 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2068 {
2069         if (!scale)
2070                 return;
2071
2072         if (user_tsc_khz > tsc_khz) {
2073                 vcpu->arch.tsc_catchup = 1;
2074                 vcpu->arch.tsc_always_catchup = 1;
2075         } else
2076                 WARN(1, "user requested TSC rate below hardware speed\n");
2077 }
2078
2079 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2080 {
2081         return vmcs_read64(TSC_OFFSET);
2082 }
2083
2084 /*
2085  * writes 'offset' into guest's timestamp counter offset register
2086  */
2087 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2088 {
2089         if (is_guest_mode(vcpu)) {
2090                 /*
2091                  * We're here if L1 chose not to trap WRMSR to TSC. According
2092                  * to the spec, this should set L1's TSC; The offset that L1
2093                  * set for L2 remains unchanged, and still needs to be added
2094                  * to the newly set TSC to get L2's TSC.
2095                  */
2096                 struct vmcs12 *vmcs12;
2097                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2098                 /* recalculate vmcs02.TSC_OFFSET: */
2099                 vmcs12 = get_vmcs12(vcpu);
2100                 vmcs_write64(TSC_OFFSET, offset +
2101                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2102                          vmcs12->tsc_offset : 0));
2103         } else {
2104                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2105                                            vmcs_read64(TSC_OFFSET), offset);
2106                 vmcs_write64(TSC_OFFSET, offset);
2107         }
2108 }
2109
2110 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2111 {
2112         u64 offset = vmcs_read64(TSC_OFFSET);
2113
2114         vmcs_write64(TSC_OFFSET, offset + adjustment);
2115         if (is_guest_mode(vcpu)) {
2116                 /* Even when running L2, the adjustment needs to apply to L1 */
2117                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2118         } else
2119                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2120                                            offset + adjustment);
2121 }
2122
2123 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2124 {
2125         return target_tsc - native_read_tsc();
2126 }
2127
2128 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2129 {
2130         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2131         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2132 }
2133
2134 /*
2135  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2136  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2137  * all guests if the "nested" module option is off, and can also be disabled
2138  * for a single guest by disabling its VMX cpuid bit.
2139  */
2140 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2141 {
2142         return nested && guest_cpuid_has_vmx(vcpu);
2143 }
2144
2145 /*
2146  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2147  * returned for the various VMX controls MSRs when nested VMX is enabled.
2148  * The same values should also be used to verify that vmcs12 control fields are
2149  * valid during nested entry from L1 to L2.
2150  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2151  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2152  * bit in the high half is on if the corresponding bit in the control field
2153  * may be on. See also vmx_control_verify().
2154  * TODO: allow these variables to be modified (downgraded) by module options
2155  * or other means.
2156  */
2157 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2158 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2159 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2160 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2161 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2162 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2163 static u32 nested_vmx_ept_caps;
2164 static __init void nested_vmx_setup_ctls_msrs(void)
2165 {
2166         /*
2167          * Note that as a general rule, the high half of the MSRs (bits in
2168          * the control fields which may be 1) should be initialized by the
2169          * intersection of the underlying hardware's MSR (i.e., features which
2170          * can be supported) and the list of features we want to expose -
2171          * because they are known to be properly supported in our code.
2172          * Also, usually, the low half of the MSRs (bits which must be 1) can
2173          * be set to 0, meaning that L1 may turn off any of these bits. The
2174          * reason is that if one of these bits is necessary, it will appear
2175          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2176          * fields of vmcs01 and vmcs02, will turn these bits off - and
2177          * nested_vmx_exit_handled() will not pass related exits to L1.
2178          * These rules have exceptions below.
2179          */
2180
2181         /* pin-based controls */
2182         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2183               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2184         /*
2185          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2186          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2187          */
2188         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2189         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2190                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2191                 PIN_BASED_VMX_PREEMPTION_TIMER;
2192         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2193
2194         /*
2195          * Exit controls
2196          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2197          * 17 must be 1.
2198          */
2199         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2200                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2201         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2202         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2203         nested_vmx_exit_ctls_high &=
2204 #ifdef CONFIG_X86_64
2205                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2206 #endif
2207                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2208         nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2209                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
2210
2211         /* entry controls */
2212         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2213                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2214         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2215         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2216         nested_vmx_entry_ctls_high &=
2217 #ifdef CONFIG_X86_64
2218                 VM_ENTRY_IA32E_MODE |
2219 #endif
2220                 VM_ENTRY_LOAD_IA32_PAT;
2221         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2222                                        VM_ENTRY_LOAD_IA32_EFER);
2223
2224         /* cpu-based controls */
2225         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2226                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2227         nested_vmx_procbased_ctls_low = 0;
2228         nested_vmx_procbased_ctls_high &=
2229                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2230                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2231                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2232                 CPU_BASED_CR3_STORE_EXITING |
2233 #ifdef CONFIG_X86_64
2234                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2235 #endif
2236                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2237                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2238                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2239                 CPU_BASED_PAUSE_EXITING |
2240                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2241         /*
2242          * We can allow some features even when not supported by the
2243          * hardware. For example, L1 can specify an MSR bitmap - and we
2244          * can use it to avoid exits to L1 - even when L0 runs L2
2245          * without MSR bitmaps.
2246          */
2247         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2248
2249         /* secondary cpu-based controls */
2250         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2251                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2252         nested_vmx_secondary_ctls_low = 0;
2253         nested_vmx_secondary_ctls_high &=
2254                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2255                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2256                 SECONDARY_EXEC_WBINVD_EXITING;
2257
2258         if (enable_ept) {
2259                 /* nested EPT: emulate EPT also to L1 */
2260                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2261                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2262                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2263                 nested_vmx_ept_caps &= vmx_capability.ept;
2264                 /*
2265                  * Since invept is completely emulated we support both global
2266                  * and context invalidation independent of what host cpu
2267                  * supports
2268                  */
2269                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2270                         VMX_EPT_EXTENT_CONTEXT_BIT;
2271         } else
2272                 nested_vmx_ept_caps = 0;
2273
2274         /* miscellaneous data */
2275         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2276         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2277                 VMX_MISC_SAVE_EFER_LMA;
2278         nested_vmx_misc_high = 0;
2279 }
2280
2281 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2282 {
2283         /*
2284          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2285          */
2286         return ((control & high) | low) == control;
2287 }
2288
2289 static inline u64 vmx_control_msr(u32 low, u32 high)
2290 {
2291         return low | ((u64)high << 32);
2292 }
2293
2294 /*
2295  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2296  * also let it use VMX-specific MSRs.
2297  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2298  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2299  * like all other MSRs).
2300  */
2301 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2302 {
2303         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2304                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2305                 /*
2306                  * According to the spec, processors which do not support VMX
2307                  * should throw a #GP(0) when VMX capability MSRs are read.
2308                  */
2309                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2310                 return 1;
2311         }
2312
2313         switch (msr_index) {
2314         case MSR_IA32_FEATURE_CONTROL:
2315                 if (nested_vmx_allowed(vcpu)) {
2316                         *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2317                         break;
2318                 }
2319                 return 0;
2320         case MSR_IA32_VMX_BASIC:
2321                 /*
2322                  * This MSR reports some information about VMX support. We
2323                  * should return information about the VMX we emulate for the
2324                  * guest, and the VMCS structure we give it - not about the
2325                  * VMX support of the underlying hardware.
2326                  */
2327                 *pdata = VMCS12_REVISION |
2328                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2329                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2330                 break;
2331         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2332         case MSR_IA32_VMX_PINBASED_CTLS:
2333                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2334                                         nested_vmx_pinbased_ctls_high);
2335                 break;
2336         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2337         case MSR_IA32_VMX_PROCBASED_CTLS:
2338                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2339                                         nested_vmx_procbased_ctls_high);
2340                 break;
2341         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2342         case MSR_IA32_VMX_EXIT_CTLS:
2343                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2344                                         nested_vmx_exit_ctls_high);
2345                 break;
2346         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2347         case MSR_IA32_VMX_ENTRY_CTLS:
2348                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2349                                         nested_vmx_entry_ctls_high);
2350                 break;
2351         case MSR_IA32_VMX_MISC:
2352                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2353                                          nested_vmx_misc_high);
2354                 break;
2355         /*
2356          * These MSRs specify bits which the guest must keep fixed (on or off)
2357          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2358          * We picked the standard core2 setting.
2359          */
2360 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2361 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2362         case MSR_IA32_VMX_CR0_FIXED0:
2363                 *pdata = VMXON_CR0_ALWAYSON;
2364                 break;
2365         case MSR_IA32_VMX_CR0_FIXED1:
2366                 *pdata = -1ULL;
2367                 break;
2368         case MSR_IA32_VMX_CR4_FIXED0:
2369                 *pdata = VMXON_CR4_ALWAYSON;
2370                 break;
2371         case MSR_IA32_VMX_CR4_FIXED1:
2372                 *pdata = -1ULL;
2373                 break;
2374         case MSR_IA32_VMX_VMCS_ENUM:
2375                 *pdata = 0x1f;
2376                 break;
2377         case MSR_IA32_VMX_PROCBASED_CTLS2:
2378                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2379                                         nested_vmx_secondary_ctls_high);
2380                 break;
2381         case MSR_IA32_VMX_EPT_VPID_CAP:
2382                 /* Currently, no nested vpid support */
2383                 *pdata = nested_vmx_ept_caps;
2384                 break;
2385         default:
2386                 return 0;
2387         }
2388
2389         return 1;
2390 }
2391
2392 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2393 {
2394         u32 msr_index = msr_info->index;
2395         u64 data = msr_info->data;
2396         bool host_initialized = msr_info->host_initiated;
2397
2398         if (!nested_vmx_allowed(vcpu))
2399                 return 0;
2400
2401         if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2402                 if (!host_initialized &&
2403                                 to_vmx(vcpu)->nested.msr_ia32_feature_control
2404                                 & FEATURE_CONTROL_LOCKED)
2405                         return 0;
2406                 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
2407                 return 1;
2408         }
2409
2410         /*
2411          * No need to treat VMX capability MSRs specially: If we don't handle
2412          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2413          */
2414         return 0;
2415 }
2416
2417 /*
2418  * Reads an msr value (of 'msr_index') into 'pdata'.
2419  * Returns 0 on success, non-0 otherwise.
2420  * Assumes vcpu_load() was already called.
2421  */
2422 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2423 {
2424         u64 data;
2425         struct shared_msr_entry *msr;
2426
2427         if (!pdata) {
2428                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2429                 return -EINVAL;
2430         }
2431
2432         switch (msr_index) {
2433 #ifdef CONFIG_X86_64
2434         case MSR_FS_BASE:
2435                 data = vmcs_readl(GUEST_FS_BASE);
2436                 break;
2437         case MSR_GS_BASE:
2438                 data = vmcs_readl(GUEST_GS_BASE);
2439                 break;
2440         case MSR_KERNEL_GS_BASE:
2441                 vmx_load_host_state(to_vmx(vcpu));
2442                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2443                 break;
2444 #endif
2445         case MSR_EFER:
2446                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2447         case MSR_IA32_TSC:
2448                 data = guest_read_tsc();
2449                 break;
2450         case MSR_IA32_SYSENTER_CS:
2451                 data = vmcs_read32(GUEST_SYSENTER_CS);
2452                 break;
2453         case MSR_IA32_SYSENTER_EIP:
2454                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2455                 break;
2456         case MSR_IA32_SYSENTER_ESP:
2457                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2458                 break;
2459         case MSR_TSC_AUX:
2460                 if (!to_vmx(vcpu)->rdtscp_enabled)
2461                         return 1;
2462                 /* Otherwise falls through */
2463         default:
2464                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2465                         return 0;
2466                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2467                 if (msr) {
2468                         data = msr->data;
2469                         break;
2470                 }
2471                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2472         }
2473
2474         *pdata = data;
2475         return 0;
2476 }
2477
2478 /*
2479  * Writes msr value into into the appropriate "register".
2480  * Returns 0 on success, non-0 otherwise.
2481  * Assumes vcpu_load() was already called.
2482  */
2483 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2484 {
2485         struct vcpu_vmx *vmx = to_vmx(vcpu);
2486         struct shared_msr_entry *msr;
2487         int ret = 0;
2488         u32 msr_index = msr_info->index;
2489         u64 data = msr_info->data;
2490
2491         switch (msr_index) {
2492         case MSR_EFER:
2493                 ret = kvm_set_msr_common(vcpu, msr_info);
2494                 break;
2495 #ifdef CONFIG_X86_64
2496         case MSR_FS_BASE:
2497                 vmx_segment_cache_clear(vmx);
2498                 vmcs_writel(GUEST_FS_BASE, data);
2499                 break;
2500         case MSR_GS_BASE:
2501                 vmx_segment_cache_clear(vmx);
2502                 vmcs_writel(GUEST_GS_BASE, data);
2503                 break;
2504         case MSR_KERNEL_GS_BASE:
2505                 vmx_load_host_state(vmx);
2506                 vmx->msr_guest_kernel_gs_base = data;
2507                 break;
2508 #endif
2509         case MSR_IA32_SYSENTER_CS:
2510                 vmcs_write32(GUEST_SYSENTER_CS, data);
2511                 break;
2512         case MSR_IA32_SYSENTER_EIP:
2513                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2514                 break;
2515         case MSR_IA32_SYSENTER_ESP:
2516                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2517                 break;
2518         case MSR_IA32_TSC:
2519                 kvm_write_tsc(vcpu, msr_info);
2520                 break;
2521         case MSR_IA32_CR_PAT:
2522                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2523                         vmcs_write64(GUEST_IA32_PAT, data);
2524                         vcpu->arch.pat = data;
2525                         break;
2526                 }
2527                 ret = kvm_set_msr_common(vcpu, msr_info);
2528                 break;
2529         case MSR_IA32_TSC_ADJUST:
2530                 ret = kvm_set_msr_common(vcpu, msr_info);
2531                 break;
2532         case MSR_TSC_AUX:
2533                 if (!vmx->rdtscp_enabled)
2534                         return 1;
2535                 /* Check reserved bit, higher 32 bits should be zero */
2536                 if ((data >> 32) != 0)
2537                         return 1;
2538                 /* Otherwise falls through */
2539         default:
2540                 if (vmx_set_vmx_msr(vcpu, msr_info))
2541                         break;
2542                 msr = find_msr_entry(vmx, msr_index);
2543                 if (msr) {
2544                         msr->data = data;
2545                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2546                                 preempt_disable();
2547                                 kvm_set_shared_msr(msr->index, msr->data,
2548                                                    msr->mask);
2549                                 preempt_enable();
2550                         }
2551                         break;
2552                 }
2553                 ret = kvm_set_msr_common(vcpu, msr_info);
2554         }
2555
2556         return ret;
2557 }
2558
2559 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2560 {
2561         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2562         switch (reg) {
2563         case VCPU_REGS_RSP:
2564                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2565                 break;
2566         case VCPU_REGS_RIP:
2567                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2568                 break;
2569         case VCPU_EXREG_PDPTR:
2570                 if (enable_ept)
2571                         ept_save_pdptrs(vcpu);
2572                 break;
2573         default:
2574                 break;
2575         }
2576 }
2577
2578 static __init int cpu_has_kvm_support(void)
2579 {
2580         return cpu_has_vmx();
2581 }
2582
2583 static __init int vmx_disabled_by_bios(void)
2584 {
2585         u64 msr;
2586
2587         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2588         if (msr & FEATURE_CONTROL_LOCKED) {
2589                 /* launched w/ TXT and VMX disabled */
2590                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2591                         && tboot_enabled())
2592                         return 1;
2593                 /* launched w/o TXT and VMX only enabled w/ TXT */
2594                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2595                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2596                         && !tboot_enabled()) {
2597                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2598                                 "activate TXT before enabling KVM\n");
2599                         return 1;
2600                 }
2601                 /* launched w/o TXT and VMX disabled */
2602                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2603                         && !tboot_enabled())
2604                         return 1;
2605         }
2606
2607         return 0;
2608 }
2609
2610 static void kvm_cpu_vmxon(u64 addr)
2611 {
2612         asm volatile (ASM_VMX_VMXON_RAX
2613                         : : "a"(&addr), "m"(addr)
2614                         : "memory", "cc");
2615 }
2616
2617 static int hardware_enable(void *garbage)
2618 {
2619         int cpu = raw_smp_processor_id();
2620         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2621         u64 old, test_bits;
2622
2623         if (read_cr4() & X86_CR4_VMXE)
2624                 return -EBUSY;
2625
2626         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2627
2628         /*
2629          * Now we can enable the vmclear operation in kdump
2630          * since the loaded_vmcss_on_cpu list on this cpu
2631          * has been initialized.
2632          *
2633          * Though the cpu is not in VMX operation now, there
2634          * is no problem to enable the vmclear operation
2635          * for the loaded_vmcss_on_cpu list is empty!
2636          */
2637         crash_enable_local_vmclear(cpu);
2638
2639         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2640
2641         test_bits = FEATURE_CONTROL_LOCKED;
2642         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2643         if (tboot_enabled())
2644                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2645
2646         if ((old & test_bits) != test_bits) {
2647                 /* enable and lock */
2648                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2649         }
2650         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2651
2652         if (vmm_exclusive) {
2653                 kvm_cpu_vmxon(phys_addr);
2654                 ept_sync_global();
2655         }
2656
2657         native_store_gdt(&__get_cpu_var(host_gdt));
2658
2659         return 0;
2660 }
2661
2662 static void vmclear_local_loaded_vmcss(void)
2663 {
2664         int cpu = raw_smp_processor_id();
2665         struct loaded_vmcs *v, *n;
2666
2667         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2668                                  loaded_vmcss_on_cpu_link)
2669                 __loaded_vmcs_clear(v);
2670 }
2671
2672
2673 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2674  * tricks.
2675  */
2676 static void kvm_cpu_vmxoff(void)
2677 {
2678         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2679 }
2680
2681 static void hardware_disable(void *garbage)
2682 {
2683         if (vmm_exclusive) {
2684                 vmclear_local_loaded_vmcss();
2685                 kvm_cpu_vmxoff();
2686         }
2687         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2688 }
2689
2690 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2691                                       u32 msr, u32 *result)
2692 {
2693         u32 vmx_msr_low, vmx_msr_high;
2694         u32 ctl = ctl_min | ctl_opt;
2695
2696         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2697
2698         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2699         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2700
2701         /* Ensure minimum (required) set of control bits are supported. */
2702         if (ctl_min & ~ctl)
2703                 return -EIO;
2704
2705         *result = ctl;
2706         return 0;
2707 }
2708
2709 static __init bool allow_1_setting(u32 msr, u32 ctl)
2710 {
2711         u32 vmx_msr_low, vmx_msr_high;
2712
2713         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2714         return vmx_msr_high & ctl;
2715 }
2716
2717 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2718 {
2719         u32 vmx_msr_low, vmx_msr_high;
2720         u32 min, opt, min2, opt2;
2721         u32 _pin_based_exec_control = 0;
2722         u32 _cpu_based_exec_control = 0;
2723         u32 _cpu_based_2nd_exec_control = 0;
2724         u32 _vmexit_control = 0;
2725         u32 _vmentry_control = 0;
2726
2727         min = CPU_BASED_HLT_EXITING |
2728 #ifdef CONFIG_X86_64
2729               CPU_BASED_CR8_LOAD_EXITING |
2730               CPU_BASED_CR8_STORE_EXITING |
2731 #endif
2732               CPU_BASED_CR3_LOAD_EXITING |
2733               CPU_BASED_CR3_STORE_EXITING |
2734               CPU_BASED_USE_IO_BITMAPS |
2735               CPU_BASED_MOV_DR_EXITING |
2736               CPU_BASED_USE_TSC_OFFSETING |
2737               CPU_BASED_MWAIT_EXITING |
2738               CPU_BASED_MONITOR_EXITING |
2739               CPU_BASED_INVLPG_EXITING |
2740               CPU_BASED_RDPMC_EXITING;
2741
2742         opt = CPU_BASED_TPR_SHADOW |
2743               CPU_BASED_USE_MSR_BITMAPS |
2744               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2745         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2746                                 &_cpu_based_exec_control) < 0)
2747                 return -EIO;
2748 #ifdef CONFIG_X86_64
2749         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2750                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2751                                            ~CPU_BASED_CR8_STORE_EXITING;
2752 #endif
2753         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2754                 min2 = 0;
2755                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2756                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2757                         SECONDARY_EXEC_WBINVD_EXITING |
2758                         SECONDARY_EXEC_ENABLE_VPID |
2759                         SECONDARY_EXEC_ENABLE_EPT |
2760                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2761                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2762                         SECONDARY_EXEC_RDTSCP |
2763                         SECONDARY_EXEC_ENABLE_INVPCID |
2764                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2765                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2766                         SECONDARY_EXEC_SHADOW_VMCS;
2767                 if (adjust_vmx_controls(min2, opt2,
2768                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2769                                         &_cpu_based_2nd_exec_control) < 0)
2770                         return -EIO;
2771         }
2772 #ifndef CONFIG_X86_64
2773         if (!(_cpu_based_2nd_exec_control &
2774                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2775                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2776 #endif
2777
2778         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2779                 _cpu_based_2nd_exec_control &= ~(
2780                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2781                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2782                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2783
2784         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2785                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2786                    enabled */
2787                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2788                                              CPU_BASED_CR3_STORE_EXITING |
2789                                              CPU_BASED_INVLPG_EXITING);
2790                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2791                       vmx_capability.ept, vmx_capability.vpid);
2792         }
2793
2794         min = 0;
2795 #ifdef CONFIG_X86_64
2796         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2797 #endif
2798         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2799                 VM_EXIT_ACK_INTR_ON_EXIT;
2800         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2801                                 &_vmexit_control) < 0)
2802                 return -EIO;
2803
2804         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2805         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2806         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2807                                 &_pin_based_exec_control) < 0)
2808                 return -EIO;
2809
2810         if (!(_cpu_based_2nd_exec_control &
2811                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2812                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2813                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2814
2815         min = 0;
2816         opt = VM_ENTRY_LOAD_IA32_PAT;
2817         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2818                                 &_vmentry_control) < 0)
2819                 return -EIO;
2820
2821         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2822
2823         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2824         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2825                 return -EIO;
2826
2827 #ifdef CONFIG_X86_64
2828         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2829         if (vmx_msr_high & (1u<<16))
2830                 return -EIO;
2831 #endif
2832
2833         /* Require Write-Back (WB) memory type for VMCS accesses. */
2834         if (((vmx_msr_high >> 18) & 15) != 6)
2835                 return -EIO;
2836
2837         vmcs_conf->size = vmx_msr_high & 0x1fff;
2838         vmcs_conf->order = get_order(vmcs_config.size);
2839         vmcs_conf->revision_id = vmx_msr_low;
2840
2841         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2842         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2843         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2844         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2845         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2846
2847         cpu_has_load_ia32_efer =
2848                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2849                                 VM_ENTRY_LOAD_IA32_EFER)
2850                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2851                                    VM_EXIT_LOAD_IA32_EFER);
2852
2853         cpu_has_load_perf_global_ctrl =
2854                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2855                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2856                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2857                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2858
2859         /*
2860          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2861          * but due to arrata below it can't be used. Workaround is to use
2862          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2863          *
2864          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2865          *
2866          * AAK155             (model 26)
2867          * AAP115             (model 30)
2868          * AAT100             (model 37)
2869          * BC86,AAY89,BD102   (model 44)
2870          * BA97               (model 46)
2871          *
2872          */
2873         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2874                 switch (boot_cpu_data.x86_model) {
2875                 case 26:
2876                 case 30:
2877                 case 37:
2878                 case 44:
2879                 case 46:
2880                         cpu_has_load_perf_global_ctrl = false;
2881                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2882                                         "does not work properly. Using workaround\n");
2883                         break;
2884                 default:
2885                         break;
2886                 }
2887         }
2888
2889         return 0;
2890 }
2891
2892 static struct vmcs *alloc_vmcs_cpu(int cpu)
2893 {
2894         int node = cpu_to_node(cpu);
2895         struct page *pages;
2896         struct vmcs *vmcs;
2897
2898         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2899         if (!pages)
2900                 return NULL;
2901         vmcs = page_address(pages);
2902         memset(vmcs, 0, vmcs_config.size);
2903         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2904         return vmcs;
2905 }
2906
2907 static struct vmcs *alloc_vmcs(void)
2908 {
2909         return alloc_vmcs_cpu(raw_smp_processor_id());
2910 }
2911
2912 static void free_vmcs(struct vmcs *vmcs)
2913 {
2914         free_pages((unsigned long)vmcs, vmcs_config.order);
2915 }
2916
2917 /*
2918  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2919  */
2920 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2921 {
2922         if (!loaded_vmcs->vmcs)
2923                 return;
2924         loaded_vmcs_clear(loaded_vmcs);
2925         free_vmcs(loaded_vmcs->vmcs);
2926         loaded_vmcs->vmcs = NULL;
2927 }
2928
2929 static void free_kvm_area(void)
2930 {
2931         int cpu;
2932
2933         for_each_possible_cpu(cpu) {
2934                 free_vmcs(per_cpu(vmxarea, cpu));
2935                 per_cpu(vmxarea, cpu) = NULL;
2936         }
2937 }
2938
2939 static __init int alloc_kvm_area(void)
2940 {
2941         int cpu;
2942
2943         for_each_possible_cpu(cpu) {
2944                 struct vmcs *vmcs;
2945
2946                 vmcs = alloc_vmcs_cpu(cpu);
2947                 if (!vmcs) {
2948                         free_kvm_area();
2949                         return -ENOMEM;
2950                 }
2951
2952                 per_cpu(vmxarea, cpu) = vmcs;
2953         }
2954         return 0;
2955 }
2956
2957 static __init int hardware_setup(void)
2958 {
2959         if (setup_vmcs_config(&vmcs_config) < 0)
2960                 return -EIO;
2961
2962         if (boot_cpu_has(X86_FEATURE_NX))
2963                 kvm_enable_efer_bits(EFER_NX);
2964
2965         if (!cpu_has_vmx_vpid())
2966                 enable_vpid = 0;
2967         if (!cpu_has_vmx_shadow_vmcs())
2968                 enable_shadow_vmcs = 0;
2969
2970         if (!cpu_has_vmx_ept() ||
2971             !cpu_has_vmx_ept_4levels()) {
2972                 enable_ept = 0;
2973                 enable_unrestricted_guest = 0;
2974                 enable_ept_ad_bits = 0;
2975         }
2976
2977         if (!cpu_has_vmx_ept_ad_bits())
2978                 enable_ept_ad_bits = 0;
2979
2980         if (!cpu_has_vmx_unrestricted_guest())
2981                 enable_unrestricted_guest = 0;
2982
2983         if (!cpu_has_vmx_flexpriority())
2984                 flexpriority_enabled = 0;
2985
2986         if (!cpu_has_vmx_tpr_shadow())
2987                 kvm_x86_ops->update_cr8_intercept = NULL;
2988
2989         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2990                 kvm_disable_largepages();
2991
2992         if (!cpu_has_vmx_ple())
2993                 ple_gap = 0;
2994
2995         if (!cpu_has_vmx_apicv())
2996                 enable_apicv = 0;
2997
2998         if (enable_apicv)
2999                 kvm_x86_ops->update_cr8_intercept = NULL;
3000         else {
3001                 kvm_x86_ops->hwapic_irr_update = NULL;
3002                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3003                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3004         }
3005
3006         if (nested)
3007                 nested_vmx_setup_ctls_msrs();
3008
3009         return alloc_kvm_area();
3010 }
3011
3012 static __exit void hardware_unsetup(void)
3013 {
3014         free_kvm_area();
3015 }
3016
3017 static bool emulation_required(struct kvm_vcpu *vcpu)
3018 {
3019         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3020 }
3021
3022 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3023                 struct kvm_segment *save)
3024 {
3025         if (!emulate_invalid_guest_state) {
3026                 /*
3027                  * CS and SS RPL should be equal during guest entry according
3028                  * to VMX spec, but in reality it is not always so. Since vcpu
3029                  * is in the middle of the transition from real mode to
3030                  * protected mode it is safe to assume that RPL 0 is a good
3031                  * default value.
3032                  */
3033                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3034                         save->selector &= ~SELECTOR_RPL_MASK;
3035                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3036                 save->s = 1;
3037         }
3038         vmx_set_segment(vcpu, save, seg);
3039 }
3040
3041 static void enter_pmode(struct kvm_vcpu *vcpu)
3042 {
3043         unsigned long flags;
3044         struct vcpu_vmx *vmx = to_vmx(vcpu);
3045
3046         /*
3047          * Update real mode segment cache. It may be not up-to-date if sement
3048          * register was written while vcpu was in a guest mode.
3049          */
3050         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3051         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3052         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3053         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3054         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3055         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3056
3057         vmx->rmode.vm86_active = 0;
3058
3059         vmx_segment_cache_clear(vmx);
3060
3061         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3062
3063         flags = vmcs_readl(GUEST_RFLAGS);
3064         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3065         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3066         vmcs_writel(GUEST_RFLAGS, flags);
3067
3068         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3069                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3070
3071         update_exception_bitmap(vcpu);
3072
3073         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3074         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3075         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3076         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3077         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3078         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3079
3080         /* CPL is always 0 when CPU enters protected mode */
3081         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3082         vmx->cpl = 0;
3083 }
3084
3085 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3086 {
3087         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3088         struct kvm_segment var = *save;
3089
3090         var.dpl = 0x3;
3091         if (seg == VCPU_SREG_CS)
3092                 var.type = 0x3;
3093
3094         if (!emulate_invalid_guest_state) {
3095                 var.selector = var.base >> 4;
3096                 var.base = var.base & 0xffff0;
3097                 var.limit = 0xffff;
3098                 var.g = 0;
3099                 var.db = 0;
3100                 var.present = 1;
3101                 var.s = 1;
3102                 var.l = 0;
3103                 var.unusable = 0;
3104                 var.type = 0x3;
3105                 var.avl = 0;
3106                 if (save->base & 0xf)
3107                         printk_once(KERN_WARNING "kvm: segment base is not "
3108                                         "paragraph aligned when entering "
3109                                         "protected mode (seg=%d)", seg);
3110         }
3111
3112         vmcs_write16(sf->selector, var.selector);
3113         vmcs_write32(sf->base, var.base);
3114         vmcs_write32(sf->limit, var.limit);
3115         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3116 }
3117
3118 static void enter_rmode(struct kvm_vcpu *vcpu)
3119 {
3120         unsigned long flags;
3121         struct vcpu_vmx *vmx = to_vmx(vcpu);
3122
3123         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3124         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3125         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3126         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3127         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3128         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3129         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3130
3131         vmx->rmode.vm86_active = 1;
3132
3133         /*
3134          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3135          * vcpu. Warn the user that an update is overdue.
3136          */
3137         if (!vcpu->kvm->arch.tss_addr)
3138                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3139                              "called before entering vcpu\n");
3140
3141         vmx_segment_cache_clear(vmx);
3142
3143         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3144         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3145         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3146
3147         flags = vmcs_readl(GUEST_RFLAGS);
3148         vmx->rmode.save_rflags = flags;
3149
3150         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3151
3152         vmcs_writel(GUEST_RFLAGS, flags);
3153         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3154         update_exception_bitmap(vcpu);
3155
3156         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3157         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3158         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3159         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3160         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3161         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3162
3163         kvm_mmu_reset_context(vcpu);
3164 }
3165
3166 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3167 {
3168         struct vcpu_vmx *vmx = to_vmx(vcpu);
3169         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3170
3171         if (!msr)
3172                 return;
3173
3174         /*
3175          * Force kernel_gs_base reloading before EFER changes, as control
3176          * of this msr depends on is_long_mode().
3177          */
3178         vmx_load_host_state(to_vmx(vcpu));
3179         vcpu->arch.efer = efer;
3180         if (efer & EFER_LMA) {
3181                 vmcs_write32(VM_ENTRY_CONTROLS,
3182                              vmcs_read32(VM_ENTRY_CONTROLS) |
3183                              VM_ENTRY_IA32E_MODE);
3184                 msr->data = efer;
3185         } else {
3186                 vmcs_write32(VM_ENTRY_CONTROLS,
3187                              vmcs_read32(VM_ENTRY_CONTROLS) &
3188                              ~VM_ENTRY_IA32E_MODE);
3189
3190                 msr->data = efer & ~EFER_LME;
3191         }
3192         setup_msrs(vmx);
3193 }
3194
3195 #ifdef CONFIG_X86_64
3196
3197 static void enter_lmode(struct kvm_vcpu *vcpu)
3198 {
3199         u32 guest_tr_ar;
3200
3201         vmx_segment_cache_clear(to_vmx(vcpu));
3202
3203         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3204         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3205                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3206                                      __func__);
3207                 vmcs_write32(GUEST_TR_AR_BYTES,
3208                              (guest_tr_ar & ~AR_TYPE_MASK)
3209                              | AR_TYPE_BUSY_64_TSS);
3210         }
3211         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3212 }
3213
3214 static void exit_lmode(struct kvm_vcpu *vcpu)
3215 {
3216         vmcs_write32(VM_ENTRY_CONTROLS,
3217                      vmcs_read32(VM_ENTRY_CONTROLS)
3218                      & ~VM_ENTRY_IA32E_MODE);
3219         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3220 }
3221
3222 #endif
3223
3224 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3225 {
3226         vpid_sync_context(to_vmx(vcpu));
3227         if (enable_ept) {
3228                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3229                         return;
3230                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3231         }
3232 }
3233
3234 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3235 {
3236         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3237
3238         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3239         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3240 }
3241
3242 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3243 {
3244         if (enable_ept && is_paging(vcpu))
3245                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3246         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3247 }
3248
3249 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3250 {
3251         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3252
3253         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3254         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3255 }
3256
3257 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3258 {
3259         if (!test_bit(VCPU_EXREG_PDPTR,
3260                       (unsigned long *)&vcpu->arch.regs_dirty))
3261                 return;
3262
3263         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3264                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3265                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3266                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3267                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3268         }
3269 }
3270
3271 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3272 {
3273         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3274                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3275                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3276                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3277                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3278         }
3279
3280         __set_bit(VCPU_EXREG_PDPTR,
3281                   (unsigned long *)&vcpu->arch.regs_avail);
3282         __set_bit(VCPU_EXREG_PDPTR,
3283                   (unsigned long *)&vcpu->arch.regs_dirty);
3284 }
3285
3286 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3287
3288 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3289                                         unsigned long cr0,
3290                                         struct kvm_vcpu *vcpu)
3291 {
3292         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3293                 vmx_decache_cr3(vcpu);
3294         if (!(cr0 & X86_CR0_PG)) {
3295                 /* From paging/starting to nonpaging */
3296                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3297                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3298                              (CPU_BASED_CR3_LOAD_EXITING |
3299                               CPU_BASED_CR3_STORE_EXITING));
3300                 vcpu->arch.cr0 = cr0;
3301                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3302         } else if (!is_paging(vcpu)) {
3303                 /* From nonpaging to paging */
3304                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3305                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3306                              ~(CPU_BASED_CR3_LOAD_EXITING |
3307                                CPU_BASED_CR3_STORE_EXITING));
3308                 vcpu->arch.cr0 = cr0;
3309                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3310         }
3311
3312         if (!(cr0 & X86_CR0_WP))
3313                 *hw_cr0 &= ~X86_CR0_WP;
3314 }
3315
3316 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3317 {
3318         struct vcpu_vmx *vmx = to_vmx(vcpu);
3319         unsigned long hw_cr0;
3320
3321         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3322         if (enable_unrestricted_guest)
3323                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3324         else {
3325                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3326
3327                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3328                         enter_pmode(vcpu);
3329
3330                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3331                         enter_rmode(vcpu);
3332         }
3333
3334 #ifdef CONFIG_X86_64
3335         if (vcpu->arch.efer & EFER_LME) {
3336                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3337                         enter_lmode(vcpu);
3338                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3339                         exit_lmode(vcpu);
3340         }
3341 #endif
3342
3343         if (enable_ept)
3344                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3345
3346         if (!vcpu->fpu_active)
3347                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3348
3349         vmcs_writel(CR0_READ_SHADOW, cr0);
3350         vmcs_writel(GUEST_CR0, hw_cr0);
3351         vcpu->arch.cr0 = cr0;
3352
3353         /* depends on vcpu->arch.cr0 to be set to a new value */
3354         vmx->emulation_required = emulation_required(vcpu);
3355 }
3356
3357 static u64 construct_eptp(unsigned long root_hpa)
3358 {
3359         u64 eptp;
3360
3361         /* TODO write the value reading from MSR */
3362         eptp = VMX_EPT_DEFAULT_MT |
3363                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3364         if (enable_ept_ad_bits)
3365                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3366         eptp |= (root_hpa & PAGE_MASK);
3367
3368         return eptp;
3369 }
3370
3371 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3372 {
3373         unsigned long guest_cr3;
3374         u64 eptp;
3375
3376         guest_cr3 = cr3;
3377         if (enable_ept) {
3378                 eptp = construct_eptp(cr3);
3379                 vmcs_write64(EPT_POINTER, eptp);
3380                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3381                         guest_cr3 = kvm_read_cr3(vcpu);
3382                 else
3383                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3384                 ept_load_pdptrs(vcpu);
3385         }
3386
3387         vmx_flush_tlb(vcpu);
3388         vmcs_writel(GUEST_CR3, guest_cr3);
3389 }
3390
3391 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3392 {
3393         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3394                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3395
3396         if (cr4 & X86_CR4_VMXE) {
3397                 /*
3398                  * To use VMXON (and later other VMX instructions), a guest
3399                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3400                  * So basically the check on whether to allow nested VMX
3401                  * is here.
3402                  */
3403                 if (!nested_vmx_allowed(vcpu))
3404                         return 1;
3405         }
3406         if (to_vmx(vcpu)->nested.vmxon &&
3407             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3408                 return 1;
3409
3410         vcpu->arch.cr4 = cr4;
3411         if (enable_ept) {
3412                 if (!is_paging(vcpu)) {
3413                         hw_cr4 &= ~X86_CR4_PAE;
3414                         hw_cr4 |= X86_CR4_PSE;
3415                         /*
3416                          * SMEP is disabled if CPU is in non-paging mode in
3417                          * hardware. However KVM always uses paging mode to
3418                          * emulate guest non-paging mode with TDP.
3419                          * To emulate this behavior, SMEP needs to be manually
3420                          * disabled when guest switches to non-paging mode.
3421                          */
3422                         hw_cr4 &= ~X86_CR4_SMEP;
3423                 } else if (!(cr4 & X86_CR4_PAE)) {
3424                         hw_cr4 &= ~X86_CR4_PAE;
3425                 }
3426         }
3427
3428         vmcs_writel(CR4_READ_SHADOW, cr4);
3429         vmcs_writel(GUEST_CR4, hw_cr4);
3430         return 0;
3431 }
3432
3433 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3434                             struct kvm_segment *var, int seg)
3435 {
3436         struct vcpu_vmx *vmx = to_vmx(vcpu);
3437         u32 ar;
3438
3439         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3440                 *var = vmx->rmode.segs[seg];
3441                 if (seg == VCPU_SREG_TR
3442                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3443                         return;
3444                 var->base = vmx_read_guest_seg_base(vmx, seg);
3445                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3446                 return;
3447         }
3448         var->base = vmx_read_guest_seg_base(vmx, seg);
3449         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3450         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3451         ar = vmx_read_guest_seg_ar(vmx, seg);
3452         var->unusable = (ar >> 16) & 1;
3453         var->type = ar & 15;
3454         var->s = (ar >> 4) & 1;
3455         var->dpl = (ar >> 5) & 3;
3456         /*
3457          * Some userspaces do not preserve unusable property. Since usable
3458          * segment has to be present according to VMX spec we can use present
3459          * property to amend userspace bug by making unusable segment always
3460          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3461          * segment as unusable.
3462          */
3463         var->present = !var->unusable;
3464         var->avl = (ar >> 12) & 1;
3465         var->l = (ar >> 13) & 1;
3466         var->db = (ar >> 14) & 1;
3467         var->g = (ar >> 15) & 1;
3468 }
3469
3470 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3471 {
3472         struct kvm_segment s;
3473
3474         if (to_vmx(vcpu)->rmode.vm86_active) {
3475                 vmx_get_segment(vcpu, &s, seg);
3476                 return s.base;
3477         }
3478         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3479 }
3480
3481 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3482 {
3483         struct vcpu_vmx *vmx = to_vmx(vcpu);
3484
3485         if (!is_protmode(vcpu))
3486                 return 0;
3487
3488         if (!is_long_mode(vcpu)
3489             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3490                 return 3;
3491
3492         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3493                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3494                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3495         }
3496
3497         return vmx->cpl;
3498 }
3499
3500
3501 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3502 {
3503         u32 ar;
3504
3505         if (var->unusable || !var->present)
3506                 ar = 1 << 16;
3507         else {
3508                 ar = var->type & 15;
3509                 ar |= (var->s & 1) << 4;
3510                 ar |= (var->dpl & 3) << 5;
3511                 ar |= (var->present & 1) << 7;
3512                 ar |= (var->avl & 1) << 12;
3513                 ar |= (var->l & 1) << 13;
3514                 ar |= (var->db & 1) << 14;
3515                 ar |= (var->g & 1) << 15;
3516         }
3517
3518         return ar;
3519 }
3520
3521 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3522                             struct kvm_segment *var, int seg)
3523 {
3524         struct vcpu_vmx *vmx = to_vmx(vcpu);
3525         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3526
3527         vmx_segment_cache_clear(vmx);
3528         if (seg == VCPU_SREG_CS)
3529                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3530
3531         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3532                 vmx->rmode.segs[seg] = *var;
3533                 if (seg == VCPU_SREG_TR)
3534                         vmcs_write16(sf->selector, var->selector);
3535                 else if (var->s)
3536                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3537                 goto out;
3538         }
3539
3540         vmcs_writel(sf->base, var->base);
3541         vmcs_write32(sf->limit, var->limit);
3542         vmcs_write16(sf->selector, var->selector);
3543
3544         /*
3545          *   Fix the "Accessed" bit in AR field of segment registers for older
3546          * qemu binaries.
3547          *   IA32 arch specifies that at the time of processor reset the
3548          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3549          * is setting it to 0 in the userland code. This causes invalid guest
3550          * state vmexit when "unrestricted guest" mode is turned on.
3551          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3552          * tree. Newer qemu binaries with that qemu fix would not need this
3553          * kvm hack.
3554          */
3555         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3556                 var->type |= 0x1; /* Accessed */
3557
3558         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3559
3560 out:
3561         vmx->emulation_required |= emulation_required(vcpu);
3562 }
3563
3564 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3565 {
3566         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3567
3568         *db = (ar >> 14) & 1;
3569         *l = (ar >> 13) & 1;
3570 }
3571
3572 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3573 {
3574         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3575         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3576 }
3577
3578 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3579 {
3580         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3581         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3582 }
3583
3584 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3585 {
3586         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3587         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3588 }
3589
3590 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3591 {
3592         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3593         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3594 }
3595
3596 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3597 {
3598         struct kvm_segment var;
3599         u32 ar;
3600
3601         vmx_get_segment(vcpu, &var, seg);
3602         var.dpl = 0x3;
3603         if (seg == VCPU_SREG_CS)
3604                 var.type = 0x3;
3605         ar = vmx_segment_access_rights(&var);
3606
3607         if (var.base != (var.selector << 4))
3608                 return false;
3609         if (var.limit != 0xffff)
3610                 return false;
3611         if (ar != 0xf3)
3612                 return false;
3613
3614         return true;
3615 }
3616
3617 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3618 {
3619         struct kvm_segment cs;
3620         unsigned int cs_rpl;
3621
3622         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3623         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3624
3625         if (cs.unusable)
3626                 return false;
3627         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3628                 return false;
3629         if (!cs.s)
3630                 return false;
3631         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3632                 if (cs.dpl > cs_rpl)
3633                         return false;
3634         } else {
3635                 if (cs.dpl != cs_rpl)
3636                         return false;
3637         }
3638         if (!cs.present)
3639                 return false;
3640
3641         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3642         return true;
3643 }
3644
3645 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3646 {
3647         struct kvm_segment ss;
3648         unsigned int ss_rpl;
3649
3650         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3651         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3652
3653         if (ss.unusable)
3654                 return true;
3655         if (ss.type != 3 && ss.type != 7)
3656                 return false;
3657         if (!ss.s)
3658                 return false;
3659         if (ss.dpl != ss_rpl) /* DPL != RPL */
3660                 return false;
3661         if (!ss.present)
3662                 return false;
3663
3664         return true;
3665 }
3666
3667 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3668 {
3669         struct kvm_segment var;
3670         unsigned int rpl;
3671
3672         vmx_get_segment(vcpu, &var, seg);
3673         rpl = var.selector & SELECTOR_RPL_MASK;
3674
3675         if (var.unusable)
3676                 return true;
3677         if (!var.s)
3678                 return false;
3679         if (!var.present)
3680                 return false;
3681         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3682                 if (var.dpl < rpl) /* DPL < RPL */
3683                         return false;
3684         }
3685
3686         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3687          * rights flags
3688          */
3689         return true;
3690 }
3691
3692 static bool tr_valid(struct kvm_vcpu *vcpu)
3693 {
3694         struct kvm_segment tr;
3695
3696         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3697
3698         if (tr.unusable)
3699                 return false;
3700         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3701                 return false;
3702         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3703                 return false;
3704         if (!tr.present)
3705                 return false;
3706
3707         return true;
3708 }
3709
3710 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3711 {
3712         struct kvm_segment ldtr;
3713
3714         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3715
3716         if (ldtr.unusable)
3717                 return true;
3718         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3719                 return false;
3720         if (ldtr.type != 2)
3721                 return false;
3722         if (!ldtr.present)
3723                 return false;
3724
3725         return true;
3726 }
3727
3728 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3729 {
3730         struct kvm_segment cs, ss;
3731
3732         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3733         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3734
3735         return ((cs.selector & SELECTOR_RPL_MASK) ==
3736                  (ss.selector & SELECTOR_RPL_MASK));
3737 }
3738
3739 /*
3740  * Check if guest state is valid. Returns true if valid, false if
3741  * not.
3742  * We assume that registers are always usable
3743  */
3744 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3745 {
3746         if (enable_unrestricted_guest)
3747                 return true;
3748
3749         /* real mode guest state checks */
3750         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3751                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3752                         return false;
3753                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3754                         return false;
3755                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3756                         return false;
3757                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3758                         return false;
3759                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3760                         return false;
3761                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3762                         return false;
3763         } else {
3764         /* protected mode guest state checks */
3765                 if (!cs_ss_rpl_check(vcpu))
3766                         return false;
3767                 if (!code_segment_valid(vcpu))
3768                         return false;
3769                 if (!stack_segment_valid(vcpu))
3770                         return false;
3771                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3772                         return false;
3773                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3774                         return false;
3775                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3776                         return false;
3777                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3778                         return false;
3779                 if (!tr_valid(vcpu))
3780                         return false;
3781                 if (!ldtr_valid(vcpu))
3782                         return false;
3783         }
3784         /* TODO:
3785          * - Add checks on RIP
3786          * - Add checks on RFLAGS
3787          */
3788
3789         return true;
3790 }
3791
3792 static int init_rmode_tss(struct kvm *kvm)
3793 {
3794         gfn_t fn;
3795         u16 data = 0;
3796         int r, idx, ret = 0;
3797
3798         idx = srcu_read_lock(&kvm->srcu);
3799         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3800         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3801         if (r < 0)
3802                 goto out;
3803         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3804         r = kvm_write_guest_page(kvm, fn++, &data,
3805                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3806         if (r < 0)
3807                 goto out;
3808         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3809         if (r < 0)
3810                 goto out;
3811         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3812         if (r < 0)
3813                 goto out;
3814         data = ~0;
3815         r = kvm_write_guest_page(kvm, fn, &data,
3816                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3817                                  sizeof(u8));
3818         if (r < 0)
3819                 goto out;
3820
3821         ret = 1;
3822 out:
3823         srcu_read_unlock(&kvm->srcu, idx);
3824         return ret;
3825 }
3826
3827 static int init_rmode_identity_map(struct kvm *kvm)
3828 {
3829         int i, idx, r, ret;
3830         pfn_t identity_map_pfn;
3831         u32 tmp;
3832
3833         if (!enable_ept)
3834                 return 1;
3835         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3836                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3837                         "haven't been allocated!\n");
3838                 return 0;
3839         }
3840         if (likely(kvm->arch.ept_identity_pagetable_done))
3841                 return 1;
3842         ret = 0;
3843         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3844         idx = srcu_read_lock(&kvm->srcu);
3845         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3846         if (r < 0)
3847                 goto out;
3848         /* Set up identity-mapping pagetable for EPT in real mode */
3849         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3850                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3851                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3852                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3853                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3854                 if (r < 0)
3855                         goto out;
3856         }
3857         kvm->arch.ept_identity_pagetable_done = true;
3858         ret = 1;
3859 out:
3860         srcu_read_unlock(&kvm->srcu, idx);
3861         return ret;
3862 }
3863
3864 static void seg_setup(int seg)
3865 {
3866         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3867         unsigned int ar;
3868
3869         vmcs_write16(sf->selector, 0);
3870         vmcs_writel(sf->base, 0);
3871         vmcs_write32(sf->limit, 0xffff);
3872         ar = 0x93;
3873         if (seg == VCPU_SREG_CS)
3874                 ar |= 0x08; /* code segment */
3875
3876         vmcs_write32(sf->ar_bytes, ar);
3877 }
3878
3879 static int alloc_apic_access_page(struct kvm *kvm)
3880 {
3881         struct page *page;
3882         struct kvm_userspace_memory_region kvm_userspace_mem;
3883         int r = 0;
3884
3885         mutex_lock(&kvm->slots_lock);
3886         if (kvm->arch.apic_access_page)
3887                 goto out;
3888         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3889         kvm_userspace_mem.flags = 0;
3890         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3891         kvm_userspace_mem.memory_size = PAGE_SIZE;
3892         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3893         if (r)
3894                 goto out;
3895
3896         page = gfn_to_page(kvm, 0xfee00);
3897         if (is_error_page(page)) {
3898                 r = -EFAULT;
3899                 goto out;
3900         }
3901
3902         kvm->arch.apic_access_page = page;
3903 out:
3904         mutex_unlock(&kvm->slots_lock);
3905         return r;
3906 }
3907
3908 static int alloc_identity_pagetable(struct kvm *kvm)
3909 {
3910         struct page *page;
3911         struct kvm_userspace_memory_region kvm_userspace_mem;
3912         int r = 0;
3913
3914         mutex_lock(&kvm->slots_lock);
3915         if (kvm->arch.ept_identity_pagetable)
3916                 goto out;
3917         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3918         kvm_userspace_mem.flags = 0;
3919         kvm_userspace_mem.guest_phys_addr =
3920                 kvm->arch.ept_identity_map_addr;
3921         kvm_userspace_mem.memory_size = PAGE_SIZE;
3922         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3923         if (r)
3924                 goto out;
3925
3926         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3927         if (is_error_page(page)) {
3928                 r = -EFAULT;
3929                 goto out;
3930         }
3931
3932         kvm->arch.ept_identity_pagetable = page;
3933 out:
3934         mutex_unlock(&kvm->slots_lock);
3935         return r;
3936 }
3937
3938 static void allocate_vpid(struct vcpu_vmx *vmx)
3939 {
3940         int vpid;
3941
3942         vmx->vpid = 0;
3943         if (!enable_vpid)
3944                 return;
3945         spin_lock(&vmx_vpid_lock);
3946         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3947         if (vpid < VMX_NR_VPIDS) {
3948                 vmx->vpid = vpid;
3949                 __set_bit(vpid, vmx_vpid_bitmap);
3950         }
3951         spin_unlock(&vmx_vpid_lock);
3952 }
3953
3954 static void free_vpid(struct vcpu_vmx *vmx)
3955 {
3956         if (!enable_vpid)
3957                 return;
3958         spin_lock(&vmx_vpid_lock);
3959         if (vmx->vpid != 0)
3960                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3961         spin_unlock(&vmx_vpid_lock);
3962 }
3963
3964 #define MSR_TYPE_R      1
3965 #define MSR_TYPE_W      2
3966 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3967                                                 u32 msr, int type)
3968 {
3969         int f = sizeof(unsigned long);
3970
3971         if (!cpu_has_vmx_msr_bitmap())
3972                 return;
3973
3974         /*
3975          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3976          * have the write-low and read-high bitmap offsets the wrong way round.
3977          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3978          */
3979         if (msr <= 0x1fff) {
3980                 if (type & MSR_TYPE_R)
3981                         /* read-low */
3982                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3983
3984                 if (type & MSR_TYPE_W)
3985                         /* write-low */
3986                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3987
3988         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3989                 msr &= 0x1fff;
3990                 if (type & MSR_TYPE_R)
3991                         /* read-high */
3992                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3993
3994                 if (type & MSR_TYPE_W)
3995                         /* write-high */
3996                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3997
3998         }
3999 }
4000
4001 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4002                                                 u32 msr, int type)
4003 {
4004         int f = sizeof(unsigned long);
4005
4006         if (!cpu_has_vmx_msr_bitmap())
4007                 return;
4008
4009         /*
4010          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4011          * have the write-low and read-high bitmap offsets the wrong way round.
4012          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4013          */
4014         if (msr <= 0x1fff) {
4015                 if (type & MSR_TYPE_R)
4016                         /* read-low */
4017                         __set_bit(msr, msr_bitmap + 0x000 / f);
4018
4019                 if (type & MSR_TYPE_W)
4020                         /* write-low */
4021                         __set_bit(msr, msr_bitmap + 0x800 / f);
4022
4023         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4024                 msr &= 0x1fff;
4025                 if (type & MSR_TYPE_R)
4026                         /* read-high */
4027                         __set_bit(msr, msr_bitmap + 0x400 / f);
4028
4029                 if (type & MSR_TYPE_W)
4030                         /* write-high */
4031                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4032
4033         }
4034 }
4035
4036 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4037 {
4038         if (!longmode_only)
4039                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4040                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4041         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4042                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4043 }
4044
4045 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4046 {
4047         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4048                         msr, MSR_TYPE_R);
4049         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4050                         msr, MSR_TYPE_R);
4051 }
4052
4053 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4054 {
4055         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4056                         msr, MSR_TYPE_R);
4057         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4058                         msr, MSR_TYPE_R);
4059 }
4060
4061 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4062 {
4063         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4064                         msr, MSR_TYPE_W);
4065         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4066                         msr, MSR_TYPE_W);
4067 }
4068
4069 static int vmx_vm_has_apicv(struct kvm *kvm)
4070 {
4071         return enable_apicv && irqchip_in_kernel(kvm);
4072 }
4073
4074 /*
4075  * Send interrupt to vcpu via posted interrupt way.
4076  * 1. If target vcpu is running(non-root mode), send posted interrupt
4077  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4078  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4079  * interrupt from PIR in next vmentry.
4080  */
4081 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4082 {
4083         struct vcpu_vmx *vmx = to_vmx(vcpu);
4084         int r;
4085
4086         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4087                 return;
4088
4089         r = pi_test_and_set_on(&vmx->pi_desc);
4090         kvm_make_request(KVM_REQ_EVENT, vcpu);
4091 #ifdef CONFIG_SMP
4092         if (!r && (vcpu->mode == IN_GUEST_MODE))
4093                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4094                                 POSTED_INTR_VECTOR);
4095         else
4096 #endif
4097                 kvm_vcpu_kick(vcpu);
4098 }
4099
4100 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4101 {
4102         struct vcpu_vmx *vmx = to_vmx(vcpu);
4103
4104         if (!pi_test_and_clear_on(&vmx->pi_desc))
4105                 return;
4106
4107         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4108 }
4109
4110 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4111 {
4112         return;
4113 }
4114
4115 /*
4116  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4117  * will not change in the lifetime of the guest.
4118  * Note that host-state that does change is set elsewhere. E.g., host-state
4119  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4120  */
4121 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4122 {
4123         u32 low32, high32;
4124         unsigned long tmpl;
4125         struct desc_ptr dt;
4126
4127         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4128         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4129         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4130
4131         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4132 #ifdef CONFIG_X86_64
4133         /*
4134          * Load null selectors, so we can avoid reloading them in
4135          * __vmx_load_host_state(), in case userspace uses the null selectors
4136          * too (the expected case).
4137          */
4138         vmcs_write16(HOST_DS_SELECTOR, 0);
4139         vmcs_write16(HOST_ES_SELECTOR, 0);
4140 #else
4141         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4142         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4143 #endif
4144         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4145         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4146
4147         native_store_idt(&dt);
4148         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4149         vmx->host_idt_base = dt.address;
4150
4151         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4152
4153         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4154         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4155         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4156         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4157
4158         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4159                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4160                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4161         }
4162 }
4163
4164 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4165 {
4166         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4167         if (enable_ept)
4168                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4169         if (is_guest_mode(&vmx->vcpu))
4170                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4171                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4172         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4173 }
4174
4175 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4176 {
4177         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4178
4179         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4180                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4181         return pin_based_exec_ctrl;
4182 }
4183
4184 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4185 {
4186         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4187         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4188                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4189 #ifdef CONFIG_X86_64
4190                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4191                                 CPU_BASED_CR8_LOAD_EXITING;
4192 #endif
4193         }
4194         if (!enable_ept)
4195                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4196                                 CPU_BASED_CR3_LOAD_EXITING  |
4197                                 CPU_BASED_INVLPG_EXITING;
4198         return exec_control;
4199 }
4200
4201 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4202 {
4203         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4204         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4205                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4206         if (vmx->vpid == 0)
4207                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4208         if (!enable_ept) {
4209                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4210                 enable_unrestricted_guest = 0;
4211                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4212                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4213         }
4214         if (!enable_unrestricted_guest)
4215                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4216         if (!ple_gap)
4217                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4218         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4219                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4220                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4221         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4222         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4223            (handle_vmptrld).
4224            We can NOT enable shadow_vmcs here because we don't have yet
4225            a current VMCS12
4226         */
4227         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4228         return exec_control;
4229 }
4230
4231 static void ept_set_mmio_spte_mask(void)
4232 {
4233         /*
4234          * EPT Misconfigurations can be generated if the value of bits 2:0
4235          * of an EPT paging-structure entry is 110b (write/execute).
4236          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4237          * spte.
4238          */
4239         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4240 }
4241
4242 /*
4243  * Sets up the vmcs for emulated real mode.
4244  */
4245 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4246 {
4247 #ifdef CONFIG_X86_64
4248         unsigned long a;
4249 #endif
4250         int i;
4251
4252         /* I/O */
4253         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4254         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4255
4256         if (enable_shadow_vmcs) {
4257                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4258                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4259         }
4260         if (cpu_has_vmx_msr_bitmap())
4261                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4262
4263         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4264
4265         /* Control */
4266         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4267
4268         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4269
4270         if (cpu_has_secondary_exec_ctrls()) {
4271                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4272                                 vmx_secondary_exec_control(vmx));
4273         }
4274
4275         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4276                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4277                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4278                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4279                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4280
4281                 vmcs_write16(GUEST_INTR_STATUS, 0);
4282
4283                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4284                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4285         }
4286
4287         if (ple_gap) {
4288                 vmcs_write32(PLE_GAP, ple_gap);
4289                 vmcs_write32(PLE_WINDOW, ple_window);
4290         }
4291
4292         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4293         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4294         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4295
4296         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4297         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4298         vmx_set_constant_host_state(vmx);
4299 #ifdef CONFIG_X86_64
4300         rdmsrl(MSR_FS_BASE, a);
4301         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4302         rdmsrl(MSR_GS_BASE, a);
4303         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4304 #else
4305         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4306         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4307 #endif
4308
4309         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4310         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4311         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4312         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4313         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4314
4315         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4316                 u32 msr_low, msr_high;
4317                 u64 host_pat;
4318                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4319                 host_pat = msr_low | ((u64) msr_high << 32);
4320                 /* Write the default value follow host pat */
4321                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4322                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4323                 vmx->vcpu.arch.pat = host_pat;
4324         }
4325
4326         for (i = 0; i < NR_VMX_MSR; ++i) {
4327                 u32 index = vmx_msr_index[i];
4328                 u32 data_low, data_high;
4329                 int j = vmx->nmsrs;
4330
4331                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4332                         continue;
4333                 if (wrmsr_safe(index, data_low, data_high) < 0)
4334                         continue;
4335                 vmx->guest_msrs[j].index = i;
4336                 vmx->guest_msrs[j].data = 0;
4337                 vmx->guest_msrs[j].mask = -1ull;
4338                 ++vmx->nmsrs;
4339         }
4340
4341         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4342
4343         /* 22.2.1, 20.8.1 */
4344         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4345
4346         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4347         set_cr4_guest_host_mask(vmx);
4348
4349         return 0;
4350 }
4351
4352 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4353 {
4354         struct vcpu_vmx *vmx = to_vmx(vcpu);
4355         u64 msr;
4356
4357         vmx->rmode.vm86_active = 0;
4358
4359         vmx->soft_vnmi_blocked = 0;
4360
4361         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4362         kvm_set_cr8(&vmx->vcpu, 0);
4363         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4364         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4365                 msr |= MSR_IA32_APICBASE_BSP;
4366         kvm_set_apic_base(&vmx->vcpu, msr);
4367
4368         vmx_segment_cache_clear(vmx);
4369
4370         seg_setup(VCPU_SREG_CS);
4371         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4372         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4373
4374         seg_setup(VCPU_SREG_DS);
4375         seg_setup(VCPU_SREG_ES);
4376         seg_setup(VCPU_SREG_FS);
4377         seg_setup(VCPU_SREG_GS);
4378         seg_setup(VCPU_SREG_SS);
4379
4380         vmcs_write16(GUEST_TR_SELECTOR, 0);
4381         vmcs_writel(GUEST_TR_BASE, 0);
4382         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4383         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4384
4385         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4386         vmcs_writel(GUEST_LDTR_BASE, 0);
4387         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4388         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4389
4390         vmcs_write32(GUEST_SYSENTER_CS, 0);
4391         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4392         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4393
4394         vmcs_writel(GUEST_RFLAGS, 0x02);
4395         kvm_rip_write(vcpu, 0xfff0);
4396
4397         vmcs_writel(GUEST_GDTR_BASE, 0);
4398         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4399
4400         vmcs_writel(GUEST_IDTR_BASE, 0);
4401         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4402
4403         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4404         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4405         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4406
4407         /* Special registers */
4408         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4409
4410         setup_msrs(vmx);
4411
4412         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4413
4414         if (cpu_has_vmx_tpr_shadow()) {
4415                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4416                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4417                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4418                                      __pa(vmx->vcpu.arch.apic->regs));
4419                 vmcs_write32(TPR_THRESHOLD, 0);
4420         }
4421
4422         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4423                 vmcs_write64(APIC_ACCESS_ADDR,
4424                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4425
4426         if (vmx_vm_has_apicv(vcpu->kvm))
4427                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4428
4429         if (vmx->vpid != 0)
4430                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4431
4432         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4433         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4434         vmx_set_cr4(&vmx->vcpu, 0);
4435         vmx_set_efer(&vmx->vcpu, 0);
4436         vmx_fpu_activate(&vmx->vcpu);
4437         update_exception_bitmap(&vmx->vcpu);
4438
4439         vpid_sync_context(vmx);
4440 }
4441
4442 /*
4443  * In nested virtualization, check if L1 asked to exit on external interrupts.
4444  * For most existing hypervisors, this will always return true.
4445  */
4446 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4447 {
4448         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4449                 PIN_BASED_EXT_INTR_MASK;
4450 }
4451
4452 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4453 {
4454         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4455                 PIN_BASED_NMI_EXITING;
4456 }
4457
4458 static int enable_irq_window(struct kvm_vcpu *vcpu)
4459 {
4460         u32 cpu_based_vm_exec_control;
4461
4462         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4463                 /*
4464                  * We get here if vmx_interrupt_allowed() said we can't
4465                  * inject to L1 now because L2 must run. The caller will have
4466                  * to make L2 exit right after entry, so we can inject to L1
4467                  * more promptly.
4468                  */
4469                 return -EBUSY;
4470
4471         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4472         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4473         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4474         return 0;
4475 }
4476
4477 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4478 {
4479         u32 cpu_based_vm_exec_control;
4480
4481         if (!cpu_has_virtual_nmis())
4482                 return enable_irq_window(vcpu);
4483
4484         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4485                 return enable_irq_window(vcpu);
4486
4487         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4488         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4489         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4490         return 0;
4491 }
4492
4493 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4494 {
4495         struct vcpu_vmx *vmx = to_vmx(vcpu);
4496         uint32_t intr;
4497         int irq = vcpu->arch.interrupt.nr;
4498
4499         trace_kvm_inj_virq(irq);
4500
4501         ++vcpu->stat.irq_injections;
4502         if (vmx->rmode.vm86_active) {
4503                 int inc_eip = 0;
4504                 if (vcpu->arch.interrupt.soft)
4505                         inc_eip = vcpu->arch.event_exit_inst_len;
4506                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4507                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4508                 return;
4509         }
4510         intr = irq | INTR_INFO_VALID_MASK;
4511         if (vcpu->arch.interrupt.soft) {
4512                 intr |= INTR_TYPE_SOFT_INTR;
4513                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4514                              vmx->vcpu.arch.event_exit_inst_len);
4515         } else
4516                 intr |= INTR_TYPE_EXT_INTR;
4517         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4518 }
4519
4520 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4521 {
4522         struct vcpu_vmx *vmx = to_vmx(vcpu);
4523
4524         if (is_guest_mode(vcpu))
4525                 return;
4526
4527         if (!cpu_has_virtual_nmis()) {
4528                 /*
4529                  * Tracking the NMI-blocked state in software is built upon
4530                  * finding the next open IRQ window. This, in turn, depends on
4531                  * well-behaving guests: They have to keep IRQs disabled at
4532                  * least as long as the NMI handler runs. Otherwise we may
4533                  * cause NMI nesting, maybe breaking the guest. But as this is
4534                  * highly unlikely, we can live with the residual risk.
4535                  */
4536                 vmx->soft_vnmi_blocked = 1;
4537                 vmx->vnmi_blocked_time = 0;
4538         }
4539
4540         ++vcpu->stat.nmi_injections;
4541         vmx->nmi_known_unmasked = false;
4542         if (vmx->rmode.vm86_active) {
4543                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4544                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4545                 return;
4546         }
4547         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4548                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4549 }
4550
4551 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4552 {
4553         if (!cpu_has_virtual_nmis())
4554                 return to_vmx(vcpu)->soft_vnmi_blocked;
4555         if (to_vmx(vcpu)->nmi_known_unmasked)
4556                 return false;
4557         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4558 }
4559
4560 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4561 {
4562         struct vcpu_vmx *vmx = to_vmx(vcpu);
4563
4564         if (!cpu_has_virtual_nmis()) {
4565                 if (vmx->soft_vnmi_blocked != masked) {
4566                         vmx->soft_vnmi_blocked = masked;
4567                         vmx->vnmi_blocked_time = 0;
4568                 }
4569         } else {
4570                 vmx->nmi_known_unmasked = !masked;
4571                 if (masked)
4572                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4573                                       GUEST_INTR_STATE_NMI);
4574                 else
4575                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4576                                         GUEST_INTR_STATE_NMI);
4577         }
4578 }
4579
4580 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4581 {
4582         if (is_guest_mode(vcpu)) {
4583                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4584
4585                 if (to_vmx(vcpu)->nested.nested_run_pending)
4586                         return 0;
4587                 if (nested_exit_on_nmi(vcpu)) {
4588                         nested_vmx_vmexit(vcpu);
4589                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4590                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4591                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4592                         /*
4593                          * The NMI-triggered VM exit counts as injection:
4594                          * clear this one and block further NMIs.
4595                          */
4596                         vcpu->arch.nmi_pending = 0;
4597                         vmx_set_nmi_mask(vcpu, true);
4598                         return 0;
4599                 }
4600         }
4601
4602         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4603                 return 0;
4604
4605         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4606                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4607                    | GUEST_INTR_STATE_NMI));
4608 }
4609
4610 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4611 {
4612         if (is_guest_mode(vcpu)) {
4613                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4614
4615                 if (to_vmx(vcpu)->nested.nested_run_pending)
4616                         return 0;
4617                 if (nested_exit_on_intr(vcpu)) {
4618                         nested_vmx_vmexit(vcpu);
4619                         vmcs12->vm_exit_reason =
4620                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4621                         vmcs12->vm_exit_intr_info = 0;
4622                         /*
4623                          * fall through to normal code, but now in L1, not L2
4624                          */
4625                 }
4626         }
4627
4628         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4629                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4630                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4631 }
4632
4633 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4634 {
4635         int ret;
4636         struct kvm_userspace_memory_region tss_mem = {
4637                 .slot = TSS_PRIVATE_MEMSLOT,
4638                 .guest_phys_addr = addr,
4639                 .memory_size = PAGE_SIZE * 3,
4640                 .flags = 0,
4641         };
4642
4643         ret = kvm_set_memory_region(kvm, &tss_mem);
4644         if (ret)
4645                 return ret;
4646         kvm->arch.tss_addr = addr;
4647         if (!init_rmode_tss(kvm))
4648                 return  -ENOMEM;
4649
4650         return 0;
4651 }
4652
4653 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4654 {
4655         switch (vec) {
4656         case BP_VECTOR:
4657                 /*
4658                  * Update instruction length as we may reinject the exception
4659                  * from user space while in guest debugging mode.
4660                  */
4661                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4662                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4663                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4664                         return false;
4665                 /* fall through */
4666         case DB_VECTOR:
4667                 if (vcpu->guest_debug &
4668                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4669                         return false;
4670                 /* fall through */
4671         case DE_VECTOR:
4672         case OF_VECTOR:
4673         case BR_VECTOR:
4674         case UD_VECTOR:
4675         case DF_VECTOR:
4676         case SS_VECTOR:
4677         case GP_VECTOR:
4678         case MF_VECTOR:
4679                 return true;
4680         break;
4681         }
4682         return false;
4683 }
4684
4685 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4686                                   int vec, u32 err_code)
4687 {
4688         /*
4689          * Instruction with address size override prefix opcode 0x67
4690          * Cause the #SS fault with 0 error code in VM86 mode.
4691          */
4692         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4693                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4694                         if (vcpu->arch.halt_request) {
4695                                 vcpu->arch.halt_request = 0;
4696                                 return kvm_emulate_halt(vcpu);
4697                         }
4698                         return 1;
4699                 }
4700                 return 0;
4701         }
4702
4703         /*
4704          * Forward all other exceptions that are valid in real mode.
4705          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4706          *        the required debugging infrastructure rework.
4707          */
4708         kvm_queue_exception(vcpu, vec);
4709         return 1;
4710 }
4711
4712 /*
4713  * Trigger machine check on the host. We assume all the MSRs are already set up
4714  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4715  * We pass a fake environment to the machine check handler because we want
4716  * the guest to be always treated like user space, no matter what context
4717  * it used internally.
4718  */
4719 static void kvm_machine_check(void)
4720 {
4721 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4722         struct pt_regs regs = {
4723                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4724                 .flags = X86_EFLAGS_IF,
4725         };
4726
4727         do_machine_check(&regs, 0);
4728 #endif
4729 }
4730
4731 static int handle_machine_check(struct kvm_vcpu *vcpu)
4732 {
4733         /* already handled by vcpu_run */
4734         return 1;
4735 }
4736
4737 static int handle_exception(struct kvm_vcpu *vcpu)
4738 {
4739         struct vcpu_vmx *vmx = to_vmx(vcpu);
4740         struct kvm_run *kvm_run = vcpu->run;
4741         u32 intr_info, ex_no, error_code;
4742         unsigned long cr2, rip, dr6;
4743         u32 vect_info;
4744         enum emulation_result er;
4745
4746         vect_info = vmx->idt_vectoring_info;
4747         intr_info = vmx->exit_intr_info;
4748
4749         if (is_machine_check(intr_info))
4750                 return handle_machine_check(vcpu);
4751
4752         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4753                 return 1;  /* already handled by vmx_vcpu_run() */
4754
4755         if (is_no_device(intr_info)) {
4756                 vmx_fpu_activate(vcpu);
4757                 return 1;
4758         }
4759
4760         if (is_invalid_opcode(intr_info)) {
4761                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4762                 if (er != EMULATE_DONE)
4763                         kvm_queue_exception(vcpu, UD_VECTOR);
4764                 return 1;
4765         }
4766
4767         error_code = 0;
4768         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4769                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4770
4771         /*
4772          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4773          * MMIO, it is better to report an internal error.
4774          * See the comments in vmx_handle_exit.
4775          */
4776         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4777             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4778                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4779                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4780                 vcpu->run->internal.ndata = 2;
4781                 vcpu->run->internal.data[0] = vect_info;
4782                 vcpu->run->internal.data[1] = intr_info;
4783                 return 0;
4784         }
4785
4786         if (is_page_fault(intr_info)) {
4787                 /* EPT won't cause page fault directly */
4788                 BUG_ON(enable_ept);
4789                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4790                 trace_kvm_page_fault(cr2, error_code);
4791
4792                 if (kvm_event_needs_reinjection(vcpu))
4793                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4794                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4795         }
4796
4797         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4798
4799         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4800                 return handle_rmode_exception(vcpu, ex_no, error_code);
4801
4802         switch (ex_no) {
4803         case DB_VECTOR:
4804                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4805                 if (!(vcpu->guest_debug &
4806                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4807                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4808                         kvm_queue_exception(vcpu, DB_VECTOR);
4809                         return 1;
4810                 }
4811                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4812                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4813                 /* fall through */
4814         case BP_VECTOR:
4815                 /*
4816                  * Update instruction length as we may reinject #BP from
4817                  * user space while in guest debugging mode. Reading it for
4818                  * #DB as well causes no harm, it is not used in that case.
4819                  */
4820                 vmx->vcpu.arch.event_exit_inst_len =
4821                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4822                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4823                 rip = kvm_rip_read(vcpu);
4824                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4825                 kvm_run->debug.arch.exception = ex_no;
4826                 break;
4827         default:
4828                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4829                 kvm_run->ex.exception = ex_no;
4830                 kvm_run->ex.error_code = error_code;
4831                 break;
4832         }
4833         return 0;
4834 }
4835
4836 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4837 {
4838         ++vcpu->stat.irq_exits;
4839         return 1;
4840 }
4841
4842 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4843 {
4844         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4845         return 0;
4846 }
4847
4848 static int handle_io(struct kvm_vcpu *vcpu)
4849 {
4850         unsigned long exit_qualification;
4851         int size, in, string;
4852         unsigned port;
4853
4854         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4855         string = (exit_qualification & 16) != 0;
4856         in = (exit_qualification & 8) != 0;
4857
4858         ++vcpu->stat.io_exits;
4859
4860         if (string || in)
4861                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4862
4863         port = exit_qualification >> 16;
4864         size = (exit_qualification & 7) + 1;
4865         skip_emulated_instruction(vcpu);
4866
4867         return kvm_fast_pio_out(vcpu, size, port);
4868 }
4869
4870 static void
4871 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4872 {
4873         /*
4874          * Patch in the VMCALL instruction:
4875          */
4876         hypercall[0] = 0x0f;
4877         hypercall[1] = 0x01;
4878         hypercall[2] = 0xc1;
4879 }
4880
4881 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4882 {
4883         unsigned long always_on = VMXON_CR0_ALWAYSON;
4884
4885         if (nested_vmx_secondary_ctls_high &
4886                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4887             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4888                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4889         return (val & always_on) == always_on;
4890 }
4891
4892 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4893 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4894 {
4895         if (is_guest_mode(vcpu)) {
4896                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4897                 unsigned long orig_val = val;
4898
4899                 /*
4900                  * We get here when L2 changed cr0 in a way that did not change
4901                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4902                  * but did change L0 shadowed bits. So we first calculate the
4903                  * effective cr0 value that L1 would like to write into the
4904                  * hardware. It consists of the L2-owned bits from the new
4905                  * value combined with the L1-owned bits from L1's guest_cr0.
4906                  */
4907                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4908                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4909
4910                 if (!nested_cr0_valid(vmcs12, val))
4911                         return 1;
4912
4913                 if (kvm_set_cr0(vcpu, val))
4914                         return 1;
4915                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4916                 return 0;
4917         } else {
4918                 if (to_vmx(vcpu)->nested.vmxon &&
4919                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4920                         return 1;
4921                 return kvm_set_cr0(vcpu, val);
4922         }
4923 }
4924
4925 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4926 {
4927         if (is_guest_mode(vcpu)) {
4928                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4929                 unsigned long orig_val = val;
4930
4931                 /* analogously to handle_set_cr0 */
4932                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4933                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4934                 if (kvm_set_cr4(vcpu, val))
4935                         return 1;
4936                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4937                 return 0;
4938         } else
4939                 return kvm_set_cr4(vcpu, val);
4940 }
4941
4942 /* called to set cr0 as approriate for clts instruction exit. */
4943 static void handle_clts(struct kvm_vcpu *vcpu)
4944 {
4945         if (is_guest_mode(vcpu)) {
4946                 /*
4947                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4948                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4949                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4950                  */
4951                 vmcs_writel(CR0_READ_SHADOW,
4952                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4953                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4954         } else
4955                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4956 }
4957
4958 static int handle_cr(struct kvm_vcpu *vcpu)
4959 {
4960         unsigned long exit_qualification, val;
4961         int cr;
4962         int reg;
4963         int err;
4964
4965         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4966         cr = exit_qualification & 15;
4967         reg = (exit_qualification >> 8) & 15;
4968         switch ((exit_qualification >> 4) & 3) {
4969         case 0: /* mov to cr */
4970                 val = kvm_register_read(vcpu, reg);
4971                 trace_kvm_cr_write(cr, val);
4972                 switch (cr) {
4973                 case 0:
4974                         err = handle_set_cr0(vcpu, val);
4975                         kvm_complete_insn_gp(vcpu, err);
4976                         return 1;
4977                 case 3:
4978                         err = kvm_set_cr3(vcpu, val);
4979                         kvm_complete_insn_gp(vcpu, err);
4980                         return 1;
4981                 case 4:
4982                         err = handle_set_cr4(vcpu, val);
4983                         kvm_complete_insn_gp(vcpu, err);
4984                         return 1;
4985                 case 8: {
4986                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4987                                 u8 cr8 = kvm_register_read(vcpu, reg);
4988                                 err = kvm_set_cr8(vcpu, cr8);
4989                                 kvm_complete_insn_gp(vcpu, err);
4990                                 if (irqchip_in_kernel(vcpu->kvm))
4991                                         return 1;
4992                                 if (cr8_prev <= cr8)
4993                                         return 1;
4994                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4995                                 return 0;
4996                         }
4997                 }
4998                 break;
4999         case 2: /* clts */
5000                 handle_clts(vcpu);
5001                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5002                 skip_emulated_instruction(vcpu);
5003                 vmx_fpu_activate(vcpu);
5004                 return 1;
5005         case 1: /*mov from cr*/
5006                 switch (cr) {
5007                 case 3:
5008                         val = kvm_read_cr3(vcpu);
5009                         kvm_register_write(vcpu, reg, val);
5010                         trace_kvm_cr_read(cr, val);
5011                         skip_emulated_instruction(vcpu);
5012                         return 1;
5013                 case 8:
5014                         val = kvm_get_cr8(vcpu);
5015                         kvm_register_write(vcpu, reg, val);
5016                         trace_kvm_cr_read(cr, val);
5017                         skip_emulated_instruction(vcpu);
5018                         return 1;
5019                 }
5020                 break;
5021         case 3: /* lmsw */
5022                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5023                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5024                 kvm_lmsw(vcpu, val);
5025
5026                 skip_emulated_instruction(vcpu);
5027                 return 1;
5028         default:
5029                 break;
5030         }
5031         vcpu->run->exit_reason = 0;
5032         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5033                (int)(exit_qualification >> 4) & 3, cr);
5034         return 0;
5035 }
5036
5037 static int handle_dr(struct kvm_vcpu *vcpu)
5038 {
5039         unsigned long exit_qualification;
5040         int dr, reg;
5041
5042         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5043         if (!kvm_require_cpl(vcpu, 0))
5044                 return 1;
5045         dr = vmcs_readl(GUEST_DR7);
5046         if (dr & DR7_GD) {
5047                 /*
5048                  * As the vm-exit takes precedence over the debug trap, we
5049                  * need to emulate the latter, either for the host or the
5050                  * guest debugging itself.
5051                  */
5052                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5053                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5054                         vcpu->run->debug.arch.dr7 = dr;
5055                         vcpu->run->debug.arch.pc =
5056                                 vmcs_readl(GUEST_CS_BASE) +
5057                                 vmcs_readl(GUEST_RIP);
5058                         vcpu->run->debug.arch.exception = DB_VECTOR;
5059                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5060                         return 0;
5061                 } else {
5062                         vcpu->arch.dr7 &= ~DR7_GD;
5063                         vcpu->arch.dr6 |= DR6_BD;
5064                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5065                         kvm_queue_exception(vcpu, DB_VECTOR);
5066                         return 1;
5067                 }
5068         }
5069
5070         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5071         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5072         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5073         if (exit_qualification & TYPE_MOV_FROM_DR) {
5074                 unsigned long val;
5075                 if (!kvm_get_dr(vcpu, dr, &val))
5076                         kvm_register_write(vcpu, reg, val);
5077         } else
5078                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5079         skip_emulated_instruction(vcpu);
5080         return 1;
5081 }
5082
5083 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5084 {
5085         vmcs_writel(GUEST_DR7, val);
5086 }
5087
5088 static int handle_cpuid(struct kvm_vcpu *vcpu)
5089 {
5090         kvm_emulate_cpuid(vcpu);
5091         return 1;
5092 }
5093
5094 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5095 {
5096         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5097         u64 data;
5098
5099         if (vmx_get_msr(vcpu, ecx, &data)) {
5100                 trace_kvm_msr_read_ex(ecx);
5101                 kvm_inject_gp(vcpu, 0);
5102                 return 1;
5103         }
5104
5105         trace_kvm_msr_read(ecx, data);
5106
5107         /* FIXME: handling of bits 32:63 of rax, rdx */
5108         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5109         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5110         skip_emulated_instruction(vcpu);
5111         return 1;
5112 }
5113
5114 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5115 {
5116         struct msr_data msr;
5117         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5118         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5119                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5120
5121         msr.data = data;
5122         msr.index = ecx;
5123         msr.host_initiated = false;
5124         if (vmx_set_msr(vcpu, &msr) != 0) {
5125                 trace_kvm_msr_write_ex(ecx, data);
5126                 kvm_inject_gp(vcpu, 0);
5127                 return 1;
5128         }
5129
5130         trace_kvm_msr_write(ecx, data);
5131         skip_emulated_instruction(vcpu);
5132         return 1;
5133 }
5134
5135 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5136 {
5137         kvm_make_request(KVM_REQ_EVENT, vcpu);
5138         return 1;
5139 }
5140
5141 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5142 {
5143         u32 cpu_based_vm_exec_control;
5144
5145         /* clear pending irq */
5146         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5147         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5148         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5149
5150         kvm_make_request(KVM_REQ_EVENT, vcpu);
5151
5152         ++vcpu->stat.irq_window_exits;
5153
5154         /*
5155          * If the user space waits to inject interrupts, exit as soon as
5156          * possible
5157          */
5158         if (!irqchip_in_kernel(vcpu->kvm) &&
5159             vcpu->run->request_interrupt_window &&
5160             !kvm_cpu_has_interrupt(vcpu)) {
5161                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5162                 return 0;
5163         }
5164         return 1;
5165 }
5166
5167 static int handle_halt(struct kvm_vcpu *vcpu)
5168 {
5169         skip_emulated_instruction(vcpu);
5170         return kvm_emulate_halt(vcpu);
5171 }
5172
5173 static int handle_vmcall(struct kvm_vcpu *vcpu)
5174 {
5175         skip_emulated_instruction(vcpu);
5176         kvm_emulate_hypercall(vcpu);
5177         return 1;
5178 }
5179
5180 static int handle_invd(struct kvm_vcpu *vcpu)
5181 {
5182         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5183 }
5184
5185 static int handle_invlpg(struct kvm_vcpu *vcpu)
5186 {
5187         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5188
5189         kvm_mmu_invlpg(vcpu, exit_qualification);
5190         skip_emulated_instruction(vcpu);
5191         return 1;
5192 }
5193
5194 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5195 {
5196         int err;
5197
5198         err = kvm_rdpmc(vcpu);
5199         kvm_complete_insn_gp(vcpu, err);
5200
5201         return 1;
5202 }
5203
5204 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5205 {
5206         skip_emulated_instruction(vcpu);
5207         kvm_emulate_wbinvd(vcpu);
5208         return 1;
5209 }
5210
5211 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5212 {
5213         u64 new_bv = kvm_read_edx_eax(vcpu);
5214         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5215
5216         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5217                 skip_emulated_instruction(vcpu);
5218         return 1;
5219 }
5220
5221 static int handle_apic_access(struct kvm_vcpu *vcpu)
5222 {
5223         if (likely(fasteoi)) {
5224                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5225                 int access_type, offset;
5226
5227                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5228                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5229                 /*
5230                  * Sane guest uses MOV to write EOI, with written value
5231                  * not cared. So make a short-circuit here by avoiding
5232                  * heavy instruction emulation.
5233                  */
5234                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5235                     (offset == APIC_EOI)) {
5236                         kvm_lapic_set_eoi(vcpu);
5237                         skip_emulated_instruction(vcpu);
5238                         return 1;
5239                 }
5240         }
5241         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5242 }
5243
5244 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5245 {
5246         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5247         int vector = exit_qualification & 0xff;
5248
5249         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5250         kvm_apic_set_eoi_accelerated(vcpu, vector);
5251         return 1;
5252 }
5253
5254 static int handle_apic_write(struct kvm_vcpu *vcpu)
5255 {
5256         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5257         u32 offset = exit_qualification & 0xfff;
5258
5259         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5260         kvm_apic_write_nodecode(vcpu, offset);
5261         return 1;
5262 }
5263
5264 static int handle_task_switch(struct kvm_vcpu *vcpu)
5265 {
5266         struct vcpu_vmx *vmx = to_vmx(vcpu);
5267         unsigned long exit_qualification;
5268         bool has_error_code = false;
5269         u32 error_code = 0;
5270         u16 tss_selector;
5271         int reason, type, idt_v, idt_index;
5272
5273         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5274         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5275         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5276
5277         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5278
5279         reason = (u32)exit_qualification >> 30;
5280         if (reason == TASK_SWITCH_GATE && idt_v) {
5281                 switch (type) {
5282                 case INTR_TYPE_NMI_INTR:
5283                         vcpu->arch.nmi_injected = false;
5284                         vmx_set_nmi_mask(vcpu, true);
5285                         break;
5286                 case INTR_TYPE_EXT_INTR:
5287                 case INTR_TYPE_SOFT_INTR:
5288                         kvm_clear_interrupt_queue(vcpu);
5289                         break;
5290                 case INTR_TYPE_HARD_EXCEPTION:
5291                         if (vmx->idt_vectoring_info &
5292                             VECTORING_INFO_DELIVER_CODE_MASK) {
5293                                 has_error_code = true;
5294                                 error_code =
5295                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5296                         }
5297                         /* fall through */
5298                 case INTR_TYPE_SOFT_EXCEPTION:
5299                         kvm_clear_exception_queue(vcpu);
5300                         break;
5301                 default:
5302                         break;
5303                 }
5304         }
5305         tss_selector = exit_qualification;
5306
5307         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5308                        type != INTR_TYPE_EXT_INTR &&
5309                        type != INTR_TYPE_NMI_INTR))
5310                 skip_emulated_instruction(vcpu);
5311
5312         if (kvm_task_switch(vcpu, tss_selector,
5313                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5314                             has_error_code, error_code) == EMULATE_FAIL) {
5315                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5316                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5317                 vcpu->run->internal.ndata = 0;
5318                 return 0;
5319         }
5320
5321         /* clear all local breakpoint enable flags */
5322         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5323
5324         /*
5325          * TODO: What about debug traps on tss switch?
5326          *       Are we supposed to inject them and update dr6?
5327          */
5328
5329         return 1;
5330 }
5331
5332 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5333 {
5334         unsigned long exit_qualification;
5335         gpa_t gpa;
5336         u32 error_code;
5337         int gla_validity;
5338
5339         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5340
5341         gla_validity = (exit_qualification >> 7) & 0x3;
5342         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5343                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5344                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5345                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5346                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5347                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5348                         (long unsigned int)exit_qualification);
5349                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5350                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5351                 return 0;
5352         }
5353
5354         /*
5355          * EPT violation happened while executing iret from NMI,
5356          * "blocked by NMI" bit has to be set before next VM entry.
5357          * There are errata that may cause this bit to not be set:
5358          * AAK134, BY25.
5359          */
5360         if (exit_qualification & INTR_INFO_UNBLOCK_NMI)
5361                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5362
5363         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5364         trace_kvm_page_fault(gpa, exit_qualification);
5365
5366         /* It is a write fault? */
5367         error_code = exit_qualification & (1U << 1);
5368         /* It is a fetch fault? */
5369         error_code |= (exit_qualification & (1U << 2)) << 2;
5370         /* ept page table is present? */
5371         error_code |= (exit_qualification >> 3) & 0x1;
5372
5373         vcpu->arch.exit_qualification = exit_qualification;
5374
5375         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5376 }
5377
5378 static u64 ept_rsvd_mask(u64 spte, int level)
5379 {
5380         int i;
5381         u64 mask = 0;
5382
5383         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5384                 mask |= (1ULL << i);
5385
5386         if (level > 2)
5387                 /* bits 7:3 reserved */
5388                 mask |= 0xf8;
5389         else if (level == 2) {
5390                 if (spte & (1ULL << 7))
5391                         /* 2MB ref, bits 20:12 reserved */
5392                         mask |= 0x1ff000;
5393                 else
5394                         /* bits 6:3 reserved */
5395                         mask |= 0x78;
5396         }
5397
5398         return mask;
5399 }
5400
5401 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5402                                        int level)
5403 {
5404         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5405
5406         /* 010b (write-only) */
5407         WARN_ON((spte & 0x7) == 0x2);
5408
5409         /* 110b (write/execute) */
5410         WARN_ON((spte & 0x7) == 0x6);
5411
5412         /* 100b (execute-only) and value not supported by logical processor */
5413         if (!cpu_has_vmx_ept_execute_only())
5414                 WARN_ON((spte & 0x7) == 0x4);
5415
5416         /* not 000b */
5417         if ((spte & 0x7)) {
5418                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5419
5420                 if (rsvd_bits != 0) {
5421                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5422                                          __func__, rsvd_bits);
5423                         WARN_ON(1);
5424                 }
5425
5426                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5427                         u64 ept_mem_type = (spte & 0x38) >> 3;
5428
5429                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5430                             ept_mem_type == 7) {
5431                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5432                                                 __func__, ept_mem_type);
5433                                 WARN_ON(1);
5434                         }
5435                 }
5436         }
5437 }
5438
5439 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5440 {
5441         u64 sptes[4];
5442         int nr_sptes, i, ret;
5443         gpa_t gpa;
5444
5445         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5446
5447         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5448         if (likely(ret == RET_MMIO_PF_EMULATE))
5449                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5450                                               EMULATE_DONE;
5451
5452         if (unlikely(ret == RET_MMIO_PF_INVALID))
5453                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5454
5455         if (unlikely(ret == RET_MMIO_PF_RETRY))
5456                 return 1;
5457
5458         /* It is the real ept misconfig */
5459         printk(KERN_ERR "EPT: Misconfiguration.\n");
5460         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5461
5462         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5463
5464         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5465                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5466
5467         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5468         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5469
5470         return 0;
5471 }
5472
5473 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5474 {
5475         u32 cpu_based_vm_exec_control;
5476
5477         /* clear pending NMI */
5478         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5479         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5480         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5481         ++vcpu->stat.nmi_window_exits;
5482         kvm_make_request(KVM_REQ_EVENT, vcpu);
5483
5484         return 1;
5485 }
5486
5487 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5488 {
5489         struct vcpu_vmx *vmx = to_vmx(vcpu);
5490         enum emulation_result err = EMULATE_DONE;
5491         int ret = 1;
5492         u32 cpu_exec_ctrl;
5493         bool intr_window_requested;
5494         unsigned count = 130;
5495
5496         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5497         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5498
5499         while (!guest_state_valid(vcpu) && count-- != 0) {
5500                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5501                         return handle_interrupt_window(&vmx->vcpu);
5502
5503                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5504                         return 1;
5505
5506                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5507
5508                 if (err == EMULATE_USER_EXIT) {
5509                         ++vcpu->stat.mmio_exits;
5510                         ret = 0;
5511                         goto out;
5512                 }
5513
5514                 if (err != EMULATE_DONE) {
5515                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5516                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5517                         vcpu->run->internal.ndata = 0;
5518                         return 0;
5519                 }
5520
5521                 if (vcpu->arch.halt_request) {
5522                         vcpu->arch.halt_request = 0;
5523                         ret = kvm_emulate_halt(vcpu);
5524                         goto out;
5525                 }
5526
5527                 if (signal_pending(current))
5528                         goto out;
5529                 if (need_resched())
5530                         schedule();
5531         }
5532
5533         vmx->emulation_required = emulation_required(vcpu);
5534 out:
5535         return ret;
5536 }
5537
5538 /*
5539  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5540  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5541  */
5542 static int handle_pause(struct kvm_vcpu *vcpu)
5543 {
5544         skip_emulated_instruction(vcpu);
5545         kvm_vcpu_on_spin(vcpu);
5546
5547         return 1;
5548 }
5549
5550 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5551 {
5552         kvm_queue_exception(vcpu, UD_VECTOR);
5553         return 1;
5554 }
5555
5556 /*
5557  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5558  * We could reuse a single VMCS for all the L2 guests, but we also want the
5559  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5560  * allows keeping them loaded on the processor, and in the future will allow
5561  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5562  * every entry if they never change.
5563  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5564  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5565  *
5566  * The following functions allocate and free a vmcs02 in this pool.
5567  */
5568
5569 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5570 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5571 {
5572         struct vmcs02_list *item;
5573         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5574                 if (item->vmptr == vmx->nested.current_vmptr) {
5575                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5576                         return &item->vmcs02;
5577                 }
5578
5579         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5580                 /* Recycle the least recently used VMCS. */
5581                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5582                         struct vmcs02_list, list);
5583                 item->vmptr = vmx->nested.current_vmptr;
5584                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5585                 return &item->vmcs02;
5586         }
5587
5588         /* Create a new VMCS */
5589         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5590         if (!item)
5591                 return NULL;
5592         item->vmcs02.vmcs = alloc_vmcs();
5593         if (!item->vmcs02.vmcs) {
5594                 kfree(item);
5595                 return NULL;
5596         }
5597         loaded_vmcs_init(&item->vmcs02);
5598         item->vmptr = vmx->nested.current_vmptr;
5599         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5600         vmx->nested.vmcs02_num++;
5601         return &item->vmcs02;
5602 }
5603
5604 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5605 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5606 {
5607         struct vmcs02_list *item;
5608         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5609                 if (item->vmptr == vmptr) {
5610                         free_loaded_vmcs(&item->vmcs02);
5611                         list_del(&item->list);
5612                         kfree(item);
5613                         vmx->nested.vmcs02_num--;
5614                         return;
5615                 }
5616 }
5617
5618 /*
5619  * Free all VMCSs saved for this vcpu, except the one pointed by
5620  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5621  * currently used, if running L2), and vmcs01 when running L2.
5622  */
5623 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5624 {
5625         struct vmcs02_list *item, *n;
5626         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5627                 if (vmx->loaded_vmcs != &item->vmcs02)
5628                         free_loaded_vmcs(&item->vmcs02);
5629                 list_del(&item->list);
5630                 kfree(item);
5631         }
5632         vmx->nested.vmcs02_num = 0;
5633
5634         if (vmx->loaded_vmcs != &vmx->vmcs01)
5635                 free_loaded_vmcs(&vmx->vmcs01);
5636 }
5637
5638 /*
5639  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5640  * set the success or error code of an emulated VMX instruction, as specified
5641  * by Vol 2B, VMX Instruction Reference, "Conventions".
5642  */
5643 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5644 {
5645         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5646                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5647                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5648 }
5649
5650 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5651 {
5652         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5653                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5654                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5655                         | X86_EFLAGS_CF);
5656 }
5657
5658 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5659                                         u32 vm_instruction_error)
5660 {
5661         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5662                 /*
5663                  * failValid writes the error number to the current VMCS, which
5664                  * can't be done there isn't a current VMCS.
5665                  */
5666                 nested_vmx_failInvalid(vcpu);
5667                 return;
5668         }
5669         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5670                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5671                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5672                         | X86_EFLAGS_ZF);
5673         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5674         /*
5675          * We don't need to force a shadow sync because
5676          * VM_INSTRUCTION_ERROR is not shadowed
5677          */
5678 }
5679
5680 /*
5681  * Emulate the VMXON instruction.
5682  * Currently, we just remember that VMX is active, and do not save or even
5683  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5684  * do not currently need to store anything in that guest-allocated memory
5685  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5686  * argument is different from the VMXON pointer (which the spec says they do).
5687  */
5688 static int handle_vmon(struct kvm_vcpu *vcpu)
5689 {
5690         struct kvm_segment cs;
5691         struct vcpu_vmx *vmx = to_vmx(vcpu);
5692         struct vmcs *shadow_vmcs;
5693         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5694                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5695
5696         /* The Intel VMX Instruction Reference lists a bunch of bits that
5697          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5698          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5699          * Otherwise, we should fail with #UD. We test these now:
5700          */
5701         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5702             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5703             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5704                 kvm_queue_exception(vcpu, UD_VECTOR);
5705                 return 1;
5706         }
5707
5708         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5709         if (is_long_mode(vcpu) && !cs.l) {
5710                 kvm_queue_exception(vcpu, UD_VECTOR);
5711                 return 1;
5712         }
5713
5714         if (vmx_get_cpl(vcpu)) {
5715                 kvm_inject_gp(vcpu, 0);
5716                 return 1;
5717         }
5718         if (vmx->nested.vmxon) {
5719                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5720                 skip_emulated_instruction(vcpu);
5721                 return 1;
5722         }
5723
5724         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5725                         != VMXON_NEEDED_FEATURES) {
5726                 kvm_inject_gp(vcpu, 0);
5727                 return 1;
5728         }
5729
5730         if (enable_shadow_vmcs) {
5731                 shadow_vmcs = alloc_vmcs();
5732                 if (!shadow_vmcs)
5733                         return -ENOMEM;
5734                 /* mark vmcs as shadow */
5735                 shadow_vmcs->revision_id |= (1u << 31);
5736                 /* init shadow vmcs */
5737                 vmcs_clear(shadow_vmcs);
5738                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5739         }
5740
5741         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5742         vmx->nested.vmcs02_num = 0;
5743
5744         vmx->nested.vmxon = true;
5745
5746         skip_emulated_instruction(vcpu);
5747         nested_vmx_succeed(vcpu);
5748         return 1;
5749 }
5750
5751 /*
5752  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5753  * for running VMX instructions (except VMXON, whose prerequisites are
5754  * slightly different). It also specifies what exception to inject otherwise.
5755  */
5756 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5757 {
5758         struct kvm_segment cs;
5759         struct vcpu_vmx *vmx = to_vmx(vcpu);
5760
5761         if (!vmx->nested.vmxon) {
5762                 kvm_queue_exception(vcpu, UD_VECTOR);
5763                 return 0;
5764         }
5765
5766         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5767         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5768             (is_long_mode(vcpu) && !cs.l)) {
5769                 kvm_queue_exception(vcpu, UD_VECTOR);
5770                 return 0;
5771         }
5772
5773         if (vmx_get_cpl(vcpu)) {
5774                 kvm_inject_gp(vcpu, 0);
5775                 return 0;
5776         }
5777
5778         return 1;
5779 }
5780
5781 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5782 {
5783         u32 exec_control;
5784         if (enable_shadow_vmcs) {
5785                 if (vmx->nested.current_vmcs12 != NULL) {
5786                         /* copy to memory all shadowed fields in case
5787                            they were modified */
5788                         copy_shadow_to_vmcs12(vmx);
5789                         vmx->nested.sync_shadow_vmcs = false;
5790                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5791                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5792                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5793                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5794                 }
5795         }
5796         kunmap(vmx->nested.current_vmcs12_page);
5797         nested_release_page(vmx->nested.current_vmcs12_page);
5798 }
5799
5800 /*
5801  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5802  * just stops using VMX.
5803  */
5804 static void free_nested(struct vcpu_vmx *vmx)
5805 {
5806         if (!vmx->nested.vmxon)
5807                 return;
5808         vmx->nested.vmxon = false;
5809         if (vmx->nested.current_vmptr != -1ull) {
5810                 nested_release_vmcs12(vmx);
5811                 vmx->nested.current_vmptr = -1ull;
5812                 vmx->nested.current_vmcs12 = NULL;
5813         }
5814         if (enable_shadow_vmcs)
5815                 free_vmcs(vmx->nested.current_shadow_vmcs);
5816         /* Unpin physical memory we referred to in current vmcs02 */
5817         if (vmx->nested.apic_access_page) {
5818                 nested_release_page(vmx->nested.apic_access_page);
5819                 vmx->nested.apic_access_page = 0;
5820         }
5821
5822         nested_free_all_saved_vmcss(vmx);
5823 }
5824
5825 /* Emulate the VMXOFF instruction */
5826 static int handle_vmoff(struct kvm_vcpu *vcpu)
5827 {
5828         if (!nested_vmx_check_permission(vcpu))
5829                 return 1;
5830         free_nested(to_vmx(vcpu));
5831         skip_emulated_instruction(vcpu);
5832         nested_vmx_succeed(vcpu);
5833         return 1;
5834 }
5835
5836 /*
5837  * Decode the memory-address operand of a vmx instruction, as recorded on an
5838  * exit caused by such an instruction (run by a guest hypervisor).
5839  * On success, returns 0. When the operand is invalid, returns 1 and throws
5840  * #UD or #GP.
5841  */
5842 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5843                                  unsigned long exit_qualification,
5844                                  u32 vmx_instruction_info, gva_t *ret)
5845 {
5846         /*
5847          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5848          * Execution", on an exit, vmx_instruction_info holds most of the
5849          * addressing components of the operand. Only the displacement part
5850          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5851          * For how an actual address is calculated from all these components,
5852          * refer to Vol. 1, "Operand Addressing".
5853          */
5854         int  scaling = vmx_instruction_info & 3;
5855         int  addr_size = (vmx_instruction_info >> 7) & 7;
5856         bool is_reg = vmx_instruction_info & (1u << 10);
5857         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5858         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5859         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5860         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5861         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5862
5863         if (is_reg) {
5864                 kvm_queue_exception(vcpu, UD_VECTOR);
5865                 return 1;
5866         }
5867
5868         /* Addr = segment_base + offset */
5869         /* offset = base + [index * scale] + displacement */
5870         *ret = vmx_get_segment_base(vcpu, seg_reg);
5871         if (base_is_valid)
5872                 *ret += kvm_register_read(vcpu, base_reg);
5873         if (index_is_valid)
5874                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5875         *ret += exit_qualification; /* holds the displacement */
5876
5877         if (addr_size == 1) /* 32 bit */
5878                 *ret &= 0xffffffff;
5879
5880         /*
5881          * TODO: throw #GP (and return 1) in various cases that the VM*
5882          * instructions require it - e.g., offset beyond segment limit,
5883          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5884          * address, and so on. Currently these are not checked.
5885          */
5886         return 0;
5887 }
5888
5889 /* Emulate the VMCLEAR instruction */
5890 static int handle_vmclear(struct kvm_vcpu *vcpu)
5891 {
5892         struct vcpu_vmx *vmx = to_vmx(vcpu);
5893         gva_t gva;
5894         gpa_t vmptr;
5895         struct vmcs12 *vmcs12;
5896         struct page *page;
5897         struct x86_exception e;
5898
5899         if (!nested_vmx_check_permission(vcpu))
5900                 return 1;
5901
5902         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5903                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5904                 return 1;
5905
5906         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5907                                 sizeof(vmptr), &e)) {
5908                 kvm_inject_page_fault(vcpu, &e);
5909                 return 1;
5910         }
5911
5912         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5913                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5914                 skip_emulated_instruction(vcpu);
5915                 return 1;
5916         }
5917
5918         if (vmptr == vmx->nested.current_vmptr) {
5919                 nested_release_vmcs12(vmx);
5920                 vmx->nested.current_vmptr = -1ull;
5921                 vmx->nested.current_vmcs12 = NULL;
5922         }
5923
5924         page = nested_get_page(vcpu, vmptr);
5925         if (page == NULL) {
5926                 /*
5927                  * For accurate processor emulation, VMCLEAR beyond available
5928                  * physical memory should do nothing at all. However, it is
5929                  * possible that a nested vmx bug, not a guest hypervisor bug,
5930                  * resulted in this case, so let's shut down before doing any
5931                  * more damage:
5932                  */
5933                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5934                 return 1;
5935         }
5936         vmcs12 = kmap(page);
5937         vmcs12->launch_state = 0;
5938         kunmap(page);
5939         nested_release_page(page);
5940
5941         nested_free_vmcs02(vmx, vmptr);
5942
5943         skip_emulated_instruction(vcpu);
5944         nested_vmx_succeed(vcpu);
5945         return 1;
5946 }
5947
5948 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5949
5950 /* Emulate the VMLAUNCH instruction */
5951 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5952 {
5953         return nested_vmx_run(vcpu, true);
5954 }
5955
5956 /* Emulate the VMRESUME instruction */
5957 static int handle_vmresume(struct kvm_vcpu *vcpu)
5958 {
5959
5960         return nested_vmx_run(vcpu, false);
5961 }
5962
5963 enum vmcs_field_type {
5964         VMCS_FIELD_TYPE_U16 = 0,
5965         VMCS_FIELD_TYPE_U64 = 1,
5966         VMCS_FIELD_TYPE_U32 = 2,
5967         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5968 };
5969
5970 static inline int vmcs_field_type(unsigned long field)
5971 {
5972         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5973                 return VMCS_FIELD_TYPE_U32;
5974         return (field >> 13) & 0x3 ;
5975 }
5976
5977 static inline int vmcs_field_readonly(unsigned long field)
5978 {
5979         return (((field >> 10) & 0x3) == 1);
5980 }
5981
5982 /*
5983  * Read a vmcs12 field. Since these can have varying lengths and we return
5984  * one type, we chose the biggest type (u64) and zero-extend the return value
5985  * to that size. Note that the caller, handle_vmread, might need to use only
5986  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5987  * 64-bit fields are to be returned).
5988  */
5989 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5990                                         unsigned long field, u64 *ret)
5991 {
5992         short offset = vmcs_field_to_offset(field);
5993         char *p;
5994
5995         if (offset < 0)
5996                 return 0;
5997
5998         p = ((char *)(get_vmcs12(vcpu))) + offset;
5999
6000         switch (vmcs_field_type(field)) {
6001         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6002                 *ret = *((natural_width *)p);
6003                 return 1;
6004         case VMCS_FIELD_TYPE_U16:
6005                 *ret = *((u16 *)p);
6006                 return 1;
6007         case VMCS_FIELD_TYPE_U32:
6008                 *ret = *((u32 *)p);
6009                 return 1;
6010         case VMCS_FIELD_TYPE_U64:
6011                 *ret = *((u64 *)p);
6012                 return 1;
6013         default:
6014                 return 0; /* can never happen. */
6015         }
6016 }
6017
6018
6019 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6020                                     unsigned long field, u64 field_value){
6021         short offset = vmcs_field_to_offset(field);
6022         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6023         if (offset < 0)
6024                 return false;
6025
6026         switch (vmcs_field_type(field)) {
6027         case VMCS_FIELD_TYPE_U16:
6028                 *(u16 *)p = field_value;
6029                 return true;
6030         case VMCS_FIELD_TYPE_U32:
6031                 *(u32 *)p = field_value;
6032                 return true;
6033         case VMCS_FIELD_TYPE_U64:
6034                 *(u64 *)p = field_value;
6035                 return true;
6036         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6037                 *(natural_width *)p = field_value;
6038                 return true;
6039         default:
6040                 return false; /* can never happen. */
6041         }
6042
6043 }
6044
6045 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6046 {
6047         int i;
6048         unsigned long field;
6049         u64 field_value;
6050         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6051         const unsigned long *fields = shadow_read_write_fields;
6052         const int num_fields = max_shadow_read_write_fields;
6053
6054         vmcs_load(shadow_vmcs);
6055
6056         for (i = 0; i < num_fields; i++) {
6057                 field = fields[i];
6058                 switch (vmcs_field_type(field)) {
6059                 case VMCS_FIELD_TYPE_U16:
6060                         field_value = vmcs_read16(field);
6061                         break;
6062                 case VMCS_FIELD_TYPE_U32:
6063                         field_value = vmcs_read32(field);
6064                         break;
6065                 case VMCS_FIELD_TYPE_U64:
6066                         field_value = vmcs_read64(field);
6067                         break;
6068                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6069                         field_value = vmcs_readl(field);
6070                         break;
6071                 }
6072                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6073         }
6074
6075         vmcs_clear(shadow_vmcs);
6076         vmcs_load(vmx->loaded_vmcs->vmcs);
6077 }
6078
6079 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6080 {
6081         const unsigned long *fields[] = {
6082                 shadow_read_write_fields,
6083                 shadow_read_only_fields
6084         };
6085         const int max_fields[] = {
6086                 max_shadow_read_write_fields,
6087                 max_shadow_read_only_fields
6088         };
6089         int i, q;
6090         unsigned long field;
6091         u64 field_value = 0;
6092         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6093
6094         vmcs_load(shadow_vmcs);
6095
6096         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6097                 for (i = 0; i < max_fields[q]; i++) {
6098                         field = fields[q][i];
6099                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6100
6101                         switch (vmcs_field_type(field)) {
6102                         case VMCS_FIELD_TYPE_U16:
6103                                 vmcs_write16(field, (u16)field_value);
6104                                 break;
6105                         case VMCS_FIELD_TYPE_U32:
6106                                 vmcs_write32(field, (u32)field_value);
6107                                 break;
6108                         case VMCS_FIELD_TYPE_U64:
6109                                 vmcs_write64(field, (u64)field_value);
6110                                 break;
6111                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6112                                 vmcs_writel(field, (long)field_value);
6113                                 break;
6114                         }
6115                 }
6116         }
6117
6118         vmcs_clear(shadow_vmcs);
6119         vmcs_load(vmx->loaded_vmcs->vmcs);
6120 }
6121
6122 /*
6123  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6124  * used before) all generate the same failure when it is missing.
6125  */
6126 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6127 {
6128         struct vcpu_vmx *vmx = to_vmx(vcpu);
6129         if (vmx->nested.current_vmptr == -1ull) {
6130                 nested_vmx_failInvalid(vcpu);
6131                 skip_emulated_instruction(vcpu);
6132                 return 0;
6133         }
6134         return 1;
6135 }
6136
6137 static int handle_vmread(struct kvm_vcpu *vcpu)
6138 {
6139         unsigned long field;
6140         u64 field_value;
6141         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6142         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6143         gva_t gva = 0;
6144
6145         if (!nested_vmx_check_permission(vcpu) ||
6146             !nested_vmx_check_vmcs12(vcpu))
6147                 return 1;
6148
6149         /* Decode instruction info and find the field to read */
6150         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6151         /* Read the field, zero-extended to a u64 field_value */
6152         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6153                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6154                 skip_emulated_instruction(vcpu);
6155                 return 1;
6156         }
6157         /*
6158          * Now copy part of this value to register or memory, as requested.
6159          * Note that the number of bits actually copied is 32 or 64 depending
6160          * on the guest's mode (32 or 64 bit), not on the given field's length.
6161          */
6162         if (vmx_instruction_info & (1u << 10)) {
6163                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6164                         field_value);
6165         } else {
6166                 if (get_vmx_mem_address(vcpu, exit_qualification,
6167                                 vmx_instruction_info, &gva))
6168                         return 1;
6169                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6170                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6171                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6172         }
6173
6174         nested_vmx_succeed(vcpu);
6175         skip_emulated_instruction(vcpu);
6176         return 1;
6177 }
6178
6179
6180 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6181 {
6182         unsigned long field;
6183         gva_t gva;
6184         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6185         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6186         /* The value to write might be 32 or 64 bits, depending on L1's long
6187          * mode, and eventually we need to write that into a field of several
6188          * possible lengths. The code below first zero-extends the value to 64
6189          * bit (field_value), and then copies only the approriate number of
6190          * bits into the vmcs12 field.
6191          */
6192         u64 field_value = 0;
6193         struct x86_exception e;
6194
6195         if (!nested_vmx_check_permission(vcpu) ||
6196             !nested_vmx_check_vmcs12(vcpu))
6197                 return 1;
6198
6199         if (vmx_instruction_info & (1u << 10))
6200                 field_value = kvm_register_read(vcpu,
6201                         (((vmx_instruction_info) >> 3) & 0xf));
6202         else {
6203                 if (get_vmx_mem_address(vcpu, exit_qualification,
6204                                 vmx_instruction_info, &gva))
6205                         return 1;
6206                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6207                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6208                         kvm_inject_page_fault(vcpu, &e);
6209                         return 1;
6210                 }
6211         }
6212
6213
6214         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6215         if (vmcs_field_readonly(field)) {
6216                 nested_vmx_failValid(vcpu,
6217                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6218                 skip_emulated_instruction(vcpu);
6219                 return 1;
6220         }
6221
6222         if (!vmcs12_write_any(vcpu, field, field_value)) {
6223                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6224                 skip_emulated_instruction(vcpu);
6225                 return 1;
6226         }
6227
6228         nested_vmx_succeed(vcpu);
6229         skip_emulated_instruction(vcpu);
6230         return 1;
6231 }
6232
6233 /* Emulate the VMPTRLD instruction */
6234 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6235 {
6236         struct vcpu_vmx *vmx = to_vmx(vcpu);
6237         gva_t gva;
6238         gpa_t vmptr;
6239         struct x86_exception e;
6240         u32 exec_control;
6241
6242         if (!nested_vmx_check_permission(vcpu))
6243                 return 1;
6244
6245         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6246                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6247                 return 1;
6248
6249         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6250                                 sizeof(vmptr), &e)) {
6251                 kvm_inject_page_fault(vcpu, &e);
6252                 return 1;
6253         }
6254
6255         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6256                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6257                 skip_emulated_instruction(vcpu);
6258                 return 1;
6259         }
6260
6261         if (vmx->nested.current_vmptr != vmptr) {
6262                 struct vmcs12 *new_vmcs12;
6263                 struct page *page;
6264                 page = nested_get_page(vcpu, vmptr);
6265                 if (page == NULL) {
6266                         nested_vmx_failInvalid(vcpu);
6267                         skip_emulated_instruction(vcpu);
6268                         return 1;
6269                 }
6270                 new_vmcs12 = kmap(page);
6271                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6272                         kunmap(page);
6273                         nested_release_page_clean(page);
6274                         nested_vmx_failValid(vcpu,
6275                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6276                         skip_emulated_instruction(vcpu);
6277                         return 1;
6278                 }
6279                 if (vmx->nested.current_vmptr != -1ull)
6280                         nested_release_vmcs12(vmx);
6281
6282                 vmx->nested.current_vmptr = vmptr;
6283                 vmx->nested.current_vmcs12 = new_vmcs12;
6284                 vmx->nested.current_vmcs12_page = page;
6285                 if (enable_shadow_vmcs) {
6286                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6287                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6288                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6289                         vmcs_write64(VMCS_LINK_POINTER,
6290                                      __pa(vmx->nested.current_shadow_vmcs));
6291                         vmx->nested.sync_shadow_vmcs = true;
6292                 }
6293         }
6294
6295         nested_vmx_succeed(vcpu);
6296         skip_emulated_instruction(vcpu);
6297         return 1;
6298 }
6299
6300 /* Emulate the VMPTRST instruction */
6301 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6302 {
6303         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6304         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6305         gva_t vmcs_gva;
6306         struct x86_exception e;
6307
6308         if (!nested_vmx_check_permission(vcpu))
6309                 return 1;
6310
6311         if (get_vmx_mem_address(vcpu, exit_qualification,
6312                         vmx_instruction_info, &vmcs_gva))
6313                 return 1;
6314         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6315         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6316                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6317                                  sizeof(u64), &e)) {
6318                 kvm_inject_page_fault(vcpu, &e);
6319                 return 1;
6320         }
6321         nested_vmx_succeed(vcpu);
6322         skip_emulated_instruction(vcpu);
6323         return 1;
6324 }
6325
6326 /* Emulate the INVEPT instruction */
6327 static int handle_invept(struct kvm_vcpu *vcpu)
6328 {
6329         u32 vmx_instruction_info, types;
6330         unsigned long type;
6331         gva_t gva;
6332         struct x86_exception e;
6333         struct {
6334                 u64 eptp, gpa;
6335         } operand;
6336         u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6337
6338         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6339             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6340                 kvm_queue_exception(vcpu, UD_VECTOR);
6341                 return 1;
6342         }
6343
6344         if (!nested_vmx_check_permission(vcpu))
6345                 return 1;
6346
6347         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6348                 kvm_queue_exception(vcpu, UD_VECTOR);
6349                 return 1;
6350         }
6351
6352         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6353         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6354
6355         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6356
6357         if (!(types & (1UL << type))) {
6358                 nested_vmx_failValid(vcpu,
6359                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6360                 return 1;
6361         }
6362
6363         /* According to the Intel VMX instruction reference, the memory
6364          * operand is read even if it isn't needed (e.g., for type==global)
6365          */
6366         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6367                         vmx_instruction_info, &gva))
6368                 return 1;
6369         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6370                                 sizeof(operand), &e)) {
6371                 kvm_inject_page_fault(vcpu, &e);
6372                 return 1;
6373         }
6374
6375         switch (type) {
6376         case VMX_EPT_EXTENT_CONTEXT:
6377                 if ((operand.eptp & eptp_mask) !=
6378                                 (nested_ept_get_cr3(vcpu) & eptp_mask))
6379                         break;
6380         case VMX_EPT_EXTENT_GLOBAL:
6381                 kvm_mmu_sync_roots(vcpu);
6382                 kvm_mmu_flush_tlb(vcpu);
6383                 nested_vmx_succeed(vcpu);
6384                 break;
6385         default:
6386                 BUG_ON(1);
6387                 break;
6388         }
6389
6390         skip_emulated_instruction(vcpu);
6391         return 1;
6392 }
6393
6394 /*
6395  * The exit handlers return 1 if the exit was handled fully and guest execution
6396  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6397  * to be done to userspace and return 0.
6398  */
6399 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6400         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6401         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6402         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6403         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6404         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6405         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6406         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6407         [EXIT_REASON_CPUID]                   = handle_cpuid,
6408         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6409         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6410         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6411         [EXIT_REASON_HLT]                     = handle_halt,
6412         [EXIT_REASON_INVD]                    = handle_invd,
6413         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6414         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6415         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6416         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6417         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6418         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6419         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6420         [EXIT_REASON_VMREAD]                  = handle_vmread,
6421         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6422         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6423         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6424         [EXIT_REASON_VMON]                    = handle_vmon,
6425         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6426         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6427         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6428         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6429         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6430         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6431         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6432         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6433         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6434         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6435         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6436         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6437         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6438         [EXIT_REASON_INVEPT]                  = handle_invept,
6439 };
6440
6441 static const int kvm_vmx_max_exit_handlers =
6442         ARRAY_SIZE(kvm_vmx_exit_handlers);
6443
6444 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6445                                        struct vmcs12 *vmcs12)
6446 {
6447         unsigned long exit_qualification;
6448         gpa_t bitmap, last_bitmap;
6449         unsigned int port;
6450         int size;
6451         u8 b;
6452
6453         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6454                 return 1;
6455
6456         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6457                 return 0;
6458
6459         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6460
6461         port = exit_qualification >> 16;
6462         size = (exit_qualification & 7) + 1;
6463
6464         last_bitmap = (gpa_t)-1;
6465         b = -1;
6466
6467         while (size > 0) {
6468                 if (port < 0x8000)
6469                         bitmap = vmcs12->io_bitmap_a;
6470                 else if (port < 0x10000)
6471                         bitmap = vmcs12->io_bitmap_b;
6472                 else
6473                         return 1;
6474                 bitmap += (port & 0x7fff) / 8;
6475
6476                 if (last_bitmap != bitmap)
6477                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6478                                 return 1;
6479                 if (b & (1 << (port & 7)))
6480                         return 1;
6481
6482                 port++;
6483                 size--;
6484                 last_bitmap = bitmap;
6485         }
6486
6487         return 0;
6488 }
6489
6490 /*
6491  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6492  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6493  * disinterest in the current event (read or write a specific MSR) by using an
6494  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6495  */
6496 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6497         struct vmcs12 *vmcs12, u32 exit_reason)
6498 {
6499         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6500         gpa_t bitmap;
6501
6502         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6503                 return 1;
6504
6505         /*
6506          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6507          * for the four combinations of read/write and low/high MSR numbers.
6508          * First we need to figure out which of the four to use:
6509          */
6510         bitmap = vmcs12->msr_bitmap;
6511         if (exit_reason == EXIT_REASON_MSR_WRITE)
6512                 bitmap += 2048;
6513         if (msr_index >= 0xc0000000) {
6514                 msr_index -= 0xc0000000;
6515                 bitmap += 1024;
6516         }
6517
6518         /* Then read the msr_index'th bit from this bitmap: */
6519         if (msr_index < 1024*8) {
6520                 unsigned char b;
6521                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6522                         return 1;
6523                 return 1 & (b >> (msr_index & 7));
6524         } else
6525                 return 1; /* let L1 handle the wrong parameter */
6526 }
6527
6528 /*
6529  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6530  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6531  * intercept (via guest_host_mask etc.) the current event.
6532  */
6533 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6534         struct vmcs12 *vmcs12)
6535 {
6536         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6537         int cr = exit_qualification & 15;
6538         int reg = (exit_qualification >> 8) & 15;
6539         unsigned long val = kvm_register_read(vcpu, reg);
6540
6541         switch ((exit_qualification >> 4) & 3) {
6542         case 0: /* mov to cr */
6543                 switch (cr) {
6544                 case 0:
6545                         if (vmcs12->cr0_guest_host_mask &
6546                             (val ^ vmcs12->cr0_read_shadow))
6547                                 return 1;
6548                         break;
6549                 case 3:
6550                         if ((vmcs12->cr3_target_count >= 1 &&
6551                                         vmcs12->cr3_target_value0 == val) ||
6552                                 (vmcs12->cr3_target_count >= 2 &&
6553                                         vmcs12->cr3_target_value1 == val) ||
6554                                 (vmcs12->cr3_target_count >= 3 &&
6555                                         vmcs12->cr3_target_value2 == val) ||
6556                                 (vmcs12->cr3_target_count >= 4 &&
6557                                         vmcs12->cr3_target_value3 == val))
6558                                 return 0;
6559                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6560                                 return 1;
6561                         break;
6562                 case 4:
6563                         if (vmcs12->cr4_guest_host_mask &
6564                             (vmcs12->cr4_read_shadow ^ val))
6565                                 return 1;
6566                         break;
6567                 case 8:
6568                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6569                                 return 1;
6570                         break;
6571                 }
6572                 break;
6573         case 2: /* clts */
6574                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6575                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6576                         return 1;
6577                 break;
6578         case 1: /* mov from cr */
6579                 switch (cr) {
6580                 case 3:
6581                         if (vmcs12->cpu_based_vm_exec_control &
6582                             CPU_BASED_CR3_STORE_EXITING)
6583                                 return 1;
6584                         break;
6585                 case 8:
6586                         if (vmcs12->cpu_based_vm_exec_control &
6587                             CPU_BASED_CR8_STORE_EXITING)
6588                                 return 1;
6589                         break;
6590                 }
6591                 break;
6592         case 3: /* lmsw */
6593                 /*
6594                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6595                  * cr0. Other attempted changes are ignored, with no exit.
6596                  */
6597                 if (vmcs12->cr0_guest_host_mask & 0xe &
6598                     (val ^ vmcs12->cr0_read_shadow))
6599                         return 1;
6600                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6601                     !(vmcs12->cr0_read_shadow & 0x1) &&
6602                     (val & 0x1))
6603                         return 1;
6604                 break;
6605         }
6606         return 0;
6607 }
6608
6609 /*
6610  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6611  * should handle it ourselves in L0 (and then continue L2). Only call this
6612  * when in is_guest_mode (L2).
6613  */
6614 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6615 {
6616         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6617         struct vcpu_vmx *vmx = to_vmx(vcpu);
6618         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6619         u32 exit_reason = vmx->exit_reason;
6620
6621         if (vmx->nested.nested_run_pending)
6622                 return 0;
6623
6624         if (unlikely(vmx->fail)) {
6625                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6626                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6627                 return 1;
6628         }
6629
6630         switch (exit_reason) {
6631         case EXIT_REASON_EXCEPTION_NMI:
6632                 if (!is_exception(intr_info))
6633                         return 0;
6634                 else if (is_page_fault(intr_info))
6635                         return enable_ept;
6636                 return vmcs12->exception_bitmap &
6637                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6638         case EXIT_REASON_EXTERNAL_INTERRUPT:
6639                 return 0;
6640         case EXIT_REASON_TRIPLE_FAULT:
6641                 return 1;
6642         case EXIT_REASON_PENDING_INTERRUPT:
6643                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6644         case EXIT_REASON_NMI_WINDOW:
6645                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6646         case EXIT_REASON_TASK_SWITCH:
6647                 return 1;
6648         case EXIT_REASON_CPUID:
6649                 return 1;
6650         case EXIT_REASON_HLT:
6651                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6652         case EXIT_REASON_INVD:
6653                 return 1;
6654         case EXIT_REASON_INVLPG:
6655                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6656         case EXIT_REASON_RDPMC:
6657                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6658         case EXIT_REASON_RDTSC:
6659                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6660         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6661         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6662         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6663         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6664         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6665         case EXIT_REASON_INVEPT:
6666                 /*
6667                  * VMX instructions trap unconditionally. This allows L1 to
6668                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6669                  */
6670                 return 1;
6671         case EXIT_REASON_CR_ACCESS:
6672                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6673         case EXIT_REASON_DR_ACCESS:
6674                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6675         case EXIT_REASON_IO_INSTRUCTION:
6676                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6677         case EXIT_REASON_MSR_READ:
6678         case EXIT_REASON_MSR_WRITE:
6679                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6680         case EXIT_REASON_INVALID_STATE:
6681                 return 1;
6682         case EXIT_REASON_MWAIT_INSTRUCTION:
6683                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6684         case EXIT_REASON_MONITOR_INSTRUCTION:
6685                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6686         case EXIT_REASON_PAUSE_INSTRUCTION:
6687                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6688                         nested_cpu_has2(vmcs12,
6689                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6690         case EXIT_REASON_MCE_DURING_VMENTRY:
6691                 return 0;
6692         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6693                 return 1;
6694         case EXIT_REASON_APIC_ACCESS:
6695                 return nested_cpu_has2(vmcs12,
6696                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6697         case EXIT_REASON_EPT_VIOLATION:
6698                 /*
6699                  * L0 always deals with the EPT violation. If nested EPT is
6700                  * used, and the nested mmu code discovers that the address is
6701                  * missing in the guest EPT table (EPT12), the EPT violation
6702                  * will be injected with nested_ept_inject_page_fault()
6703                  */
6704                 return 0;
6705         case EXIT_REASON_EPT_MISCONFIG:
6706                 /*
6707                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6708                  * table (shadow on EPT) or a merged EPT table that L0 built
6709                  * (EPT on EPT). So any problems with the structure of the
6710                  * table is L0's fault.
6711                  */
6712                 return 0;
6713         case EXIT_REASON_PREEMPTION_TIMER:
6714                 return vmcs12->pin_based_vm_exec_control &
6715                         PIN_BASED_VMX_PREEMPTION_TIMER;
6716         case EXIT_REASON_WBINVD:
6717                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6718         case EXIT_REASON_XSETBV:
6719                 return 1;
6720         default:
6721                 return 1;
6722         }
6723 }
6724
6725 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6726 {
6727         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6728         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6729 }
6730
6731 /*
6732  * The guest has exited.  See if we can fix it or if we need userspace
6733  * assistance.
6734  */
6735 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6736 {
6737         struct vcpu_vmx *vmx = to_vmx(vcpu);
6738         u32 exit_reason = vmx->exit_reason;
6739         u32 vectoring_info = vmx->idt_vectoring_info;
6740
6741         /* If guest state is invalid, start emulating */
6742         if (vmx->emulation_required)
6743                 return handle_invalid_guest_state(vcpu);
6744
6745         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6746                 nested_vmx_vmexit(vcpu);
6747                 return 1;
6748         }
6749
6750         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6751                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6752                 vcpu->run->fail_entry.hardware_entry_failure_reason
6753                         = exit_reason;
6754                 return 0;
6755         }
6756
6757         if (unlikely(vmx->fail)) {
6758                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6759                 vcpu->run->fail_entry.hardware_entry_failure_reason
6760                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6761                 return 0;
6762         }
6763
6764         /*
6765          * Note:
6766          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6767          * delivery event since it indicates guest is accessing MMIO.
6768          * The vm-exit can be triggered again after return to guest that
6769          * will cause infinite loop.
6770          */
6771         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6772                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6773                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6774                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6775                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6776                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6777                 vcpu->run->internal.ndata = 2;
6778                 vcpu->run->internal.data[0] = vectoring_info;
6779                 vcpu->run->internal.data[1] = exit_reason;
6780                 return 0;
6781         }
6782
6783         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6784             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6785                                         get_vmcs12(vcpu))))) {
6786                 if (vmx_interrupt_allowed(vcpu)) {
6787                         vmx->soft_vnmi_blocked = 0;
6788                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6789                            vcpu->arch.nmi_pending) {
6790                         /*
6791                          * This CPU don't support us in finding the end of an
6792                          * NMI-blocked window if the guest runs with IRQs
6793                          * disabled. So we pull the trigger after 1 s of
6794                          * futile waiting, but inform the user about this.
6795                          */
6796                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6797                                "state on VCPU %d after 1 s timeout\n",
6798                                __func__, vcpu->vcpu_id);
6799                         vmx->soft_vnmi_blocked = 0;
6800                 }
6801         }
6802
6803         if (exit_reason < kvm_vmx_max_exit_handlers
6804             && kvm_vmx_exit_handlers[exit_reason])
6805                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6806         else {
6807                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6808                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6809         }
6810         return 0;
6811 }
6812
6813 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6814 {
6815         if (irr == -1 || tpr < irr) {
6816                 vmcs_write32(TPR_THRESHOLD, 0);
6817                 return;
6818         }
6819
6820         vmcs_write32(TPR_THRESHOLD, irr);
6821 }
6822
6823 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6824 {
6825         u32 sec_exec_control;
6826
6827         /*
6828          * There is not point to enable virtualize x2apic without enable
6829          * apicv
6830          */
6831         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6832                                 !vmx_vm_has_apicv(vcpu->kvm))
6833                 return;
6834
6835         if (!vm_need_tpr_shadow(vcpu->kvm))
6836                 return;
6837
6838         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6839
6840         if (set) {
6841                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6842                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6843         } else {
6844                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6845                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6846         }
6847         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6848
6849         vmx_set_msr_bitmap(vcpu);
6850 }
6851
6852 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6853 {
6854         u16 status;
6855         u8 old;
6856
6857         if (!vmx_vm_has_apicv(kvm))
6858                 return;
6859
6860         if (isr == -1)
6861                 isr = 0;
6862
6863         status = vmcs_read16(GUEST_INTR_STATUS);
6864         old = status >> 8;
6865         if (isr != old) {
6866                 status &= 0xff;
6867                 status |= isr << 8;
6868                 vmcs_write16(GUEST_INTR_STATUS, status);
6869         }
6870 }
6871
6872 static void vmx_set_rvi(int vector)
6873 {
6874         u16 status;
6875         u8 old;
6876
6877         status = vmcs_read16(GUEST_INTR_STATUS);
6878         old = (u8)status & 0xff;
6879         if ((u8)vector != old) {
6880                 status &= ~0xff;
6881                 status |= (u8)vector;
6882                 vmcs_write16(GUEST_INTR_STATUS, status);
6883         }
6884 }
6885
6886 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6887 {
6888         if (max_irr == -1)
6889                 return;
6890
6891         vmx_set_rvi(max_irr);
6892 }
6893
6894 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6895 {
6896         if (!vmx_vm_has_apicv(vcpu->kvm))
6897                 return;
6898
6899         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6900         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6901         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6902         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6903 }
6904
6905 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6906 {
6907         u32 exit_intr_info;
6908
6909         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6910               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6911                 return;
6912
6913         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6914         exit_intr_info = vmx->exit_intr_info;
6915
6916         /* Handle machine checks before interrupts are enabled */
6917         if (is_machine_check(exit_intr_info))
6918                 kvm_machine_check();
6919
6920         /* We need to handle NMIs before interrupts are enabled */
6921         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6922             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6923                 kvm_before_handle_nmi(&vmx->vcpu);
6924                 asm("int $2");
6925                 kvm_after_handle_nmi(&vmx->vcpu);
6926         }
6927 }
6928
6929 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6930 {
6931         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6932
6933         /*
6934          * If external interrupt exists, IF bit is set in rflags/eflags on the
6935          * interrupt stack frame, and interrupt will be enabled on a return
6936          * from interrupt handler.
6937          */
6938         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6939                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6940                 unsigned int vector;
6941                 unsigned long entry;
6942                 gate_desc *desc;
6943                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6944 #ifdef CONFIG_X86_64
6945                 unsigned long tmp;
6946 #endif
6947
6948                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6949                 desc = (gate_desc *)vmx->host_idt_base + vector;
6950                 entry = gate_offset(*desc);
6951                 asm volatile(
6952 #ifdef CONFIG_X86_64
6953                         "mov %%" _ASM_SP ", %[sp]\n\t"
6954                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6955                         "push $%c[ss]\n\t"
6956                         "push %[sp]\n\t"
6957 #endif
6958                         "pushf\n\t"
6959                         "orl $0x200, (%%" _ASM_SP ")\n\t"
6960                         __ASM_SIZE(push) " $%c[cs]\n\t"
6961                         "call *%[entry]\n\t"
6962                         :
6963 #ifdef CONFIG_X86_64
6964                         [sp]"=&r"(tmp)
6965 #endif
6966                         :
6967                         [entry]"r"(entry),
6968                         [ss]"i"(__KERNEL_DS),
6969                         [cs]"i"(__KERNEL_CS)
6970                         );
6971         } else
6972                 local_irq_enable();
6973 }
6974
6975 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6976 {
6977         u32 exit_intr_info;
6978         bool unblock_nmi;
6979         u8 vector;
6980         bool idtv_info_valid;
6981
6982         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6983
6984         if (cpu_has_virtual_nmis()) {
6985                 if (vmx->nmi_known_unmasked)
6986                         return;
6987                 /*
6988                  * Can't use vmx->exit_intr_info since we're not sure what
6989                  * the exit reason is.
6990                  */
6991                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6992                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6993                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6994                 /*
6995                  * SDM 3: 27.7.1.2 (September 2008)
6996                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6997                  * a guest IRET fault.
6998                  * SDM 3: 23.2.2 (September 2008)
6999                  * Bit 12 is undefined in any of the following cases:
7000                  *  If the VM exit sets the valid bit in the IDT-vectoring
7001                  *   information field.
7002                  *  If the VM exit is due to a double fault.
7003                  */
7004                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7005                     vector != DF_VECTOR && !idtv_info_valid)
7006                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7007                                       GUEST_INTR_STATE_NMI);
7008                 else
7009                         vmx->nmi_known_unmasked =
7010                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7011                                   & GUEST_INTR_STATE_NMI);
7012         } else if (unlikely(vmx->soft_vnmi_blocked))
7013                 vmx->vnmi_blocked_time +=
7014                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7015 }
7016
7017 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7018                                       u32 idt_vectoring_info,
7019                                       int instr_len_field,
7020                                       int error_code_field)
7021 {
7022         u8 vector;
7023         int type;
7024         bool idtv_info_valid;
7025
7026         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7027
7028         vcpu->arch.nmi_injected = false;
7029         kvm_clear_exception_queue(vcpu);
7030         kvm_clear_interrupt_queue(vcpu);
7031
7032         if (!idtv_info_valid)
7033                 return;
7034
7035         kvm_make_request(KVM_REQ_EVENT, vcpu);
7036
7037         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7038         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7039
7040         switch (type) {
7041         case INTR_TYPE_NMI_INTR:
7042                 vcpu->arch.nmi_injected = true;
7043                 /*
7044                  * SDM 3: 27.7.1.2 (September 2008)
7045                  * Clear bit "block by NMI" before VM entry if a NMI
7046                  * delivery faulted.
7047                  */
7048                 vmx_set_nmi_mask(vcpu, false);
7049                 break;
7050         case INTR_TYPE_SOFT_EXCEPTION:
7051                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7052                 /* fall through */
7053         case INTR_TYPE_HARD_EXCEPTION:
7054                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7055                         u32 err = vmcs_read32(error_code_field);
7056                         kvm_requeue_exception_e(vcpu, vector, err);
7057                 } else
7058                         kvm_requeue_exception(vcpu, vector);
7059                 break;
7060         case INTR_TYPE_SOFT_INTR:
7061                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7062                 /* fall through */
7063         case INTR_TYPE_EXT_INTR:
7064                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7065                 break;
7066         default:
7067                 break;
7068         }
7069 }
7070
7071 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7072 {
7073         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7074                                   VM_EXIT_INSTRUCTION_LEN,
7075                                   IDT_VECTORING_ERROR_CODE);
7076 }
7077
7078 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7079 {
7080         __vmx_complete_interrupts(vcpu,
7081                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7082                                   VM_ENTRY_INSTRUCTION_LEN,
7083                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7084
7085         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7086 }
7087
7088 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7089 {
7090         int i, nr_msrs;
7091         struct perf_guest_switch_msr *msrs;
7092
7093         msrs = perf_guest_get_msrs(&nr_msrs);
7094
7095         if (!msrs)
7096                 return;
7097
7098         for (i = 0; i < nr_msrs; i++)
7099                 if (msrs[i].host == msrs[i].guest)
7100                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7101                 else
7102                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7103                                         msrs[i].host);
7104 }
7105
7106 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7107 {
7108         struct vcpu_vmx *vmx = to_vmx(vcpu);
7109         unsigned long debugctlmsr;
7110
7111         /* Record the guest's net vcpu time for enforced NMI injections. */
7112         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7113                 vmx->entry_time = ktime_get();
7114
7115         /* Don't enter VMX if guest state is invalid, let the exit handler
7116            start emulation until we arrive back to a valid state */
7117         if (vmx->emulation_required)
7118                 return;
7119
7120         if (vmx->nested.sync_shadow_vmcs) {
7121                 copy_vmcs12_to_shadow(vmx);
7122                 vmx->nested.sync_shadow_vmcs = false;
7123         }
7124
7125         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7126                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7127         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7128                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7129
7130         /* When single-stepping over STI and MOV SS, we must clear the
7131          * corresponding interruptibility bits in the guest state. Otherwise
7132          * vmentry fails as it then expects bit 14 (BS) in pending debug
7133          * exceptions being set, but that's not correct for the guest debugging
7134          * case. */
7135         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7136                 vmx_set_interrupt_shadow(vcpu, 0);
7137
7138         atomic_switch_perf_msrs(vmx);
7139         debugctlmsr = get_debugctlmsr();
7140
7141         vmx->__launched = vmx->loaded_vmcs->launched;
7142         asm(
7143                 /* Store host registers */
7144                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7145                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7146                 "push %%" _ASM_CX " \n\t"
7147                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7148                 "je 1f \n\t"
7149                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7150                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7151                 "1: \n\t"
7152                 /* Reload cr2 if changed */
7153                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7154                 "mov %%cr2, %%" _ASM_DX " \n\t"
7155                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7156                 "je 2f \n\t"
7157                 "mov %%" _ASM_AX", %%cr2 \n\t"
7158                 "2: \n\t"
7159                 /* Check if vmlaunch of vmresume is needed */
7160                 "cmpl $0, %c[launched](%0) \n\t"
7161                 /* Load guest registers.  Don't clobber flags. */
7162                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7163                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7164                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7165                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7166                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7167                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7168 #ifdef CONFIG_X86_64
7169                 "mov %c[r8](%0),  %%r8  \n\t"
7170                 "mov %c[r9](%0),  %%r9  \n\t"
7171                 "mov %c[r10](%0), %%r10 \n\t"
7172                 "mov %c[r11](%0), %%r11 \n\t"
7173                 "mov %c[r12](%0), %%r12 \n\t"
7174                 "mov %c[r13](%0), %%r13 \n\t"
7175                 "mov %c[r14](%0), %%r14 \n\t"
7176                 "mov %c[r15](%0), %%r15 \n\t"
7177 #endif
7178                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7179
7180                 /* Enter guest mode */
7181                 "jne 1f \n\t"
7182                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7183                 "jmp 2f \n\t"
7184                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7185                 "2: "
7186                 /* Save guest registers, load host registers, keep flags */
7187                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7188                 "pop %0 \n\t"
7189                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7190                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7191                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7192                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7193                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7194                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7195                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7196 #ifdef CONFIG_X86_64
7197                 "mov %%r8,  %c[r8](%0) \n\t"
7198                 "mov %%r9,  %c[r9](%0) \n\t"
7199                 "mov %%r10, %c[r10](%0) \n\t"
7200                 "mov %%r11, %c[r11](%0) \n\t"
7201                 "mov %%r12, %c[r12](%0) \n\t"
7202                 "mov %%r13, %c[r13](%0) \n\t"
7203                 "mov %%r14, %c[r14](%0) \n\t"
7204                 "mov %%r15, %c[r15](%0) \n\t"
7205 #endif
7206                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7207                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7208
7209                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7210                 "setbe %c[fail](%0) \n\t"
7211                 ".pushsection .rodata \n\t"
7212                 ".global vmx_return \n\t"
7213                 "vmx_return: " _ASM_PTR " 2b \n\t"
7214                 ".popsection"
7215               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7216                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7217                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7218                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7219                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7220                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7221                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7222                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7223                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7224                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7225                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7226 #ifdef CONFIG_X86_64
7227                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7228                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7229                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7230                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7231                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7232                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7233                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7234                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7235 #endif
7236                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7237                 [wordsize]"i"(sizeof(ulong))
7238               : "cc", "memory"
7239 #ifdef CONFIG_X86_64
7240                 , "rax", "rbx", "rdi", "rsi"
7241                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7242 #else
7243                 , "eax", "ebx", "edi", "esi"
7244 #endif
7245               );
7246
7247         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7248         if (debugctlmsr)
7249                 update_debugctlmsr(debugctlmsr);
7250
7251 #ifndef CONFIG_X86_64
7252         /*
7253          * The sysexit path does not restore ds/es, so we must set them to
7254          * a reasonable value ourselves.
7255          *
7256          * We can't defer this to vmx_load_host_state() since that function
7257          * may be executed in interrupt context, which saves and restore segments
7258          * around it, nullifying its effect.
7259          */
7260         loadsegment(ds, __USER_DS);
7261         loadsegment(es, __USER_DS);
7262 #endif
7263
7264         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7265                                   | (1 << VCPU_EXREG_RFLAGS)
7266                                   | (1 << VCPU_EXREG_CPL)
7267                                   | (1 << VCPU_EXREG_PDPTR)
7268                                   | (1 << VCPU_EXREG_SEGMENTS)
7269                                   | (1 << VCPU_EXREG_CR3));
7270         vcpu->arch.regs_dirty = 0;
7271
7272         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7273
7274         vmx->loaded_vmcs->launched = 1;
7275
7276         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7277         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7278
7279         /*
7280          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7281          * we did not inject a still-pending event to L1 now because of
7282          * nested_run_pending, we need to re-enable this bit.
7283          */
7284         if (vmx->nested.nested_run_pending)
7285                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7286
7287         vmx->nested.nested_run_pending = 0;
7288
7289         vmx_complete_atomic_exit(vmx);
7290         vmx_recover_nmi_blocking(vmx);
7291         vmx_complete_interrupts(vmx);
7292 }
7293
7294 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7295 {
7296         struct vcpu_vmx *vmx = to_vmx(vcpu);
7297
7298         free_vpid(vmx);
7299         free_nested(vmx);
7300         free_loaded_vmcs(vmx->loaded_vmcs);
7301         kfree(vmx->guest_msrs);
7302         kvm_vcpu_uninit(vcpu);
7303         kmem_cache_free(kvm_vcpu_cache, vmx);
7304 }
7305
7306 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7307 {
7308         int err;
7309         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7310         int cpu;
7311
7312         if (!vmx)
7313                 return ERR_PTR(-ENOMEM);
7314
7315         allocate_vpid(vmx);
7316
7317         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7318         if (err)
7319                 goto free_vcpu;
7320
7321         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7322         err = -ENOMEM;
7323         if (!vmx->guest_msrs) {
7324                 goto uninit_vcpu;
7325         }
7326
7327         vmx->loaded_vmcs = &vmx->vmcs01;
7328         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7329         if (!vmx->loaded_vmcs->vmcs)
7330                 goto free_msrs;
7331         if (!vmm_exclusive)
7332                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7333         loaded_vmcs_init(vmx->loaded_vmcs);
7334         if (!vmm_exclusive)
7335                 kvm_cpu_vmxoff();
7336
7337         cpu = get_cpu();
7338         vmx_vcpu_load(&vmx->vcpu, cpu);
7339         vmx->vcpu.cpu = cpu;
7340         err = vmx_vcpu_setup(vmx);
7341         vmx_vcpu_put(&vmx->vcpu);
7342         put_cpu();
7343         if (err)
7344                 goto free_vmcs;
7345         if (vm_need_virtualize_apic_accesses(kvm)) {
7346                 err = alloc_apic_access_page(kvm);
7347                 if (err)
7348                         goto free_vmcs;
7349         }
7350
7351         if (enable_ept) {
7352                 if (!kvm->arch.ept_identity_map_addr)
7353                         kvm->arch.ept_identity_map_addr =
7354                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7355                 err = -ENOMEM;
7356                 if (alloc_identity_pagetable(kvm) != 0)
7357                         goto free_vmcs;
7358                 if (!init_rmode_identity_map(kvm))
7359                         goto free_vmcs;
7360         }
7361
7362         vmx->nested.current_vmptr = -1ull;
7363         vmx->nested.current_vmcs12 = NULL;
7364
7365         return &vmx->vcpu;
7366
7367 free_vmcs:
7368         free_loaded_vmcs(vmx->loaded_vmcs);
7369 free_msrs:
7370         kfree(vmx->guest_msrs);
7371 uninit_vcpu:
7372         kvm_vcpu_uninit(&vmx->vcpu);
7373 free_vcpu:
7374         free_vpid(vmx);
7375         kmem_cache_free(kvm_vcpu_cache, vmx);
7376         return ERR_PTR(err);
7377 }
7378
7379 static void __init vmx_check_processor_compat(void *rtn)
7380 {
7381         struct vmcs_config vmcs_conf;
7382
7383         *(int *)rtn = 0;
7384         if (setup_vmcs_config(&vmcs_conf) < 0)
7385                 *(int *)rtn = -EIO;
7386         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7387                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7388                                 smp_processor_id());
7389                 *(int *)rtn = -EIO;
7390         }
7391 }
7392
7393 static int get_ept_level(void)
7394 {
7395         return VMX_EPT_DEFAULT_GAW + 1;
7396 }
7397
7398 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7399 {
7400         u64 ret;
7401
7402         /* For VT-d and EPT combination
7403          * 1. MMIO: always map as UC
7404          * 2. EPT with VT-d:
7405          *   a. VT-d without snooping control feature: can't guarantee the
7406          *      result, try to trust guest.
7407          *   b. VT-d with snooping control feature: snooping control feature of
7408          *      VT-d engine can guarantee the cache correctness. Just set it
7409          *      to WB to keep consistent with host. So the same as item 3.
7410          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7411          *    consistent with host MTRR
7412          */
7413         if (is_mmio)
7414                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7415         else if (vcpu->kvm->arch.iommu_domain &&
7416                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7417                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7418                       VMX_EPT_MT_EPTE_SHIFT;
7419         else
7420                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7421                         | VMX_EPT_IPAT_BIT;
7422
7423         return ret;
7424 }
7425
7426 static int vmx_get_lpage_level(void)
7427 {
7428         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7429                 return PT_DIRECTORY_LEVEL;
7430         else
7431                 /* For shadow and EPT supported 1GB page */
7432                 return PT_PDPE_LEVEL;
7433 }
7434
7435 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7436 {
7437         struct kvm_cpuid_entry2 *best;
7438         struct vcpu_vmx *vmx = to_vmx(vcpu);
7439         u32 exec_control;
7440
7441         vmx->rdtscp_enabled = false;
7442         if (vmx_rdtscp_supported()) {
7443                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7444                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7445                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7446                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7447                                 vmx->rdtscp_enabled = true;
7448                         else {
7449                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7450                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7451                                                 exec_control);
7452                         }
7453                 }
7454         }
7455
7456         /* Exposing INVPCID only when PCID is exposed */
7457         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7458         if (vmx_invpcid_supported() &&
7459             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7460             guest_cpuid_has_pcid(vcpu)) {
7461                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7462                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7463                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7464                              exec_control);
7465         } else {
7466                 if (cpu_has_secondary_exec_ctrls()) {
7467                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7468                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7469                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7470                                      exec_control);
7471                 }
7472                 if (best)
7473                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7474         }
7475 }
7476
7477 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7478 {
7479         if (func == 1 && nested)
7480                 entry->ecx |= bit(X86_FEATURE_VMX);
7481 }
7482
7483 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7484                 struct x86_exception *fault)
7485 {
7486         struct vmcs12 *vmcs12;
7487         nested_vmx_vmexit(vcpu);
7488         vmcs12 = get_vmcs12(vcpu);
7489
7490         if (fault->error_code & PFERR_RSVD_MASK)
7491                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7492         else
7493                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7494         vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7495         vmcs12->guest_physical_address = fault->address;
7496 }
7497
7498 /* Callbacks for nested_ept_init_mmu_context: */
7499
7500 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7501 {
7502         /* return the page table to be shadowed - in our case, EPT12 */
7503         return get_vmcs12(vcpu)->ept_pointer;
7504 }
7505
7506 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7507 {
7508         int r = kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7509                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7510
7511         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7512         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7513         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7514
7515         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7516
7517         return r;
7518 }
7519
7520 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7521 {
7522         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7523 }
7524
7525 /*
7526  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7527  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7528  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7529  * guest in a way that will both be appropriate to L1's requests, and our
7530  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7531  * function also has additional necessary side-effects, like setting various
7532  * vcpu->arch fields.
7533  */
7534 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7535 {
7536         struct vcpu_vmx *vmx = to_vmx(vcpu);
7537         u32 exec_control;
7538
7539         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7540         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7541         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7542         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7543         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7544         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7545         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7546         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7547         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7548         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7549         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7550         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7551         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7552         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7553         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7554         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7555         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7556         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7557         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7558         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7559         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7560         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7561         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7562         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7563         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7564         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7565         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7566         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7567         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7568         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7569         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7570         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7571         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7572         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7573         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7574         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7575
7576         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7577         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7578                 vmcs12->vm_entry_intr_info_field);
7579         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7580                 vmcs12->vm_entry_exception_error_code);
7581         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7582                 vmcs12->vm_entry_instruction_len);
7583         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7584                 vmcs12->guest_interruptibility_info);
7585         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7586         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7587         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7588         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7589                 vmcs12->guest_pending_dbg_exceptions);
7590         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7591         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7592
7593         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7594
7595         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7596                 (vmcs_config.pin_based_exec_ctrl |
7597                  vmcs12->pin_based_vm_exec_control));
7598
7599         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7600                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7601                              vmcs12->vmx_preemption_timer_value);
7602
7603         /*
7604          * Whether page-faults are trapped is determined by a combination of
7605          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7606          * If enable_ept, L0 doesn't care about page faults and we should
7607          * set all of these to L1's desires. However, if !enable_ept, L0 does
7608          * care about (at least some) page faults, and because it is not easy
7609          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7610          * to exit on each and every L2 page fault. This is done by setting
7611          * MASK=MATCH=0 and (see below) EB.PF=1.
7612          * Note that below we don't need special code to set EB.PF beyond the
7613          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7614          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7615          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7616          *
7617          * A problem with this approach (when !enable_ept) is that L1 may be
7618          * injected with more page faults than it asked for. This could have
7619          * caused problems, but in practice existing hypervisors don't care.
7620          * To fix this, we will need to emulate the PFEC checking (on the L1
7621          * page tables), using walk_addr(), when injecting PFs to L1.
7622          */
7623         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7624                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7625         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7626                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7627
7628         if (cpu_has_secondary_exec_ctrls()) {
7629                 u32 exec_control = vmx_secondary_exec_control(vmx);
7630                 if (!vmx->rdtscp_enabled)
7631                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7632                 /* Take the following fields only from vmcs12 */
7633                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7634                 if (nested_cpu_has(vmcs12,
7635                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7636                         exec_control |= vmcs12->secondary_vm_exec_control;
7637
7638                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7639                         /*
7640                          * Translate L1 physical address to host physical
7641                          * address for vmcs02. Keep the page pinned, so this
7642                          * physical address remains valid. We keep a reference
7643                          * to it so we can release it later.
7644                          */
7645                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7646                                 nested_release_page(vmx->nested.apic_access_page);
7647                         vmx->nested.apic_access_page =
7648                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7649                         /*
7650                          * If translation failed, no matter: This feature asks
7651                          * to exit when accessing the given address, and if it
7652                          * can never be accessed, this feature won't do
7653                          * anything anyway.
7654                          */
7655                         if (!vmx->nested.apic_access_page)
7656                                 exec_control &=
7657                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7658                         else
7659                                 vmcs_write64(APIC_ACCESS_ADDR,
7660                                   page_to_phys(vmx->nested.apic_access_page));
7661                 }
7662
7663                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7664         }
7665
7666
7667         /*
7668          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7669          * Some constant fields are set here by vmx_set_constant_host_state().
7670          * Other fields are different per CPU, and will be set later when
7671          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7672          */
7673         vmx_set_constant_host_state(vmx);
7674
7675         /*
7676          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7677          * entry, but only if the current (host) sp changed from the value
7678          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7679          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7680          * here we just force the write to happen on entry.
7681          */
7682         vmx->host_rsp = 0;
7683
7684         exec_control = vmx_exec_control(vmx); /* L0's desires */
7685         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7686         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7687         exec_control &= ~CPU_BASED_TPR_SHADOW;
7688         exec_control |= vmcs12->cpu_based_vm_exec_control;
7689         /*
7690          * Merging of IO and MSR bitmaps not currently supported.
7691          * Rather, exit every time.
7692          */
7693         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7694         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7695         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7696
7697         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7698
7699         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7700          * bitwise-or of what L1 wants to trap for L2, and what we want to
7701          * trap. Note that CR0.TS also needs updating - we do this later.
7702          */
7703         update_exception_bitmap(vcpu);
7704         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7705         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7706
7707         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7708          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7709          * bits are further modified by vmx_set_efer() below.
7710          */
7711         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7712
7713         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7714          * emulated by vmx_set_efer(), below.
7715          */
7716         vmcs_write32(VM_ENTRY_CONTROLS,
7717                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7718                         ~VM_ENTRY_IA32E_MODE) |
7719                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7720
7721         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7722                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7723                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7724         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7725                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7726
7727
7728         set_cr4_guest_host_mask(vmx);
7729
7730         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7731                 vmcs_write64(TSC_OFFSET,
7732                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7733         else
7734                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7735
7736         if (enable_vpid) {
7737                 /*
7738                  * Trivially support vpid by letting L2s share their parent
7739                  * L1's vpid. TODO: move to a more elaborate solution, giving
7740                  * each L2 its own vpid and exposing the vpid feature to L1.
7741                  */
7742                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7743                 vmx_flush_tlb(vcpu);
7744         }
7745
7746         if (nested_cpu_has_ept(vmcs12)) {
7747                 kvm_mmu_unload(vcpu);
7748                 nested_ept_init_mmu_context(vcpu);
7749         }
7750
7751         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7752                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7753         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7754                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7755         else
7756                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7757         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7758         vmx_set_efer(vcpu, vcpu->arch.efer);
7759
7760         /*
7761          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7762          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7763          * The CR0_READ_SHADOW is what L2 should have expected to read given
7764          * the specifications by L1; It's not enough to take
7765          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7766          * have more bits than L1 expected.
7767          */
7768         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7769         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7770
7771         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7772         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7773
7774         /* shadow page tables on either EPT or shadow page tables */
7775         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7776         kvm_mmu_reset_context(vcpu);
7777
7778         /*
7779          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7780          */
7781         if (enable_ept) {
7782                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7783                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7784                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7785                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7786                 __clear_bit(VCPU_EXREG_PDPTR,
7787                                 (unsigned long *)&vcpu->arch.regs_avail);
7788                 __clear_bit(VCPU_EXREG_PDPTR,
7789                                 (unsigned long *)&vcpu->arch.regs_dirty);
7790         }
7791
7792         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7793         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7794 }
7795
7796 /*
7797  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7798  * for running an L2 nested guest.
7799  */
7800 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7801 {
7802         struct vmcs12 *vmcs12;
7803         struct vcpu_vmx *vmx = to_vmx(vcpu);
7804         int cpu;
7805         struct loaded_vmcs *vmcs02;
7806         bool ia32e;
7807
7808         if (!nested_vmx_check_permission(vcpu) ||
7809             !nested_vmx_check_vmcs12(vcpu))
7810                 return 1;
7811
7812         skip_emulated_instruction(vcpu);
7813         vmcs12 = get_vmcs12(vcpu);
7814
7815         if (enable_shadow_vmcs)
7816                 copy_shadow_to_vmcs12(vmx);
7817
7818         /*
7819          * The nested entry process starts with enforcing various prerequisites
7820          * on vmcs12 as required by the Intel SDM, and act appropriately when
7821          * they fail: As the SDM explains, some conditions should cause the
7822          * instruction to fail, while others will cause the instruction to seem
7823          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7824          * To speed up the normal (success) code path, we should avoid checking
7825          * for misconfigurations which will anyway be caught by the processor
7826          * when using the merged vmcs02.
7827          */
7828         if (vmcs12->launch_state == launch) {
7829                 nested_vmx_failValid(vcpu,
7830                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7831                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7832                 return 1;
7833         }
7834
7835         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7836                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7837                 return 1;
7838         }
7839
7840         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7841                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7842                 /*TODO: Also verify bits beyond physical address width are 0*/
7843                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7844                 return 1;
7845         }
7846
7847         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7848                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7849                 /*TODO: Also verify bits beyond physical address width are 0*/
7850                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7851                 return 1;
7852         }
7853
7854         if (vmcs12->vm_entry_msr_load_count > 0 ||
7855             vmcs12->vm_exit_msr_load_count > 0 ||
7856             vmcs12->vm_exit_msr_store_count > 0) {
7857                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7858                                     __func__);
7859                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7860                 return 1;
7861         }
7862
7863         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7864               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7865             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7866               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7867             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7868               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7869             !vmx_control_verify(vmcs12->vm_exit_controls,
7870               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7871             !vmx_control_verify(vmcs12->vm_entry_controls,
7872               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7873         {
7874                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7875                 return 1;
7876         }
7877
7878         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7879             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7880                 nested_vmx_failValid(vcpu,
7881                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7882                 return 1;
7883         }
7884
7885         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7886             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7887                 nested_vmx_entry_failure(vcpu, vmcs12,
7888                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7889                 return 1;
7890         }
7891         if (vmcs12->vmcs_link_pointer != -1ull) {
7892                 nested_vmx_entry_failure(vcpu, vmcs12,
7893                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7894                 return 1;
7895         }
7896
7897         /*
7898          * If the load IA32_EFER VM-entry control is 1, the following checks
7899          * are performed on the field for the IA32_EFER MSR:
7900          * - Bits reserved in the IA32_EFER MSR must be 0.
7901          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7902          *   the IA-32e mode guest VM-exit control. It must also be identical
7903          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7904          *   CR0.PG) is 1.
7905          */
7906         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7907                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7908                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7909                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7910                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7911                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7912                         nested_vmx_entry_failure(vcpu, vmcs12,
7913                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7914                         return 1;
7915                 }
7916         }
7917
7918         /*
7919          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7920          * IA32_EFER MSR must be 0 in the field for that register. In addition,
7921          * the values of the LMA and LME bits in the field must each be that of
7922          * the host address-space size VM-exit control.
7923          */
7924         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7925                 ia32e = (vmcs12->vm_exit_controls &
7926                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7927                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7928                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7929                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7930                         nested_vmx_entry_failure(vcpu, vmcs12,
7931                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7932                         return 1;
7933                 }
7934         }
7935
7936         /*
7937          * We're finally done with prerequisite checking, and can start with
7938          * the nested entry.
7939          */
7940
7941         vmcs02 = nested_get_current_vmcs02(vmx);
7942         if (!vmcs02)
7943                 return -ENOMEM;
7944
7945         enter_guest_mode(vcpu);
7946
7947         vmx->nested.nested_run_pending = 1;
7948
7949         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7950
7951         cpu = get_cpu();
7952         vmx->loaded_vmcs = vmcs02;
7953         vmx_vcpu_put(vcpu);
7954         vmx_vcpu_load(vcpu, cpu);
7955         vcpu->cpu = cpu;
7956         put_cpu();
7957
7958         vmx_segment_cache_clear(vmx);
7959
7960         vmcs12->launch_state = 1;
7961
7962         prepare_vmcs02(vcpu, vmcs12);
7963
7964         /*
7965          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7966          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7967          * returned as far as L1 is concerned. It will only return (and set
7968          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7969          */
7970         return 1;
7971 }
7972
7973 /*
7974  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7975  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7976  * This function returns the new value we should put in vmcs12.guest_cr0.
7977  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7978  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7979  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7980  *     didn't trap the bit, because if L1 did, so would L0).
7981  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7982  *     been modified by L2, and L1 knows it. So just leave the old value of
7983  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7984  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7985  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7986  *     changed these bits, and therefore they need to be updated, but L0
7987  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7988  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7989  */
7990 static inline unsigned long
7991 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7992 {
7993         return
7994         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7995         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7996         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7997                         vcpu->arch.cr0_guest_owned_bits));
7998 }
7999
8000 static inline unsigned long
8001 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8002 {
8003         return
8004         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8005         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8006         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8007                         vcpu->arch.cr4_guest_owned_bits));
8008 }
8009
8010 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8011                                        struct vmcs12 *vmcs12)
8012 {
8013         u32 idt_vectoring;
8014         unsigned int nr;
8015
8016         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8017                 nr = vcpu->arch.exception.nr;
8018                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8019
8020                 if (kvm_exception_is_soft(nr)) {
8021                         vmcs12->vm_exit_instruction_len =
8022                                 vcpu->arch.event_exit_inst_len;
8023                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8024                 } else
8025                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8026
8027                 if (vcpu->arch.exception.has_error_code) {
8028                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8029                         vmcs12->idt_vectoring_error_code =
8030                                 vcpu->arch.exception.error_code;
8031                 }
8032
8033                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8034         } else if (vcpu->arch.nmi_pending) {
8035                 vmcs12->idt_vectoring_info_field =
8036                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8037         } else if (vcpu->arch.interrupt.pending) {
8038                 nr = vcpu->arch.interrupt.nr;
8039                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8040
8041                 if (vcpu->arch.interrupt.soft) {
8042                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8043                         vmcs12->vm_entry_instruction_len =
8044                                 vcpu->arch.event_exit_inst_len;
8045                 } else
8046                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8047
8048                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8049         }
8050 }
8051
8052 /*
8053  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8054  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8055  * and this function updates it to reflect the changes to the guest state while
8056  * L2 was running (and perhaps made some exits which were handled directly by L0
8057  * without going back to L1), and to reflect the exit reason.
8058  * Note that we do not have to copy here all VMCS fields, just those that
8059  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8060  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8061  * which already writes to vmcs12 directly.
8062  */
8063 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8064 {
8065         /* update guest state fields: */
8066         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8067         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8068
8069         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8070         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8071         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8072         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8073
8074         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8075         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8076         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8077         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8078         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8079         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8080         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8081         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8082         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8083         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8084         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8085         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8086         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8087         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8088         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8089         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8090         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8091         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8092         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8093         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8094         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8095         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8096         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8097         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8098         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8099         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8100         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8101         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8102         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8103         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8104         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8105         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8106         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8107         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8108         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8109         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8110
8111         vmcs12->guest_interruptibility_info =
8112                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8113         vmcs12->guest_pending_dbg_exceptions =
8114                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8115
8116         /*
8117          * In some cases (usually, nested EPT), L2 is allowed to change its
8118          * own CR3 without exiting. If it has changed it, we must keep it.
8119          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8120          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8121          *
8122          * Additionally, restore L2's PDPTR to vmcs12.
8123          */
8124         if (enable_ept) {
8125                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8126                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8127                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8128                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8129                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8130         }
8131
8132         vmcs12->vm_entry_controls =
8133                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8134                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8135
8136         /* TODO: These cannot have changed unless we have MSR bitmaps and
8137          * the relevant bit asks not to trap the change */
8138         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8139         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8140                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8141         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8142                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8143         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8144         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8145         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8146
8147         /* update exit information fields: */
8148
8149         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
8150         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8151
8152         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8153         if ((vmcs12->vm_exit_intr_info &
8154              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8155             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8156                 vmcs12->vm_exit_intr_error_code =
8157                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8158         vmcs12->idt_vectoring_info_field = 0;
8159         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8160         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8161
8162         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8163                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8164                  * instead of reading the real value. */
8165                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8166
8167                 /*
8168                  * Transfer the event that L0 or L1 may wanted to inject into
8169                  * L2 to IDT_VECTORING_INFO_FIELD.
8170                  */
8171                 vmcs12_save_pending_event(vcpu, vmcs12);
8172         }
8173
8174         /*
8175          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8176          * preserved above and would only end up incorrectly in L1.
8177          */
8178         vcpu->arch.nmi_injected = false;
8179         kvm_clear_exception_queue(vcpu);
8180         kvm_clear_interrupt_queue(vcpu);
8181 }
8182
8183 /*
8184  * A part of what we need to when the nested L2 guest exits and we want to
8185  * run its L1 parent, is to reset L1's guest state to the host state specified
8186  * in vmcs12.
8187  * This function is to be called not only on normal nested exit, but also on
8188  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8189  * Failures During or After Loading Guest State").
8190  * This function should be called when the active VMCS is L1's (vmcs01).
8191  */
8192 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8193                                    struct vmcs12 *vmcs12)
8194 {
8195         struct kvm_segment seg;
8196
8197         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8198                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8199         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8200                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8201         else
8202                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8203         vmx_set_efer(vcpu, vcpu->arch.efer);
8204
8205         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8206         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8207         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8208         /*
8209          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8210          * actually changed, because it depends on the current state of
8211          * fpu_active (which may have changed).
8212          * Note that vmx_set_cr0 refers to efer set above.
8213          */
8214         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8215         /*
8216          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8217          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8218          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8219          */
8220         update_exception_bitmap(vcpu);
8221         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8222         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8223
8224         /*
8225          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8226          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8227          */
8228         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8229         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8230
8231         if (nested_cpu_has_ept(vmcs12))
8232                 nested_ept_uninit_mmu_context(vcpu);
8233
8234         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8235         kvm_mmu_reset_context(vcpu);
8236
8237         if (enable_vpid) {
8238                 /*
8239                  * Trivially support vpid by letting L2s share their parent
8240                  * L1's vpid. TODO: move to a more elaborate solution, giving
8241                  * each L2 its own vpid and exposing the vpid feature to L1.
8242                  */
8243                 vmx_flush_tlb(vcpu);
8244         }
8245
8246
8247         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8248         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8249         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8250         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8251         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8252
8253         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8254                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8255                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8256         }
8257         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8258                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8259                         vmcs12->host_ia32_perf_global_ctrl);
8260
8261         /* Set L1 segment info according to Intel SDM
8262             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8263         seg = (struct kvm_segment) {
8264                 .base = 0,
8265                 .limit = 0xFFFFFFFF,
8266                 .selector = vmcs12->host_cs_selector,
8267                 .type = 11,
8268                 .present = 1,
8269                 .s = 1,
8270                 .g = 1
8271         };
8272         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8273                 seg.l = 1;
8274         else
8275                 seg.db = 1;
8276         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8277         seg = (struct kvm_segment) {
8278                 .base = 0,
8279                 .limit = 0xFFFFFFFF,
8280                 .type = 3,
8281                 .present = 1,
8282                 .s = 1,
8283                 .db = 1,
8284                 .g = 1
8285         };
8286         seg.selector = vmcs12->host_ds_selector;
8287         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8288         seg.selector = vmcs12->host_es_selector;
8289         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8290         seg.selector = vmcs12->host_ss_selector;
8291         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8292         seg.selector = vmcs12->host_fs_selector;
8293         seg.base = vmcs12->host_fs_base;
8294         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8295         seg.selector = vmcs12->host_gs_selector;
8296         seg.base = vmcs12->host_gs_base;
8297         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8298         seg = (struct kvm_segment) {
8299                 .base = vmcs12->host_tr_base,
8300                 .limit = 0x67,
8301                 .selector = vmcs12->host_tr_selector,
8302                 .type = 11,
8303                 .present = 1
8304         };
8305         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8306
8307         kvm_set_dr(vcpu, 7, 0x400);
8308         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8309 }
8310
8311 /*
8312  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8313  * and modify vmcs12 to make it see what it would expect to see there if
8314  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8315  */
8316 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8317 {
8318         struct vcpu_vmx *vmx = to_vmx(vcpu);
8319         int cpu;
8320         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8321
8322         /* trying to cancel vmlaunch/vmresume is a bug */
8323         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8324
8325         leave_guest_mode(vcpu);
8326         prepare_vmcs12(vcpu, vmcs12);
8327
8328         cpu = get_cpu();
8329         vmx->loaded_vmcs = &vmx->vmcs01;
8330         vmx_vcpu_put(vcpu);
8331         vmx_vcpu_load(vcpu, cpu);
8332         vcpu->cpu = cpu;
8333         put_cpu();
8334
8335         vmx_segment_cache_clear(vmx);
8336
8337         /* if no vmcs02 cache requested, remove the one we used */
8338         if (VMCS02_POOL_SIZE == 0)
8339                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8340
8341         load_vmcs12_host_state(vcpu, vmcs12);
8342
8343         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8344         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8345
8346         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8347         vmx->host_rsp = 0;
8348
8349         /* Unpin physical memory we referred to in vmcs02 */
8350         if (vmx->nested.apic_access_page) {
8351                 nested_release_page(vmx->nested.apic_access_page);
8352                 vmx->nested.apic_access_page = 0;
8353         }
8354
8355         /*
8356          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8357          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8358          * success or failure flag accordingly.
8359          */
8360         if (unlikely(vmx->fail)) {
8361                 vmx->fail = 0;
8362                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8363         } else
8364                 nested_vmx_succeed(vcpu);
8365         if (enable_shadow_vmcs)
8366                 vmx->nested.sync_shadow_vmcs = true;
8367 }
8368
8369 /*
8370  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8371  * 23.7 "VM-entry failures during or after loading guest state" (this also
8372  * lists the acceptable exit-reason and exit-qualification parameters).
8373  * It should only be called before L2 actually succeeded to run, and when
8374  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8375  */
8376 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8377                         struct vmcs12 *vmcs12,
8378                         u32 reason, unsigned long qualification)
8379 {
8380         load_vmcs12_host_state(vcpu, vmcs12);
8381         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8382         vmcs12->exit_qualification = qualification;
8383         nested_vmx_succeed(vcpu);
8384         if (enable_shadow_vmcs)
8385                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8386 }
8387
8388 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8389                                struct x86_instruction_info *info,
8390                                enum x86_intercept_stage stage)
8391 {
8392         return X86EMUL_CONTINUE;
8393 }
8394
8395 static struct kvm_x86_ops vmx_x86_ops = {
8396         .cpu_has_kvm_support = cpu_has_kvm_support,
8397         .disabled_by_bios = vmx_disabled_by_bios,
8398         .hardware_setup = hardware_setup,
8399         .hardware_unsetup = hardware_unsetup,
8400         .check_processor_compatibility = vmx_check_processor_compat,
8401         .hardware_enable = hardware_enable,
8402         .hardware_disable = hardware_disable,
8403         .cpu_has_accelerated_tpr = report_flexpriority,
8404
8405         .vcpu_create = vmx_create_vcpu,
8406         .vcpu_free = vmx_free_vcpu,
8407         .vcpu_reset = vmx_vcpu_reset,
8408
8409         .prepare_guest_switch = vmx_save_host_state,
8410         .vcpu_load = vmx_vcpu_load,
8411         .vcpu_put = vmx_vcpu_put,
8412
8413         .update_db_bp_intercept = update_exception_bitmap,
8414         .get_msr = vmx_get_msr,
8415         .set_msr = vmx_set_msr,
8416         .get_segment_base = vmx_get_segment_base,
8417         .get_segment = vmx_get_segment,
8418         .set_segment = vmx_set_segment,
8419         .get_cpl = vmx_get_cpl,
8420         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8421         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8422         .decache_cr3 = vmx_decache_cr3,
8423         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8424         .set_cr0 = vmx_set_cr0,
8425         .set_cr3 = vmx_set_cr3,
8426         .set_cr4 = vmx_set_cr4,
8427         .set_efer = vmx_set_efer,
8428         .get_idt = vmx_get_idt,
8429         .set_idt = vmx_set_idt,
8430         .get_gdt = vmx_get_gdt,
8431         .set_gdt = vmx_set_gdt,
8432         .set_dr7 = vmx_set_dr7,
8433         .cache_reg = vmx_cache_reg,
8434         .get_rflags = vmx_get_rflags,
8435         .set_rflags = vmx_set_rflags,
8436         .fpu_activate = vmx_fpu_activate,
8437         .fpu_deactivate = vmx_fpu_deactivate,
8438
8439         .tlb_flush = vmx_flush_tlb,
8440
8441         .run = vmx_vcpu_run,
8442         .handle_exit = vmx_handle_exit,
8443         .skip_emulated_instruction = skip_emulated_instruction,
8444         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8445         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8446         .patch_hypercall = vmx_patch_hypercall,
8447         .set_irq = vmx_inject_irq,
8448         .set_nmi = vmx_inject_nmi,
8449         .queue_exception = vmx_queue_exception,
8450         .cancel_injection = vmx_cancel_injection,
8451         .interrupt_allowed = vmx_interrupt_allowed,
8452         .nmi_allowed = vmx_nmi_allowed,
8453         .get_nmi_mask = vmx_get_nmi_mask,
8454         .set_nmi_mask = vmx_set_nmi_mask,
8455         .enable_nmi_window = enable_nmi_window,
8456         .enable_irq_window = enable_irq_window,
8457         .update_cr8_intercept = update_cr8_intercept,
8458         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8459         .vm_has_apicv = vmx_vm_has_apicv,
8460         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8461         .hwapic_irr_update = vmx_hwapic_irr_update,
8462         .hwapic_isr_update = vmx_hwapic_isr_update,
8463         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8464         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8465
8466         .set_tss_addr = vmx_set_tss_addr,
8467         .get_tdp_level = get_ept_level,
8468         .get_mt_mask = vmx_get_mt_mask,
8469
8470         .get_exit_info = vmx_get_exit_info,
8471
8472         .get_lpage_level = vmx_get_lpage_level,
8473
8474         .cpuid_update = vmx_cpuid_update,
8475
8476         .rdtscp_supported = vmx_rdtscp_supported,
8477         .invpcid_supported = vmx_invpcid_supported,
8478
8479         .set_supported_cpuid = vmx_set_supported_cpuid,
8480
8481         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8482
8483         .set_tsc_khz = vmx_set_tsc_khz,
8484         .read_tsc_offset = vmx_read_tsc_offset,
8485         .write_tsc_offset = vmx_write_tsc_offset,
8486         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8487         .compute_tsc_offset = vmx_compute_tsc_offset,
8488         .read_l1_tsc = vmx_read_l1_tsc,
8489
8490         .set_tdp_cr3 = vmx_set_cr3,
8491
8492         .check_intercept = vmx_check_intercept,
8493         .handle_external_intr = vmx_handle_external_intr,
8494 };
8495
8496 static int __init vmx_init(void)
8497 {
8498         int r, i, msr;
8499
8500         rdmsrl_safe(MSR_EFER, &host_efer);
8501
8502         for (i = 0; i < NR_VMX_MSR; ++i)
8503                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8504
8505         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8506         if (!vmx_io_bitmap_a)
8507                 return -ENOMEM;
8508
8509         r = -ENOMEM;
8510
8511         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8512         if (!vmx_io_bitmap_b)
8513                 goto out;
8514
8515         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8516         if (!vmx_msr_bitmap_legacy)
8517                 goto out1;
8518
8519         vmx_msr_bitmap_legacy_x2apic =
8520                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8521         if (!vmx_msr_bitmap_legacy_x2apic)
8522                 goto out2;
8523
8524         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8525         if (!vmx_msr_bitmap_longmode)
8526                 goto out3;
8527
8528         vmx_msr_bitmap_longmode_x2apic =
8529                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8530         if (!vmx_msr_bitmap_longmode_x2apic)
8531                 goto out4;
8532         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8533         if (!vmx_vmread_bitmap)
8534                 goto out5;
8535
8536         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8537         if (!vmx_vmwrite_bitmap)
8538                 goto out6;
8539
8540         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8541         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8542         /* shadowed read/write fields */
8543         for (i = 0; i < max_shadow_read_write_fields; i++) {
8544                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8545                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8546         }
8547         /* shadowed read only fields */
8548         for (i = 0; i < max_shadow_read_only_fields; i++)
8549                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8550
8551         /*
8552          * Allow direct access to the PC debug port (it is often used for I/O
8553          * delays, but the vmexits simply slow things down).
8554          */
8555         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8556         clear_bit(0x80, vmx_io_bitmap_a);
8557
8558         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8559
8560         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8561         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8562
8563         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8564
8565         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8566                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8567         if (r)
8568                 goto out7;
8569
8570 #ifdef CONFIG_KEXEC
8571         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8572                            crash_vmclear_local_loaded_vmcss);
8573 #endif
8574
8575         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8576         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8577         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8578         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8579         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8580         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8581         memcpy(vmx_msr_bitmap_legacy_x2apic,
8582                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8583         memcpy(vmx_msr_bitmap_longmode_x2apic,
8584                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8585
8586         if (enable_apicv) {
8587                 for (msr = 0x800; msr <= 0x8ff; msr++)
8588                         vmx_disable_intercept_msr_read_x2apic(msr);
8589
8590                 /* According SDM, in x2apic mode, the whole id reg is used.
8591                  * But in KVM, it only use the highest eight bits. Need to
8592                  * intercept it */
8593                 vmx_enable_intercept_msr_read_x2apic(0x802);
8594                 /* TMCCT */
8595                 vmx_enable_intercept_msr_read_x2apic(0x839);
8596                 /* TPR */
8597                 vmx_disable_intercept_msr_write_x2apic(0x808);
8598                 /* EOI */
8599                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8600                 /* SELF-IPI */
8601                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8602         }
8603
8604         if (enable_ept) {
8605                 kvm_mmu_set_mask_ptes(0ull,
8606                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8607                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8608                         0ull, VMX_EPT_EXECUTABLE_MASK);
8609                 ept_set_mmio_spte_mask();
8610                 kvm_enable_tdp();
8611         } else
8612                 kvm_disable_tdp();
8613
8614         return 0;
8615
8616 out7:
8617         free_page((unsigned long)vmx_vmwrite_bitmap);
8618 out6:
8619         free_page((unsigned long)vmx_vmread_bitmap);
8620 out5:
8621         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8622 out4:
8623         free_page((unsigned long)vmx_msr_bitmap_longmode);
8624 out3:
8625         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8626 out2:
8627         free_page((unsigned long)vmx_msr_bitmap_legacy);
8628 out1:
8629         free_page((unsigned long)vmx_io_bitmap_b);
8630 out:
8631         free_page((unsigned long)vmx_io_bitmap_a);
8632         return r;
8633 }
8634
8635 static void __exit vmx_exit(void)
8636 {
8637         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8638         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8639         free_page((unsigned long)vmx_msr_bitmap_legacy);
8640         free_page((unsigned long)vmx_msr_bitmap_longmode);
8641         free_page((unsigned long)vmx_io_bitmap_b);
8642         free_page((unsigned long)vmx_io_bitmap_a);
8643         free_page((unsigned long)vmx_vmwrite_bitmap);
8644         free_page((unsigned long)vmx_vmread_bitmap);
8645
8646 #ifdef CONFIG_KEXEC
8647         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8648         synchronize_rcu();
8649 #endif
8650
8651         kvm_exit();
8652 }
8653
8654 module_init(vmx_init)
8655 module_exit(vmx_exit)