Pileus Git - ~andy/linux/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376         u64 msr_ia32_feature_control;
 377 };
 378
 379 #define POSTED_INTR_ON  0
 380 /* Posted-Interrupt Descriptor */
 381 struct pi_desc {
 382         u32 pir[8];     /* Posted interrupt requested */
 383         u32 control;    /* bit 0 of control is outstanding notification bit */
 384         u32 rsvd[7];
 385 } __aligned(64);
 386
 387 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 388 {
 389         return test_and_set_bit(POSTED_INTR_ON,
 390                         (unsigned long *)&pi_desc->control);
 391 }
 392
 393 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 394 {
 395         return test_and_clear_bit(POSTED_INTR_ON,
 396                         (unsigned long *)&pi_desc->control);
 397 }
 398
 399 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 400 {
 401         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 402 }
 403
 404 struct vcpu_vmx {
 405         struct kvm_vcpu       vcpu;
 406         unsigned long         host_rsp;
 407         u8                    fail;
 408         u8                    cpl;
 409         bool                  nmi_known_unmasked;
 410         u32                   exit_intr_info;
 411         u32                   idt_vectoring_info;
 412         ulong                 rflags;
 413         struct shared_msr_entry *guest_msrs;
 414         int                   nmsrs;
 415         int                   save_nmsrs;
 416         unsigned long         host_idt_base;
 417 #ifdef CONFIG_X86_64
 418         u64                   msr_host_kernel_gs_base;
 419         u64                   msr_guest_kernel_gs_base;
 420 #endif
 421         /*
 422          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 423          * non-nested (L1) guest, it always points to vmcs01. For a nested
 424          * guest (L2), it points to a different VMCS.
 425          */
 426         struct loaded_vmcs    vmcs01;
 427         struct loaded_vmcs   *loaded_vmcs;
 428         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 429         struct msr_autoload {
 430                 unsigned nr;
 431                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 432                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 433         } msr_autoload;
 434         struct {
 435                 int           loaded;
 436                 u16           fs_sel, gs_sel, ldt_sel;
 437 #ifdef CONFIG_X86_64
 438                 u16           ds_sel, es_sel;
 439 #endif
 440                 int           gs_ldt_reload_needed;
 441                 int           fs_reload_needed;
 442         } host_state;
 443         struct {
 444                 int vm86_active;
 445                 ulong save_rflags;
 446                 struct kvm_segment segs[8];
 447         } rmode;
 448         struct {
 449                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 450                 struct kvm_save_segment {
 451                         u16 selector;
 452                         unsigned long base;
 453                         u32 limit;
 454                         u32 ar;
 455                 } seg[8];
 456         } segment_cache;
 457         int vpid;
 458         bool emulation_required;
 459
 460         /* Support for vnmi-less CPUs */
 461         int soft_vnmi_blocked;
 462         ktime_t entry_time;
 463         s64 vnmi_blocked_time;
 464         u32 exit_reason;
 465
 466         bool rdtscp_enabled;
 467
 468         /* Posted interrupt descriptor */
 469         struct pi_desc pi_desc;
 470
 471         /* Support for a guest hypervisor (nested VMX) */
 472         struct nested_vmx nested;
 473 };
 474
 475 enum segment_cache_field {
 476         SEG_FIELD_SEL = 0,
 477         SEG_FIELD_BASE = 1,
 478         SEG_FIELD_LIMIT = 2,
 479         SEG_FIELD_AR = 3,
 480
 481         SEG_FIELD_NR = 4
 482 };
 483
 484 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 485 {
 486         return container_of(vcpu, struct vcpu_vmx, vcpu);
 487 }
 488
 489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 490 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 491 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 492                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 493
 494
 495 static const unsigned long shadow_read_only_fields[] = {
 496         /*
 497          * We do NOT shadow fields that are modified when L0
 498          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 499          * VMXON...) executed by L1.
 500          * For example, VM_INSTRUCTION_ERROR is read
 501          * by L1 if a vmx instruction fails (part of the error path).
 502          * Note the code assumes this logic. If for some reason
 503          * we start shadowing these fields then we need to
 504          * force a shadow sync when L0 emulates vmx instructions
 505          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 506          * by nested_vmx_failValid)
 507          */
 508         VM_EXIT_REASON,
 509         VM_EXIT_INTR_INFO,
 510         VM_EXIT_INSTRUCTION_LEN,
 511         IDT_VECTORING_INFO_FIELD,
 512         IDT_VECTORING_ERROR_CODE,
 513         VM_EXIT_INTR_ERROR_CODE,
 514         EXIT_QUALIFICATION,
 515         GUEST_LINEAR_ADDRESS,
 516         GUEST_PHYSICAL_ADDRESS
 517 };
 518 static const int max_shadow_read_only_fields =
 519         ARRAY_SIZE(shadow_read_only_fields);
 520
 521 static const unsigned long shadow_read_write_fields[] = {
 522         GUEST_RIP,
 523         GUEST_RSP,
 524         GUEST_CR0,
 525         GUEST_CR3,
 526         GUEST_CR4,
 527         GUEST_INTERRUPTIBILITY_INFO,
 528         GUEST_RFLAGS,
 529         GUEST_CS_SELECTOR,
 530         GUEST_CS_AR_BYTES,
 531         GUEST_CS_LIMIT,
 532         GUEST_CS_BASE,
 533         GUEST_ES_BASE,
 534         CR0_GUEST_HOST_MASK,
 535         CR0_READ_SHADOW,
 536         CR4_READ_SHADOW,
 537         TSC_OFFSET,
 538         EXCEPTION_BITMAP,
 539         CPU_BASED_VM_EXEC_CONTROL,
 540         VM_ENTRY_EXCEPTION_ERROR_CODE,
 541         VM_ENTRY_INTR_INFO_FIELD,
 542         VM_ENTRY_INSTRUCTION_LEN,
 543         VM_ENTRY_EXCEPTION_ERROR_CODE,
 544         HOST_FS_BASE,
 545         HOST_GS_BASE,
 546         HOST_FS_SELECTOR,
 547         HOST_GS_SELECTOR
 548 };
 549 static const int max_shadow_read_write_fields =
 550         ARRAY_SIZE(shadow_read_write_fields);
 551
 552 static const unsigned short vmcs_field_to_offset_table[] = {
 553         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 554         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 555         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 556         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 557         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 558         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 559         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 560         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 561         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 562         FIELD(HOST_ES_SELECTOR, host_es_selector),
 563         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 564         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 565         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 566         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 567         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 568         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 569         FIELD64(IO_BITMAP_A, io_bitmap_a),
 570         FIELD64(IO_BITMAP_B, io_bitmap_b),
 571         FIELD64(MSR_BITMAP, msr_bitmap),
 572         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 573         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 574         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 575         FIELD64(TSC_OFFSET, tsc_offset),
 576         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 577         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 578         FIELD64(EPT_POINTER, ept_pointer),
 579         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 580         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 581         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 582         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 583         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 584         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 585         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 586         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 587         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 588         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 589         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 590         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 591         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 592         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 593         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 594         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 595         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 596         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 597         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 598         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 599         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 600         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 601         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 602         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 603         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 604         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 605         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 606         FIELD(TPR_THRESHOLD, tpr_threshold),
 607         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 608         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 609         FIELD(VM_EXIT_REASON, vm_exit_reason),
 610         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 611         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 612         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 613         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 614         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 615         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 616         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 617         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 618         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 619         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 620         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 621         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 622         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 623         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 624         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 625         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 626         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 627         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 628         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 629         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 630         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 631         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 632         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 633         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 634         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 635         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 636         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 637         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 638         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 639         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 640         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 641         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 642         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 643         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 644         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 645         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 646         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 647         FIELD(EXIT_QUALIFICATION, exit_qualification),
 648         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 649         FIELD(GUEST_CR0, guest_cr0),
 650         FIELD(GUEST_CR3, guest_cr3),
 651         FIELD(GUEST_CR4, guest_cr4),
 652         FIELD(GUEST_ES_BASE, guest_es_base),
 653         FIELD(GUEST_CS_BASE, guest_cs_base),
 654         FIELD(GUEST_SS_BASE, guest_ss_base),
 655         FIELD(GUEST_DS_BASE, guest_ds_base),
 656         FIELD(GUEST_FS_BASE, guest_fs_base),
 657         FIELD(GUEST_GS_BASE, guest_gs_base),
 658         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 659         FIELD(GUEST_TR_BASE, guest_tr_base),
 660         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 661         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 662         FIELD(GUEST_DR7, guest_dr7),
 663         FIELD(GUEST_RSP, guest_rsp),
 664         FIELD(GUEST_RIP, guest_rip),
 665         FIELD(GUEST_RFLAGS, guest_rflags),
 666         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 667         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 668         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 669         FIELD(HOST_CR0, host_cr0),
 670         FIELD(HOST_CR3, host_cr3),
 671         FIELD(HOST_CR4, host_cr4),
 672         FIELD(HOST_FS_BASE, host_fs_base),
 673         FIELD(HOST_GS_BASE, host_gs_base),
 674         FIELD(HOST_TR_BASE, host_tr_base),
 675         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 676         FIELD(HOST_IDTR_BASE, host_idtr_base),
 677         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 678         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 679         FIELD(HOST_RSP, host_rsp),
 680         FIELD(HOST_RIP, host_rip),
 681 };
 682 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 683
 684 static inline short vmcs_field_to_offset(unsigned long field)
 685 {
 686         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 687                 return -1;
 688         return vmcs_field_to_offset_table[field];
 689 }
 690
 691 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 692 {
 693         return to_vmx(vcpu)->nested.current_vmcs12;
 694 }
 695
 696 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 697 {
 698         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 699         if (is_error_page(page))
 700                 return NULL;
 701
 702         return page;
 703 }
 704
 705 static void nested_release_page(struct page *page)
 706 {
 707         kvm_release_page_dirty(page);
 708 }
 709
 710 static void nested_release_page_clean(struct page *page)
 711 {
 712         kvm_release_page_clean(page);
 713 }
 714
 715 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 716 static u64 construct_eptp(unsigned long root_hpa);
 717 static void kvm_cpu_vmxon(u64 addr);
 718 static void kvm_cpu_vmxoff(void);
 719 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 720 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 721                             struct kvm_segment *var, int seg);
 722 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 723                             struct kvm_segment *var, int seg);
 724 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 725 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 726 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 727 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 728 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 729
 730 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 731 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 732 /*
 733  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 734  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 735  */
 736 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 737 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 738
 739 static unsigned long *vmx_io_bitmap_a;
 740 static unsigned long *vmx_io_bitmap_b;
 741 static unsigned long *vmx_msr_bitmap_legacy;
 742 static unsigned long *vmx_msr_bitmap_longmode;
 743 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 744 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 745 static unsigned long *vmx_vmread_bitmap;
 746 static unsigned long *vmx_vmwrite_bitmap;
 747
 748 static bool cpu_has_load_ia32_efer;
 749 static bool cpu_has_load_perf_global_ctrl;
 750
 751 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 752 static DEFINE_SPINLOCK(vmx_vpid_lock);
 753
 754 static struct vmcs_config {
 755         int size;
 756         int order;
 757         u32 revision_id;
 758         u32 pin_based_exec_ctrl;
 759         u32 cpu_based_exec_ctrl;
 760         u32 cpu_based_2nd_exec_ctrl;
 761         u32 vmexit_ctrl;
 762         u32 vmentry_ctrl;
 763 } vmcs_config;
 764
 765 static struct vmx_capability {
 766         u32 ept;
 767         u32 vpid;
 768 } vmx_capability;
 769
 770 #define VMX_SEGMENT_FIELD(seg)                                  \
 771         [VCPU_SREG_##seg] = {                                   \
 772                 .selector = GUEST_##seg##_SELECTOR,             \
 773                 .base = GUEST_##seg##_BASE,                     \
 774                 .limit = GUEST_##seg##_LIMIT,                   \
 775                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 776         }
 777
 778 static const struct kvm_vmx_segment_field {
 779         unsigned selector;
 780         unsigned base;
 781         unsigned limit;
 782         unsigned ar_bytes;
 783 } kvm_vmx_segment_fields[] = {
 784         VMX_SEGMENT_FIELD(CS),
 785         VMX_SEGMENT_FIELD(DS),
 786         VMX_SEGMENT_FIELD(ES),
 787         VMX_SEGMENT_FIELD(FS),
 788         VMX_SEGMENT_FIELD(GS),
 789         VMX_SEGMENT_FIELD(SS),
 790         VMX_SEGMENT_FIELD(TR),
 791         VMX_SEGMENT_FIELD(LDTR),
 792 };
 793
 794 static u64 host_efer;
 795
 796 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 797
 798 /*
 799  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 800  * away by decrementing the array size.
 801  */
 802 static const u32 vmx_msr_index[] = {
 803 #ifdef CONFIG_X86_64
 804         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 805 #endif
 806         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 807 };
 808 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 809
 810 static inline bool is_page_fault(u32 intr_info)
 811 {
 812         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 813                              INTR_INFO_VALID_MASK)) ==
 814                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 815 }
 816
 817 static inline bool is_no_device(u32 intr_info)
 818 {
 819         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 820                              INTR_INFO_VALID_MASK)) ==
 821                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 822 }
 823
 824 static inline bool is_invalid_opcode(u32 intr_info)
 825 {
 826         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 827                              INTR_INFO_VALID_MASK)) ==
 828                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 829 }
 830
 831 static inline bool is_external_interrupt(u32 intr_info)
 832 {
 833         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 834                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 835 }
 836
 837 static inline bool is_machine_check(u32 intr_info)
 838 {
 839         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 840                              INTR_INFO_VALID_MASK)) ==
 841                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 842 }
 843
 844 static inline bool cpu_has_vmx_msr_bitmap(void)
 845 {
 846         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 847 }
 848
 849 static inline bool cpu_has_vmx_tpr_shadow(void)
 850 {
 851         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 852 }
 853
 854 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 855 {
 856         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 857 }
 858
 859 static inline bool cpu_has_secondary_exec_ctrls(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl &
 862                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 863 }
 864
 865 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 866 {
 867         return vmcs_config.cpu_based_2nd_exec_ctrl &
 868                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 869 }
 870
 871 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 872 {
 873         return vmcs_config.cpu_based_2nd_exec_ctrl &
 874                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 875 }
 876
 877 static inline bool cpu_has_vmx_apic_register_virt(void)
 878 {
 879         return vmcs_config.cpu_based_2nd_exec_ctrl &
 880                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 881 }
 882
 883 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 884 {
 885         return vmcs_config.cpu_based_2nd_exec_ctrl &
 886                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 887 }
 888
 889 static inline bool cpu_has_vmx_posted_intr(void)
 890 {
 891         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 892 }
 893
 894 static inline bool cpu_has_vmx_apicv(void)
 895 {
 896         return cpu_has_vmx_apic_register_virt() &&
 897                 cpu_has_vmx_virtual_intr_delivery() &&
 898                 cpu_has_vmx_posted_intr();
 899 }
 900
 901 static inline bool cpu_has_vmx_flexpriority(void)
 902 {
 903         return cpu_has_vmx_tpr_shadow() &&
 904                 cpu_has_vmx_virtualize_apic_accesses();
 905 }
 906
 907 static inline bool cpu_has_vmx_ept_execute_only(void)
 908 {
 909         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 910 }
 911
 912 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 913 {
 914         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 915 }
 916
 917 static inline bool cpu_has_vmx_eptp_writeback(void)
 918 {
 919         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_2m_page(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_ept_1g_page(void)
 928 {
 929         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_ept_4levels(void)
 933 {
 934         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_ad_bits(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_AD_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_invept_context(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_invept_global(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_invvpid_single(void)
 953 {
 954         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invvpid_global(void)
 958 {
 959         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_ept(void)
 963 {
 964         return vmcs_config.cpu_based_2nd_exec_ctrl &
 965                 SECONDARY_EXEC_ENABLE_EPT;
 966 }
 967
 968 static inline bool cpu_has_vmx_unrestricted_guest(void)
 969 {
 970         return vmcs_config.cpu_based_2nd_exec_ctrl &
 971                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 972 }
 973
 974 static inline bool cpu_has_vmx_ple(void)
 975 {
 976         return vmcs_config.cpu_based_2nd_exec_ctrl &
 977                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 978 }
 979
 980 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 981 {
 982         return flexpriority_enabled && irqchip_in_kernel(kvm);
 983 }
 984
 985 static inline bool cpu_has_vmx_vpid(void)
 986 {
 987         return vmcs_config.cpu_based_2nd_exec_ctrl &
 988                 SECONDARY_EXEC_ENABLE_VPID;
 989 }
 990
 991 static inline bool cpu_has_vmx_rdtscp(void)
 992 {
 993         return vmcs_config.cpu_based_2nd_exec_ctrl &
 994                 SECONDARY_EXEC_RDTSCP;
 995 }
 996
 997 static inline bool cpu_has_vmx_invpcid(void)
 998 {
 999         return vmcs_config.cpu_based_2nd_exec_ctrl &
1000                 SECONDARY_EXEC_ENABLE_INVPCID;
1001 }
1002
1003 static inline bool cpu_has_virtual_nmis(void)
1004 {
1005         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006 }
1007
1008 static inline bool cpu_has_vmx_wbinvd_exit(void)
1009 {
1010         return vmcs_config.cpu_based_2nd_exec_ctrl &
1011                 SECONDARY_EXEC_WBINVD_EXITING;
1012 }
1013
1014 static inline bool cpu_has_vmx_shadow_vmcs(void)
1015 {
1016         u64 vmx_msr;
1017         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018         /* check if the cpu supports writing r/o exit information fields */
1019         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020                 return false;
1021
1022         return vmcs_config.cpu_based_2nd_exec_ctrl &
1023                 SECONDARY_EXEC_SHADOW_VMCS;
1024 }
1025
1026 static inline bool report_flexpriority(void)
1027 {
1028         return flexpriority_enabled;
1029 }
1030
1031 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032 {
1033         return vmcs12->cpu_based_vm_exec_control & bit;
1034 }
1035
1036 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037 {
1038         return (vmcs12->cpu_based_vm_exec_control &
1039                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040                 (vmcs12->secondary_vm_exec_control & bit);
1041 }
1042
1043 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1044 {
1045         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046 }
1047
1048 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1049 {
1050         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1051 }
1052
1053 static inline bool is_exception(u32 intr_info)
1054 {
1055         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1057 }
1058
1059 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1060 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061                         struct vmcs12 *vmcs12,
1062                         u32 reason, unsigned long qualification);
1063
1064 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1065 {
1066         int i;
1067
1068         for (i = 0; i < vmx->nmsrs; ++i)
1069                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1070                         return i;
1071         return -1;
1072 }
1073
1074 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1075 {
1076     struct {
1077         u64 vpid : 16;
1078         u64 rsvd : 48;
1079         u64 gva;
1080     } operand = { vpid, 0, gva };
1081
1082     asm volatile (__ex(ASM_VMX_INVVPID)
1083                   /* CF==1 or ZF==1 --> rc = -1 */
1084                   "; ja 1f ; ud2 ; 1:"
1085                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1086 }
1087
1088 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1089 {
1090         struct {
1091                 u64 eptp, gpa;
1092         } operand = {eptp, gpa};
1093
1094         asm volatile (__ex(ASM_VMX_INVEPT)
1095                         /* CF==1 or ZF==1 --> rc = -1 */
1096                         "; ja 1f ; ud2 ; 1:\n"
1097                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1098 }
1099
1100 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1101 {
1102         int i;
1103
1104         i = __find_msr_index(vmx, msr);
1105         if (i >= 0)
1106                 return &vmx->guest_msrs[i];
1107         return NULL;
1108 }
1109
1110 static void vmcs_clear(struct vmcs *vmcs)
1111 {
1112         u64 phys_addr = __pa(vmcs);
1113         u8 error;
1114
1115         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1116                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1117                       : "cc", "memory");
1118         if (error)
1119                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1120                        vmcs, phys_addr);
1121 }
1122
1123 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1124 {
1125         vmcs_clear(loaded_vmcs->vmcs);
1126         loaded_vmcs->cpu = -1;
1127         loaded_vmcs->launched = 0;
1128 }
1129
1130 static void vmcs_load(struct vmcs *vmcs)
1131 {
1132         u64 phys_addr = __pa(vmcs);
1133         u8 error;
1134
1135         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1136                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1137                         : "cc", "memory");
1138         if (error)
1139                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1140                        vmcs, phys_addr);
1141 }
1142
1143 #ifdef CONFIG_KEXEC
1144 /*
1145  * This bitmap is used to indicate whether the vmclear
1146  * operation is enabled on all cpus. All disabled by
1147  * default.
1148  */
1149 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1150
1151 static inline void crash_enable_local_vmclear(int cpu)
1152 {
1153         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154 }
1155
1156 static inline void crash_disable_local_vmclear(int cpu)
1157 {
1158         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159 }
1160
1161 static inline int crash_local_vmclear_enabled(int cpu)
1162 {
1163         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164 }
1165
1166 static void crash_vmclear_local_loaded_vmcss(void)
1167 {
1168         int cpu = raw_smp_processor_id();
1169         struct loaded_vmcs *v;
1170
1171         if (!crash_local_vmclear_enabled(cpu))
1172                 return;
1173
1174         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175                             loaded_vmcss_on_cpu_link)
1176                 vmcs_clear(v->vmcs);
1177 }
1178 #else
1179 static inline void crash_enable_local_vmclear(int cpu) { }
1180 static inline void crash_disable_local_vmclear(int cpu) { }
1181 #endif /* CONFIG_KEXEC */
1182
1183 static void __loaded_vmcs_clear(void *arg)
1184 {
1185         struct loaded_vmcs *loaded_vmcs = arg;
1186         int cpu = raw_smp_processor_id();
1187
1188         if (loaded_vmcs->cpu != cpu)
1189                 return; /* vcpu migration can race with cpu offline */
1190         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1191                 per_cpu(current_vmcs, cpu) = NULL;
1192         crash_disable_local_vmclear(cpu);
1193         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1194
1195         /*
1196          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197          * is before setting loaded_vmcs->vcpu to -1 which is done in
1198          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199          * then adds the vmcs into percpu list before it is deleted.
1200          */
1201         smp_wmb();
1202
1203         loaded_vmcs_init(loaded_vmcs);
1204         crash_enable_local_vmclear(cpu);
1205 }
1206
1207 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1208 {
1209         int cpu = loaded_vmcs->cpu;
1210
1211         if (cpu != -1)
1212                 smp_call_function_single(cpu,
1213                          __loaded_vmcs_clear, loaded_vmcs, 1);
1214 }
1215
1216 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1217 {
1218         if (vmx->vpid == 0)
1219                 return;
1220
1221         if (cpu_has_vmx_invvpid_single())
1222                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1223 }
1224
1225 static inline void vpid_sync_vcpu_global(void)
1226 {
1227         if (cpu_has_vmx_invvpid_global())
1228                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1229 }
1230
1231 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1232 {
1233         if (cpu_has_vmx_invvpid_single())
1234                 vpid_sync_vcpu_single(vmx);
1235         else
1236                 vpid_sync_vcpu_global();
1237 }
1238
1239 static inline void ept_sync_global(void)
1240 {
1241         if (cpu_has_vmx_invept_global())
1242                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1243 }
1244
1245 static inline void ept_sync_context(u64 eptp)
1246 {
1247         if (enable_ept) {
1248                 if (cpu_has_vmx_invept_context())
1249                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1250                 else
1251                         ept_sync_global();
1252         }
1253 }
1254
1255 static __always_inline unsigned long vmcs_readl(unsigned long field)
1256 {
1257         unsigned long value;
1258
1259         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260                       : "=a"(value) : "d"(field) : "cc");
1261         return value;
1262 }
1263
1264 static __always_inline u16 vmcs_read16(unsigned long field)
1265 {
1266         return vmcs_readl(field);
1267 }
1268
1269 static __always_inline u32 vmcs_read32(unsigned long field)
1270 {
1271         return vmcs_readl(field);
1272 }
1273
1274 static __always_inline u64 vmcs_read64(unsigned long field)
1275 {
1276 #ifdef CONFIG_X86_64
1277         return vmcs_readl(field);
1278 #else
1279         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1280 #endif
1281 }
1282
1283 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1284 {
1285         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1287         dump_stack();
1288 }
1289
1290 static void vmcs_writel(unsigned long field, unsigned long value)
1291 {
1292         u8 error;
1293
1294         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1295                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1296         if (unlikely(error))
1297                 vmwrite_error(field, value);
1298 }
1299
1300 static void vmcs_write16(unsigned long field, u16 value)
1301 {
1302         vmcs_writel(field, value);
1303 }
1304
1305 static void vmcs_write32(unsigned long field, u32 value)
1306 {
1307         vmcs_writel(field, value);
1308 }
1309
1310 static void vmcs_write64(unsigned long field, u64 value)
1311 {
1312         vmcs_writel(field, value);
1313 #ifndef CONFIG_X86_64
1314         asm volatile ("");
1315         vmcs_writel(field+1, value >> 32);
1316 #endif
1317 }
1318
1319 static void vmcs_clear_bits(unsigned long field, u32 mask)
1320 {
1321         vmcs_writel(field, vmcs_readl(field) & ~mask);
1322 }
1323
1324 static void vmcs_set_bits(unsigned long field, u32 mask)
1325 {
1326         vmcs_writel(field, vmcs_readl(field) | mask);
1327 }
1328
1329 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1330 {
1331         vmx->segment_cache.bitmask = 0;
1332 }
1333
1334 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1335                                        unsigned field)
1336 {
1337         bool ret;
1338         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1339
1340         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342                 vmx->segment_cache.bitmask = 0;
1343         }
1344         ret = vmx->segment_cache.bitmask & mask;
1345         vmx->segment_cache.bitmask |= mask;
1346         return ret;
1347 }
1348
1349 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1350 {
1351         u16 *p = &vmx->segment_cache.seg[seg].selector;
1352
1353         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1355         return *p;
1356 }
1357
1358 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1359 {
1360         ulong *p = &vmx->segment_cache.seg[seg].base;
1361
1362         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1364         return *p;
1365 }
1366
1367 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1368 {
1369         u32 *p = &vmx->segment_cache.seg[seg].limit;
1370
1371         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1373         return *p;
1374 }
1375
1376 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1377 {
1378         u32 *p = &vmx->segment_cache.seg[seg].ar;
1379
1380         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1382         return *p;
1383 }
1384
1385 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1386 {
1387         u32 eb;
1388
1389         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391         if ((vcpu->guest_debug &
1392              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394                 eb |= 1u << BP_VECTOR;
1395         if (to_vmx(vcpu)->rmode.vm86_active)
1396                 eb = ~0;
1397         if (enable_ept)
1398                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1399         if (vcpu->fpu_active)
1400                 eb &= ~(1u << NM_VECTOR);
1401
1402         /* When we are running a nested L2 guest and L1 specified for it a
1403          * certain exception bitmap, we must trap the same exceptions and pass
1404          * them to L1. When running L2, we will only handle the exceptions
1405          * specified above if L1 did not want them.
1406          */
1407         if (is_guest_mode(vcpu))
1408                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1409
1410         vmcs_write32(EXCEPTION_BITMAP, eb);
1411 }
1412
1413 static void clear_atomic_switch_msr_special(unsigned long entry,
1414                 unsigned long exit)
1415 {
1416         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1418 }
1419
1420 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1421 {
1422         unsigned i;
1423         struct msr_autoload *m = &vmx->msr_autoload;
1424
1425         switch (msr) {
1426         case MSR_EFER:
1427                 if (cpu_has_load_ia32_efer) {
1428                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429                                         VM_EXIT_LOAD_IA32_EFER);
1430                         return;
1431                 }
1432                 break;
1433         case MSR_CORE_PERF_GLOBAL_CTRL:
1434                 if (cpu_has_load_perf_global_ctrl) {
1435                         clear_atomic_switch_msr_special(
1436                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1438                         return;
1439                 }
1440                 break;
1441         }
1442
1443         for (i = 0; i < m->nr; ++i)
1444                 if (m->guest[i].index == msr)
1445                         break;
1446
1447         if (i == m->nr)
1448                 return;
1449         --m->nr;
1450         m->guest[i] = m->guest[m->nr];
1451         m->host[i] = m->host[m->nr];
1452         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1454 }
1455
1456 static void add_atomic_switch_msr_special(unsigned long entry,
1457                 unsigned long exit, unsigned long guest_val_vmcs,
1458                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1459 {
1460         vmcs_write64(guest_val_vmcs, guest_val);
1461         vmcs_write64(host_val_vmcs, host_val);
1462         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1464 }
1465
1466 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467                                   u64 guest_val, u64 host_val)
1468 {
1469         unsigned i;
1470         struct msr_autoload *m = &vmx->msr_autoload;
1471
1472         switch (msr) {
1473         case MSR_EFER:
1474                 if (cpu_has_load_ia32_efer) {
1475                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476                                         VM_EXIT_LOAD_IA32_EFER,
1477                                         GUEST_IA32_EFER,
1478                                         HOST_IA32_EFER,
1479                                         guest_val, host_val);
1480                         return;
1481                 }
1482                 break;
1483         case MSR_CORE_PERF_GLOBAL_CTRL:
1484                 if (cpu_has_load_perf_global_ctrl) {
1485                         add_atomic_switch_msr_special(
1486                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1489                                         HOST_IA32_PERF_GLOBAL_CTRL,
1490                                         guest_val, host_val);
1491                         return;
1492                 }
1493                 break;
1494         }
1495
1496         for (i = 0; i < m->nr; ++i)
1497                 if (m->guest[i].index == msr)
1498                         break;
1499
1500         if (i == NR_AUTOLOAD_MSRS) {
1501                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1502                                 "Can't add msr %x\n", msr);
1503                 return;
1504         } else if (i == m->nr) {
1505                 ++m->nr;
1506                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1508         }
1509
1510         m->guest[i].index = msr;
1511         m->guest[i].value = guest_val;
1512         m->host[i].index = msr;
1513         m->host[i].value = host_val;
1514 }
1515
1516 static void reload_tss(void)
1517 {
1518         /*
1519          * VT restores TR but not its size.  Useless.
1520          */
1521         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1522         struct desc_struct *descs;
1523
1524         descs = (void *)gdt->address;
1525         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1526         load_TR_desc();
1527 }
1528
1529 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1530 {
1531         u64 guest_efer;
1532         u64 ignore_bits;
1533
1534         guest_efer = vmx->vcpu.arch.efer;
1535
1536         /*
1537          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1538          * outside long mode
1539          */
1540         ignore_bits = EFER_NX | EFER_SCE;
1541 #ifdef CONFIG_X86_64
1542         ignore_bits |= EFER_LMA | EFER_LME;
1543         /* SCE is meaningful only in long mode on Intel */
1544         if (guest_efer & EFER_LMA)
1545                 ignore_bits &= ~(u64)EFER_SCE;
1546 #endif
1547         guest_efer &= ~ignore_bits;
1548         guest_efer |= host_efer & ignore_bits;
1549         vmx->guest_msrs[efer_offset].data = guest_efer;
1550         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1551
1552         clear_atomic_switch_msr(vmx, MSR_EFER);
1553         /* On ept, can't emulate nx, and must switch nx atomically */
1554         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555                 guest_efer = vmx->vcpu.arch.efer;
1556                 if (!(guest_efer & EFER_LMA))
1557                         guest_efer &= ~EFER_LME;
1558                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1559                 return false;
1560         }
1561
1562         return true;
1563 }
1564
1565 static unsigned long segment_base(u16 selector)
1566 {
1567         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1568         struct desc_struct *d;
1569         unsigned long table_base;
1570         unsigned long v;
1571
1572         if (!(selector & ~3))
1573                 return 0;
1574
1575         table_base = gdt->address;
1576
1577         if (selector & 4) {           /* from ldt */
1578                 u16 ldt_selector = kvm_read_ldt();
1579
1580                 if (!(ldt_selector & ~3))
1581                         return 0;
1582
1583                 table_base = segment_base(ldt_selector);
1584         }
1585         d = (struct desc_struct *)(table_base + (selector & ~7));
1586         v = get_desc_base(d);
1587 #ifdef CONFIG_X86_64
1588        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1590 #endif
1591         return v;
1592 }
1593
1594 static inline unsigned long kvm_read_tr_base(void)
1595 {
1596         u16 tr;
1597         asm("str %0" : "=g"(tr));
1598         return segment_base(tr);
1599 }
1600
1601 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1602 {
1603         struct vcpu_vmx *vmx = to_vmx(vcpu);
1604         int i;
1605
1606         if (vmx->host_state.loaded)
1607                 return;
1608
1609         vmx->host_state.loaded = 1;
1610         /*
1611          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1612          * allow segment selectors with cpl > 0 or ti == 1.
1613          */
1614         vmx->host_state.ldt_sel = kvm_read_ldt();
1615         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1616         savesegment(fs, vmx->host_state.fs_sel);
1617         if (!(vmx->host_state.fs_sel & 7)) {
1618                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1619                 vmx->host_state.fs_reload_needed = 0;
1620         } else {
1621                 vmcs_write16(HOST_FS_SELECTOR, 0);
1622                 vmx->host_state.fs_reload_needed = 1;
1623         }
1624         savesegment(gs, vmx->host_state.gs_sel);
1625         if (!(vmx->host_state.gs_sel & 7))
1626                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1627         else {
1628                 vmcs_write16(HOST_GS_SELECTOR, 0);
1629                 vmx->host_state.gs_ldt_reload_needed = 1;
1630         }
1631
1632 #ifdef CONFIG_X86_64
1633         savesegment(ds, vmx->host_state.ds_sel);
1634         savesegment(es, vmx->host_state.es_sel);
1635 #endif
1636
1637 #ifdef CONFIG_X86_64
1638         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1640 #else
1641         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1643 #endif
1644
1645 #ifdef CONFIG_X86_64
1646         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647         if (is_long_mode(&vmx->vcpu))
1648                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1649 #endif
1650         for (i = 0; i < vmx->save_nmsrs; ++i)
1651                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1652                                    vmx->guest_msrs[i].data,
1653                                    vmx->guest_msrs[i].mask);
1654 }
1655
1656 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1657 {
1658         if (!vmx->host_state.loaded)
1659                 return;
1660
1661         ++vmx->vcpu.stat.host_state_reload;
1662         vmx->host_state.loaded = 0;
1663 #ifdef CONFIG_X86_64
1664         if (is_long_mode(&vmx->vcpu))
1665                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1666 #endif
1667         if (vmx->host_state.gs_ldt_reload_needed) {
1668                 kvm_load_ldt(vmx->host_state.ldt_sel);
1669 #ifdef CONFIG_X86_64
1670                 load_gs_index(vmx->host_state.gs_sel);
1671 #else
1672                 loadsegment(gs, vmx->host_state.gs_sel);
1673 #endif
1674         }
1675         if (vmx->host_state.fs_reload_needed)
1676                 loadsegment(fs, vmx->host_state.fs_sel);
1677 #ifdef CONFIG_X86_64
1678         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679                 loadsegment(ds, vmx->host_state.ds_sel);
1680                 loadsegment(es, vmx->host_state.es_sel);
1681         }
1682 #endif
1683         reload_tss();
1684 #ifdef CONFIG_X86_64
1685         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1686 #endif
1687         /*
1688          * If the FPU is not active (through the host task or
1689          * the guest vcpu), then restore the cr0.TS bit.
1690          */
1691         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1692                 stts();
1693         load_gdt(&__get_cpu_var(host_gdt));
1694 }
1695
1696 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1697 {
1698         preempt_disable();
1699         __vmx_load_host_state(vmx);
1700         preempt_enable();
1701 }
1702
1703 /*
1704  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705  * vcpu mutex is already taken.
1706  */
1707 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1708 {
1709         struct vcpu_vmx *vmx = to_vmx(vcpu);
1710         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1711
1712         if (!vmm_exclusive)
1713                 kvm_cpu_vmxon(phys_addr);
1714         else if (vmx->loaded_vmcs->cpu != cpu)
1715                 loaded_vmcs_clear(vmx->loaded_vmcs);
1716
1717         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719                 vmcs_load(vmx->loaded_vmcs->vmcs);
1720         }
1721
1722         if (vmx->loaded_vmcs->cpu != cpu) {
1723                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1724                 unsigned long sysenter_esp;
1725
1726                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1727                 local_irq_disable();
1728                 crash_disable_local_vmclear(cpu);
1729
1730                 /*
1731                  * Read loaded_vmcs->cpu should be before fetching
1732                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733                  * See the comments in __loaded_vmcs_clear().
1734                  */
1735                 smp_rmb();
1736
1737                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1739                 crash_enable_local_vmclear(cpu);
1740                 local_irq_enable();
1741
1742                 /*
1743                  * Linux uses per-cpu TSS and GDT, so set these when switching
1744                  * processors.
1745                  */
1746                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1747                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1748
1749                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1751                 vmx->loaded_vmcs->cpu = cpu;
1752         }
1753 }
1754
1755 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1756 {
1757         __vmx_load_host_state(to_vmx(vcpu));
1758         if (!vmm_exclusive) {
1759                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1760                 vcpu->cpu = -1;
1761                 kvm_cpu_vmxoff();
1762         }
1763 }
1764
1765 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1766 {
1767         ulong cr0;
1768
1769         if (vcpu->fpu_active)
1770                 return;
1771         vcpu->fpu_active = 1;
1772         cr0 = vmcs_readl(GUEST_CR0);
1773         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775         vmcs_writel(GUEST_CR0, cr0);
1776         update_exception_bitmap(vcpu);
1777         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1778         if (is_guest_mode(vcpu))
1779                 vcpu->arch.cr0_guest_owned_bits &=
1780                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1781         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1782 }
1783
1784 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1785
1786 /*
1787  * Return the cr0 value that a nested guest would read. This is a combination
1788  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789  * its hypervisor (cr0_read_shadow).
1790  */
1791 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1792 {
1793         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1795 }
1796 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1797 {
1798         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1800 }
1801
1802 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1803 {
1804         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805          * set this *before* calling this function.
1806          */
1807         vmx_decache_cr0_guest_bits(vcpu);
1808         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1809         update_exception_bitmap(vcpu);
1810         vcpu->arch.cr0_guest_owned_bits = 0;
1811         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1812         if (is_guest_mode(vcpu)) {
1813                 /*
1814                  * L1's specified read shadow might not contain the TS bit,
1815                  * so now that we turned on shadowing of this bit, we need to
1816                  * set this bit of the shadow. Like in nested_vmx_run we need
1817                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818                  * up-to-date here because we just decached cr0.TS (and we'll
1819                  * only update vmcs12->guest_cr0 on nested exit).
1820                  */
1821                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823                         (vcpu->arch.cr0 & X86_CR0_TS);
1824                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1825         } else
1826                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1827 }
1828
1829 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1830 {
1831         unsigned long rflags, save_rflags;
1832
1833         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835                 rflags = vmcs_readl(GUEST_RFLAGS);
1836                 if (to_vmx(vcpu)->rmode.vm86_active) {
1837                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1840                 }
1841                 to_vmx(vcpu)->rflags = rflags;
1842         }
1843         return to_vmx(vcpu)->rflags;
1844 }
1845
1846 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1847 {
1848         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849         to_vmx(vcpu)->rflags = rflags;
1850         if (to_vmx(vcpu)->rmode.vm86_active) {
1851                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1852                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1853         }
1854         vmcs_writel(GUEST_RFLAGS, rflags);
1855 }
1856
1857 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858 {
1859         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860         int ret = 0;
1861
1862         if (interruptibility & GUEST_INTR_STATE_STI)
1863                 ret |= KVM_X86_SHADOW_INT_STI;
1864         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1865                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1866
1867         return ret & mask;
1868 }
1869
1870 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1871 {
1872         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873         u32 interruptibility = interruptibility_old;
1874
1875         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1876
1877         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1878                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1879         else if (mask & KVM_X86_SHADOW_INT_STI)
1880                 interruptibility |= GUEST_INTR_STATE_STI;
1881
1882         if ((interruptibility != interruptibility_old))
1883                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1884 }
1885
1886 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1887 {
1888         unsigned long rip;
1889
1890         rip = kvm_rip_read(vcpu);
1891         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1892         kvm_rip_write(vcpu, rip);
1893
1894         /* skipping an emulated instruction also counts */
1895         vmx_set_interrupt_shadow(vcpu, 0);
1896 }
1897
1898 /*
1899  * KVM wants to inject page-faults which it got to the guest. This function
1900  * checks whether in a nested guest, we need to inject them to L1 or L2.
1901  */
1902 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
1903 {
1904         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1905
1906         if (!(vmcs12->exception_bitmap & (1u << nr)))
1907                 return 0;
1908
1909         nested_vmx_vmexit(vcpu);
1910         return 1;
1911 }
1912
1913 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1914                                 bool has_error_code, u32 error_code,
1915                                 bool reinject)
1916 {
1917         struct vcpu_vmx *vmx = to_vmx(vcpu);
1918         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1919
1920         if (!reinject && is_guest_mode(vcpu) &&
1921             nested_vmx_check_exception(vcpu, nr))
1922                 return;
1923
1924         if (has_error_code) {
1925                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1926                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1927         }
1928
1929         if (vmx->rmode.vm86_active) {
1930                 int inc_eip = 0;
1931                 if (kvm_exception_is_soft(nr))
1932                         inc_eip = vcpu->arch.event_exit_inst_len;
1933                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1934                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1935                 return;
1936         }
1937
1938         if (kvm_exception_is_soft(nr)) {
1939                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1940                              vmx->vcpu.arch.event_exit_inst_len);
1941                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1942         } else
1943                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1944
1945         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1946 }
1947
1948 static bool vmx_rdtscp_supported(void)
1949 {
1950         return cpu_has_vmx_rdtscp();
1951 }
1952
1953 static bool vmx_invpcid_supported(void)
1954 {
1955         return cpu_has_vmx_invpcid() && enable_ept;
1956 }
1957
1958 /*
1959  * Swap MSR entry in host/guest MSR entry array.
1960  */
1961 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1962 {
1963         struct shared_msr_entry tmp;
1964
1965         tmp = vmx->guest_msrs[to];
1966         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1967         vmx->guest_msrs[from] = tmp;
1968 }
1969
1970 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1971 {
1972         unsigned long *msr_bitmap;
1973
1974         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1975                 if (is_long_mode(vcpu))
1976                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1977                 else
1978                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1979         } else {
1980                 if (is_long_mode(vcpu))
1981                         msr_bitmap = vmx_msr_bitmap_longmode;
1982                 else
1983                         msr_bitmap = vmx_msr_bitmap_legacy;
1984         }
1985
1986         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1987 }
1988
1989 /*
1990  * Set up the vmcs to automatically save and restore system
1991  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1992  * mode, as fiddling with msrs is very expensive.
1993  */
1994 static void setup_msrs(struct vcpu_vmx *vmx)
1995 {
1996         int save_nmsrs, index;
1997
1998         save_nmsrs = 0;
1999 #ifdef CONFIG_X86_64
2000         if (is_long_mode(&vmx->vcpu)) {
2001                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2002                 if (index >= 0)
2003                         move_msr_up(vmx, index, save_nmsrs++);
2004                 index = __find_msr_index(vmx, MSR_LSTAR);
2005                 if (index >= 0)
2006                         move_msr_up(vmx, index, save_nmsrs++);
2007                 index = __find_msr_index(vmx, MSR_CSTAR);
2008                 if (index >= 0)
2009                         move_msr_up(vmx, index, save_nmsrs++);
2010                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2011                 if (index >= 0 && vmx->rdtscp_enabled)
2012                         move_msr_up(vmx, index, save_nmsrs++);
2013                 /*
2014                  * MSR_STAR is only needed on long mode guests, and only
2015                  * if efer.sce is enabled.
2016                  */
2017                 index = __find_msr_index(vmx, MSR_STAR);
2018                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2019                         move_msr_up(vmx, index, save_nmsrs++);
2020         }
2021 #endif
2022         index = __find_msr_index(vmx, MSR_EFER);
2023         if (index >= 0 && update_transition_efer(vmx, index))
2024                 move_msr_up(vmx, index, save_nmsrs++);
2025
2026         vmx->save_nmsrs = save_nmsrs;
2027
2028         if (cpu_has_vmx_msr_bitmap())
2029                 vmx_set_msr_bitmap(&vmx->vcpu);
2030 }
2031
2032 /*
2033  * reads and returns guest's timestamp counter "register"
2034  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2035  */
2036 static u64 guest_read_tsc(void)
2037 {
2038         u64 host_tsc, tsc_offset;
2039
2040         rdtscll(host_tsc);
2041         tsc_offset = vmcs_read64(TSC_OFFSET);
2042         return host_tsc + tsc_offset;
2043 }
2044
2045 /*
2046  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2047  * counter, even if a nested guest (L2) is currently running.
2048  */
2049 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2050 {
2051         u64 tsc_offset;
2052
2053         tsc_offset = is_guest_mode(vcpu) ?
2054                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2055                 vmcs_read64(TSC_OFFSET);
2056         return host_tsc + tsc_offset;
2057 }
2058
2059 /*
2060  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2061  * software catchup for faster rates on slower CPUs.
2062  */
2063 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2064 {
2065         if (!scale)
2066                 return;
2067
2068         if (user_tsc_khz > tsc_khz) {
2069                 vcpu->arch.tsc_catchup = 1;
2070                 vcpu->arch.tsc_always_catchup = 1;
2071         } else
2072                 WARN(1, "user requested TSC rate below hardware speed\n");
2073 }
2074
2075 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2076 {
2077         return vmcs_read64(TSC_OFFSET);
2078 }
2079
2080 /*
2081  * writes 'offset' into guest's timestamp counter offset register
2082  */
2083 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2084 {
2085         if (is_guest_mode(vcpu)) {
2086                 /*
2087                  * We're here if L1 chose not to trap WRMSR to TSC. According
2088                  * to the spec, this should set L1's TSC; The offset that L1
2089                  * set for L2 remains unchanged, and still needs to be added
2090                  * to the newly set TSC to get L2's TSC.
2091                  */
2092                 struct vmcs12 *vmcs12;
2093                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2094                 /* recalculate vmcs02.TSC_OFFSET: */
2095                 vmcs12 = get_vmcs12(vcpu);
2096                 vmcs_write64(TSC_OFFSET, offset +
2097                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2098                          vmcs12->tsc_offset : 0));
2099         } else {
2100                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2101                                            vmcs_read64(TSC_OFFSET), offset);
2102                 vmcs_write64(TSC_OFFSET, offset);
2103         }
2104 }
2105
2106 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2107 {
2108         u64 offset = vmcs_read64(TSC_OFFSET);
2109
2110         vmcs_write64(TSC_OFFSET, offset + adjustment);
2111         if (is_guest_mode(vcpu)) {
2112                 /* Even when running L2, the adjustment needs to apply to L1 */
2113                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2114         } else
2115                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2116                                            offset + adjustment);
2117 }
2118
2119 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2120 {
2121         return target_tsc - native_read_tsc();
2122 }
2123
2124 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2125 {
2126         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2127         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2128 }
2129
2130 /*
2131  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2132  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2133  * all guests if the "nested" module option is off, and can also be disabled
2134  * for a single guest by disabling its VMX cpuid bit.
2135  */
2136 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2137 {
2138         return nested && guest_cpuid_has_vmx(vcpu);
2139 }
2140
2141 /*
2142  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2143  * returned for the various VMX controls MSRs when nested VMX is enabled.
2144  * The same values should also be used to verify that vmcs12 control fields are
2145  * valid during nested entry from L1 to L2.
2146  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2147  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2148  * bit in the high half is on if the corresponding bit in the control field
2149  * may be on. See also vmx_control_verify().
2150  * TODO: allow these variables to be modified (downgraded) by module options
2151  * or other means.
2152  */
2153 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2154 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2155 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2156 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2157 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2158 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2159 static u32 nested_vmx_ept_caps;
2160 static __init void nested_vmx_setup_ctls_msrs(void)
2161 {
2162         /*
2163          * Note that as a general rule, the high half of the MSRs (bits in
2164          * the control fields which may be 1) should be initialized by the
2165          * intersection of the underlying hardware's MSR (i.e., features which
2166          * can be supported) and the list of features we want to expose -
2167          * because they are known to be properly supported in our code.
2168          * Also, usually, the low half of the MSRs (bits which must be 1) can
2169          * be set to 0, meaning that L1 may turn off any of these bits. The
2170          * reason is that if one of these bits is necessary, it will appear
2171          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2172          * fields of vmcs01 and vmcs02, will turn these bits off - and
2173          * nested_vmx_exit_handled() will not pass related exits to L1.
2174          * These rules have exceptions below.
2175          */
2176
2177         /* pin-based controls */
2178         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2179               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2180         /*
2181          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2182          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2183          */
2184         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2185         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2186                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2187                 PIN_BASED_VMX_PREEMPTION_TIMER;
2188         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2189
2190         /*
2191          * Exit controls
2192          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2193          * 17 must be 1.
2194          */
2195         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2196                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2197         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2198         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2199         nested_vmx_exit_ctls_high &=
2200 #ifdef CONFIG_X86_64
2201                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2202 #endif
2203                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2204                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2205         if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2206             !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2207                 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2208                 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2209         }
2210         nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2211                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
2212
2213         /* entry controls */
2214         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2215                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2216         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2217         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2218         nested_vmx_entry_ctls_high &=
2219 #ifdef CONFIG_X86_64
2220                 VM_ENTRY_IA32E_MODE |
2221 #endif
2222                 VM_ENTRY_LOAD_IA32_PAT;
2223         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2224                                        VM_ENTRY_LOAD_IA32_EFER);
2225
2226         /* cpu-based controls */
2227         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2228                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2229         nested_vmx_procbased_ctls_low = 0;
2230         nested_vmx_procbased_ctls_high &=
2231                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2232                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2233                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2234                 CPU_BASED_CR3_STORE_EXITING |
2235 #ifdef CONFIG_X86_64
2236                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2237 #endif
2238                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2239                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2240                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2241                 CPU_BASED_PAUSE_EXITING |
2242                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2243         /*
2244          * We can allow some features even when not supported by the
2245          * hardware. For example, L1 can specify an MSR bitmap - and we
2246          * can use it to avoid exits to L1 - even when L0 runs L2
2247          * without MSR bitmaps.
2248          */
2249         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2250
2251         /* secondary cpu-based controls */
2252         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2253                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2254         nested_vmx_secondary_ctls_low = 0;
2255         nested_vmx_secondary_ctls_high &=
2256                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2257                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2258                 SECONDARY_EXEC_WBINVD_EXITING;
2259
2260         if (enable_ept) {
2261                 /* nested EPT: emulate EPT also to L1 */
2262                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2263                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2264                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2265                 nested_vmx_ept_caps &= vmx_capability.ept;
2266                 /*
2267                  * Since invept is completely emulated we support both global
2268                  * and context invalidation independent of what host cpu
2269                  * supports
2270                  */
2271                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2272                         VMX_EPT_EXTENT_CONTEXT_BIT;
2273         } else
2274                 nested_vmx_ept_caps = 0;
2275
2276         /* miscellaneous data */
2277         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2278         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2279                 VMX_MISC_SAVE_EFER_LMA;
2280         nested_vmx_misc_high = 0;
2281 }
2282
2283 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2284 {
2285         /*
2286          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2287          */
2288         return ((control & high) | low) == control;
2289 }
2290
2291 static inline u64 vmx_control_msr(u32 low, u32 high)
2292 {
2293         return low | ((u64)high << 32);
2294 }
2295
2296 /*
2297  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2298  * also let it use VMX-specific MSRs.
2299  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2300  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2301  * like all other MSRs).
2302  */
2303 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2304 {
2305         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2306                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2307                 /*
2308                  * According to the spec, processors which do not support VMX
2309                  * should throw a #GP(0) when VMX capability MSRs are read.
2310                  */
2311                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2312                 return 1;
2313         }
2314
2315         switch (msr_index) {
2316         case MSR_IA32_FEATURE_CONTROL:
2317                 if (nested_vmx_allowed(vcpu)) {
2318                         *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2319                         break;
2320                 }
2321                 return 0;
2322         case MSR_IA32_VMX_BASIC:
2323                 /*
2324                  * This MSR reports some information about VMX support. We
2325                  * should return information about the VMX we emulate for the
2326                  * guest, and the VMCS structure we give it - not about the
2327                  * VMX support of the underlying hardware.
2328                  */
2329                 *pdata = VMCS12_REVISION |
2330                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2331                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2332                 break;
2333         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2334         case MSR_IA32_VMX_PINBASED_CTLS:
2335                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2336                                         nested_vmx_pinbased_ctls_high);
2337                 break;
2338         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2339         case MSR_IA32_VMX_PROCBASED_CTLS:
2340                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2341                                         nested_vmx_procbased_ctls_high);
2342                 break;
2343         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2344         case MSR_IA32_VMX_EXIT_CTLS:
2345                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2346                                         nested_vmx_exit_ctls_high);
2347                 break;
2348         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2349         case MSR_IA32_VMX_ENTRY_CTLS:
2350                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2351                                         nested_vmx_entry_ctls_high);
2352                 break;
2353         case MSR_IA32_VMX_MISC:
2354                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2355                                          nested_vmx_misc_high);
2356                 break;
2357         /*
2358          * These MSRs specify bits which the guest must keep fixed (on or off)
2359          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2360          * We picked the standard core2 setting.
2361          */
2362 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2363 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2364         case MSR_IA32_VMX_CR0_FIXED0:
2365                 *pdata = VMXON_CR0_ALWAYSON;
2366                 break;
2367         case MSR_IA32_VMX_CR0_FIXED1:
2368                 *pdata = -1ULL;
2369                 break;
2370         case MSR_IA32_VMX_CR4_FIXED0:
2371                 *pdata = VMXON_CR4_ALWAYSON;
2372                 break;
2373         case MSR_IA32_VMX_CR4_FIXED1:
2374                 *pdata = -1ULL;
2375                 break;
2376         case MSR_IA32_VMX_VMCS_ENUM:
2377                 *pdata = 0x1f;
2378                 break;
2379         case MSR_IA32_VMX_PROCBASED_CTLS2:
2380                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2381                                         nested_vmx_secondary_ctls_high);
2382                 break;
2383         case MSR_IA32_VMX_EPT_VPID_CAP:
2384                 /* Currently, no nested vpid support */
2385                 *pdata = nested_vmx_ept_caps;
2386                 break;
2387         default:
2388                 return 0;
2389         }
2390
2391         return 1;
2392 }
2393
2394 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2395 {
2396         u32 msr_index = msr_info->index;
2397         u64 data = msr_info->data;
2398         bool host_initialized = msr_info->host_initiated;
2399
2400         if (!nested_vmx_allowed(vcpu))
2401                 return 0;
2402
2403         if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2404                 if (!host_initialized &&
2405                                 to_vmx(vcpu)->nested.msr_ia32_feature_control
2406                                 & FEATURE_CONTROL_LOCKED)
2407                         return 0;
2408                 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
2409                 return 1;
2410         }
2411
2412         /*
2413          * No need to treat VMX capability MSRs specially: If we don't handle
2414          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2415          */
2416         return 0;
2417 }
2418
2419 /*
2420  * Reads an msr value (of 'msr_index') into 'pdata'.
2421  * Returns 0 on success, non-0 otherwise.
2422  * Assumes vcpu_load() was already called.
2423  */
2424 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2425 {
2426         u64 data;
2427         struct shared_msr_entry *msr;
2428
2429         if (!pdata) {
2430                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2431                 return -EINVAL;
2432         }
2433
2434         switch (msr_index) {
2435 #ifdef CONFIG_X86_64
2436         case MSR_FS_BASE:
2437                 data = vmcs_readl(GUEST_FS_BASE);
2438                 break;
2439         case MSR_GS_BASE:
2440                 data = vmcs_readl(GUEST_GS_BASE);
2441                 break;
2442         case MSR_KERNEL_GS_BASE:
2443                 vmx_load_host_state(to_vmx(vcpu));
2444                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2445                 break;
2446 #endif
2447         case MSR_EFER:
2448                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2449         case MSR_IA32_TSC:
2450                 data = guest_read_tsc();
2451                 break;
2452         case MSR_IA32_SYSENTER_CS:
2453                 data = vmcs_read32(GUEST_SYSENTER_CS);
2454                 break;
2455         case MSR_IA32_SYSENTER_EIP:
2456                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2457                 break;
2458         case MSR_IA32_SYSENTER_ESP:
2459                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2460                 break;
2461         case MSR_TSC_AUX:
2462                 if (!to_vmx(vcpu)->rdtscp_enabled)
2463                         return 1;
2464                 /* Otherwise falls through */
2465         default:
2466                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2467                         return 0;
2468                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2469                 if (msr) {
2470                         data = msr->data;
2471                         break;
2472                 }
2473                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2474         }
2475
2476         *pdata = data;
2477         return 0;
2478 }
2479
2480 /*
2481  * Writes msr value into into the appropriate "register".
2482  * Returns 0 on success, non-0 otherwise.
2483  * Assumes vcpu_load() was already called.
2484  */
2485 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2486 {
2487         struct vcpu_vmx *vmx = to_vmx(vcpu);
2488         struct shared_msr_entry *msr;
2489         int ret = 0;
2490         u32 msr_index = msr_info->index;
2491         u64 data = msr_info->data;
2492
2493         switch (msr_index) {
2494         case MSR_EFER:
2495                 ret = kvm_set_msr_common(vcpu, msr_info);
2496                 break;
2497 #ifdef CONFIG_X86_64
2498         case MSR_FS_BASE:
2499                 vmx_segment_cache_clear(vmx);
2500                 vmcs_writel(GUEST_FS_BASE, data);
2501                 break;
2502         case MSR_GS_BASE:
2503                 vmx_segment_cache_clear(vmx);
2504                 vmcs_writel(GUEST_GS_BASE, data);
2505                 break;
2506         case MSR_KERNEL_GS_BASE:
2507                 vmx_load_host_state(vmx);
2508                 vmx->msr_guest_kernel_gs_base = data;
2509                 break;
2510 #endif
2511         case MSR_IA32_SYSENTER_CS:
2512                 vmcs_write32(GUEST_SYSENTER_CS, data);
2513                 break;
2514         case MSR_IA32_SYSENTER_EIP:
2515                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2516                 break;
2517         case MSR_IA32_SYSENTER_ESP:
2518                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2519                 break;
2520         case MSR_IA32_TSC:
2521                 kvm_write_tsc(vcpu, msr_info);
2522                 break;
2523         case MSR_IA32_CR_PAT:
2524                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2525                         vmcs_write64(GUEST_IA32_PAT, data);
2526                         vcpu->arch.pat = data;
2527                         break;
2528                 }
2529                 ret = kvm_set_msr_common(vcpu, msr_info);
2530                 break;
2531         case MSR_IA32_TSC_ADJUST:
2532                 ret = kvm_set_msr_common(vcpu, msr_info);
2533                 break;
2534         case MSR_TSC_AUX:
2535                 if (!vmx->rdtscp_enabled)
2536                         return 1;
2537                 /* Check reserved bit, higher 32 bits should be zero */
2538                 if ((data >> 32) != 0)
2539                         return 1;
2540                 /* Otherwise falls through */
2541         default:
2542                 if (vmx_set_vmx_msr(vcpu, msr_info))
2543                         break;
2544                 msr = find_msr_entry(vmx, msr_index);
2545                 if (msr) {
2546                         msr->data = data;
2547                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2548                                 preempt_disable();
2549                                 kvm_set_shared_msr(msr->index, msr->data,
2550                                                    msr->mask);
2551                                 preempt_enable();
2552                         }
2553                         break;
2554                 }
2555                 ret = kvm_set_msr_common(vcpu, msr_info);
2556         }
2557
2558         return ret;
2559 }
2560
2561 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2562 {
2563         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2564         switch (reg) {
2565         case VCPU_REGS_RSP:
2566                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2567                 break;
2568         case VCPU_REGS_RIP:
2569                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2570                 break;
2571         case VCPU_EXREG_PDPTR:
2572                 if (enable_ept)
2573                         ept_save_pdptrs(vcpu);
2574                 break;
2575         default:
2576                 break;
2577         }
2578 }
2579
2580 static __init int cpu_has_kvm_support(void)
2581 {
2582         return cpu_has_vmx();
2583 }
2584
2585 static __init int vmx_disabled_by_bios(void)
2586 {
2587         u64 msr;
2588
2589         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2590         if (msr & FEATURE_CONTROL_LOCKED) {
2591                 /* launched w/ TXT and VMX disabled */
2592                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2593                         && tboot_enabled())
2594                         return 1;
2595                 /* launched w/o TXT and VMX only enabled w/ TXT */
2596                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2597                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2598                         && !tboot_enabled()) {
2599                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2600                                 "activate TXT before enabling KVM\n");
2601                         return 1;
2602                 }
2603                 /* launched w/o TXT and VMX disabled */
2604                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2605                         && !tboot_enabled())
2606                         return 1;
2607         }
2608
2609         return 0;
2610 }
2611
2612 static void kvm_cpu_vmxon(u64 addr)
2613 {
2614         asm volatile (ASM_VMX_VMXON_RAX
2615                         : : "a"(&addr), "m"(addr)
2616                         : "memory", "cc");
2617 }
2618
2619 static int hardware_enable(void *garbage)
2620 {
2621         int cpu = raw_smp_processor_id();
2622         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2623         u64 old, test_bits;
2624
2625         if (read_cr4() & X86_CR4_VMXE)
2626                 return -EBUSY;
2627
2628         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2629
2630         /*
2631          * Now we can enable the vmclear operation in kdump
2632          * since the loaded_vmcss_on_cpu list on this cpu
2633          * has been initialized.
2634          *
2635          * Though the cpu is not in VMX operation now, there
2636          * is no problem to enable the vmclear operation
2637          * for the loaded_vmcss_on_cpu list is empty!
2638          */
2639         crash_enable_local_vmclear(cpu);
2640
2641         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2642
2643         test_bits = FEATURE_CONTROL_LOCKED;
2644         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2645         if (tboot_enabled())
2646                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2647
2648         if ((old & test_bits) != test_bits) {
2649                 /* enable and lock */
2650                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2651         }
2652         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2653
2654         if (vmm_exclusive) {
2655                 kvm_cpu_vmxon(phys_addr);
2656                 ept_sync_global();
2657         }
2658
2659         native_store_gdt(&__get_cpu_var(host_gdt));
2660
2661         return 0;
2662 }
2663
2664 static void vmclear_local_loaded_vmcss(void)
2665 {
2666         int cpu = raw_smp_processor_id();
2667         struct loaded_vmcs *v, *n;
2668
2669         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2670                                  loaded_vmcss_on_cpu_link)
2671                 __loaded_vmcs_clear(v);
2672 }
2673
2674
2675 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2676  * tricks.
2677  */
2678 static void kvm_cpu_vmxoff(void)
2679 {
2680         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2681 }
2682
2683 static void hardware_disable(void *garbage)
2684 {
2685         if (vmm_exclusive) {
2686                 vmclear_local_loaded_vmcss();
2687                 kvm_cpu_vmxoff();
2688         }
2689         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2690 }
2691
2692 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2693                                       u32 msr, u32 *result)
2694 {
2695         u32 vmx_msr_low, vmx_msr_high;
2696         u32 ctl = ctl_min | ctl_opt;
2697
2698         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2699
2700         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2701         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2702
2703         /* Ensure minimum (required) set of control bits are supported. */
2704         if (ctl_min & ~ctl)
2705                 return -EIO;
2706
2707         *result = ctl;
2708         return 0;
2709 }
2710
2711 static __init bool allow_1_setting(u32 msr, u32 ctl)
2712 {
2713         u32 vmx_msr_low, vmx_msr_high;
2714
2715         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2716         return vmx_msr_high & ctl;
2717 }
2718
2719 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2720 {
2721         u32 vmx_msr_low, vmx_msr_high;
2722         u32 min, opt, min2, opt2;
2723         u32 _pin_based_exec_control = 0;
2724         u32 _cpu_based_exec_control = 0;
2725         u32 _cpu_based_2nd_exec_control = 0;
2726         u32 _vmexit_control = 0;
2727         u32 _vmentry_control = 0;
2728
2729         min = CPU_BASED_HLT_EXITING |
2730 #ifdef CONFIG_X86_64
2731               CPU_BASED_CR8_LOAD_EXITING |
2732               CPU_BASED_CR8_STORE_EXITING |
2733 #endif
2734               CPU_BASED_CR3_LOAD_EXITING |
2735               CPU_BASED_CR3_STORE_EXITING |
2736               CPU_BASED_USE_IO_BITMAPS |
2737               CPU_BASED_MOV_DR_EXITING |
2738               CPU_BASED_USE_TSC_OFFSETING |
2739               CPU_BASED_MWAIT_EXITING |
2740               CPU_BASED_MONITOR_EXITING |
2741               CPU_BASED_INVLPG_EXITING |
2742               CPU_BASED_RDPMC_EXITING;
2743
2744         opt = CPU_BASED_TPR_SHADOW |
2745               CPU_BASED_USE_MSR_BITMAPS |
2746               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2747         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2748                                 &_cpu_based_exec_control) < 0)
2749                 return -EIO;
2750 #ifdef CONFIG_X86_64
2751         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2752                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2753                                            ~CPU_BASED_CR8_STORE_EXITING;
2754 #endif
2755         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2756                 min2 = 0;
2757                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2758                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2759                         SECONDARY_EXEC_WBINVD_EXITING |
2760                         SECONDARY_EXEC_ENABLE_VPID |
2761                         SECONDARY_EXEC_ENABLE_EPT |
2762                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2763                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2764                         SECONDARY_EXEC_RDTSCP |
2765                         SECONDARY_EXEC_ENABLE_INVPCID |
2766                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2767                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2768                         SECONDARY_EXEC_SHADOW_VMCS;
2769                 if (adjust_vmx_controls(min2, opt2,
2770                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2771                                         &_cpu_based_2nd_exec_control) < 0)
2772                         return -EIO;
2773         }
2774 #ifndef CONFIG_X86_64
2775         if (!(_cpu_based_2nd_exec_control &
2776                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2777                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2778 #endif
2779
2780         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2781                 _cpu_based_2nd_exec_control &= ~(
2782                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2783                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2784                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2785
2786         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2787                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2788                    enabled */
2789                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2790                                              CPU_BASED_CR3_STORE_EXITING |
2791                                              CPU_BASED_INVLPG_EXITING);
2792                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2793                       vmx_capability.ept, vmx_capability.vpid);
2794         }
2795
2796         min = 0;
2797 #ifdef CONFIG_X86_64
2798         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2799 #endif
2800         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2801                 VM_EXIT_ACK_INTR_ON_EXIT;
2802         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2803                                 &_vmexit_control) < 0)
2804                 return -EIO;
2805
2806         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2807         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2808         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2809                                 &_pin_based_exec_control) < 0)
2810                 return -EIO;
2811
2812         if (!(_cpu_based_2nd_exec_control &
2813                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2814                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2815                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2816
2817         min = 0;
2818         opt = VM_ENTRY_LOAD_IA32_PAT;
2819         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2820                                 &_vmentry_control) < 0)
2821                 return -EIO;
2822
2823         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2824
2825         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2826         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2827                 return -EIO;
2828
2829 #ifdef CONFIG_X86_64
2830         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2831         if (vmx_msr_high & (1u<<16))
2832                 return -EIO;
2833 #endif
2834
2835         /* Require Write-Back (WB) memory type for VMCS accesses. */
2836         if (((vmx_msr_high >> 18) & 15) != 6)
2837                 return -EIO;
2838
2839         vmcs_conf->size = vmx_msr_high & 0x1fff;
2840         vmcs_conf->order = get_order(vmcs_config.size);
2841         vmcs_conf->revision_id = vmx_msr_low;
2842
2843         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2844         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2845         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2846         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2847         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2848
2849         cpu_has_load_ia32_efer =
2850                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2851                                 VM_ENTRY_LOAD_IA32_EFER)
2852                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2853                                    VM_EXIT_LOAD_IA32_EFER);
2854
2855         cpu_has_load_perf_global_ctrl =
2856                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2857                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2858                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2859                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2860
2861         /*
2862          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2863          * but due to arrata below it can't be used. Workaround is to use
2864          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2865          *
2866          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2867          *
2868          * AAK155             (model 26)
2869          * AAP115             (model 30)
2870          * AAT100             (model 37)
2871          * BC86,AAY89,BD102   (model 44)
2872          * BA97               (model 46)
2873          *
2874          */
2875         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2876                 switch (boot_cpu_data.x86_model) {
2877                 case 26:
2878                 case 30:
2879                 case 37:
2880                 case 44:
2881                 case 46:
2882                         cpu_has_load_perf_global_ctrl = false;
2883                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2884                                         "does not work properly. Using workaround\n");
2885                         break;
2886                 default:
2887                         break;
2888                 }
2889         }
2890
2891         return 0;
2892 }
2893
2894 static struct vmcs *alloc_vmcs_cpu(int cpu)
2895 {
2896         int node = cpu_to_node(cpu);
2897         struct page *pages;
2898         struct vmcs *vmcs;
2899
2900         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2901         if (!pages)
2902                 return NULL;
2903         vmcs = page_address(pages);
2904         memset(vmcs, 0, vmcs_config.size);
2905         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2906         return vmcs;
2907 }
2908
2909 static struct vmcs *alloc_vmcs(void)
2910 {
2911         return alloc_vmcs_cpu(raw_smp_processor_id());
2912 }
2913
2914 static void free_vmcs(struct vmcs *vmcs)
2915 {
2916         free_pages((unsigned long)vmcs, vmcs_config.order);
2917 }
2918
2919 /*
2920  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2921  */
2922 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2923 {
2924         if (!loaded_vmcs->vmcs)
2925                 return;
2926         loaded_vmcs_clear(loaded_vmcs);
2927         free_vmcs(loaded_vmcs->vmcs);
2928         loaded_vmcs->vmcs = NULL;
2929 }
2930
2931 static void free_kvm_area(void)
2932 {
2933         int cpu;
2934
2935         for_each_possible_cpu(cpu) {
2936                 free_vmcs(per_cpu(vmxarea, cpu));
2937                 per_cpu(vmxarea, cpu) = NULL;
2938         }
2939 }
2940
2941 static __init int alloc_kvm_area(void)
2942 {
2943         int cpu;
2944
2945         for_each_possible_cpu(cpu) {
2946                 struct vmcs *vmcs;
2947
2948                 vmcs = alloc_vmcs_cpu(cpu);
2949                 if (!vmcs) {
2950                         free_kvm_area();
2951                         return -ENOMEM;
2952                 }
2953
2954                 per_cpu(vmxarea, cpu) = vmcs;
2955         }
2956         return 0;
2957 }
2958
2959 static __init int hardware_setup(void)
2960 {
2961         if (setup_vmcs_config(&vmcs_config) < 0)
2962                 return -EIO;
2963
2964         if (boot_cpu_has(X86_FEATURE_NX))
2965                 kvm_enable_efer_bits(EFER_NX);
2966
2967         if (!cpu_has_vmx_vpid())
2968                 enable_vpid = 0;
2969         if (!cpu_has_vmx_shadow_vmcs())
2970                 enable_shadow_vmcs = 0;
2971
2972         if (!cpu_has_vmx_ept() ||
2973             !cpu_has_vmx_ept_4levels()) {
2974                 enable_ept = 0;
2975                 enable_unrestricted_guest = 0;
2976                 enable_ept_ad_bits = 0;
2977         }
2978
2979         if (!cpu_has_vmx_ept_ad_bits())
2980                 enable_ept_ad_bits = 0;
2981
2982         if (!cpu_has_vmx_unrestricted_guest())
2983                 enable_unrestricted_guest = 0;
2984
2985         if (!cpu_has_vmx_flexpriority())
2986                 flexpriority_enabled = 0;
2987
2988         if (!cpu_has_vmx_tpr_shadow())
2989                 kvm_x86_ops->update_cr8_intercept = NULL;
2990
2991         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2992                 kvm_disable_largepages();
2993
2994         if (!cpu_has_vmx_ple())
2995                 ple_gap = 0;
2996
2997         if (!cpu_has_vmx_apicv())
2998                 enable_apicv = 0;
2999
3000         if (enable_apicv)
3001                 kvm_x86_ops->update_cr8_intercept = NULL;
3002         else {
3003                 kvm_x86_ops->hwapic_irr_update = NULL;
3004                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3005                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3006         }
3007
3008         if (nested)
3009                 nested_vmx_setup_ctls_msrs();
3010
3011         return alloc_kvm_area();
3012 }
3013
3014 static __exit void hardware_unsetup(void)
3015 {
3016         free_kvm_area();
3017 }
3018
3019 static bool emulation_required(struct kvm_vcpu *vcpu)
3020 {
3021         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3022 }
3023
3024 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3025                 struct kvm_segment *save)
3026 {
3027         if (!emulate_invalid_guest_state) {
3028                 /*
3029                  * CS and SS RPL should be equal during guest entry according
3030                  * to VMX spec, but in reality it is not always so. Since vcpu
3031                  * is in the middle of the transition from real mode to
3032                  * protected mode it is safe to assume that RPL 0 is a good
3033                  * default value.
3034                  */
3035                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3036                         save->selector &= ~SELECTOR_RPL_MASK;
3037                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3038                 save->s = 1;
3039         }
3040         vmx_set_segment(vcpu, save, seg);
3041 }
3042
3043 static void enter_pmode(struct kvm_vcpu *vcpu)
3044 {
3045         unsigned long flags;
3046         struct vcpu_vmx *vmx = to_vmx(vcpu);
3047
3048         /*
3049          * Update real mode segment cache. It may be not up-to-date if sement
3050          * register was written while vcpu was in a guest mode.
3051          */
3052         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3053         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3054         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3055         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3056         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3057         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3058
3059         vmx->rmode.vm86_active = 0;
3060
3061         vmx_segment_cache_clear(vmx);
3062
3063         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3064
3065         flags = vmcs_readl(GUEST_RFLAGS);
3066         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3067         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3068         vmcs_writel(GUEST_RFLAGS, flags);
3069
3070         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3071                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3072
3073         update_exception_bitmap(vcpu);
3074
3075         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3076         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3077         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3078         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3079         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3080         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3081
3082         /* CPL is always 0 when CPU enters protected mode */
3083         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3084         vmx->cpl = 0;
3085 }
3086
3087 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3088 {
3089         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3090         struct kvm_segment var = *save;
3091
3092         var.dpl = 0x3;
3093         if (seg == VCPU_SREG_CS)
3094                 var.type = 0x3;
3095
3096         if (!emulate_invalid_guest_state) {
3097                 var.selector = var.base >> 4;
3098                 var.base = var.base & 0xffff0;
3099                 var.limit = 0xffff;
3100                 var.g = 0;
3101                 var.db = 0;
3102                 var.present = 1;
3103                 var.s = 1;
3104                 var.l = 0;
3105                 var.unusable = 0;
3106                 var.type = 0x3;
3107                 var.avl = 0;
3108                 if (save->base & 0xf)
3109                         printk_once(KERN_WARNING "kvm: segment base is not "
3110                                         "paragraph aligned when entering "
3111                                         "protected mode (seg=%d)", seg);
3112         }
3113
3114         vmcs_write16(sf->selector, var.selector);
3115         vmcs_write32(sf->base, var.base);
3116         vmcs_write32(sf->limit, var.limit);
3117         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3118 }
3119
3120 static void enter_rmode(struct kvm_vcpu *vcpu)
3121 {
3122         unsigned long flags;
3123         struct vcpu_vmx *vmx = to_vmx(vcpu);
3124
3125         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3126         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3127         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3128         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3129         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3130         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3131         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3132
3133         vmx->rmode.vm86_active = 1;
3134
3135         /*
3136          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3137          * vcpu. Warn the user that an update is overdue.
3138          */
3139         if (!vcpu->kvm->arch.tss_addr)
3140                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3141                              "called before entering vcpu\n");
3142
3143         vmx_segment_cache_clear(vmx);
3144
3145         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3146         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3147         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3148
3149         flags = vmcs_readl(GUEST_RFLAGS);
3150         vmx->rmode.save_rflags = flags;
3151
3152         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3153
3154         vmcs_writel(GUEST_RFLAGS, flags);
3155         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3156         update_exception_bitmap(vcpu);
3157
3158         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3159         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3160         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3161         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3162         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3163         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3164
3165         kvm_mmu_reset_context(vcpu);
3166 }
3167
3168 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3169 {
3170         struct vcpu_vmx *vmx = to_vmx(vcpu);
3171         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3172
3173         if (!msr)
3174                 return;
3175
3176         /*
3177          * Force kernel_gs_base reloading before EFER changes, as control
3178          * of this msr depends on is_long_mode().
3179          */
3180         vmx_load_host_state(to_vmx(vcpu));
3181         vcpu->arch.efer = efer;
3182         if (efer & EFER_LMA) {
3183                 vmcs_write32(VM_ENTRY_CONTROLS,
3184                              vmcs_read32(VM_ENTRY_CONTROLS) |
3185                              VM_ENTRY_IA32E_MODE);
3186                 msr->data = efer;
3187         } else {
3188                 vmcs_write32(VM_ENTRY_CONTROLS,
3189                              vmcs_read32(VM_ENTRY_CONTROLS) &
3190                              ~VM_ENTRY_IA32E_MODE);
3191
3192                 msr->data = efer & ~EFER_LME;
3193         }
3194         setup_msrs(vmx);
3195 }
3196
3197 #ifdef CONFIG_X86_64
3198
3199 static void enter_lmode(struct kvm_vcpu *vcpu)
3200 {
3201         u32 guest_tr_ar;
3202
3203         vmx_segment_cache_clear(to_vmx(vcpu));
3204
3205         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3206         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3207                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3208                                      __func__);
3209                 vmcs_write32(GUEST_TR_AR_BYTES,
3210                              (guest_tr_ar & ~AR_TYPE_MASK)
3211                              | AR_TYPE_BUSY_64_TSS);
3212         }
3213         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3214 }
3215
3216 static void exit_lmode(struct kvm_vcpu *vcpu)
3217 {
3218         vmcs_write32(VM_ENTRY_CONTROLS,
3219                      vmcs_read32(VM_ENTRY_CONTROLS)
3220                      & ~VM_ENTRY_IA32E_MODE);
3221         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3222 }
3223
3224 #endif
3225
3226 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3227 {
3228         vpid_sync_context(to_vmx(vcpu));
3229         if (enable_ept) {
3230                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3231                         return;
3232                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3233         }
3234 }
3235
3236 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3237 {
3238         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3239
3240         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3241         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3242 }
3243
3244 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3245 {
3246         if (enable_ept && is_paging(vcpu))
3247                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3248         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3249 }
3250
3251 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3252 {
3253         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3254
3255         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3256         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3257 }
3258
3259 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3260 {
3261         if (!test_bit(VCPU_EXREG_PDPTR,
3262                       (unsigned long *)&vcpu->arch.regs_dirty))
3263                 return;
3264
3265         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3266                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3267                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3268                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3269                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3270         }
3271 }
3272
3273 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3274 {
3275         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3276                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3277                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3278                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3279                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3280         }
3281
3282         __set_bit(VCPU_EXREG_PDPTR,
3283                   (unsigned long *)&vcpu->arch.regs_avail);
3284         __set_bit(VCPU_EXREG_PDPTR,
3285                   (unsigned long *)&vcpu->arch.regs_dirty);
3286 }
3287
3288 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3289
3290 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3291                                         unsigned long cr0,
3292                                         struct kvm_vcpu *vcpu)
3293 {
3294         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3295                 vmx_decache_cr3(vcpu);
3296         if (!(cr0 & X86_CR0_PG)) {
3297                 /* From paging/starting to nonpaging */
3298                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3299                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3300                              (CPU_BASED_CR3_LOAD_EXITING |
3301                               CPU_BASED_CR3_STORE_EXITING));
3302                 vcpu->arch.cr0 = cr0;
3303                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3304         } else if (!is_paging(vcpu)) {
3305                 /* From nonpaging to paging */
3306                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3307                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3308                              ~(CPU_BASED_CR3_LOAD_EXITING |
3309                                CPU_BASED_CR3_STORE_EXITING));
3310                 vcpu->arch.cr0 = cr0;
3311                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3312         }
3313
3314         if (!(cr0 & X86_CR0_WP))
3315                 *hw_cr0 &= ~X86_CR0_WP;
3316 }
3317
3318 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3319 {
3320         struct vcpu_vmx *vmx = to_vmx(vcpu);
3321         unsigned long hw_cr0;
3322
3323         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3324         if (enable_unrestricted_guest)
3325                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3326         else {
3327                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3328
3329                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3330                         enter_pmode(vcpu);
3331
3332                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3333                         enter_rmode(vcpu);
3334         }
3335
3336 #ifdef CONFIG_X86_64
3337         if (vcpu->arch.efer & EFER_LME) {
3338                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3339                         enter_lmode(vcpu);
3340                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3341                         exit_lmode(vcpu);
3342         }
3343 #endif
3344
3345         if (enable_ept)
3346                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3347
3348         if (!vcpu->fpu_active)
3349                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3350
3351         vmcs_writel(CR0_READ_SHADOW, cr0);
3352         vmcs_writel(GUEST_CR0, hw_cr0);
3353         vcpu->arch.cr0 = cr0;
3354
3355         /* depends on vcpu->arch.cr0 to be set to a new value */
3356         vmx->emulation_required = emulation_required(vcpu);
3357 }
3358
3359 static u64 construct_eptp(unsigned long root_hpa)
3360 {
3361         u64 eptp;
3362
3363         /* TODO write the value reading from MSR */
3364         eptp = VMX_EPT_DEFAULT_MT |
3365                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3366         if (enable_ept_ad_bits)
3367                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3368         eptp |= (root_hpa & PAGE_MASK);
3369
3370         return eptp;
3371 }
3372
3373 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3374 {
3375         unsigned long guest_cr3;
3376         u64 eptp;
3377
3378         guest_cr3 = cr3;
3379         if (enable_ept) {
3380                 eptp = construct_eptp(cr3);
3381                 vmcs_write64(EPT_POINTER, eptp);
3382                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3383                         guest_cr3 = kvm_read_cr3(vcpu);
3384                 else
3385                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3386                 ept_load_pdptrs(vcpu);
3387         }
3388
3389         vmx_flush_tlb(vcpu);
3390         vmcs_writel(GUEST_CR3, guest_cr3);
3391 }
3392
3393 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3394 {
3395         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3396                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3397
3398         if (cr4 & X86_CR4_VMXE) {
3399                 /*
3400                  * To use VMXON (and later other VMX instructions), a guest
3401                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3402                  * So basically the check on whether to allow nested VMX
3403                  * is here.
3404                  */
3405                 if (!nested_vmx_allowed(vcpu))
3406                         return 1;
3407         }
3408         if (to_vmx(vcpu)->nested.vmxon &&
3409             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3410                 return 1;
3411
3412         vcpu->arch.cr4 = cr4;
3413         if (enable_ept) {
3414                 if (!is_paging(vcpu)) {
3415                         hw_cr4 &= ~X86_CR4_PAE;
3416                         hw_cr4 |= X86_CR4_PSE;
3417                         /*
3418                          * SMEP is disabled if CPU is in non-paging mode in
3419                          * hardware. However KVM always uses paging mode to
3420                          * emulate guest non-paging mode with TDP.
3421                          * To emulate this behavior, SMEP needs to be manually
3422                          * disabled when guest switches to non-paging mode.
3423                          */
3424                         hw_cr4 &= ~X86_CR4_SMEP;
3425                 } else if (!(cr4 & X86_CR4_PAE)) {
3426                         hw_cr4 &= ~X86_CR4_PAE;
3427                 }
3428         }
3429
3430         vmcs_writel(CR4_READ_SHADOW, cr4);
3431         vmcs_writel(GUEST_CR4, hw_cr4);
3432         return 0;
3433 }
3434
3435 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3436                             struct kvm_segment *var, int seg)
3437 {
3438         struct vcpu_vmx *vmx = to_vmx(vcpu);
3439         u32 ar;
3440
3441         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3442                 *var = vmx->rmode.segs[seg];
3443                 if (seg == VCPU_SREG_TR
3444                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3445                         return;
3446                 var->base = vmx_read_guest_seg_base(vmx, seg);
3447                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3448                 return;
3449         }
3450         var->base = vmx_read_guest_seg_base(vmx, seg);
3451         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3452         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3453         ar = vmx_read_guest_seg_ar(vmx, seg);
3454         var->unusable = (ar >> 16) & 1;
3455         var->type = ar & 15;
3456         var->s = (ar >> 4) & 1;
3457         var->dpl = (ar >> 5) & 3;
3458         /*
3459          * Some userspaces do not preserve unusable property. Since usable
3460          * segment has to be present according to VMX spec we can use present
3461          * property to amend userspace bug by making unusable segment always
3462          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3463          * segment as unusable.
3464          */
3465         var->present = !var->unusable;
3466         var->avl = (ar >> 12) & 1;
3467         var->l = (ar >> 13) & 1;
3468         var->db = (ar >> 14) & 1;
3469         var->g = (ar >> 15) & 1;
3470 }
3471
3472 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3473 {
3474         struct kvm_segment s;
3475
3476         if (to_vmx(vcpu)->rmode.vm86_active) {
3477                 vmx_get_segment(vcpu, &s, seg);
3478                 return s.base;
3479         }
3480         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3481 }
3482
3483 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3484 {
3485         struct vcpu_vmx *vmx = to_vmx(vcpu);
3486
3487         if (!is_protmode(vcpu))
3488                 return 0;
3489
3490         if (!is_long_mode(vcpu)
3491             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3492                 return 3;
3493
3494         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3495                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3496                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3497         }
3498
3499         return vmx->cpl;
3500 }
3501
3502
3503 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3504 {
3505         u32 ar;
3506
3507         if (var->unusable || !var->present)
3508                 ar = 1 << 16;
3509         else {
3510                 ar = var->type & 15;
3511                 ar |= (var->s & 1) << 4;
3512                 ar |= (var->dpl & 3) << 5;
3513                 ar |= (var->present & 1) << 7;
3514                 ar |= (var->avl & 1) << 12;
3515                 ar |= (var->l & 1) << 13;
3516                 ar |= (var->db & 1) << 14;
3517                 ar |= (var->g & 1) << 15;
3518         }
3519
3520         return ar;
3521 }
3522
3523 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3524                             struct kvm_segment *var, int seg)
3525 {
3526         struct vcpu_vmx *vmx = to_vmx(vcpu);
3527         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3528
3529         vmx_segment_cache_clear(vmx);
3530         if (seg == VCPU_SREG_CS)
3531                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3532
3533         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3534                 vmx->rmode.segs[seg] = *var;
3535                 if (seg == VCPU_SREG_TR)
3536                         vmcs_write16(sf->selector, var->selector);
3537                 else if (var->s)
3538                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3539                 goto out;
3540         }
3541
3542         vmcs_writel(sf->base, var->base);
3543         vmcs_write32(sf->limit, var->limit);
3544         vmcs_write16(sf->selector, var->selector);
3545
3546         /*
3547          *   Fix the "Accessed" bit in AR field of segment registers for older
3548          * qemu binaries.
3549          *   IA32 arch specifies that at the time of processor reset the
3550          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3551          * is setting it to 0 in the userland code. This causes invalid guest
3552          * state vmexit when "unrestricted guest" mode is turned on.
3553          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3554          * tree. Newer qemu binaries with that qemu fix would not need this
3555          * kvm hack.
3556          */
3557         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3558                 var->type |= 0x1; /* Accessed */
3559
3560         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3561
3562 out:
3563         vmx->emulation_required |= emulation_required(vcpu);
3564 }
3565
3566 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3567 {
3568         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3569
3570         *db = (ar >> 14) & 1;
3571         *l = (ar >> 13) & 1;
3572 }
3573
3574 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3575 {
3576         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3577         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3578 }
3579
3580 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3581 {
3582         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3583         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3584 }
3585
3586 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3587 {
3588         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3589         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3590 }
3591
3592 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3593 {
3594         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3595         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3596 }
3597
3598 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3599 {
3600         struct kvm_segment var;
3601         u32 ar;
3602
3603         vmx_get_segment(vcpu, &var, seg);
3604         var.dpl = 0x3;
3605         if (seg == VCPU_SREG_CS)
3606                 var.type = 0x3;
3607         ar = vmx_segment_access_rights(&var);
3608
3609         if (var.base != (var.selector << 4))
3610                 return false;
3611         if (var.limit != 0xffff)
3612                 return false;
3613         if (ar != 0xf3)
3614                 return false;
3615
3616         return true;
3617 }
3618
3619 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3620 {
3621         struct kvm_segment cs;
3622         unsigned int cs_rpl;
3623
3624         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3625         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3626
3627         if (cs.unusable)
3628                 return false;
3629         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3630                 return false;
3631         if (!cs.s)
3632                 return false;
3633         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3634                 if (cs.dpl > cs_rpl)
3635                         return false;
3636         } else {
3637                 if (cs.dpl != cs_rpl)
3638                         return false;
3639         }
3640         if (!cs.present)
3641                 return false;
3642
3643         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3644         return true;
3645 }
3646
3647 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3648 {
3649         struct kvm_segment ss;
3650         unsigned int ss_rpl;
3651
3652         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3653         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3654
3655         if (ss.unusable)
3656                 return true;
3657         if (ss.type != 3 && ss.type != 7)
3658                 return false;
3659         if (!ss.s)
3660                 return false;
3661         if (ss.dpl != ss_rpl) /* DPL != RPL */
3662                 return false;
3663         if (!ss.present)
3664                 return false;
3665
3666         return true;
3667 }
3668
3669 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3670 {
3671         struct kvm_segment var;
3672         unsigned int rpl;
3673
3674         vmx_get_segment(vcpu, &var, seg);
3675         rpl = var.selector & SELECTOR_RPL_MASK;
3676
3677         if (var.unusable)
3678                 return true;
3679         if (!var.s)
3680                 return false;
3681         if (!var.present)
3682                 return false;
3683         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3684                 if (var.dpl < rpl) /* DPL < RPL */
3685                         return false;
3686         }
3687
3688         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3689          * rights flags
3690          */
3691         return true;
3692 }
3693
3694 static bool tr_valid(struct kvm_vcpu *vcpu)
3695 {
3696         struct kvm_segment tr;
3697
3698         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3699
3700         if (tr.unusable)
3701                 return false;
3702         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3703                 return false;
3704         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3705                 return false;
3706         if (!tr.present)
3707                 return false;
3708
3709         return true;
3710 }
3711
3712 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3713 {
3714         struct kvm_segment ldtr;
3715
3716         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3717
3718         if (ldtr.unusable)
3719                 return true;
3720         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3721                 return false;
3722         if (ldtr.type != 2)
3723                 return false;
3724         if (!ldtr.present)
3725                 return false;
3726
3727         return true;
3728 }
3729
3730 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3731 {
3732         struct kvm_segment cs, ss;
3733
3734         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3735         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3736
3737         return ((cs.selector & SELECTOR_RPL_MASK) ==
3738                  (ss.selector & SELECTOR_RPL_MASK));
3739 }
3740
3741 /*
3742  * Check if guest state is valid. Returns true if valid, false if
3743  * not.
3744  * We assume that registers are always usable
3745  */
3746 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3747 {
3748         if (enable_unrestricted_guest)
3749                 return true;
3750
3751         /* real mode guest state checks */
3752         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3753                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3754                         return false;
3755                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3756                         return false;
3757                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3758                         return false;
3759                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3760                         return false;
3761                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3762                         return false;
3763                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3764                         return false;
3765         } else {
3766         /* protected mode guest state checks */
3767                 if (!cs_ss_rpl_check(vcpu))
3768                         return false;
3769                 if (!code_segment_valid(vcpu))
3770                         return false;
3771                 if (!stack_segment_valid(vcpu))
3772                         return false;
3773                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3774                         return false;
3775                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3776                         return false;
3777                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3778                         return false;
3779                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3780                         return false;
3781                 if (!tr_valid(vcpu))
3782                         return false;
3783                 if (!ldtr_valid(vcpu))
3784                         return false;
3785         }
3786         /* TODO:
3787          * - Add checks on RIP
3788          * - Add checks on RFLAGS
3789          */
3790
3791         return true;
3792 }
3793
3794 static int init_rmode_tss(struct kvm *kvm)
3795 {
3796         gfn_t fn;
3797         u16 data = 0;
3798         int r, idx, ret = 0;
3799
3800         idx = srcu_read_lock(&kvm->srcu);
3801         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3802         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3803         if (r < 0)
3804                 goto out;
3805         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3806         r = kvm_write_guest_page(kvm, fn++, &data,
3807                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3808         if (r < 0)
3809                 goto out;
3810         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3811         if (r < 0)
3812                 goto out;
3813         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3814         if (r < 0)
3815                 goto out;
3816         data = ~0;
3817         r = kvm_write_guest_page(kvm, fn, &data,
3818                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3819                                  sizeof(u8));
3820         if (r < 0)
3821                 goto out;
3822
3823         ret = 1;
3824 out:
3825         srcu_read_unlock(&kvm->srcu, idx);
3826         return ret;
3827 }
3828
3829 static int init_rmode_identity_map(struct kvm *kvm)
3830 {
3831         int i, idx, r, ret;
3832         pfn_t identity_map_pfn;
3833         u32 tmp;
3834
3835         if (!enable_ept)
3836                 return 1;
3837         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3838                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3839                         "haven't been allocated!\n");
3840                 return 0;
3841         }
3842         if (likely(kvm->arch.ept_identity_pagetable_done))
3843                 return 1;
3844         ret = 0;
3845         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3846         idx = srcu_read_lock(&kvm->srcu);
3847         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3848         if (r < 0)
3849                 goto out;
3850         /* Set up identity-mapping pagetable for EPT in real mode */
3851         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3852                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3853                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3854                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3855                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3856                 if (r < 0)
3857                         goto out;
3858         }
3859         kvm->arch.ept_identity_pagetable_done = true;
3860         ret = 1;
3861 out:
3862         srcu_read_unlock(&kvm->srcu, idx);
3863         return ret;
3864 }
3865
3866 static void seg_setup(int seg)
3867 {
3868         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3869         unsigned int ar;
3870
3871         vmcs_write16(sf->selector, 0);
3872         vmcs_writel(sf->base, 0);
3873         vmcs_write32(sf->limit, 0xffff);
3874         ar = 0x93;
3875         if (seg == VCPU_SREG_CS)
3876                 ar |= 0x08; /* code segment */
3877
3878         vmcs_write32(sf->ar_bytes, ar);
3879 }
3880
3881 static int alloc_apic_access_page(struct kvm *kvm)
3882 {
3883         struct page *page;
3884         struct kvm_userspace_memory_region kvm_userspace_mem;
3885         int r = 0;
3886
3887         mutex_lock(&kvm->slots_lock);
3888         if (kvm->arch.apic_access_page)
3889                 goto out;
3890         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3891         kvm_userspace_mem.flags = 0;
3892         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3893         kvm_userspace_mem.memory_size = PAGE_SIZE;
3894         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3895         if (r)
3896                 goto out;
3897
3898         page = gfn_to_page(kvm, 0xfee00);
3899         if (is_error_page(page)) {
3900                 r = -EFAULT;
3901                 goto out;
3902         }
3903
3904         kvm->arch.apic_access_page = page;
3905 out:
3906         mutex_unlock(&kvm->slots_lock);
3907         return r;
3908 }
3909
3910 static int alloc_identity_pagetable(struct kvm *kvm)
3911 {
3912         struct page *page;
3913         struct kvm_userspace_memory_region kvm_userspace_mem;
3914         int r = 0;
3915
3916         mutex_lock(&kvm->slots_lock);
3917         if (kvm->arch.ept_identity_pagetable)
3918                 goto out;
3919         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3920         kvm_userspace_mem.flags = 0;
3921         kvm_userspace_mem.guest_phys_addr =
3922                 kvm->arch.ept_identity_map_addr;
3923         kvm_userspace_mem.memory_size = PAGE_SIZE;
3924         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3925         if (r)
3926                 goto out;
3927
3928         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3929         if (is_error_page(page)) {
3930                 r = -EFAULT;
3931                 goto out;
3932         }
3933
3934         kvm->arch.ept_identity_pagetable = page;
3935 out:
3936         mutex_unlock(&kvm->slots_lock);
3937         return r;
3938 }
3939
3940 static void allocate_vpid(struct vcpu_vmx *vmx)
3941 {
3942         int vpid;
3943
3944         vmx->vpid = 0;
3945         if (!enable_vpid)
3946                 return;
3947         spin_lock(&vmx_vpid_lock);
3948         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3949         if (vpid < VMX_NR_VPIDS) {
3950                 vmx->vpid = vpid;
3951                 __set_bit(vpid, vmx_vpid_bitmap);
3952         }
3953         spin_unlock(&vmx_vpid_lock);
3954 }
3955
3956 static void free_vpid(struct vcpu_vmx *vmx)
3957 {
3958         if (!enable_vpid)
3959                 return;
3960         spin_lock(&vmx_vpid_lock);
3961         if (vmx->vpid != 0)
3962                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3963         spin_unlock(&vmx_vpid_lock);
3964 }
3965
3966 #define MSR_TYPE_R      1
3967 #define MSR_TYPE_W      2
3968 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3969                                                 u32 msr, int type)
3970 {
3971         int f = sizeof(unsigned long);
3972
3973         if (!cpu_has_vmx_msr_bitmap())
3974                 return;
3975
3976         /*
3977          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3978          * have the write-low and read-high bitmap offsets the wrong way round.
3979          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3980          */
3981         if (msr <= 0x1fff) {
3982                 if (type & MSR_TYPE_R)
3983                         /* read-low */
3984                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3985
3986                 if (type & MSR_TYPE_W)
3987                         /* write-low */
3988                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3989
3990         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3991                 msr &= 0x1fff;
3992                 if (type & MSR_TYPE_R)
3993                         /* read-high */
3994                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3995
3996                 if (type & MSR_TYPE_W)
3997                         /* write-high */
3998                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3999
4000         }
4001 }
4002
4003 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4004                                                 u32 msr, int type)
4005 {
4006         int f = sizeof(unsigned long);
4007
4008         if (!cpu_has_vmx_msr_bitmap())
4009                 return;
4010
4011         /*
4012          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4013          * have the write-low and read-high bitmap offsets the wrong way round.
4014          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4015          */
4016         if (msr <= 0x1fff) {
4017                 if (type & MSR_TYPE_R)
4018                         /* read-low */
4019                         __set_bit(msr, msr_bitmap + 0x000 / f);
4020
4021                 if (type & MSR_TYPE_W)
4022                         /* write-low */
4023                         __set_bit(msr, msr_bitmap + 0x800 / f);
4024
4025         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4026                 msr &= 0x1fff;
4027                 if (type & MSR_TYPE_R)
4028                         /* read-high */
4029                         __set_bit(msr, msr_bitmap + 0x400 / f);
4030
4031                 if (type & MSR_TYPE_W)
4032                         /* write-high */
4033                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4034
4035         }
4036 }
4037
4038 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4039 {
4040         if (!longmode_only)
4041                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4042                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4043         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4044                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4045 }
4046
4047 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4048 {
4049         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4050                         msr, MSR_TYPE_R);
4051         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4052                         msr, MSR_TYPE_R);
4053 }
4054
4055 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4056 {
4057         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4058                         msr, MSR_TYPE_R);
4059         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4060                         msr, MSR_TYPE_R);
4061 }
4062
4063 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4064 {
4065         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4066                         msr, MSR_TYPE_W);
4067         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4068                         msr, MSR_TYPE_W);
4069 }
4070
4071 static int vmx_vm_has_apicv(struct kvm *kvm)
4072 {
4073         return enable_apicv && irqchip_in_kernel(kvm);
4074 }
4075
4076 /*
4077  * Send interrupt to vcpu via posted interrupt way.
4078  * 1. If target vcpu is running(non-root mode), send posted interrupt
4079  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4080  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4081  * interrupt from PIR in next vmentry.
4082  */
4083 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4084 {
4085         struct vcpu_vmx *vmx = to_vmx(vcpu);
4086         int r;
4087
4088         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4089                 return;
4090
4091         r = pi_test_and_set_on(&vmx->pi_desc);
4092         kvm_make_request(KVM_REQ_EVENT, vcpu);
4093 #ifdef CONFIG_SMP
4094         if (!r && (vcpu->mode == IN_GUEST_MODE))
4095                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4096                                 POSTED_INTR_VECTOR);
4097         else
4098 #endif
4099                 kvm_vcpu_kick(vcpu);
4100 }
4101
4102 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4103 {
4104         struct vcpu_vmx *vmx = to_vmx(vcpu);
4105
4106         if (!pi_test_and_clear_on(&vmx->pi_desc))
4107                 return;
4108
4109         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4110 }
4111
4112 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4113 {
4114         return;
4115 }
4116
4117 /*
4118  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4119  * will not change in the lifetime of the guest.
4120  * Note that host-state that does change is set elsewhere. E.g., host-state
4121  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4122  */
4123 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4124 {
4125         u32 low32, high32;
4126         unsigned long tmpl;
4127         struct desc_ptr dt;
4128
4129         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4130         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4131         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4132
4133         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4134 #ifdef CONFIG_X86_64
4135         /*
4136          * Load null selectors, so we can avoid reloading them in
4137          * __vmx_load_host_state(), in case userspace uses the null selectors
4138          * too (the expected case).
4139          */
4140         vmcs_write16(HOST_DS_SELECTOR, 0);
4141         vmcs_write16(HOST_ES_SELECTOR, 0);
4142 #else
4143         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4144         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4145 #endif
4146         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4147         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4148
4149         native_store_idt(&dt);
4150         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4151         vmx->host_idt_base = dt.address;
4152
4153         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4154
4155         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4156         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4157         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4158         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4159
4160         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4161                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4162                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4163         }
4164 }
4165
4166 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4167 {
4168         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4169         if (enable_ept)
4170                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4171         if (is_guest_mode(&vmx->vcpu))
4172                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4173                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4174         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4175 }
4176
4177 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4178 {
4179         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4180
4181         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4182                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4183         return pin_based_exec_ctrl;
4184 }
4185
4186 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4187 {
4188         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4189         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4190                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4191 #ifdef CONFIG_X86_64
4192                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4193                                 CPU_BASED_CR8_LOAD_EXITING;
4194 #endif
4195         }
4196         if (!enable_ept)
4197                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4198                                 CPU_BASED_CR3_LOAD_EXITING  |
4199                                 CPU_BASED_INVLPG_EXITING;
4200         return exec_control;
4201 }
4202
4203 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4204 {
4205         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4206         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4207                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4208         if (vmx->vpid == 0)
4209                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4210         if (!enable_ept) {
4211                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4212                 enable_unrestricted_guest = 0;
4213                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4214                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4215         }
4216         if (!enable_unrestricted_guest)
4217                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4218         if (!ple_gap)
4219                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4220         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4221                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4222                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4223         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4224         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4225            (handle_vmptrld).
4226            We can NOT enable shadow_vmcs here because we don't have yet
4227            a current VMCS12
4228         */
4229         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4230         return exec_control;
4231 }
4232
4233 static void ept_set_mmio_spte_mask(void)
4234 {
4235         /*
4236          * EPT Misconfigurations can be generated if the value of bits 2:0
4237          * of an EPT paging-structure entry is 110b (write/execute).
4238          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4239          * spte.
4240          */
4241         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4242 }
4243
4244 /*
4245  * Sets up the vmcs for emulated real mode.
4246  */
4247 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4248 {
4249 #ifdef CONFIG_X86_64
4250         unsigned long a;
4251 #endif
4252         int i;
4253
4254         /* I/O */
4255         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4256         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4257
4258         if (enable_shadow_vmcs) {
4259                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4260                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4261         }
4262         if (cpu_has_vmx_msr_bitmap())
4263                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4264
4265         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4266
4267         /* Control */
4268         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4269
4270         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4271
4272         if (cpu_has_secondary_exec_ctrls()) {
4273                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4274                                 vmx_secondary_exec_control(vmx));
4275         }
4276
4277         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4278                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4279                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4280                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4281                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4282
4283                 vmcs_write16(GUEST_INTR_STATUS, 0);
4284
4285                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4286                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4287         }
4288
4289         if (ple_gap) {
4290                 vmcs_write32(PLE_GAP, ple_gap);
4291                 vmcs_write32(PLE_WINDOW, ple_window);
4292         }
4293
4294         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4295         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4296         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4297
4298         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4299         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4300         vmx_set_constant_host_state(vmx);
4301 #ifdef CONFIG_X86_64
4302         rdmsrl(MSR_FS_BASE, a);
4303         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4304         rdmsrl(MSR_GS_BASE, a);
4305         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4306 #else
4307         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4308         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4309 #endif
4310
4311         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4312         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4313         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4314         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4315         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4316
4317         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4318                 u32 msr_low, msr_high;
4319                 u64 host_pat;
4320                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4321                 host_pat = msr_low | ((u64) msr_high << 32);
4322                 /* Write the default value follow host pat */
4323                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4324                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4325                 vmx->vcpu.arch.pat = host_pat;
4326         }
4327
4328         for (i = 0; i < NR_VMX_MSR; ++i) {
4329                 u32 index = vmx_msr_index[i];
4330                 u32 data_low, data_high;
4331                 int j = vmx->nmsrs;
4332
4333                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4334                         continue;
4335                 if (wrmsr_safe(index, data_low, data_high) < 0)
4336                         continue;
4337                 vmx->guest_msrs[j].index = i;
4338                 vmx->guest_msrs[j].data = 0;
4339                 vmx->guest_msrs[j].mask = -1ull;
4340                 ++vmx->nmsrs;
4341         }
4342
4343         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4344
4345         /* 22.2.1, 20.8.1 */
4346         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4347
4348         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4349         set_cr4_guest_host_mask(vmx);
4350
4351         return 0;
4352 }
4353
4354 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4355 {
4356         struct vcpu_vmx *vmx = to_vmx(vcpu);
4357         u64 msr;
4358
4359         vmx->rmode.vm86_active = 0;
4360
4361         vmx->soft_vnmi_blocked = 0;
4362
4363         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4364         kvm_set_cr8(&vmx->vcpu, 0);
4365         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4366         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4367                 msr |= MSR_IA32_APICBASE_BSP;
4368         kvm_set_apic_base(&vmx->vcpu, msr);
4369
4370         vmx_segment_cache_clear(vmx);
4371
4372         seg_setup(VCPU_SREG_CS);
4373         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4374         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4375
4376         seg_setup(VCPU_SREG_DS);
4377         seg_setup(VCPU_SREG_ES);
4378         seg_setup(VCPU_SREG_FS);
4379         seg_setup(VCPU_SREG_GS);
4380         seg_setup(VCPU_SREG_SS);
4381
4382         vmcs_write16(GUEST_TR_SELECTOR, 0);
4383         vmcs_writel(GUEST_TR_BASE, 0);
4384         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4385         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4386
4387         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4388         vmcs_writel(GUEST_LDTR_BASE, 0);
4389         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4390         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4391
4392         vmcs_write32(GUEST_SYSENTER_CS, 0);
4393         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4394         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4395
4396         vmcs_writel(GUEST_RFLAGS, 0x02);
4397         kvm_rip_write(vcpu, 0xfff0);
4398
4399         vmcs_writel(GUEST_GDTR_BASE, 0);
4400         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4401
4402         vmcs_writel(GUEST_IDTR_BASE, 0);
4403         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4404
4405         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4406         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4407         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4408
4409         /* Special registers */
4410         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4411
4412         setup_msrs(vmx);
4413
4414         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4415
4416         if (cpu_has_vmx_tpr_shadow()) {
4417                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4418                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4419                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4420                                      __pa(vmx->vcpu.arch.apic->regs));
4421                 vmcs_write32(TPR_THRESHOLD, 0);
4422         }
4423
4424         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4425                 vmcs_write64(APIC_ACCESS_ADDR,
4426                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4427
4428         if (vmx_vm_has_apicv(vcpu->kvm))
4429                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4430
4431         if (vmx->vpid != 0)
4432                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4433
4434         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4435         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4436         vmx_set_cr4(&vmx->vcpu, 0);
4437         vmx_set_efer(&vmx->vcpu, 0);
4438         vmx_fpu_activate(&vmx->vcpu);
4439         update_exception_bitmap(&vmx->vcpu);
4440
4441         vpid_sync_context(vmx);
4442 }
4443
4444 /*
4445  * In nested virtualization, check if L1 asked to exit on external interrupts.
4446  * For most existing hypervisors, this will always return true.
4447  */
4448 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4449 {
4450         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4451                 PIN_BASED_EXT_INTR_MASK;
4452 }
4453
4454 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4455 {
4456         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4457                 PIN_BASED_NMI_EXITING;
4458 }
4459
4460 static int enable_irq_window(struct kvm_vcpu *vcpu)
4461 {
4462         u32 cpu_based_vm_exec_control;
4463
4464         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4465                 /*
4466                  * We get here if vmx_interrupt_allowed() said we can't
4467                  * inject to L1 now because L2 must run. The caller will have
4468                  * to make L2 exit right after entry, so we can inject to L1
4469                  * more promptly.
4470                  */
4471                 return -EBUSY;
4472
4473         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4474         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4475         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4476         return 0;
4477 }
4478
4479 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4480 {
4481         u32 cpu_based_vm_exec_control;
4482
4483         if (!cpu_has_virtual_nmis())
4484                 return enable_irq_window(vcpu);
4485
4486         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4487                 return enable_irq_window(vcpu);
4488
4489         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4490         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4491         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4492         return 0;
4493 }
4494
4495 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4496 {
4497         struct vcpu_vmx *vmx = to_vmx(vcpu);
4498         uint32_t intr;
4499         int irq = vcpu->arch.interrupt.nr;
4500
4501         trace_kvm_inj_virq(irq);
4502
4503         ++vcpu->stat.irq_injections;
4504         if (vmx->rmode.vm86_active) {
4505                 int inc_eip = 0;
4506                 if (vcpu->arch.interrupt.soft)
4507                         inc_eip = vcpu->arch.event_exit_inst_len;
4508                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4509                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4510                 return;
4511         }
4512         intr = irq | INTR_INFO_VALID_MASK;
4513         if (vcpu->arch.interrupt.soft) {
4514                 intr |= INTR_TYPE_SOFT_INTR;
4515                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4516                              vmx->vcpu.arch.event_exit_inst_len);
4517         } else
4518                 intr |= INTR_TYPE_EXT_INTR;
4519         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4520 }
4521
4522 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4523 {
4524         struct vcpu_vmx *vmx = to_vmx(vcpu);
4525
4526         if (is_guest_mode(vcpu))
4527                 return;
4528
4529         if (!cpu_has_virtual_nmis()) {
4530                 /*
4531                  * Tracking the NMI-blocked state in software is built upon
4532                  * finding the next open IRQ window. This, in turn, depends on
4533                  * well-behaving guests: They have to keep IRQs disabled at
4534                  * least as long as the NMI handler runs. Otherwise we may
4535                  * cause NMI nesting, maybe breaking the guest. But as this is
4536                  * highly unlikely, we can live with the residual risk.
4537                  */
4538                 vmx->soft_vnmi_blocked = 1;
4539                 vmx->vnmi_blocked_time = 0;
4540         }
4541
4542         ++vcpu->stat.nmi_injections;
4543         vmx->nmi_known_unmasked = false;
4544         if (vmx->rmode.vm86_active) {
4545                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4546                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4547                 return;
4548         }
4549         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4550                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4551 }
4552
4553 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4554 {
4555         if (!cpu_has_virtual_nmis())
4556                 return to_vmx(vcpu)->soft_vnmi_blocked;
4557         if (to_vmx(vcpu)->nmi_known_unmasked)
4558                 return false;
4559         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4560 }
4561
4562 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4563 {
4564         struct vcpu_vmx *vmx = to_vmx(vcpu);
4565
4566         if (!cpu_has_virtual_nmis()) {
4567                 if (vmx->soft_vnmi_blocked != masked) {
4568                         vmx->soft_vnmi_blocked = masked;
4569                         vmx->vnmi_blocked_time = 0;
4570                 }
4571         } else {
4572                 vmx->nmi_known_unmasked = !masked;
4573                 if (masked)
4574                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4575                                       GUEST_INTR_STATE_NMI);
4576                 else
4577                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4578                                         GUEST_INTR_STATE_NMI);
4579         }
4580 }
4581
4582 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4583 {
4584         if (is_guest_mode(vcpu)) {
4585                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4586
4587                 if (to_vmx(vcpu)->nested.nested_run_pending)
4588                         return 0;
4589                 if (nested_exit_on_nmi(vcpu)) {
4590                         nested_vmx_vmexit(vcpu);
4591                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4592                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4593                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4594                         /*
4595                          * The NMI-triggered VM exit counts as injection:
4596                          * clear this one and block further NMIs.
4597                          */
4598                         vcpu->arch.nmi_pending = 0;
4599                         vmx_set_nmi_mask(vcpu, true);
4600                         return 0;
4601                 }
4602         }
4603
4604         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4605                 return 0;
4606
4607         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4608                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4609                    | GUEST_INTR_STATE_NMI));
4610 }
4611
4612 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4613 {
4614         if (is_guest_mode(vcpu)) {
4615                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4616
4617                 if (to_vmx(vcpu)->nested.nested_run_pending)
4618                         return 0;
4619                 if (nested_exit_on_intr(vcpu)) {
4620                         nested_vmx_vmexit(vcpu);
4621                         vmcs12->vm_exit_reason =
4622                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4623                         vmcs12->vm_exit_intr_info = 0;
4624                         /*
4625                          * fall through to normal code, but now in L1, not L2
4626                          */
4627                 }
4628         }
4629
4630         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4631                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4632                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4633 }
4634
4635 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4636 {
4637         int ret;
4638         struct kvm_userspace_memory_region tss_mem = {
4639                 .slot = TSS_PRIVATE_MEMSLOT,
4640                 .guest_phys_addr = addr,
4641                 .memory_size = PAGE_SIZE * 3,
4642                 .flags = 0,
4643         };
4644
4645         ret = kvm_set_memory_region(kvm, &tss_mem);
4646         if (ret)
4647                 return ret;
4648         kvm->arch.tss_addr = addr;
4649         if (!init_rmode_tss(kvm))
4650                 return  -ENOMEM;
4651
4652         return 0;
4653 }
4654
4655 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4656 {
4657         switch (vec) {
4658         case BP_VECTOR:
4659                 /*
4660                  * Update instruction length as we may reinject the exception
4661                  * from user space while in guest debugging mode.
4662                  */
4663                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4664                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4665                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4666                         return false;
4667                 /* fall through */
4668         case DB_VECTOR:
4669                 if (vcpu->guest_debug &
4670                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4671                         return false;
4672                 /* fall through */
4673         case DE_VECTOR:
4674         case OF_VECTOR:
4675         case BR_VECTOR:
4676         case UD_VECTOR:
4677         case DF_VECTOR:
4678         case SS_VECTOR:
4679         case GP_VECTOR:
4680         case MF_VECTOR:
4681                 return true;
4682         break;
4683         }
4684         return false;
4685 }
4686
4687 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4688                                   int vec, u32 err_code)
4689 {
4690         /*
4691          * Instruction with address size override prefix opcode 0x67
4692          * Cause the #SS fault with 0 error code in VM86 mode.
4693          */
4694         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4695                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4696                         if (vcpu->arch.halt_request) {
4697                                 vcpu->arch.halt_request = 0;
4698                                 return kvm_emulate_halt(vcpu);
4699                         }
4700                         return 1;
4701                 }
4702                 return 0;
4703         }
4704
4705         /*
4706          * Forward all other exceptions that are valid in real mode.
4707          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4708          *        the required debugging infrastructure rework.
4709          */
4710         kvm_queue_exception(vcpu, vec);
4711         return 1;
4712 }
4713
4714 /*
4715  * Trigger machine check on the host. We assume all the MSRs are already set up
4716  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4717  * We pass a fake environment to the machine check handler because we want
4718  * the guest to be always treated like user space, no matter what context
4719  * it used internally.
4720  */
4721 static void kvm_machine_check(void)
4722 {
4723 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4724         struct pt_regs regs = {
4725                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4726                 .flags = X86_EFLAGS_IF,
4727         };
4728
4729         do_machine_check(&regs, 0);
4730 #endif
4731 }
4732
4733 static int handle_machine_check(struct kvm_vcpu *vcpu)
4734 {
4735         /* already handled by vcpu_run */
4736         return 1;
4737 }
4738
4739 static int handle_exception(struct kvm_vcpu *vcpu)
4740 {
4741         struct vcpu_vmx *vmx = to_vmx(vcpu);
4742         struct kvm_run *kvm_run = vcpu->run;
4743         u32 intr_info, ex_no, error_code;
4744         unsigned long cr2, rip, dr6;
4745         u32 vect_info;
4746         enum emulation_result er;
4747
4748         vect_info = vmx->idt_vectoring_info;
4749         intr_info = vmx->exit_intr_info;
4750
4751         if (is_machine_check(intr_info))
4752                 return handle_machine_check(vcpu);
4753
4754         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4755                 return 1;  /* already handled by vmx_vcpu_run() */
4756
4757         if (is_no_device(intr_info)) {
4758                 vmx_fpu_activate(vcpu);
4759                 return 1;
4760         }
4761
4762         if (is_invalid_opcode(intr_info)) {
4763                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4764                 if (er != EMULATE_DONE)
4765                         kvm_queue_exception(vcpu, UD_VECTOR);
4766                 return 1;
4767         }
4768
4769         error_code = 0;
4770         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4771                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4772
4773         /*
4774          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4775          * MMIO, it is better to report an internal error.
4776          * See the comments in vmx_handle_exit.
4777          */
4778         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4779             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4780                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4781                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4782                 vcpu->run->internal.ndata = 2;
4783                 vcpu->run->internal.data[0] = vect_info;
4784                 vcpu->run->internal.data[1] = intr_info;
4785                 return 0;
4786         }
4787
4788         if (is_page_fault(intr_info)) {
4789                 /* EPT won't cause page fault directly */
4790                 BUG_ON(enable_ept);
4791                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4792                 trace_kvm_page_fault(cr2, error_code);
4793
4794                 if (kvm_event_needs_reinjection(vcpu))
4795                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4796                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4797         }
4798
4799         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4800
4801         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4802                 return handle_rmode_exception(vcpu, ex_no, error_code);
4803
4804         switch (ex_no) {
4805         case DB_VECTOR:
4806                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4807                 if (!(vcpu->guest_debug &
4808                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4809                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4810                         kvm_queue_exception(vcpu, DB_VECTOR);
4811                         return 1;
4812                 }
4813                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4814                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4815                 /* fall through */
4816         case BP_VECTOR:
4817                 /*
4818                  * Update instruction length as we may reinject #BP from
4819                  * user space while in guest debugging mode. Reading it for
4820                  * #DB as well causes no harm, it is not used in that case.
4821                  */
4822                 vmx->vcpu.arch.event_exit_inst_len =
4823                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4824                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4825                 rip = kvm_rip_read(vcpu);
4826                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4827                 kvm_run->debug.arch.exception = ex_no;
4828                 break;
4829         default:
4830                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4831                 kvm_run->ex.exception = ex_no;
4832                 kvm_run->ex.error_code = error_code;
4833                 break;
4834         }
4835         return 0;
4836 }
4837
4838 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4839 {
4840         ++vcpu->stat.irq_exits;
4841         return 1;
4842 }
4843
4844 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4845 {
4846         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4847         return 0;
4848 }
4849
4850 static int handle_io(struct kvm_vcpu *vcpu)
4851 {
4852         unsigned long exit_qualification;
4853         int size, in, string;
4854         unsigned port;
4855
4856         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4857         string = (exit_qualification & 16) != 0;
4858         in = (exit_qualification & 8) != 0;
4859
4860         ++vcpu->stat.io_exits;
4861
4862         if (string || in)
4863                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4864
4865         port = exit_qualification >> 16;
4866         size = (exit_qualification & 7) + 1;
4867         skip_emulated_instruction(vcpu);
4868
4869         return kvm_fast_pio_out(vcpu, size, port);
4870 }
4871
4872 static void
4873 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4874 {
4875         /*
4876          * Patch in the VMCALL instruction:
4877          */
4878         hypercall[0] = 0x0f;
4879         hypercall[1] = 0x01;
4880         hypercall[2] = 0xc1;
4881 }
4882
4883 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4884 {
4885         unsigned long always_on = VMXON_CR0_ALWAYSON;
4886
4887         if (nested_vmx_secondary_ctls_high &
4888                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4889             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4890                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4891         return (val & always_on) == always_on;
4892 }
4893
4894 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4895 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4896 {
4897         if (is_guest_mode(vcpu)) {
4898                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4899                 unsigned long orig_val = val;
4900
4901                 /*
4902                  * We get here when L2 changed cr0 in a way that did not change
4903                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4904                  * but did change L0 shadowed bits. So we first calculate the
4905                  * effective cr0 value that L1 would like to write into the
4906                  * hardware. It consists of the L2-owned bits from the new
4907                  * value combined with the L1-owned bits from L1's guest_cr0.
4908                  */
4909                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4910                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4911
4912                 if (!nested_cr0_valid(vmcs12, val))
4913                         return 1;
4914
4915                 if (kvm_set_cr0(vcpu, val))
4916                         return 1;
4917                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4918                 return 0;
4919         } else {
4920                 if (to_vmx(vcpu)->nested.vmxon &&
4921                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4922                         return 1;
4923                 return kvm_set_cr0(vcpu, val);
4924         }
4925 }
4926
4927 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4928 {
4929         if (is_guest_mode(vcpu)) {
4930                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4931                 unsigned long orig_val = val;
4932
4933                 /* analogously to handle_set_cr0 */
4934                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4935                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4936                 if (kvm_set_cr4(vcpu, val))
4937                         return 1;
4938                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4939                 return 0;
4940         } else
4941                 return kvm_set_cr4(vcpu, val);
4942 }
4943
4944 /* called to set cr0 as approriate for clts instruction exit. */
4945 static void handle_clts(struct kvm_vcpu *vcpu)
4946 {
4947         if (is_guest_mode(vcpu)) {
4948                 /*
4949                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4950                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4951                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4952                  */
4953                 vmcs_writel(CR0_READ_SHADOW,
4954                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4955                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4956         } else
4957                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4958 }
4959
4960 static int handle_cr(struct kvm_vcpu *vcpu)
4961 {
4962         unsigned long exit_qualification, val;
4963         int cr;
4964         int reg;
4965         int err;
4966
4967         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4968         cr = exit_qualification & 15;
4969         reg = (exit_qualification >> 8) & 15;
4970         switch ((exit_qualification >> 4) & 3) {
4971         case 0: /* mov to cr */
4972                 val = kvm_register_read(vcpu, reg);
4973                 trace_kvm_cr_write(cr, val);
4974                 switch (cr) {
4975                 case 0:
4976                         err = handle_set_cr0(vcpu, val);
4977                         kvm_complete_insn_gp(vcpu, err);
4978                         return 1;
4979                 case 3:
4980                         err = kvm_set_cr3(vcpu, val);
4981                         kvm_complete_insn_gp(vcpu, err);
4982                         return 1;
4983                 case 4:
4984                         err = handle_set_cr4(vcpu, val);
4985                         kvm_complete_insn_gp(vcpu, err);
4986                         return 1;
4987                 case 8: {
4988                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4989                                 u8 cr8 = kvm_register_read(vcpu, reg);
4990                                 err = kvm_set_cr8(vcpu, cr8);
4991                                 kvm_complete_insn_gp(vcpu, err);
4992                                 if (irqchip_in_kernel(vcpu->kvm))
4993                                         return 1;
4994                                 if (cr8_prev <= cr8)
4995                                         return 1;
4996                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4997                                 return 0;
4998                         }
4999                 }
5000                 break;
5001         case 2: /* clts */
5002                 handle_clts(vcpu);
5003                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5004                 skip_emulated_instruction(vcpu);
5005                 vmx_fpu_activate(vcpu);
5006                 return 1;
5007         case 1: /*mov from cr*/
5008                 switch (cr) {
5009                 case 3:
5010                         val = kvm_read_cr3(vcpu);
5011                         kvm_register_write(vcpu, reg, val);
5012                         trace_kvm_cr_read(cr, val);
5013                         skip_emulated_instruction(vcpu);
5014                         return 1;
5015                 case 8:
5016                         val = kvm_get_cr8(vcpu);
5017                         kvm_register_write(vcpu, reg, val);
5018                         trace_kvm_cr_read(cr, val);
5019                         skip_emulated_instruction(vcpu);
5020                         return 1;
5021                 }
5022                 break;
5023         case 3: /* lmsw */
5024                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5025                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5026                 kvm_lmsw(vcpu, val);
5027
5028                 skip_emulated_instruction(vcpu);
5029                 return 1;
5030         default:
5031                 break;
5032         }
5033         vcpu->run->exit_reason = 0;
5034         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5035                (int)(exit_qualification >> 4) & 3, cr);
5036         return 0;
5037 }
5038
5039 static int handle_dr(struct kvm_vcpu *vcpu)
5040 {
5041         unsigned long exit_qualification;
5042         int dr, reg;
5043
5044         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5045         if (!kvm_require_cpl(vcpu, 0))
5046                 return 1;
5047         dr = vmcs_readl(GUEST_DR7);
5048         if (dr & DR7_GD) {
5049                 /*
5050                  * As the vm-exit takes precedence over the debug trap, we
5051                  * need to emulate the latter, either for the host or the
5052                  * guest debugging itself.
5053                  */
5054                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5055                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5056                         vcpu->run->debug.arch.dr7 = dr;
5057                         vcpu->run->debug.arch.pc =
5058                                 vmcs_readl(GUEST_CS_BASE) +
5059                                 vmcs_readl(GUEST_RIP);
5060                         vcpu->run->debug.arch.exception = DB_VECTOR;
5061                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5062                         return 0;
5063                 } else {
5064                         vcpu->arch.dr7 &= ~DR7_GD;
5065                         vcpu->arch.dr6 |= DR6_BD;
5066                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5067                         kvm_queue_exception(vcpu, DB_VECTOR);
5068                         return 1;
5069                 }
5070         }
5071
5072         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5073         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5074         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5075         if (exit_qualification & TYPE_MOV_FROM_DR) {
5076                 unsigned long val;
5077                 if (!kvm_get_dr(vcpu, dr, &val))
5078                         kvm_register_write(vcpu, reg, val);
5079         } else
5080                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5081         skip_emulated_instruction(vcpu);
5082         return 1;
5083 }
5084
5085 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5086 {
5087         vmcs_writel(GUEST_DR7, val);
5088 }
5089
5090 static int handle_cpuid(struct kvm_vcpu *vcpu)
5091 {
5092         kvm_emulate_cpuid(vcpu);
5093         return 1;
5094 }
5095
5096 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5097 {
5098         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5099         u64 data;
5100
5101         if (vmx_get_msr(vcpu, ecx, &data)) {
5102                 trace_kvm_msr_read_ex(ecx);
5103                 kvm_inject_gp(vcpu, 0);
5104                 return 1;
5105         }
5106
5107         trace_kvm_msr_read(ecx, data);
5108
5109         /* FIXME: handling of bits 32:63 of rax, rdx */
5110         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5111         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5112         skip_emulated_instruction(vcpu);
5113         return 1;
5114 }
5115
5116 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5117 {
5118         struct msr_data msr;
5119         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5120         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5121                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5122
5123         msr.data = data;
5124         msr.index = ecx;
5125         msr.host_initiated = false;
5126         if (vmx_set_msr(vcpu, &msr) != 0) {
5127                 trace_kvm_msr_write_ex(ecx, data);
5128                 kvm_inject_gp(vcpu, 0);
5129                 return 1;
5130         }
5131
5132         trace_kvm_msr_write(ecx, data);
5133         skip_emulated_instruction(vcpu);
5134         return 1;
5135 }
5136
5137 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5138 {
5139         kvm_make_request(KVM_REQ_EVENT, vcpu);
5140         return 1;
5141 }
5142
5143 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5144 {
5145         u32 cpu_based_vm_exec_control;
5146
5147         /* clear pending irq */
5148         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5149         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5150         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5151
5152         kvm_make_request(KVM_REQ_EVENT, vcpu);
5153
5154         ++vcpu->stat.irq_window_exits;
5155
5156         /*
5157          * If the user space waits to inject interrupts, exit as soon as
5158          * possible
5159          */
5160         if (!irqchip_in_kernel(vcpu->kvm) &&
5161             vcpu->run->request_interrupt_window &&
5162             !kvm_cpu_has_interrupt(vcpu)) {
5163                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5164                 return 0;
5165         }
5166         return 1;
5167 }
5168
5169 static int handle_halt(struct kvm_vcpu *vcpu)
5170 {
5171         skip_emulated_instruction(vcpu);
5172         return kvm_emulate_halt(vcpu);
5173 }
5174
5175 static int handle_vmcall(struct kvm_vcpu *vcpu)
5176 {
5177         skip_emulated_instruction(vcpu);
5178         kvm_emulate_hypercall(vcpu);
5179         return 1;
5180 }
5181
5182 static int handle_invd(struct kvm_vcpu *vcpu)
5183 {
5184         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5185 }
5186
5187 static int handle_invlpg(struct kvm_vcpu *vcpu)
5188 {
5189         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5190
5191         kvm_mmu_invlpg(vcpu, exit_qualification);
5192         skip_emulated_instruction(vcpu);
5193         return 1;
5194 }
5195
5196 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5197 {
5198         int err;
5199
5200         err = kvm_rdpmc(vcpu);
5201         kvm_complete_insn_gp(vcpu, err);
5202
5203         return 1;
5204 }
5205
5206 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5207 {
5208         skip_emulated_instruction(vcpu);
5209         kvm_emulate_wbinvd(vcpu);
5210         return 1;
5211 }
5212
5213 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5214 {
5215         u64 new_bv = kvm_read_edx_eax(vcpu);
5216         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5217
5218         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5219                 skip_emulated_instruction(vcpu);
5220         return 1;
5221 }
5222
5223 static int handle_apic_access(struct kvm_vcpu *vcpu)
5224 {
5225         if (likely(fasteoi)) {
5226                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5227                 int access_type, offset;
5228
5229                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5230                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5231                 /*
5232                  * Sane guest uses MOV to write EOI, with written value
5233                  * not cared. So make a short-circuit here by avoiding
5234                  * heavy instruction emulation.
5235                  */
5236                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5237                     (offset == APIC_EOI)) {
5238                         kvm_lapic_set_eoi(vcpu);
5239                         skip_emulated_instruction(vcpu);
5240                         return 1;
5241                 }
5242         }
5243         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5244 }
5245
5246 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5247 {
5248         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5249         int vector = exit_qualification & 0xff;
5250
5251         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5252         kvm_apic_set_eoi_accelerated(vcpu, vector);
5253         return 1;
5254 }
5255
5256 static int handle_apic_write(struct kvm_vcpu *vcpu)
5257 {
5258         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5259         u32 offset = exit_qualification & 0xfff;
5260
5261         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5262         kvm_apic_write_nodecode(vcpu, offset);
5263         return 1;
5264 }
5265
5266 static int handle_task_switch(struct kvm_vcpu *vcpu)
5267 {
5268         struct vcpu_vmx *vmx = to_vmx(vcpu);
5269         unsigned long exit_qualification;
5270         bool has_error_code = false;
5271         u32 error_code = 0;
5272         u16 tss_selector;
5273         int reason, type, idt_v, idt_index;
5274
5275         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5276         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5277         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5278
5279         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5280
5281         reason = (u32)exit_qualification >> 30;
5282         if (reason == TASK_SWITCH_GATE && idt_v) {
5283                 switch (type) {
5284                 case INTR_TYPE_NMI_INTR:
5285                         vcpu->arch.nmi_injected = false;
5286                         vmx_set_nmi_mask(vcpu, true);
5287                         break;
5288                 case INTR_TYPE_EXT_INTR:
5289                 case INTR_TYPE_SOFT_INTR:
5290                         kvm_clear_interrupt_queue(vcpu);
5291                         break;
5292                 case INTR_TYPE_HARD_EXCEPTION:
5293                         if (vmx->idt_vectoring_info &
5294                             VECTORING_INFO_DELIVER_CODE_MASK) {
5295                                 has_error_code = true;
5296                                 error_code =
5297                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5298                         }
5299                         /* fall through */
5300                 case INTR_TYPE_SOFT_EXCEPTION:
5301                         kvm_clear_exception_queue(vcpu);
5302                         break;
5303                 default:
5304                         break;
5305                 }
5306         }
5307         tss_selector = exit_qualification;
5308
5309         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5310                        type != INTR_TYPE_EXT_INTR &&
5311                        type != INTR_TYPE_NMI_INTR))
5312                 skip_emulated_instruction(vcpu);
5313
5314         if (kvm_task_switch(vcpu, tss_selector,
5315                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5316                             has_error_code, error_code) == EMULATE_FAIL) {
5317                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5318                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5319                 vcpu->run->internal.ndata = 0;
5320                 return 0;
5321         }
5322
5323         /* clear all local breakpoint enable flags */
5324         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5325
5326         /*
5327          * TODO: What about debug traps on tss switch?
5328          *       Are we supposed to inject them and update dr6?
5329          */
5330
5331         return 1;
5332 }
5333
5334 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5335 {
5336         unsigned long exit_qualification;
5337         gpa_t gpa;
5338         u32 error_code;
5339         int gla_validity;
5340
5341         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5342
5343         gla_validity = (exit_qualification >> 7) & 0x3;
5344         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5345                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5346                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5347                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5348                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5349                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5350                         (long unsigned int)exit_qualification);
5351                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5352                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5353                 return 0;
5354         }
5355
5356         /*
5357          * EPT violation happened while executing iret from NMI,
5358          * "blocked by NMI" bit has to be set before next VM entry.
5359          * There are errata that may cause this bit to not be set:
5360          * AAK134, BY25.
5361          */
5362         if (exit_qualification & INTR_INFO_UNBLOCK_NMI)
5363                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5364
5365         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5366         trace_kvm_page_fault(gpa, exit_qualification);
5367
5368         /* It is a write fault? */
5369         error_code = exit_qualification & (1U << 1);
5370         /* It is a fetch fault? */
5371         error_code |= (exit_qualification & (1U << 2)) << 2;
5372         /* ept page table is present? */
5373         error_code |= (exit_qualification >> 3) & 0x1;
5374
5375         vcpu->arch.exit_qualification = exit_qualification;
5376
5377         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5378 }
5379
5380 static u64 ept_rsvd_mask(u64 spte, int level)
5381 {
5382         int i;
5383         u64 mask = 0;
5384
5385         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5386                 mask |= (1ULL << i);
5387
5388         if (level > 2)
5389                 /* bits 7:3 reserved */
5390                 mask |= 0xf8;
5391         else if (level == 2) {
5392                 if (spte & (1ULL << 7))
5393                         /* 2MB ref, bits 20:12 reserved */
5394                         mask |= 0x1ff000;
5395                 else
5396                         /* bits 6:3 reserved */
5397                         mask |= 0x78;
5398         }
5399
5400         return mask;
5401 }
5402
5403 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5404                                        int level)
5405 {
5406         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5407
5408         /* 010b (write-only) */
5409         WARN_ON((spte & 0x7) == 0x2);
5410
5411         /* 110b (write/execute) */
5412         WARN_ON((spte & 0x7) == 0x6);
5413
5414         /* 100b (execute-only) and value not supported by logical processor */
5415         if (!cpu_has_vmx_ept_execute_only())
5416                 WARN_ON((spte & 0x7) == 0x4);
5417
5418         /* not 000b */
5419         if ((spte & 0x7)) {
5420                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5421
5422                 if (rsvd_bits != 0) {
5423                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5424                                          __func__, rsvd_bits);
5425                         WARN_ON(1);
5426                 }
5427
5428                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5429                         u64 ept_mem_type = (spte & 0x38) >> 3;
5430
5431                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5432                             ept_mem_type == 7) {
5433                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5434                                                 __func__, ept_mem_type);
5435                                 WARN_ON(1);
5436                         }
5437                 }
5438         }
5439 }
5440
5441 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5442 {
5443         u64 sptes[4];
5444         int nr_sptes, i, ret;
5445         gpa_t gpa;
5446
5447         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5448
5449         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5450         if (likely(ret == RET_MMIO_PF_EMULATE))
5451                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5452                                               EMULATE_DONE;
5453
5454         if (unlikely(ret == RET_MMIO_PF_INVALID))
5455                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5456
5457         if (unlikely(ret == RET_MMIO_PF_RETRY))
5458                 return 1;
5459
5460         /* It is the real ept misconfig */
5461         printk(KERN_ERR "EPT: Misconfiguration.\n");
5462         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5463
5464         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5465
5466         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5467                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5468
5469         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5470         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5471
5472         return 0;
5473 }
5474
5475 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5476 {
5477         u32 cpu_based_vm_exec_control;
5478
5479         /* clear pending NMI */
5480         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5481         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5482         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5483         ++vcpu->stat.nmi_window_exits;
5484         kvm_make_request(KVM_REQ_EVENT, vcpu);
5485
5486         return 1;
5487 }
5488
5489 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5490 {
5491         struct vcpu_vmx *vmx = to_vmx(vcpu);
5492         enum emulation_result err = EMULATE_DONE;
5493         int ret = 1;
5494         u32 cpu_exec_ctrl;
5495         bool intr_window_requested;
5496         unsigned count = 130;
5497
5498         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5499         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5500
5501         while (!guest_state_valid(vcpu) && count-- != 0) {
5502                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5503                         return handle_interrupt_window(&vmx->vcpu);
5504
5505                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5506                         return 1;
5507
5508                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5509
5510                 if (err == EMULATE_USER_EXIT) {
5511                         ++vcpu->stat.mmio_exits;
5512                         ret = 0;
5513                         goto out;
5514                 }
5515
5516                 if (err != EMULATE_DONE) {
5517                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5518                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5519                         vcpu->run->internal.ndata = 0;
5520                         return 0;
5521                 }
5522
5523                 if (vcpu->arch.halt_request) {
5524                         vcpu->arch.halt_request = 0;
5525                         ret = kvm_emulate_halt(vcpu);
5526                         goto out;
5527                 }
5528
5529                 if (signal_pending(current))
5530                         goto out;
5531                 if (need_resched())
5532                         schedule();
5533         }
5534
5535         vmx->emulation_required = emulation_required(vcpu);
5536 out:
5537         return ret;
5538 }
5539
5540 /*
5541  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5542  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5543  */
5544 static int handle_pause(struct kvm_vcpu *vcpu)
5545 {
5546         skip_emulated_instruction(vcpu);
5547         kvm_vcpu_on_spin(vcpu);
5548
5549         return 1;
5550 }
5551
5552 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5553 {
5554         kvm_queue_exception(vcpu, UD_VECTOR);
5555         return 1;
5556 }
5557
5558 /*
5559  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5560  * We could reuse a single VMCS for all the L2 guests, but we also want the
5561  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5562  * allows keeping them loaded on the processor, and in the future will allow
5563  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5564  * every entry if they never change.
5565  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5566  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5567  *
5568  * The following functions allocate and free a vmcs02 in this pool.
5569  */
5570
5571 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5572 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5573 {
5574         struct vmcs02_list *item;
5575         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5576                 if (item->vmptr == vmx->nested.current_vmptr) {
5577                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5578                         return &item->vmcs02;
5579                 }
5580
5581         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5582                 /* Recycle the least recently used VMCS. */
5583                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5584                         struct vmcs02_list, list);
5585                 item->vmptr = vmx->nested.current_vmptr;
5586                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5587                 return &item->vmcs02;
5588         }
5589
5590         /* Create a new VMCS */
5591         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5592         if (!item)
5593                 return NULL;
5594         item->vmcs02.vmcs = alloc_vmcs();
5595         if (!item->vmcs02.vmcs) {
5596                 kfree(item);
5597                 return NULL;
5598         }
5599         loaded_vmcs_init(&item->vmcs02);
5600         item->vmptr = vmx->nested.current_vmptr;
5601         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5602         vmx->nested.vmcs02_num++;
5603         return &item->vmcs02;
5604 }
5605
5606 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5607 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5608 {
5609         struct vmcs02_list *item;
5610         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5611                 if (item->vmptr == vmptr) {
5612                         free_loaded_vmcs(&item->vmcs02);
5613                         list_del(&item->list);
5614                         kfree(item);
5615                         vmx->nested.vmcs02_num--;
5616                         return;
5617                 }
5618 }
5619
5620 /*
5621  * Free all VMCSs saved for this vcpu, except the one pointed by
5622  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5623  * currently used, if running L2), and vmcs01 when running L2.
5624  */
5625 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5626 {
5627         struct vmcs02_list *item, *n;
5628         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5629                 if (vmx->loaded_vmcs != &item->vmcs02)
5630                         free_loaded_vmcs(&item->vmcs02);
5631                 list_del(&item->list);
5632                 kfree(item);
5633         }
5634         vmx->nested.vmcs02_num = 0;
5635
5636         if (vmx->loaded_vmcs != &vmx->vmcs01)
5637                 free_loaded_vmcs(&vmx->vmcs01);
5638 }
5639
5640 /*
5641  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5642  * set the success or error code of an emulated VMX instruction, as specified
5643  * by Vol 2B, VMX Instruction Reference, "Conventions".
5644  */
5645 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5646 {
5647         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5648                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5649                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5650 }
5651
5652 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5653 {
5654         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5655                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5656                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5657                         | X86_EFLAGS_CF);
5658 }
5659
5660 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5661                                         u32 vm_instruction_error)
5662 {
5663         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5664                 /*
5665                  * failValid writes the error number to the current VMCS, which
5666                  * can't be done there isn't a current VMCS.
5667                  */
5668                 nested_vmx_failInvalid(vcpu);
5669                 return;
5670         }
5671         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5672                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5673                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5674                         | X86_EFLAGS_ZF);
5675         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5676         /*
5677          * We don't need to force a shadow sync because
5678          * VM_INSTRUCTION_ERROR is not shadowed
5679          */
5680 }
5681
5682 /*
5683  * Emulate the VMXON instruction.
5684  * Currently, we just remember that VMX is active, and do not save or even
5685  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5686  * do not currently need to store anything in that guest-allocated memory
5687  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5688  * argument is different from the VMXON pointer (which the spec says they do).
5689  */
5690 static int handle_vmon(struct kvm_vcpu *vcpu)
5691 {
5692         struct kvm_segment cs;
5693         struct vcpu_vmx *vmx = to_vmx(vcpu);
5694         struct vmcs *shadow_vmcs;
5695         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5696                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5697
5698         /* The Intel VMX Instruction Reference lists a bunch of bits that
5699          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5700          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5701          * Otherwise, we should fail with #UD. We test these now:
5702          */
5703         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5704             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5705             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5706                 kvm_queue_exception(vcpu, UD_VECTOR);
5707                 return 1;
5708         }
5709
5710         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5711         if (is_long_mode(vcpu) && !cs.l) {
5712                 kvm_queue_exception(vcpu, UD_VECTOR);
5713                 return 1;
5714         }
5715
5716         if (vmx_get_cpl(vcpu)) {
5717                 kvm_inject_gp(vcpu, 0);
5718                 return 1;
5719         }
5720         if (vmx->nested.vmxon) {
5721                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5722                 skip_emulated_instruction(vcpu);
5723                 return 1;
5724         }
5725
5726         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5727                         != VMXON_NEEDED_FEATURES) {
5728                 kvm_inject_gp(vcpu, 0);
5729                 return 1;
5730         }
5731
5732         if (enable_shadow_vmcs) {
5733                 shadow_vmcs = alloc_vmcs();
5734                 if (!shadow_vmcs)
5735                         return -ENOMEM;
5736                 /* mark vmcs as shadow */
5737                 shadow_vmcs->revision_id |= (1u << 31);
5738                 /* init shadow vmcs */
5739                 vmcs_clear(shadow_vmcs);
5740                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5741         }
5742
5743         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5744         vmx->nested.vmcs02_num = 0;
5745
5746         vmx->nested.vmxon = true;
5747
5748         skip_emulated_instruction(vcpu);
5749         nested_vmx_succeed(vcpu);
5750         return 1;
5751 }
5752
5753 /*
5754  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5755  * for running VMX instructions (except VMXON, whose prerequisites are
5756  * slightly different). It also specifies what exception to inject otherwise.
5757  */
5758 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5759 {
5760         struct kvm_segment cs;
5761         struct vcpu_vmx *vmx = to_vmx(vcpu);
5762
5763         if (!vmx->nested.vmxon) {
5764                 kvm_queue_exception(vcpu, UD_VECTOR);
5765                 return 0;
5766         }
5767
5768         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5769         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5770             (is_long_mode(vcpu) && !cs.l)) {
5771                 kvm_queue_exception(vcpu, UD_VECTOR);
5772                 return 0;
5773         }
5774
5775         if (vmx_get_cpl(vcpu)) {
5776                 kvm_inject_gp(vcpu, 0);
5777                 return 0;
5778         }
5779
5780         return 1;
5781 }
5782
5783 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5784 {
5785         u32 exec_control;
5786         if (enable_shadow_vmcs) {
5787                 if (vmx->nested.current_vmcs12 != NULL) {
5788                         /* copy to memory all shadowed fields in case
5789                            they were modified */
5790                         copy_shadow_to_vmcs12(vmx);
5791                         vmx->nested.sync_shadow_vmcs = false;
5792                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5793                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5794                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5795                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5796                 }
5797         }
5798         kunmap(vmx->nested.current_vmcs12_page);
5799         nested_release_page(vmx->nested.current_vmcs12_page);
5800 }
5801
5802 /*
5803  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5804  * just stops using VMX.
5805  */
5806 static void free_nested(struct vcpu_vmx *vmx)
5807 {
5808         if (!vmx->nested.vmxon)
5809                 return;
5810         vmx->nested.vmxon = false;
5811         if (vmx->nested.current_vmptr != -1ull) {
5812                 nested_release_vmcs12(vmx);
5813                 vmx->nested.current_vmptr = -1ull;
5814                 vmx->nested.current_vmcs12 = NULL;
5815         }
5816         if (enable_shadow_vmcs)
5817                 free_vmcs(vmx->nested.current_shadow_vmcs);
5818         /* Unpin physical memory we referred to in current vmcs02 */
5819         if (vmx->nested.apic_access_page) {
5820                 nested_release_page(vmx->nested.apic_access_page);
5821                 vmx->nested.apic_access_page = 0;
5822         }
5823
5824         nested_free_all_saved_vmcss(vmx);
5825 }
5826
5827 /* Emulate the VMXOFF instruction */
5828 static int handle_vmoff(struct kvm_vcpu *vcpu)
5829 {
5830         if (!nested_vmx_check_permission(vcpu))
5831                 return 1;
5832         free_nested(to_vmx(vcpu));
5833         skip_emulated_instruction(vcpu);
5834         nested_vmx_succeed(vcpu);
5835         return 1;
5836 }
5837
5838 /*
5839  * Decode the memory-address operand of a vmx instruction, as recorded on an
5840  * exit caused by such an instruction (run by a guest hypervisor).
5841  * On success, returns 0. When the operand is invalid, returns 1 and throws
5842  * #UD or #GP.
5843  */
5844 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5845                                  unsigned long exit_qualification,
5846                                  u32 vmx_instruction_info, gva_t *ret)
5847 {
5848         /*
5849          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5850          * Execution", on an exit, vmx_instruction_info holds most of the
5851          * addressing components of the operand. Only the displacement part
5852          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5853          * For how an actual address is calculated from all these components,
5854          * refer to Vol. 1, "Operand Addressing".
5855          */
5856         int  scaling = vmx_instruction_info & 3;
5857         int  addr_size = (vmx_instruction_info >> 7) & 7;
5858         bool is_reg = vmx_instruction_info & (1u << 10);
5859         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5860         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5861         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5862         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5863         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5864
5865         if (is_reg) {
5866                 kvm_queue_exception(vcpu, UD_VECTOR);
5867                 return 1;
5868         }
5869
5870         /* Addr = segment_base + offset */
5871         /* offset = base + [index * scale] + displacement */
5872         *ret = vmx_get_segment_base(vcpu, seg_reg);
5873         if (base_is_valid)
5874                 *ret += kvm_register_read(vcpu, base_reg);
5875         if (index_is_valid)
5876                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5877         *ret += exit_qualification; /* holds the displacement */
5878
5879         if (addr_size == 1) /* 32 bit */
5880                 *ret &= 0xffffffff;
5881
5882         /*
5883          * TODO: throw #GP (and return 1) in various cases that the VM*
5884          * instructions require it - e.g., offset beyond segment limit,
5885          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5886          * address, and so on. Currently these are not checked.
5887          */
5888         return 0;
5889 }
5890
5891 /* Emulate the VMCLEAR instruction */
5892 static int handle_vmclear(struct kvm_vcpu *vcpu)
5893 {
5894         struct vcpu_vmx *vmx = to_vmx(vcpu);
5895         gva_t gva;
5896         gpa_t vmptr;
5897         struct vmcs12 *vmcs12;
5898         struct page *page;
5899         struct x86_exception e;
5900
5901         if (!nested_vmx_check_permission(vcpu))
5902                 return 1;
5903
5904         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5905                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5906                 return 1;
5907
5908         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5909                                 sizeof(vmptr), &e)) {
5910                 kvm_inject_page_fault(vcpu, &e);
5911                 return 1;
5912         }
5913
5914         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5915                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5916                 skip_emulated_instruction(vcpu);
5917                 return 1;
5918         }
5919
5920         if (vmptr == vmx->nested.current_vmptr) {
5921                 nested_release_vmcs12(vmx);
5922                 vmx->nested.current_vmptr = -1ull;
5923                 vmx->nested.current_vmcs12 = NULL;
5924         }
5925
5926         page = nested_get_page(vcpu, vmptr);
5927         if (page == NULL) {
5928                 /*
5929                  * For accurate processor emulation, VMCLEAR beyond available
5930                  * physical memory should do nothing at all. However, it is
5931                  * possible that a nested vmx bug, not a guest hypervisor bug,
5932                  * resulted in this case, so let's shut down before doing any
5933                  * more damage:
5934                  */
5935                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5936                 return 1;
5937         }
5938         vmcs12 = kmap(page);
5939         vmcs12->launch_state = 0;
5940         kunmap(page);
5941         nested_release_page(page);
5942
5943         nested_free_vmcs02(vmx, vmptr);
5944
5945         skip_emulated_instruction(vcpu);
5946         nested_vmx_succeed(vcpu);
5947         return 1;
5948 }
5949
5950 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5951
5952 /* Emulate the VMLAUNCH instruction */
5953 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5954 {
5955         return nested_vmx_run(vcpu, true);
5956 }
5957
5958 /* Emulate the VMRESUME instruction */
5959 static int handle_vmresume(struct kvm_vcpu *vcpu)
5960 {
5961
5962         return nested_vmx_run(vcpu, false);
5963 }
5964
5965 enum vmcs_field_type {
5966         VMCS_FIELD_TYPE_U16 = 0,
5967         VMCS_FIELD_TYPE_U64 = 1,
5968         VMCS_FIELD_TYPE_U32 = 2,
5969         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5970 };
5971
5972 static inline int vmcs_field_type(unsigned long field)
5973 {
5974         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5975                 return VMCS_FIELD_TYPE_U32;
5976         return (field >> 13) & 0x3 ;
5977 }
5978
5979 static inline int vmcs_field_readonly(unsigned long field)
5980 {
5981         return (((field >> 10) & 0x3) == 1);
5982 }
5983
5984 /*
5985  * Read a vmcs12 field. Since these can have varying lengths and we return
5986  * one type, we chose the biggest type (u64) and zero-extend the return value
5987  * to that size. Note that the caller, handle_vmread, might need to use only
5988  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5989  * 64-bit fields are to be returned).
5990  */
5991 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5992                                         unsigned long field, u64 *ret)
5993 {
5994         short offset = vmcs_field_to_offset(field);
5995         char *p;
5996
5997         if (offset < 0)
5998                 return 0;
5999
6000         p = ((char *)(get_vmcs12(vcpu))) + offset;
6001
6002         switch (vmcs_field_type(field)) {
6003         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6004                 *ret = *((natural_width *)p);
6005                 return 1;
6006         case VMCS_FIELD_TYPE_U16:
6007                 *ret = *((u16 *)p);
6008                 return 1;
6009         case VMCS_FIELD_TYPE_U32:
6010                 *ret = *((u32 *)p);
6011                 return 1;
6012         case VMCS_FIELD_TYPE_U64:
6013                 *ret = *((u64 *)p);
6014                 return 1;
6015         default:
6016                 return 0; /* can never happen. */
6017         }
6018 }
6019
6020
6021 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6022                                     unsigned long field, u64 field_value){
6023         short offset = vmcs_field_to_offset(field);
6024         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6025         if (offset < 0)
6026                 return false;
6027
6028         switch (vmcs_field_type(field)) {
6029         case VMCS_FIELD_TYPE_U16:
6030                 *(u16 *)p = field_value;
6031                 return true;
6032         case VMCS_FIELD_TYPE_U32:
6033                 *(u32 *)p = field_value;
6034                 return true;
6035         case VMCS_FIELD_TYPE_U64:
6036                 *(u64 *)p = field_value;
6037                 return true;
6038         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6039                 *(natural_width *)p = field_value;
6040                 return true;
6041         default:
6042                 return false; /* can never happen. */
6043         }
6044
6045 }
6046
6047 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6048 {
6049         int i;
6050         unsigned long field;
6051         u64 field_value;
6052         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6053         const unsigned long *fields = shadow_read_write_fields;
6054         const int num_fields = max_shadow_read_write_fields;
6055
6056         vmcs_load(shadow_vmcs);
6057
6058         for (i = 0; i < num_fields; i++) {
6059                 field = fields[i];
6060                 switch (vmcs_field_type(field)) {
6061                 case VMCS_FIELD_TYPE_U16:
6062                         field_value = vmcs_read16(field);
6063                         break;
6064                 case VMCS_FIELD_TYPE_U32:
6065                         field_value = vmcs_read32(field);
6066                         break;
6067                 case VMCS_FIELD_TYPE_U64:
6068                         field_value = vmcs_read64(field);
6069                         break;
6070                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6071                         field_value = vmcs_readl(field);
6072                         break;
6073                 }
6074                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6075         }
6076
6077         vmcs_clear(shadow_vmcs);
6078         vmcs_load(vmx->loaded_vmcs->vmcs);
6079 }
6080
6081 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6082 {
6083         const unsigned long *fields[] = {
6084                 shadow_read_write_fields,
6085                 shadow_read_only_fields
6086         };
6087         const int max_fields[] = {
6088                 max_shadow_read_write_fields,
6089                 max_shadow_read_only_fields
6090         };
6091         int i, q;
6092         unsigned long field;
6093         u64 field_value = 0;
6094         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6095
6096         vmcs_load(shadow_vmcs);
6097
6098         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6099                 for (i = 0; i < max_fields[q]; i++) {
6100                         field = fields[q][i];
6101                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6102
6103                         switch (vmcs_field_type(field)) {
6104                         case VMCS_FIELD_TYPE_U16:
6105                                 vmcs_write16(field, (u16)field_value);
6106                                 break;
6107                         case VMCS_FIELD_TYPE_U32:
6108                                 vmcs_write32(field, (u32)field_value);
6109                                 break;
6110                         case VMCS_FIELD_TYPE_U64:
6111                                 vmcs_write64(field, (u64)field_value);
6112                                 break;
6113                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6114                                 vmcs_writel(field, (long)field_value);
6115                                 break;
6116                         }
6117                 }
6118         }
6119
6120         vmcs_clear(shadow_vmcs);
6121         vmcs_load(vmx->loaded_vmcs->vmcs);
6122 }
6123
6124 /*
6125  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6126  * used before) all generate the same failure when it is missing.
6127  */
6128 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6129 {
6130         struct vcpu_vmx *vmx = to_vmx(vcpu);
6131         if (vmx->nested.current_vmptr == -1ull) {
6132                 nested_vmx_failInvalid(vcpu);
6133                 skip_emulated_instruction(vcpu);
6134                 return 0;
6135         }
6136         return 1;
6137 }
6138
6139 static int handle_vmread(struct kvm_vcpu *vcpu)
6140 {
6141         unsigned long field;
6142         u64 field_value;
6143         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6144         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6145         gva_t gva = 0;
6146
6147         if (!nested_vmx_check_permission(vcpu) ||
6148             !nested_vmx_check_vmcs12(vcpu))
6149                 return 1;
6150
6151         /* Decode instruction info and find the field to read */
6152         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6153         /* Read the field, zero-extended to a u64 field_value */
6154         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6155                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6156                 skip_emulated_instruction(vcpu);
6157                 return 1;
6158         }
6159         /*
6160          * Now copy part of this value to register or memory, as requested.
6161          * Note that the number of bits actually copied is 32 or 64 depending
6162          * on the guest's mode (32 or 64 bit), not on the given field's length.
6163          */
6164         if (vmx_instruction_info & (1u << 10)) {
6165                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6166                         field_value);
6167         } else {
6168                 if (get_vmx_mem_address(vcpu, exit_qualification,
6169                                 vmx_instruction_info, &gva))
6170                         return 1;
6171                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6172                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6173                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6174         }
6175
6176         nested_vmx_succeed(vcpu);
6177         skip_emulated_instruction(vcpu);
6178         return 1;
6179 }
6180
6181
6182 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6183 {
6184         unsigned long field;
6185         gva_t gva;
6186         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6187         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6188         /* The value to write might be 32 or 64 bits, depending on L1's long
6189          * mode, and eventually we need to write that into a field of several
6190          * possible lengths. The code below first zero-extends the value to 64
6191          * bit (field_value), and then copies only the approriate number of
6192          * bits into the vmcs12 field.
6193          */
6194         u64 field_value = 0;
6195         struct x86_exception e;
6196
6197         if (!nested_vmx_check_permission(vcpu) ||
6198             !nested_vmx_check_vmcs12(vcpu))
6199                 return 1;
6200
6201         if (vmx_instruction_info & (1u << 10))
6202                 field_value = kvm_register_read(vcpu,
6203                         (((vmx_instruction_info) >> 3) & 0xf));
6204         else {
6205                 if (get_vmx_mem_address(vcpu, exit_qualification,
6206                                 vmx_instruction_info, &gva))
6207                         return 1;
6208                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6209                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6210                         kvm_inject_page_fault(vcpu, &e);
6211                         return 1;
6212                 }
6213         }
6214
6215
6216         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6217         if (vmcs_field_readonly(field)) {
6218                 nested_vmx_failValid(vcpu,
6219                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6220                 skip_emulated_instruction(vcpu);
6221                 return 1;
6222         }
6223
6224         if (!vmcs12_write_any(vcpu, field, field_value)) {
6225                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6226                 skip_emulated_instruction(vcpu);
6227                 return 1;
6228         }
6229
6230         nested_vmx_succeed(vcpu);
6231         skip_emulated_instruction(vcpu);
6232         return 1;
6233 }
6234
6235 /* Emulate the VMPTRLD instruction */
6236 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6237 {
6238         struct vcpu_vmx *vmx = to_vmx(vcpu);
6239         gva_t gva;
6240         gpa_t vmptr;
6241         struct x86_exception e;
6242         u32 exec_control;
6243
6244         if (!nested_vmx_check_permission(vcpu))
6245                 return 1;
6246
6247         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6248                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6249                 return 1;
6250
6251         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6252                                 sizeof(vmptr), &e)) {
6253                 kvm_inject_page_fault(vcpu, &e);
6254                 return 1;
6255         }
6256
6257         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6258                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6259                 skip_emulated_instruction(vcpu);
6260                 return 1;
6261         }
6262
6263         if (vmx->nested.current_vmptr != vmptr) {
6264                 struct vmcs12 *new_vmcs12;
6265                 struct page *page;
6266                 page = nested_get_page(vcpu, vmptr);
6267                 if (page == NULL) {
6268                         nested_vmx_failInvalid(vcpu);
6269                         skip_emulated_instruction(vcpu);
6270                         return 1;
6271                 }
6272                 new_vmcs12 = kmap(page);
6273                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6274                         kunmap(page);
6275                         nested_release_page_clean(page);
6276                         nested_vmx_failValid(vcpu,
6277                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6278                         skip_emulated_instruction(vcpu);
6279                         return 1;
6280                 }
6281                 if (vmx->nested.current_vmptr != -1ull)
6282                         nested_release_vmcs12(vmx);
6283
6284                 vmx->nested.current_vmptr = vmptr;
6285                 vmx->nested.current_vmcs12 = new_vmcs12;
6286                 vmx->nested.current_vmcs12_page = page;
6287                 if (enable_shadow_vmcs) {
6288                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6289                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6290                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6291                         vmcs_write64(VMCS_LINK_POINTER,
6292                                      __pa(vmx->nested.current_shadow_vmcs));
6293                         vmx->nested.sync_shadow_vmcs = true;
6294                 }
6295         }
6296
6297         nested_vmx_succeed(vcpu);
6298         skip_emulated_instruction(vcpu);
6299         return 1;
6300 }
6301
6302 /* Emulate the VMPTRST instruction */
6303 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6304 {
6305         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6306         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6307         gva_t vmcs_gva;
6308         struct x86_exception e;
6309
6310         if (!nested_vmx_check_permission(vcpu))
6311                 return 1;
6312
6313         if (get_vmx_mem_address(vcpu, exit_qualification,
6314                         vmx_instruction_info, &vmcs_gva))
6315                 return 1;
6316         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6317         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6318                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6319                                  sizeof(u64), &e)) {
6320                 kvm_inject_page_fault(vcpu, &e);
6321                 return 1;
6322         }
6323         nested_vmx_succeed(vcpu);
6324         skip_emulated_instruction(vcpu);
6325         return 1;
6326 }
6327
6328 /* Emulate the INVEPT instruction */
6329 static int handle_invept(struct kvm_vcpu *vcpu)
6330 {
6331         u32 vmx_instruction_info, types;
6332         unsigned long type;
6333         gva_t gva;
6334         struct x86_exception e;
6335         struct {
6336                 u64 eptp, gpa;
6337         } operand;
6338         u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6339
6340         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6341             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6342                 kvm_queue_exception(vcpu, UD_VECTOR);
6343                 return 1;
6344         }
6345
6346         if (!nested_vmx_check_permission(vcpu))
6347                 return 1;
6348
6349         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6350                 kvm_queue_exception(vcpu, UD_VECTOR);
6351                 return 1;
6352         }
6353
6354         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6355         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6356
6357         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6358
6359         if (!(types & (1UL << type))) {
6360                 nested_vmx_failValid(vcpu,
6361                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6362                 return 1;
6363         }
6364
6365         /* According to the Intel VMX instruction reference, the memory
6366          * operand is read even if it isn't needed (e.g., for type==global)
6367          */
6368         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6369                         vmx_instruction_info, &gva))
6370                 return 1;
6371         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6372                                 sizeof(operand), &e)) {
6373                 kvm_inject_page_fault(vcpu, &e);
6374                 return 1;
6375         }
6376
6377         switch (type) {
6378         case VMX_EPT_EXTENT_CONTEXT:
6379                 if ((operand.eptp & eptp_mask) !=
6380                                 (nested_ept_get_cr3(vcpu) & eptp_mask))
6381                         break;
6382         case VMX_EPT_EXTENT_GLOBAL:
6383                 kvm_mmu_sync_roots(vcpu);
6384                 kvm_mmu_flush_tlb(vcpu);
6385                 nested_vmx_succeed(vcpu);
6386                 break;
6387         default:
6388                 BUG_ON(1);
6389                 break;
6390         }
6391
6392         skip_emulated_instruction(vcpu);
6393         return 1;
6394 }
6395
6396 /*
6397  * The exit handlers return 1 if the exit was handled fully and guest execution
6398  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6399  * to be done to userspace and return 0.
6400  */
6401 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6402         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6403         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6404         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6405         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6406         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6407         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6408         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6409         [EXIT_REASON_CPUID]                   = handle_cpuid,
6410         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6411         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6412         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6413         [EXIT_REASON_HLT]                     = handle_halt,
6414         [EXIT_REASON_INVD]                    = handle_invd,
6415         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6416         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6417         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6418         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6419         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6420         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6421         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6422         [EXIT_REASON_VMREAD]                  = handle_vmread,
6423         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6424         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6425         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6426         [EXIT_REASON_VMON]                    = handle_vmon,
6427         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6428         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6429         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6430         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6431         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6432         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6433         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6434         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6435         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6436         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6437         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6438         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6439         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6440         [EXIT_REASON_INVEPT]                  = handle_invept,
6441 };
6442
6443 static const int kvm_vmx_max_exit_handlers =
6444         ARRAY_SIZE(kvm_vmx_exit_handlers);
6445
6446 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6447                                        struct vmcs12 *vmcs12)
6448 {
6449         unsigned long exit_qualification;
6450         gpa_t bitmap, last_bitmap;
6451         unsigned int port;
6452         int size;
6453         u8 b;
6454
6455         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6456                 return 1;
6457
6458         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6459                 return 0;
6460
6461         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6462
6463         port = exit_qualification >> 16;
6464         size = (exit_qualification & 7) + 1;
6465
6466         last_bitmap = (gpa_t)-1;
6467         b = -1;
6468
6469         while (size > 0) {
6470                 if (port < 0x8000)
6471                         bitmap = vmcs12->io_bitmap_a;
6472                 else if (port < 0x10000)
6473                         bitmap = vmcs12->io_bitmap_b;
6474                 else
6475                         return 1;
6476                 bitmap += (port & 0x7fff) / 8;
6477
6478                 if (last_bitmap != bitmap)
6479                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6480                                 return 1;
6481                 if (b & (1 << (port & 7)))
6482                         return 1;
6483
6484                 port++;
6485                 size--;
6486                 last_bitmap = bitmap;
6487         }
6488
6489         return 0;
6490 }
6491
6492 /*
6493  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6494  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6495  * disinterest in the current event (read or write a specific MSR) by using an
6496  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6497  */
6498 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6499         struct vmcs12 *vmcs12, u32 exit_reason)
6500 {
6501         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6502         gpa_t bitmap;
6503
6504         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6505                 return 1;
6506
6507         /*
6508          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6509          * for the four combinations of read/write and low/high MSR numbers.
6510          * First we need to figure out which of the four to use:
6511          */
6512         bitmap = vmcs12->msr_bitmap;
6513         if (exit_reason == EXIT_REASON_MSR_WRITE)
6514                 bitmap += 2048;
6515         if (msr_index >= 0xc0000000) {
6516                 msr_index -= 0xc0000000;
6517                 bitmap += 1024;
6518         }
6519
6520         /* Then read the msr_index'th bit from this bitmap: */
6521         if (msr_index < 1024*8) {
6522                 unsigned char b;
6523                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6524                         return 1;
6525                 return 1 & (b >> (msr_index & 7));
6526         } else
6527                 return 1; /* let L1 handle the wrong parameter */
6528 }
6529
6530 /*
6531  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6532  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6533  * intercept (via guest_host_mask etc.) the current event.
6534  */
6535 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6536         struct vmcs12 *vmcs12)
6537 {
6538         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6539         int cr = exit_qualification & 15;
6540         int reg = (exit_qualification >> 8) & 15;
6541         unsigned long val = kvm_register_read(vcpu, reg);
6542
6543         switch ((exit_qualification >> 4) & 3) {
6544         case 0: /* mov to cr */
6545                 switch (cr) {
6546                 case 0:
6547                         if (vmcs12->cr0_guest_host_mask &
6548                             (val ^ vmcs12->cr0_read_shadow))
6549                                 return 1;
6550                         break;
6551                 case 3:
6552                         if ((vmcs12->cr3_target_count >= 1 &&
6553                                         vmcs12->cr3_target_value0 == val) ||
6554                                 (vmcs12->cr3_target_count >= 2 &&
6555                                         vmcs12->cr3_target_value1 == val) ||
6556                                 (vmcs12->cr3_target_count >= 3 &&
6557                                         vmcs12->cr3_target_value2 == val) ||
6558                                 (vmcs12->cr3_target_count >= 4 &&
6559                                         vmcs12->cr3_target_value3 == val))
6560                                 return 0;
6561                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6562                                 return 1;
6563                         break;
6564                 case 4:
6565                         if (vmcs12->cr4_guest_host_mask &
6566                             (vmcs12->cr4_read_shadow ^ val))
6567                                 return 1;
6568                         break;
6569                 case 8:
6570                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6571                                 return 1;
6572                         break;
6573                 }
6574                 break;
6575         case 2: /* clts */
6576                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6577                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6578                         return 1;
6579                 break;
6580         case 1: /* mov from cr */
6581                 switch (cr) {
6582                 case 3:
6583                         if (vmcs12->cpu_based_vm_exec_control &
6584                             CPU_BASED_CR3_STORE_EXITING)
6585                                 return 1;
6586                         break;
6587                 case 8:
6588                         if (vmcs12->cpu_based_vm_exec_control &
6589                             CPU_BASED_CR8_STORE_EXITING)
6590                                 return 1;
6591                         break;
6592                 }
6593                 break;
6594         case 3: /* lmsw */
6595                 /*
6596                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6597                  * cr0. Other attempted changes are ignored, with no exit.
6598                  */
6599                 if (vmcs12->cr0_guest_host_mask & 0xe &
6600                     (val ^ vmcs12->cr0_read_shadow))
6601                         return 1;
6602                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6603                     !(vmcs12->cr0_read_shadow & 0x1) &&
6604                     (val & 0x1))
6605                         return 1;
6606                 break;
6607         }
6608         return 0;
6609 }
6610
6611 /*
6612  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6613  * should handle it ourselves in L0 (and then continue L2). Only call this
6614  * when in is_guest_mode (L2).
6615  */
6616 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6617 {
6618         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6619         struct vcpu_vmx *vmx = to_vmx(vcpu);
6620         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6621         u32 exit_reason = vmx->exit_reason;
6622
6623         if (vmx->nested.nested_run_pending)
6624                 return 0;
6625
6626         if (unlikely(vmx->fail)) {
6627                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6628                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6629                 return 1;
6630         }
6631
6632         switch (exit_reason) {
6633         case EXIT_REASON_EXCEPTION_NMI:
6634                 if (!is_exception(intr_info))
6635                         return 0;
6636                 else if (is_page_fault(intr_info))
6637                         return enable_ept;
6638                 return vmcs12->exception_bitmap &
6639                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6640         case EXIT_REASON_EXTERNAL_INTERRUPT:
6641                 return 0;
6642         case EXIT_REASON_TRIPLE_FAULT:
6643                 return 1;
6644         case EXIT_REASON_PENDING_INTERRUPT:
6645                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6646         case EXIT_REASON_NMI_WINDOW:
6647                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6648         case EXIT_REASON_TASK_SWITCH:
6649                 return 1;
6650         case EXIT_REASON_CPUID:
6651                 return 1;
6652         case EXIT_REASON_HLT:
6653                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6654         case EXIT_REASON_INVD:
6655                 return 1;
6656         case EXIT_REASON_INVLPG:
6657                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6658         case EXIT_REASON_RDPMC:
6659                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6660         case EXIT_REASON_RDTSC:
6661                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6662         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6663         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6664         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6665         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6666         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6667         case EXIT_REASON_INVEPT:
6668                 /*
6669                  * VMX instructions trap unconditionally. This allows L1 to
6670                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6671                  */
6672                 return 1;
6673         case EXIT_REASON_CR_ACCESS:
6674                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6675         case EXIT_REASON_DR_ACCESS:
6676                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6677         case EXIT_REASON_IO_INSTRUCTION:
6678                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6679         case EXIT_REASON_MSR_READ:
6680         case EXIT_REASON_MSR_WRITE:
6681                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6682         case EXIT_REASON_INVALID_STATE:
6683                 return 1;
6684         case EXIT_REASON_MWAIT_INSTRUCTION:
6685                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6686         case EXIT_REASON_MONITOR_INSTRUCTION:
6687                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6688         case EXIT_REASON_PAUSE_INSTRUCTION:
6689                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6690                         nested_cpu_has2(vmcs12,
6691                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6692         case EXIT_REASON_MCE_DURING_VMENTRY:
6693                 return 0;
6694         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6695                 return 1;
6696         case EXIT_REASON_APIC_ACCESS:
6697                 return nested_cpu_has2(vmcs12,
6698                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6699         case EXIT_REASON_EPT_VIOLATION:
6700                 /*
6701                  * L0 always deals with the EPT violation. If nested EPT is
6702                  * used, and the nested mmu code discovers that the address is
6703                  * missing in the guest EPT table (EPT12), the EPT violation
6704                  * will be injected with nested_ept_inject_page_fault()
6705                  */
6706                 return 0;
6707         case EXIT_REASON_EPT_MISCONFIG:
6708                 /*
6709                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6710                  * table (shadow on EPT) or a merged EPT table that L0 built
6711                  * (EPT on EPT). So any problems with the structure of the
6712                  * table is L0's fault.
6713                  */
6714                 return 0;
6715         case EXIT_REASON_PREEMPTION_TIMER:
6716                 return vmcs12->pin_based_vm_exec_control &
6717                         PIN_BASED_VMX_PREEMPTION_TIMER;
6718         case EXIT_REASON_WBINVD:
6719                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6720         case EXIT_REASON_XSETBV:
6721                 return 1;
6722         default:
6723                 return 1;
6724         }
6725 }
6726
6727 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6728 {
6729         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6730         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6731 }
6732
6733 static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6734 {
6735         u64 delta_tsc_l1;
6736         u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6737
6738         if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6739                         PIN_BASED_VMX_PREEMPTION_TIMER))
6740                 return;
6741         preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6742                         MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6743         preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6744         delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6745                 - vcpu->arch.last_guest_tsc;
6746         preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6747         if (preempt_val_l2 <= preempt_val_l1)
6748                 preempt_val_l2 = 0;
6749         else
6750                 preempt_val_l2 -= preempt_val_l1;
6751         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6752 }
6753
6754 /*
6755  * The guest has exited.  See if we can fix it or if we need userspace
6756  * assistance.
6757  */
6758 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6759 {
6760         struct vcpu_vmx *vmx = to_vmx(vcpu);
6761         u32 exit_reason = vmx->exit_reason;
6762         u32 vectoring_info = vmx->idt_vectoring_info;
6763
6764         /* If guest state is invalid, start emulating */
6765         if (vmx->emulation_required)
6766                 return handle_invalid_guest_state(vcpu);
6767
6768         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6769                 nested_vmx_vmexit(vcpu);
6770                 return 1;
6771         }
6772
6773         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6774                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6775                 vcpu->run->fail_entry.hardware_entry_failure_reason
6776                         = exit_reason;
6777                 return 0;
6778         }
6779
6780         if (unlikely(vmx->fail)) {
6781                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6782                 vcpu->run->fail_entry.hardware_entry_failure_reason
6783                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6784                 return 0;
6785         }
6786
6787         /*
6788          * Note:
6789          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6790          * delivery event since it indicates guest is accessing MMIO.
6791          * The vm-exit can be triggered again after return to guest that
6792          * will cause infinite loop.
6793          */
6794         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6795                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6796                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6797                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6798                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6799                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6800                 vcpu->run->internal.ndata = 2;
6801                 vcpu->run->internal.data[0] = vectoring_info;
6802                 vcpu->run->internal.data[1] = exit_reason;
6803                 return 0;
6804         }
6805
6806         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6807             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6808                                         get_vmcs12(vcpu))))) {
6809                 if (vmx_interrupt_allowed(vcpu)) {
6810                         vmx->soft_vnmi_blocked = 0;
6811                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6812                            vcpu->arch.nmi_pending) {
6813                         /*
6814                          * This CPU don't support us in finding the end of an
6815                          * NMI-blocked window if the guest runs with IRQs
6816                          * disabled. So we pull the trigger after 1 s of
6817                          * futile waiting, but inform the user about this.
6818                          */
6819                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6820                                "state on VCPU %d after 1 s timeout\n",
6821                                __func__, vcpu->vcpu_id);
6822                         vmx->soft_vnmi_blocked = 0;
6823                 }
6824         }
6825
6826         if (exit_reason < kvm_vmx_max_exit_handlers
6827             && kvm_vmx_exit_handlers[exit_reason])
6828                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6829         else {
6830                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6831                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6832         }
6833         return 0;
6834 }
6835
6836 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6837 {
6838         if (irr == -1 || tpr < irr) {
6839                 vmcs_write32(TPR_THRESHOLD, 0);
6840                 return;
6841         }
6842
6843         vmcs_write32(TPR_THRESHOLD, irr);
6844 }
6845
6846 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6847 {
6848         u32 sec_exec_control;
6849
6850         /*
6851          * There is not point to enable virtualize x2apic without enable
6852          * apicv
6853          */
6854         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6855                                 !vmx_vm_has_apicv(vcpu->kvm))
6856                 return;
6857
6858         if (!vm_need_tpr_shadow(vcpu->kvm))
6859                 return;
6860
6861         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6862
6863         if (set) {
6864                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6865                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6866         } else {
6867                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6868                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6869         }
6870         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6871
6872         vmx_set_msr_bitmap(vcpu);
6873 }
6874
6875 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6876 {
6877         u16 status;
6878         u8 old;
6879
6880         if (!vmx_vm_has_apicv(kvm))
6881                 return;
6882
6883         if (isr == -1)
6884                 isr = 0;
6885
6886         status = vmcs_read16(GUEST_INTR_STATUS);
6887         old = status >> 8;
6888         if (isr != old) {
6889                 status &= 0xff;
6890                 status |= isr << 8;
6891                 vmcs_write16(GUEST_INTR_STATUS, status);
6892         }
6893 }
6894
6895 static void vmx_set_rvi(int vector)
6896 {
6897         u16 status;
6898         u8 old;
6899
6900         status = vmcs_read16(GUEST_INTR_STATUS);
6901         old = (u8)status & 0xff;
6902         if ((u8)vector != old) {
6903                 status &= ~0xff;
6904                 status |= (u8)vector;
6905                 vmcs_write16(GUEST_INTR_STATUS, status);
6906         }
6907 }
6908
6909 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6910 {
6911         if (max_irr == -1)
6912                 return;
6913
6914         vmx_set_rvi(max_irr);
6915 }
6916
6917 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6918 {
6919         if (!vmx_vm_has_apicv(vcpu->kvm))
6920                 return;
6921
6922         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6923         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6924         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6925         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6926 }
6927
6928 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6929 {
6930         u32 exit_intr_info;
6931
6932         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6933               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6934                 return;
6935
6936         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6937         exit_intr_info = vmx->exit_intr_info;
6938
6939         /* Handle machine checks before interrupts are enabled */
6940         if (is_machine_check(exit_intr_info))
6941                 kvm_machine_check();
6942
6943         /* We need to handle NMIs before interrupts are enabled */
6944         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6945             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6946                 kvm_before_handle_nmi(&vmx->vcpu);
6947                 asm("int $2");
6948                 kvm_after_handle_nmi(&vmx->vcpu);
6949         }
6950 }
6951
6952 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6953 {
6954         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6955
6956         /*
6957          * If external interrupt exists, IF bit is set in rflags/eflags on the
6958          * interrupt stack frame, and interrupt will be enabled on a return
6959          * from interrupt handler.
6960          */
6961         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6962                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6963                 unsigned int vector;
6964                 unsigned long entry;
6965                 gate_desc *desc;
6966                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6967 #ifdef CONFIG_X86_64
6968                 unsigned long tmp;
6969 #endif
6970
6971                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6972                 desc = (gate_desc *)vmx->host_idt_base + vector;
6973                 entry = gate_offset(*desc);
6974                 asm volatile(
6975 #ifdef CONFIG_X86_64
6976                         "mov %%" _ASM_SP ", %[sp]\n\t"
6977                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6978                         "push $%c[ss]\n\t"
6979                         "push %[sp]\n\t"
6980 #endif
6981                         "pushf\n\t"
6982                         "orl $0x200, (%%" _ASM_SP ")\n\t"
6983                         __ASM_SIZE(push) " $%c[cs]\n\t"
6984                         "call *%[entry]\n\t"
6985                         :
6986 #ifdef CONFIG_X86_64
6987                         [sp]"=&r"(tmp)
6988 #endif
6989                         :
6990                         [entry]"r"(entry),
6991                         [ss]"i"(__KERNEL_DS),
6992                         [cs]"i"(__KERNEL_CS)
6993                         );
6994         } else
6995                 local_irq_enable();
6996 }
6997
6998 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6999 {
7000         u32 exit_intr_info;
7001         bool unblock_nmi;
7002         u8 vector;
7003         bool idtv_info_valid;
7004
7005         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7006
7007         if (cpu_has_virtual_nmis()) {
7008                 if (vmx->nmi_known_unmasked)
7009                         return;
7010                 /*
7011                  * Can't use vmx->exit_intr_info since we're not sure what
7012                  * the exit reason is.
7013                  */
7014                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7015                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7016                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7017                 /*
7018                  * SDM 3: 27.7.1.2 (September 2008)
7019                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7020                  * a guest IRET fault.
7021                  * SDM 3: 23.2.2 (September 2008)
7022                  * Bit 12 is undefined in any of the following cases:
7023                  *  If the VM exit sets the valid bit in the IDT-vectoring
7024                  *   information field.
7025                  *  If the VM exit is due to a double fault.
7026                  */
7027                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7028                     vector != DF_VECTOR && !idtv_info_valid)
7029                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7030                                       GUEST_INTR_STATE_NMI);
7031                 else
7032                         vmx->nmi_known_unmasked =
7033                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7034                                   & GUEST_INTR_STATE_NMI);
7035         } else if (unlikely(vmx->soft_vnmi_blocked))
7036                 vmx->vnmi_blocked_time +=
7037                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7038 }
7039
7040 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7041                                       u32 idt_vectoring_info,
7042                                       int instr_len_field,
7043                                       int error_code_field)
7044 {
7045         u8 vector;
7046         int type;
7047         bool idtv_info_valid;
7048
7049         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7050
7051         vcpu->arch.nmi_injected = false;
7052         kvm_clear_exception_queue(vcpu);
7053         kvm_clear_interrupt_queue(vcpu);
7054
7055         if (!idtv_info_valid)
7056                 return;
7057
7058         kvm_make_request(KVM_REQ_EVENT, vcpu);
7059
7060         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7061         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7062
7063         switch (type) {
7064         case INTR_TYPE_NMI_INTR:
7065                 vcpu->arch.nmi_injected = true;
7066                 /*
7067                  * SDM 3: 27.7.1.2 (September 2008)
7068                  * Clear bit "block by NMI" before VM entry if a NMI
7069                  * delivery faulted.
7070                  */
7071                 vmx_set_nmi_mask(vcpu, false);
7072                 break;
7073         case INTR_TYPE_SOFT_EXCEPTION:
7074                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7075                 /* fall through */
7076         case INTR_TYPE_HARD_EXCEPTION:
7077                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7078                         u32 err = vmcs_read32(error_code_field);
7079                         kvm_requeue_exception_e(vcpu, vector, err);
7080                 } else
7081                         kvm_requeue_exception(vcpu, vector);
7082                 break;
7083         case INTR_TYPE_SOFT_INTR:
7084                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7085                 /* fall through */
7086         case INTR_TYPE_EXT_INTR:
7087                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7088                 break;
7089         default:
7090                 break;
7091         }
7092 }
7093
7094 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7095 {
7096         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7097                                   VM_EXIT_INSTRUCTION_LEN,
7098                                   IDT_VECTORING_ERROR_CODE);
7099 }
7100
7101 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7102 {
7103         __vmx_complete_interrupts(vcpu,
7104                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7105                                   VM_ENTRY_INSTRUCTION_LEN,
7106                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7107
7108         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7109 }
7110
7111 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7112 {
7113         int i, nr_msrs;
7114         struct perf_guest_switch_msr *msrs;
7115
7116         msrs = perf_guest_get_msrs(&nr_msrs);
7117
7118         if (!msrs)
7119                 return;
7120
7121         for (i = 0; i < nr_msrs; i++)
7122                 if (msrs[i].host == msrs[i].guest)
7123                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7124                 else
7125                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7126                                         msrs[i].host);
7127 }
7128
7129 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7130 {
7131         struct vcpu_vmx *vmx = to_vmx(vcpu);
7132         unsigned long debugctlmsr;
7133
7134         /* Record the guest's net vcpu time for enforced NMI injections. */
7135         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7136                 vmx->entry_time = ktime_get();
7137
7138         /* Don't enter VMX if guest state is invalid, let the exit handler
7139            start emulation until we arrive back to a valid state */
7140         if (vmx->emulation_required)
7141                 return;
7142
7143         if (vmx->nested.sync_shadow_vmcs) {
7144                 copy_vmcs12_to_shadow(vmx);
7145                 vmx->nested.sync_shadow_vmcs = false;
7146         }
7147
7148         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7149                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7150         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7151                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7152
7153         /* When single-stepping over STI and MOV SS, we must clear the
7154          * corresponding interruptibility bits in the guest state. Otherwise
7155          * vmentry fails as it then expects bit 14 (BS) in pending debug
7156          * exceptions being set, but that's not correct for the guest debugging
7157          * case. */
7158         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7159                 vmx_set_interrupt_shadow(vcpu, 0);
7160
7161         atomic_switch_perf_msrs(vmx);
7162         debugctlmsr = get_debugctlmsr();
7163
7164         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7165                 nested_adjust_preemption_timer(vcpu);
7166         vmx->__launched = vmx->loaded_vmcs->launched;
7167         asm(
7168                 /* Store host registers */
7169                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7170                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7171                 "push %%" _ASM_CX " \n\t"
7172                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7173                 "je 1f \n\t"
7174                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7175                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7176                 "1: \n\t"
7177                 /* Reload cr2 if changed */
7178                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7179                 "mov %%cr2, %%" _ASM_DX " \n\t"
7180                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7181                 "je 2f \n\t"
7182                 "mov %%" _ASM_AX", %%cr2 \n\t"
7183                 "2: \n\t"
7184                 /* Check if vmlaunch of vmresume is needed */
7185                 "cmpl $0, %c[launched](%0) \n\t"
7186                 /* Load guest registers.  Don't clobber flags. */
7187                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7188                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7189                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7190                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7191                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7192                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7193 #ifdef CONFIG_X86_64
7194                 "mov %c[r8](%0),  %%r8  \n\t"
7195                 "mov %c[r9](%0),  %%r9  \n\t"
7196                 "mov %c[r10](%0), %%r10 \n\t"
7197                 "mov %c[r11](%0), %%r11 \n\t"
7198                 "mov %c[r12](%0), %%r12 \n\t"
7199                 "mov %c[r13](%0), %%r13 \n\t"
7200                 "mov %c[r14](%0), %%r14 \n\t"
7201                 "mov %c[r15](%0), %%r15 \n\t"
7202 #endif
7203                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7204
7205                 /* Enter guest mode */
7206                 "jne 1f \n\t"
7207                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7208                 "jmp 2f \n\t"
7209                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7210                 "2: "
7211                 /* Save guest registers, load host registers, keep flags */
7212                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7213                 "pop %0 \n\t"
7214                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7215                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7216                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7217                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7218                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7219                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7220                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7221 #ifdef CONFIG_X86_64
7222                 "mov %%r8,  %c[r8](%0) \n\t"
7223                 "mov %%r9,  %c[r9](%0) \n\t"
7224                 "mov %%r10, %c[r10](%0) \n\t"
7225                 "mov %%r11, %c[r11](%0) \n\t"
7226                 "mov %%r12, %c[r12](%0) \n\t"
7227                 "mov %%r13, %c[r13](%0) \n\t"
7228                 "mov %%r14, %c[r14](%0) \n\t"
7229                 "mov %%r15, %c[r15](%0) \n\t"
7230 #endif
7231                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7232                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7233
7234                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7235                 "setbe %c[fail](%0) \n\t"
7236                 ".pushsection .rodata \n\t"
7237                 ".global vmx_return \n\t"
7238                 "vmx_return: " _ASM_PTR " 2b \n\t"
7239                 ".popsection"
7240               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7241                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7242                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7243                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7244                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7245                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7246                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7247                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7248                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7249                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7250                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7251 #ifdef CONFIG_X86_64
7252                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7253                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7254                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7255                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7256                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7257                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7258                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7259                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7260 #endif
7261                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7262                 [wordsize]"i"(sizeof(ulong))
7263               : "cc", "memory"
7264 #ifdef CONFIG_X86_64
7265                 , "rax", "rbx", "rdi", "rsi"
7266                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7267 #else
7268                 , "eax", "ebx", "edi", "esi"
7269 #endif
7270               );
7271
7272         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7273         if (debugctlmsr)
7274                 update_debugctlmsr(debugctlmsr);
7275
7276 #ifndef CONFIG_X86_64
7277         /*
7278          * The sysexit path does not restore ds/es, so we must set them to
7279          * a reasonable value ourselves.
7280          *
7281          * We can't defer this to vmx_load_host_state() since that function
7282          * may be executed in interrupt context, which saves and restore segments
7283          * around it, nullifying its effect.
7284          */
7285         loadsegment(ds, __USER_DS);
7286         loadsegment(es, __USER_DS);
7287 #endif
7288
7289         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7290                                   | (1 << VCPU_EXREG_RFLAGS)
7291                                   | (1 << VCPU_EXREG_CPL)
7292                                   | (1 << VCPU_EXREG_PDPTR)
7293                                   | (1 << VCPU_EXREG_SEGMENTS)
7294                                   | (1 << VCPU_EXREG_CR3));
7295         vcpu->arch.regs_dirty = 0;
7296
7297         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7298
7299         vmx->loaded_vmcs->launched = 1;
7300
7301         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7302         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7303
7304         /*
7305          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7306          * we did not inject a still-pending event to L1 now because of
7307          * nested_run_pending, we need to re-enable this bit.
7308          */
7309         if (vmx->nested.nested_run_pending)
7310                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7311
7312         vmx->nested.nested_run_pending = 0;
7313
7314         vmx_complete_atomic_exit(vmx);
7315         vmx_recover_nmi_blocking(vmx);
7316         vmx_complete_interrupts(vmx);
7317 }
7318
7319 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7320 {
7321         struct vcpu_vmx *vmx = to_vmx(vcpu);
7322
7323         free_vpid(vmx);
7324         free_nested(vmx);
7325         free_loaded_vmcs(vmx->loaded_vmcs);
7326         kfree(vmx->guest_msrs);
7327         kvm_vcpu_uninit(vcpu);
7328         kmem_cache_free(kvm_vcpu_cache, vmx);
7329 }
7330
7331 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7332 {
7333         int err;
7334         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7335         int cpu;
7336
7337         if (!vmx)
7338                 return ERR_PTR(-ENOMEM);
7339
7340         allocate_vpid(vmx);
7341
7342         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7343         if (err)
7344                 goto free_vcpu;
7345
7346         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7347         err = -ENOMEM;
7348         if (!vmx->guest_msrs) {
7349                 goto uninit_vcpu;
7350         }
7351
7352         vmx->loaded_vmcs = &vmx->vmcs01;
7353         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7354         if (!vmx->loaded_vmcs->vmcs)
7355                 goto free_msrs;
7356         if (!vmm_exclusive)
7357                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7358         loaded_vmcs_init(vmx->loaded_vmcs);
7359         if (!vmm_exclusive)
7360                 kvm_cpu_vmxoff();
7361
7362         cpu = get_cpu();
7363         vmx_vcpu_load(&vmx->vcpu, cpu);
7364         vmx->vcpu.cpu = cpu;
7365         err = vmx_vcpu_setup(vmx);
7366         vmx_vcpu_put(&vmx->vcpu);
7367         put_cpu();
7368         if (err)
7369                 goto free_vmcs;
7370         if (vm_need_virtualize_apic_accesses(kvm)) {
7371                 err = alloc_apic_access_page(kvm);
7372                 if (err)
7373                         goto free_vmcs;
7374         }
7375
7376         if (enable_ept) {
7377                 if (!kvm->arch.ept_identity_map_addr)
7378                         kvm->arch.ept_identity_map_addr =
7379                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7380                 err = -ENOMEM;
7381                 if (alloc_identity_pagetable(kvm) != 0)
7382                         goto free_vmcs;
7383                 if (!init_rmode_identity_map(kvm))
7384                         goto free_vmcs;
7385         }
7386
7387         vmx->nested.current_vmptr = -1ull;
7388         vmx->nested.current_vmcs12 = NULL;
7389
7390         return &vmx->vcpu;
7391
7392 free_vmcs:
7393         free_loaded_vmcs(vmx->loaded_vmcs);
7394 free_msrs:
7395         kfree(vmx->guest_msrs);
7396 uninit_vcpu:
7397         kvm_vcpu_uninit(&vmx->vcpu);
7398 free_vcpu:
7399         free_vpid(vmx);
7400         kmem_cache_free(kvm_vcpu_cache, vmx);
7401         return ERR_PTR(err);
7402 }
7403
7404 static void __init vmx_check_processor_compat(void *rtn)
7405 {
7406         struct vmcs_config vmcs_conf;
7407
7408         *(int *)rtn = 0;
7409         if (setup_vmcs_config(&vmcs_conf) < 0)
7410                 *(int *)rtn = -EIO;
7411         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7412                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7413                                 smp_processor_id());
7414                 *(int *)rtn = -EIO;
7415         }
7416 }
7417
7418 static int get_ept_level(void)
7419 {
7420         return VMX_EPT_DEFAULT_GAW + 1;
7421 }
7422
7423 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7424 {
7425         u64 ret;
7426
7427         /* For VT-d and EPT combination
7428          * 1. MMIO: always map as UC
7429          * 2. EPT with VT-d:
7430          *   a. VT-d without snooping control feature: can't guarantee the
7431          *      result, try to trust guest.
7432          *   b. VT-d with snooping control feature: snooping control feature of
7433          *      VT-d engine can guarantee the cache correctness. Just set it
7434          *      to WB to keep consistent with host. So the same as item 3.
7435          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7436          *    consistent with host MTRR
7437          */
7438         if (is_mmio)
7439                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7440         else if (vcpu->kvm->arch.iommu_domain &&
7441                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7442                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7443                       VMX_EPT_MT_EPTE_SHIFT;
7444         else
7445                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7446                         | VMX_EPT_IPAT_BIT;
7447
7448         return ret;
7449 }
7450
7451 static int vmx_get_lpage_level(void)
7452 {
7453         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7454                 return PT_DIRECTORY_LEVEL;
7455         else
7456                 /* For shadow and EPT supported 1GB page */
7457                 return PT_PDPE_LEVEL;
7458 }
7459
7460 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7461 {
7462         struct kvm_cpuid_entry2 *best;
7463         struct vcpu_vmx *vmx = to_vmx(vcpu);
7464         u32 exec_control;
7465
7466         vmx->rdtscp_enabled = false;
7467         if (vmx_rdtscp_supported()) {
7468                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7469                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7470                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7471                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7472                                 vmx->rdtscp_enabled = true;
7473                         else {
7474                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7475                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7476                                                 exec_control);
7477                         }
7478                 }
7479         }
7480
7481         /* Exposing INVPCID only when PCID is exposed */
7482         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7483         if (vmx_invpcid_supported() &&
7484             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7485             guest_cpuid_has_pcid(vcpu)) {
7486                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7487                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7488                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7489                              exec_control);
7490         } else {
7491                 if (cpu_has_secondary_exec_ctrls()) {
7492                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7493                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7494                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7495                                      exec_control);
7496                 }
7497                 if (best)
7498                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7499         }
7500 }
7501
7502 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7503 {
7504         if (func == 1 && nested)
7505                 entry->ecx |= bit(X86_FEATURE_VMX);
7506 }
7507
7508 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7509                 struct x86_exception *fault)
7510 {
7511         struct vmcs12 *vmcs12;
7512         nested_vmx_vmexit(vcpu);
7513         vmcs12 = get_vmcs12(vcpu);
7514
7515         if (fault->error_code & PFERR_RSVD_MASK)
7516                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7517         else
7518                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7519         vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7520         vmcs12->guest_physical_address = fault->address;
7521 }
7522
7523 /* Callbacks for nested_ept_init_mmu_context: */
7524
7525 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7526 {
7527         /* return the page table to be shadowed - in our case, EPT12 */
7528         return get_vmcs12(vcpu)->ept_pointer;
7529 }
7530
7531 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7532 {
7533         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7534                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7535
7536         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7537         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7538         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7539
7540         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7541 }
7542
7543 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7544 {
7545         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7546 }
7547
7548 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7549                 struct x86_exception *fault)
7550 {
7551         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7552
7553         WARN_ON(!is_guest_mode(vcpu));
7554
7555         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7556         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7557                 nested_vmx_vmexit(vcpu);
7558         else
7559                 kvm_inject_page_fault(vcpu, fault);
7560 }
7561
7562 /*
7563  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7564  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7565  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7566  * guest in a way that will both be appropriate to L1's requests, and our
7567  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7568  * function also has additional necessary side-effects, like setting various
7569  * vcpu->arch fields.
7570  */
7571 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7572 {
7573         struct vcpu_vmx *vmx = to_vmx(vcpu);
7574         u32 exec_control;
7575         u32 exit_control;
7576
7577         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7578         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7579         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7580         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7581         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7582         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7583         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7584         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7585         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7586         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7587         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7588         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7589         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7590         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7591         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7592         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7593         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7594         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7595         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7596         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7597         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7598         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7599         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7600         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7601         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7602         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7603         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7604         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7605         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7606         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7607         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7608         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7609         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7610         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7611         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7612         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7613
7614         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7615         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7616                 vmcs12->vm_entry_intr_info_field);
7617         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7618                 vmcs12->vm_entry_exception_error_code);
7619         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7620                 vmcs12->vm_entry_instruction_len);
7621         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7622                 vmcs12->guest_interruptibility_info);
7623         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7624         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7625         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7626         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7627                 vmcs12->guest_pending_dbg_exceptions);
7628         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7629         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7630
7631         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7632
7633         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7634                 (vmcs_config.pin_based_exec_ctrl |
7635                  vmcs12->pin_based_vm_exec_control));
7636
7637         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7638                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7639                              vmcs12->vmx_preemption_timer_value);
7640
7641         /*
7642          * Whether page-faults are trapped is determined by a combination of
7643          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7644          * If enable_ept, L0 doesn't care about page faults and we should
7645          * set all of these to L1's desires. However, if !enable_ept, L0 does
7646          * care about (at least some) page faults, and because it is not easy
7647          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7648          * to exit on each and every L2 page fault. This is done by setting
7649          * MASK=MATCH=0 and (see below) EB.PF=1.
7650          * Note that below we don't need special code to set EB.PF beyond the
7651          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7652          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7653          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7654          *
7655          * A problem with this approach (when !enable_ept) is that L1 may be
7656          * injected with more page faults than it asked for. This could have
7657          * caused problems, but in practice existing hypervisors don't care.
7658          * To fix this, we will need to emulate the PFEC checking (on the L1
7659          * page tables), using walk_addr(), when injecting PFs to L1.
7660          */
7661         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7662                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7663         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7664                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7665
7666         if (cpu_has_secondary_exec_ctrls()) {
7667                 u32 exec_control = vmx_secondary_exec_control(vmx);
7668                 if (!vmx->rdtscp_enabled)
7669                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7670                 /* Take the following fields only from vmcs12 */
7671                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7672                 if (nested_cpu_has(vmcs12,
7673                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7674                         exec_control |= vmcs12->secondary_vm_exec_control;
7675
7676                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7677                         /*
7678                          * Translate L1 physical address to host physical
7679                          * address for vmcs02. Keep the page pinned, so this
7680                          * physical address remains valid. We keep a reference
7681                          * to it so we can release it later.
7682                          */
7683                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7684                                 nested_release_page(vmx->nested.apic_access_page);
7685                         vmx->nested.apic_access_page =
7686                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7687                         /*
7688                          * If translation failed, no matter: This feature asks
7689                          * to exit when accessing the given address, and if it
7690                          * can never be accessed, this feature won't do
7691                          * anything anyway.
7692                          */
7693                         if (!vmx->nested.apic_access_page)
7694                                 exec_control &=
7695                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7696                         else
7697                                 vmcs_write64(APIC_ACCESS_ADDR,
7698                                   page_to_phys(vmx->nested.apic_access_page));
7699                 }
7700
7701                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7702         }
7703
7704
7705         /*
7706          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7707          * Some constant fields are set here by vmx_set_constant_host_state().
7708          * Other fields are different per CPU, and will be set later when
7709          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7710          */
7711         vmx_set_constant_host_state(vmx);
7712
7713         /*
7714          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7715          * entry, but only if the current (host) sp changed from the value
7716          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7717          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7718          * here we just force the write to happen on entry.
7719          */
7720         vmx->host_rsp = 0;
7721
7722         exec_control = vmx_exec_control(vmx); /* L0's desires */
7723         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7724         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7725         exec_control &= ~CPU_BASED_TPR_SHADOW;
7726         exec_control |= vmcs12->cpu_based_vm_exec_control;
7727         /*
7728          * Merging of IO and MSR bitmaps not currently supported.
7729          * Rather, exit every time.
7730          */
7731         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7732         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7733         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7734
7735         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7736
7737         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7738          * bitwise-or of what L1 wants to trap for L2, and what we want to
7739          * trap. Note that CR0.TS also needs updating - we do this later.
7740          */
7741         update_exception_bitmap(vcpu);
7742         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7743         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7744
7745         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7746          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7747          * bits are further modified by vmx_set_efer() below.
7748          */
7749         exit_control = vmcs_config.vmexit_ctrl;
7750         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7751                 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
7752         vmcs_write32(VM_EXIT_CONTROLS, exit_control);
7753
7754         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7755          * emulated by vmx_set_efer(), below.
7756          */
7757         vmcs_write32(VM_ENTRY_CONTROLS,
7758                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7759                         ~VM_ENTRY_IA32E_MODE) |
7760                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7761
7762         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7763                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7764                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7765         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7766                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7767
7768
7769         set_cr4_guest_host_mask(vmx);
7770
7771         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7772                 vmcs_write64(TSC_OFFSET,
7773                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7774         else
7775                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7776
7777         if (enable_vpid) {
7778                 /*
7779                  * Trivially support vpid by letting L2s share their parent
7780                  * L1's vpid. TODO: move to a more elaborate solution, giving
7781                  * each L2 its own vpid and exposing the vpid feature to L1.
7782                  */
7783                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7784                 vmx_flush_tlb(vcpu);
7785         }
7786
7787         if (nested_cpu_has_ept(vmcs12)) {
7788                 kvm_mmu_unload(vcpu);
7789                 nested_ept_init_mmu_context(vcpu);
7790         }
7791
7792         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7793                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7794         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7795                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7796         else
7797                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7798         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7799         vmx_set_efer(vcpu, vcpu->arch.efer);
7800
7801         /*
7802          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7803          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7804          * The CR0_READ_SHADOW is what L2 should have expected to read given
7805          * the specifications by L1; It's not enough to take
7806          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7807          * have more bits than L1 expected.
7808          */
7809         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7810         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7811
7812         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7813         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7814
7815         /* shadow page tables on either EPT or shadow page tables */
7816         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7817         kvm_mmu_reset_context(vcpu);
7818
7819         if (!enable_ept)
7820                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7821
7822         /*
7823          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7824          */
7825         if (enable_ept) {
7826                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7827                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7828                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7829                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7830                 __clear_bit(VCPU_EXREG_PDPTR,
7831                                 (unsigned long *)&vcpu->arch.regs_avail);
7832                 __clear_bit(VCPU_EXREG_PDPTR,
7833                                 (unsigned long *)&vcpu->arch.regs_dirty);
7834         }
7835
7836         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7837         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7838 }
7839
7840 /*
7841  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7842  * for running an L2 nested guest.
7843  */
7844 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7845 {
7846         struct vmcs12 *vmcs12;
7847         struct vcpu_vmx *vmx = to_vmx(vcpu);
7848         int cpu;
7849         struct loaded_vmcs *vmcs02;
7850         bool ia32e;
7851
7852         if (!nested_vmx_check_permission(vcpu) ||
7853             !nested_vmx_check_vmcs12(vcpu))
7854                 return 1;
7855
7856         skip_emulated_instruction(vcpu);
7857         vmcs12 = get_vmcs12(vcpu);
7858
7859         if (enable_shadow_vmcs)
7860                 copy_shadow_to_vmcs12(vmx);
7861
7862         /*
7863          * The nested entry process starts with enforcing various prerequisites
7864          * on vmcs12 as required by the Intel SDM, and act appropriately when
7865          * they fail: As the SDM explains, some conditions should cause the
7866          * instruction to fail, while others will cause the instruction to seem
7867          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7868          * To speed up the normal (success) code path, we should avoid checking
7869          * for misconfigurations which will anyway be caught by the processor
7870          * when using the merged vmcs02.
7871          */
7872         if (vmcs12->launch_state == launch) {
7873                 nested_vmx_failValid(vcpu,
7874                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7875                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7876                 return 1;
7877         }
7878
7879         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7880                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7881                 return 1;
7882         }
7883
7884         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7885                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7886                 /*TODO: Also verify bits beyond physical address width are 0*/
7887                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7888                 return 1;
7889         }
7890
7891         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7892                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7893                 /*TODO: Also verify bits beyond physical address width are 0*/
7894                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7895                 return 1;
7896         }
7897
7898         if (vmcs12->vm_entry_msr_load_count > 0 ||
7899             vmcs12->vm_exit_msr_load_count > 0 ||
7900             vmcs12->vm_exit_msr_store_count > 0) {
7901                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7902                                     __func__);
7903                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7904                 return 1;
7905         }
7906
7907         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7908               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7909             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7910               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7911             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7912               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7913             !vmx_control_verify(vmcs12->vm_exit_controls,
7914               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7915             !vmx_control_verify(vmcs12->vm_entry_controls,
7916               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7917         {
7918                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7919                 return 1;
7920         }
7921
7922         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7923             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7924                 nested_vmx_failValid(vcpu,
7925                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7926                 return 1;
7927         }
7928
7929         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7930             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7931                 nested_vmx_entry_failure(vcpu, vmcs12,
7932                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7933                 return 1;
7934         }
7935         if (vmcs12->vmcs_link_pointer != -1ull) {
7936                 nested_vmx_entry_failure(vcpu, vmcs12,
7937                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7938                 return 1;
7939         }
7940
7941         /*
7942          * If the load IA32_EFER VM-entry control is 1, the following checks
7943          * are performed on the field for the IA32_EFER MSR:
7944          * - Bits reserved in the IA32_EFER MSR must be 0.
7945          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7946          *   the IA-32e mode guest VM-exit control. It must also be identical
7947          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7948          *   CR0.PG) is 1.
7949          */
7950         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7951                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7952                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7953                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7954                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7955                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7956                         nested_vmx_entry_failure(vcpu, vmcs12,
7957                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7958                         return 1;
7959                 }
7960         }
7961
7962         /*
7963          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7964          * IA32_EFER MSR must be 0 in the field for that register. In addition,
7965          * the values of the LMA and LME bits in the field must each be that of
7966          * the host address-space size VM-exit control.
7967          */
7968         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7969                 ia32e = (vmcs12->vm_exit_controls &
7970                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7971                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7972                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7973                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7974                         nested_vmx_entry_failure(vcpu, vmcs12,
7975                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7976                         return 1;
7977                 }
7978         }
7979
7980         /*
7981          * We're finally done with prerequisite checking, and can start with
7982          * the nested entry.
7983          */
7984
7985         vmcs02 = nested_get_current_vmcs02(vmx);
7986         if (!vmcs02)
7987                 return -ENOMEM;
7988
7989         enter_guest_mode(vcpu);
7990
7991         vmx->nested.nested_run_pending = 1;
7992
7993         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7994
7995         cpu = get_cpu();
7996         vmx->loaded_vmcs = vmcs02;
7997         vmx_vcpu_put(vcpu);
7998         vmx_vcpu_load(vcpu, cpu);
7999         vcpu->cpu = cpu;
8000         put_cpu();
8001
8002         vmx_segment_cache_clear(vmx);
8003
8004         vmcs12->launch_state = 1;
8005
8006         prepare_vmcs02(vcpu, vmcs12);
8007
8008         /*
8009          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8010          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8011          * returned as far as L1 is concerned. It will only return (and set
8012          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8013          */
8014         return 1;
8015 }
8016
8017 /*
8018  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8019  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8020  * This function returns the new value we should put in vmcs12.guest_cr0.
8021  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8022  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8023  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8024  *     didn't trap the bit, because if L1 did, so would L0).
8025  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8026  *     been modified by L2, and L1 knows it. So just leave the old value of
8027  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8028  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8029  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8030  *     changed these bits, and therefore they need to be updated, but L0
8031  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8032  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8033  */
8034 static inline unsigned long
8035 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8036 {
8037         return
8038         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8039         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8040         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8041                         vcpu->arch.cr0_guest_owned_bits));
8042 }
8043
8044 static inline unsigned long
8045 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8046 {
8047         return
8048         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8049         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8050         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8051                         vcpu->arch.cr4_guest_owned_bits));
8052 }
8053
8054 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8055                                        struct vmcs12 *vmcs12)
8056 {
8057         u32 idt_vectoring;
8058         unsigned int nr;
8059
8060         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8061                 nr = vcpu->arch.exception.nr;
8062                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8063
8064                 if (kvm_exception_is_soft(nr)) {
8065                         vmcs12->vm_exit_instruction_len =
8066                                 vcpu->arch.event_exit_inst_len;
8067                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8068                 } else
8069                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8070
8071                 if (vcpu->arch.exception.has_error_code) {
8072                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8073                         vmcs12->idt_vectoring_error_code =
8074                                 vcpu->arch.exception.error_code;
8075                 }
8076
8077                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8078         } else if (vcpu->arch.nmi_pending) {
8079                 vmcs12->idt_vectoring_info_field =
8080                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8081         } else if (vcpu->arch.interrupt.pending) {
8082                 nr = vcpu->arch.interrupt.nr;
8083                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8084
8085                 if (vcpu->arch.interrupt.soft) {
8086                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8087                         vmcs12->vm_entry_instruction_len =
8088                                 vcpu->arch.event_exit_inst_len;
8089                 } else
8090                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8091
8092                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8093         }
8094 }
8095
8096 /*
8097  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8098  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8099  * and this function updates it to reflect the changes to the guest state while
8100  * L2 was running (and perhaps made some exits which were handled directly by L0
8101  * without going back to L1), and to reflect the exit reason.
8102  * Note that we do not have to copy here all VMCS fields, just those that
8103  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8104  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8105  * which already writes to vmcs12 directly.
8106  */
8107 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8108 {
8109         /* update guest state fields: */
8110         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8111         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8112
8113         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8114         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8115         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8116         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8117
8118         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8119         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8120         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8121         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8122         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8123         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8124         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8125         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8126         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8127         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8128         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8129         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8130         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8131         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8132         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8133         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8134         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8135         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8136         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8137         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8138         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8139         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8140         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8141         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8142         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8143         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8144         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8145         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8146         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8147         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8148         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8149         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8150         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8151         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8152         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8153         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8154
8155         vmcs12->guest_interruptibility_info =
8156                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8157         vmcs12->guest_pending_dbg_exceptions =
8158                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8159
8160         if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8161             (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8162                 vmcs12->vmx_preemption_timer_value =
8163                         vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8164
8165         /*
8166          * In some cases (usually, nested EPT), L2 is allowed to change its
8167          * own CR3 without exiting. If it has changed it, we must keep it.
8168          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8169          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8170          *
8171          * Additionally, restore L2's PDPTR to vmcs12.
8172          */
8173         if (enable_ept) {
8174                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8175                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8176                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8177                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8178                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8179         }
8180
8181         vmcs12->vm_entry_controls =
8182                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8183                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8184
8185         /* TODO: These cannot have changed unless we have MSR bitmaps and
8186          * the relevant bit asks not to trap the change */
8187         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8188         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8189                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8190         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8191                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8192         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8193         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8194         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8195
8196         /* update exit information fields: */
8197
8198         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
8199         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8200
8201         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8202         if ((vmcs12->vm_exit_intr_info &
8203              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8204             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8205                 vmcs12->vm_exit_intr_error_code =
8206                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8207         vmcs12->idt_vectoring_info_field = 0;
8208         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8209         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8210
8211         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8212                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8213                  * instead of reading the real value. */
8214                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8215
8216                 /*
8217                  * Transfer the event that L0 or L1 may wanted to inject into
8218                  * L2 to IDT_VECTORING_INFO_FIELD.
8219                  */
8220                 vmcs12_save_pending_event(vcpu, vmcs12);
8221         }
8222
8223         /*
8224          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8225          * preserved above and would only end up incorrectly in L1.
8226          */
8227         vcpu->arch.nmi_injected = false;
8228         kvm_clear_exception_queue(vcpu);
8229         kvm_clear_interrupt_queue(vcpu);
8230 }
8231
8232 /*
8233  * A part of what we need to when the nested L2 guest exits and we want to
8234  * run its L1 parent, is to reset L1's guest state to the host state specified
8235  * in vmcs12.
8236  * This function is to be called not only on normal nested exit, but also on
8237  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8238  * Failures During or After Loading Guest State").
8239  * This function should be called when the active VMCS is L1's (vmcs01).
8240  */
8241 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8242                                    struct vmcs12 *vmcs12)
8243 {
8244         struct kvm_segment seg;
8245
8246         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8247                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8248         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8249                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8250         else
8251                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8252         vmx_set_efer(vcpu, vcpu->arch.efer);
8253
8254         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8255         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8256         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8257         /*
8258          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8259          * actually changed, because it depends on the current state of
8260          * fpu_active (which may have changed).
8261          * Note that vmx_set_cr0 refers to efer set above.
8262          */
8263         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8264         /*
8265          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8266          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8267          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8268          */
8269         update_exception_bitmap(vcpu);
8270         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8271         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8272
8273         /*
8274          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8275          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8276          */
8277         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8278         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8279
8280         if (nested_cpu_has_ept(vmcs12))
8281                 nested_ept_uninit_mmu_context(vcpu);
8282
8283         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8284         kvm_mmu_reset_context(vcpu);
8285
8286         if (!enable_ept)
8287                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8288
8289         if (enable_vpid) {
8290                 /*
8291                  * Trivially support vpid by letting L2s share their parent
8292                  * L1's vpid. TODO: move to a more elaborate solution, giving
8293                  * each L2 its own vpid and exposing the vpid feature to L1.
8294                  */
8295                 vmx_flush_tlb(vcpu);
8296         }
8297
8298
8299         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8300         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8301         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8302         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8303         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8304
8305         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8306                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8307                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8308         }
8309         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8310                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8311                         vmcs12->host_ia32_perf_global_ctrl);
8312
8313         /* Set L1 segment info according to Intel SDM
8314             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8315         seg = (struct kvm_segment) {
8316                 .base = 0,
8317                 .limit = 0xFFFFFFFF,
8318                 .selector = vmcs12->host_cs_selector,
8319                 .type = 11,
8320                 .present = 1,
8321                 .s = 1,
8322                 .g = 1
8323         };
8324         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8325                 seg.l = 1;
8326         else
8327                 seg.db = 1;
8328         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8329         seg = (struct kvm_segment) {
8330                 .base = 0,
8331                 .limit = 0xFFFFFFFF,
8332                 .type = 3,
8333                 .present = 1,
8334                 .s = 1,
8335                 .db = 1,
8336                 .g = 1
8337         };
8338         seg.selector = vmcs12->host_ds_selector;
8339         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8340         seg.selector = vmcs12->host_es_selector;
8341         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8342         seg.selector = vmcs12->host_ss_selector;
8343         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8344         seg.selector = vmcs12->host_fs_selector;
8345         seg.base = vmcs12->host_fs_base;
8346         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8347         seg.selector = vmcs12->host_gs_selector;
8348         seg.base = vmcs12->host_gs_base;
8349         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8350         seg = (struct kvm_segment) {
8351                 .base = vmcs12->host_tr_base,
8352                 .limit = 0x67,
8353                 .selector = vmcs12->host_tr_selector,
8354                 .type = 11,
8355                 .present = 1
8356         };
8357         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8358
8359         kvm_set_dr(vcpu, 7, 0x400);
8360         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8361 }
8362
8363 /*
8364  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8365  * and modify vmcs12 to make it see what it would expect to see there if
8366  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8367  */
8368 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8369 {
8370         struct vcpu_vmx *vmx = to_vmx(vcpu);
8371         int cpu;
8372         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8373
8374         /* trying to cancel vmlaunch/vmresume is a bug */
8375         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8376
8377         leave_guest_mode(vcpu);
8378         prepare_vmcs12(vcpu, vmcs12);
8379
8380         cpu = get_cpu();
8381         vmx->loaded_vmcs = &vmx->vmcs01;
8382         vmx_vcpu_put(vcpu);
8383         vmx_vcpu_load(vcpu, cpu);
8384         vcpu->cpu = cpu;
8385         put_cpu();
8386
8387         vmx_segment_cache_clear(vmx);
8388
8389         /* if no vmcs02 cache requested, remove the one we used */
8390         if (VMCS02_POOL_SIZE == 0)
8391                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8392
8393         load_vmcs12_host_state(vcpu, vmcs12);
8394
8395         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8396         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8397
8398         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8399         vmx->host_rsp = 0;
8400
8401         /* Unpin physical memory we referred to in vmcs02 */
8402         if (vmx->nested.apic_access_page) {
8403                 nested_release_page(vmx->nested.apic_access_page);
8404                 vmx->nested.apic_access_page = 0;
8405         }
8406
8407         /*
8408          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8409          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8410          * success or failure flag accordingly.
8411          */
8412         if (unlikely(vmx->fail)) {
8413                 vmx->fail = 0;
8414                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8415         } else
8416                 nested_vmx_succeed(vcpu);
8417         if (enable_shadow_vmcs)
8418                 vmx->nested.sync_shadow_vmcs = true;
8419 }
8420
8421 /*
8422  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8423  * 23.7 "VM-entry failures during or after loading guest state" (this also
8424  * lists the acceptable exit-reason and exit-qualification parameters).
8425  * It should only be called before L2 actually succeeded to run, and when
8426  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8427  */
8428 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8429                         struct vmcs12 *vmcs12,
8430                         u32 reason, unsigned long qualification)
8431 {
8432         load_vmcs12_host_state(vcpu, vmcs12);
8433         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8434         vmcs12->exit_qualification = qualification;
8435         nested_vmx_succeed(vcpu);
8436         if (enable_shadow_vmcs)
8437                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8438 }
8439
8440 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8441                                struct x86_instruction_info *info,
8442                                enum x86_intercept_stage stage)
8443 {
8444         return X86EMUL_CONTINUE;
8445 }
8446
8447 static struct kvm_x86_ops vmx_x86_ops = {
8448         .cpu_has_kvm_support = cpu_has_kvm_support,
8449         .disabled_by_bios = vmx_disabled_by_bios,
8450         .hardware_setup = hardware_setup,
8451         .hardware_unsetup = hardware_unsetup,
8452         .check_processor_compatibility = vmx_check_processor_compat,
8453         .hardware_enable = hardware_enable,
8454         .hardware_disable = hardware_disable,
8455         .cpu_has_accelerated_tpr = report_flexpriority,
8456
8457         .vcpu_create = vmx_create_vcpu,
8458         .vcpu_free = vmx_free_vcpu,
8459         .vcpu_reset = vmx_vcpu_reset,
8460
8461         .prepare_guest_switch = vmx_save_host_state,
8462         .vcpu_load = vmx_vcpu_load,
8463         .vcpu_put = vmx_vcpu_put,
8464
8465         .update_db_bp_intercept = update_exception_bitmap,
8466         .get_msr = vmx_get_msr,
8467         .set_msr = vmx_set_msr,
8468         .get_segment_base = vmx_get_segment_base,
8469         .get_segment = vmx_get_segment,
8470         .set_segment = vmx_set_segment,
8471         .get_cpl = vmx_get_cpl,
8472         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8473         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8474         .decache_cr3 = vmx_decache_cr3,
8475         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8476         .set_cr0 = vmx_set_cr0,
8477         .set_cr3 = vmx_set_cr3,
8478         .set_cr4 = vmx_set_cr4,
8479         .set_efer = vmx_set_efer,
8480         .get_idt = vmx_get_idt,
8481         .set_idt = vmx_set_idt,
8482         .get_gdt = vmx_get_gdt,
8483         .set_gdt = vmx_set_gdt,
8484         .set_dr7 = vmx_set_dr7,
8485         .cache_reg = vmx_cache_reg,
8486         .get_rflags = vmx_get_rflags,
8487         .set_rflags = vmx_set_rflags,
8488         .fpu_activate = vmx_fpu_activate,
8489         .fpu_deactivate = vmx_fpu_deactivate,
8490
8491         .tlb_flush = vmx_flush_tlb,
8492
8493         .run = vmx_vcpu_run,
8494         .handle_exit = vmx_handle_exit,
8495         .skip_emulated_instruction = skip_emulated_instruction,
8496         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8497         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8498         .patch_hypercall = vmx_patch_hypercall,
8499         .set_irq = vmx_inject_irq,
8500         .set_nmi = vmx_inject_nmi,
8501         .queue_exception = vmx_queue_exception,
8502         .cancel_injection = vmx_cancel_injection,
8503         .interrupt_allowed = vmx_interrupt_allowed,
8504         .nmi_allowed = vmx_nmi_allowed,
8505         .get_nmi_mask = vmx_get_nmi_mask,
8506         .set_nmi_mask = vmx_set_nmi_mask,
8507         .enable_nmi_window = enable_nmi_window,
8508         .enable_irq_window = enable_irq_window,
8509         .update_cr8_intercept = update_cr8_intercept,
8510         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8511         .vm_has_apicv = vmx_vm_has_apicv,
8512         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8513         .hwapic_irr_update = vmx_hwapic_irr_update,
8514         .hwapic_isr_update = vmx_hwapic_isr_update,
8515         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8516         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8517
8518         .set_tss_addr = vmx_set_tss_addr,
8519         .get_tdp_level = get_ept_level,
8520         .get_mt_mask = vmx_get_mt_mask,
8521
8522         .get_exit_info = vmx_get_exit_info,
8523
8524         .get_lpage_level = vmx_get_lpage_level,
8525
8526         .cpuid_update = vmx_cpuid_update,
8527
8528         .rdtscp_supported = vmx_rdtscp_supported,
8529         .invpcid_supported = vmx_invpcid_supported,
8530
8531         .set_supported_cpuid = vmx_set_supported_cpuid,
8532
8533         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8534
8535         .set_tsc_khz = vmx_set_tsc_khz,
8536         .read_tsc_offset = vmx_read_tsc_offset,
8537         .write_tsc_offset = vmx_write_tsc_offset,
8538         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8539         .compute_tsc_offset = vmx_compute_tsc_offset,
8540         .read_l1_tsc = vmx_read_l1_tsc,
8541
8542         .set_tdp_cr3 = vmx_set_cr3,
8543
8544         .check_intercept = vmx_check_intercept,
8545         .handle_external_intr = vmx_handle_external_intr,
8546 };
8547
8548 static int __init vmx_init(void)
8549 {
8550         int r, i, msr;
8551
8552         rdmsrl_safe(MSR_EFER, &host_efer);
8553
8554         for (i = 0; i < NR_VMX_MSR; ++i)
8555                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8556
8557         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8558         if (!vmx_io_bitmap_a)
8559                 return -ENOMEM;
8560
8561         r = -ENOMEM;
8562
8563         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8564         if (!vmx_io_bitmap_b)
8565                 goto out;
8566
8567         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8568         if (!vmx_msr_bitmap_legacy)
8569                 goto out1;
8570
8571         vmx_msr_bitmap_legacy_x2apic =
8572                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8573         if (!vmx_msr_bitmap_legacy_x2apic)
8574                 goto out2;
8575
8576         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8577         if (!vmx_msr_bitmap_longmode)
8578                 goto out3;
8579
8580         vmx_msr_bitmap_longmode_x2apic =
8581                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8582         if (!vmx_msr_bitmap_longmode_x2apic)
8583                 goto out4;
8584         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8585         if (!vmx_vmread_bitmap)
8586                 goto out5;
8587
8588         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8589         if (!vmx_vmwrite_bitmap)
8590                 goto out6;
8591
8592         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8593         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8594         /* shadowed read/write fields */
8595         for (i = 0; i < max_shadow_read_write_fields; i++) {
8596                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8597                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8598         }
8599         /* shadowed read only fields */
8600         for (i = 0; i < max_shadow_read_only_fields; i++)
8601                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8602
8603         /*
8604          * Allow direct access to the PC debug port (it is often used for I/O
8605          * delays, but the vmexits simply slow things down).
8606          */
8607         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8608         clear_bit(0x80, vmx_io_bitmap_a);
8609
8610         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8611
8612         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8613         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8614
8615         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8616
8617         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8618                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8619         if (r)
8620                 goto out7;
8621
8622 #ifdef CONFIG_KEXEC
8623         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8624                            crash_vmclear_local_loaded_vmcss);
8625 #endif
8626
8627         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8628         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8629         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8630         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8631         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8632         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8633         memcpy(vmx_msr_bitmap_legacy_x2apic,
8634                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8635         memcpy(vmx_msr_bitmap_longmode_x2apic,
8636                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8637
8638         if (enable_apicv) {
8639                 for (msr = 0x800; msr <= 0x8ff; msr++)
8640                         vmx_disable_intercept_msr_read_x2apic(msr);
8641
8642                 /* According SDM, in x2apic mode, the whole id reg is used.
8643                  * But in KVM, it only use the highest eight bits. Need to
8644                  * intercept it */
8645                 vmx_enable_intercept_msr_read_x2apic(0x802);
8646                 /* TMCCT */
8647                 vmx_enable_intercept_msr_read_x2apic(0x839);
8648                 /* TPR */
8649                 vmx_disable_intercept_msr_write_x2apic(0x808);
8650                 /* EOI */
8651                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8652                 /* SELF-IPI */
8653                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8654         }
8655
8656         if (enable_ept) {
8657                 kvm_mmu_set_mask_ptes(0ull,
8658                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8659                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8660                         0ull, VMX_EPT_EXECUTABLE_MASK);
8661                 ept_set_mmio_spte_mask();
8662                 kvm_enable_tdp();
8663         } else
8664                 kvm_disable_tdp();
8665
8666         return 0;
8667
8668 out7:
8669         free_page((unsigned long)vmx_vmwrite_bitmap);
8670 out6:
8671         free_page((unsigned long)vmx_vmread_bitmap);
8672 out5:
8673         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8674 out4:
8675         free_page((unsigned long)vmx_msr_bitmap_longmode);
8676 out3:
8677         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8678 out2:
8679         free_page((unsigned long)vmx_msr_bitmap_legacy);
8680 out1:
8681         free_page((unsigned long)vmx_io_bitmap_b);
8682 out:
8683         free_page((unsigned long)vmx_io_bitmap_a);
8684         return r;
8685 }
8686
8687 static void __exit vmx_exit(void)
8688 {
8689         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8690         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8691         free_page((unsigned long)vmx_msr_bitmap_legacy);
8692         free_page((unsigned long)vmx_msr_bitmap_longmode);
8693         free_page((unsigned long)vmx_io_bitmap_b);
8694         free_page((unsigned long)vmx_io_bitmap_a);
8695         free_page((unsigned long)vmx_vmwrite_bitmap);
8696         free_page((unsigned long)vmx_vmread_bitmap);
8697
8698 #ifdef CONFIG_KEXEC
8699         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8700         synchronize_rcu();
8701 #endif
8702
8703         kvm_exit();
8704 }
8705
8706 module_init(vmx_init)
8707 module_exit(vmx_exit)