Pileus Git - ~andy/linux/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376 };
 377
 378 #define POSTED_INTR_ON  0
 379 /* Posted-Interrupt Descriptor */
 380 struct pi_desc {
 381         u32 pir[8];     /* Posted interrupt requested */
 382         u32 control;    /* bit 0 of control is outstanding notification bit */
 383         u32 rsvd[7];
 384 } __aligned(64);
 385
 386 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 387 {
 388         return test_and_set_bit(POSTED_INTR_ON,
 389                         (unsigned long *)&pi_desc->control);
 390 }
 391
 392 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 393 {
 394         return test_and_clear_bit(POSTED_INTR_ON,
 395                         (unsigned long *)&pi_desc->control);
 396 }
 397
 398 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 399 {
 400         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 401 }
 402
 403 struct vcpu_vmx {
 404         struct kvm_vcpu       vcpu;
 405         unsigned long         host_rsp;
 406         u8                    fail;
 407         u8                    cpl;
 408         bool                  nmi_known_unmasked;
 409         u32                   exit_intr_info;
 410         u32                   idt_vectoring_info;
 411         ulong                 rflags;
 412         struct shared_msr_entry *guest_msrs;
 413         int                   nmsrs;
 414         int                   save_nmsrs;
 415         unsigned long         host_idt_base;
 416 #ifdef CONFIG_X86_64
 417         u64                   msr_host_kernel_gs_base;
 418         u64                   msr_guest_kernel_gs_base;
 419 #endif
 420         /*
 421          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 422          * non-nested (L1) guest, it always points to vmcs01. For a nested
 423          * guest (L2), it points to a different VMCS.
 424          */
 425         struct loaded_vmcs    vmcs01;
 426         struct loaded_vmcs   *loaded_vmcs;
 427         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 428         struct msr_autoload {
 429                 unsigned nr;
 430                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 431                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 432         } msr_autoload;
 433         struct {
 434                 int           loaded;
 435                 u16           fs_sel, gs_sel, ldt_sel;
 436 #ifdef CONFIG_X86_64
 437                 u16           ds_sel, es_sel;
 438 #endif
 439                 int           gs_ldt_reload_needed;
 440                 int           fs_reload_needed;
 441         } host_state;
 442         struct {
 443                 int vm86_active;
 444                 ulong save_rflags;
 445                 struct kvm_segment segs[8];
 446         } rmode;
 447         struct {
 448                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 449                 struct kvm_save_segment {
 450                         u16 selector;
 451                         unsigned long base;
 452                         u32 limit;
 453                         u32 ar;
 454                 } seg[8];
 455         } segment_cache;
 456         int vpid;
 457         bool emulation_required;
 458
 459         /* Support for vnmi-less CPUs */
 460         int soft_vnmi_blocked;
 461         ktime_t entry_time;
 462         s64 vnmi_blocked_time;
 463         u32 exit_reason;
 464
 465         bool rdtscp_enabled;
 466
 467         /* Posted interrupt descriptor */
 468         struct pi_desc pi_desc;
 469
 470         /* Support for a guest hypervisor (nested VMX) */
 471         struct nested_vmx nested;
 472 };
 473
 474 enum segment_cache_field {
 475         SEG_FIELD_SEL = 0,
 476         SEG_FIELD_BASE = 1,
 477         SEG_FIELD_LIMIT = 2,
 478         SEG_FIELD_AR = 3,
 479
 480         SEG_FIELD_NR = 4
 481 };
 482
 483 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 484 {
 485         return container_of(vcpu, struct vcpu_vmx, vcpu);
 486 }
 487
 488 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 489 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 490 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 491                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 492
 493
 494 static const unsigned long shadow_read_only_fields[] = {
 495         /*
 496          * We do NOT shadow fields that are modified when L0
 497          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 498          * VMXON...) executed by L1.
 499          * For example, VM_INSTRUCTION_ERROR is read
 500          * by L1 if a vmx instruction fails (part of the error path).
 501          * Note the code assumes this logic. If for some reason
 502          * we start shadowing these fields then we need to
 503          * force a shadow sync when L0 emulates vmx instructions
 504          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 505          * by nested_vmx_failValid)
 506          */
 507         VM_EXIT_REASON,
 508         VM_EXIT_INTR_INFO,
 509         VM_EXIT_INSTRUCTION_LEN,
 510         IDT_VECTORING_INFO_FIELD,
 511         IDT_VECTORING_ERROR_CODE,
 512         VM_EXIT_INTR_ERROR_CODE,
 513         EXIT_QUALIFICATION,
 514         GUEST_LINEAR_ADDRESS,
 515         GUEST_PHYSICAL_ADDRESS
 516 };
 517 static const int max_shadow_read_only_fields =
 518         ARRAY_SIZE(shadow_read_only_fields);
 519
 520 static const unsigned long shadow_read_write_fields[] = {
 521         GUEST_RIP,
 522         GUEST_RSP,
 523         GUEST_CR0,
 524         GUEST_CR3,
 525         GUEST_CR4,
 526         GUEST_INTERRUPTIBILITY_INFO,
 527         GUEST_RFLAGS,
 528         GUEST_CS_SELECTOR,
 529         GUEST_CS_AR_BYTES,
 530         GUEST_CS_LIMIT,
 531         GUEST_CS_BASE,
 532         GUEST_ES_BASE,
 533         CR0_GUEST_HOST_MASK,
 534         CR0_READ_SHADOW,
 535         CR4_READ_SHADOW,
 536         TSC_OFFSET,
 537         EXCEPTION_BITMAP,
 538         CPU_BASED_VM_EXEC_CONTROL,
 539         VM_ENTRY_EXCEPTION_ERROR_CODE,
 540         VM_ENTRY_INTR_INFO_FIELD,
 541         VM_ENTRY_INSTRUCTION_LEN,
 542         VM_ENTRY_EXCEPTION_ERROR_CODE,
 543         HOST_FS_BASE,
 544         HOST_GS_BASE,
 545         HOST_FS_SELECTOR,
 546         HOST_GS_SELECTOR
 547 };
 548 static const int max_shadow_read_write_fields =
 549         ARRAY_SIZE(shadow_read_write_fields);
 550
 551 static const unsigned short vmcs_field_to_offset_table[] = {
 552         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 553         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 554         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 555         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 556         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 557         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 558         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 559         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 560         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 561         FIELD(HOST_ES_SELECTOR, host_es_selector),
 562         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 563         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 564         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 565         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 566         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 567         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 568         FIELD64(IO_BITMAP_A, io_bitmap_a),
 569         FIELD64(IO_BITMAP_B, io_bitmap_b),
 570         FIELD64(MSR_BITMAP, msr_bitmap),
 571         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 572         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 573         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 574         FIELD64(TSC_OFFSET, tsc_offset),
 575         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 576         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 577         FIELD64(EPT_POINTER, ept_pointer),
 578         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 579         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 580         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 581         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 582         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 583         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 584         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 585         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 586         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 587         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 588         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 589         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 590         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 591         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 592         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 593         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 594         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 595         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 596         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 597         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 598         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 599         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 600         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 601         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 602         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 603         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 604         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 605         FIELD(TPR_THRESHOLD, tpr_threshold),
 606         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 607         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 608         FIELD(VM_EXIT_REASON, vm_exit_reason),
 609         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 610         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 611         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 612         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 613         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 614         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 615         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 616         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 617         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 618         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 619         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 620         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 621         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 622         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 623         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 624         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 625         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 626         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 627         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 628         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 629         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 630         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 631         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 632         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 633         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 634         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 635         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 636         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 637         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 638         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 639         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 640         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 641         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 642         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 643         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 644         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 645         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 646         FIELD(EXIT_QUALIFICATION, exit_qualification),
 647         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 648         FIELD(GUEST_CR0, guest_cr0),
 649         FIELD(GUEST_CR3, guest_cr3),
 650         FIELD(GUEST_CR4, guest_cr4),
 651         FIELD(GUEST_ES_BASE, guest_es_base),
 652         FIELD(GUEST_CS_BASE, guest_cs_base),
 653         FIELD(GUEST_SS_BASE, guest_ss_base),
 654         FIELD(GUEST_DS_BASE, guest_ds_base),
 655         FIELD(GUEST_FS_BASE, guest_fs_base),
 656         FIELD(GUEST_GS_BASE, guest_gs_base),
 657         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 658         FIELD(GUEST_TR_BASE, guest_tr_base),
 659         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 660         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 661         FIELD(GUEST_DR7, guest_dr7),
 662         FIELD(GUEST_RSP, guest_rsp),
 663         FIELD(GUEST_RIP, guest_rip),
 664         FIELD(GUEST_RFLAGS, guest_rflags),
 665         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 666         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 667         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 668         FIELD(HOST_CR0, host_cr0),
 669         FIELD(HOST_CR3, host_cr3),
 670         FIELD(HOST_CR4, host_cr4),
 671         FIELD(HOST_FS_BASE, host_fs_base),
 672         FIELD(HOST_GS_BASE, host_gs_base),
 673         FIELD(HOST_TR_BASE, host_tr_base),
 674         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 675         FIELD(HOST_IDTR_BASE, host_idtr_base),
 676         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 677         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 678         FIELD(HOST_RSP, host_rsp),
 679         FIELD(HOST_RIP, host_rip),
 680 };
 681 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 682
 683 static inline short vmcs_field_to_offset(unsigned long field)
 684 {
 685         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 686                 return -1;
 687         return vmcs_field_to_offset_table[field];
 688 }
 689
 690 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 691 {
 692         return to_vmx(vcpu)->nested.current_vmcs12;
 693 }
 694
 695 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 696 {
 697         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 698         if (is_error_page(page))
 699                 return NULL;
 700
 701         return page;
 702 }
 703
 704 static void nested_release_page(struct page *page)
 705 {
 706         kvm_release_page_dirty(page);
 707 }
 708
 709 static void nested_release_page_clean(struct page *page)
 710 {
 711         kvm_release_page_clean(page);
 712 }
 713
 714 static u64 construct_eptp(unsigned long root_hpa);
 715 static void kvm_cpu_vmxon(u64 addr);
 716 static void kvm_cpu_vmxoff(void);
 717 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 718 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 719 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 720                             struct kvm_segment *var, int seg);
 721 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 722                             struct kvm_segment *var, int seg);
 723 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 724 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 725 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 726 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 727 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 728
 729 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 730 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 731 /*
 732  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 733  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 734  */
 735 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 736 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 737
 738 static unsigned long *vmx_io_bitmap_a;
 739 static unsigned long *vmx_io_bitmap_b;
 740 static unsigned long *vmx_msr_bitmap_legacy;
 741 static unsigned long *vmx_msr_bitmap_longmode;
 742 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 743 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 744 static unsigned long *vmx_vmread_bitmap;
 745 static unsigned long *vmx_vmwrite_bitmap;
 746
 747 static bool cpu_has_load_ia32_efer;
 748 static bool cpu_has_load_perf_global_ctrl;
 749
 750 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 751 static DEFINE_SPINLOCK(vmx_vpid_lock);
 752
 753 static struct vmcs_config {
 754         int size;
 755         int order;
 756         u32 revision_id;
 757         u32 pin_based_exec_ctrl;
 758         u32 cpu_based_exec_ctrl;
 759         u32 cpu_based_2nd_exec_ctrl;
 760         u32 vmexit_ctrl;
 761         u32 vmentry_ctrl;
 762 } vmcs_config;
 763
 764 static struct vmx_capability {
 765         u32 ept;
 766         u32 vpid;
 767 } vmx_capability;
 768
 769 #define VMX_SEGMENT_FIELD(seg)                                  \
 770         [VCPU_SREG_##seg] = {                                   \
 771                 .selector = GUEST_##seg##_SELECTOR,             \
 772                 .base = GUEST_##seg##_BASE,                     \
 773                 .limit = GUEST_##seg##_LIMIT,                   \
 774                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 775         }
 776
 777 static const struct kvm_vmx_segment_field {
 778         unsigned selector;
 779         unsigned base;
 780         unsigned limit;
 781         unsigned ar_bytes;
 782 } kvm_vmx_segment_fields[] = {
 783         VMX_SEGMENT_FIELD(CS),
 784         VMX_SEGMENT_FIELD(DS),
 785         VMX_SEGMENT_FIELD(ES),
 786         VMX_SEGMENT_FIELD(FS),
 787         VMX_SEGMENT_FIELD(GS),
 788         VMX_SEGMENT_FIELD(SS),
 789         VMX_SEGMENT_FIELD(TR),
 790         VMX_SEGMENT_FIELD(LDTR),
 791 };
 792
 793 static u64 host_efer;
 794
 795 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 796
 797 /*
 798  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 799  * away by decrementing the array size.
 800  */
 801 static const u32 vmx_msr_index[] = {
 802 #ifdef CONFIG_X86_64
 803         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 804 #endif
 805         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 806 };
 807 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 808
 809 static inline bool is_page_fault(u32 intr_info)
 810 {
 811         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 812                              INTR_INFO_VALID_MASK)) ==
 813                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 814 }
 815
 816 static inline bool is_no_device(u32 intr_info)
 817 {
 818         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 819                              INTR_INFO_VALID_MASK)) ==
 820                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 821 }
 822
 823 static inline bool is_invalid_opcode(u32 intr_info)
 824 {
 825         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 826                              INTR_INFO_VALID_MASK)) ==
 827                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 828 }
 829
 830 static inline bool is_external_interrupt(u32 intr_info)
 831 {
 832         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 833                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 834 }
 835
 836 static inline bool is_machine_check(u32 intr_info)
 837 {
 838         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 839                              INTR_INFO_VALID_MASK)) ==
 840                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 841 }
 842
 843 static inline bool cpu_has_vmx_msr_bitmap(void)
 844 {
 845         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 846 }
 847
 848 static inline bool cpu_has_vmx_tpr_shadow(void)
 849 {
 850         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 851 }
 852
 853 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 854 {
 855         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 856 }
 857
 858 static inline bool cpu_has_secondary_exec_ctrls(void)
 859 {
 860         return vmcs_config.cpu_based_exec_ctrl &
 861                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 862 }
 863
 864 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 865 {
 866         return vmcs_config.cpu_based_2nd_exec_ctrl &
 867                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 868 }
 869
 870 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 871 {
 872         return vmcs_config.cpu_based_2nd_exec_ctrl &
 873                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 874 }
 875
 876 static inline bool cpu_has_vmx_apic_register_virt(void)
 877 {
 878         return vmcs_config.cpu_based_2nd_exec_ctrl &
 879                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 880 }
 881
 882 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 883 {
 884         return vmcs_config.cpu_based_2nd_exec_ctrl &
 885                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 886 }
 887
 888 static inline bool cpu_has_vmx_posted_intr(void)
 889 {
 890         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 891 }
 892
 893 static inline bool cpu_has_vmx_apicv(void)
 894 {
 895         return cpu_has_vmx_apic_register_virt() &&
 896                 cpu_has_vmx_virtual_intr_delivery() &&
 897                 cpu_has_vmx_posted_intr();
 898 }
 899
 900 static inline bool cpu_has_vmx_flexpriority(void)
 901 {
 902         return cpu_has_vmx_tpr_shadow() &&
 903                 cpu_has_vmx_virtualize_apic_accesses();
 904 }
 905
 906 static inline bool cpu_has_vmx_ept_execute_only(void)
 907 {
 908         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 909 }
 910
 911 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 912 {
 913         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 914 }
 915
 916 static inline bool cpu_has_vmx_eptp_writeback(void)
 917 {
 918         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 919 }
 920
 921 static inline bool cpu_has_vmx_ept_2m_page(void)
 922 {
 923         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 924 }
 925
 926 static inline bool cpu_has_vmx_ept_1g_page(void)
 927 {
 928         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 929 }
 930
 931 static inline bool cpu_has_vmx_ept_4levels(void)
 932 {
 933         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 934 }
 935
 936 static inline bool cpu_has_vmx_ept_ad_bits(void)
 937 {
 938         return vmx_capability.ept & VMX_EPT_AD_BIT;
 939 }
 940
 941 static inline bool cpu_has_vmx_invept_context(void)
 942 {
 943         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 944 }
 945
 946 static inline bool cpu_has_vmx_invept_global(void)
 947 {
 948         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 949 }
 950
 951 static inline bool cpu_has_vmx_invvpid_single(void)
 952 {
 953         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 954 }
 955
 956 static inline bool cpu_has_vmx_invvpid_global(void)
 957 {
 958         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 959 }
 960
 961 static inline bool cpu_has_vmx_ept(void)
 962 {
 963         return vmcs_config.cpu_based_2nd_exec_ctrl &
 964                 SECONDARY_EXEC_ENABLE_EPT;
 965 }
 966
 967 static inline bool cpu_has_vmx_unrestricted_guest(void)
 968 {
 969         return vmcs_config.cpu_based_2nd_exec_ctrl &
 970                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 971 }
 972
 973 static inline bool cpu_has_vmx_ple(void)
 974 {
 975         return vmcs_config.cpu_based_2nd_exec_ctrl &
 976                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 977 }
 978
 979 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 980 {
 981         return flexpriority_enabled && irqchip_in_kernel(kvm);
 982 }
 983
 984 static inline bool cpu_has_vmx_vpid(void)
 985 {
 986         return vmcs_config.cpu_based_2nd_exec_ctrl &
 987                 SECONDARY_EXEC_ENABLE_VPID;
 988 }
 989
 990 static inline bool cpu_has_vmx_rdtscp(void)
 991 {
 992         return vmcs_config.cpu_based_2nd_exec_ctrl &
 993                 SECONDARY_EXEC_RDTSCP;
 994 }
 995
 996 static inline bool cpu_has_vmx_invpcid(void)
 997 {
 998         return vmcs_config.cpu_based_2nd_exec_ctrl &
 999                 SECONDARY_EXEC_ENABLE_INVPCID;
1000 }
1001
1002 static inline bool cpu_has_virtual_nmis(void)
1003 {
1004         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1005 }
1006
1007 static inline bool cpu_has_vmx_wbinvd_exit(void)
1008 {
1009         return vmcs_config.cpu_based_2nd_exec_ctrl &
1010                 SECONDARY_EXEC_WBINVD_EXITING;
1011 }
1012
1013 static inline bool cpu_has_vmx_shadow_vmcs(void)
1014 {
1015         u64 vmx_msr;
1016         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1017         /* check if the cpu supports writing r/o exit information fields */
1018         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1019                 return false;
1020
1021         return vmcs_config.cpu_based_2nd_exec_ctrl &
1022                 SECONDARY_EXEC_SHADOW_VMCS;
1023 }
1024
1025 static inline bool report_flexpriority(void)
1026 {
1027         return flexpriority_enabled;
1028 }
1029
1030 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1031 {
1032         return vmcs12->cpu_based_vm_exec_control & bit;
1033 }
1034
1035 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1036 {
1037         return (vmcs12->cpu_based_vm_exec_control &
1038                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1039                 (vmcs12->secondary_vm_exec_control & bit);
1040 }
1041
1042 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1043         struct kvm_vcpu *vcpu)
1044 {
1045         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046 }
1047
1048 static inline bool is_exception(u32 intr_info)
1049 {
1050         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1051                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1052 }
1053
1054 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1055 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1056                         struct vmcs12 *vmcs12,
1057                         u32 reason, unsigned long qualification);
1058
1059 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1060 {
1061         int i;
1062
1063         for (i = 0; i < vmx->nmsrs; ++i)
1064                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1065                         return i;
1066         return -1;
1067 }
1068
1069 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1070 {
1071     struct {
1072         u64 vpid : 16;
1073         u64 rsvd : 48;
1074         u64 gva;
1075     } operand = { vpid, 0, gva };
1076
1077     asm volatile (__ex(ASM_VMX_INVVPID)
1078                   /* CF==1 or ZF==1 --> rc = -1 */
1079                   "; ja 1f ; ud2 ; 1:"
1080                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1081 }
1082
1083 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1084 {
1085         struct {
1086                 u64 eptp, gpa;
1087         } operand = {eptp, gpa};
1088
1089         asm volatile (__ex(ASM_VMX_INVEPT)
1090                         /* CF==1 or ZF==1 --> rc = -1 */
1091                         "; ja 1f ; ud2 ; 1:\n"
1092                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1093 }
1094
1095 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1096 {
1097         int i;
1098
1099         i = __find_msr_index(vmx, msr);
1100         if (i >= 0)
1101                 return &vmx->guest_msrs[i];
1102         return NULL;
1103 }
1104
1105 static void vmcs_clear(struct vmcs *vmcs)
1106 {
1107         u64 phys_addr = __pa(vmcs);
1108         u8 error;
1109
1110         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1111                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1112                       : "cc", "memory");
1113         if (error)
1114                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1115                        vmcs, phys_addr);
1116 }
1117
1118 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1119 {
1120         vmcs_clear(loaded_vmcs->vmcs);
1121         loaded_vmcs->cpu = -1;
1122         loaded_vmcs->launched = 0;
1123 }
1124
1125 static void vmcs_load(struct vmcs *vmcs)
1126 {
1127         u64 phys_addr = __pa(vmcs);
1128         u8 error;
1129
1130         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1131                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1132                         : "cc", "memory");
1133         if (error)
1134                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1135                        vmcs, phys_addr);
1136 }
1137
1138 #ifdef CONFIG_KEXEC
1139 /*
1140  * This bitmap is used to indicate whether the vmclear
1141  * operation is enabled on all cpus. All disabled by
1142  * default.
1143  */
1144 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1145
1146 static inline void crash_enable_local_vmclear(int cpu)
1147 {
1148         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1149 }
1150
1151 static inline void crash_disable_local_vmclear(int cpu)
1152 {
1153         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154 }
1155
1156 static inline int crash_local_vmclear_enabled(int cpu)
1157 {
1158         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159 }
1160
1161 static void crash_vmclear_local_loaded_vmcss(void)
1162 {
1163         int cpu = raw_smp_processor_id();
1164         struct loaded_vmcs *v;
1165
1166         if (!crash_local_vmclear_enabled(cpu))
1167                 return;
1168
1169         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1170                             loaded_vmcss_on_cpu_link)
1171                 vmcs_clear(v->vmcs);
1172 }
1173 #else
1174 static inline void crash_enable_local_vmclear(int cpu) { }
1175 static inline void crash_disable_local_vmclear(int cpu) { }
1176 #endif /* CONFIG_KEXEC */
1177
1178 static void __loaded_vmcs_clear(void *arg)
1179 {
1180         struct loaded_vmcs *loaded_vmcs = arg;
1181         int cpu = raw_smp_processor_id();
1182
1183         if (loaded_vmcs->cpu != cpu)
1184                 return; /* vcpu migration can race with cpu offline */
1185         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1186                 per_cpu(current_vmcs, cpu) = NULL;
1187         crash_disable_local_vmclear(cpu);
1188         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1189
1190         /*
1191          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1192          * is before setting loaded_vmcs->vcpu to -1 which is done in
1193          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1194          * then adds the vmcs into percpu list before it is deleted.
1195          */
1196         smp_wmb();
1197
1198         loaded_vmcs_init(loaded_vmcs);
1199         crash_enable_local_vmclear(cpu);
1200 }
1201
1202 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1203 {
1204         int cpu = loaded_vmcs->cpu;
1205
1206         if (cpu != -1)
1207                 smp_call_function_single(cpu,
1208                          __loaded_vmcs_clear, loaded_vmcs, 1);
1209 }
1210
1211 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1212 {
1213         if (vmx->vpid == 0)
1214                 return;
1215
1216         if (cpu_has_vmx_invvpid_single())
1217                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1218 }
1219
1220 static inline void vpid_sync_vcpu_global(void)
1221 {
1222         if (cpu_has_vmx_invvpid_global())
1223                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1224 }
1225
1226 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1227 {
1228         if (cpu_has_vmx_invvpid_single())
1229                 vpid_sync_vcpu_single(vmx);
1230         else
1231                 vpid_sync_vcpu_global();
1232 }
1233
1234 static inline void ept_sync_global(void)
1235 {
1236         if (cpu_has_vmx_invept_global())
1237                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1238 }
1239
1240 static inline void ept_sync_context(u64 eptp)
1241 {
1242         if (enable_ept) {
1243                 if (cpu_has_vmx_invept_context())
1244                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1245                 else
1246                         ept_sync_global();
1247         }
1248 }
1249
1250 static __always_inline unsigned long vmcs_readl(unsigned long field)
1251 {
1252         unsigned long value;
1253
1254         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1255                       : "=a"(value) : "d"(field) : "cc");
1256         return value;
1257 }
1258
1259 static __always_inline u16 vmcs_read16(unsigned long field)
1260 {
1261         return vmcs_readl(field);
1262 }
1263
1264 static __always_inline u32 vmcs_read32(unsigned long field)
1265 {
1266         return vmcs_readl(field);
1267 }
1268
1269 static __always_inline u64 vmcs_read64(unsigned long field)
1270 {
1271 #ifdef CONFIG_X86_64
1272         return vmcs_readl(field);
1273 #else
1274         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1275 #endif
1276 }
1277
1278 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1279 {
1280         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1281                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1282         dump_stack();
1283 }
1284
1285 static void vmcs_writel(unsigned long field, unsigned long value)
1286 {
1287         u8 error;
1288
1289         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1290                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1291         if (unlikely(error))
1292                 vmwrite_error(field, value);
1293 }
1294
1295 static void vmcs_write16(unsigned long field, u16 value)
1296 {
1297         vmcs_writel(field, value);
1298 }
1299
1300 static void vmcs_write32(unsigned long field, u32 value)
1301 {
1302         vmcs_writel(field, value);
1303 }
1304
1305 static void vmcs_write64(unsigned long field, u64 value)
1306 {
1307         vmcs_writel(field, value);
1308 #ifndef CONFIG_X86_64
1309         asm volatile ("");
1310         vmcs_writel(field+1, value >> 32);
1311 #endif
1312 }
1313
1314 static void vmcs_clear_bits(unsigned long field, u32 mask)
1315 {
1316         vmcs_writel(field, vmcs_readl(field) & ~mask);
1317 }
1318
1319 static void vmcs_set_bits(unsigned long field, u32 mask)
1320 {
1321         vmcs_writel(field, vmcs_readl(field) | mask);
1322 }
1323
1324 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1325 {
1326         vmx->segment_cache.bitmask = 0;
1327 }
1328
1329 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1330                                        unsigned field)
1331 {
1332         bool ret;
1333         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1334
1335         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1336                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1337                 vmx->segment_cache.bitmask = 0;
1338         }
1339         ret = vmx->segment_cache.bitmask & mask;
1340         vmx->segment_cache.bitmask |= mask;
1341         return ret;
1342 }
1343
1344 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1345 {
1346         u16 *p = &vmx->segment_cache.seg[seg].selector;
1347
1348         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1349                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1350         return *p;
1351 }
1352
1353 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1354 {
1355         ulong *p = &vmx->segment_cache.seg[seg].base;
1356
1357         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1358                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1359         return *p;
1360 }
1361
1362 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1363 {
1364         u32 *p = &vmx->segment_cache.seg[seg].limit;
1365
1366         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1367                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1368         return *p;
1369 }
1370
1371 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1372 {
1373         u32 *p = &vmx->segment_cache.seg[seg].ar;
1374
1375         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1376                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1377         return *p;
1378 }
1379
1380 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1381 {
1382         u32 eb;
1383
1384         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1385              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1386         if ((vcpu->guest_debug &
1387              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1388             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1389                 eb |= 1u << BP_VECTOR;
1390         if (to_vmx(vcpu)->rmode.vm86_active)
1391                 eb = ~0;
1392         if (enable_ept)
1393                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1394         if (vcpu->fpu_active)
1395                 eb &= ~(1u << NM_VECTOR);
1396
1397         /* When we are running a nested L2 guest and L1 specified for it a
1398          * certain exception bitmap, we must trap the same exceptions and pass
1399          * them to L1. When running L2, we will only handle the exceptions
1400          * specified above if L1 did not want them.
1401          */
1402         if (is_guest_mode(vcpu))
1403                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1404
1405         vmcs_write32(EXCEPTION_BITMAP, eb);
1406 }
1407
1408 static void clear_atomic_switch_msr_special(unsigned long entry,
1409                 unsigned long exit)
1410 {
1411         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1412         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1413 }
1414
1415 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1416 {
1417         unsigned i;
1418         struct msr_autoload *m = &vmx->msr_autoload;
1419
1420         switch (msr) {
1421         case MSR_EFER:
1422                 if (cpu_has_load_ia32_efer) {
1423                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1424                                         VM_EXIT_LOAD_IA32_EFER);
1425                         return;
1426                 }
1427                 break;
1428         case MSR_CORE_PERF_GLOBAL_CTRL:
1429                 if (cpu_has_load_perf_global_ctrl) {
1430                         clear_atomic_switch_msr_special(
1431                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1432                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1433                         return;
1434                 }
1435                 break;
1436         }
1437
1438         for (i = 0; i < m->nr; ++i)
1439                 if (m->guest[i].index == msr)
1440                         break;
1441
1442         if (i == m->nr)
1443                 return;
1444         --m->nr;
1445         m->guest[i] = m->guest[m->nr];
1446         m->host[i] = m->host[m->nr];
1447         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1448         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1449 }
1450
1451 static void add_atomic_switch_msr_special(unsigned long entry,
1452                 unsigned long exit, unsigned long guest_val_vmcs,
1453                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1454 {
1455         vmcs_write64(guest_val_vmcs, guest_val);
1456         vmcs_write64(host_val_vmcs, host_val);
1457         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1458         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1459 }
1460
1461 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1462                                   u64 guest_val, u64 host_val)
1463 {
1464         unsigned i;
1465         struct msr_autoload *m = &vmx->msr_autoload;
1466
1467         switch (msr) {
1468         case MSR_EFER:
1469                 if (cpu_has_load_ia32_efer) {
1470                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1471                                         VM_EXIT_LOAD_IA32_EFER,
1472                                         GUEST_IA32_EFER,
1473                                         HOST_IA32_EFER,
1474                                         guest_val, host_val);
1475                         return;
1476                 }
1477                 break;
1478         case MSR_CORE_PERF_GLOBAL_CTRL:
1479                 if (cpu_has_load_perf_global_ctrl) {
1480                         add_atomic_switch_msr_special(
1481                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1482                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1483                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1484                                         HOST_IA32_PERF_GLOBAL_CTRL,
1485                                         guest_val, host_val);
1486                         return;
1487                 }
1488                 break;
1489         }
1490
1491         for (i = 0; i < m->nr; ++i)
1492                 if (m->guest[i].index == msr)
1493                         break;
1494
1495         if (i == NR_AUTOLOAD_MSRS) {
1496                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1497                                 "Can't add msr %x\n", msr);
1498                 return;
1499         } else if (i == m->nr) {
1500                 ++m->nr;
1501                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1502                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1503         }
1504
1505         m->guest[i].index = msr;
1506         m->guest[i].value = guest_val;
1507         m->host[i].index = msr;
1508         m->host[i].value = host_val;
1509 }
1510
1511 static void reload_tss(void)
1512 {
1513         /*
1514          * VT restores TR but not its size.  Useless.
1515          */
1516         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1517         struct desc_struct *descs;
1518
1519         descs = (void *)gdt->address;
1520         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1521         load_TR_desc();
1522 }
1523
1524 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1525 {
1526         u64 guest_efer;
1527         u64 ignore_bits;
1528
1529         guest_efer = vmx->vcpu.arch.efer;
1530
1531         /*
1532          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1533          * outside long mode
1534          */
1535         ignore_bits = EFER_NX | EFER_SCE;
1536 #ifdef CONFIG_X86_64
1537         ignore_bits |= EFER_LMA | EFER_LME;
1538         /* SCE is meaningful only in long mode on Intel */
1539         if (guest_efer & EFER_LMA)
1540                 ignore_bits &= ~(u64)EFER_SCE;
1541 #endif
1542         guest_efer &= ~ignore_bits;
1543         guest_efer |= host_efer & ignore_bits;
1544         vmx->guest_msrs[efer_offset].data = guest_efer;
1545         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1546
1547         clear_atomic_switch_msr(vmx, MSR_EFER);
1548         /* On ept, can't emulate nx, and must switch nx atomically */
1549         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1550                 guest_efer = vmx->vcpu.arch.efer;
1551                 if (!(guest_efer & EFER_LMA))
1552                         guest_efer &= ~EFER_LME;
1553                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1554                 return false;
1555         }
1556
1557         return true;
1558 }
1559
1560 static unsigned long segment_base(u16 selector)
1561 {
1562         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1563         struct desc_struct *d;
1564         unsigned long table_base;
1565         unsigned long v;
1566
1567         if (!(selector & ~3))
1568                 return 0;
1569
1570         table_base = gdt->address;
1571
1572         if (selector & 4) {           /* from ldt */
1573                 u16 ldt_selector = kvm_read_ldt();
1574
1575                 if (!(ldt_selector & ~3))
1576                         return 0;
1577
1578                 table_base = segment_base(ldt_selector);
1579         }
1580         d = (struct desc_struct *)(table_base + (selector & ~7));
1581         v = get_desc_base(d);
1582 #ifdef CONFIG_X86_64
1583        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1584                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1585 #endif
1586         return v;
1587 }
1588
1589 static inline unsigned long kvm_read_tr_base(void)
1590 {
1591         u16 tr;
1592         asm("str %0" : "=g"(tr));
1593         return segment_base(tr);
1594 }
1595
1596 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1597 {
1598         struct vcpu_vmx *vmx = to_vmx(vcpu);
1599         int i;
1600
1601         if (vmx->host_state.loaded)
1602                 return;
1603
1604         vmx->host_state.loaded = 1;
1605         /*
1606          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1607          * allow segment selectors with cpl > 0 or ti == 1.
1608          */
1609         vmx->host_state.ldt_sel = kvm_read_ldt();
1610         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1611         savesegment(fs, vmx->host_state.fs_sel);
1612         if (!(vmx->host_state.fs_sel & 7)) {
1613                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1614                 vmx->host_state.fs_reload_needed = 0;
1615         } else {
1616                 vmcs_write16(HOST_FS_SELECTOR, 0);
1617                 vmx->host_state.fs_reload_needed = 1;
1618         }
1619         savesegment(gs, vmx->host_state.gs_sel);
1620         if (!(vmx->host_state.gs_sel & 7))
1621                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1622         else {
1623                 vmcs_write16(HOST_GS_SELECTOR, 0);
1624                 vmx->host_state.gs_ldt_reload_needed = 1;
1625         }
1626
1627 #ifdef CONFIG_X86_64
1628         savesegment(ds, vmx->host_state.ds_sel);
1629         savesegment(es, vmx->host_state.es_sel);
1630 #endif
1631
1632 #ifdef CONFIG_X86_64
1633         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1634         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1635 #else
1636         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1637         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1638 #endif
1639
1640 #ifdef CONFIG_X86_64
1641         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1642         if (is_long_mode(&vmx->vcpu))
1643                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1644 #endif
1645         for (i = 0; i < vmx->save_nmsrs; ++i)
1646                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1647                                    vmx->guest_msrs[i].data,
1648                                    vmx->guest_msrs[i].mask);
1649 }
1650
1651 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1652 {
1653         if (!vmx->host_state.loaded)
1654                 return;
1655
1656         ++vmx->vcpu.stat.host_state_reload;
1657         vmx->host_state.loaded = 0;
1658 #ifdef CONFIG_X86_64
1659         if (is_long_mode(&vmx->vcpu))
1660                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1661 #endif
1662         if (vmx->host_state.gs_ldt_reload_needed) {
1663                 kvm_load_ldt(vmx->host_state.ldt_sel);
1664 #ifdef CONFIG_X86_64
1665                 load_gs_index(vmx->host_state.gs_sel);
1666 #else
1667                 loadsegment(gs, vmx->host_state.gs_sel);
1668 #endif
1669         }
1670         if (vmx->host_state.fs_reload_needed)
1671                 loadsegment(fs, vmx->host_state.fs_sel);
1672 #ifdef CONFIG_X86_64
1673         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1674                 loadsegment(ds, vmx->host_state.ds_sel);
1675                 loadsegment(es, vmx->host_state.es_sel);
1676         }
1677 #endif
1678         reload_tss();
1679 #ifdef CONFIG_X86_64
1680         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1681 #endif
1682         /*
1683          * If the FPU is not active (through the host task or
1684          * the guest vcpu), then restore the cr0.TS bit.
1685          */
1686         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1687                 stts();
1688         load_gdt(&__get_cpu_var(host_gdt));
1689 }
1690
1691 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1692 {
1693         preempt_disable();
1694         __vmx_load_host_state(vmx);
1695         preempt_enable();
1696 }
1697
1698 /*
1699  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1700  * vcpu mutex is already taken.
1701  */
1702 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1703 {
1704         struct vcpu_vmx *vmx = to_vmx(vcpu);
1705         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1706
1707         if (!vmm_exclusive)
1708                 kvm_cpu_vmxon(phys_addr);
1709         else if (vmx->loaded_vmcs->cpu != cpu)
1710                 loaded_vmcs_clear(vmx->loaded_vmcs);
1711
1712         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1713                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1714                 vmcs_load(vmx->loaded_vmcs->vmcs);
1715         }
1716
1717         if (vmx->loaded_vmcs->cpu != cpu) {
1718                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1719                 unsigned long sysenter_esp;
1720
1721                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1722                 local_irq_disable();
1723                 crash_disable_local_vmclear(cpu);
1724
1725                 /*
1726                  * Read loaded_vmcs->cpu should be before fetching
1727                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1728                  * See the comments in __loaded_vmcs_clear().
1729                  */
1730                 smp_rmb();
1731
1732                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1733                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1734                 crash_enable_local_vmclear(cpu);
1735                 local_irq_enable();
1736
1737                 /*
1738                  * Linux uses per-cpu TSS and GDT, so set these when switching
1739                  * processors.
1740                  */
1741                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1742                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1743
1744                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1745                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1746                 vmx->loaded_vmcs->cpu = cpu;
1747         }
1748 }
1749
1750 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1751 {
1752         __vmx_load_host_state(to_vmx(vcpu));
1753         if (!vmm_exclusive) {
1754                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1755                 vcpu->cpu = -1;
1756                 kvm_cpu_vmxoff();
1757         }
1758 }
1759
1760 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1761 {
1762         ulong cr0;
1763
1764         if (vcpu->fpu_active)
1765                 return;
1766         vcpu->fpu_active = 1;
1767         cr0 = vmcs_readl(GUEST_CR0);
1768         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1769         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1770         vmcs_writel(GUEST_CR0, cr0);
1771         update_exception_bitmap(vcpu);
1772         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1773         if (is_guest_mode(vcpu))
1774                 vcpu->arch.cr0_guest_owned_bits &=
1775                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1776         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1777 }
1778
1779 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1780
1781 /*
1782  * Return the cr0 value that a nested guest would read. This is a combination
1783  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1784  * its hypervisor (cr0_read_shadow).
1785  */
1786 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1787 {
1788         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1789                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1790 }
1791 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1792 {
1793         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1794                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1795 }
1796
1797 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1798 {
1799         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1800          * set this *before* calling this function.
1801          */
1802         vmx_decache_cr0_guest_bits(vcpu);
1803         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1804         update_exception_bitmap(vcpu);
1805         vcpu->arch.cr0_guest_owned_bits = 0;
1806         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1807         if (is_guest_mode(vcpu)) {
1808                 /*
1809                  * L1's specified read shadow might not contain the TS bit,
1810                  * so now that we turned on shadowing of this bit, we need to
1811                  * set this bit of the shadow. Like in nested_vmx_run we need
1812                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1813                  * up-to-date here because we just decached cr0.TS (and we'll
1814                  * only update vmcs12->guest_cr0 on nested exit).
1815                  */
1816                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1817                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1818                         (vcpu->arch.cr0 & X86_CR0_TS);
1819                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1820         } else
1821                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1822 }
1823
1824 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1825 {
1826         unsigned long rflags, save_rflags;
1827
1828         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1829                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1830                 rflags = vmcs_readl(GUEST_RFLAGS);
1831                 if (to_vmx(vcpu)->rmode.vm86_active) {
1832                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1833                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1834                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1835                 }
1836                 to_vmx(vcpu)->rflags = rflags;
1837         }
1838         return to_vmx(vcpu)->rflags;
1839 }
1840
1841 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1842 {
1843         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1844         to_vmx(vcpu)->rflags = rflags;
1845         if (to_vmx(vcpu)->rmode.vm86_active) {
1846                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1847                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1848         }
1849         vmcs_writel(GUEST_RFLAGS, rflags);
1850 }
1851
1852 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1853 {
1854         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1855         int ret = 0;
1856
1857         if (interruptibility & GUEST_INTR_STATE_STI)
1858                 ret |= KVM_X86_SHADOW_INT_STI;
1859         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1860                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1861
1862         return ret & mask;
1863 }
1864
1865 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1866 {
1867         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1868         u32 interruptibility = interruptibility_old;
1869
1870         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1871
1872         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1873                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1874         else if (mask & KVM_X86_SHADOW_INT_STI)
1875                 interruptibility |= GUEST_INTR_STATE_STI;
1876
1877         if ((interruptibility != interruptibility_old))
1878                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1879 }
1880
1881 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1882 {
1883         unsigned long rip;
1884
1885         rip = kvm_rip_read(vcpu);
1886         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1887         kvm_rip_write(vcpu, rip);
1888
1889         /* skipping an emulated instruction also counts */
1890         vmx_set_interrupt_shadow(vcpu, 0);
1891 }
1892
1893 /*
1894  * KVM wants to inject page-faults which it got to the guest. This function
1895  * checks whether in a nested guest, we need to inject them to L1 or L2.
1896  * This function assumes it is called with the exit reason in vmcs02 being
1897  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1898  * is running).
1899  */
1900 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1901 {
1902         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1903
1904         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1905         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1906                 return 0;
1907
1908         nested_vmx_vmexit(vcpu);
1909         return 1;
1910 }
1911
1912 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1913                                 bool has_error_code, u32 error_code,
1914                                 bool reinject)
1915 {
1916         struct vcpu_vmx *vmx = to_vmx(vcpu);
1917         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1918
1919         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1920             !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1921                 return;
1922
1923         if (has_error_code) {
1924                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1925                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1926         }
1927
1928         if (vmx->rmode.vm86_active) {
1929                 int inc_eip = 0;
1930                 if (kvm_exception_is_soft(nr))
1931                         inc_eip = vcpu->arch.event_exit_inst_len;
1932                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1933                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1934                 return;
1935         }
1936
1937         if (kvm_exception_is_soft(nr)) {
1938                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1939                              vmx->vcpu.arch.event_exit_inst_len);
1940                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1941         } else
1942                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1943
1944         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1945 }
1946
1947 static bool vmx_rdtscp_supported(void)
1948 {
1949         return cpu_has_vmx_rdtscp();
1950 }
1951
1952 static bool vmx_invpcid_supported(void)
1953 {
1954         return cpu_has_vmx_invpcid() && enable_ept;
1955 }
1956
1957 /*
1958  * Swap MSR entry in host/guest MSR entry array.
1959  */
1960 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1961 {
1962         struct shared_msr_entry tmp;
1963
1964         tmp = vmx->guest_msrs[to];
1965         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1966         vmx->guest_msrs[from] = tmp;
1967 }
1968
1969 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1970 {
1971         unsigned long *msr_bitmap;
1972
1973         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1974                 if (is_long_mode(vcpu))
1975                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1976                 else
1977                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1978         } else {
1979                 if (is_long_mode(vcpu))
1980                         msr_bitmap = vmx_msr_bitmap_longmode;
1981                 else
1982                         msr_bitmap = vmx_msr_bitmap_legacy;
1983         }
1984
1985         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1986 }
1987
1988 /*
1989  * Set up the vmcs to automatically save and restore system
1990  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1991  * mode, as fiddling with msrs is very expensive.
1992  */
1993 static void setup_msrs(struct vcpu_vmx *vmx)
1994 {
1995         int save_nmsrs, index;
1996
1997         save_nmsrs = 0;
1998 #ifdef CONFIG_X86_64
1999         if (is_long_mode(&vmx->vcpu)) {
2000                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2001                 if (index >= 0)
2002                         move_msr_up(vmx, index, save_nmsrs++);
2003                 index = __find_msr_index(vmx, MSR_LSTAR);
2004                 if (index >= 0)
2005                         move_msr_up(vmx, index, save_nmsrs++);
2006                 index = __find_msr_index(vmx, MSR_CSTAR);
2007                 if (index >= 0)
2008                         move_msr_up(vmx, index, save_nmsrs++);
2009                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2010                 if (index >= 0 && vmx->rdtscp_enabled)
2011                         move_msr_up(vmx, index, save_nmsrs++);
2012                 /*
2013                  * MSR_STAR is only needed on long mode guests, and only
2014                  * if efer.sce is enabled.
2015                  */
2016                 index = __find_msr_index(vmx, MSR_STAR);
2017                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2018                         move_msr_up(vmx, index, save_nmsrs++);
2019         }
2020 #endif
2021         index = __find_msr_index(vmx, MSR_EFER);
2022         if (index >= 0 && update_transition_efer(vmx, index))
2023                 move_msr_up(vmx, index, save_nmsrs++);
2024
2025         vmx->save_nmsrs = save_nmsrs;
2026
2027         if (cpu_has_vmx_msr_bitmap())
2028                 vmx_set_msr_bitmap(&vmx->vcpu);
2029 }
2030
2031 /*
2032  * reads and returns guest's timestamp counter "register"
2033  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2034  */
2035 static u64 guest_read_tsc(void)
2036 {
2037         u64 host_tsc, tsc_offset;
2038
2039         rdtscll(host_tsc);
2040         tsc_offset = vmcs_read64(TSC_OFFSET);
2041         return host_tsc + tsc_offset;
2042 }
2043
2044 /*
2045  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2046  * counter, even if a nested guest (L2) is currently running.
2047  */
2048 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2049 {
2050         u64 tsc_offset;
2051
2052         tsc_offset = is_guest_mode(vcpu) ?
2053                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2054                 vmcs_read64(TSC_OFFSET);
2055         return host_tsc + tsc_offset;
2056 }
2057
2058 /*
2059  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2060  * software catchup for faster rates on slower CPUs.
2061  */
2062 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2063 {
2064         if (!scale)
2065                 return;
2066
2067         if (user_tsc_khz > tsc_khz) {
2068                 vcpu->arch.tsc_catchup = 1;
2069                 vcpu->arch.tsc_always_catchup = 1;
2070         } else
2071                 WARN(1, "user requested TSC rate below hardware speed\n");
2072 }
2073
2074 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2075 {
2076         return vmcs_read64(TSC_OFFSET);
2077 }
2078
2079 /*
2080  * writes 'offset' into guest's timestamp counter offset register
2081  */
2082 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2083 {
2084         if (is_guest_mode(vcpu)) {
2085                 /*
2086                  * We're here if L1 chose not to trap WRMSR to TSC. According
2087                  * to the spec, this should set L1's TSC; The offset that L1
2088                  * set for L2 remains unchanged, and still needs to be added
2089                  * to the newly set TSC to get L2's TSC.
2090                  */
2091                 struct vmcs12 *vmcs12;
2092                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2093                 /* recalculate vmcs02.TSC_OFFSET: */
2094                 vmcs12 = get_vmcs12(vcpu);
2095                 vmcs_write64(TSC_OFFSET, offset +
2096                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2097                          vmcs12->tsc_offset : 0));
2098         } else {
2099                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2100                                            vmcs_read64(TSC_OFFSET), offset);
2101                 vmcs_write64(TSC_OFFSET, offset);
2102         }
2103 }
2104
2105 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2106 {
2107         u64 offset = vmcs_read64(TSC_OFFSET);
2108
2109         vmcs_write64(TSC_OFFSET, offset + adjustment);
2110         if (is_guest_mode(vcpu)) {
2111                 /* Even when running L2, the adjustment needs to apply to L1 */
2112                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2113         } else
2114                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2115                                            offset + adjustment);
2116 }
2117
2118 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2119 {
2120         return target_tsc - native_read_tsc();
2121 }
2122
2123 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2124 {
2125         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2126         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2127 }
2128
2129 /*
2130  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2131  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2132  * all guests if the "nested" module option is off, and can also be disabled
2133  * for a single guest by disabling its VMX cpuid bit.
2134  */
2135 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2136 {
2137         return nested && guest_cpuid_has_vmx(vcpu);
2138 }
2139
2140 /*
2141  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2142  * returned for the various VMX controls MSRs when nested VMX is enabled.
2143  * The same values should also be used to verify that vmcs12 control fields are
2144  * valid during nested entry from L1 to L2.
2145  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2146  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2147  * bit in the high half is on if the corresponding bit in the control field
2148  * may be on. See also vmx_control_verify().
2149  * TODO: allow these variables to be modified (downgraded) by module options
2150  * or other means.
2151  */
2152 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2153 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2154 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2155 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2156 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2157 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2158 static __init void nested_vmx_setup_ctls_msrs(void)
2159 {
2160         /*
2161          * Note that as a general rule, the high half of the MSRs (bits in
2162          * the control fields which may be 1) should be initialized by the
2163          * intersection of the underlying hardware's MSR (i.e., features which
2164          * can be supported) and the list of features we want to expose -
2165          * because they are known to be properly supported in our code.
2166          * Also, usually, the low half of the MSRs (bits which must be 1) can
2167          * be set to 0, meaning that L1 may turn off any of these bits. The
2168          * reason is that if one of these bits is necessary, it will appear
2169          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2170          * fields of vmcs01 and vmcs02, will turn these bits off - and
2171          * nested_vmx_exit_handled() will not pass related exits to L1.
2172          * These rules have exceptions below.
2173          */
2174
2175         /* pin-based controls */
2176         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2177               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2178         /*
2179          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2180          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2181          */
2182         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2183         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2184                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2185                 PIN_BASED_VMX_PREEMPTION_TIMER;
2186         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2187
2188         /*
2189          * Exit controls
2190          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2191          * 17 must be 1.
2192          */
2193         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2194         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2195 #ifdef CONFIG_X86_64
2196         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2197 #else
2198         nested_vmx_exit_ctls_high = 0;
2199 #endif
2200         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2201
2202         /* entry controls */
2203         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2204                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2205         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2206         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2207         nested_vmx_entry_ctls_high &=
2208                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2209         nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2210
2211         /* cpu-based controls */
2212         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2213                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2214         nested_vmx_procbased_ctls_low = 0;
2215         nested_vmx_procbased_ctls_high &=
2216                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2217                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2218                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2219                 CPU_BASED_CR3_STORE_EXITING |
2220 #ifdef CONFIG_X86_64
2221                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2222 #endif
2223                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2224                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2225                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2226                 CPU_BASED_PAUSE_EXITING |
2227                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2228         /*
2229          * We can allow some features even when not supported by the
2230          * hardware. For example, L1 can specify an MSR bitmap - and we
2231          * can use it to avoid exits to L1 - even when L0 runs L2
2232          * without MSR bitmaps.
2233          */
2234         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2235
2236         /* secondary cpu-based controls */
2237         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2238                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2239         nested_vmx_secondary_ctls_low = 0;
2240         nested_vmx_secondary_ctls_high &=
2241                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2242                 SECONDARY_EXEC_WBINVD_EXITING;
2243
2244         /* miscellaneous data */
2245         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2246         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2247                 VMX_MISC_SAVE_EFER_LMA;
2248         nested_vmx_misc_high = 0;
2249 }
2250
2251 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2252 {
2253         /*
2254          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2255          */
2256         return ((control & high) | low) == control;
2257 }
2258
2259 static inline u64 vmx_control_msr(u32 low, u32 high)
2260 {
2261         return low | ((u64)high << 32);
2262 }
2263
2264 /*
2265  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2266  * also let it use VMX-specific MSRs.
2267  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2268  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2269  * like all other MSRs).
2270  */
2271 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2272 {
2273         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2274                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2275                 /*
2276                  * According to the spec, processors which do not support VMX
2277                  * should throw a #GP(0) when VMX capability MSRs are read.
2278                  */
2279                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2280                 return 1;
2281         }
2282
2283         switch (msr_index) {
2284         case MSR_IA32_FEATURE_CONTROL:
2285                 *pdata = 0;
2286                 break;
2287         case MSR_IA32_VMX_BASIC:
2288                 /*
2289                  * This MSR reports some information about VMX support. We
2290                  * should return information about the VMX we emulate for the
2291                  * guest, and the VMCS structure we give it - not about the
2292                  * VMX support of the underlying hardware.
2293                  */
2294                 *pdata = VMCS12_REVISION |
2295                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2296                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2297                 break;
2298         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2299         case MSR_IA32_VMX_PINBASED_CTLS:
2300                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2301                                         nested_vmx_pinbased_ctls_high);
2302                 break;
2303         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2304         case MSR_IA32_VMX_PROCBASED_CTLS:
2305                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2306                                         nested_vmx_procbased_ctls_high);
2307                 break;
2308         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2309         case MSR_IA32_VMX_EXIT_CTLS:
2310                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2311                                         nested_vmx_exit_ctls_high);
2312                 break;
2313         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2314         case MSR_IA32_VMX_ENTRY_CTLS:
2315                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2316                                         nested_vmx_entry_ctls_high);
2317                 break;
2318         case MSR_IA32_VMX_MISC:
2319                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2320                                          nested_vmx_misc_high);
2321                 break;
2322         /*
2323          * These MSRs specify bits which the guest must keep fixed (on or off)
2324          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2325          * We picked the standard core2 setting.
2326          */
2327 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2328 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2329         case MSR_IA32_VMX_CR0_FIXED0:
2330                 *pdata = VMXON_CR0_ALWAYSON;
2331                 break;
2332         case MSR_IA32_VMX_CR0_FIXED1:
2333                 *pdata = -1ULL;
2334                 break;
2335         case MSR_IA32_VMX_CR4_FIXED0:
2336                 *pdata = VMXON_CR4_ALWAYSON;
2337                 break;
2338         case MSR_IA32_VMX_CR4_FIXED1:
2339                 *pdata = -1ULL;
2340                 break;
2341         case MSR_IA32_VMX_VMCS_ENUM:
2342                 *pdata = 0x1f;
2343                 break;
2344         case MSR_IA32_VMX_PROCBASED_CTLS2:
2345                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2346                                         nested_vmx_secondary_ctls_high);
2347                 break;
2348         case MSR_IA32_VMX_EPT_VPID_CAP:
2349                 /* Currently, no nested ept or nested vpid */
2350                 *pdata = 0;
2351                 break;
2352         default:
2353                 return 0;
2354         }
2355
2356         return 1;
2357 }
2358
2359 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2360 {
2361         if (!nested_vmx_allowed(vcpu))
2362                 return 0;
2363
2364         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2365                 /* TODO: the right thing. */
2366                 return 1;
2367         /*
2368          * No need to treat VMX capability MSRs specially: If we don't handle
2369          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2370          */
2371         return 0;
2372 }
2373
2374 /*
2375  * Reads an msr value (of 'msr_index') into 'pdata'.
2376  * Returns 0 on success, non-0 otherwise.
2377  * Assumes vcpu_load() was already called.
2378  */
2379 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2380 {
2381         u64 data;
2382         struct shared_msr_entry *msr;
2383
2384         if (!pdata) {
2385                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2386                 return -EINVAL;
2387         }
2388
2389         switch (msr_index) {
2390 #ifdef CONFIG_X86_64
2391         case MSR_FS_BASE:
2392                 data = vmcs_readl(GUEST_FS_BASE);
2393                 break;
2394         case MSR_GS_BASE:
2395                 data = vmcs_readl(GUEST_GS_BASE);
2396                 break;
2397         case MSR_KERNEL_GS_BASE:
2398                 vmx_load_host_state(to_vmx(vcpu));
2399                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2400                 break;
2401 #endif
2402         case MSR_EFER:
2403                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2404         case MSR_IA32_TSC:
2405                 data = guest_read_tsc();
2406                 break;
2407         case MSR_IA32_SYSENTER_CS:
2408                 data = vmcs_read32(GUEST_SYSENTER_CS);
2409                 break;
2410         case MSR_IA32_SYSENTER_EIP:
2411                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2412                 break;
2413         case MSR_IA32_SYSENTER_ESP:
2414                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2415                 break;
2416         case MSR_TSC_AUX:
2417                 if (!to_vmx(vcpu)->rdtscp_enabled)
2418                         return 1;
2419                 /* Otherwise falls through */
2420         default:
2421                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2422                         return 0;
2423                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2424                 if (msr) {
2425                         data = msr->data;
2426                         break;
2427                 }
2428                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2429         }
2430
2431         *pdata = data;
2432         return 0;
2433 }
2434
2435 /*
2436  * Writes msr value into into the appropriate "register".
2437  * Returns 0 on success, non-0 otherwise.
2438  * Assumes vcpu_load() was already called.
2439  */
2440 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2441 {
2442         struct vcpu_vmx *vmx = to_vmx(vcpu);
2443         struct shared_msr_entry *msr;
2444         int ret = 0;
2445         u32 msr_index = msr_info->index;
2446         u64 data = msr_info->data;
2447
2448         switch (msr_index) {
2449         case MSR_EFER:
2450                 ret = kvm_set_msr_common(vcpu, msr_info);
2451                 break;
2452 #ifdef CONFIG_X86_64
2453         case MSR_FS_BASE:
2454                 vmx_segment_cache_clear(vmx);
2455                 vmcs_writel(GUEST_FS_BASE, data);
2456                 break;
2457         case MSR_GS_BASE:
2458                 vmx_segment_cache_clear(vmx);
2459                 vmcs_writel(GUEST_GS_BASE, data);
2460                 break;
2461         case MSR_KERNEL_GS_BASE:
2462                 vmx_load_host_state(vmx);
2463                 vmx->msr_guest_kernel_gs_base = data;
2464                 break;
2465 #endif
2466         case MSR_IA32_SYSENTER_CS:
2467                 vmcs_write32(GUEST_SYSENTER_CS, data);
2468                 break;
2469         case MSR_IA32_SYSENTER_EIP:
2470                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2471                 break;
2472         case MSR_IA32_SYSENTER_ESP:
2473                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2474                 break;
2475         case MSR_IA32_TSC:
2476                 kvm_write_tsc(vcpu, msr_info);
2477                 break;
2478         case MSR_IA32_CR_PAT:
2479                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2480                         vmcs_write64(GUEST_IA32_PAT, data);
2481                         vcpu->arch.pat = data;
2482                         break;
2483                 }
2484                 ret = kvm_set_msr_common(vcpu, msr_info);
2485                 break;
2486         case MSR_IA32_TSC_ADJUST:
2487                 ret = kvm_set_msr_common(vcpu, msr_info);
2488                 break;
2489         case MSR_TSC_AUX:
2490                 if (!vmx->rdtscp_enabled)
2491                         return 1;
2492                 /* Check reserved bit, higher 32 bits should be zero */
2493                 if ((data >> 32) != 0)
2494                         return 1;
2495                 /* Otherwise falls through */
2496         default:
2497                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2498                         break;
2499                 msr = find_msr_entry(vmx, msr_index);
2500                 if (msr) {
2501                         msr->data = data;
2502                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2503                                 preempt_disable();
2504                                 kvm_set_shared_msr(msr->index, msr->data,
2505                                                    msr->mask);
2506                                 preempt_enable();
2507                         }
2508                         break;
2509                 }
2510                 ret = kvm_set_msr_common(vcpu, msr_info);
2511         }
2512
2513         return ret;
2514 }
2515
2516 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2517 {
2518         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2519         switch (reg) {
2520         case VCPU_REGS_RSP:
2521                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2522                 break;
2523         case VCPU_REGS_RIP:
2524                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2525                 break;
2526         case VCPU_EXREG_PDPTR:
2527                 if (enable_ept)
2528                         ept_save_pdptrs(vcpu);
2529                 break;
2530         default:
2531                 break;
2532         }
2533 }
2534
2535 static __init int cpu_has_kvm_support(void)
2536 {
2537         return cpu_has_vmx();
2538 }
2539
2540 static __init int vmx_disabled_by_bios(void)
2541 {
2542         u64 msr;
2543
2544         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2545         if (msr & FEATURE_CONTROL_LOCKED) {
2546                 /* launched w/ TXT and VMX disabled */
2547                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2548                         && tboot_enabled())
2549                         return 1;
2550                 /* launched w/o TXT and VMX only enabled w/ TXT */
2551                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2552                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2553                         && !tboot_enabled()) {
2554                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2555                                 "activate TXT before enabling KVM\n");
2556                         return 1;
2557                 }
2558                 /* launched w/o TXT and VMX disabled */
2559                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2560                         && !tboot_enabled())
2561                         return 1;
2562         }
2563
2564         return 0;
2565 }
2566
2567 static void kvm_cpu_vmxon(u64 addr)
2568 {
2569         asm volatile (ASM_VMX_VMXON_RAX
2570                         : : "a"(&addr), "m"(addr)
2571                         : "memory", "cc");
2572 }
2573
2574 static int hardware_enable(void *garbage)
2575 {
2576         int cpu = raw_smp_processor_id();
2577         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2578         u64 old, test_bits;
2579
2580         if (read_cr4() & X86_CR4_VMXE)
2581                 return -EBUSY;
2582
2583         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2584
2585         /*
2586          * Now we can enable the vmclear operation in kdump
2587          * since the loaded_vmcss_on_cpu list on this cpu
2588          * has been initialized.
2589          *
2590          * Though the cpu is not in VMX operation now, there
2591          * is no problem to enable the vmclear operation
2592          * for the loaded_vmcss_on_cpu list is empty!
2593          */
2594         crash_enable_local_vmclear(cpu);
2595
2596         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2597
2598         test_bits = FEATURE_CONTROL_LOCKED;
2599         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2600         if (tboot_enabled())
2601                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2602
2603         if ((old & test_bits) != test_bits) {
2604                 /* enable and lock */
2605                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2606         }
2607         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2608
2609         if (vmm_exclusive) {
2610                 kvm_cpu_vmxon(phys_addr);
2611                 ept_sync_global();
2612         }
2613
2614         native_store_gdt(&__get_cpu_var(host_gdt));
2615
2616         return 0;
2617 }
2618
2619 static void vmclear_local_loaded_vmcss(void)
2620 {
2621         int cpu = raw_smp_processor_id();
2622         struct loaded_vmcs *v, *n;
2623
2624         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2625                                  loaded_vmcss_on_cpu_link)
2626                 __loaded_vmcs_clear(v);
2627 }
2628
2629
2630 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2631  * tricks.
2632  */
2633 static void kvm_cpu_vmxoff(void)
2634 {
2635         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2636 }
2637
2638 static void hardware_disable(void *garbage)
2639 {
2640         if (vmm_exclusive) {
2641                 vmclear_local_loaded_vmcss();
2642                 kvm_cpu_vmxoff();
2643         }
2644         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2645 }
2646
2647 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2648                                       u32 msr, u32 *result)
2649 {
2650         u32 vmx_msr_low, vmx_msr_high;
2651         u32 ctl = ctl_min | ctl_opt;
2652
2653         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2654
2655         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2656         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2657
2658         /* Ensure minimum (required) set of control bits are supported. */
2659         if (ctl_min & ~ctl)
2660                 return -EIO;
2661
2662         *result = ctl;
2663         return 0;
2664 }
2665
2666 static __init bool allow_1_setting(u32 msr, u32 ctl)
2667 {
2668         u32 vmx_msr_low, vmx_msr_high;
2669
2670         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2671         return vmx_msr_high & ctl;
2672 }
2673
2674 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2675 {
2676         u32 vmx_msr_low, vmx_msr_high;
2677         u32 min, opt, min2, opt2;
2678         u32 _pin_based_exec_control = 0;
2679         u32 _cpu_based_exec_control = 0;
2680         u32 _cpu_based_2nd_exec_control = 0;
2681         u32 _vmexit_control = 0;
2682         u32 _vmentry_control = 0;
2683
2684         min = CPU_BASED_HLT_EXITING |
2685 #ifdef CONFIG_X86_64
2686               CPU_BASED_CR8_LOAD_EXITING |
2687               CPU_BASED_CR8_STORE_EXITING |
2688 #endif
2689               CPU_BASED_CR3_LOAD_EXITING |
2690               CPU_BASED_CR3_STORE_EXITING |
2691               CPU_BASED_USE_IO_BITMAPS |
2692               CPU_BASED_MOV_DR_EXITING |
2693               CPU_BASED_USE_TSC_OFFSETING |
2694               CPU_BASED_MWAIT_EXITING |
2695               CPU_BASED_MONITOR_EXITING |
2696               CPU_BASED_INVLPG_EXITING |
2697               CPU_BASED_RDPMC_EXITING;
2698
2699         opt = CPU_BASED_TPR_SHADOW |
2700               CPU_BASED_USE_MSR_BITMAPS |
2701               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2702         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2703                                 &_cpu_based_exec_control) < 0)
2704                 return -EIO;
2705 #ifdef CONFIG_X86_64
2706         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2707                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2708                                            ~CPU_BASED_CR8_STORE_EXITING;
2709 #endif
2710         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2711                 min2 = 0;
2712                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2713                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2714                         SECONDARY_EXEC_WBINVD_EXITING |
2715                         SECONDARY_EXEC_ENABLE_VPID |
2716                         SECONDARY_EXEC_ENABLE_EPT |
2717                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2718                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2719                         SECONDARY_EXEC_RDTSCP |
2720                         SECONDARY_EXEC_ENABLE_INVPCID |
2721                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2722                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2723                         SECONDARY_EXEC_SHADOW_VMCS;
2724                 if (adjust_vmx_controls(min2, opt2,
2725                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2726                                         &_cpu_based_2nd_exec_control) < 0)
2727                         return -EIO;
2728         }
2729 #ifndef CONFIG_X86_64
2730         if (!(_cpu_based_2nd_exec_control &
2731                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2732                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2733 #endif
2734
2735         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2736                 _cpu_based_2nd_exec_control &= ~(
2737                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2738                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2739                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2740
2741         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2742                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2743                    enabled */
2744                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2745                                              CPU_BASED_CR3_STORE_EXITING |
2746                                              CPU_BASED_INVLPG_EXITING);
2747                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2748                       vmx_capability.ept, vmx_capability.vpid);
2749         }
2750
2751         min = 0;
2752 #ifdef CONFIG_X86_64
2753         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2754 #endif
2755         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2756                 VM_EXIT_ACK_INTR_ON_EXIT;
2757         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2758                                 &_vmexit_control) < 0)
2759                 return -EIO;
2760
2761         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2762         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2763         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2764                                 &_pin_based_exec_control) < 0)
2765                 return -EIO;
2766
2767         if (!(_cpu_based_2nd_exec_control &
2768                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2769                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2770                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2771
2772         min = 0;
2773         opt = VM_ENTRY_LOAD_IA32_PAT;
2774         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2775                                 &_vmentry_control) < 0)
2776                 return -EIO;
2777
2778         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2779
2780         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2781         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2782                 return -EIO;
2783
2784 #ifdef CONFIG_X86_64
2785         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2786         if (vmx_msr_high & (1u<<16))
2787                 return -EIO;
2788 #endif
2789
2790         /* Require Write-Back (WB) memory type for VMCS accesses. */
2791         if (((vmx_msr_high >> 18) & 15) != 6)
2792                 return -EIO;
2793
2794         vmcs_conf->size = vmx_msr_high & 0x1fff;
2795         vmcs_conf->order = get_order(vmcs_config.size);
2796         vmcs_conf->revision_id = vmx_msr_low;
2797
2798         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2799         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2800         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2801         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2802         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2803
2804         cpu_has_load_ia32_efer =
2805                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2806                                 VM_ENTRY_LOAD_IA32_EFER)
2807                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2808                                    VM_EXIT_LOAD_IA32_EFER);
2809
2810         cpu_has_load_perf_global_ctrl =
2811                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2812                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2813                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2814                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2815
2816         /*
2817          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2818          * but due to arrata below it can't be used. Workaround is to use
2819          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2820          *
2821          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2822          *
2823          * AAK155             (model 26)
2824          * AAP115             (model 30)
2825          * AAT100             (model 37)
2826          * BC86,AAY89,BD102   (model 44)
2827          * BA97               (model 46)
2828          *
2829          */
2830         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2831                 switch (boot_cpu_data.x86_model) {
2832                 case 26:
2833                 case 30:
2834                 case 37:
2835                 case 44:
2836                 case 46:
2837                         cpu_has_load_perf_global_ctrl = false;
2838                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2839                                         "does not work properly. Using workaround\n");
2840                         break;
2841                 default:
2842                         break;
2843                 }
2844         }
2845
2846         return 0;
2847 }
2848
2849 static struct vmcs *alloc_vmcs_cpu(int cpu)
2850 {
2851         int node = cpu_to_node(cpu);
2852         struct page *pages;
2853         struct vmcs *vmcs;
2854
2855         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2856         if (!pages)
2857                 return NULL;
2858         vmcs = page_address(pages);
2859         memset(vmcs, 0, vmcs_config.size);
2860         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2861         return vmcs;
2862 }
2863
2864 static struct vmcs *alloc_vmcs(void)
2865 {
2866         return alloc_vmcs_cpu(raw_smp_processor_id());
2867 }
2868
2869 static void free_vmcs(struct vmcs *vmcs)
2870 {
2871         free_pages((unsigned long)vmcs, vmcs_config.order);
2872 }
2873
2874 /*
2875  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2876  */
2877 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2878 {
2879         if (!loaded_vmcs->vmcs)
2880                 return;
2881         loaded_vmcs_clear(loaded_vmcs);
2882         free_vmcs(loaded_vmcs->vmcs);
2883         loaded_vmcs->vmcs = NULL;
2884 }
2885
2886 static void free_kvm_area(void)
2887 {
2888         int cpu;
2889
2890         for_each_possible_cpu(cpu) {
2891                 free_vmcs(per_cpu(vmxarea, cpu));
2892                 per_cpu(vmxarea, cpu) = NULL;
2893         }
2894 }
2895
2896 static __init int alloc_kvm_area(void)
2897 {
2898         int cpu;
2899
2900         for_each_possible_cpu(cpu) {
2901                 struct vmcs *vmcs;
2902
2903                 vmcs = alloc_vmcs_cpu(cpu);
2904                 if (!vmcs) {
2905                         free_kvm_area();
2906                         return -ENOMEM;
2907                 }
2908
2909                 per_cpu(vmxarea, cpu) = vmcs;
2910         }
2911         return 0;
2912 }
2913
2914 static __init int hardware_setup(void)
2915 {
2916         if (setup_vmcs_config(&vmcs_config) < 0)
2917                 return -EIO;
2918
2919         if (boot_cpu_has(X86_FEATURE_NX))
2920                 kvm_enable_efer_bits(EFER_NX);
2921
2922         if (!cpu_has_vmx_vpid())
2923                 enable_vpid = 0;
2924         if (!cpu_has_vmx_shadow_vmcs())
2925                 enable_shadow_vmcs = 0;
2926
2927         if (!cpu_has_vmx_ept() ||
2928             !cpu_has_vmx_ept_4levels()) {
2929                 enable_ept = 0;
2930                 enable_unrestricted_guest = 0;
2931                 enable_ept_ad_bits = 0;
2932         }
2933
2934         if (!cpu_has_vmx_ept_ad_bits())
2935                 enable_ept_ad_bits = 0;
2936
2937         if (!cpu_has_vmx_unrestricted_guest())
2938                 enable_unrestricted_guest = 0;
2939
2940         if (!cpu_has_vmx_flexpriority())
2941                 flexpriority_enabled = 0;
2942
2943         if (!cpu_has_vmx_tpr_shadow())
2944                 kvm_x86_ops->update_cr8_intercept = NULL;
2945
2946         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2947                 kvm_disable_largepages();
2948
2949         if (!cpu_has_vmx_ple())
2950                 ple_gap = 0;
2951
2952         if (!cpu_has_vmx_apicv())
2953                 enable_apicv = 0;
2954
2955         if (enable_apicv)
2956                 kvm_x86_ops->update_cr8_intercept = NULL;
2957         else {
2958                 kvm_x86_ops->hwapic_irr_update = NULL;
2959                 kvm_x86_ops->deliver_posted_interrupt = NULL;
2960                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2961         }
2962
2963         if (nested)
2964                 nested_vmx_setup_ctls_msrs();
2965
2966         return alloc_kvm_area();
2967 }
2968
2969 static __exit void hardware_unsetup(void)
2970 {
2971         free_kvm_area();
2972 }
2973
2974 static bool emulation_required(struct kvm_vcpu *vcpu)
2975 {
2976         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2977 }
2978
2979 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2980                 struct kvm_segment *save)
2981 {
2982         if (!emulate_invalid_guest_state) {
2983                 /*
2984                  * CS and SS RPL should be equal during guest entry according
2985                  * to VMX spec, but in reality it is not always so. Since vcpu
2986                  * is in the middle of the transition from real mode to
2987                  * protected mode it is safe to assume that RPL 0 is a good
2988                  * default value.
2989                  */
2990                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2991                         save->selector &= ~SELECTOR_RPL_MASK;
2992                 save->dpl = save->selector & SELECTOR_RPL_MASK;
2993                 save->s = 1;
2994         }
2995         vmx_set_segment(vcpu, save, seg);
2996 }
2997
2998 static void enter_pmode(struct kvm_vcpu *vcpu)
2999 {
3000         unsigned long flags;
3001         struct vcpu_vmx *vmx = to_vmx(vcpu);
3002
3003         /*
3004          * Update real mode segment cache. It may be not up-to-date if sement
3005          * register was written while vcpu was in a guest mode.
3006          */
3007         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3008         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3009         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3010         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3011         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3012         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3013
3014         vmx->rmode.vm86_active = 0;
3015
3016         vmx_segment_cache_clear(vmx);
3017
3018         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3019
3020         flags = vmcs_readl(GUEST_RFLAGS);
3021         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3022         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3023         vmcs_writel(GUEST_RFLAGS, flags);
3024
3025         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3026                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3027
3028         update_exception_bitmap(vcpu);
3029
3030         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3031         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3032         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3033         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3034         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3035         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3036
3037         /* CPL is always 0 when CPU enters protected mode */
3038         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3039         vmx->cpl = 0;
3040 }
3041
3042 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3043 {
3044         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3045         struct kvm_segment var = *save;
3046
3047         var.dpl = 0x3;
3048         if (seg == VCPU_SREG_CS)
3049                 var.type = 0x3;
3050
3051         if (!emulate_invalid_guest_state) {
3052                 var.selector = var.base >> 4;
3053                 var.base = var.base & 0xffff0;
3054                 var.limit = 0xffff;
3055                 var.g = 0;
3056                 var.db = 0;
3057                 var.present = 1;
3058                 var.s = 1;
3059                 var.l = 0;
3060                 var.unusable = 0;
3061                 var.type = 0x3;
3062                 var.avl = 0;
3063                 if (save->base & 0xf)
3064                         printk_once(KERN_WARNING "kvm: segment base is not "
3065                                         "paragraph aligned when entering "
3066                                         "protected mode (seg=%d)", seg);
3067         }
3068
3069         vmcs_write16(sf->selector, var.selector);
3070         vmcs_write32(sf->base, var.base);
3071         vmcs_write32(sf->limit, var.limit);
3072         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3073 }
3074
3075 static void enter_rmode(struct kvm_vcpu *vcpu)
3076 {
3077         unsigned long flags;
3078         struct vcpu_vmx *vmx = to_vmx(vcpu);
3079
3080         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3081         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3082         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3083         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3084         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3085         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3086         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3087
3088         vmx->rmode.vm86_active = 1;
3089
3090         /*
3091          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3092          * vcpu. Warn the user that an update is overdue.
3093          */
3094         if (!vcpu->kvm->arch.tss_addr)
3095                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3096                              "called before entering vcpu\n");
3097
3098         vmx_segment_cache_clear(vmx);
3099
3100         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3101         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3102         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3103
3104         flags = vmcs_readl(GUEST_RFLAGS);
3105         vmx->rmode.save_rflags = flags;
3106
3107         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3108
3109         vmcs_writel(GUEST_RFLAGS, flags);
3110         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3111         update_exception_bitmap(vcpu);
3112
3113         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3114         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3115         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3116         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3117         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3118         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3119
3120         kvm_mmu_reset_context(vcpu);
3121 }
3122
3123 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3124 {
3125         struct vcpu_vmx *vmx = to_vmx(vcpu);
3126         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3127
3128         if (!msr)
3129                 return;
3130
3131         /*
3132          * Force kernel_gs_base reloading before EFER changes, as control
3133          * of this msr depends on is_long_mode().
3134          */
3135         vmx_load_host_state(to_vmx(vcpu));
3136         vcpu->arch.efer = efer;
3137         if (efer & EFER_LMA) {
3138                 vmcs_write32(VM_ENTRY_CONTROLS,
3139                              vmcs_read32(VM_ENTRY_CONTROLS) |
3140                              VM_ENTRY_IA32E_MODE);
3141                 msr->data = efer;
3142         } else {
3143                 vmcs_write32(VM_ENTRY_CONTROLS,
3144                              vmcs_read32(VM_ENTRY_CONTROLS) &
3145                              ~VM_ENTRY_IA32E_MODE);
3146
3147                 msr->data = efer & ~EFER_LME;
3148         }
3149         setup_msrs(vmx);
3150 }
3151
3152 #ifdef CONFIG_X86_64
3153
3154 static void enter_lmode(struct kvm_vcpu *vcpu)
3155 {
3156         u32 guest_tr_ar;
3157
3158         vmx_segment_cache_clear(to_vmx(vcpu));
3159
3160         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3161         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3162                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3163                                      __func__);
3164                 vmcs_write32(GUEST_TR_AR_BYTES,
3165                              (guest_tr_ar & ~AR_TYPE_MASK)
3166                              | AR_TYPE_BUSY_64_TSS);
3167         }
3168         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3169 }
3170
3171 static void exit_lmode(struct kvm_vcpu *vcpu)
3172 {
3173         vmcs_write32(VM_ENTRY_CONTROLS,
3174                      vmcs_read32(VM_ENTRY_CONTROLS)
3175                      & ~VM_ENTRY_IA32E_MODE);
3176         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3177 }
3178
3179 #endif
3180
3181 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3182 {
3183         vpid_sync_context(to_vmx(vcpu));
3184         if (enable_ept) {
3185                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3186                         return;
3187                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3188         }
3189 }
3190
3191 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3192 {
3193         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3194
3195         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3196         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3197 }
3198
3199 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3200 {
3201         if (enable_ept && is_paging(vcpu))
3202                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3203         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3204 }
3205
3206 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3207 {
3208         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3209
3210         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3211         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3212 }
3213
3214 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3215 {
3216         if (!test_bit(VCPU_EXREG_PDPTR,
3217                       (unsigned long *)&vcpu->arch.regs_dirty))
3218                 return;
3219
3220         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3221                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3222                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3223                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3224                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3225         }
3226 }
3227
3228 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3229 {
3230         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3231                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3232                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3233                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3234                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3235         }
3236
3237         __set_bit(VCPU_EXREG_PDPTR,
3238                   (unsigned long *)&vcpu->arch.regs_avail);
3239         __set_bit(VCPU_EXREG_PDPTR,
3240                   (unsigned long *)&vcpu->arch.regs_dirty);
3241 }
3242
3243 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3244
3245 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3246                                         unsigned long cr0,
3247                                         struct kvm_vcpu *vcpu)
3248 {
3249         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3250                 vmx_decache_cr3(vcpu);
3251         if (!(cr0 & X86_CR0_PG)) {
3252                 /* From paging/starting to nonpaging */
3253                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3254                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3255                              (CPU_BASED_CR3_LOAD_EXITING |
3256                               CPU_BASED_CR3_STORE_EXITING));
3257                 vcpu->arch.cr0 = cr0;
3258                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3259         } else if (!is_paging(vcpu)) {
3260                 /* From nonpaging to paging */
3261                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3262                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3263                              ~(CPU_BASED_CR3_LOAD_EXITING |
3264                                CPU_BASED_CR3_STORE_EXITING));
3265                 vcpu->arch.cr0 = cr0;
3266                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3267         }
3268
3269         if (!(cr0 & X86_CR0_WP))
3270                 *hw_cr0 &= ~X86_CR0_WP;
3271 }
3272
3273 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3274 {
3275         struct vcpu_vmx *vmx = to_vmx(vcpu);
3276         unsigned long hw_cr0;
3277
3278         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3279         if (enable_unrestricted_guest)
3280                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3281         else {
3282                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3283
3284                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3285                         enter_pmode(vcpu);
3286
3287                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3288                         enter_rmode(vcpu);
3289         }
3290
3291 #ifdef CONFIG_X86_64
3292         if (vcpu->arch.efer & EFER_LME) {
3293                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3294                         enter_lmode(vcpu);
3295                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3296                         exit_lmode(vcpu);
3297         }
3298 #endif
3299
3300         if (enable_ept)
3301                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3302
3303         if (!vcpu->fpu_active)
3304                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3305
3306         vmcs_writel(CR0_READ_SHADOW, cr0);
3307         vmcs_writel(GUEST_CR0, hw_cr0);
3308         vcpu->arch.cr0 = cr0;
3309
3310         /* depends on vcpu->arch.cr0 to be set to a new value */
3311         vmx->emulation_required = emulation_required(vcpu);
3312 }
3313
3314 static u64 construct_eptp(unsigned long root_hpa)
3315 {
3316         u64 eptp;
3317
3318         /* TODO write the value reading from MSR */
3319         eptp = VMX_EPT_DEFAULT_MT |
3320                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3321         if (enable_ept_ad_bits)
3322                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3323         eptp |= (root_hpa & PAGE_MASK);
3324
3325         return eptp;
3326 }
3327
3328 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3329 {
3330         unsigned long guest_cr3;
3331         u64 eptp;
3332
3333         guest_cr3 = cr3;
3334         if (enable_ept) {
3335                 eptp = construct_eptp(cr3);
3336                 vmcs_write64(EPT_POINTER, eptp);
3337                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3338                         vcpu->kvm->arch.ept_identity_map_addr;
3339                 ept_load_pdptrs(vcpu);
3340         }
3341
3342         vmx_flush_tlb(vcpu);
3343         vmcs_writel(GUEST_CR3, guest_cr3);
3344 }
3345
3346 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3347 {
3348         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3349                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3350
3351         if (cr4 & X86_CR4_VMXE) {
3352                 /*
3353                  * To use VMXON (and later other VMX instructions), a guest
3354                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3355                  * So basically the check on whether to allow nested VMX
3356                  * is here.
3357                  */
3358                 if (!nested_vmx_allowed(vcpu))
3359                         return 1;
3360         }
3361         if (to_vmx(vcpu)->nested.vmxon &&
3362             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3363                 return 1;
3364
3365         vcpu->arch.cr4 = cr4;
3366         if (enable_ept) {
3367                 if (!is_paging(vcpu)) {
3368                         hw_cr4 &= ~X86_CR4_PAE;
3369                         hw_cr4 |= X86_CR4_PSE;
3370                         /*
3371                          * SMEP is disabled if CPU is in non-paging mode in
3372                          * hardware. However KVM always uses paging mode to
3373                          * emulate guest non-paging mode with TDP.
3374                          * To emulate this behavior, SMEP needs to be manually
3375                          * disabled when guest switches to non-paging mode.
3376                          */
3377                         hw_cr4 &= ~X86_CR4_SMEP;
3378                 } else if (!(cr4 & X86_CR4_PAE)) {
3379                         hw_cr4 &= ~X86_CR4_PAE;
3380                 }
3381         }
3382
3383         vmcs_writel(CR4_READ_SHADOW, cr4);
3384         vmcs_writel(GUEST_CR4, hw_cr4);
3385         return 0;
3386 }
3387
3388 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3389                             struct kvm_segment *var, int seg)
3390 {
3391         struct vcpu_vmx *vmx = to_vmx(vcpu);
3392         u32 ar;
3393
3394         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3395                 *var = vmx->rmode.segs[seg];
3396                 if (seg == VCPU_SREG_TR
3397                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3398                         return;
3399                 var->base = vmx_read_guest_seg_base(vmx, seg);
3400                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3401                 return;
3402         }
3403         var->base = vmx_read_guest_seg_base(vmx, seg);
3404         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3405         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3406         ar = vmx_read_guest_seg_ar(vmx, seg);
3407         var->unusable = (ar >> 16) & 1;
3408         var->type = ar & 15;
3409         var->s = (ar >> 4) & 1;
3410         var->dpl = (ar >> 5) & 3;
3411         /*
3412          * Some userspaces do not preserve unusable property. Since usable
3413          * segment has to be present according to VMX spec we can use present
3414          * property to amend userspace bug by making unusable segment always
3415          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3416          * segment as unusable.
3417          */
3418         var->present = !var->unusable;
3419         var->avl = (ar >> 12) & 1;
3420         var->l = (ar >> 13) & 1;
3421         var->db = (ar >> 14) & 1;
3422         var->g = (ar >> 15) & 1;
3423 }
3424
3425 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3426 {
3427         struct kvm_segment s;
3428
3429         if (to_vmx(vcpu)->rmode.vm86_active) {
3430                 vmx_get_segment(vcpu, &s, seg);
3431                 return s.base;
3432         }
3433         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3434 }
3435
3436 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3437 {
3438         struct vcpu_vmx *vmx = to_vmx(vcpu);
3439
3440         if (!is_protmode(vcpu))
3441                 return 0;
3442
3443         if (!is_long_mode(vcpu)
3444             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3445                 return 3;
3446
3447         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3448                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3449                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3450         }
3451
3452         return vmx->cpl;
3453 }
3454
3455
3456 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3457 {
3458         u32 ar;
3459
3460         if (var->unusable || !var->present)
3461                 ar = 1 << 16;
3462         else {
3463                 ar = var->type & 15;
3464                 ar |= (var->s & 1) << 4;
3465                 ar |= (var->dpl & 3) << 5;
3466                 ar |= (var->present & 1) << 7;
3467                 ar |= (var->avl & 1) << 12;
3468                 ar |= (var->l & 1) << 13;
3469                 ar |= (var->db & 1) << 14;
3470                 ar |= (var->g & 1) << 15;
3471         }
3472
3473         return ar;
3474 }
3475
3476 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3477                             struct kvm_segment *var, int seg)
3478 {
3479         struct vcpu_vmx *vmx = to_vmx(vcpu);
3480         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3481
3482         vmx_segment_cache_clear(vmx);
3483         if (seg == VCPU_SREG_CS)
3484                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3485
3486         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3487                 vmx->rmode.segs[seg] = *var;
3488                 if (seg == VCPU_SREG_TR)
3489                         vmcs_write16(sf->selector, var->selector);
3490                 else if (var->s)
3491                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3492                 goto out;
3493         }
3494
3495         vmcs_writel(sf->base, var->base);
3496         vmcs_write32(sf->limit, var->limit);
3497         vmcs_write16(sf->selector, var->selector);
3498
3499         /*
3500          *   Fix the "Accessed" bit in AR field of segment registers for older
3501          * qemu binaries.
3502          *   IA32 arch specifies that at the time of processor reset the
3503          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3504          * is setting it to 0 in the userland code. This causes invalid guest
3505          * state vmexit when "unrestricted guest" mode is turned on.
3506          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3507          * tree. Newer qemu binaries with that qemu fix would not need this
3508          * kvm hack.
3509          */
3510         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3511                 var->type |= 0x1; /* Accessed */
3512
3513         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3514
3515 out:
3516         vmx->emulation_required |= emulation_required(vcpu);
3517 }
3518
3519 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3520 {
3521         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3522
3523         *db = (ar >> 14) & 1;
3524         *l = (ar >> 13) & 1;
3525 }
3526
3527 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3528 {
3529         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3530         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3531 }
3532
3533 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3534 {
3535         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3536         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3537 }
3538
3539 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3540 {
3541         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3542         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3543 }
3544
3545 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3546 {
3547         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3548         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3549 }
3550
3551 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3552 {
3553         struct kvm_segment var;
3554         u32 ar;
3555
3556         vmx_get_segment(vcpu, &var, seg);
3557         var.dpl = 0x3;
3558         if (seg == VCPU_SREG_CS)
3559                 var.type = 0x3;
3560         ar = vmx_segment_access_rights(&var);
3561
3562         if (var.base != (var.selector << 4))
3563                 return false;
3564         if (var.limit != 0xffff)
3565                 return false;
3566         if (ar != 0xf3)
3567                 return false;
3568
3569         return true;
3570 }
3571
3572 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3573 {
3574         struct kvm_segment cs;
3575         unsigned int cs_rpl;
3576
3577         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3578         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3579
3580         if (cs.unusable)
3581                 return false;
3582         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3583                 return false;
3584         if (!cs.s)
3585                 return false;
3586         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3587                 if (cs.dpl > cs_rpl)
3588                         return false;
3589         } else {
3590                 if (cs.dpl != cs_rpl)
3591                         return false;
3592         }
3593         if (!cs.present)
3594                 return false;
3595
3596         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3597         return true;
3598 }
3599
3600 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3601 {
3602         struct kvm_segment ss;
3603         unsigned int ss_rpl;
3604
3605         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3606         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3607
3608         if (ss.unusable)
3609                 return true;
3610         if (ss.type != 3 && ss.type != 7)
3611                 return false;
3612         if (!ss.s)
3613                 return false;
3614         if (ss.dpl != ss_rpl) /* DPL != RPL */
3615                 return false;
3616         if (!ss.present)
3617                 return false;
3618
3619         return true;
3620 }
3621
3622 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3623 {
3624         struct kvm_segment var;
3625         unsigned int rpl;
3626
3627         vmx_get_segment(vcpu, &var, seg);
3628         rpl = var.selector & SELECTOR_RPL_MASK;
3629
3630         if (var.unusable)
3631                 return true;
3632         if (!var.s)
3633                 return false;
3634         if (!var.present)
3635                 return false;
3636         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3637                 if (var.dpl < rpl) /* DPL < RPL */
3638                         return false;
3639         }
3640
3641         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3642          * rights flags
3643          */
3644         return true;
3645 }
3646
3647 static bool tr_valid(struct kvm_vcpu *vcpu)
3648 {
3649         struct kvm_segment tr;
3650
3651         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3652
3653         if (tr.unusable)
3654                 return false;
3655         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3656                 return false;
3657         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3658                 return false;
3659         if (!tr.present)
3660                 return false;
3661
3662         return true;
3663 }
3664
3665 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3666 {
3667         struct kvm_segment ldtr;
3668
3669         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3670
3671         if (ldtr.unusable)
3672                 return true;
3673         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3674                 return false;
3675         if (ldtr.type != 2)
3676                 return false;
3677         if (!ldtr.present)
3678                 return false;
3679
3680         return true;
3681 }
3682
3683 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3684 {
3685         struct kvm_segment cs, ss;
3686
3687         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3688         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3689
3690         return ((cs.selector & SELECTOR_RPL_MASK) ==
3691                  (ss.selector & SELECTOR_RPL_MASK));
3692 }
3693
3694 /*
3695  * Check if guest state is valid. Returns true if valid, false if
3696  * not.
3697  * We assume that registers are always usable
3698  */
3699 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3700 {
3701         if (enable_unrestricted_guest)
3702                 return true;
3703
3704         /* real mode guest state checks */
3705         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3706                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3707                         return false;
3708                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3709                         return false;
3710                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3711                         return false;
3712                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3713                         return false;
3714                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3715                         return false;
3716                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3717                         return false;
3718         } else {
3719         /* protected mode guest state checks */
3720                 if (!cs_ss_rpl_check(vcpu))
3721                         return false;
3722                 if (!code_segment_valid(vcpu))
3723                         return false;
3724                 if (!stack_segment_valid(vcpu))
3725                         return false;
3726                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3727                         return false;
3728                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3729                         return false;
3730                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3731                         return false;
3732                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3733                         return false;
3734                 if (!tr_valid(vcpu))
3735                         return false;
3736                 if (!ldtr_valid(vcpu))
3737                         return false;
3738         }
3739         /* TODO:
3740          * - Add checks on RIP
3741          * - Add checks on RFLAGS
3742          */
3743
3744         return true;
3745 }
3746
3747 static int init_rmode_tss(struct kvm *kvm)
3748 {
3749         gfn_t fn;
3750         u16 data = 0;
3751         int r, idx, ret = 0;
3752
3753         idx = srcu_read_lock(&kvm->srcu);
3754         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3755         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3756         if (r < 0)
3757                 goto out;
3758         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3759         r = kvm_write_guest_page(kvm, fn++, &data,
3760                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3761         if (r < 0)
3762                 goto out;
3763         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3764         if (r < 0)
3765                 goto out;
3766         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3767         if (r < 0)
3768                 goto out;
3769         data = ~0;
3770         r = kvm_write_guest_page(kvm, fn, &data,
3771                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3772                                  sizeof(u8));
3773         if (r < 0)
3774                 goto out;
3775
3776         ret = 1;
3777 out:
3778         srcu_read_unlock(&kvm->srcu, idx);
3779         return ret;
3780 }
3781
3782 static int init_rmode_identity_map(struct kvm *kvm)
3783 {
3784         int i, idx, r, ret;
3785         pfn_t identity_map_pfn;
3786         u32 tmp;
3787
3788         if (!enable_ept)
3789                 return 1;
3790         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3791                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3792                         "haven't been allocated!\n");
3793                 return 0;
3794         }
3795         if (likely(kvm->arch.ept_identity_pagetable_done))
3796                 return 1;
3797         ret = 0;
3798         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3799         idx = srcu_read_lock(&kvm->srcu);
3800         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3801         if (r < 0)
3802                 goto out;
3803         /* Set up identity-mapping pagetable for EPT in real mode */
3804         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3805                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3806                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3807                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3808                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3809                 if (r < 0)
3810                         goto out;
3811         }
3812         kvm->arch.ept_identity_pagetable_done = true;
3813         ret = 1;
3814 out:
3815         srcu_read_unlock(&kvm->srcu, idx);
3816         return ret;
3817 }
3818
3819 static void seg_setup(int seg)
3820 {
3821         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3822         unsigned int ar;
3823
3824         vmcs_write16(sf->selector, 0);
3825         vmcs_writel(sf->base, 0);
3826         vmcs_write32(sf->limit, 0xffff);
3827         ar = 0x93;
3828         if (seg == VCPU_SREG_CS)
3829                 ar |= 0x08; /* code segment */
3830
3831         vmcs_write32(sf->ar_bytes, ar);
3832 }
3833
3834 static int alloc_apic_access_page(struct kvm *kvm)
3835 {
3836         struct page *page;
3837         struct kvm_userspace_memory_region kvm_userspace_mem;
3838         int r = 0;
3839
3840         mutex_lock(&kvm->slots_lock);
3841         if (kvm->arch.apic_access_page)
3842                 goto out;
3843         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3844         kvm_userspace_mem.flags = 0;
3845         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3846         kvm_userspace_mem.memory_size = PAGE_SIZE;
3847         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3848         if (r)
3849                 goto out;
3850
3851         page = gfn_to_page(kvm, 0xfee00);
3852         if (is_error_page(page)) {
3853                 r = -EFAULT;
3854                 goto out;
3855         }
3856
3857         kvm->arch.apic_access_page = page;
3858 out:
3859         mutex_unlock(&kvm->slots_lock);
3860         return r;
3861 }
3862
3863 static int alloc_identity_pagetable(struct kvm *kvm)
3864 {
3865         struct page *page;
3866         struct kvm_userspace_memory_region kvm_userspace_mem;
3867         int r = 0;
3868
3869         mutex_lock(&kvm->slots_lock);
3870         if (kvm->arch.ept_identity_pagetable)
3871                 goto out;
3872         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3873         kvm_userspace_mem.flags = 0;
3874         kvm_userspace_mem.guest_phys_addr =
3875                 kvm->arch.ept_identity_map_addr;
3876         kvm_userspace_mem.memory_size = PAGE_SIZE;
3877         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3878         if (r)
3879                 goto out;
3880
3881         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3882         if (is_error_page(page)) {
3883                 r = -EFAULT;
3884                 goto out;
3885         }
3886
3887         kvm->arch.ept_identity_pagetable = page;
3888 out:
3889         mutex_unlock(&kvm->slots_lock);
3890         return r;
3891 }
3892
3893 static void allocate_vpid(struct vcpu_vmx *vmx)
3894 {
3895         int vpid;
3896
3897         vmx->vpid = 0;
3898         if (!enable_vpid)
3899                 return;
3900         spin_lock(&vmx_vpid_lock);
3901         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3902         if (vpid < VMX_NR_VPIDS) {
3903                 vmx->vpid = vpid;
3904                 __set_bit(vpid, vmx_vpid_bitmap);
3905         }
3906         spin_unlock(&vmx_vpid_lock);
3907 }
3908
3909 static void free_vpid(struct vcpu_vmx *vmx)
3910 {
3911         if (!enable_vpid)
3912                 return;
3913         spin_lock(&vmx_vpid_lock);
3914         if (vmx->vpid != 0)
3915                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3916         spin_unlock(&vmx_vpid_lock);
3917 }
3918
3919 #define MSR_TYPE_R      1
3920 #define MSR_TYPE_W      2
3921 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3922                                                 u32 msr, int type)
3923 {
3924         int f = sizeof(unsigned long);
3925
3926         if (!cpu_has_vmx_msr_bitmap())
3927                 return;
3928
3929         /*
3930          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3931          * have the write-low and read-high bitmap offsets the wrong way round.
3932          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3933          */
3934         if (msr <= 0x1fff) {
3935                 if (type & MSR_TYPE_R)
3936                         /* read-low */
3937                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3938
3939                 if (type & MSR_TYPE_W)
3940                         /* write-low */
3941                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3942
3943         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3944                 msr &= 0x1fff;
3945                 if (type & MSR_TYPE_R)
3946                         /* read-high */
3947                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3948
3949                 if (type & MSR_TYPE_W)
3950                         /* write-high */
3951                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3952
3953         }
3954 }
3955
3956 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3957                                                 u32 msr, int type)
3958 {
3959         int f = sizeof(unsigned long);
3960
3961         if (!cpu_has_vmx_msr_bitmap())
3962                 return;
3963
3964         /*
3965          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3966          * have the write-low and read-high bitmap offsets the wrong way round.
3967          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3968          */
3969         if (msr <= 0x1fff) {
3970                 if (type & MSR_TYPE_R)
3971                         /* read-low */
3972                         __set_bit(msr, msr_bitmap + 0x000 / f);
3973
3974                 if (type & MSR_TYPE_W)
3975                         /* write-low */
3976                         __set_bit(msr, msr_bitmap + 0x800 / f);
3977
3978         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3979                 msr &= 0x1fff;
3980                 if (type & MSR_TYPE_R)
3981                         /* read-high */
3982                         __set_bit(msr, msr_bitmap + 0x400 / f);
3983
3984                 if (type & MSR_TYPE_W)
3985                         /* write-high */
3986                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3987
3988         }
3989 }
3990
3991 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3992 {
3993         if (!longmode_only)
3994                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3995                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3996         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3997                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3998 }
3999
4000 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4001 {
4002         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4003                         msr, MSR_TYPE_R);
4004         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4005                         msr, MSR_TYPE_R);
4006 }
4007
4008 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4009 {
4010         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4011                         msr, MSR_TYPE_R);
4012         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4013                         msr, MSR_TYPE_R);
4014 }
4015
4016 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4017 {
4018         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4019                         msr, MSR_TYPE_W);
4020         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4021                         msr, MSR_TYPE_W);
4022 }
4023
4024 static int vmx_vm_has_apicv(struct kvm *kvm)
4025 {
4026         return enable_apicv && irqchip_in_kernel(kvm);
4027 }
4028
4029 /*
4030  * Send interrupt to vcpu via posted interrupt way.
4031  * 1. If target vcpu is running(non-root mode), send posted interrupt
4032  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4033  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4034  * interrupt from PIR in next vmentry.
4035  */
4036 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4037 {
4038         struct vcpu_vmx *vmx = to_vmx(vcpu);
4039         int r;
4040
4041         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4042                 return;
4043
4044         r = pi_test_and_set_on(&vmx->pi_desc);
4045         kvm_make_request(KVM_REQ_EVENT, vcpu);
4046 #ifdef CONFIG_SMP
4047         if (!r && (vcpu->mode == IN_GUEST_MODE))
4048                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4049                                 POSTED_INTR_VECTOR);
4050         else
4051 #endif
4052                 kvm_vcpu_kick(vcpu);
4053 }
4054
4055 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4056 {
4057         struct vcpu_vmx *vmx = to_vmx(vcpu);
4058
4059         if (!pi_test_and_clear_on(&vmx->pi_desc))
4060                 return;
4061
4062         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4063 }
4064
4065 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4066 {
4067         return;
4068 }
4069
4070 /*
4071  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4072  * will not change in the lifetime of the guest.
4073  * Note that host-state that does change is set elsewhere. E.g., host-state
4074  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4075  */
4076 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4077 {
4078         u32 low32, high32;
4079         unsigned long tmpl;
4080         struct desc_ptr dt;
4081
4082         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4083         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4084         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4085
4086         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4087 #ifdef CONFIG_X86_64
4088         /*
4089          * Load null selectors, so we can avoid reloading them in
4090          * __vmx_load_host_state(), in case userspace uses the null selectors
4091          * too (the expected case).
4092          */
4093         vmcs_write16(HOST_DS_SELECTOR, 0);
4094         vmcs_write16(HOST_ES_SELECTOR, 0);
4095 #else
4096         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4097         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4098 #endif
4099         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4100         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4101
4102         native_store_idt(&dt);
4103         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4104         vmx->host_idt_base = dt.address;
4105
4106         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4107
4108         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4109         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4110         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4111         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4112
4113         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4114                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4115                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4116         }
4117 }
4118
4119 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4120 {
4121         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4122         if (enable_ept)
4123                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4124         if (is_guest_mode(&vmx->vcpu))
4125                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4126                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4127         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4128 }
4129
4130 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4131 {
4132         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4133
4134         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4135                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4136         return pin_based_exec_ctrl;
4137 }
4138
4139 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4140 {
4141         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4142         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4143                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4144 #ifdef CONFIG_X86_64
4145                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4146                                 CPU_BASED_CR8_LOAD_EXITING;
4147 #endif
4148         }
4149         if (!enable_ept)
4150                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4151                                 CPU_BASED_CR3_LOAD_EXITING  |
4152                                 CPU_BASED_INVLPG_EXITING;
4153         return exec_control;
4154 }
4155
4156 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4157 {
4158         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4159         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4160                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4161         if (vmx->vpid == 0)
4162                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4163         if (!enable_ept) {
4164                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4165                 enable_unrestricted_guest = 0;
4166                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4167                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4168         }
4169         if (!enable_unrestricted_guest)
4170                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4171         if (!ple_gap)
4172                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4173         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4174                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4175                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4176         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4177         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4178            (handle_vmptrld).
4179            We can NOT enable shadow_vmcs here because we don't have yet
4180            a current VMCS12
4181         */
4182         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4183         return exec_control;
4184 }
4185
4186 static void ept_set_mmio_spte_mask(void)
4187 {
4188         /*
4189          * EPT Misconfigurations can be generated if the value of bits 2:0
4190          * of an EPT paging-structure entry is 110b (write/execute).
4191          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4192          * spte.
4193          */
4194         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4195 }
4196
4197 /*
4198  * Sets up the vmcs for emulated real mode.
4199  */
4200 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4201 {
4202 #ifdef CONFIG_X86_64
4203         unsigned long a;
4204 #endif
4205         int i;
4206
4207         /* I/O */
4208         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4209         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4210
4211         if (enable_shadow_vmcs) {
4212                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4213                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4214         }
4215         if (cpu_has_vmx_msr_bitmap())
4216                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4217
4218         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4219
4220         /* Control */
4221         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4222
4223         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4224
4225         if (cpu_has_secondary_exec_ctrls()) {
4226                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4227                                 vmx_secondary_exec_control(vmx));
4228         }
4229
4230         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4231                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4232                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4233                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4234                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4235
4236                 vmcs_write16(GUEST_INTR_STATUS, 0);
4237
4238                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4239                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4240         }
4241
4242         if (ple_gap) {
4243                 vmcs_write32(PLE_GAP, ple_gap);
4244                 vmcs_write32(PLE_WINDOW, ple_window);
4245         }
4246
4247         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4248         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4249         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4250
4251         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4252         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4253         vmx_set_constant_host_state(vmx);
4254 #ifdef CONFIG_X86_64
4255         rdmsrl(MSR_FS_BASE, a);
4256         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4257         rdmsrl(MSR_GS_BASE, a);
4258         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4259 #else
4260         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4261         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4262 #endif
4263
4264         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4265         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4266         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4267         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4268         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4269
4270         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4271                 u32 msr_low, msr_high;
4272                 u64 host_pat;
4273                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4274                 host_pat = msr_low | ((u64) msr_high << 32);
4275                 /* Write the default value follow host pat */
4276                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4277                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4278                 vmx->vcpu.arch.pat = host_pat;
4279         }
4280
4281         for (i = 0; i < NR_VMX_MSR; ++i) {
4282                 u32 index = vmx_msr_index[i];
4283                 u32 data_low, data_high;
4284                 int j = vmx->nmsrs;
4285
4286                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4287                         continue;
4288                 if (wrmsr_safe(index, data_low, data_high) < 0)
4289                         continue;
4290                 vmx->guest_msrs[j].index = i;
4291                 vmx->guest_msrs[j].data = 0;
4292                 vmx->guest_msrs[j].mask = -1ull;
4293                 ++vmx->nmsrs;
4294         }
4295
4296         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4297
4298         /* 22.2.1, 20.8.1 */
4299         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4300
4301         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4302         set_cr4_guest_host_mask(vmx);
4303
4304         return 0;
4305 }
4306
4307 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4308 {
4309         struct vcpu_vmx *vmx = to_vmx(vcpu);
4310         u64 msr;
4311
4312         vmx->rmode.vm86_active = 0;
4313
4314         vmx->soft_vnmi_blocked = 0;
4315
4316         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4317         kvm_set_cr8(&vmx->vcpu, 0);
4318         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4319         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4320                 msr |= MSR_IA32_APICBASE_BSP;
4321         kvm_set_apic_base(&vmx->vcpu, msr);
4322
4323         vmx_segment_cache_clear(vmx);
4324
4325         seg_setup(VCPU_SREG_CS);
4326         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4327         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4328
4329         seg_setup(VCPU_SREG_DS);
4330         seg_setup(VCPU_SREG_ES);
4331         seg_setup(VCPU_SREG_FS);
4332         seg_setup(VCPU_SREG_GS);
4333         seg_setup(VCPU_SREG_SS);
4334
4335         vmcs_write16(GUEST_TR_SELECTOR, 0);
4336         vmcs_writel(GUEST_TR_BASE, 0);
4337         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4338         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4339
4340         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4341         vmcs_writel(GUEST_LDTR_BASE, 0);
4342         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4343         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4344
4345         vmcs_write32(GUEST_SYSENTER_CS, 0);
4346         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4347         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4348
4349         vmcs_writel(GUEST_RFLAGS, 0x02);
4350         kvm_rip_write(vcpu, 0xfff0);
4351
4352         vmcs_writel(GUEST_GDTR_BASE, 0);
4353         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4354
4355         vmcs_writel(GUEST_IDTR_BASE, 0);
4356         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4357
4358         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4359         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4360         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4361
4362         /* Special registers */
4363         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4364
4365         setup_msrs(vmx);
4366
4367         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4368
4369         if (cpu_has_vmx_tpr_shadow()) {
4370                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4371                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4372                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4373                                      __pa(vmx->vcpu.arch.apic->regs));
4374                 vmcs_write32(TPR_THRESHOLD, 0);
4375         }
4376
4377         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4378                 vmcs_write64(APIC_ACCESS_ADDR,
4379                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4380
4381         if (vmx_vm_has_apicv(vcpu->kvm))
4382                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4383
4384         if (vmx->vpid != 0)
4385                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4386
4387         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4388         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4389         vmx_set_cr4(&vmx->vcpu, 0);
4390         vmx_set_efer(&vmx->vcpu, 0);
4391         vmx_fpu_activate(&vmx->vcpu);
4392         update_exception_bitmap(&vmx->vcpu);
4393
4394         vpid_sync_context(vmx);
4395 }
4396
4397 /*
4398  * In nested virtualization, check if L1 asked to exit on external interrupts.
4399  * For most existing hypervisors, this will always return true.
4400  */
4401 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4402 {
4403         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4404                 PIN_BASED_EXT_INTR_MASK;
4405 }
4406
4407 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4408 {
4409         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4410                 PIN_BASED_NMI_EXITING;
4411 }
4412
4413 static int enable_irq_window(struct kvm_vcpu *vcpu)
4414 {
4415         u32 cpu_based_vm_exec_control;
4416
4417         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4418                 /*
4419                  * We get here if vmx_interrupt_allowed() said we can't
4420                  * inject to L1 now because L2 must run. The caller will have
4421                  * to make L2 exit right after entry, so we can inject to L1
4422                  * more promptly.
4423                  */
4424                 return -EBUSY;
4425
4426         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4427         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4428         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4429         return 0;
4430 }
4431
4432 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4433 {
4434         u32 cpu_based_vm_exec_control;
4435
4436         if (!cpu_has_virtual_nmis())
4437                 return enable_irq_window(vcpu);
4438
4439         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4440                 return enable_irq_window(vcpu);
4441
4442         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4443         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4444         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4445         return 0;
4446 }
4447
4448 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4449 {
4450         struct vcpu_vmx *vmx = to_vmx(vcpu);
4451         uint32_t intr;
4452         int irq = vcpu->arch.interrupt.nr;
4453
4454         trace_kvm_inj_virq(irq);
4455
4456         ++vcpu->stat.irq_injections;
4457         if (vmx->rmode.vm86_active) {
4458                 int inc_eip = 0;
4459                 if (vcpu->arch.interrupt.soft)
4460                         inc_eip = vcpu->arch.event_exit_inst_len;
4461                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4462                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4463                 return;
4464         }
4465         intr = irq | INTR_INFO_VALID_MASK;
4466         if (vcpu->arch.interrupt.soft) {
4467                 intr |= INTR_TYPE_SOFT_INTR;
4468                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4469                              vmx->vcpu.arch.event_exit_inst_len);
4470         } else
4471                 intr |= INTR_TYPE_EXT_INTR;
4472         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4473 }
4474
4475 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4476 {
4477         struct vcpu_vmx *vmx = to_vmx(vcpu);
4478
4479         if (is_guest_mode(vcpu))
4480                 return;
4481
4482         if (!cpu_has_virtual_nmis()) {
4483                 /*
4484                  * Tracking the NMI-blocked state in software is built upon
4485                  * finding the next open IRQ window. This, in turn, depends on
4486                  * well-behaving guests: They have to keep IRQs disabled at
4487                  * least as long as the NMI handler runs. Otherwise we may
4488                  * cause NMI nesting, maybe breaking the guest. But as this is
4489                  * highly unlikely, we can live with the residual risk.
4490                  */
4491                 vmx->soft_vnmi_blocked = 1;
4492                 vmx->vnmi_blocked_time = 0;
4493         }
4494
4495         ++vcpu->stat.nmi_injections;
4496         vmx->nmi_known_unmasked = false;
4497         if (vmx->rmode.vm86_active) {
4498                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4499                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4500                 return;
4501         }
4502         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4503                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4504 }
4505
4506 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4507 {
4508         if (!cpu_has_virtual_nmis())
4509                 return to_vmx(vcpu)->soft_vnmi_blocked;
4510         if (to_vmx(vcpu)->nmi_known_unmasked)
4511                 return false;
4512         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4513 }
4514
4515 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4516 {
4517         struct vcpu_vmx *vmx = to_vmx(vcpu);
4518
4519         if (!cpu_has_virtual_nmis()) {
4520                 if (vmx->soft_vnmi_blocked != masked) {
4521                         vmx->soft_vnmi_blocked = masked;
4522                         vmx->vnmi_blocked_time = 0;
4523                 }
4524         } else {
4525                 vmx->nmi_known_unmasked = !masked;
4526                 if (masked)
4527                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4528                                       GUEST_INTR_STATE_NMI);
4529                 else
4530                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4531                                         GUEST_INTR_STATE_NMI);
4532         }
4533 }
4534
4535 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4536 {
4537         if (is_guest_mode(vcpu)) {
4538                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4539
4540                 if (to_vmx(vcpu)->nested.nested_run_pending)
4541                         return 0;
4542                 if (nested_exit_on_nmi(vcpu)) {
4543                         nested_vmx_vmexit(vcpu);
4544                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4545                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4546                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4547                         /*
4548                          * The NMI-triggered VM exit counts as injection:
4549                          * clear this one and block further NMIs.
4550                          */
4551                         vcpu->arch.nmi_pending = 0;
4552                         vmx_set_nmi_mask(vcpu, true);
4553                         return 0;
4554                 }
4555         }
4556
4557         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4558                 return 0;
4559
4560         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4561                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4562                    | GUEST_INTR_STATE_NMI));
4563 }
4564
4565 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4566 {
4567         if (is_guest_mode(vcpu)) {
4568                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4569
4570                 if (to_vmx(vcpu)->nested.nested_run_pending)
4571                         return 0;
4572                 if (nested_exit_on_intr(vcpu)) {
4573                         nested_vmx_vmexit(vcpu);
4574                         vmcs12->vm_exit_reason =
4575                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4576                         vmcs12->vm_exit_intr_info = 0;
4577                         /*
4578                          * fall through to normal code, but now in L1, not L2
4579                          */
4580                 }
4581         }
4582
4583         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4584                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4585                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4586 }
4587
4588 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4589 {
4590         int ret;
4591         struct kvm_userspace_memory_region tss_mem = {
4592                 .slot = TSS_PRIVATE_MEMSLOT,
4593                 .guest_phys_addr = addr,
4594                 .memory_size = PAGE_SIZE * 3,
4595                 .flags = 0,
4596         };
4597
4598         ret = kvm_set_memory_region(kvm, &tss_mem);
4599         if (ret)
4600                 return ret;
4601         kvm->arch.tss_addr = addr;
4602         if (!init_rmode_tss(kvm))
4603                 return  -ENOMEM;
4604
4605         return 0;
4606 }
4607
4608 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4609 {
4610         switch (vec) {
4611         case BP_VECTOR:
4612                 /*
4613                  * Update instruction length as we may reinject the exception
4614                  * from user space while in guest debugging mode.
4615                  */
4616                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4617                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4618                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4619                         return false;
4620                 /* fall through */
4621         case DB_VECTOR:
4622                 if (vcpu->guest_debug &
4623                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4624                         return false;
4625                 /* fall through */
4626         case DE_VECTOR:
4627         case OF_VECTOR:
4628         case BR_VECTOR:
4629         case UD_VECTOR:
4630         case DF_VECTOR:
4631         case SS_VECTOR:
4632         case GP_VECTOR:
4633         case MF_VECTOR:
4634                 return true;
4635         break;
4636         }
4637         return false;
4638 }
4639
4640 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4641                                   int vec, u32 err_code)
4642 {
4643         /*
4644          * Instruction with address size override prefix opcode 0x67
4645          * Cause the #SS fault with 0 error code in VM86 mode.
4646          */
4647         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4648                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4649                         if (vcpu->arch.halt_request) {
4650                                 vcpu->arch.halt_request = 0;
4651                                 return kvm_emulate_halt(vcpu);
4652                         }
4653                         return 1;
4654                 }
4655                 return 0;
4656         }
4657
4658         /*
4659          * Forward all other exceptions that are valid in real mode.
4660          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4661          *        the required debugging infrastructure rework.
4662          */
4663         kvm_queue_exception(vcpu, vec);
4664         return 1;
4665 }
4666
4667 /*
4668  * Trigger machine check on the host. We assume all the MSRs are already set up
4669  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4670  * We pass a fake environment to the machine check handler because we want
4671  * the guest to be always treated like user space, no matter what context
4672  * it used internally.
4673  */
4674 static void kvm_machine_check(void)
4675 {
4676 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4677         struct pt_regs regs = {
4678                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4679                 .flags = X86_EFLAGS_IF,
4680         };
4681
4682         do_machine_check(&regs, 0);
4683 #endif
4684 }
4685
4686 static int handle_machine_check(struct kvm_vcpu *vcpu)
4687 {
4688         /* already handled by vcpu_run */
4689         return 1;
4690 }
4691
4692 static int handle_exception(struct kvm_vcpu *vcpu)
4693 {
4694         struct vcpu_vmx *vmx = to_vmx(vcpu);
4695         struct kvm_run *kvm_run = vcpu->run;
4696         u32 intr_info, ex_no, error_code;
4697         unsigned long cr2, rip, dr6;
4698         u32 vect_info;
4699         enum emulation_result er;
4700
4701         vect_info = vmx->idt_vectoring_info;
4702         intr_info = vmx->exit_intr_info;
4703
4704         if (is_machine_check(intr_info))
4705                 return handle_machine_check(vcpu);
4706
4707         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4708                 return 1;  /* already handled by vmx_vcpu_run() */
4709
4710         if (is_no_device(intr_info)) {
4711                 vmx_fpu_activate(vcpu);
4712                 return 1;
4713         }
4714
4715         if (is_invalid_opcode(intr_info)) {
4716                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4717                 if (er != EMULATE_DONE)
4718                         kvm_queue_exception(vcpu, UD_VECTOR);
4719                 return 1;
4720         }
4721
4722         error_code = 0;
4723         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4724                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4725
4726         /*
4727          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4728          * MMIO, it is better to report an internal error.
4729          * See the comments in vmx_handle_exit.
4730          */
4731         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4732             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4733                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4734                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4735                 vcpu->run->internal.ndata = 2;
4736                 vcpu->run->internal.data[0] = vect_info;
4737                 vcpu->run->internal.data[1] = intr_info;
4738                 return 0;
4739         }
4740
4741         if (is_page_fault(intr_info)) {
4742                 /* EPT won't cause page fault directly */
4743                 BUG_ON(enable_ept);
4744                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4745                 trace_kvm_page_fault(cr2, error_code);
4746
4747                 if (kvm_event_needs_reinjection(vcpu))
4748                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4749                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4750         }
4751
4752         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4753
4754         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4755                 return handle_rmode_exception(vcpu, ex_no, error_code);
4756
4757         switch (ex_no) {
4758         case DB_VECTOR:
4759                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4760                 if (!(vcpu->guest_debug &
4761                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4762                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4763                         kvm_queue_exception(vcpu, DB_VECTOR);
4764                         return 1;
4765                 }
4766                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4767                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4768                 /* fall through */
4769         case BP_VECTOR:
4770                 /*
4771                  * Update instruction length as we may reinject #BP from
4772                  * user space while in guest debugging mode. Reading it for
4773                  * #DB as well causes no harm, it is not used in that case.
4774                  */
4775                 vmx->vcpu.arch.event_exit_inst_len =
4776                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4777                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4778                 rip = kvm_rip_read(vcpu);
4779                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4780                 kvm_run->debug.arch.exception = ex_no;
4781                 break;
4782         default:
4783                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4784                 kvm_run->ex.exception = ex_no;
4785                 kvm_run->ex.error_code = error_code;
4786                 break;
4787         }
4788         return 0;
4789 }
4790
4791 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4792 {
4793         ++vcpu->stat.irq_exits;
4794         return 1;
4795 }
4796
4797 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4798 {
4799         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4800         return 0;
4801 }
4802
4803 static int handle_io(struct kvm_vcpu *vcpu)
4804 {
4805         unsigned long exit_qualification;
4806         int size, in, string;
4807         unsigned port;
4808
4809         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4810         string = (exit_qualification & 16) != 0;
4811         in = (exit_qualification & 8) != 0;
4812
4813         ++vcpu->stat.io_exits;
4814
4815         if (string || in)
4816                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4817
4818         port = exit_qualification >> 16;
4819         size = (exit_qualification & 7) + 1;
4820         skip_emulated_instruction(vcpu);
4821
4822         return kvm_fast_pio_out(vcpu, size, port);
4823 }
4824
4825 static void
4826 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4827 {
4828         /*
4829          * Patch in the VMCALL instruction:
4830          */
4831         hypercall[0] = 0x0f;
4832         hypercall[1] = 0x01;
4833         hypercall[2] = 0xc1;
4834 }
4835
4836 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4837 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4838 {
4839         if (is_guest_mode(vcpu)) {
4840                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4841                 unsigned long orig_val = val;
4842
4843                 /*
4844                  * We get here when L2 changed cr0 in a way that did not change
4845                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4846                  * but did change L0 shadowed bits. So we first calculate the
4847                  * effective cr0 value that L1 would like to write into the
4848                  * hardware. It consists of the L2-owned bits from the new
4849                  * value combined with the L1-owned bits from L1's guest_cr0.
4850                  */
4851                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4852                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4853
4854                 /* TODO: will have to take unrestricted guest mode into
4855                  * account */
4856                 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4857                         return 1;
4858
4859                 if (kvm_set_cr0(vcpu, val))
4860                         return 1;
4861                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4862                 return 0;
4863         } else {
4864                 if (to_vmx(vcpu)->nested.vmxon &&
4865                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4866                         return 1;
4867                 return kvm_set_cr0(vcpu, val);
4868         }
4869 }
4870
4871 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4872 {
4873         if (is_guest_mode(vcpu)) {
4874                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4875                 unsigned long orig_val = val;
4876
4877                 /* analogously to handle_set_cr0 */
4878                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4879                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4880                 if (kvm_set_cr4(vcpu, val))
4881                         return 1;
4882                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4883                 return 0;
4884         } else
4885                 return kvm_set_cr4(vcpu, val);
4886 }
4887
4888 /* called to set cr0 as approriate for clts instruction exit. */
4889 static void handle_clts(struct kvm_vcpu *vcpu)
4890 {
4891         if (is_guest_mode(vcpu)) {
4892                 /*
4893                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4894                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4895                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4896                  */
4897                 vmcs_writel(CR0_READ_SHADOW,
4898                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4899                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4900         } else
4901                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4902 }
4903
4904 static int handle_cr(struct kvm_vcpu *vcpu)
4905 {
4906         unsigned long exit_qualification, val;
4907         int cr;
4908         int reg;
4909         int err;
4910
4911         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4912         cr = exit_qualification & 15;
4913         reg = (exit_qualification >> 8) & 15;
4914         switch ((exit_qualification >> 4) & 3) {
4915         case 0: /* mov to cr */
4916                 val = kvm_register_read(vcpu, reg);
4917                 trace_kvm_cr_write(cr, val);
4918                 switch (cr) {
4919                 case 0:
4920                         err = handle_set_cr0(vcpu, val);
4921                         kvm_complete_insn_gp(vcpu, err);
4922                         return 1;
4923                 case 3:
4924                         err = kvm_set_cr3(vcpu, val);
4925                         kvm_complete_insn_gp(vcpu, err);
4926                         return 1;
4927                 case 4:
4928                         err = handle_set_cr4(vcpu, val);
4929                         kvm_complete_insn_gp(vcpu, err);
4930                         return 1;
4931                 case 8: {
4932                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4933                                 u8 cr8 = kvm_register_read(vcpu, reg);
4934                                 err = kvm_set_cr8(vcpu, cr8);
4935                                 kvm_complete_insn_gp(vcpu, err);
4936                                 if (irqchip_in_kernel(vcpu->kvm))
4937                                         return 1;
4938                                 if (cr8_prev <= cr8)
4939                                         return 1;
4940                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4941                                 return 0;
4942                         }
4943                 }
4944                 break;
4945         case 2: /* clts */
4946                 handle_clts(vcpu);
4947                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4948                 skip_emulated_instruction(vcpu);
4949                 vmx_fpu_activate(vcpu);
4950                 return 1;
4951         case 1: /*mov from cr*/
4952                 switch (cr) {
4953                 case 3:
4954                         val = kvm_read_cr3(vcpu);
4955                         kvm_register_write(vcpu, reg, val);
4956                         trace_kvm_cr_read(cr, val);
4957                         skip_emulated_instruction(vcpu);
4958                         return 1;
4959                 case 8:
4960                         val = kvm_get_cr8(vcpu);
4961                         kvm_register_write(vcpu, reg, val);
4962                         trace_kvm_cr_read(cr, val);
4963                         skip_emulated_instruction(vcpu);
4964                         return 1;
4965                 }
4966                 break;
4967         case 3: /* lmsw */
4968                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4969                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4970                 kvm_lmsw(vcpu, val);
4971
4972                 skip_emulated_instruction(vcpu);
4973                 return 1;
4974         default:
4975                 break;
4976         }
4977         vcpu->run->exit_reason = 0;
4978         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4979                (int)(exit_qualification >> 4) & 3, cr);
4980         return 0;
4981 }
4982
4983 static int handle_dr(struct kvm_vcpu *vcpu)
4984 {
4985         unsigned long exit_qualification;
4986         int dr, reg;
4987
4988         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4989         if (!kvm_require_cpl(vcpu, 0))
4990                 return 1;
4991         dr = vmcs_readl(GUEST_DR7);
4992         if (dr & DR7_GD) {
4993                 /*
4994                  * As the vm-exit takes precedence over the debug trap, we
4995                  * need to emulate the latter, either for the host or the
4996                  * guest debugging itself.
4997                  */
4998                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4999                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5000                         vcpu->run->debug.arch.dr7 = dr;
5001                         vcpu->run->debug.arch.pc =
5002                                 vmcs_readl(GUEST_CS_BASE) +
5003                                 vmcs_readl(GUEST_RIP);
5004                         vcpu->run->debug.arch.exception = DB_VECTOR;
5005                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5006                         return 0;
5007                 } else {
5008                         vcpu->arch.dr7 &= ~DR7_GD;
5009                         vcpu->arch.dr6 |= DR6_BD;
5010                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5011                         kvm_queue_exception(vcpu, DB_VECTOR);
5012                         return 1;
5013                 }
5014         }
5015
5016         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5017         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5018         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5019         if (exit_qualification & TYPE_MOV_FROM_DR) {
5020                 unsigned long val;
5021                 if (!kvm_get_dr(vcpu, dr, &val))
5022                         kvm_register_write(vcpu, reg, val);
5023         } else
5024                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5025         skip_emulated_instruction(vcpu);
5026         return 1;
5027 }
5028
5029 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5030 {
5031         vmcs_writel(GUEST_DR7, val);
5032 }
5033
5034 static int handle_cpuid(struct kvm_vcpu *vcpu)
5035 {
5036         kvm_emulate_cpuid(vcpu);
5037         return 1;
5038 }
5039
5040 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5041 {
5042         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5043         u64 data;
5044
5045         if (vmx_get_msr(vcpu, ecx, &data)) {
5046                 trace_kvm_msr_read_ex(ecx);
5047                 kvm_inject_gp(vcpu, 0);
5048                 return 1;
5049         }
5050
5051         trace_kvm_msr_read(ecx, data);
5052
5053         /* FIXME: handling of bits 32:63 of rax, rdx */
5054         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5055         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5056         skip_emulated_instruction(vcpu);
5057         return 1;
5058 }
5059
5060 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5061 {
5062         struct msr_data msr;
5063         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5064         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5065                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5066
5067         msr.data = data;
5068         msr.index = ecx;
5069         msr.host_initiated = false;
5070         if (vmx_set_msr(vcpu, &msr) != 0) {
5071                 trace_kvm_msr_write_ex(ecx, data);
5072                 kvm_inject_gp(vcpu, 0);
5073                 return 1;
5074         }
5075
5076         trace_kvm_msr_write(ecx, data);
5077         skip_emulated_instruction(vcpu);
5078         return 1;
5079 }
5080
5081 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5082 {
5083         kvm_make_request(KVM_REQ_EVENT, vcpu);
5084         return 1;
5085 }
5086
5087 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5088 {
5089         u32 cpu_based_vm_exec_control;
5090
5091         /* clear pending irq */
5092         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5093         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5094         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5095
5096         kvm_make_request(KVM_REQ_EVENT, vcpu);
5097
5098         ++vcpu->stat.irq_window_exits;
5099
5100         /*
5101          * If the user space waits to inject interrupts, exit as soon as
5102          * possible
5103          */
5104         if (!irqchip_in_kernel(vcpu->kvm) &&
5105             vcpu->run->request_interrupt_window &&
5106             !kvm_cpu_has_interrupt(vcpu)) {
5107                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5108                 return 0;
5109         }
5110         return 1;
5111 }
5112
5113 static int handle_halt(struct kvm_vcpu *vcpu)
5114 {
5115         skip_emulated_instruction(vcpu);
5116         return kvm_emulate_halt(vcpu);
5117 }
5118
5119 static int handle_vmcall(struct kvm_vcpu *vcpu)
5120 {
5121         skip_emulated_instruction(vcpu);
5122         kvm_emulate_hypercall(vcpu);
5123         return 1;
5124 }
5125
5126 static int handle_invd(struct kvm_vcpu *vcpu)
5127 {
5128         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5129 }
5130
5131 static int handle_invlpg(struct kvm_vcpu *vcpu)
5132 {
5133         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5134
5135         kvm_mmu_invlpg(vcpu, exit_qualification);
5136         skip_emulated_instruction(vcpu);
5137         return 1;
5138 }
5139
5140 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5141 {
5142         int err;
5143
5144         err = kvm_rdpmc(vcpu);
5145         kvm_complete_insn_gp(vcpu, err);
5146
5147         return 1;
5148 }
5149
5150 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5151 {
5152         skip_emulated_instruction(vcpu);
5153         kvm_emulate_wbinvd(vcpu);
5154         return 1;
5155 }
5156
5157 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5158 {
5159         u64 new_bv = kvm_read_edx_eax(vcpu);
5160         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5161
5162         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5163                 skip_emulated_instruction(vcpu);
5164         return 1;
5165 }
5166
5167 static int handle_apic_access(struct kvm_vcpu *vcpu)
5168 {
5169         if (likely(fasteoi)) {
5170                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5171                 int access_type, offset;
5172
5173                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5174                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5175                 /*
5176                  * Sane guest uses MOV to write EOI, with written value
5177                  * not cared. So make a short-circuit here by avoiding
5178                  * heavy instruction emulation.
5179                  */
5180                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5181                     (offset == APIC_EOI)) {
5182                         kvm_lapic_set_eoi(vcpu);
5183                         skip_emulated_instruction(vcpu);
5184                         return 1;
5185                 }
5186         }
5187         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5188 }
5189
5190 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5191 {
5192         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5193         int vector = exit_qualification & 0xff;
5194
5195         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5196         kvm_apic_set_eoi_accelerated(vcpu, vector);
5197         return 1;
5198 }
5199
5200 static int handle_apic_write(struct kvm_vcpu *vcpu)
5201 {
5202         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5203         u32 offset = exit_qualification & 0xfff;
5204
5205         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5206         kvm_apic_write_nodecode(vcpu, offset);
5207         return 1;
5208 }
5209
5210 static int handle_task_switch(struct kvm_vcpu *vcpu)
5211 {
5212         struct vcpu_vmx *vmx = to_vmx(vcpu);
5213         unsigned long exit_qualification;
5214         bool has_error_code = false;
5215         u32 error_code = 0;
5216         u16 tss_selector;
5217         int reason, type, idt_v, idt_index;
5218
5219         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5220         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5221         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5222
5223         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5224
5225         reason = (u32)exit_qualification >> 30;
5226         if (reason == TASK_SWITCH_GATE && idt_v) {
5227                 switch (type) {
5228                 case INTR_TYPE_NMI_INTR:
5229                         vcpu->arch.nmi_injected = false;
5230                         vmx_set_nmi_mask(vcpu, true);
5231                         break;
5232                 case INTR_TYPE_EXT_INTR:
5233                 case INTR_TYPE_SOFT_INTR:
5234                         kvm_clear_interrupt_queue(vcpu);
5235                         break;
5236                 case INTR_TYPE_HARD_EXCEPTION:
5237                         if (vmx->idt_vectoring_info &
5238                             VECTORING_INFO_DELIVER_CODE_MASK) {
5239                                 has_error_code = true;
5240                                 error_code =
5241                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5242                         }
5243                         /* fall through */
5244                 case INTR_TYPE_SOFT_EXCEPTION:
5245                         kvm_clear_exception_queue(vcpu);
5246                         break;
5247                 default:
5248                         break;
5249                 }
5250         }
5251         tss_selector = exit_qualification;
5252
5253         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5254                        type != INTR_TYPE_EXT_INTR &&
5255                        type != INTR_TYPE_NMI_INTR))
5256                 skip_emulated_instruction(vcpu);
5257
5258         if (kvm_task_switch(vcpu, tss_selector,
5259                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5260                             has_error_code, error_code) == EMULATE_FAIL) {
5261                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5262                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5263                 vcpu->run->internal.ndata = 0;
5264                 return 0;
5265         }
5266
5267         /* clear all local breakpoint enable flags */
5268         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5269
5270         /*
5271          * TODO: What about debug traps on tss switch?
5272          *       Are we supposed to inject them and update dr6?
5273          */
5274
5275         return 1;
5276 }
5277
5278 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5279 {
5280         unsigned long exit_qualification;
5281         gpa_t gpa;
5282         u32 error_code;
5283         int gla_validity;
5284
5285         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5286
5287         gla_validity = (exit_qualification >> 7) & 0x3;
5288         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5289                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5290                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5291                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5292                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5293                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5294                         (long unsigned int)exit_qualification);
5295                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5296                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5297                 return 0;
5298         }
5299
5300         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5301         trace_kvm_page_fault(gpa, exit_qualification);
5302
5303         /* It is a write fault? */
5304         error_code = exit_qualification & (1U << 1);
5305         /* ept page table is present? */
5306         error_code |= (exit_qualification >> 3) & 0x1;
5307
5308         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5309 }
5310
5311 static u64 ept_rsvd_mask(u64 spte, int level)
5312 {
5313         int i;
5314         u64 mask = 0;
5315
5316         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5317                 mask |= (1ULL << i);
5318
5319         if (level > 2)
5320                 /* bits 7:3 reserved */
5321                 mask |= 0xf8;
5322         else if (level == 2) {
5323                 if (spte & (1ULL << 7))
5324                         /* 2MB ref, bits 20:12 reserved */
5325                         mask |= 0x1ff000;
5326                 else
5327                         /* bits 6:3 reserved */
5328                         mask |= 0x78;
5329         }
5330
5331         return mask;
5332 }
5333
5334 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5335                                        int level)
5336 {
5337         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5338
5339         /* 010b (write-only) */
5340         WARN_ON((spte & 0x7) == 0x2);
5341
5342         /* 110b (write/execute) */
5343         WARN_ON((spte & 0x7) == 0x6);
5344
5345         /* 100b (execute-only) and value not supported by logical processor */
5346         if (!cpu_has_vmx_ept_execute_only())
5347                 WARN_ON((spte & 0x7) == 0x4);
5348
5349         /* not 000b */
5350         if ((spte & 0x7)) {
5351                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5352
5353                 if (rsvd_bits != 0) {
5354                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5355                                          __func__, rsvd_bits);
5356                         WARN_ON(1);
5357                 }
5358
5359                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5360                         u64 ept_mem_type = (spte & 0x38) >> 3;
5361
5362                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5363                             ept_mem_type == 7) {
5364                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5365                                                 __func__, ept_mem_type);
5366                                 WARN_ON(1);
5367                         }
5368                 }
5369         }
5370 }
5371
5372 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5373 {
5374         u64 sptes[4];
5375         int nr_sptes, i, ret;
5376         gpa_t gpa;
5377
5378         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5379
5380         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5381         if (likely(ret == RET_MMIO_PF_EMULATE))
5382                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5383                                               EMULATE_DONE;
5384
5385         if (unlikely(ret == RET_MMIO_PF_INVALID))
5386                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5387
5388         if (unlikely(ret == RET_MMIO_PF_RETRY))
5389                 return 1;
5390
5391         /* It is the real ept misconfig */
5392         printk(KERN_ERR "EPT: Misconfiguration.\n");
5393         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5394
5395         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5396
5397         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5398                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5399
5400         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5401         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5402
5403         return 0;
5404 }
5405
5406 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5407 {
5408         u32 cpu_based_vm_exec_control;
5409
5410         /* clear pending NMI */
5411         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5412         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5413         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5414         ++vcpu->stat.nmi_window_exits;
5415         kvm_make_request(KVM_REQ_EVENT, vcpu);
5416
5417         return 1;
5418 }
5419
5420 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5421 {
5422         struct vcpu_vmx *vmx = to_vmx(vcpu);
5423         enum emulation_result err = EMULATE_DONE;
5424         int ret = 1;
5425         u32 cpu_exec_ctrl;
5426         bool intr_window_requested;
5427         unsigned count = 130;
5428
5429         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5430         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5431
5432         while (!guest_state_valid(vcpu) && count-- != 0) {
5433                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5434                         return handle_interrupt_window(&vmx->vcpu);
5435
5436                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5437                         return 1;
5438
5439                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5440
5441                 if (err == EMULATE_DO_MMIO) {
5442                         ret = 0;
5443                         goto out;
5444                 }
5445
5446                 if (err != EMULATE_DONE) {
5447                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5448                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5449                         vcpu->run->internal.ndata = 0;
5450                         return 0;
5451                 }
5452
5453                 if (vcpu->arch.halt_request) {
5454                         vcpu->arch.halt_request = 0;
5455                         ret = kvm_emulate_halt(vcpu);
5456                         goto out;
5457                 }
5458
5459                 if (signal_pending(current))
5460                         goto out;
5461                 if (need_resched())
5462                         schedule();
5463         }
5464
5465         vmx->emulation_required = emulation_required(vcpu);
5466 out:
5467         return ret;
5468 }
5469
5470 /*
5471  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5472  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5473  */
5474 static int handle_pause(struct kvm_vcpu *vcpu)
5475 {
5476         skip_emulated_instruction(vcpu);
5477         kvm_vcpu_on_spin(vcpu);
5478
5479         return 1;
5480 }
5481
5482 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5483 {
5484         kvm_queue_exception(vcpu, UD_VECTOR);
5485         return 1;
5486 }
5487
5488 /*
5489  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5490  * We could reuse a single VMCS for all the L2 guests, but we also want the
5491  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5492  * allows keeping them loaded on the processor, and in the future will allow
5493  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5494  * every entry if they never change.
5495  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5496  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5497  *
5498  * The following functions allocate and free a vmcs02 in this pool.
5499  */
5500
5501 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5502 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5503 {
5504         struct vmcs02_list *item;
5505         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5506                 if (item->vmptr == vmx->nested.current_vmptr) {
5507                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5508                         return &item->vmcs02;
5509                 }
5510
5511         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5512                 /* Recycle the least recently used VMCS. */
5513                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5514                         struct vmcs02_list, list);
5515                 item->vmptr = vmx->nested.current_vmptr;
5516                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5517                 return &item->vmcs02;
5518         }
5519
5520         /* Create a new VMCS */
5521         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5522         if (!item)
5523                 return NULL;
5524         item->vmcs02.vmcs = alloc_vmcs();
5525         if (!item->vmcs02.vmcs) {
5526                 kfree(item);
5527                 return NULL;
5528         }
5529         loaded_vmcs_init(&item->vmcs02);
5530         item->vmptr = vmx->nested.current_vmptr;
5531         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5532         vmx->nested.vmcs02_num++;
5533         return &item->vmcs02;
5534 }
5535
5536 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5537 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5538 {
5539         struct vmcs02_list *item;
5540         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5541                 if (item->vmptr == vmptr) {
5542                         free_loaded_vmcs(&item->vmcs02);
5543                         list_del(&item->list);
5544                         kfree(item);
5545                         vmx->nested.vmcs02_num--;
5546                         return;
5547                 }
5548 }
5549
5550 /*
5551  * Free all VMCSs saved for this vcpu, except the one pointed by
5552  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5553  * currently used, if running L2), and vmcs01 when running L2.
5554  */
5555 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5556 {
5557         struct vmcs02_list *item, *n;
5558         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5559                 if (vmx->loaded_vmcs != &item->vmcs02)
5560                         free_loaded_vmcs(&item->vmcs02);
5561                 list_del(&item->list);
5562                 kfree(item);
5563         }
5564         vmx->nested.vmcs02_num = 0;
5565
5566         if (vmx->loaded_vmcs != &vmx->vmcs01)
5567                 free_loaded_vmcs(&vmx->vmcs01);
5568 }
5569
5570 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5571                                  u32 vm_instruction_error);
5572
5573 /*
5574  * Emulate the VMXON instruction.
5575  * Currently, we just remember that VMX is active, and do not save or even
5576  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5577  * do not currently need to store anything in that guest-allocated memory
5578  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5579  * argument is different from the VMXON pointer (which the spec says they do).
5580  */
5581 static int handle_vmon(struct kvm_vcpu *vcpu)
5582 {
5583         struct kvm_segment cs;
5584         struct vcpu_vmx *vmx = to_vmx(vcpu);
5585         struct vmcs *shadow_vmcs;
5586
5587         /* The Intel VMX Instruction Reference lists a bunch of bits that
5588          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5589          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5590          * Otherwise, we should fail with #UD. We test these now:
5591          */
5592         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5593             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5594             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5595                 kvm_queue_exception(vcpu, UD_VECTOR);
5596                 return 1;
5597         }
5598
5599         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5600         if (is_long_mode(vcpu) && !cs.l) {
5601                 kvm_queue_exception(vcpu, UD_VECTOR);
5602                 return 1;
5603         }
5604
5605         if (vmx_get_cpl(vcpu)) {
5606                 kvm_inject_gp(vcpu, 0);
5607                 return 1;
5608         }
5609         if (vmx->nested.vmxon) {
5610                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5611                 skip_emulated_instruction(vcpu);
5612                 return 1;
5613         }
5614         if (enable_shadow_vmcs) {
5615                 shadow_vmcs = alloc_vmcs();
5616                 if (!shadow_vmcs)
5617                         return -ENOMEM;
5618                 /* mark vmcs as shadow */
5619                 shadow_vmcs->revision_id |= (1u << 31);
5620                 /* init shadow vmcs */
5621                 vmcs_clear(shadow_vmcs);
5622                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5623         }
5624
5625         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5626         vmx->nested.vmcs02_num = 0;
5627
5628         vmx->nested.vmxon = true;
5629
5630         skip_emulated_instruction(vcpu);
5631         return 1;
5632 }
5633
5634 /*
5635  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5636  * for running VMX instructions (except VMXON, whose prerequisites are
5637  * slightly different). It also specifies what exception to inject otherwise.
5638  */
5639 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5640 {
5641         struct kvm_segment cs;
5642         struct vcpu_vmx *vmx = to_vmx(vcpu);
5643
5644         if (!vmx->nested.vmxon) {
5645                 kvm_queue_exception(vcpu, UD_VECTOR);
5646                 return 0;
5647         }
5648
5649         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5650         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5651             (is_long_mode(vcpu) && !cs.l)) {
5652                 kvm_queue_exception(vcpu, UD_VECTOR);
5653                 return 0;
5654         }
5655
5656         if (vmx_get_cpl(vcpu)) {
5657                 kvm_inject_gp(vcpu, 0);
5658                 return 0;
5659         }
5660
5661         return 1;
5662 }
5663
5664 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5665 {
5666         u32 exec_control;
5667         if (enable_shadow_vmcs) {
5668                 if (vmx->nested.current_vmcs12 != NULL) {
5669                         /* copy to memory all shadowed fields in case
5670                            they were modified */
5671                         copy_shadow_to_vmcs12(vmx);
5672                         vmx->nested.sync_shadow_vmcs = false;
5673                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5674                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5675                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5676                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5677                 }
5678         }
5679         kunmap(vmx->nested.current_vmcs12_page);
5680         nested_release_page(vmx->nested.current_vmcs12_page);
5681 }
5682
5683 /*
5684  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5685  * just stops using VMX.
5686  */
5687 static void free_nested(struct vcpu_vmx *vmx)
5688 {
5689         if (!vmx->nested.vmxon)
5690                 return;
5691         vmx->nested.vmxon = false;
5692         if (vmx->nested.current_vmptr != -1ull) {
5693                 nested_release_vmcs12(vmx);
5694                 vmx->nested.current_vmptr = -1ull;
5695                 vmx->nested.current_vmcs12 = NULL;
5696         }
5697         if (enable_shadow_vmcs)
5698                 free_vmcs(vmx->nested.current_shadow_vmcs);
5699         /* Unpin physical memory we referred to in current vmcs02 */
5700         if (vmx->nested.apic_access_page) {
5701                 nested_release_page(vmx->nested.apic_access_page);
5702                 vmx->nested.apic_access_page = 0;
5703         }
5704
5705         nested_free_all_saved_vmcss(vmx);
5706 }
5707
5708 /* Emulate the VMXOFF instruction */
5709 static int handle_vmoff(struct kvm_vcpu *vcpu)
5710 {
5711         if (!nested_vmx_check_permission(vcpu))
5712                 return 1;
5713         free_nested(to_vmx(vcpu));
5714         skip_emulated_instruction(vcpu);
5715         return 1;
5716 }
5717
5718 /*
5719  * Decode the memory-address operand of a vmx instruction, as recorded on an
5720  * exit caused by such an instruction (run by a guest hypervisor).
5721  * On success, returns 0. When the operand is invalid, returns 1 and throws
5722  * #UD or #GP.
5723  */
5724 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5725                                  unsigned long exit_qualification,
5726                                  u32 vmx_instruction_info, gva_t *ret)
5727 {
5728         /*
5729          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5730          * Execution", on an exit, vmx_instruction_info holds most of the
5731          * addressing components of the operand. Only the displacement part
5732          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5733          * For how an actual address is calculated from all these components,
5734          * refer to Vol. 1, "Operand Addressing".
5735          */
5736         int  scaling = vmx_instruction_info & 3;
5737         int  addr_size = (vmx_instruction_info >> 7) & 7;
5738         bool is_reg = vmx_instruction_info & (1u << 10);
5739         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5740         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5741         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5742         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5743         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5744
5745         if (is_reg) {
5746                 kvm_queue_exception(vcpu, UD_VECTOR);
5747                 return 1;
5748         }
5749
5750         /* Addr = segment_base + offset */
5751         /* offset = base + [index * scale] + displacement */
5752         *ret = vmx_get_segment_base(vcpu, seg_reg);
5753         if (base_is_valid)
5754                 *ret += kvm_register_read(vcpu, base_reg);
5755         if (index_is_valid)
5756                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5757         *ret += exit_qualification; /* holds the displacement */
5758
5759         if (addr_size == 1) /* 32 bit */
5760                 *ret &= 0xffffffff;
5761
5762         /*
5763          * TODO: throw #GP (and return 1) in various cases that the VM*
5764          * instructions require it - e.g., offset beyond segment limit,
5765          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5766          * address, and so on. Currently these are not checked.
5767          */
5768         return 0;
5769 }
5770
5771 /*
5772  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5773  * set the success or error code of an emulated VMX instruction, as specified
5774  * by Vol 2B, VMX Instruction Reference, "Conventions".
5775  */
5776 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5777 {
5778         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5779                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5780                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5781 }
5782
5783 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5784 {
5785         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5786                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5787                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5788                         | X86_EFLAGS_CF);
5789 }
5790
5791 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5792                                         u32 vm_instruction_error)
5793 {
5794         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5795                 /*
5796                  * failValid writes the error number to the current VMCS, which
5797                  * can't be done there isn't a current VMCS.
5798                  */
5799                 nested_vmx_failInvalid(vcpu);
5800                 return;
5801         }
5802         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5803                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5804                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5805                         | X86_EFLAGS_ZF);
5806         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5807         /*
5808          * We don't need to force a shadow sync because
5809          * VM_INSTRUCTION_ERROR is not shadowed
5810          */
5811 }
5812
5813 /* Emulate the VMCLEAR instruction */
5814 static int handle_vmclear(struct kvm_vcpu *vcpu)
5815 {
5816         struct vcpu_vmx *vmx = to_vmx(vcpu);
5817         gva_t gva;
5818         gpa_t vmptr;
5819         struct vmcs12 *vmcs12;
5820         struct page *page;
5821         struct x86_exception e;
5822
5823         if (!nested_vmx_check_permission(vcpu))
5824                 return 1;
5825
5826         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5827                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5828                 return 1;
5829
5830         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5831                                 sizeof(vmptr), &e)) {
5832                 kvm_inject_page_fault(vcpu, &e);
5833                 return 1;
5834         }
5835
5836         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5837                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5838                 skip_emulated_instruction(vcpu);
5839                 return 1;
5840         }
5841
5842         if (vmptr == vmx->nested.current_vmptr) {
5843                 nested_release_vmcs12(vmx);
5844                 vmx->nested.current_vmptr = -1ull;
5845                 vmx->nested.current_vmcs12 = NULL;
5846         }
5847
5848         page = nested_get_page(vcpu, vmptr);
5849         if (page == NULL) {
5850                 /*
5851                  * For accurate processor emulation, VMCLEAR beyond available
5852                  * physical memory should do nothing at all. However, it is
5853                  * possible that a nested vmx bug, not a guest hypervisor bug,
5854                  * resulted in this case, so let's shut down before doing any
5855                  * more damage:
5856                  */
5857                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5858                 return 1;
5859         }
5860         vmcs12 = kmap(page);
5861         vmcs12->launch_state = 0;
5862         kunmap(page);
5863         nested_release_page(page);
5864
5865         nested_free_vmcs02(vmx, vmptr);
5866
5867         skip_emulated_instruction(vcpu);
5868         nested_vmx_succeed(vcpu);
5869         return 1;
5870 }
5871
5872 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5873
5874 /* Emulate the VMLAUNCH instruction */
5875 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5876 {
5877         return nested_vmx_run(vcpu, true);
5878 }
5879
5880 /* Emulate the VMRESUME instruction */
5881 static int handle_vmresume(struct kvm_vcpu *vcpu)
5882 {
5883
5884         return nested_vmx_run(vcpu, false);
5885 }
5886
5887 enum vmcs_field_type {
5888         VMCS_FIELD_TYPE_U16 = 0,
5889         VMCS_FIELD_TYPE_U64 = 1,
5890         VMCS_FIELD_TYPE_U32 = 2,
5891         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5892 };
5893
5894 static inline int vmcs_field_type(unsigned long field)
5895 {
5896         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5897                 return VMCS_FIELD_TYPE_U32;
5898         return (field >> 13) & 0x3 ;
5899 }
5900
5901 static inline int vmcs_field_readonly(unsigned long field)
5902 {
5903         return (((field >> 10) & 0x3) == 1);
5904 }
5905
5906 /*
5907  * Read a vmcs12 field. Since these can have varying lengths and we return
5908  * one type, we chose the biggest type (u64) and zero-extend the return value
5909  * to that size. Note that the caller, handle_vmread, might need to use only
5910  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5911  * 64-bit fields are to be returned).
5912  */
5913 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5914                                         unsigned long field, u64 *ret)
5915 {
5916         short offset = vmcs_field_to_offset(field);
5917         char *p;
5918
5919         if (offset < 0)
5920                 return 0;
5921
5922         p = ((char *)(get_vmcs12(vcpu))) + offset;
5923
5924         switch (vmcs_field_type(field)) {
5925         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5926                 *ret = *((natural_width *)p);
5927                 return 1;
5928         case VMCS_FIELD_TYPE_U16:
5929                 *ret = *((u16 *)p);
5930                 return 1;
5931         case VMCS_FIELD_TYPE_U32:
5932                 *ret = *((u32 *)p);
5933                 return 1;
5934         case VMCS_FIELD_TYPE_U64:
5935                 *ret = *((u64 *)p);
5936                 return 1;
5937         default:
5938                 return 0; /* can never happen. */
5939         }
5940 }
5941
5942
5943 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5944                                     unsigned long field, u64 field_value){
5945         short offset = vmcs_field_to_offset(field);
5946         char *p = ((char *) get_vmcs12(vcpu)) + offset;
5947         if (offset < 0)
5948                 return false;
5949
5950         switch (vmcs_field_type(field)) {
5951         case VMCS_FIELD_TYPE_U16:
5952                 *(u16 *)p = field_value;
5953                 return true;
5954         case VMCS_FIELD_TYPE_U32:
5955                 *(u32 *)p = field_value;
5956                 return true;
5957         case VMCS_FIELD_TYPE_U64:
5958                 *(u64 *)p = field_value;
5959                 return true;
5960         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5961                 *(natural_width *)p = field_value;
5962                 return true;
5963         default:
5964                 return false; /* can never happen. */
5965         }
5966
5967 }
5968
5969 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5970 {
5971         int i;
5972         unsigned long field;
5973         u64 field_value;
5974         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5975         unsigned long *fields = (unsigned long *)shadow_read_write_fields;
5976         int num_fields = max_shadow_read_write_fields;
5977
5978         vmcs_load(shadow_vmcs);
5979
5980         for (i = 0; i < num_fields; i++) {
5981                 field = fields[i];
5982                 switch (vmcs_field_type(field)) {
5983                 case VMCS_FIELD_TYPE_U16:
5984                         field_value = vmcs_read16(field);
5985                         break;
5986                 case VMCS_FIELD_TYPE_U32:
5987                         field_value = vmcs_read32(field);
5988                         break;
5989                 case VMCS_FIELD_TYPE_U64:
5990                         field_value = vmcs_read64(field);
5991                         break;
5992                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5993                         field_value = vmcs_readl(field);
5994                         break;
5995                 }
5996                 vmcs12_write_any(&vmx->vcpu, field, field_value);
5997         }
5998
5999         vmcs_clear(shadow_vmcs);
6000         vmcs_load(vmx->loaded_vmcs->vmcs);
6001 }
6002
6003 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6004 {
6005         unsigned long *fields[] = {
6006                 (unsigned long *)shadow_read_write_fields,
6007                 (unsigned long *)shadow_read_only_fields
6008         };
6009         int num_lists =  ARRAY_SIZE(fields);
6010         int max_fields[] = {
6011                 max_shadow_read_write_fields,
6012                 max_shadow_read_only_fields
6013         };
6014         int i, q;
6015         unsigned long field;
6016         u64 field_value = 0;
6017         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6018
6019         vmcs_load(shadow_vmcs);
6020
6021         for (q = 0; q < num_lists; q++) {
6022                 for (i = 0; i < max_fields[q]; i++) {
6023                         field = fields[q][i];
6024                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6025
6026                         switch (vmcs_field_type(field)) {
6027                         case VMCS_FIELD_TYPE_U16:
6028                                 vmcs_write16(field, (u16)field_value);
6029                                 break;
6030                         case VMCS_FIELD_TYPE_U32:
6031                                 vmcs_write32(field, (u32)field_value);
6032                                 break;
6033                         case VMCS_FIELD_TYPE_U64:
6034                                 vmcs_write64(field, (u64)field_value);
6035                                 break;
6036                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6037                                 vmcs_writel(field, (long)field_value);
6038                                 break;
6039                         }
6040                 }
6041         }
6042
6043         vmcs_clear(shadow_vmcs);
6044         vmcs_load(vmx->loaded_vmcs->vmcs);
6045 }
6046
6047 /*
6048  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6049  * used before) all generate the same failure when it is missing.
6050  */
6051 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6052 {
6053         struct vcpu_vmx *vmx = to_vmx(vcpu);
6054         if (vmx->nested.current_vmptr == -1ull) {
6055                 nested_vmx_failInvalid(vcpu);
6056                 skip_emulated_instruction(vcpu);
6057                 return 0;
6058         }
6059         return 1;
6060 }
6061
6062 static int handle_vmread(struct kvm_vcpu *vcpu)
6063 {
6064         unsigned long field;
6065         u64 field_value;
6066         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6067         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6068         gva_t gva = 0;
6069
6070         if (!nested_vmx_check_permission(vcpu) ||
6071             !nested_vmx_check_vmcs12(vcpu))
6072                 return 1;
6073
6074         /* Decode instruction info and find the field to read */
6075         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6076         /* Read the field, zero-extended to a u64 field_value */
6077         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6078                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6079                 skip_emulated_instruction(vcpu);
6080                 return 1;
6081         }
6082         /*
6083          * Now copy part of this value to register or memory, as requested.
6084          * Note that the number of bits actually copied is 32 or 64 depending
6085          * on the guest's mode (32 or 64 bit), not on the given field's length.
6086          */
6087         if (vmx_instruction_info & (1u << 10)) {
6088                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6089                         field_value);
6090         } else {
6091                 if (get_vmx_mem_address(vcpu, exit_qualification,
6092                                 vmx_instruction_info, &gva))
6093                         return 1;
6094                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6095                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6096                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6097         }
6098
6099         nested_vmx_succeed(vcpu);
6100         skip_emulated_instruction(vcpu);
6101         return 1;
6102 }
6103
6104
6105 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6106 {
6107         unsigned long field;
6108         gva_t gva;
6109         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6110         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6111         /* The value to write might be 32 or 64 bits, depending on L1's long
6112          * mode, and eventually we need to write that into a field of several
6113          * possible lengths. The code below first zero-extends the value to 64
6114          * bit (field_value), and then copies only the approriate number of
6115          * bits into the vmcs12 field.
6116          */
6117         u64 field_value = 0;
6118         struct x86_exception e;
6119
6120         if (!nested_vmx_check_permission(vcpu) ||
6121             !nested_vmx_check_vmcs12(vcpu))
6122                 return 1;
6123
6124         if (vmx_instruction_info & (1u << 10))
6125                 field_value = kvm_register_read(vcpu,
6126                         (((vmx_instruction_info) >> 3) & 0xf));
6127         else {
6128                 if (get_vmx_mem_address(vcpu, exit_qualification,
6129                                 vmx_instruction_info, &gva))
6130                         return 1;
6131                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6132                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6133                         kvm_inject_page_fault(vcpu, &e);
6134                         return 1;
6135                 }
6136         }
6137
6138
6139         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6140         if (vmcs_field_readonly(field)) {
6141                 nested_vmx_failValid(vcpu,
6142                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6143                 skip_emulated_instruction(vcpu);
6144                 return 1;
6145         }
6146
6147         if (!vmcs12_write_any(vcpu, field, field_value)) {
6148                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6149                 skip_emulated_instruction(vcpu);
6150                 return 1;
6151         }
6152
6153         nested_vmx_succeed(vcpu);
6154         skip_emulated_instruction(vcpu);
6155         return 1;
6156 }
6157
6158 /* Emulate the VMPTRLD instruction */
6159 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6160 {
6161         struct vcpu_vmx *vmx = to_vmx(vcpu);
6162         gva_t gva;
6163         gpa_t vmptr;
6164         struct x86_exception e;
6165         u32 exec_control;
6166
6167         if (!nested_vmx_check_permission(vcpu))
6168                 return 1;
6169
6170         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6171                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6172                 return 1;
6173
6174         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6175                                 sizeof(vmptr), &e)) {
6176                 kvm_inject_page_fault(vcpu, &e);
6177                 return 1;
6178         }
6179
6180         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6181                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6182                 skip_emulated_instruction(vcpu);
6183                 return 1;
6184         }
6185
6186         if (vmx->nested.current_vmptr != vmptr) {
6187                 struct vmcs12 *new_vmcs12;
6188                 struct page *page;
6189                 page = nested_get_page(vcpu, vmptr);
6190                 if (page == NULL) {
6191                         nested_vmx_failInvalid(vcpu);
6192                         skip_emulated_instruction(vcpu);
6193                         return 1;
6194                 }
6195                 new_vmcs12 = kmap(page);
6196                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6197                         kunmap(page);
6198                         nested_release_page_clean(page);
6199                         nested_vmx_failValid(vcpu,
6200                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6201                         skip_emulated_instruction(vcpu);
6202                         return 1;
6203                 }
6204                 if (vmx->nested.current_vmptr != -1ull)
6205                         nested_release_vmcs12(vmx);
6206
6207                 vmx->nested.current_vmptr = vmptr;
6208                 vmx->nested.current_vmcs12 = new_vmcs12;
6209                 vmx->nested.current_vmcs12_page = page;
6210                 if (enable_shadow_vmcs) {
6211                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6212                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6213                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6214                         vmcs_write64(VMCS_LINK_POINTER,
6215                                      __pa(vmx->nested.current_shadow_vmcs));
6216                         vmx->nested.sync_shadow_vmcs = true;
6217                 }
6218         }
6219
6220         nested_vmx_succeed(vcpu);
6221         skip_emulated_instruction(vcpu);
6222         return 1;
6223 }
6224
6225 /* Emulate the VMPTRST instruction */
6226 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6227 {
6228         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6229         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6230         gva_t vmcs_gva;
6231         struct x86_exception e;
6232
6233         if (!nested_vmx_check_permission(vcpu))
6234                 return 1;
6235
6236         if (get_vmx_mem_address(vcpu, exit_qualification,
6237                         vmx_instruction_info, &vmcs_gva))
6238                 return 1;
6239         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6240         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6241                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6242                                  sizeof(u64), &e)) {
6243                 kvm_inject_page_fault(vcpu, &e);
6244                 return 1;
6245         }
6246         nested_vmx_succeed(vcpu);
6247         skip_emulated_instruction(vcpu);
6248         return 1;
6249 }
6250
6251 /*
6252  * The exit handlers return 1 if the exit was handled fully and guest execution
6253  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6254  * to be done to userspace and return 0.
6255  */
6256 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6257         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6258         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6259         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6260         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6261         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6262         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6263         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6264         [EXIT_REASON_CPUID]                   = handle_cpuid,
6265         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6266         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6267         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6268         [EXIT_REASON_HLT]                     = handle_halt,
6269         [EXIT_REASON_INVD]                    = handle_invd,
6270         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6271         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6272         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6273         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6274         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6275         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6276         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6277         [EXIT_REASON_VMREAD]                  = handle_vmread,
6278         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6279         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6280         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6281         [EXIT_REASON_VMON]                    = handle_vmon,
6282         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6283         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6284         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6285         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6286         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6287         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6288         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6289         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6290         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6291         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6292         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6293         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6294         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6295 };
6296
6297 static const int kvm_vmx_max_exit_handlers =
6298         ARRAY_SIZE(kvm_vmx_exit_handlers);
6299
6300 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6301                                        struct vmcs12 *vmcs12)
6302 {
6303         unsigned long exit_qualification;
6304         gpa_t bitmap, last_bitmap;
6305         unsigned int port;
6306         int size;
6307         u8 b;
6308
6309         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6310                 return 1;
6311
6312         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6313                 return 0;
6314
6315         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6316
6317         port = exit_qualification >> 16;
6318         size = (exit_qualification & 7) + 1;
6319
6320         last_bitmap = (gpa_t)-1;
6321         b = -1;
6322
6323         while (size > 0) {
6324                 if (port < 0x8000)
6325                         bitmap = vmcs12->io_bitmap_a;
6326                 else if (port < 0x10000)
6327                         bitmap = vmcs12->io_bitmap_b;
6328                 else
6329                         return 1;
6330                 bitmap += (port & 0x7fff) / 8;
6331
6332                 if (last_bitmap != bitmap)
6333                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6334                                 return 1;
6335                 if (b & (1 << (port & 7)))
6336                         return 1;
6337
6338                 port++;
6339                 size--;
6340                 last_bitmap = bitmap;
6341         }
6342
6343         return 0;
6344 }
6345
6346 /*
6347  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6348  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6349  * disinterest in the current event (read or write a specific MSR) by using an
6350  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6351  */
6352 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6353         struct vmcs12 *vmcs12, u32 exit_reason)
6354 {
6355         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6356         gpa_t bitmap;
6357
6358         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6359                 return 1;
6360
6361         /*
6362          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6363          * for the four combinations of read/write and low/high MSR numbers.
6364          * First we need to figure out which of the four to use:
6365          */
6366         bitmap = vmcs12->msr_bitmap;
6367         if (exit_reason == EXIT_REASON_MSR_WRITE)
6368                 bitmap += 2048;
6369         if (msr_index >= 0xc0000000) {
6370                 msr_index -= 0xc0000000;
6371                 bitmap += 1024;
6372         }
6373
6374         /* Then read the msr_index'th bit from this bitmap: */
6375         if (msr_index < 1024*8) {
6376                 unsigned char b;
6377                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6378                         return 1;
6379                 return 1 & (b >> (msr_index & 7));
6380         } else
6381                 return 1; /* let L1 handle the wrong parameter */
6382 }
6383
6384 /*
6385  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6386  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6387  * intercept (via guest_host_mask etc.) the current event.
6388  */
6389 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6390         struct vmcs12 *vmcs12)
6391 {
6392         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6393         int cr = exit_qualification & 15;
6394         int reg = (exit_qualification >> 8) & 15;
6395         unsigned long val = kvm_register_read(vcpu, reg);
6396
6397         switch ((exit_qualification >> 4) & 3) {
6398         case 0: /* mov to cr */
6399                 switch (cr) {
6400                 case 0:
6401                         if (vmcs12->cr0_guest_host_mask &
6402                             (val ^ vmcs12->cr0_read_shadow))
6403                                 return 1;
6404                         break;
6405                 case 3:
6406                         if ((vmcs12->cr3_target_count >= 1 &&
6407                                         vmcs12->cr3_target_value0 == val) ||
6408                                 (vmcs12->cr3_target_count >= 2 &&
6409                                         vmcs12->cr3_target_value1 == val) ||
6410                                 (vmcs12->cr3_target_count >= 3 &&
6411                                         vmcs12->cr3_target_value2 == val) ||
6412                                 (vmcs12->cr3_target_count >= 4 &&
6413                                         vmcs12->cr3_target_value3 == val))
6414                                 return 0;
6415                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6416                                 return 1;
6417                         break;
6418                 case 4:
6419                         if (vmcs12->cr4_guest_host_mask &
6420                             (vmcs12->cr4_read_shadow ^ val))
6421                                 return 1;
6422                         break;
6423                 case 8:
6424                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6425                                 return 1;
6426                         break;
6427                 }
6428                 break;
6429         case 2: /* clts */
6430                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6431                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6432                         return 1;
6433                 break;
6434         case 1: /* mov from cr */
6435                 switch (cr) {
6436                 case 3:
6437                         if (vmcs12->cpu_based_vm_exec_control &
6438                             CPU_BASED_CR3_STORE_EXITING)
6439                                 return 1;
6440                         break;
6441                 case 8:
6442                         if (vmcs12->cpu_based_vm_exec_control &
6443                             CPU_BASED_CR8_STORE_EXITING)
6444                                 return 1;
6445                         break;
6446                 }
6447                 break;
6448         case 3: /* lmsw */
6449                 /*
6450                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6451                  * cr0. Other attempted changes are ignored, with no exit.
6452                  */
6453                 if (vmcs12->cr0_guest_host_mask & 0xe &
6454                     (val ^ vmcs12->cr0_read_shadow))
6455                         return 1;
6456                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6457                     !(vmcs12->cr0_read_shadow & 0x1) &&
6458                     (val & 0x1))
6459                         return 1;
6460                 break;
6461         }
6462         return 0;
6463 }
6464
6465 /*
6466  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6467  * should handle it ourselves in L0 (and then continue L2). Only call this
6468  * when in is_guest_mode (L2).
6469  */
6470 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6471 {
6472         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6473         struct vcpu_vmx *vmx = to_vmx(vcpu);
6474         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6475         u32 exit_reason = vmx->exit_reason;
6476
6477         if (vmx->nested.nested_run_pending)
6478                 return 0;
6479
6480         if (unlikely(vmx->fail)) {
6481                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6482                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6483                 return 1;
6484         }
6485
6486         switch (exit_reason) {
6487         case EXIT_REASON_EXCEPTION_NMI:
6488                 if (!is_exception(intr_info))
6489                         return 0;
6490                 else if (is_page_fault(intr_info))
6491                         return enable_ept;
6492                 return vmcs12->exception_bitmap &
6493                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6494         case EXIT_REASON_EXTERNAL_INTERRUPT:
6495                 return 0;
6496         case EXIT_REASON_TRIPLE_FAULT:
6497                 return 1;
6498         case EXIT_REASON_PENDING_INTERRUPT:
6499                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6500         case EXIT_REASON_NMI_WINDOW:
6501                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6502         case EXIT_REASON_TASK_SWITCH:
6503                 return 1;
6504         case EXIT_REASON_CPUID:
6505                 return 1;
6506         case EXIT_REASON_HLT:
6507                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6508         case EXIT_REASON_INVD:
6509                 return 1;
6510         case EXIT_REASON_INVLPG:
6511                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6512         case EXIT_REASON_RDPMC:
6513                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6514         case EXIT_REASON_RDTSC:
6515                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6516         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6517         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6518         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6519         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6520         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6521                 /*
6522                  * VMX instructions trap unconditionally. This allows L1 to
6523                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6524                  */
6525                 return 1;
6526         case EXIT_REASON_CR_ACCESS:
6527                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6528         case EXIT_REASON_DR_ACCESS:
6529                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6530         case EXIT_REASON_IO_INSTRUCTION:
6531                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6532         case EXIT_REASON_MSR_READ:
6533         case EXIT_REASON_MSR_WRITE:
6534                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6535         case EXIT_REASON_INVALID_STATE:
6536                 return 1;
6537         case EXIT_REASON_MWAIT_INSTRUCTION:
6538                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6539         case EXIT_REASON_MONITOR_INSTRUCTION:
6540                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6541         case EXIT_REASON_PAUSE_INSTRUCTION:
6542                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6543                         nested_cpu_has2(vmcs12,
6544                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6545         case EXIT_REASON_MCE_DURING_VMENTRY:
6546                 return 0;
6547         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6548                 return 1;
6549         case EXIT_REASON_APIC_ACCESS:
6550                 return nested_cpu_has2(vmcs12,
6551                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6552         case EXIT_REASON_EPT_VIOLATION:
6553         case EXIT_REASON_EPT_MISCONFIG:
6554                 return 0;
6555         case EXIT_REASON_PREEMPTION_TIMER:
6556                 return vmcs12->pin_based_vm_exec_control &
6557                         PIN_BASED_VMX_PREEMPTION_TIMER;
6558         case EXIT_REASON_WBINVD:
6559                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6560         case EXIT_REASON_XSETBV:
6561                 return 1;
6562         default:
6563                 return 1;
6564         }
6565 }
6566
6567 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6568 {
6569         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6570         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6571 }
6572
6573 /*
6574  * The guest has exited.  See if we can fix it or if we need userspace
6575  * assistance.
6576  */
6577 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6578 {
6579         struct vcpu_vmx *vmx = to_vmx(vcpu);
6580         u32 exit_reason = vmx->exit_reason;
6581         u32 vectoring_info = vmx->idt_vectoring_info;
6582
6583         /* If guest state is invalid, start emulating */
6584         if (vmx->emulation_required)
6585                 return handle_invalid_guest_state(vcpu);
6586
6587         /*
6588          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6589          * we did not inject a still-pending event to L1 now because of
6590          * nested_run_pending, we need to re-enable this bit.
6591          */
6592         if (vmx->nested.nested_run_pending)
6593                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6594
6595         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6596             exit_reason == EXIT_REASON_VMRESUME))
6597                 vmx->nested.nested_run_pending = 1;
6598         else
6599                 vmx->nested.nested_run_pending = 0;
6600
6601         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6602                 nested_vmx_vmexit(vcpu);
6603                 return 1;
6604         }
6605
6606         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6607                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6608                 vcpu->run->fail_entry.hardware_entry_failure_reason
6609                         = exit_reason;
6610                 return 0;
6611         }
6612
6613         if (unlikely(vmx->fail)) {
6614                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6615                 vcpu->run->fail_entry.hardware_entry_failure_reason
6616                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6617                 return 0;
6618         }
6619
6620         /*
6621          * Note:
6622          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6623          * delivery event since it indicates guest is accessing MMIO.
6624          * The vm-exit can be triggered again after return to guest that
6625          * will cause infinite loop.
6626          */
6627         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6628                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6629                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6630                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6631                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6632                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6633                 vcpu->run->internal.ndata = 2;
6634                 vcpu->run->internal.data[0] = vectoring_info;
6635                 vcpu->run->internal.data[1] = exit_reason;
6636                 return 0;
6637         }
6638
6639         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6640             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6641                                         get_vmcs12(vcpu), vcpu)))) {
6642                 if (vmx_interrupt_allowed(vcpu)) {
6643                         vmx->soft_vnmi_blocked = 0;
6644                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6645                            vcpu->arch.nmi_pending) {
6646                         /*
6647                          * This CPU don't support us in finding the end of an
6648                          * NMI-blocked window if the guest runs with IRQs
6649                          * disabled. So we pull the trigger after 1 s of
6650                          * futile waiting, but inform the user about this.
6651                          */
6652                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6653                                "state on VCPU %d after 1 s timeout\n",
6654                                __func__, vcpu->vcpu_id);
6655                         vmx->soft_vnmi_blocked = 0;
6656                 }
6657         }
6658
6659         if (exit_reason < kvm_vmx_max_exit_handlers
6660             && kvm_vmx_exit_handlers[exit_reason])
6661                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6662         else {
6663                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6664                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6665         }
6666         return 0;
6667 }
6668
6669 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6670 {
6671         if (irr == -1 || tpr < irr) {
6672                 vmcs_write32(TPR_THRESHOLD, 0);
6673                 return;
6674         }
6675
6676         vmcs_write32(TPR_THRESHOLD, irr);
6677 }
6678
6679 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6680 {
6681         u32 sec_exec_control;
6682
6683         /*
6684          * There is not point to enable virtualize x2apic without enable
6685          * apicv
6686          */
6687         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6688                                 !vmx_vm_has_apicv(vcpu->kvm))
6689                 return;
6690
6691         if (!vm_need_tpr_shadow(vcpu->kvm))
6692                 return;
6693
6694         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6695
6696         if (set) {
6697                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6698                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6699         } else {
6700                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6701                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6702         }
6703         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6704
6705         vmx_set_msr_bitmap(vcpu);
6706 }
6707
6708 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6709 {
6710         u16 status;
6711         u8 old;
6712
6713         if (!vmx_vm_has_apicv(kvm))
6714                 return;
6715
6716         if (isr == -1)
6717                 isr = 0;
6718
6719         status = vmcs_read16(GUEST_INTR_STATUS);
6720         old = status >> 8;
6721         if (isr != old) {
6722                 status &= 0xff;
6723                 status |= isr << 8;
6724                 vmcs_write16(GUEST_INTR_STATUS, status);
6725         }
6726 }
6727
6728 static void vmx_set_rvi(int vector)
6729 {
6730         u16 status;
6731         u8 old;
6732
6733         status = vmcs_read16(GUEST_INTR_STATUS);
6734         old = (u8)status & 0xff;
6735         if ((u8)vector != old) {
6736                 status &= ~0xff;
6737                 status |= (u8)vector;
6738                 vmcs_write16(GUEST_INTR_STATUS, status);
6739         }
6740 }
6741
6742 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6743 {
6744         if (max_irr == -1)
6745                 return;
6746
6747         vmx_set_rvi(max_irr);
6748 }
6749
6750 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6751 {
6752         if (!vmx_vm_has_apicv(vcpu->kvm))
6753                 return;
6754
6755         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6756         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6757         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6758         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6759 }
6760
6761 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6762 {
6763         u32 exit_intr_info;
6764
6765         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6766               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6767                 return;
6768
6769         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6770         exit_intr_info = vmx->exit_intr_info;
6771
6772         /* Handle machine checks before interrupts are enabled */
6773         if (is_machine_check(exit_intr_info))
6774                 kvm_machine_check();
6775
6776         /* We need to handle NMIs before interrupts are enabled */
6777         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6778             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6779                 kvm_before_handle_nmi(&vmx->vcpu);
6780                 asm("int $2");
6781                 kvm_after_handle_nmi(&vmx->vcpu);
6782         }
6783 }
6784
6785 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6786 {
6787         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6788
6789         /*
6790          * If external interrupt exists, IF bit is set in rflags/eflags on the
6791          * interrupt stack frame, and interrupt will be enabled on a return
6792          * from interrupt handler.
6793          */
6794         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6795                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6796                 unsigned int vector;
6797                 unsigned long entry;
6798                 gate_desc *desc;
6799                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6800 #ifdef CONFIG_X86_64
6801                 unsigned long tmp;
6802 #endif
6803
6804                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6805                 desc = (gate_desc *)vmx->host_idt_base + vector;
6806                 entry = gate_offset(*desc);
6807                 asm volatile(
6808 #ifdef CONFIG_X86_64
6809                         "mov %%" _ASM_SP ", %[sp]\n\t"
6810                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6811                         "push $%c[ss]\n\t"
6812                         "push %[sp]\n\t"
6813 #endif
6814                         "pushf\n\t"
6815                         "orl $0x200, (%%" _ASM_SP ")\n\t"
6816                         __ASM_SIZE(push) " $%c[cs]\n\t"
6817                         "call *%[entry]\n\t"
6818                         :
6819 #ifdef CONFIG_X86_64
6820                         [sp]"=&r"(tmp)
6821 #endif
6822                         :
6823                         [entry]"r"(entry),
6824                         [ss]"i"(__KERNEL_DS),
6825                         [cs]"i"(__KERNEL_CS)
6826                         );
6827         } else
6828                 local_irq_enable();
6829 }
6830
6831 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6832 {
6833         u32 exit_intr_info;
6834         bool unblock_nmi;
6835         u8 vector;
6836         bool idtv_info_valid;
6837
6838         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6839
6840         if (cpu_has_virtual_nmis()) {
6841                 if (vmx->nmi_known_unmasked)
6842                         return;
6843                 /*
6844                  * Can't use vmx->exit_intr_info since we're not sure what
6845                  * the exit reason is.
6846                  */
6847                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6848                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6849                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6850                 /*
6851                  * SDM 3: 27.7.1.2 (September 2008)
6852                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6853                  * a guest IRET fault.
6854                  * SDM 3: 23.2.2 (September 2008)
6855                  * Bit 12 is undefined in any of the following cases:
6856                  *  If the VM exit sets the valid bit in the IDT-vectoring
6857                  *   information field.
6858                  *  If the VM exit is due to a double fault.
6859                  */
6860                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6861                     vector != DF_VECTOR && !idtv_info_valid)
6862                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6863                                       GUEST_INTR_STATE_NMI);
6864                 else
6865                         vmx->nmi_known_unmasked =
6866                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6867                                   & GUEST_INTR_STATE_NMI);
6868         } else if (unlikely(vmx->soft_vnmi_blocked))
6869                 vmx->vnmi_blocked_time +=
6870                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6871 }
6872
6873 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6874                                       u32 idt_vectoring_info,
6875                                       int instr_len_field,
6876                                       int error_code_field)
6877 {
6878         u8 vector;
6879         int type;
6880         bool idtv_info_valid;
6881
6882         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6883
6884         vcpu->arch.nmi_injected = false;
6885         kvm_clear_exception_queue(vcpu);
6886         kvm_clear_interrupt_queue(vcpu);
6887
6888         if (!idtv_info_valid)
6889                 return;
6890
6891         kvm_make_request(KVM_REQ_EVENT, vcpu);
6892
6893         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6894         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6895
6896         switch (type) {
6897         case INTR_TYPE_NMI_INTR:
6898                 vcpu->arch.nmi_injected = true;
6899                 /*
6900                  * SDM 3: 27.7.1.2 (September 2008)
6901                  * Clear bit "block by NMI" before VM entry if a NMI
6902                  * delivery faulted.
6903                  */
6904                 vmx_set_nmi_mask(vcpu, false);
6905                 break;
6906         case INTR_TYPE_SOFT_EXCEPTION:
6907                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6908                 /* fall through */
6909         case INTR_TYPE_HARD_EXCEPTION:
6910                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6911                         u32 err = vmcs_read32(error_code_field);
6912                         kvm_queue_exception_e(vcpu, vector, err);
6913                 } else
6914                         kvm_queue_exception(vcpu, vector);
6915                 break;
6916         case INTR_TYPE_SOFT_INTR:
6917                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6918                 /* fall through */
6919         case INTR_TYPE_EXT_INTR:
6920                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6921                 break;
6922         default:
6923                 break;
6924         }
6925 }
6926
6927 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6928 {
6929         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6930                                   VM_EXIT_INSTRUCTION_LEN,
6931                                   IDT_VECTORING_ERROR_CODE);
6932 }
6933
6934 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6935 {
6936         __vmx_complete_interrupts(vcpu,
6937                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6938                                   VM_ENTRY_INSTRUCTION_LEN,
6939                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6940
6941         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6942 }
6943
6944 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6945 {
6946         int i, nr_msrs;
6947         struct perf_guest_switch_msr *msrs;
6948
6949         msrs = perf_guest_get_msrs(&nr_msrs);
6950
6951         if (!msrs)
6952                 return;
6953
6954         for (i = 0; i < nr_msrs; i++)
6955                 if (msrs[i].host == msrs[i].guest)
6956                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6957                 else
6958                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6959                                         msrs[i].host);
6960 }
6961
6962 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6963 {
6964         struct vcpu_vmx *vmx = to_vmx(vcpu);
6965         unsigned long debugctlmsr;
6966
6967         /* Record the guest's net vcpu time for enforced NMI injections. */
6968         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6969                 vmx->entry_time = ktime_get();
6970
6971         /* Don't enter VMX if guest state is invalid, let the exit handler
6972            start emulation until we arrive back to a valid state */
6973         if (vmx->emulation_required)
6974                 return;
6975
6976         if (vmx->nested.sync_shadow_vmcs) {
6977                 copy_vmcs12_to_shadow(vmx);
6978                 vmx->nested.sync_shadow_vmcs = false;
6979         }
6980
6981         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6982                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6983         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6984                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6985
6986         /* When single-stepping over STI and MOV SS, we must clear the
6987          * corresponding interruptibility bits in the guest state. Otherwise
6988          * vmentry fails as it then expects bit 14 (BS) in pending debug
6989          * exceptions being set, but that's not correct for the guest debugging
6990          * case. */
6991         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6992                 vmx_set_interrupt_shadow(vcpu, 0);
6993
6994         atomic_switch_perf_msrs(vmx);
6995         debugctlmsr = get_debugctlmsr();
6996
6997         vmx->__launched = vmx->loaded_vmcs->launched;
6998         asm(
6999                 /* Store host registers */
7000                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7001                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7002                 "push %%" _ASM_CX " \n\t"
7003                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7004                 "je 1f \n\t"
7005                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7006                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7007                 "1: \n\t"
7008                 /* Reload cr2 if changed */
7009                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7010                 "mov %%cr2, %%" _ASM_DX " \n\t"
7011                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7012                 "je 2f \n\t"
7013                 "mov %%" _ASM_AX", %%cr2 \n\t"
7014                 "2: \n\t"
7015                 /* Check if vmlaunch of vmresume is needed */
7016                 "cmpl $0, %c[launched](%0) \n\t"
7017                 /* Load guest registers.  Don't clobber flags. */
7018                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7019                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7020                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7021                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7022                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7023                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7024 #ifdef CONFIG_X86_64
7025                 "mov %c[r8](%0),  %%r8  \n\t"
7026                 "mov %c[r9](%0),  %%r9  \n\t"
7027                 "mov %c[r10](%0), %%r10 \n\t"
7028                 "mov %c[r11](%0), %%r11 \n\t"
7029                 "mov %c[r12](%0), %%r12 \n\t"
7030                 "mov %c[r13](%0), %%r13 \n\t"
7031                 "mov %c[r14](%0), %%r14 \n\t"
7032                 "mov %c[r15](%0), %%r15 \n\t"
7033 #endif
7034                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7035
7036                 /* Enter guest mode */
7037                 "jne 1f \n\t"
7038                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7039                 "jmp 2f \n\t"
7040                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7041                 "2: "
7042                 /* Save guest registers, load host registers, keep flags */
7043                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7044                 "pop %0 \n\t"
7045                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7046                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7047                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7048                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7049                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7050                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7051                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7052 #ifdef CONFIG_X86_64
7053                 "mov %%r8,  %c[r8](%0) \n\t"
7054                 "mov %%r9,  %c[r9](%0) \n\t"
7055                 "mov %%r10, %c[r10](%0) \n\t"
7056                 "mov %%r11, %c[r11](%0) \n\t"
7057                 "mov %%r12, %c[r12](%0) \n\t"
7058                 "mov %%r13, %c[r13](%0) \n\t"
7059                 "mov %%r14, %c[r14](%0) \n\t"
7060                 "mov %%r15, %c[r15](%0) \n\t"
7061 #endif
7062                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7063                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7064
7065                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7066                 "setbe %c[fail](%0) \n\t"
7067                 ".pushsection .rodata \n\t"
7068                 ".global vmx_return \n\t"
7069                 "vmx_return: " _ASM_PTR " 2b \n\t"
7070                 ".popsection"
7071               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7072                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7073                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7074                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7075                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7076                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7077                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7078                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7079                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7080                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7081                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7082 #ifdef CONFIG_X86_64
7083                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7084                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7085                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7086                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7087                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7088                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7089                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7090                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7091 #endif
7092                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7093                 [wordsize]"i"(sizeof(ulong))
7094               : "cc", "memory"
7095 #ifdef CONFIG_X86_64
7096                 , "rax", "rbx", "rdi", "rsi"
7097                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7098 #else
7099                 , "eax", "ebx", "edi", "esi"
7100 #endif
7101               );
7102
7103         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7104         if (debugctlmsr)
7105                 update_debugctlmsr(debugctlmsr);
7106
7107 #ifndef CONFIG_X86_64
7108         /*
7109          * The sysexit path does not restore ds/es, so we must set them to
7110          * a reasonable value ourselves.
7111          *
7112          * We can't defer this to vmx_load_host_state() since that function
7113          * may be executed in interrupt context, which saves and restore segments
7114          * around it, nullifying its effect.
7115          */
7116         loadsegment(ds, __USER_DS);
7117         loadsegment(es, __USER_DS);
7118 #endif
7119
7120         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7121                                   | (1 << VCPU_EXREG_RFLAGS)
7122                                   | (1 << VCPU_EXREG_CPL)
7123                                   | (1 << VCPU_EXREG_PDPTR)
7124                                   | (1 << VCPU_EXREG_SEGMENTS)
7125                                   | (1 << VCPU_EXREG_CR3));
7126         vcpu->arch.regs_dirty = 0;
7127
7128         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7129
7130         vmx->loaded_vmcs->launched = 1;
7131
7132         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7133         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7134
7135         vmx_complete_atomic_exit(vmx);
7136         vmx_recover_nmi_blocking(vmx);
7137         vmx_complete_interrupts(vmx);
7138 }
7139
7140 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7141 {
7142         struct vcpu_vmx *vmx = to_vmx(vcpu);
7143
7144         free_vpid(vmx);
7145         free_nested(vmx);
7146         free_loaded_vmcs(vmx->loaded_vmcs);
7147         kfree(vmx->guest_msrs);
7148         kvm_vcpu_uninit(vcpu);
7149         kmem_cache_free(kvm_vcpu_cache, vmx);
7150 }
7151
7152 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7153 {
7154         int err;
7155         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7156         int cpu;
7157
7158         if (!vmx)
7159                 return ERR_PTR(-ENOMEM);
7160
7161         allocate_vpid(vmx);
7162
7163         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7164         if (err)
7165                 goto free_vcpu;
7166
7167         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7168         err = -ENOMEM;
7169         if (!vmx->guest_msrs) {
7170                 goto uninit_vcpu;
7171         }
7172
7173         vmx->loaded_vmcs = &vmx->vmcs01;
7174         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7175         if (!vmx->loaded_vmcs->vmcs)
7176                 goto free_msrs;
7177         if (!vmm_exclusive)
7178                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7179         loaded_vmcs_init(vmx->loaded_vmcs);
7180         if (!vmm_exclusive)
7181                 kvm_cpu_vmxoff();
7182
7183         cpu = get_cpu();
7184         vmx_vcpu_load(&vmx->vcpu, cpu);
7185         vmx->vcpu.cpu = cpu;
7186         err = vmx_vcpu_setup(vmx);
7187         vmx_vcpu_put(&vmx->vcpu);
7188         put_cpu();
7189         if (err)
7190                 goto free_vmcs;
7191         if (vm_need_virtualize_apic_accesses(kvm)) {
7192                 err = alloc_apic_access_page(kvm);
7193                 if (err)
7194                         goto free_vmcs;
7195         }
7196
7197         if (enable_ept) {
7198                 if (!kvm->arch.ept_identity_map_addr)
7199                         kvm->arch.ept_identity_map_addr =
7200                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7201                 err = -ENOMEM;
7202                 if (alloc_identity_pagetable(kvm) != 0)
7203                         goto free_vmcs;
7204                 if (!init_rmode_identity_map(kvm))
7205                         goto free_vmcs;
7206         }
7207
7208         vmx->nested.current_vmptr = -1ull;
7209         vmx->nested.current_vmcs12 = NULL;
7210
7211         return &vmx->vcpu;
7212
7213 free_vmcs:
7214         free_loaded_vmcs(vmx->loaded_vmcs);
7215 free_msrs:
7216         kfree(vmx->guest_msrs);
7217 uninit_vcpu:
7218         kvm_vcpu_uninit(&vmx->vcpu);
7219 free_vcpu:
7220         free_vpid(vmx);
7221         kmem_cache_free(kvm_vcpu_cache, vmx);
7222         return ERR_PTR(err);
7223 }
7224
7225 static void __init vmx_check_processor_compat(void *rtn)
7226 {
7227         struct vmcs_config vmcs_conf;
7228
7229         *(int *)rtn = 0;
7230         if (setup_vmcs_config(&vmcs_conf) < 0)
7231                 *(int *)rtn = -EIO;
7232         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7233                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7234                                 smp_processor_id());
7235                 *(int *)rtn = -EIO;
7236         }
7237 }
7238
7239 static int get_ept_level(void)
7240 {
7241         return VMX_EPT_DEFAULT_GAW + 1;
7242 }
7243
7244 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7245 {
7246         u64 ret;
7247
7248         /* For VT-d and EPT combination
7249          * 1. MMIO: always map as UC
7250          * 2. EPT with VT-d:
7251          *   a. VT-d without snooping control feature: can't guarantee the
7252          *      result, try to trust guest.
7253          *   b. VT-d with snooping control feature: snooping control feature of
7254          *      VT-d engine can guarantee the cache correctness. Just set it
7255          *      to WB to keep consistent with host. So the same as item 3.
7256          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7257          *    consistent with host MTRR
7258          */
7259         if (is_mmio)
7260                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7261         else if (vcpu->kvm->arch.iommu_domain &&
7262                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7263                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7264                       VMX_EPT_MT_EPTE_SHIFT;
7265         else
7266                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7267                         | VMX_EPT_IPAT_BIT;
7268
7269         return ret;
7270 }
7271
7272 static int vmx_get_lpage_level(void)
7273 {
7274         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7275                 return PT_DIRECTORY_LEVEL;
7276         else
7277                 /* For shadow and EPT supported 1GB page */
7278                 return PT_PDPE_LEVEL;
7279 }
7280
7281 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7282 {
7283         struct kvm_cpuid_entry2 *best;
7284         struct vcpu_vmx *vmx = to_vmx(vcpu);
7285         u32 exec_control;
7286
7287         vmx->rdtscp_enabled = false;
7288         if (vmx_rdtscp_supported()) {
7289                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7290                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7291                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7292                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7293                                 vmx->rdtscp_enabled = true;
7294                         else {
7295                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7296                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7297                                                 exec_control);
7298                         }
7299                 }
7300         }
7301
7302         /* Exposing INVPCID only when PCID is exposed */
7303         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7304         if (vmx_invpcid_supported() &&
7305             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7306             guest_cpuid_has_pcid(vcpu)) {
7307                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7308                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7309                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7310                              exec_control);
7311         } else {
7312                 if (cpu_has_secondary_exec_ctrls()) {
7313                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7314                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7315                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7316                                      exec_control);
7317                 }
7318                 if (best)
7319                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7320         }
7321 }
7322
7323 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7324 {
7325         if (func == 1 && nested)
7326                 entry->ecx |= bit(X86_FEATURE_VMX);
7327 }
7328
7329 /*
7330  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7331  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7332  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7333  * guest in a way that will both be appropriate to L1's requests, and our
7334  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7335  * function also has additional necessary side-effects, like setting various
7336  * vcpu->arch fields.
7337  */
7338 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7339 {
7340         struct vcpu_vmx *vmx = to_vmx(vcpu);
7341         u32 exec_control;
7342
7343         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7344         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7345         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7346         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7347         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7348         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7349         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7350         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7351         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7352         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7353         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7354         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7355         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7356         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7357         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7358         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7359         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7360         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7361         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7362         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7363         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7364         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7365         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7366         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7367         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7368         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7369         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7370         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7371         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7372         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7373         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7374         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7375         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7376         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7377         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7378         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7379
7380         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7381         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7382                 vmcs12->vm_entry_intr_info_field);
7383         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7384                 vmcs12->vm_entry_exception_error_code);
7385         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7386                 vmcs12->vm_entry_instruction_len);
7387         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7388                 vmcs12->guest_interruptibility_info);
7389         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7390         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7391         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7392         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7393                 vmcs12->guest_pending_dbg_exceptions);
7394         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7395         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7396
7397         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7398
7399         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7400                 (vmcs_config.pin_based_exec_ctrl |
7401                  vmcs12->pin_based_vm_exec_control));
7402
7403         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7404                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7405                              vmcs12->vmx_preemption_timer_value);
7406
7407         /*
7408          * Whether page-faults are trapped is determined by a combination of
7409          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7410          * If enable_ept, L0 doesn't care about page faults and we should
7411          * set all of these to L1's desires. However, if !enable_ept, L0 does
7412          * care about (at least some) page faults, and because it is not easy
7413          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7414          * to exit on each and every L2 page fault. This is done by setting
7415          * MASK=MATCH=0 and (see below) EB.PF=1.
7416          * Note that below we don't need special code to set EB.PF beyond the
7417          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7418          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7419          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7420          *
7421          * A problem with this approach (when !enable_ept) is that L1 may be
7422          * injected with more page faults than it asked for. This could have
7423          * caused problems, but in practice existing hypervisors don't care.
7424          * To fix this, we will need to emulate the PFEC checking (on the L1
7425          * page tables), using walk_addr(), when injecting PFs to L1.
7426          */
7427         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7428                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7429         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7430                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7431
7432         if (cpu_has_secondary_exec_ctrls()) {
7433                 u32 exec_control = vmx_secondary_exec_control(vmx);
7434                 if (!vmx->rdtscp_enabled)
7435                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7436                 /* Take the following fields only from vmcs12 */
7437                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7438                 if (nested_cpu_has(vmcs12,
7439                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7440                         exec_control |= vmcs12->secondary_vm_exec_control;
7441
7442                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7443                         /*
7444                          * Translate L1 physical address to host physical
7445                          * address for vmcs02. Keep the page pinned, so this
7446                          * physical address remains valid. We keep a reference
7447                          * to it so we can release it later.
7448                          */
7449                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7450                                 nested_release_page(vmx->nested.apic_access_page);
7451                         vmx->nested.apic_access_page =
7452                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7453                         /*
7454                          * If translation failed, no matter: This feature asks
7455                          * to exit when accessing the given address, and if it
7456                          * can never be accessed, this feature won't do
7457                          * anything anyway.
7458                          */
7459                         if (!vmx->nested.apic_access_page)
7460                                 exec_control &=
7461                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7462                         else
7463                                 vmcs_write64(APIC_ACCESS_ADDR,
7464                                   page_to_phys(vmx->nested.apic_access_page));
7465                 }
7466
7467                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7468         }
7469
7470
7471         /*
7472          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7473          * Some constant fields are set here by vmx_set_constant_host_state().
7474          * Other fields are different per CPU, and will be set later when
7475          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7476          */
7477         vmx_set_constant_host_state(vmx);
7478
7479         /*
7480          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7481          * entry, but only if the current (host) sp changed from the value
7482          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7483          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7484          * here we just force the write to happen on entry.
7485          */
7486         vmx->host_rsp = 0;
7487
7488         exec_control = vmx_exec_control(vmx); /* L0's desires */
7489         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7490         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7491         exec_control &= ~CPU_BASED_TPR_SHADOW;
7492         exec_control |= vmcs12->cpu_based_vm_exec_control;
7493         /*
7494          * Merging of IO and MSR bitmaps not currently supported.
7495          * Rather, exit every time.
7496          */
7497         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7498         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7499         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7500
7501         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7502
7503         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7504          * bitwise-or of what L1 wants to trap for L2, and what we want to
7505          * trap. Note that CR0.TS also needs updating - we do this later.
7506          */
7507         update_exception_bitmap(vcpu);
7508         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7509         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7510
7511         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7512         vmcs_write32(VM_EXIT_CONTROLS,
7513                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7514         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7515                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7516
7517         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7518                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7519         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7520                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7521
7522
7523         set_cr4_guest_host_mask(vmx);
7524
7525         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7526                 vmcs_write64(TSC_OFFSET,
7527                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7528         else
7529                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7530
7531         if (enable_vpid) {
7532                 /*
7533                  * Trivially support vpid by letting L2s share their parent
7534                  * L1's vpid. TODO: move to a more elaborate solution, giving
7535                  * each L2 its own vpid and exposing the vpid feature to L1.
7536                  */
7537                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7538                 vmx_flush_tlb(vcpu);
7539         }
7540
7541         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7542                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7543         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7544                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7545         else
7546                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7547         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7548         vmx_set_efer(vcpu, vcpu->arch.efer);
7549
7550         /*
7551          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7552          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7553          * The CR0_READ_SHADOW is what L2 should have expected to read given
7554          * the specifications by L1; It's not enough to take
7555          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7556          * have more bits than L1 expected.
7557          */
7558         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7559         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7560
7561         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7562         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7563
7564         /* shadow page tables on either EPT or shadow page tables */
7565         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7566         kvm_mmu_reset_context(vcpu);
7567
7568         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7569         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7570 }
7571
7572 /*
7573  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7574  * for running an L2 nested guest.
7575  */
7576 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7577 {
7578         struct vmcs12 *vmcs12;
7579         struct vcpu_vmx *vmx = to_vmx(vcpu);
7580         int cpu;
7581         struct loaded_vmcs *vmcs02;
7582         bool ia32e;
7583
7584         if (!nested_vmx_check_permission(vcpu) ||
7585             !nested_vmx_check_vmcs12(vcpu))
7586                 return 1;
7587
7588         skip_emulated_instruction(vcpu);
7589         vmcs12 = get_vmcs12(vcpu);
7590
7591         if (enable_shadow_vmcs)
7592                 copy_shadow_to_vmcs12(vmx);
7593
7594         /*
7595          * The nested entry process starts with enforcing various prerequisites
7596          * on vmcs12 as required by the Intel SDM, and act appropriately when
7597          * they fail: As the SDM explains, some conditions should cause the
7598          * instruction to fail, while others will cause the instruction to seem
7599          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7600          * To speed up the normal (success) code path, we should avoid checking
7601          * for misconfigurations which will anyway be caught by the processor
7602          * when using the merged vmcs02.
7603          */
7604         if (vmcs12->launch_state == launch) {
7605                 nested_vmx_failValid(vcpu,
7606                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7607                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7608                 return 1;
7609         }
7610
7611         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7612                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7613                 return 1;
7614         }
7615
7616         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7617                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7618                 /*TODO: Also verify bits beyond physical address width are 0*/
7619                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7620                 return 1;
7621         }
7622
7623         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7624                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7625                 /*TODO: Also verify bits beyond physical address width are 0*/
7626                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7627                 return 1;
7628         }
7629
7630         if (vmcs12->vm_entry_msr_load_count > 0 ||
7631             vmcs12->vm_exit_msr_load_count > 0 ||
7632             vmcs12->vm_exit_msr_store_count > 0) {
7633                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7634                                     __func__);
7635                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7636                 return 1;
7637         }
7638
7639         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7640               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7641             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7642               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7643             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7644               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7645             !vmx_control_verify(vmcs12->vm_exit_controls,
7646               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7647             !vmx_control_verify(vmcs12->vm_entry_controls,
7648               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7649         {
7650                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7651                 return 1;
7652         }
7653
7654         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7655             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7656                 nested_vmx_failValid(vcpu,
7657                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7658                 return 1;
7659         }
7660
7661         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7662             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7663                 nested_vmx_entry_failure(vcpu, vmcs12,
7664                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7665                 return 1;
7666         }
7667         if (vmcs12->vmcs_link_pointer != -1ull) {
7668                 nested_vmx_entry_failure(vcpu, vmcs12,
7669                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7670                 return 1;
7671         }
7672
7673         /*
7674          * If the load IA32_EFER VM-entry control is 1, the following checks
7675          * are performed on the field for the IA32_EFER MSR:
7676          * - Bits reserved in the IA32_EFER MSR must be 0.
7677          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7678          *   the IA-32e mode guest VM-exit control. It must also be identical
7679          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7680          *   CR0.PG) is 1.
7681          */
7682         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7683                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7684                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7685                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7686                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7687                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7688                         nested_vmx_entry_failure(vcpu, vmcs12,
7689                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7690                         return 1;
7691                 }
7692         }
7693
7694         /*
7695          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7696          * IA32_EFER MSR must be 0 in the field for that register. In addition,
7697          * the values of the LMA and LME bits in the field must each be that of
7698          * the host address-space size VM-exit control.
7699          */
7700         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7701                 ia32e = (vmcs12->vm_exit_controls &
7702                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7703                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7704                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7705                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7706                         nested_vmx_entry_failure(vcpu, vmcs12,
7707                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7708                         return 1;
7709                 }
7710         }
7711
7712         /*
7713          * We're finally done with prerequisite checking, and can start with
7714          * the nested entry.
7715          */
7716
7717         vmcs02 = nested_get_current_vmcs02(vmx);
7718         if (!vmcs02)
7719                 return -ENOMEM;
7720
7721         enter_guest_mode(vcpu);
7722
7723         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7724
7725         cpu = get_cpu();
7726         vmx->loaded_vmcs = vmcs02;
7727         vmx_vcpu_put(vcpu);
7728         vmx_vcpu_load(vcpu, cpu);
7729         vcpu->cpu = cpu;
7730         put_cpu();
7731
7732         vmx_segment_cache_clear(vmx);
7733
7734         vmcs12->launch_state = 1;
7735
7736         prepare_vmcs02(vcpu, vmcs12);
7737
7738         /*
7739          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7740          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7741          * returned as far as L1 is concerned. It will only return (and set
7742          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7743          */
7744         return 1;
7745 }
7746
7747 /*
7748  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7749  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7750  * This function returns the new value we should put in vmcs12.guest_cr0.
7751  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7752  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7753  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7754  *     didn't trap the bit, because if L1 did, so would L0).
7755  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7756  *     been modified by L2, and L1 knows it. So just leave the old value of
7757  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7758  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7759  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7760  *     changed these bits, and therefore they need to be updated, but L0
7761  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7762  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7763  */
7764 static inline unsigned long
7765 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7766 {
7767         return
7768         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7769         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7770         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7771                         vcpu->arch.cr0_guest_owned_bits));
7772 }
7773
7774 static inline unsigned long
7775 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7776 {
7777         return
7778         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7779         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7780         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7781                         vcpu->arch.cr4_guest_owned_bits));
7782 }
7783
7784 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7785                                        struct vmcs12 *vmcs12)
7786 {
7787         u32 idt_vectoring;
7788         unsigned int nr;
7789
7790         if (vcpu->arch.exception.pending) {
7791                 nr = vcpu->arch.exception.nr;
7792                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7793
7794                 if (kvm_exception_is_soft(nr)) {
7795                         vmcs12->vm_exit_instruction_len =
7796                                 vcpu->arch.event_exit_inst_len;
7797                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7798                 } else
7799                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7800
7801                 if (vcpu->arch.exception.has_error_code) {
7802                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7803                         vmcs12->idt_vectoring_error_code =
7804                                 vcpu->arch.exception.error_code;
7805                 }
7806
7807                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7808         } else if (vcpu->arch.nmi_pending) {
7809                 vmcs12->idt_vectoring_info_field =
7810                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7811         } else if (vcpu->arch.interrupt.pending) {
7812                 nr = vcpu->arch.interrupt.nr;
7813                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7814
7815                 if (vcpu->arch.interrupt.soft) {
7816                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
7817                         vmcs12->vm_entry_instruction_len =
7818                                 vcpu->arch.event_exit_inst_len;
7819                 } else
7820                         idt_vectoring |= INTR_TYPE_EXT_INTR;
7821
7822                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7823         }
7824 }
7825
7826 /*
7827  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7828  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7829  * and this function updates it to reflect the changes to the guest state while
7830  * L2 was running (and perhaps made some exits which were handled directly by L0
7831  * without going back to L1), and to reflect the exit reason.
7832  * Note that we do not have to copy here all VMCS fields, just those that
7833  * could have changed by the L2 guest or the exit - i.e., the guest-state and
7834  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7835  * which already writes to vmcs12 directly.
7836  */
7837 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7838 {
7839         /* update guest state fields: */
7840         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7841         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7842
7843         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7844         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7845         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7846         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7847
7848         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7849         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7850         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7851         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7852         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7853         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7854         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7855         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7856         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7857         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7858         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7859         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7860         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7861         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7862         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7863         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7864         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7865         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7866         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7867         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7868         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7869         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7870         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7871         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7872         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7873         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7874         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7875         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7876         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7877         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7878         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7879         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7880         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7881         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7882         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7883         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7884
7885         vmcs12->guest_interruptibility_info =
7886                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7887         vmcs12->guest_pending_dbg_exceptions =
7888                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7889
7890         vmcs12->vm_entry_controls =
7891                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7892                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7893
7894         /* TODO: These cannot have changed unless we have MSR bitmaps and
7895          * the relevant bit asks not to trap the change */
7896         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7897         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
7898                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7899         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7900         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7901         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7902
7903         /* update exit information fields: */
7904
7905         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
7906         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7907
7908         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7909         if ((vmcs12->vm_exit_intr_info &
7910              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7911             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7912                 vmcs12->vm_exit_intr_error_code =
7913                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7914         vmcs12->idt_vectoring_info_field = 0;
7915         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7916         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7917
7918         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7919                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7920                  * instead of reading the real value. */
7921                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7922
7923                 /*
7924                  * Transfer the event that L0 or L1 may wanted to inject into
7925                  * L2 to IDT_VECTORING_INFO_FIELD.
7926                  */
7927                 vmcs12_save_pending_event(vcpu, vmcs12);
7928         }
7929
7930         /*
7931          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7932          * preserved above and would only end up incorrectly in L1.
7933          */
7934         vcpu->arch.nmi_injected = false;
7935         kvm_clear_exception_queue(vcpu);
7936         kvm_clear_interrupt_queue(vcpu);
7937 }
7938
7939 /*
7940  * A part of what we need to when the nested L2 guest exits and we want to
7941  * run its L1 parent, is to reset L1's guest state to the host state specified
7942  * in vmcs12.
7943  * This function is to be called not only on normal nested exit, but also on
7944  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7945  * Failures During or After Loading Guest State").
7946  * This function should be called when the active VMCS is L1's (vmcs01).
7947  */
7948 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7949                                    struct vmcs12 *vmcs12)
7950 {
7951         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7952                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7953         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7954                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7955         else
7956                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7957         vmx_set_efer(vcpu, vcpu->arch.efer);
7958
7959         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7960         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7961         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
7962         /*
7963          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7964          * actually changed, because it depends on the current state of
7965          * fpu_active (which may have changed).
7966          * Note that vmx_set_cr0 refers to efer set above.
7967          */
7968         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7969         /*
7970          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7971          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7972          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7973          */
7974         update_exception_bitmap(vcpu);
7975         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7976         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7977
7978         /*
7979          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7980          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7981          */
7982         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7983         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7984
7985         /* shadow page tables on either EPT or shadow page tables */
7986         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7987         kvm_mmu_reset_context(vcpu);
7988
7989         if (enable_vpid) {
7990                 /*
7991                  * Trivially support vpid by letting L2s share their parent
7992                  * L1's vpid. TODO: move to a more elaborate solution, giving
7993                  * each L2 its own vpid and exposing the vpid feature to L1.
7994                  */
7995                 vmx_flush_tlb(vcpu);
7996         }
7997
7998
7999         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8000         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8001         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8002         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8003         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8004         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
8005         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
8006         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
8007         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
8008         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
8009         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
8010         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
8011         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
8012         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
8013         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
8014
8015         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8016                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8017         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8018                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8019                         vmcs12->host_ia32_perf_global_ctrl);
8020
8021         kvm_set_dr(vcpu, 7, 0x400);
8022         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8023 }
8024
8025 /*
8026  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8027  * and modify vmcs12 to make it see what it would expect to see there if
8028  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8029  */
8030 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8031 {
8032         struct vcpu_vmx *vmx = to_vmx(vcpu);
8033         int cpu;
8034         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8035
8036         /* trying to cancel vmlaunch/vmresume is a bug */
8037         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8038
8039         leave_guest_mode(vcpu);
8040         prepare_vmcs12(vcpu, vmcs12);
8041
8042         cpu = get_cpu();
8043         vmx->loaded_vmcs = &vmx->vmcs01;
8044         vmx_vcpu_put(vcpu);
8045         vmx_vcpu_load(vcpu, cpu);
8046         vcpu->cpu = cpu;
8047         put_cpu();
8048
8049         vmx_segment_cache_clear(vmx);
8050
8051         /* if no vmcs02 cache requested, remove the one we used */
8052         if (VMCS02_POOL_SIZE == 0)
8053                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8054
8055         load_vmcs12_host_state(vcpu, vmcs12);
8056
8057         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8058         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8059
8060         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8061         vmx->host_rsp = 0;
8062
8063         /* Unpin physical memory we referred to in vmcs02 */
8064         if (vmx->nested.apic_access_page) {
8065                 nested_release_page(vmx->nested.apic_access_page);
8066                 vmx->nested.apic_access_page = 0;
8067         }
8068
8069         /*
8070          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8071          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8072          * success or failure flag accordingly.
8073          */
8074         if (unlikely(vmx->fail)) {
8075                 vmx->fail = 0;
8076                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8077         } else
8078                 nested_vmx_succeed(vcpu);
8079         if (enable_shadow_vmcs)
8080                 vmx->nested.sync_shadow_vmcs = true;
8081 }
8082
8083 /*
8084  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8085  * 23.7 "VM-entry failures during or after loading guest state" (this also
8086  * lists the acceptable exit-reason and exit-qualification parameters).
8087  * It should only be called before L2 actually succeeded to run, and when
8088  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8089  */
8090 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8091                         struct vmcs12 *vmcs12,
8092                         u32 reason, unsigned long qualification)
8093 {
8094         load_vmcs12_host_state(vcpu, vmcs12);
8095         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8096         vmcs12->exit_qualification = qualification;
8097         nested_vmx_succeed(vcpu);
8098         if (enable_shadow_vmcs)
8099                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8100 }
8101
8102 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8103                                struct x86_instruction_info *info,
8104                                enum x86_intercept_stage stage)
8105 {
8106         return X86EMUL_CONTINUE;
8107 }
8108
8109 static struct kvm_x86_ops vmx_x86_ops = {
8110         .cpu_has_kvm_support = cpu_has_kvm_support,
8111         .disabled_by_bios = vmx_disabled_by_bios,
8112         .hardware_setup = hardware_setup,
8113         .hardware_unsetup = hardware_unsetup,
8114         .check_processor_compatibility = vmx_check_processor_compat,
8115         .hardware_enable = hardware_enable,
8116         .hardware_disable = hardware_disable,
8117         .cpu_has_accelerated_tpr = report_flexpriority,
8118
8119         .vcpu_create = vmx_create_vcpu,
8120         .vcpu_free = vmx_free_vcpu,
8121         .vcpu_reset = vmx_vcpu_reset,
8122
8123         .prepare_guest_switch = vmx_save_host_state,
8124         .vcpu_load = vmx_vcpu_load,
8125         .vcpu_put = vmx_vcpu_put,
8126
8127         .update_db_bp_intercept = update_exception_bitmap,
8128         .get_msr = vmx_get_msr,
8129         .set_msr = vmx_set_msr,
8130         .get_segment_base = vmx_get_segment_base,
8131         .get_segment = vmx_get_segment,
8132         .set_segment = vmx_set_segment,
8133         .get_cpl = vmx_get_cpl,
8134         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8135         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8136         .decache_cr3 = vmx_decache_cr3,
8137         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8138         .set_cr0 = vmx_set_cr0,
8139         .set_cr3 = vmx_set_cr3,
8140         .set_cr4 = vmx_set_cr4,
8141         .set_efer = vmx_set_efer,
8142         .get_idt = vmx_get_idt,
8143         .set_idt = vmx_set_idt,
8144         .get_gdt = vmx_get_gdt,
8145         .set_gdt = vmx_set_gdt,
8146         .set_dr7 = vmx_set_dr7,
8147         .cache_reg = vmx_cache_reg,
8148         .get_rflags = vmx_get_rflags,
8149         .set_rflags = vmx_set_rflags,
8150         .fpu_activate = vmx_fpu_activate,
8151         .fpu_deactivate = vmx_fpu_deactivate,
8152
8153         .tlb_flush = vmx_flush_tlb,
8154
8155         .run = vmx_vcpu_run,
8156         .handle_exit = vmx_handle_exit,
8157         .skip_emulated_instruction = skip_emulated_instruction,
8158         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8159         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8160         .patch_hypercall = vmx_patch_hypercall,
8161         .set_irq = vmx_inject_irq,
8162         .set_nmi = vmx_inject_nmi,
8163         .queue_exception = vmx_queue_exception,
8164         .cancel_injection = vmx_cancel_injection,
8165         .interrupt_allowed = vmx_interrupt_allowed,
8166         .nmi_allowed = vmx_nmi_allowed,
8167         .get_nmi_mask = vmx_get_nmi_mask,
8168         .set_nmi_mask = vmx_set_nmi_mask,
8169         .enable_nmi_window = enable_nmi_window,
8170         .enable_irq_window = enable_irq_window,
8171         .update_cr8_intercept = update_cr8_intercept,
8172         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8173         .vm_has_apicv = vmx_vm_has_apicv,
8174         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8175         .hwapic_irr_update = vmx_hwapic_irr_update,
8176         .hwapic_isr_update = vmx_hwapic_isr_update,
8177         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8178         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8179
8180         .set_tss_addr = vmx_set_tss_addr,
8181         .get_tdp_level = get_ept_level,
8182         .get_mt_mask = vmx_get_mt_mask,
8183
8184         .get_exit_info = vmx_get_exit_info,
8185
8186         .get_lpage_level = vmx_get_lpage_level,
8187
8188         .cpuid_update = vmx_cpuid_update,
8189
8190         .rdtscp_supported = vmx_rdtscp_supported,
8191         .invpcid_supported = vmx_invpcid_supported,
8192
8193         .set_supported_cpuid = vmx_set_supported_cpuid,
8194
8195         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8196
8197         .set_tsc_khz = vmx_set_tsc_khz,
8198         .read_tsc_offset = vmx_read_tsc_offset,
8199         .write_tsc_offset = vmx_write_tsc_offset,
8200         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8201         .compute_tsc_offset = vmx_compute_tsc_offset,
8202         .read_l1_tsc = vmx_read_l1_tsc,
8203
8204         .set_tdp_cr3 = vmx_set_cr3,
8205
8206         .check_intercept = vmx_check_intercept,
8207         .handle_external_intr = vmx_handle_external_intr,
8208 };
8209
8210 static int __init vmx_init(void)
8211 {
8212         int r, i, msr;
8213
8214         rdmsrl_safe(MSR_EFER, &host_efer);
8215
8216         for (i = 0; i < NR_VMX_MSR; ++i)
8217                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8218
8219         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8220         if (!vmx_io_bitmap_a)
8221                 return -ENOMEM;
8222
8223         r = -ENOMEM;
8224
8225         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8226         if (!vmx_io_bitmap_b)
8227                 goto out;
8228
8229         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8230         if (!vmx_msr_bitmap_legacy)
8231                 goto out1;
8232
8233         vmx_msr_bitmap_legacy_x2apic =
8234                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8235         if (!vmx_msr_bitmap_legacy_x2apic)
8236                 goto out2;
8237
8238         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8239         if (!vmx_msr_bitmap_longmode)
8240                 goto out3;
8241
8242         vmx_msr_bitmap_longmode_x2apic =
8243                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8244         if (!vmx_msr_bitmap_longmode_x2apic)
8245                 goto out4;
8246         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8247         if (!vmx_vmread_bitmap)
8248                 goto out5;
8249
8250         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8251         if (!vmx_vmwrite_bitmap)
8252                 goto out6;
8253
8254         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8255         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8256         /* shadowed read/write fields */
8257         for (i = 0; i < max_shadow_read_write_fields; i++) {
8258                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8259                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8260         }
8261         /* shadowed read only fields */
8262         for (i = 0; i < max_shadow_read_only_fields; i++)
8263                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8264
8265         /*
8266          * Allow direct access to the PC debug port (it is often used for I/O
8267          * delays, but the vmexits simply slow things down).
8268          */
8269         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8270         clear_bit(0x80, vmx_io_bitmap_a);
8271
8272         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8273
8274         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8275         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8276
8277         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8278
8279         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8280                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8281         if (r)
8282                 goto out7;
8283
8284 #ifdef CONFIG_KEXEC
8285         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8286                            crash_vmclear_local_loaded_vmcss);
8287 #endif
8288
8289         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8290         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8291         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8292         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8293         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8294         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8295         memcpy(vmx_msr_bitmap_legacy_x2apic,
8296                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8297         memcpy(vmx_msr_bitmap_longmode_x2apic,
8298                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8299
8300         if (enable_apicv) {
8301                 for (msr = 0x800; msr <= 0x8ff; msr++)
8302                         vmx_disable_intercept_msr_read_x2apic(msr);
8303
8304                 /* According SDM, in x2apic mode, the whole id reg is used.
8305                  * But in KVM, it only use the highest eight bits. Need to
8306                  * intercept it */
8307                 vmx_enable_intercept_msr_read_x2apic(0x802);
8308                 /* TMCCT */
8309                 vmx_enable_intercept_msr_read_x2apic(0x839);
8310                 /* TPR */
8311                 vmx_disable_intercept_msr_write_x2apic(0x808);
8312                 /* EOI */
8313                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8314                 /* SELF-IPI */
8315                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8316         }
8317
8318         if (enable_ept) {
8319                 kvm_mmu_set_mask_ptes(0ull,
8320                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8321                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8322                         0ull, VMX_EPT_EXECUTABLE_MASK);
8323                 ept_set_mmio_spte_mask();
8324                 kvm_enable_tdp();
8325         } else
8326                 kvm_disable_tdp();
8327
8328         return 0;
8329
8330 out7:
8331         free_page((unsigned long)vmx_vmwrite_bitmap);
8332 out6:
8333         free_page((unsigned long)vmx_vmread_bitmap);
8334 out5:
8335         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8336 out4:
8337         free_page((unsigned long)vmx_msr_bitmap_longmode);
8338 out3:
8339         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8340 out2:
8341         free_page((unsigned long)vmx_msr_bitmap_legacy);
8342 out1:
8343         free_page((unsigned long)vmx_io_bitmap_b);
8344 out:
8345         free_page((unsigned long)vmx_io_bitmap_a);
8346         return r;
8347 }
8348
8349 static void __exit vmx_exit(void)
8350 {
8351         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8352         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8353         free_page((unsigned long)vmx_msr_bitmap_legacy);
8354         free_page((unsigned long)vmx_msr_bitmap_longmode);
8355         free_page((unsigned long)vmx_io_bitmap_b);
8356         free_page((unsigned long)vmx_io_bitmap_a);
8357         free_page((unsigned long)vmx_vmwrite_bitmap);
8358         free_page((unsigned long)vmx_vmread_bitmap);
8359
8360 #ifdef CONFIG_KEXEC
8361         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8362         synchronize_rcu();
8363 #endif
8364
8365         kvm_exit();
8366 }
8367
8368 module_init(vmx_init)
8369 module_exit(vmx_exit)