Pileus Git - ~andy/linux/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376         u64 msr_ia32_feature_control;
 377 };
 378
 379 #define POSTED_INTR_ON  0
 380 /* Posted-Interrupt Descriptor */
 381 struct pi_desc {
 382         u32 pir[8];     /* Posted interrupt requested */
 383         u32 control;    /* bit 0 of control is outstanding notification bit */
 384         u32 rsvd[7];
 385 } __aligned(64);
 386
 387 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 388 {
 389         return test_and_set_bit(POSTED_INTR_ON,
 390                         (unsigned long *)&pi_desc->control);
 391 }
 392
 393 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 394 {
 395         return test_and_clear_bit(POSTED_INTR_ON,
 396                         (unsigned long *)&pi_desc->control);
 397 }
 398
 399 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 400 {
 401         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 402 }
 403
 404 struct vcpu_vmx {
 405         struct kvm_vcpu       vcpu;
 406         unsigned long         host_rsp;
 407         u8                    fail;
 408         u8                    cpl;
 409         bool                  nmi_known_unmasked;
 410         u32                   exit_intr_info;
 411         u32                   idt_vectoring_info;
 412         ulong                 rflags;
 413         struct shared_msr_entry *guest_msrs;
 414         int                   nmsrs;
 415         int                   save_nmsrs;
 416         unsigned long         host_idt_base;
 417 #ifdef CONFIG_X86_64
 418         u64                   msr_host_kernel_gs_base;
 419         u64                   msr_guest_kernel_gs_base;
 420 #endif
 421         /*
 422          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 423          * non-nested (L1) guest, it always points to vmcs01. For a nested
 424          * guest (L2), it points to a different VMCS.
 425          */
 426         struct loaded_vmcs    vmcs01;
 427         struct loaded_vmcs   *loaded_vmcs;
 428         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 429         struct msr_autoload {
 430                 unsigned nr;
 431                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 432                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 433         } msr_autoload;
 434         struct {
 435                 int           loaded;
 436                 u16           fs_sel, gs_sel, ldt_sel;
 437 #ifdef CONFIG_X86_64
 438                 u16           ds_sel, es_sel;
 439 #endif
 440                 int           gs_ldt_reload_needed;
 441                 int           fs_reload_needed;
 442         } host_state;
 443         struct {
 444                 int vm86_active;
 445                 ulong save_rflags;
 446                 struct kvm_segment segs[8];
 447         } rmode;
 448         struct {
 449                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 450                 struct kvm_save_segment {
 451                         u16 selector;
 452                         unsigned long base;
 453                         u32 limit;
 454                         u32 ar;
 455                 } seg[8];
 456         } segment_cache;
 457         int vpid;
 458         bool emulation_required;
 459
 460         /* Support for vnmi-less CPUs */
 461         int soft_vnmi_blocked;
 462         ktime_t entry_time;
 463         s64 vnmi_blocked_time;
 464         u32 exit_reason;
 465
 466         bool rdtscp_enabled;
 467
 468         /* Posted interrupt descriptor */
 469         struct pi_desc pi_desc;
 470
 471         /* Support for a guest hypervisor (nested VMX) */
 472         struct nested_vmx nested;
 473 };
 474
 475 enum segment_cache_field {
 476         SEG_FIELD_SEL = 0,
 477         SEG_FIELD_BASE = 1,
 478         SEG_FIELD_LIMIT = 2,
 479         SEG_FIELD_AR = 3,
 480
 481         SEG_FIELD_NR = 4
 482 };
 483
 484 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 485 {
 486         return container_of(vcpu, struct vcpu_vmx, vcpu);
 487 }
 488
 489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 490 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 491 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 492                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 493
 494
 495 static const unsigned long shadow_read_only_fields[] = {
 496         /*
 497          * We do NOT shadow fields that are modified when L0
 498          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 499          * VMXON...) executed by L1.
 500          * For example, VM_INSTRUCTION_ERROR is read
 501          * by L1 if a vmx instruction fails (part of the error path).
 502          * Note the code assumes this logic. If for some reason
 503          * we start shadowing these fields then we need to
 504          * force a shadow sync when L0 emulates vmx instructions
 505          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 506          * by nested_vmx_failValid)
 507          */
 508         VM_EXIT_REASON,
 509         VM_EXIT_INTR_INFO,
 510         VM_EXIT_INSTRUCTION_LEN,
 511         IDT_VECTORING_INFO_FIELD,
 512         IDT_VECTORING_ERROR_CODE,
 513         VM_EXIT_INTR_ERROR_CODE,
 514         EXIT_QUALIFICATION,
 515         GUEST_LINEAR_ADDRESS,
 516         GUEST_PHYSICAL_ADDRESS
 517 };
 518 static const int max_shadow_read_only_fields =
 519         ARRAY_SIZE(shadow_read_only_fields);
 520
 521 static const unsigned long shadow_read_write_fields[] = {
 522         GUEST_RIP,
 523         GUEST_RSP,
 524         GUEST_CR0,
 525         GUEST_CR3,
 526         GUEST_CR4,
 527         GUEST_INTERRUPTIBILITY_INFO,
 528         GUEST_RFLAGS,
 529         GUEST_CS_SELECTOR,
 530         GUEST_CS_AR_BYTES,
 531         GUEST_CS_LIMIT,
 532         GUEST_CS_BASE,
 533         GUEST_ES_BASE,
 534         CR0_GUEST_HOST_MASK,
 535         CR0_READ_SHADOW,
 536         CR4_READ_SHADOW,
 537         TSC_OFFSET,
 538         EXCEPTION_BITMAP,
 539         CPU_BASED_VM_EXEC_CONTROL,
 540         VM_ENTRY_EXCEPTION_ERROR_CODE,
 541         VM_ENTRY_INTR_INFO_FIELD,
 542         VM_ENTRY_INSTRUCTION_LEN,
 543         VM_ENTRY_EXCEPTION_ERROR_CODE,
 544         HOST_FS_BASE,
 545         HOST_GS_BASE,
 546         HOST_FS_SELECTOR,
 547         HOST_GS_SELECTOR
 548 };
 549 static const int max_shadow_read_write_fields =
 550         ARRAY_SIZE(shadow_read_write_fields);
 551
 552 static const unsigned short vmcs_field_to_offset_table[] = {
 553         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 554         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 555         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 556         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 557         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 558         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 559         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 560         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 561         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 562         FIELD(HOST_ES_SELECTOR, host_es_selector),
 563         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 564         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 565         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 566         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 567         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 568         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 569         FIELD64(IO_BITMAP_A, io_bitmap_a),
 570         FIELD64(IO_BITMAP_B, io_bitmap_b),
 571         FIELD64(MSR_BITMAP, msr_bitmap),
 572         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 573         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 574         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 575         FIELD64(TSC_OFFSET, tsc_offset),
 576         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 577         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 578         FIELD64(EPT_POINTER, ept_pointer),
 579         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 580         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 581         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 582         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 583         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 584         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 585         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 586         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 587         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 588         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 589         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 590         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 591         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 592         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 593         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 594         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 595         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 596         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 597         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 598         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 599         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 600         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 601         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 602         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 603         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 604         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 605         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 606         FIELD(TPR_THRESHOLD, tpr_threshold),
 607         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 608         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 609         FIELD(VM_EXIT_REASON, vm_exit_reason),
 610         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 611         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 612         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 613         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 614         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 615         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 616         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 617         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 618         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 619         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 620         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 621         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 622         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 623         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 624         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 625         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 626         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 627         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 628         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 629         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 630         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 631         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 632         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 633         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 634         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 635         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 636         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 637         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 638         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 639         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 640         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 641         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 642         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 643         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 644         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 645         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 646         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 647         FIELD(EXIT_QUALIFICATION, exit_qualification),
 648         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 649         FIELD(GUEST_CR0, guest_cr0),
 650         FIELD(GUEST_CR3, guest_cr3),
 651         FIELD(GUEST_CR4, guest_cr4),
 652         FIELD(GUEST_ES_BASE, guest_es_base),
 653         FIELD(GUEST_CS_BASE, guest_cs_base),
 654         FIELD(GUEST_SS_BASE, guest_ss_base),
 655         FIELD(GUEST_DS_BASE, guest_ds_base),
 656         FIELD(GUEST_FS_BASE, guest_fs_base),
 657         FIELD(GUEST_GS_BASE, guest_gs_base),
 658         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 659         FIELD(GUEST_TR_BASE, guest_tr_base),
 660         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 661         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 662         FIELD(GUEST_DR7, guest_dr7),
 663         FIELD(GUEST_RSP, guest_rsp),
 664         FIELD(GUEST_RIP, guest_rip),
 665         FIELD(GUEST_RFLAGS, guest_rflags),
 666         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 667         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 668         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 669         FIELD(HOST_CR0, host_cr0),
 670         FIELD(HOST_CR3, host_cr3),
 671         FIELD(HOST_CR4, host_cr4),
 672         FIELD(HOST_FS_BASE, host_fs_base),
 673         FIELD(HOST_GS_BASE, host_gs_base),
 674         FIELD(HOST_TR_BASE, host_tr_base),
 675         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 676         FIELD(HOST_IDTR_BASE, host_idtr_base),
 677         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 678         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 679         FIELD(HOST_RSP, host_rsp),
 680         FIELD(HOST_RIP, host_rip),
 681 };
 682 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 683
 684 static inline short vmcs_field_to_offset(unsigned long field)
 685 {
 686         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 687                 return -1;
 688         return vmcs_field_to_offset_table[field];
 689 }
 690
 691 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 692 {
 693         return to_vmx(vcpu)->nested.current_vmcs12;
 694 }
 695
 696 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 697 {
 698         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 699         if (is_error_page(page))
 700                 return NULL;
 701
 702         return page;
 703 }
 704
 705 static void nested_release_page(struct page *page)
 706 {
 707         kvm_release_page_dirty(page);
 708 }
 709
 710 static void nested_release_page_clean(struct page *page)
 711 {
 712         kvm_release_page_clean(page);
 713 }
 714
 715 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 716 static u64 construct_eptp(unsigned long root_hpa);
 717 static void kvm_cpu_vmxon(u64 addr);
 718 static void kvm_cpu_vmxoff(void);
 719 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 720 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 721                             struct kvm_segment *var, int seg);
 722 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 723                             struct kvm_segment *var, int seg);
 724 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 725 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 726 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 727 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 728 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 729
 730 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 731 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 732 /*
 733  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 734  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 735  */
 736 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 737 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 738
 739 static unsigned long *vmx_io_bitmap_a;
 740 static unsigned long *vmx_io_bitmap_b;
 741 static unsigned long *vmx_msr_bitmap_legacy;
 742 static unsigned long *vmx_msr_bitmap_longmode;
 743 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 744 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 745 static unsigned long *vmx_vmread_bitmap;
 746 static unsigned long *vmx_vmwrite_bitmap;
 747
 748 static bool cpu_has_load_ia32_efer;
 749 static bool cpu_has_load_perf_global_ctrl;
 750
 751 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 752 static DEFINE_SPINLOCK(vmx_vpid_lock);
 753
 754 static struct vmcs_config {
 755         int size;
 756         int order;
 757         u32 revision_id;
 758         u32 pin_based_exec_ctrl;
 759         u32 cpu_based_exec_ctrl;
 760         u32 cpu_based_2nd_exec_ctrl;
 761         u32 vmexit_ctrl;
 762         u32 vmentry_ctrl;
 763 } vmcs_config;
 764
 765 static struct vmx_capability {
 766         u32 ept;
 767         u32 vpid;
 768 } vmx_capability;
 769
 770 #define VMX_SEGMENT_FIELD(seg)                                  \
 771         [VCPU_SREG_##seg] = {                                   \
 772                 .selector = GUEST_##seg##_SELECTOR,             \
 773                 .base = GUEST_##seg##_BASE,                     \
 774                 .limit = GUEST_##seg##_LIMIT,                   \
 775                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 776         }
 777
 778 static const struct kvm_vmx_segment_field {
 779         unsigned selector;
 780         unsigned base;
 781         unsigned limit;
 782         unsigned ar_bytes;
 783 } kvm_vmx_segment_fields[] = {
 784         VMX_SEGMENT_FIELD(CS),
 785         VMX_SEGMENT_FIELD(DS),
 786         VMX_SEGMENT_FIELD(ES),
 787         VMX_SEGMENT_FIELD(FS),
 788         VMX_SEGMENT_FIELD(GS),
 789         VMX_SEGMENT_FIELD(SS),
 790         VMX_SEGMENT_FIELD(TR),
 791         VMX_SEGMENT_FIELD(LDTR),
 792 };
 793
 794 static u64 host_efer;
 795
 796 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 797
 798 /*
 799  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 800  * away by decrementing the array size.
 801  */
 802 static const u32 vmx_msr_index[] = {
 803 #ifdef CONFIG_X86_64
 804         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 805 #endif
 806         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 807 };
 808 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 809
 810 static inline bool is_page_fault(u32 intr_info)
 811 {
 812         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 813                              INTR_INFO_VALID_MASK)) ==
 814                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 815 }
 816
 817 static inline bool is_no_device(u32 intr_info)
 818 {
 819         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 820                              INTR_INFO_VALID_MASK)) ==
 821                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 822 }
 823
 824 static inline bool is_invalid_opcode(u32 intr_info)
 825 {
 826         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 827                              INTR_INFO_VALID_MASK)) ==
 828                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 829 }
 830
 831 static inline bool is_external_interrupt(u32 intr_info)
 832 {
 833         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 834                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 835 }
 836
 837 static inline bool is_machine_check(u32 intr_info)
 838 {
 839         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 840                              INTR_INFO_VALID_MASK)) ==
 841                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 842 }
 843
 844 static inline bool cpu_has_vmx_msr_bitmap(void)
 845 {
 846         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 847 }
 848
 849 static inline bool cpu_has_vmx_tpr_shadow(void)
 850 {
 851         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 852 }
 853
 854 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 855 {
 856         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 857 }
 858
 859 static inline bool cpu_has_secondary_exec_ctrls(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl &
 862                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 863 }
 864
 865 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 866 {
 867         return vmcs_config.cpu_based_2nd_exec_ctrl &
 868                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 869 }
 870
 871 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 872 {
 873         return vmcs_config.cpu_based_2nd_exec_ctrl &
 874                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 875 }
 876
 877 static inline bool cpu_has_vmx_apic_register_virt(void)
 878 {
 879         return vmcs_config.cpu_based_2nd_exec_ctrl &
 880                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 881 }
 882
 883 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 884 {
 885         return vmcs_config.cpu_based_2nd_exec_ctrl &
 886                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 887 }
 888
 889 static inline bool cpu_has_vmx_posted_intr(void)
 890 {
 891         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 892 }
 893
 894 static inline bool cpu_has_vmx_apicv(void)
 895 {
 896         return cpu_has_vmx_apic_register_virt() &&
 897                 cpu_has_vmx_virtual_intr_delivery() &&
 898                 cpu_has_vmx_posted_intr();
 899 }
 900
 901 static inline bool cpu_has_vmx_flexpriority(void)
 902 {
 903         return cpu_has_vmx_tpr_shadow() &&
 904                 cpu_has_vmx_virtualize_apic_accesses();
 905 }
 906
 907 static inline bool cpu_has_vmx_ept_execute_only(void)
 908 {
 909         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 910 }
 911
 912 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 913 {
 914         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 915 }
 916
 917 static inline bool cpu_has_vmx_eptp_writeback(void)
 918 {
 919         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_2m_page(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_ept_1g_page(void)
 928 {
 929         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_ept_4levels(void)
 933 {
 934         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_ad_bits(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_AD_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_invept_context(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_invept_global(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_invvpid_single(void)
 953 {
 954         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invvpid_global(void)
 958 {
 959         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_ept(void)
 963 {
 964         return vmcs_config.cpu_based_2nd_exec_ctrl &
 965                 SECONDARY_EXEC_ENABLE_EPT;
 966 }
 967
 968 static inline bool cpu_has_vmx_unrestricted_guest(void)
 969 {
 970         return vmcs_config.cpu_based_2nd_exec_ctrl &
 971                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 972 }
 973
 974 static inline bool cpu_has_vmx_ple(void)
 975 {
 976         return vmcs_config.cpu_based_2nd_exec_ctrl &
 977                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 978 }
 979
 980 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 981 {
 982         return flexpriority_enabled && irqchip_in_kernel(kvm);
 983 }
 984
 985 static inline bool cpu_has_vmx_vpid(void)
 986 {
 987         return vmcs_config.cpu_based_2nd_exec_ctrl &
 988                 SECONDARY_EXEC_ENABLE_VPID;
 989 }
 990
 991 static inline bool cpu_has_vmx_rdtscp(void)
 992 {
 993         return vmcs_config.cpu_based_2nd_exec_ctrl &
 994                 SECONDARY_EXEC_RDTSCP;
 995 }
 996
 997 static inline bool cpu_has_vmx_invpcid(void)
 998 {
 999         return vmcs_config.cpu_based_2nd_exec_ctrl &
1000                 SECONDARY_EXEC_ENABLE_INVPCID;
1001 }
1002
1003 static inline bool cpu_has_virtual_nmis(void)
1004 {
1005         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006 }
1007
1008 static inline bool cpu_has_vmx_wbinvd_exit(void)
1009 {
1010         return vmcs_config.cpu_based_2nd_exec_ctrl &
1011                 SECONDARY_EXEC_WBINVD_EXITING;
1012 }
1013
1014 static inline bool cpu_has_vmx_shadow_vmcs(void)
1015 {
1016         u64 vmx_msr;
1017         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018         /* check if the cpu supports writing r/o exit information fields */
1019         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020                 return false;
1021
1022         return vmcs_config.cpu_based_2nd_exec_ctrl &
1023                 SECONDARY_EXEC_SHADOW_VMCS;
1024 }
1025
1026 static inline bool report_flexpriority(void)
1027 {
1028         return flexpriority_enabled;
1029 }
1030
1031 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032 {
1033         return vmcs12->cpu_based_vm_exec_control & bit;
1034 }
1035
1036 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037 {
1038         return (vmcs12->cpu_based_vm_exec_control &
1039                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040                 (vmcs12->secondary_vm_exec_control & bit);
1041 }
1042
1043 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1044 {
1045         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046 }
1047
1048 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1049 {
1050         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1051 }
1052
1053 static inline bool is_exception(u32 intr_info)
1054 {
1055         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1057 }
1058
1059 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1060 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061                         struct vmcs12 *vmcs12,
1062                         u32 reason, unsigned long qualification);
1063
1064 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1065 {
1066         int i;
1067
1068         for (i = 0; i < vmx->nmsrs; ++i)
1069                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1070                         return i;
1071         return -1;
1072 }
1073
1074 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1075 {
1076     struct {
1077         u64 vpid : 16;
1078         u64 rsvd : 48;
1079         u64 gva;
1080     } operand = { vpid, 0, gva };
1081
1082     asm volatile (__ex(ASM_VMX_INVVPID)
1083                   /* CF==1 or ZF==1 --> rc = -1 */
1084                   "; ja 1f ; ud2 ; 1:"
1085                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1086 }
1087
1088 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1089 {
1090         struct {
1091                 u64 eptp, gpa;
1092         } operand = {eptp, gpa};
1093
1094         asm volatile (__ex(ASM_VMX_INVEPT)
1095                         /* CF==1 or ZF==1 --> rc = -1 */
1096                         "; ja 1f ; ud2 ; 1:\n"
1097                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1098 }
1099
1100 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1101 {
1102         int i;
1103
1104         i = __find_msr_index(vmx, msr);
1105         if (i >= 0)
1106                 return &vmx->guest_msrs[i];
1107         return NULL;
1108 }
1109
1110 static void vmcs_clear(struct vmcs *vmcs)
1111 {
1112         u64 phys_addr = __pa(vmcs);
1113         u8 error;
1114
1115         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1116                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1117                       : "cc", "memory");
1118         if (error)
1119                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1120                        vmcs, phys_addr);
1121 }
1122
1123 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1124 {
1125         vmcs_clear(loaded_vmcs->vmcs);
1126         loaded_vmcs->cpu = -1;
1127         loaded_vmcs->launched = 0;
1128 }
1129
1130 static void vmcs_load(struct vmcs *vmcs)
1131 {
1132         u64 phys_addr = __pa(vmcs);
1133         u8 error;
1134
1135         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1136                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1137                         : "cc", "memory");
1138         if (error)
1139                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1140                        vmcs, phys_addr);
1141 }
1142
1143 #ifdef CONFIG_KEXEC
1144 /*
1145  * This bitmap is used to indicate whether the vmclear
1146  * operation is enabled on all cpus. All disabled by
1147  * default.
1148  */
1149 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1150
1151 static inline void crash_enable_local_vmclear(int cpu)
1152 {
1153         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154 }
1155
1156 static inline void crash_disable_local_vmclear(int cpu)
1157 {
1158         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159 }
1160
1161 static inline int crash_local_vmclear_enabled(int cpu)
1162 {
1163         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164 }
1165
1166 static void crash_vmclear_local_loaded_vmcss(void)
1167 {
1168         int cpu = raw_smp_processor_id();
1169         struct loaded_vmcs *v;
1170
1171         if (!crash_local_vmclear_enabled(cpu))
1172                 return;
1173
1174         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175                             loaded_vmcss_on_cpu_link)
1176                 vmcs_clear(v->vmcs);
1177 }
1178 #else
1179 static inline void crash_enable_local_vmclear(int cpu) { }
1180 static inline void crash_disable_local_vmclear(int cpu) { }
1181 #endif /* CONFIG_KEXEC */
1182
1183 static void __loaded_vmcs_clear(void *arg)
1184 {
1185         struct loaded_vmcs *loaded_vmcs = arg;
1186         int cpu = raw_smp_processor_id();
1187
1188         if (loaded_vmcs->cpu != cpu)
1189                 return; /* vcpu migration can race with cpu offline */
1190         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1191                 per_cpu(current_vmcs, cpu) = NULL;
1192         crash_disable_local_vmclear(cpu);
1193         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1194
1195         /*
1196          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197          * is before setting loaded_vmcs->vcpu to -1 which is done in
1198          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199          * then adds the vmcs into percpu list before it is deleted.
1200          */
1201         smp_wmb();
1202
1203         loaded_vmcs_init(loaded_vmcs);
1204         crash_enable_local_vmclear(cpu);
1205 }
1206
1207 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1208 {
1209         int cpu = loaded_vmcs->cpu;
1210
1211         if (cpu != -1)
1212                 smp_call_function_single(cpu,
1213                          __loaded_vmcs_clear, loaded_vmcs, 1);
1214 }
1215
1216 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1217 {
1218         if (vmx->vpid == 0)
1219                 return;
1220
1221         if (cpu_has_vmx_invvpid_single())
1222                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1223 }
1224
1225 static inline void vpid_sync_vcpu_global(void)
1226 {
1227         if (cpu_has_vmx_invvpid_global())
1228                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1229 }
1230
1231 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1232 {
1233         if (cpu_has_vmx_invvpid_single())
1234                 vpid_sync_vcpu_single(vmx);
1235         else
1236                 vpid_sync_vcpu_global();
1237 }
1238
1239 static inline void ept_sync_global(void)
1240 {
1241         if (cpu_has_vmx_invept_global())
1242                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1243 }
1244
1245 static inline void ept_sync_context(u64 eptp)
1246 {
1247         if (enable_ept) {
1248                 if (cpu_has_vmx_invept_context())
1249                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1250                 else
1251                         ept_sync_global();
1252         }
1253 }
1254
1255 static __always_inline unsigned long vmcs_readl(unsigned long field)
1256 {
1257         unsigned long value;
1258
1259         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260                       : "=a"(value) : "d"(field) : "cc");
1261         return value;
1262 }
1263
1264 static __always_inline u16 vmcs_read16(unsigned long field)
1265 {
1266         return vmcs_readl(field);
1267 }
1268
1269 static __always_inline u32 vmcs_read32(unsigned long field)
1270 {
1271         return vmcs_readl(field);
1272 }
1273
1274 static __always_inline u64 vmcs_read64(unsigned long field)
1275 {
1276 #ifdef CONFIG_X86_64
1277         return vmcs_readl(field);
1278 #else
1279         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1280 #endif
1281 }
1282
1283 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1284 {
1285         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1287         dump_stack();
1288 }
1289
1290 static void vmcs_writel(unsigned long field, unsigned long value)
1291 {
1292         u8 error;
1293
1294         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1295                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1296         if (unlikely(error))
1297                 vmwrite_error(field, value);
1298 }
1299
1300 static void vmcs_write16(unsigned long field, u16 value)
1301 {
1302         vmcs_writel(field, value);
1303 }
1304
1305 static void vmcs_write32(unsigned long field, u32 value)
1306 {
1307         vmcs_writel(field, value);
1308 }
1309
1310 static void vmcs_write64(unsigned long field, u64 value)
1311 {
1312         vmcs_writel(field, value);
1313 #ifndef CONFIG_X86_64
1314         asm volatile ("");
1315         vmcs_writel(field+1, value >> 32);
1316 #endif
1317 }
1318
1319 static void vmcs_clear_bits(unsigned long field, u32 mask)
1320 {
1321         vmcs_writel(field, vmcs_readl(field) & ~mask);
1322 }
1323
1324 static void vmcs_set_bits(unsigned long field, u32 mask)
1325 {
1326         vmcs_writel(field, vmcs_readl(field) | mask);
1327 }
1328
1329 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1330 {
1331         vmx->segment_cache.bitmask = 0;
1332 }
1333
1334 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1335                                        unsigned field)
1336 {
1337         bool ret;
1338         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1339
1340         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342                 vmx->segment_cache.bitmask = 0;
1343         }
1344         ret = vmx->segment_cache.bitmask & mask;
1345         vmx->segment_cache.bitmask |= mask;
1346         return ret;
1347 }
1348
1349 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1350 {
1351         u16 *p = &vmx->segment_cache.seg[seg].selector;
1352
1353         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1355         return *p;
1356 }
1357
1358 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1359 {
1360         ulong *p = &vmx->segment_cache.seg[seg].base;
1361
1362         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1364         return *p;
1365 }
1366
1367 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1368 {
1369         u32 *p = &vmx->segment_cache.seg[seg].limit;
1370
1371         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1373         return *p;
1374 }
1375
1376 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1377 {
1378         u32 *p = &vmx->segment_cache.seg[seg].ar;
1379
1380         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1382         return *p;
1383 }
1384
1385 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1386 {
1387         u32 eb;
1388
1389         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391         if ((vcpu->guest_debug &
1392              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394                 eb |= 1u << BP_VECTOR;
1395         if (to_vmx(vcpu)->rmode.vm86_active)
1396                 eb = ~0;
1397         if (enable_ept)
1398                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1399         if (vcpu->fpu_active)
1400                 eb &= ~(1u << NM_VECTOR);
1401
1402         /* When we are running a nested L2 guest and L1 specified for it a
1403          * certain exception bitmap, we must trap the same exceptions and pass
1404          * them to L1. When running L2, we will only handle the exceptions
1405          * specified above if L1 did not want them.
1406          */
1407         if (is_guest_mode(vcpu))
1408                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1409
1410         vmcs_write32(EXCEPTION_BITMAP, eb);
1411 }
1412
1413 static void clear_atomic_switch_msr_special(unsigned long entry,
1414                 unsigned long exit)
1415 {
1416         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1418 }
1419
1420 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1421 {
1422         unsigned i;
1423         struct msr_autoload *m = &vmx->msr_autoload;
1424
1425         switch (msr) {
1426         case MSR_EFER:
1427                 if (cpu_has_load_ia32_efer) {
1428                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429                                         VM_EXIT_LOAD_IA32_EFER);
1430                         return;
1431                 }
1432                 break;
1433         case MSR_CORE_PERF_GLOBAL_CTRL:
1434                 if (cpu_has_load_perf_global_ctrl) {
1435                         clear_atomic_switch_msr_special(
1436                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1438                         return;
1439                 }
1440                 break;
1441         }
1442
1443         for (i = 0; i < m->nr; ++i)
1444                 if (m->guest[i].index == msr)
1445                         break;
1446
1447         if (i == m->nr)
1448                 return;
1449         --m->nr;
1450         m->guest[i] = m->guest[m->nr];
1451         m->host[i] = m->host[m->nr];
1452         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1454 }
1455
1456 static void add_atomic_switch_msr_special(unsigned long entry,
1457                 unsigned long exit, unsigned long guest_val_vmcs,
1458                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1459 {
1460         vmcs_write64(guest_val_vmcs, guest_val);
1461         vmcs_write64(host_val_vmcs, host_val);
1462         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1464 }
1465
1466 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467                                   u64 guest_val, u64 host_val)
1468 {
1469         unsigned i;
1470         struct msr_autoload *m = &vmx->msr_autoload;
1471
1472         switch (msr) {
1473         case MSR_EFER:
1474                 if (cpu_has_load_ia32_efer) {
1475                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476                                         VM_EXIT_LOAD_IA32_EFER,
1477                                         GUEST_IA32_EFER,
1478                                         HOST_IA32_EFER,
1479                                         guest_val, host_val);
1480                         return;
1481                 }
1482                 break;
1483         case MSR_CORE_PERF_GLOBAL_CTRL:
1484                 if (cpu_has_load_perf_global_ctrl) {
1485                         add_atomic_switch_msr_special(
1486                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1489                                         HOST_IA32_PERF_GLOBAL_CTRL,
1490                                         guest_val, host_val);
1491                         return;
1492                 }
1493                 break;
1494         }
1495
1496         for (i = 0; i < m->nr; ++i)
1497                 if (m->guest[i].index == msr)
1498                         break;
1499
1500         if (i == NR_AUTOLOAD_MSRS) {
1501                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1502                                 "Can't add msr %x\n", msr);
1503                 return;
1504         } else if (i == m->nr) {
1505                 ++m->nr;
1506                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1508         }
1509
1510         m->guest[i].index = msr;
1511         m->guest[i].value = guest_val;
1512         m->host[i].index = msr;
1513         m->host[i].value = host_val;
1514 }
1515
1516 static void reload_tss(void)
1517 {
1518         /*
1519          * VT restores TR but not its size.  Useless.
1520          */
1521         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1522         struct desc_struct *descs;
1523
1524         descs = (void *)gdt->address;
1525         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1526         load_TR_desc();
1527 }
1528
1529 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1530 {
1531         u64 guest_efer;
1532         u64 ignore_bits;
1533
1534         guest_efer = vmx->vcpu.arch.efer;
1535
1536         /*
1537          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1538          * outside long mode
1539          */
1540         ignore_bits = EFER_NX | EFER_SCE;
1541 #ifdef CONFIG_X86_64
1542         ignore_bits |= EFER_LMA | EFER_LME;
1543         /* SCE is meaningful only in long mode on Intel */
1544         if (guest_efer & EFER_LMA)
1545                 ignore_bits &= ~(u64)EFER_SCE;
1546 #endif
1547         guest_efer &= ~ignore_bits;
1548         guest_efer |= host_efer & ignore_bits;
1549         vmx->guest_msrs[efer_offset].data = guest_efer;
1550         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1551
1552         clear_atomic_switch_msr(vmx, MSR_EFER);
1553         /* On ept, can't emulate nx, and must switch nx atomically */
1554         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555                 guest_efer = vmx->vcpu.arch.efer;
1556                 if (!(guest_efer & EFER_LMA))
1557                         guest_efer &= ~EFER_LME;
1558                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1559                 return false;
1560         }
1561
1562         return true;
1563 }
1564
1565 static unsigned long segment_base(u16 selector)
1566 {
1567         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1568         struct desc_struct *d;
1569         unsigned long table_base;
1570         unsigned long v;
1571
1572         if (!(selector & ~3))
1573                 return 0;
1574
1575         table_base = gdt->address;
1576
1577         if (selector & 4) {           /* from ldt */
1578                 u16 ldt_selector = kvm_read_ldt();
1579
1580                 if (!(ldt_selector & ~3))
1581                         return 0;
1582
1583                 table_base = segment_base(ldt_selector);
1584         }
1585         d = (struct desc_struct *)(table_base + (selector & ~7));
1586         v = get_desc_base(d);
1587 #ifdef CONFIG_X86_64
1588        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1590 #endif
1591         return v;
1592 }
1593
1594 static inline unsigned long kvm_read_tr_base(void)
1595 {
1596         u16 tr;
1597         asm("str %0" : "=g"(tr));
1598         return segment_base(tr);
1599 }
1600
1601 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1602 {
1603         struct vcpu_vmx *vmx = to_vmx(vcpu);
1604         int i;
1605
1606         if (vmx->host_state.loaded)
1607                 return;
1608
1609         vmx->host_state.loaded = 1;
1610         /*
1611          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1612          * allow segment selectors with cpl > 0 or ti == 1.
1613          */
1614         vmx->host_state.ldt_sel = kvm_read_ldt();
1615         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1616         savesegment(fs, vmx->host_state.fs_sel);
1617         if (!(vmx->host_state.fs_sel & 7)) {
1618                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1619                 vmx->host_state.fs_reload_needed = 0;
1620         } else {
1621                 vmcs_write16(HOST_FS_SELECTOR, 0);
1622                 vmx->host_state.fs_reload_needed = 1;
1623         }
1624         savesegment(gs, vmx->host_state.gs_sel);
1625         if (!(vmx->host_state.gs_sel & 7))
1626                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1627         else {
1628                 vmcs_write16(HOST_GS_SELECTOR, 0);
1629                 vmx->host_state.gs_ldt_reload_needed = 1;
1630         }
1631
1632 #ifdef CONFIG_X86_64
1633         savesegment(ds, vmx->host_state.ds_sel);
1634         savesegment(es, vmx->host_state.es_sel);
1635 #endif
1636
1637 #ifdef CONFIG_X86_64
1638         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1640 #else
1641         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1643 #endif
1644
1645 #ifdef CONFIG_X86_64
1646         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647         if (is_long_mode(&vmx->vcpu))
1648                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1649 #endif
1650         for (i = 0; i < vmx->save_nmsrs; ++i)
1651                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1652                                    vmx->guest_msrs[i].data,
1653                                    vmx->guest_msrs[i].mask);
1654 }
1655
1656 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1657 {
1658         if (!vmx->host_state.loaded)
1659                 return;
1660
1661         ++vmx->vcpu.stat.host_state_reload;
1662         vmx->host_state.loaded = 0;
1663 #ifdef CONFIG_X86_64
1664         if (is_long_mode(&vmx->vcpu))
1665                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1666 #endif
1667         if (vmx->host_state.gs_ldt_reload_needed) {
1668                 kvm_load_ldt(vmx->host_state.ldt_sel);
1669 #ifdef CONFIG_X86_64
1670                 load_gs_index(vmx->host_state.gs_sel);
1671 #else
1672                 loadsegment(gs, vmx->host_state.gs_sel);
1673 #endif
1674         }
1675         if (vmx->host_state.fs_reload_needed)
1676                 loadsegment(fs, vmx->host_state.fs_sel);
1677 #ifdef CONFIG_X86_64
1678         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679                 loadsegment(ds, vmx->host_state.ds_sel);
1680                 loadsegment(es, vmx->host_state.es_sel);
1681         }
1682 #endif
1683         reload_tss();
1684 #ifdef CONFIG_X86_64
1685         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1686 #endif
1687         /*
1688          * If the FPU is not active (through the host task or
1689          * the guest vcpu), then restore the cr0.TS bit.
1690          */
1691         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1692                 stts();
1693         load_gdt(&__get_cpu_var(host_gdt));
1694 }
1695
1696 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1697 {
1698         preempt_disable();
1699         __vmx_load_host_state(vmx);
1700         preempt_enable();
1701 }
1702
1703 /*
1704  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705  * vcpu mutex is already taken.
1706  */
1707 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1708 {
1709         struct vcpu_vmx *vmx = to_vmx(vcpu);
1710         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1711
1712         if (!vmm_exclusive)
1713                 kvm_cpu_vmxon(phys_addr);
1714         else if (vmx->loaded_vmcs->cpu != cpu)
1715                 loaded_vmcs_clear(vmx->loaded_vmcs);
1716
1717         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719                 vmcs_load(vmx->loaded_vmcs->vmcs);
1720         }
1721
1722         if (vmx->loaded_vmcs->cpu != cpu) {
1723                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1724                 unsigned long sysenter_esp;
1725
1726                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1727                 local_irq_disable();
1728                 crash_disable_local_vmclear(cpu);
1729
1730                 /*
1731                  * Read loaded_vmcs->cpu should be before fetching
1732                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733                  * See the comments in __loaded_vmcs_clear().
1734                  */
1735                 smp_rmb();
1736
1737                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1739                 crash_enable_local_vmclear(cpu);
1740                 local_irq_enable();
1741
1742                 /*
1743                  * Linux uses per-cpu TSS and GDT, so set these when switching
1744                  * processors.
1745                  */
1746                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1747                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1748
1749                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1751                 vmx->loaded_vmcs->cpu = cpu;
1752         }
1753 }
1754
1755 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1756 {
1757         __vmx_load_host_state(to_vmx(vcpu));
1758         if (!vmm_exclusive) {
1759                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1760                 vcpu->cpu = -1;
1761                 kvm_cpu_vmxoff();
1762         }
1763 }
1764
1765 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1766 {
1767         ulong cr0;
1768
1769         if (vcpu->fpu_active)
1770                 return;
1771         vcpu->fpu_active = 1;
1772         cr0 = vmcs_readl(GUEST_CR0);
1773         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775         vmcs_writel(GUEST_CR0, cr0);
1776         update_exception_bitmap(vcpu);
1777         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1778         if (is_guest_mode(vcpu))
1779                 vcpu->arch.cr0_guest_owned_bits &=
1780                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1781         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1782 }
1783
1784 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1785
1786 /*
1787  * Return the cr0 value that a nested guest would read. This is a combination
1788  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789  * its hypervisor (cr0_read_shadow).
1790  */
1791 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1792 {
1793         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1795 }
1796 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1797 {
1798         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1800 }
1801
1802 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1803 {
1804         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805          * set this *before* calling this function.
1806          */
1807         vmx_decache_cr0_guest_bits(vcpu);
1808         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1809         update_exception_bitmap(vcpu);
1810         vcpu->arch.cr0_guest_owned_bits = 0;
1811         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1812         if (is_guest_mode(vcpu)) {
1813                 /*
1814                  * L1's specified read shadow might not contain the TS bit,
1815                  * so now that we turned on shadowing of this bit, we need to
1816                  * set this bit of the shadow. Like in nested_vmx_run we need
1817                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818                  * up-to-date here because we just decached cr0.TS (and we'll
1819                  * only update vmcs12->guest_cr0 on nested exit).
1820                  */
1821                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823                         (vcpu->arch.cr0 & X86_CR0_TS);
1824                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1825         } else
1826                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1827 }
1828
1829 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1830 {
1831         unsigned long rflags, save_rflags;
1832
1833         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835                 rflags = vmcs_readl(GUEST_RFLAGS);
1836                 if (to_vmx(vcpu)->rmode.vm86_active) {
1837                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1840                 }
1841                 to_vmx(vcpu)->rflags = rflags;
1842         }
1843         return to_vmx(vcpu)->rflags;
1844 }
1845
1846 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1847 {
1848         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849         to_vmx(vcpu)->rflags = rflags;
1850         if (to_vmx(vcpu)->rmode.vm86_active) {
1851                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1852                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1853         }
1854         vmcs_writel(GUEST_RFLAGS, rflags);
1855 }
1856
1857 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858 {
1859         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860         int ret = 0;
1861
1862         if (interruptibility & GUEST_INTR_STATE_STI)
1863                 ret |= KVM_X86_SHADOW_INT_STI;
1864         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1865                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1866
1867         return ret & mask;
1868 }
1869
1870 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1871 {
1872         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873         u32 interruptibility = interruptibility_old;
1874
1875         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1876
1877         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1878                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1879         else if (mask & KVM_X86_SHADOW_INT_STI)
1880                 interruptibility |= GUEST_INTR_STATE_STI;
1881
1882         if ((interruptibility != interruptibility_old))
1883                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1884 }
1885
1886 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1887 {
1888         unsigned long rip;
1889
1890         rip = kvm_rip_read(vcpu);
1891         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1892         kvm_rip_write(vcpu, rip);
1893
1894         /* skipping an emulated instruction also counts */
1895         vmx_set_interrupt_shadow(vcpu, 0);
1896 }
1897
1898 /*
1899  * KVM wants to inject page-faults which it got to the guest. This function
1900  * checks whether in a nested guest, we need to inject them to L1 or L2.
1901  * This function assumes it is called with the exit reason in vmcs02 being
1902  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1903  * is running).
1904  */
1905 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1906 {
1907         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908
1909         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1910         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1911                 return 0;
1912
1913         nested_vmx_vmexit(vcpu);
1914         return 1;
1915 }
1916
1917 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1918                                 bool has_error_code, u32 error_code,
1919                                 bool reinject)
1920 {
1921         struct vcpu_vmx *vmx = to_vmx(vcpu);
1922         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1923
1924         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1925             !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1926                 return;
1927
1928         if (has_error_code) {
1929                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1930                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1931         }
1932
1933         if (vmx->rmode.vm86_active) {
1934                 int inc_eip = 0;
1935                 if (kvm_exception_is_soft(nr))
1936                         inc_eip = vcpu->arch.event_exit_inst_len;
1937                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1938                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1939                 return;
1940         }
1941
1942         if (kvm_exception_is_soft(nr)) {
1943                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1944                              vmx->vcpu.arch.event_exit_inst_len);
1945                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1946         } else
1947                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1948
1949         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1950 }
1951
1952 static bool vmx_rdtscp_supported(void)
1953 {
1954         return cpu_has_vmx_rdtscp();
1955 }
1956
1957 static bool vmx_invpcid_supported(void)
1958 {
1959         return cpu_has_vmx_invpcid() && enable_ept;
1960 }
1961
1962 /*
1963  * Swap MSR entry in host/guest MSR entry array.
1964  */
1965 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1966 {
1967         struct shared_msr_entry tmp;
1968
1969         tmp = vmx->guest_msrs[to];
1970         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1971         vmx->guest_msrs[from] = tmp;
1972 }
1973
1974 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1975 {
1976         unsigned long *msr_bitmap;
1977
1978         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1979                 if (is_long_mode(vcpu))
1980                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1981                 else
1982                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1983         } else {
1984                 if (is_long_mode(vcpu))
1985                         msr_bitmap = vmx_msr_bitmap_longmode;
1986                 else
1987                         msr_bitmap = vmx_msr_bitmap_legacy;
1988         }
1989
1990         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1991 }
1992
1993 /*
1994  * Set up the vmcs to automatically save and restore system
1995  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1996  * mode, as fiddling with msrs is very expensive.
1997  */
1998 static void setup_msrs(struct vcpu_vmx *vmx)
1999 {
2000         int save_nmsrs, index;
2001
2002         save_nmsrs = 0;
2003 #ifdef CONFIG_X86_64
2004         if (is_long_mode(&vmx->vcpu)) {
2005                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2006                 if (index >= 0)
2007                         move_msr_up(vmx, index, save_nmsrs++);
2008                 index = __find_msr_index(vmx, MSR_LSTAR);
2009                 if (index >= 0)
2010                         move_msr_up(vmx, index, save_nmsrs++);
2011                 index = __find_msr_index(vmx, MSR_CSTAR);
2012                 if (index >= 0)
2013                         move_msr_up(vmx, index, save_nmsrs++);
2014                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2015                 if (index >= 0 && vmx->rdtscp_enabled)
2016                         move_msr_up(vmx, index, save_nmsrs++);
2017                 /*
2018                  * MSR_STAR is only needed on long mode guests, and only
2019                  * if efer.sce is enabled.
2020                  */
2021                 index = __find_msr_index(vmx, MSR_STAR);
2022                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2023                         move_msr_up(vmx, index, save_nmsrs++);
2024         }
2025 #endif
2026         index = __find_msr_index(vmx, MSR_EFER);
2027         if (index >= 0 && update_transition_efer(vmx, index))
2028                 move_msr_up(vmx, index, save_nmsrs++);
2029
2030         vmx->save_nmsrs = save_nmsrs;
2031
2032         if (cpu_has_vmx_msr_bitmap())
2033                 vmx_set_msr_bitmap(&vmx->vcpu);
2034 }
2035
2036 /*
2037  * reads and returns guest's timestamp counter "register"
2038  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2039  */
2040 static u64 guest_read_tsc(void)
2041 {
2042         u64 host_tsc, tsc_offset;
2043
2044         rdtscll(host_tsc);
2045         tsc_offset = vmcs_read64(TSC_OFFSET);
2046         return host_tsc + tsc_offset;
2047 }
2048
2049 /*
2050  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2051  * counter, even if a nested guest (L2) is currently running.
2052  */
2053 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2054 {
2055         u64 tsc_offset;
2056
2057         tsc_offset = is_guest_mode(vcpu) ?
2058                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2059                 vmcs_read64(TSC_OFFSET);
2060         return host_tsc + tsc_offset;
2061 }
2062
2063 /*
2064  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2065  * software catchup for faster rates on slower CPUs.
2066  */
2067 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2068 {
2069         if (!scale)
2070                 return;
2071
2072         if (user_tsc_khz > tsc_khz) {
2073                 vcpu->arch.tsc_catchup = 1;
2074                 vcpu->arch.tsc_always_catchup = 1;
2075         } else
2076                 WARN(1, "user requested TSC rate below hardware speed\n");
2077 }
2078
2079 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2080 {
2081         return vmcs_read64(TSC_OFFSET);
2082 }
2083
2084 /*
2085  * writes 'offset' into guest's timestamp counter offset register
2086  */
2087 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2088 {
2089         if (is_guest_mode(vcpu)) {
2090                 /*
2091                  * We're here if L1 chose not to trap WRMSR to TSC. According
2092                  * to the spec, this should set L1's TSC; The offset that L1
2093                  * set for L2 remains unchanged, and still needs to be added
2094                  * to the newly set TSC to get L2's TSC.
2095                  */
2096                 struct vmcs12 *vmcs12;
2097                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2098                 /* recalculate vmcs02.TSC_OFFSET: */
2099                 vmcs12 = get_vmcs12(vcpu);
2100                 vmcs_write64(TSC_OFFSET, offset +
2101                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2102                          vmcs12->tsc_offset : 0));
2103         } else {
2104                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2105                                            vmcs_read64(TSC_OFFSET), offset);
2106                 vmcs_write64(TSC_OFFSET, offset);
2107         }
2108 }
2109
2110 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2111 {
2112         u64 offset = vmcs_read64(TSC_OFFSET);
2113
2114         vmcs_write64(TSC_OFFSET, offset + adjustment);
2115         if (is_guest_mode(vcpu)) {
2116                 /* Even when running L2, the adjustment needs to apply to L1 */
2117                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2118         } else
2119                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2120                                            offset + adjustment);
2121 }
2122
2123 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2124 {
2125         return target_tsc - native_read_tsc();
2126 }
2127
2128 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2129 {
2130         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2131         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2132 }
2133
2134 /*
2135  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2136  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2137  * all guests if the "nested" module option is off, and can also be disabled
2138  * for a single guest by disabling its VMX cpuid bit.
2139  */
2140 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2141 {
2142         return nested && guest_cpuid_has_vmx(vcpu);
2143 }
2144
2145 /*
2146  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2147  * returned for the various VMX controls MSRs when nested VMX is enabled.
2148  * The same values should also be used to verify that vmcs12 control fields are
2149  * valid during nested entry from L1 to L2.
2150  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2151  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2152  * bit in the high half is on if the corresponding bit in the control field
2153  * may be on. See also vmx_control_verify().
2154  * TODO: allow these variables to be modified (downgraded) by module options
2155  * or other means.
2156  */
2157 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2158 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2159 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2160 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2161 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2162 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2163 static u32 nested_vmx_ept_caps;
2164 static __init void nested_vmx_setup_ctls_msrs(void)
2165 {
2166         /*
2167          * Note that as a general rule, the high half of the MSRs (bits in
2168          * the control fields which may be 1) should be initialized by the
2169          * intersection of the underlying hardware's MSR (i.e., features which
2170          * can be supported) and the list of features we want to expose -
2171          * because they are known to be properly supported in our code.
2172          * Also, usually, the low half of the MSRs (bits which must be 1) can
2173          * be set to 0, meaning that L1 may turn off any of these bits. The
2174          * reason is that if one of these bits is necessary, it will appear
2175          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2176          * fields of vmcs01 and vmcs02, will turn these bits off - and
2177          * nested_vmx_exit_handled() will not pass related exits to L1.
2178          * These rules have exceptions below.
2179          */
2180
2181         /* pin-based controls */
2182         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2183               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2184         /*
2185          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2186          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2187          */
2188         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2189         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2190                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2191                 PIN_BASED_VMX_PREEMPTION_TIMER;
2192         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2193
2194         /*
2195          * Exit controls
2196          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2197          * 17 must be 1.
2198          */
2199         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2200         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2201 #ifdef CONFIG_X86_64
2202         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2203 #else
2204         nested_vmx_exit_ctls_high = 0;
2205 #endif
2206         nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2207                                       VM_EXIT_LOAD_IA32_EFER);
2208
2209         /* entry controls */
2210         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2211                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2212         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2213         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2214         nested_vmx_entry_ctls_high &=
2215 #ifdef CONFIG_X86_64
2216                 VM_ENTRY_IA32E_MODE |
2217 #endif
2218                 VM_ENTRY_LOAD_IA32_PAT;
2219         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2220                                        VM_ENTRY_LOAD_IA32_EFER);
2221
2222         /* cpu-based controls */
2223         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2224                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2225         nested_vmx_procbased_ctls_low = 0;
2226         nested_vmx_procbased_ctls_high &=
2227                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2228                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2229                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2230                 CPU_BASED_CR3_STORE_EXITING |
2231 #ifdef CONFIG_X86_64
2232                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2233 #endif
2234                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2235                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2236                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2237                 CPU_BASED_PAUSE_EXITING |
2238                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2239         /*
2240          * We can allow some features even when not supported by the
2241          * hardware. For example, L1 can specify an MSR bitmap - and we
2242          * can use it to avoid exits to L1 - even when L0 runs L2
2243          * without MSR bitmaps.
2244          */
2245         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2246
2247         /* secondary cpu-based controls */
2248         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2249                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2250         nested_vmx_secondary_ctls_low = 0;
2251         nested_vmx_secondary_ctls_high &=
2252                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2253                 SECONDARY_EXEC_WBINVD_EXITING;
2254
2255         if (enable_ept) {
2256                 /* nested EPT: emulate EPT also to L1 */
2257                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2258                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2259                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2260                 nested_vmx_ept_caps &= vmx_capability.ept;
2261                 /*
2262                  * Since invept is completely emulated we support both global
2263                  * and context invalidation independent of what host cpu
2264                  * supports
2265                  */
2266                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2267                         VMX_EPT_EXTENT_CONTEXT_BIT;
2268         } else
2269                 nested_vmx_ept_caps = 0;
2270
2271         /* miscellaneous data */
2272         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2273         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2274                 VMX_MISC_SAVE_EFER_LMA;
2275         nested_vmx_misc_high = 0;
2276 }
2277
2278 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2279 {
2280         /*
2281          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2282          */
2283         return ((control & high) | low) == control;
2284 }
2285
2286 static inline u64 vmx_control_msr(u32 low, u32 high)
2287 {
2288         return low | ((u64)high << 32);
2289 }
2290
2291 /*
2292  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2293  * also let it use VMX-specific MSRs.
2294  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2295  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2296  * like all other MSRs).
2297  */
2298 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2299 {
2300         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2301                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2302                 /*
2303                  * According to the spec, processors which do not support VMX
2304                  * should throw a #GP(0) when VMX capability MSRs are read.
2305                  */
2306                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2307                 return 1;
2308         }
2309
2310         switch (msr_index) {
2311         case MSR_IA32_FEATURE_CONTROL:
2312                 if (nested_vmx_allowed(vcpu)) {
2313                         *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2314                         break;
2315                 }
2316                 return 0;
2317         case MSR_IA32_VMX_BASIC:
2318                 /*
2319                  * This MSR reports some information about VMX support. We
2320                  * should return information about the VMX we emulate for the
2321                  * guest, and the VMCS structure we give it - not about the
2322                  * VMX support of the underlying hardware.
2323                  */
2324                 *pdata = VMCS12_REVISION |
2325                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2326                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2327                 break;
2328         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2329         case MSR_IA32_VMX_PINBASED_CTLS:
2330                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2331                                         nested_vmx_pinbased_ctls_high);
2332                 break;
2333         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2334         case MSR_IA32_VMX_PROCBASED_CTLS:
2335                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2336                                         nested_vmx_procbased_ctls_high);
2337                 break;
2338         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2339         case MSR_IA32_VMX_EXIT_CTLS:
2340                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2341                                         nested_vmx_exit_ctls_high);
2342                 break;
2343         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2344         case MSR_IA32_VMX_ENTRY_CTLS:
2345                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2346                                         nested_vmx_entry_ctls_high);
2347                 break;
2348         case MSR_IA32_VMX_MISC:
2349                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2350                                          nested_vmx_misc_high);
2351                 break;
2352         /*
2353          * These MSRs specify bits which the guest must keep fixed (on or off)
2354          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2355          * We picked the standard core2 setting.
2356          */
2357 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2358 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2359         case MSR_IA32_VMX_CR0_FIXED0:
2360                 *pdata = VMXON_CR0_ALWAYSON;
2361                 break;
2362         case MSR_IA32_VMX_CR0_FIXED1:
2363                 *pdata = -1ULL;
2364                 break;
2365         case MSR_IA32_VMX_CR4_FIXED0:
2366                 *pdata = VMXON_CR4_ALWAYSON;
2367                 break;
2368         case MSR_IA32_VMX_CR4_FIXED1:
2369                 *pdata = -1ULL;
2370                 break;
2371         case MSR_IA32_VMX_VMCS_ENUM:
2372                 *pdata = 0x1f;
2373                 break;
2374         case MSR_IA32_VMX_PROCBASED_CTLS2:
2375                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2376                                         nested_vmx_secondary_ctls_high);
2377                 break;
2378         case MSR_IA32_VMX_EPT_VPID_CAP:
2379                 /* Currently, no nested vpid support */
2380                 *pdata = nested_vmx_ept_caps;
2381                 break;
2382         default:
2383                 return 0;
2384         }
2385
2386         return 1;
2387 }
2388
2389 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2390 {
2391         u32 msr_index = msr_info->index;
2392         u64 data = msr_info->data;
2393         bool host_initialized = msr_info->host_initiated;
2394
2395         if (!nested_vmx_allowed(vcpu))
2396                 return 0;
2397
2398         if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2399                 if (!host_initialized &&
2400                                 to_vmx(vcpu)->nested.msr_ia32_feature_control
2401                                 & FEATURE_CONTROL_LOCKED)
2402                         return 0;
2403                 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
2404                 return 1;
2405         }
2406
2407         /*
2408          * No need to treat VMX capability MSRs specially: If we don't handle
2409          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2410          */
2411         return 0;
2412 }
2413
2414 /*
2415  * Reads an msr value (of 'msr_index') into 'pdata'.
2416  * Returns 0 on success, non-0 otherwise.
2417  * Assumes vcpu_load() was already called.
2418  */
2419 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2420 {
2421         u64 data;
2422         struct shared_msr_entry *msr;
2423
2424         if (!pdata) {
2425                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2426                 return -EINVAL;
2427         }
2428
2429         switch (msr_index) {
2430 #ifdef CONFIG_X86_64
2431         case MSR_FS_BASE:
2432                 data = vmcs_readl(GUEST_FS_BASE);
2433                 break;
2434         case MSR_GS_BASE:
2435                 data = vmcs_readl(GUEST_GS_BASE);
2436                 break;
2437         case MSR_KERNEL_GS_BASE:
2438                 vmx_load_host_state(to_vmx(vcpu));
2439                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2440                 break;
2441 #endif
2442         case MSR_EFER:
2443                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2444         case MSR_IA32_TSC:
2445                 data = guest_read_tsc();
2446                 break;
2447         case MSR_IA32_SYSENTER_CS:
2448                 data = vmcs_read32(GUEST_SYSENTER_CS);
2449                 break;
2450         case MSR_IA32_SYSENTER_EIP:
2451                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2452                 break;
2453         case MSR_IA32_SYSENTER_ESP:
2454                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2455                 break;
2456         case MSR_TSC_AUX:
2457                 if (!to_vmx(vcpu)->rdtscp_enabled)
2458                         return 1;
2459                 /* Otherwise falls through */
2460         default:
2461                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2462                         return 0;
2463                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2464                 if (msr) {
2465                         data = msr->data;
2466                         break;
2467                 }
2468                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2469         }
2470
2471         *pdata = data;
2472         return 0;
2473 }
2474
2475 /*
2476  * Writes msr value into into the appropriate "register".
2477  * Returns 0 on success, non-0 otherwise.
2478  * Assumes vcpu_load() was already called.
2479  */
2480 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2481 {
2482         struct vcpu_vmx *vmx = to_vmx(vcpu);
2483         struct shared_msr_entry *msr;
2484         int ret = 0;
2485         u32 msr_index = msr_info->index;
2486         u64 data = msr_info->data;
2487
2488         switch (msr_index) {
2489         case MSR_EFER:
2490                 ret = kvm_set_msr_common(vcpu, msr_info);
2491                 break;
2492 #ifdef CONFIG_X86_64
2493         case MSR_FS_BASE:
2494                 vmx_segment_cache_clear(vmx);
2495                 vmcs_writel(GUEST_FS_BASE, data);
2496                 break;
2497         case MSR_GS_BASE:
2498                 vmx_segment_cache_clear(vmx);
2499                 vmcs_writel(GUEST_GS_BASE, data);
2500                 break;
2501         case MSR_KERNEL_GS_BASE:
2502                 vmx_load_host_state(vmx);
2503                 vmx->msr_guest_kernel_gs_base = data;
2504                 break;
2505 #endif
2506         case MSR_IA32_SYSENTER_CS:
2507                 vmcs_write32(GUEST_SYSENTER_CS, data);
2508                 break;
2509         case MSR_IA32_SYSENTER_EIP:
2510                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2511                 break;
2512         case MSR_IA32_SYSENTER_ESP:
2513                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2514                 break;
2515         case MSR_IA32_TSC:
2516                 kvm_write_tsc(vcpu, msr_info);
2517                 break;
2518         case MSR_IA32_CR_PAT:
2519                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2520                         vmcs_write64(GUEST_IA32_PAT, data);
2521                         vcpu->arch.pat = data;
2522                         break;
2523                 }
2524                 ret = kvm_set_msr_common(vcpu, msr_info);
2525                 break;
2526         case MSR_IA32_TSC_ADJUST:
2527                 ret = kvm_set_msr_common(vcpu, msr_info);
2528                 break;
2529         case MSR_TSC_AUX:
2530                 if (!vmx->rdtscp_enabled)
2531                         return 1;
2532                 /* Check reserved bit, higher 32 bits should be zero */
2533                 if ((data >> 32) != 0)
2534                         return 1;
2535                 /* Otherwise falls through */
2536         default:
2537                 if (vmx_set_vmx_msr(vcpu, msr_info))
2538                         break;
2539                 msr = find_msr_entry(vmx, msr_index);
2540                 if (msr) {
2541                         msr->data = data;
2542                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2543                                 preempt_disable();
2544                                 kvm_set_shared_msr(msr->index, msr->data,
2545                                                    msr->mask);
2546                                 preempt_enable();
2547                         }
2548                         break;
2549                 }
2550                 ret = kvm_set_msr_common(vcpu, msr_info);
2551         }
2552
2553         return ret;
2554 }
2555
2556 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2557 {
2558         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2559         switch (reg) {
2560         case VCPU_REGS_RSP:
2561                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2562                 break;
2563         case VCPU_REGS_RIP:
2564                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2565                 break;
2566         case VCPU_EXREG_PDPTR:
2567                 if (enable_ept)
2568                         ept_save_pdptrs(vcpu);
2569                 break;
2570         default:
2571                 break;
2572         }
2573 }
2574
2575 static __init int cpu_has_kvm_support(void)
2576 {
2577         return cpu_has_vmx();
2578 }
2579
2580 static __init int vmx_disabled_by_bios(void)
2581 {
2582         u64 msr;
2583
2584         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2585         if (msr & FEATURE_CONTROL_LOCKED) {
2586                 /* launched w/ TXT and VMX disabled */
2587                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2588                         && tboot_enabled())
2589                         return 1;
2590                 /* launched w/o TXT and VMX only enabled w/ TXT */
2591                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2592                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2593                         && !tboot_enabled()) {
2594                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2595                                 "activate TXT before enabling KVM\n");
2596                         return 1;
2597                 }
2598                 /* launched w/o TXT and VMX disabled */
2599                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2600                         && !tboot_enabled())
2601                         return 1;
2602         }
2603
2604         return 0;
2605 }
2606
2607 static void kvm_cpu_vmxon(u64 addr)
2608 {
2609         asm volatile (ASM_VMX_VMXON_RAX
2610                         : : "a"(&addr), "m"(addr)
2611                         : "memory", "cc");
2612 }
2613
2614 static int hardware_enable(void *garbage)
2615 {
2616         int cpu = raw_smp_processor_id();
2617         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2618         u64 old, test_bits;
2619
2620         if (read_cr4() & X86_CR4_VMXE)
2621                 return -EBUSY;
2622
2623         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2624
2625         /*
2626          * Now we can enable the vmclear operation in kdump
2627          * since the loaded_vmcss_on_cpu list on this cpu
2628          * has been initialized.
2629          *
2630          * Though the cpu is not in VMX operation now, there
2631          * is no problem to enable the vmclear operation
2632          * for the loaded_vmcss_on_cpu list is empty!
2633          */
2634         crash_enable_local_vmclear(cpu);
2635
2636         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2637
2638         test_bits = FEATURE_CONTROL_LOCKED;
2639         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2640         if (tboot_enabled())
2641                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2642
2643         if ((old & test_bits) != test_bits) {
2644                 /* enable and lock */
2645                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2646         }
2647         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2648
2649         if (vmm_exclusive) {
2650                 kvm_cpu_vmxon(phys_addr);
2651                 ept_sync_global();
2652         }
2653
2654         native_store_gdt(&__get_cpu_var(host_gdt));
2655
2656         return 0;
2657 }
2658
2659 static void vmclear_local_loaded_vmcss(void)
2660 {
2661         int cpu = raw_smp_processor_id();
2662         struct loaded_vmcs *v, *n;
2663
2664         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2665                                  loaded_vmcss_on_cpu_link)
2666                 __loaded_vmcs_clear(v);
2667 }
2668
2669
2670 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2671  * tricks.
2672  */
2673 static void kvm_cpu_vmxoff(void)
2674 {
2675         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2676 }
2677
2678 static void hardware_disable(void *garbage)
2679 {
2680         if (vmm_exclusive) {
2681                 vmclear_local_loaded_vmcss();
2682                 kvm_cpu_vmxoff();
2683         }
2684         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2685 }
2686
2687 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2688                                       u32 msr, u32 *result)
2689 {
2690         u32 vmx_msr_low, vmx_msr_high;
2691         u32 ctl = ctl_min | ctl_opt;
2692
2693         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2694
2695         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2696         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2697
2698         /* Ensure minimum (required) set of control bits are supported. */
2699         if (ctl_min & ~ctl)
2700                 return -EIO;
2701
2702         *result = ctl;
2703         return 0;
2704 }
2705
2706 static __init bool allow_1_setting(u32 msr, u32 ctl)
2707 {
2708         u32 vmx_msr_low, vmx_msr_high;
2709
2710         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2711         return vmx_msr_high & ctl;
2712 }
2713
2714 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2715 {
2716         u32 vmx_msr_low, vmx_msr_high;
2717         u32 min, opt, min2, opt2;
2718         u32 _pin_based_exec_control = 0;
2719         u32 _cpu_based_exec_control = 0;
2720         u32 _cpu_based_2nd_exec_control = 0;
2721         u32 _vmexit_control = 0;
2722         u32 _vmentry_control = 0;
2723
2724         min = CPU_BASED_HLT_EXITING |
2725 #ifdef CONFIG_X86_64
2726               CPU_BASED_CR8_LOAD_EXITING |
2727               CPU_BASED_CR8_STORE_EXITING |
2728 #endif
2729               CPU_BASED_CR3_LOAD_EXITING |
2730               CPU_BASED_CR3_STORE_EXITING |
2731               CPU_BASED_USE_IO_BITMAPS |
2732               CPU_BASED_MOV_DR_EXITING |
2733               CPU_BASED_USE_TSC_OFFSETING |
2734               CPU_BASED_MWAIT_EXITING |
2735               CPU_BASED_MONITOR_EXITING |
2736               CPU_BASED_INVLPG_EXITING |
2737               CPU_BASED_RDPMC_EXITING;
2738
2739         opt = CPU_BASED_TPR_SHADOW |
2740               CPU_BASED_USE_MSR_BITMAPS |
2741               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2742         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2743                                 &_cpu_based_exec_control) < 0)
2744                 return -EIO;
2745 #ifdef CONFIG_X86_64
2746         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2747                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2748                                            ~CPU_BASED_CR8_STORE_EXITING;
2749 #endif
2750         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2751                 min2 = 0;
2752                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2753                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2754                         SECONDARY_EXEC_WBINVD_EXITING |
2755                         SECONDARY_EXEC_ENABLE_VPID |
2756                         SECONDARY_EXEC_ENABLE_EPT |
2757                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2758                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2759                         SECONDARY_EXEC_RDTSCP |
2760                         SECONDARY_EXEC_ENABLE_INVPCID |
2761                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2762                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2763                         SECONDARY_EXEC_SHADOW_VMCS;
2764                 if (adjust_vmx_controls(min2, opt2,
2765                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2766                                         &_cpu_based_2nd_exec_control) < 0)
2767                         return -EIO;
2768         }
2769 #ifndef CONFIG_X86_64
2770         if (!(_cpu_based_2nd_exec_control &
2771                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2772                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2773 #endif
2774
2775         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2776                 _cpu_based_2nd_exec_control &= ~(
2777                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2778                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2779                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2780
2781         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2782                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2783                    enabled */
2784                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2785                                              CPU_BASED_CR3_STORE_EXITING |
2786                                              CPU_BASED_INVLPG_EXITING);
2787                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2788                       vmx_capability.ept, vmx_capability.vpid);
2789         }
2790
2791         min = 0;
2792 #ifdef CONFIG_X86_64
2793         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2794 #endif
2795         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2796                 VM_EXIT_ACK_INTR_ON_EXIT;
2797         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2798                                 &_vmexit_control) < 0)
2799                 return -EIO;
2800
2801         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2802         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2803         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2804                                 &_pin_based_exec_control) < 0)
2805                 return -EIO;
2806
2807         if (!(_cpu_based_2nd_exec_control &
2808                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2809                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2810                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2811
2812         min = 0;
2813         opt = VM_ENTRY_LOAD_IA32_PAT;
2814         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2815                                 &_vmentry_control) < 0)
2816                 return -EIO;
2817
2818         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2819
2820         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2821         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2822                 return -EIO;
2823
2824 #ifdef CONFIG_X86_64
2825         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2826         if (vmx_msr_high & (1u<<16))
2827                 return -EIO;
2828 #endif
2829
2830         /* Require Write-Back (WB) memory type for VMCS accesses. */
2831         if (((vmx_msr_high >> 18) & 15) != 6)
2832                 return -EIO;
2833
2834         vmcs_conf->size = vmx_msr_high & 0x1fff;
2835         vmcs_conf->order = get_order(vmcs_config.size);
2836         vmcs_conf->revision_id = vmx_msr_low;
2837
2838         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2839         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2840         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2841         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2842         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2843
2844         cpu_has_load_ia32_efer =
2845                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2846                                 VM_ENTRY_LOAD_IA32_EFER)
2847                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2848                                    VM_EXIT_LOAD_IA32_EFER);
2849
2850         cpu_has_load_perf_global_ctrl =
2851                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2852                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2853                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2854                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2855
2856         /*
2857          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2858          * but due to arrata below it can't be used. Workaround is to use
2859          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2860          *
2861          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2862          *
2863          * AAK155             (model 26)
2864          * AAP115             (model 30)
2865          * AAT100             (model 37)
2866          * BC86,AAY89,BD102   (model 44)
2867          * BA97               (model 46)
2868          *
2869          */
2870         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2871                 switch (boot_cpu_data.x86_model) {
2872                 case 26:
2873                 case 30:
2874                 case 37:
2875                 case 44:
2876                 case 46:
2877                         cpu_has_load_perf_global_ctrl = false;
2878                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2879                                         "does not work properly. Using workaround\n");
2880                         break;
2881                 default:
2882                         break;
2883                 }
2884         }
2885
2886         return 0;
2887 }
2888
2889 static struct vmcs *alloc_vmcs_cpu(int cpu)
2890 {
2891         int node = cpu_to_node(cpu);
2892         struct page *pages;
2893         struct vmcs *vmcs;
2894
2895         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2896         if (!pages)
2897                 return NULL;
2898         vmcs = page_address(pages);
2899         memset(vmcs, 0, vmcs_config.size);
2900         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2901         return vmcs;
2902 }
2903
2904 static struct vmcs *alloc_vmcs(void)
2905 {
2906         return alloc_vmcs_cpu(raw_smp_processor_id());
2907 }
2908
2909 static void free_vmcs(struct vmcs *vmcs)
2910 {
2911         free_pages((unsigned long)vmcs, vmcs_config.order);
2912 }
2913
2914 /*
2915  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2916  */
2917 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2918 {
2919         if (!loaded_vmcs->vmcs)
2920                 return;
2921         loaded_vmcs_clear(loaded_vmcs);
2922         free_vmcs(loaded_vmcs->vmcs);
2923         loaded_vmcs->vmcs = NULL;
2924 }
2925
2926 static void free_kvm_area(void)
2927 {
2928         int cpu;
2929
2930         for_each_possible_cpu(cpu) {
2931                 free_vmcs(per_cpu(vmxarea, cpu));
2932                 per_cpu(vmxarea, cpu) = NULL;
2933         }
2934 }
2935
2936 static __init int alloc_kvm_area(void)
2937 {
2938         int cpu;
2939
2940         for_each_possible_cpu(cpu) {
2941                 struct vmcs *vmcs;
2942
2943                 vmcs = alloc_vmcs_cpu(cpu);
2944                 if (!vmcs) {
2945                         free_kvm_area();
2946                         return -ENOMEM;
2947                 }
2948
2949                 per_cpu(vmxarea, cpu) = vmcs;
2950         }
2951         return 0;
2952 }
2953
2954 static __init int hardware_setup(void)
2955 {
2956         if (setup_vmcs_config(&vmcs_config) < 0)
2957                 return -EIO;
2958
2959         if (boot_cpu_has(X86_FEATURE_NX))
2960                 kvm_enable_efer_bits(EFER_NX);
2961
2962         if (!cpu_has_vmx_vpid())
2963                 enable_vpid = 0;
2964         if (!cpu_has_vmx_shadow_vmcs())
2965                 enable_shadow_vmcs = 0;
2966
2967         if (!cpu_has_vmx_ept() ||
2968             !cpu_has_vmx_ept_4levels()) {
2969                 enable_ept = 0;
2970                 enable_unrestricted_guest = 0;
2971                 enable_ept_ad_bits = 0;
2972         }
2973
2974         if (!cpu_has_vmx_ept_ad_bits())
2975                 enable_ept_ad_bits = 0;
2976
2977         if (!cpu_has_vmx_unrestricted_guest())
2978                 enable_unrestricted_guest = 0;
2979
2980         if (!cpu_has_vmx_flexpriority())
2981                 flexpriority_enabled = 0;
2982
2983         if (!cpu_has_vmx_tpr_shadow())
2984                 kvm_x86_ops->update_cr8_intercept = NULL;
2985
2986         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2987                 kvm_disable_largepages();
2988
2989         if (!cpu_has_vmx_ple())
2990                 ple_gap = 0;
2991
2992         if (!cpu_has_vmx_apicv())
2993                 enable_apicv = 0;
2994
2995         if (enable_apicv)
2996                 kvm_x86_ops->update_cr8_intercept = NULL;
2997         else {
2998                 kvm_x86_ops->hwapic_irr_update = NULL;
2999                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3000                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3001         }
3002
3003         if (nested)
3004                 nested_vmx_setup_ctls_msrs();
3005
3006         return alloc_kvm_area();
3007 }
3008
3009 static __exit void hardware_unsetup(void)
3010 {
3011         free_kvm_area();
3012 }
3013
3014 static bool emulation_required(struct kvm_vcpu *vcpu)
3015 {
3016         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3017 }
3018
3019 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3020                 struct kvm_segment *save)
3021 {
3022         if (!emulate_invalid_guest_state) {
3023                 /*
3024                  * CS and SS RPL should be equal during guest entry according
3025                  * to VMX spec, but in reality it is not always so. Since vcpu
3026                  * is in the middle of the transition from real mode to
3027                  * protected mode it is safe to assume that RPL 0 is a good
3028                  * default value.
3029                  */
3030                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3031                         save->selector &= ~SELECTOR_RPL_MASK;
3032                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3033                 save->s = 1;
3034         }
3035         vmx_set_segment(vcpu, save, seg);
3036 }
3037
3038 static void enter_pmode(struct kvm_vcpu *vcpu)
3039 {
3040         unsigned long flags;
3041         struct vcpu_vmx *vmx = to_vmx(vcpu);
3042
3043         /*
3044          * Update real mode segment cache. It may be not up-to-date if sement
3045          * register was written while vcpu was in a guest mode.
3046          */
3047         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3048         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3049         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3050         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3051         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3052         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3053
3054         vmx->rmode.vm86_active = 0;
3055
3056         vmx_segment_cache_clear(vmx);
3057
3058         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3059
3060         flags = vmcs_readl(GUEST_RFLAGS);
3061         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3062         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3063         vmcs_writel(GUEST_RFLAGS, flags);
3064
3065         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3066                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3067
3068         update_exception_bitmap(vcpu);
3069
3070         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3071         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3072         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3073         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3074         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3075         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3076
3077         /* CPL is always 0 when CPU enters protected mode */
3078         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3079         vmx->cpl = 0;
3080 }
3081
3082 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3083 {
3084         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3085         struct kvm_segment var = *save;
3086
3087         var.dpl = 0x3;
3088         if (seg == VCPU_SREG_CS)
3089                 var.type = 0x3;
3090
3091         if (!emulate_invalid_guest_state) {
3092                 var.selector = var.base >> 4;
3093                 var.base = var.base & 0xffff0;
3094                 var.limit = 0xffff;
3095                 var.g = 0;
3096                 var.db = 0;
3097                 var.present = 1;
3098                 var.s = 1;
3099                 var.l = 0;
3100                 var.unusable = 0;
3101                 var.type = 0x3;
3102                 var.avl = 0;
3103                 if (save->base & 0xf)
3104                         printk_once(KERN_WARNING "kvm: segment base is not "
3105                                         "paragraph aligned when entering "
3106                                         "protected mode (seg=%d)", seg);
3107         }
3108
3109         vmcs_write16(sf->selector, var.selector);
3110         vmcs_write32(sf->base, var.base);
3111         vmcs_write32(sf->limit, var.limit);
3112         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3113 }
3114
3115 static void enter_rmode(struct kvm_vcpu *vcpu)
3116 {
3117         unsigned long flags;
3118         struct vcpu_vmx *vmx = to_vmx(vcpu);
3119
3120         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3121         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3122         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3123         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3124         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3125         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3126         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3127
3128         vmx->rmode.vm86_active = 1;
3129
3130         /*
3131          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3132          * vcpu. Warn the user that an update is overdue.
3133          */
3134         if (!vcpu->kvm->arch.tss_addr)
3135                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3136                              "called before entering vcpu\n");
3137
3138         vmx_segment_cache_clear(vmx);
3139
3140         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3141         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3142         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3143
3144         flags = vmcs_readl(GUEST_RFLAGS);
3145         vmx->rmode.save_rflags = flags;
3146
3147         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3148
3149         vmcs_writel(GUEST_RFLAGS, flags);
3150         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3151         update_exception_bitmap(vcpu);
3152
3153         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3154         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3155         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3156         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3157         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3158         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3159
3160         kvm_mmu_reset_context(vcpu);
3161 }
3162
3163 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3164 {
3165         struct vcpu_vmx *vmx = to_vmx(vcpu);
3166         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3167
3168         if (!msr)
3169                 return;
3170
3171         /*
3172          * Force kernel_gs_base reloading before EFER changes, as control
3173          * of this msr depends on is_long_mode().
3174          */
3175         vmx_load_host_state(to_vmx(vcpu));
3176         vcpu->arch.efer = efer;
3177         if (efer & EFER_LMA) {
3178                 vmcs_write32(VM_ENTRY_CONTROLS,
3179                              vmcs_read32(VM_ENTRY_CONTROLS) |
3180                              VM_ENTRY_IA32E_MODE);
3181                 msr->data = efer;
3182         } else {
3183                 vmcs_write32(VM_ENTRY_CONTROLS,
3184                              vmcs_read32(VM_ENTRY_CONTROLS) &
3185                              ~VM_ENTRY_IA32E_MODE);
3186
3187                 msr->data = efer & ~EFER_LME;
3188         }
3189         setup_msrs(vmx);
3190 }
3191
3192 #ifdef CONFIG_X86_64
3193
3194 static void enter_lmode(struct kvm_vcpu *vcpu)
3195 {
3196         u32 guest_tr_ar;
3197
3198         vmx_segment_cache_clear(to_vmx(vcpu));
3199
3200         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3201         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3202                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3203                                      __func__);
3204                 vmcs_write32(GUEST_TR_AR_BYTES,
3205                              (guest_tr_ar & ~AR_TYPE_MASK)
3206                              | AR_TYPE_BUSY_64_TSS);
3207         }
3208         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3209 }
3210
3211 static void exit_lmode(struct kvm_vcpu *vcpu)
3212 {
3213         vmcs_write32(VM_ENTRY_CONTROLS,
3214                      vmcs_read32(VM_ENTRY_CONTROLS)
3215                      & ~VM_ENTRY_IA32E_MODE);
3216         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3217 }
3218
3219 #endif
3220
3221 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3222 {
3223         vpid_sync_context(to_vmx(vcpu));
3224         if (enable_ept) {
3225                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3226                         return;
3227                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3228         }
3229 }
3230
3231 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3232 {
3233         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3234
3235         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3236         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3237 }
3238
3239 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3240 {
3241         if (enable_ept && is_paging(vcpu))
3242                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3243         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3244 }
3245
3246 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3247 {
3248         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3249
3250         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3251         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3252 }
3253
3254 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3255 {
3256         if (!test_bit(VCPU_EXREG_PDPTR,
3257                       (unsigned long *)&vcpu->arch.regs_dirty))
3258                 return;
3259
3260         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3261                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3262                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3263                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3264                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3265         }
3266 }
3267
3268 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3269 {
3270         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3271                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3272                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3273                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3274                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3275         }
3276
3277         __set_bit(VCPU_EXREG_PDPTR,
3278                   (unsigned long *)&vcpu->arch.regs_avail);
3279         __set_bit(VCPU_EXREG_PDPTR,
3280                   (unsigned long *)&vcpu->arch.regs_dirty);
3281 }
3282
3283 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3284
3285 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3286                                         unsigned long cr0,
3287                                         struct kvm_vcpu *vcpu)
3288 {
3289         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3290                 vmx_decache_cr3(vcpu);
3291         if (!(cr0 & X86_CR0_PG)) {
3292                 /* From paging/starting to nonpaging */
3293                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3294                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3295                              (CPU_BASED_CR3_LOAD_EXITING |
3296                               CPU_BASED_CR3_STORE_EXITING));
3297                 vcpu->arch.cr0 = cr0;
3298                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3299         } else if (!is_paging(vcpu)) {
3300                 /* From nonpaging to paging */
3301                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3302                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3303                              ~(CPU_BASED_CR3_LOAD_EXITING |
3304                                CPU_BASED_CR3_STORE_EXITING));
3305                 vcpu->arch.cr0 = cr0;
3306                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3307         }
3308
3309         if (!(cr0 & X86_CR0_WP))
3310                 *hw_cr0 &= ~X86_CR0_WP;
3311 }
3312
3313 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3314 {
3315         struct vcpu_vmx *vmx = to_vmx(vcpu);
3316         unsigned long hw_cr0;
3317
3318         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3319         if (enable_unrestricted_guest)
3320                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3321         else {
3322                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3323
3324                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3325                         enter_pmode(vcpu);
3326
3327                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3328                         enter_rmode(vcpu);
3329         }
3330
3331 #ifdef CONFIG_X86_64
3332         if (vcpu->arch.efer & EFER_LME) {
3333                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3334                         enter_lmode(vcpu);
3335                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3336                         exit_lmode(vcpu);
3337         }
3338 #endif
3339
3340         if (enable_ept)
3341                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3342
3343         if (!vcpu->fpu_active)
3344                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3345
3346         vmcs_writel(CR0_READ_SHADOW, cr0);
3347         vmcs_writel(GUEST_CR0, hw_cr0);
3348         vcpu->arch.cr0 = cr0;
3349
3350         /* depends on vcpu->arch.cr0 to be set to a new value */
3351         vmx->emulation_required = emulation_required(vcpu);
3352 }
3353
3354 static u64 construct_eptp(unsigned long root_hpa)
3355 {
3356         u64 eptp;
3357
3358         /* TODO write the value reading from MSR */
3359         eptp = VMX_EPT_DEFAULT_MT |
3360                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3361         if (enable_ept_ad_bits)
3362                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3363         eptp |= (root_hpa & PAGE_MASK);
3364
3365         return eptp;
3366 }
3367
3368 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3369 {
3370         unsigned long guest_cr3;
3371         u64 eptp;
3372
3373         guest_cr3 = cr3;
3374         if (enable_ept) {
3375                 eptp = construct_eptp(cr3);
3376                 vmcs_write64(EPT_POINTER, eptp);
3377                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3378                         vcpu->kvm->arch.ept_identity_map_addr;
3379                 ept_load_pdptrs(vcpu);
3380         }
3381
3382         vmx_flush_tlb(vcpu);
3383         vmcs_writel(GUEST_CR3, guest_cr3);
3384 }
3385
3386 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3387 {
3388         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3389                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3390
3391         if (cr4 & X86_CR4_VMXE) {
3392                 /*
3393                  * To use VMXON (and later other VMX instructions), a guest
3394                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3395                  * So basically the check on whether to allow nested VMX
3396                  * is here.
3397                  */
3398                 if (!nested_vmx_allowed(vcpu))
3399                         return 1;
3400         }
3401         if (to_vmx(vcpu)->nested.vmxon &&
3402             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3403                 return 1;
3404
3405         vcpu->arch.cr4 = cr4;
3406         if (enable_ept) {
3407                 if (!is_paging(vcpu)) {
3408                         hw_cr4 &= ~X86_CR4_PAE;
3409                         hw_cr4 |= X86_CR4_PSE;
3410                         /*
3411                          * SMEP is disabled if CPU is in non-paging mode in
3412                          * hardware. However KVM always uses paging mode to
3413                          * emulate guest non-paging mode with TDP.
3414                          * To emulate this behavior, SMEP needs to be manually
3415                          * disabled when guest switches to non-paging mode.
3416                          */
3417                         hw_cr4 &= ~X86_CR4_SMEP;
3418                 } else if (!(cr4 & X86_CR4_PAE)) {
3419                         hw_cr4 &= ~X86_CR4_PAE;
3420                 }
3421         }
3422
3423         vmcs_writel(CR4_READ_SHADOW, cr4);
3424         vmcs_writel(GUEST_CR4, hw_cr4);
3425         return 0;
3426 }
3427
3428 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3429                             struct kvm_segment *var, int seg)
3430 {
3431         struct vcpu_vmx *vmx = to_vmx(vcpu);
3432         u32 ar;
3433
3434         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3435                 *var = vmx->rmode.segs[seg];
3436                 if (seg == VCPU_SREG_TR
3437                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3438                         return;
3439                 var->base = vmx_read_guest_seg_base(vmx, seg);
3440                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3441                 return;
3442         }
3443         var->base = vmx_read_guest_seg_base(vmx, seg);
3444         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3445         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3446         ar = vmx_read_guest_seg_ar(vmx, seg);
3447         var->unusable = (ar >> 16) & 1;
3448         var->type = ar & 15;
3449         var->s = (ar >> 4) & 1;
3450         var->dpl = (ar >> 5) & 3;
3451         /*
3452          * Some userspaces do not preserve unusable property. Since usable
3453          * segment has to be present according to VMX spec we can use present
3454          * property to amend userspace bug by making unusable segment always
3455          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3456          * segment as unusable.
3457          */
3458         var->present = !var->unusable;
3459         var->avl = (ar >> 12) & 1;
3460         var->l = (ar >> 13) & 1;
3461         var->db = (ar >> 14) & 1;
3462         var->g = (ar >> 15) & 1;
3463 }
3464
3465 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3466 {
3467         struct kvm_segment s;
3468
3469         if (to_vmx(vcpu)->rmode.vm86_active) {
3470                 vmx_get_segment(vcpu, &s, seg);
3471                 return s.base;
3472         }
3473         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3474 }
3475
3476 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3477 {
3478         struct vcpu_vmx *vmx = to_vmx(vcpu);
3479
3480         if (!is_protmode(vcpu))
3481                 return 0;
3482
3483         if (!is_long_mode(vcpu)
3484             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3485                 return 3;
3486
3487         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3488                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3489                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3490         }
3491
3492         return vmx->cpl;
3493 }
3494
3495
3496 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3497 {
3498         u32 ar;
3499
3500         if (var->unusable || !var->present)
3501                 ar = 1 << 16;
3502         else {
3503                 ar = var->type & 15;
3504                 ar |= (var->s & 1) << 4;
3505                 ar |= (var->dpl & 3) << 5;
3506                 ar |= (var->present & 1) << 7;
3507                 ar |= (var->avl & 1) << 12;
3508                 ar |= (var->l & 1) << 13;
3509                 ar |= (var->db & 1) << 14;
3510                 ar |= (var->g & 1) << 15;
3511         }
3512
3513         return ar;
3514 }
3515
3516 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3517                             struct kvm_segment *var, int seg)
3518 {
3519         struct vcpu_vmx *vmx = to_vmx(vcpu);
3520         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3521
3522         vmx_segment_cache_clear(vmx);
3523         if (seg == VCPU_SREG_CS)
3524                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3525
3526         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3527                 vmx->rmode.segs[seg] = *var;
3528                 if (seg == VCPU_SREG_TR)
3529                         vmcs_write16(sf->selector, var->selector);
3530                 else if (var->s)
3531                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3532                 goto out;
3533         }
3534
3535         vmcs_writel(sf->base, var->base);
3536         vmcs_write32(sf->limit, var->limit);
3537         vmcs_write16(sf->selector, var->selector);
3538
3539         /*
3540          *   Fix the "Accessed" bit in AR field of segment registers for older
3541          * qemu binaries.
3542          *   IA32 arch specifies that at the time of processor reset the
3543          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3544          * is setting it to 0 in the userland code. This causes invalid guest
3545          * state vmexit when "unrestricted guest" mode is turned on.
3546          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3547          * tree. Newer qemu binaries with that qemu fix would not need this
3548          * kvm hack.
3549          */
3550         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3551                 var->type |= 0x1; /* Accessed */
3552
3553         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3554
3555 out:
3556         vmx->emulation_required |= emulation_required(vcpu);
3557 }
3558
3559 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3560 {
3561         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3562
3563         *db = (ar >> 14) & 1;
3564         *l = (ar >> 13) & 1;
3565 }
3566
3567 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3568 {
3569         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3570         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3571 }
3572
3573 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3574 {
3575         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3576         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3577 }
3578
3579 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3580 {
3581         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3582         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3583 }
3584
3585 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3586 {
3587         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3588         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3589 }
3590
3591 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3592 {
3593         struct kvm_segment var;
3594         u32 ar;
3595
3596         vmx_get_segment(vcpu, &var, seg);
3597         var.dpl = 0x3;
3598         if (seg == VCPU_SREG_CS)
3599                 var.type = 0x3;
3600         ar = vmx_segment_access_rights(&var);
3601
3602         if (var.base != (var.selector << 4))
3603                 return false;
3604         if (var.limit != 0xffff)
3605                 return false;
3606         if (ar != 0xf3)
3607                 return false;
3608
3609         return true;
3610 }
3611
3612 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3613 {
3614         struct kvm_segment cs;
3615         unsigned int cs_rpl;
3616
3617         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3618         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3619
3620         if (cs.unusable)
3621                 return false;
3622         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3623                 return false;
3624         if (!cs.s)
3625                 return false;
3626         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3627                 if (cs.dpl > cs_rpl)
3628                         return false;
3629         } else {
3630                 if (cs.dpl != cs_rpl)
3631                         return false;
3632         }
3633         if (!cs.present)
3634                 return false;
3635
3636         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3637         return true;
3638 }
3639
3640 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3641 {
3642         struct kvm_segment ss;
3643         unsigned int ss_rpl;
3644
3645         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3646         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3647
3648         if (ss.unusable)
3649                 return true;
3650         if (ss.type != 3 && ss.type != 7)
3651                 return false;
3652         if (!ss.s)
3653                 return false;
3654         if (ss.dpl != ss_rpl) /* DPL != RPL */
3655                 return false;
3656         if (!ss.present)
3657                 return false;
3658
3659         return true;
3660 }
3661
3662 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3663 {
3664         struct kvm_segment var;
3665         unsigned int rpl;
3666
3667         vmx_get_segment(vcpu, &var, seg);
3668         rpl = var.selector & SELECTOR_RPL_MASK;
3669
3670         if (var.unusable)
3671                 return true;
3672         if (!var.s)
3673                 return false;
3674         if (!var.present)
3675                 return false;
3676         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3677                 if (var.dpl < rpl) /* DPL < RPL */
3678                         return false;
3679         }
3680
3681         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3682          * rights flags
3683          */
3684         return true;
3685 }
3686
3687 static bool tr_valid(struct kvm_vcpu *vcpu)
3688 {
3689         struct kvm_segment tr;
3690
3691         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3692
3693         if (tr.unusable)
3694                 return false;
3695         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3696                 return false;
3697         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3698                 return false;
3699         if (!tr.present)
3700                 return false;
3701
3702         return true;
3703 }
3704
3705 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3706 {
3707         struct kvm_segment ldtr;
3708
3709         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3710
3711         if (ldtr.unusable)
3712                 return true;
3713         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3714                 return false;
3715         if (ldtr.type != 2)
3716                 return false;
3717         if (!ldtr.present)
3718                 return false;
3719
3720         return true;
3721 }
3722
3723 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3724 {
3725         struct kvm_segment cs, ss;
3726
3727         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3728         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3729
3730         return ((cs.selector & SELECTOR_RPL_MASK) ==
3731                  (ss.selector & SELECTOR_RPL_MASK));
3732 }
3733
3734 /*
3735  * Check if guest state is valid. Returns true if valid, false if
3736  * not.
3737  * We assume that registers are always usable
3738  */
3739 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3740 {
3741         if (enable_unrestricted_guest)
3742                 return true;
3743
3744         /* real mode guest state checks */
3745         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3746                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3747                         return false;
3748                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3749                         return false;
3750                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3751                         return false;
3752                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3753                         return false;
3754                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3755                         return false;
3756                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3757                         return false;
3758         } else {
3759         /* protected mode guest state checks */
3760                 if (!cs_ss_rpl_check(vcpu))
3761                         return false;
3762                 if (!code_segment_valid(vcpu))
3763                         return false;
3764                 if (!stack_segment_valid(vcpu))
3765                         return false;
3766                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3767                         return false;
3768                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3769                         return false;
3770                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3771                         return false;
3772                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3773                         return false;
3774                 if (!tr_valid(vcpu))
3775                         return false;
3776                 if (!ldtr_valid(vcpu))
3777                         return false;
3778         }
3779         /* TODO:
3780          * - Add checks on RIP
3781          * - Add checks on RFLAGS
3782          */
3783
3784         return true;
3785 }
3786
3787 static int init_rmode_tss(struct kvm *kvm)
3788 {
3789         gfn_t fn;
3790         u16 data = 0;
3791         int r, idx, ret = 0;
3792
3793         idx = srcu_read_lock(&kvm->srcu);
3794         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3795         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3796         if (r < 0)
3797                 goto out;
3798         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3799         r = kvm_write_guest_page(kvm, fn++, &data,
3800                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3801         if (r < 0)
3802                 goto out;
3803         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3804         if (r < 0)
3805                 goto out;
3806         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3807         if (r < 0)
3808                 goto out;
3809         data = ~0;
3810         r = kvm_write_guest_page(kvm, fn, &data,
3811                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3812                                  sizeof(u8));
3813         if (r < 0)
3814                 goto out;
3815
3816         ret = 1;
3817 out:
3818         srcu_read_unlock(&kvm->srcu, idx);
3819         return ret;
3820 }
3821
3822 static int init_rmode_identity_map(struct kvm *kvm)
3823 {
3824         int i, idx, r, ret;
3825         pfn_t identity_map_pfn;
3826         u32 tmp;
3827
3828         if (!enable_ept)
3829                 return 1;
3830         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3831                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3832                         "haven't been allocated!\n");
3833                 return 0;
3834         }
3835         if (likely(kvm->arch.ept_identity_pagetable_done))
3836                 return 1;
3837         ret = 0;
3838         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3839         idx = srcu_read_lock(&kvm->srcu);
3840         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3841         if (r < 0)
3842                 goto out;
3843         /* Set up identity-mapping pagetable for EPT in real mode */
3844         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3845                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3846                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3847                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3848                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3849                 if (r < 0)
3850                         goto out;
3851         }
3852         kvm->arch.ept_identity_pagetable_done = true;
3853         ret = 1;
3854 out:
3855         srcu_read_unlock(&kvm->srcu, idx);
3856         return ret;
3857 }
3858
3859 static void seg_setup(int seg)
3860 {
3861         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3862         unsigned int ar;
3863
3864         vmcs_write16(sf->selector, 0);
3865         vmcs_writel(sf->base, 0);
3866         vmcs_write32(sf->limit, 0xffff);
3867         ar = 0x93;
3868         if (seg == VCPU_SREG_CS)
3869                 ar |= 0x08; /* code segment */
3870
3871         vmcs_write32(sf->ar_bytes, ar);
3872 }
3873
3874 static int alloc_apic_access_page(struct kvm *kvm)
3875 {
3876         struct page *page;
3877         struct kvm_userspace_memory_region kvm_userspace_mem;
3878         int r = 0;
3879
3880         mutex_lock(&kvm->slots_lock);
3881         if (kvm->arch.apic_access_page)
3882                 goto out;
3883         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3884         kvm_userspace_mem.flags = 0;
3885         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3886         kvm_userspace_mem.memory_size = PAGE_SIZE;
3887         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3888         if (r)
3889                 goto out;
3890
3891         page = gfn_to_page(kvm, 0xfee00);
3892         if (is_error_page(page)) {
3893                 r = -EFAULT;
3894                 goto out;
3895         }
3896
3897         kvm->arch.apic_access_page = page;
3898 out:
3899         mutex_unlock(&kvm->slots_lock);
3900         return r;
3901 }
3902
3903 static int alloc_identity_pagetable(struct kvm *kvm)
3904 {
3905         struct page *page;
3906         struct kvm_userspace_memory_region kvm_userspace_mem;
3907         int r = 0;
3908
3909         mutex_lock(&kvm->slots_lock);
3910         if (kvm->arch.ept_identity_pagetable)
3911                 goto out;
3912         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3913         kvm_userspace_mem.flags = 0;
3914         kvm_userspace_mem.guest_phys_addr =
3915                 kvm->arch.ept_identity_map_addr;
3916         kvm_userspace_mem.memory_size = PAGE_SIZE;
3917         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3918         if (r)
3919                 goto out;
3920
3921         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3922         if (is_error_page(page)) {
3923                 r = -EFAULT;
3924                 goto out;
3925         }
3926
3927         kvm->arch.ept_identity_pagetable = page;
3928 out:
3929         mutex_unlock(&kvm->slots_lock);
3930         return r;
3931 }
3932
3933 static void allocate_vpid(struct vcpu_vmx *vmx)
3934 {
3935         int vpid;
3936
3937         vmx->vpid = 0;
3938         if (!enable_vpid)
3939                 return;
3940         spin_lock(&vmx_vpid_lock);
3941         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3942         if (vpid < VMX_NR_VPIDS) {
3943                 vmx->vpid = vpid;
3944                 __set_bit(vpid, vmx_vpid_bitmap);
3945         }
3946         spin_unlock(&vmx_vpid_lock);
3947 }
3948
3949 static void free_vpid(struct vcpu_vmx *vmx)
3950 {
3951         if (!enable_vpid)
3952                 return;
3953         spin_lock(&vmx_vpid_lock);
3954         if (vmx->vpid != 0)
3955                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3956         spin_unlock(&vmx_vpid_lock);
3957 }
3958
3959 #define MSR_TYPE_R      1
3960 #define MSR_TYPE_W      2
3961 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3962                                                 u32 msr, int type)
3963 {
3964         int f = sizeof(unsigned long);
3965
3966         if (!cpu_has_vmx_msr_bitmap())
3967                 return;
3968
3969         /*
3970          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3971          * have the write-low and read-high bitmap offsets the wrong way round.
3972          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3973          */
3974         if (msr <= 0x1fff) {
3975                 if (type & MSR_TYPE_R)
3976                         /* read-low */
3977                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3978
3979                 if (type & MSR_TYPE_W)
3980                         /* write-low */
3981                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3982
3983         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3984                 msr &= 0x1fff;
3985                 if (type & MSR_TYPE_R)
3986                         /* read-high */
3987                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3988
3989                 if (type & MSR_TYPE_W)
3990                         /* write-high */
3991                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3992
3993         }
3994 }
3995
3996 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3997                                                 u32 msr, int type)
3998 {
3999         int f = sizeof(unsigned long);
4000
4001         if (!cpu_has_vmx_msr_bitmap())
4002                 return;
4003
4004         /*
4005          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4006          * have the write-low and read-high bitmap offsets the wrong way round.
4007          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4008          */
4009         if (msr <= 0x1fff) {
4010                 if (type & MSR_TYPE_R)
4011                         /* read-low */
4012                         __set_bit(msr, msr_bitmap + 0x000 / f);
4013
4014                 if (type & MSR_TYPE_W)
4015                         /* write-low */
4016                         __set_bit(msr, msr_bitmap + 0x800 / f);
4017
4018         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4019                 msr &= 0x1fff;
4020                 if (type & MSR_TYPE_R)
4021                         /* read-high */
4022                         __set_bit(msr, msr_bitmap + 0x400 / f);
4023
4024                 if (type & MSR_TYPE_W)
4025                         /* write-high */
4026                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4027
4028         }
4029 }
4030
4031 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4032 {
4033         if (!longmode_only)
4034                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4035                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4036         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4037                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4038 }
4039
4040 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4041 {
4042         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4043                         msr, MSR_TYPE_R);
4044         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4045                         msr, MSR_TYPE_R);
4046 }
4047
4048 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4049 {
4050         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4051                         msr, MSR_TYPE_R);
4052         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4053                         msr, MSR_TYPE_R);
4054 }
4055
4056 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4057 {
4058         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4059                         msr, MSR_TYPE_W);
4060         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4061                         msr, MSR_TYPE_W);
4062 }
4063
4064 static int vmx_vm_has_apicv(struct kvm *kvm)
4065 {
4066         return enable_apicv && irqchip_in_kernel(kvm);
4067 }
4068
4069 /*
4070  * Send interrupt to vcpu via posted interrupt way.
4071  * 1. If target vcpu is running(non-root mode), send posted interrupt
4072  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4073  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4074  * interrupt from PIR in next vmentry.
4075  */
4076 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4077 {
4078         struct vcpu_vmx *vmx = to_vmx(vcpu);
4079         int r;
4080
4081         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4082                 return;
4083
4084         r = pi_test_and_set_on(&vmx->pi_desc);
4085         kvm_make_request(KVM_REQ_EVENT, vcpu);
4086 #ifdef CONFIG_SMP
4087         if (!r && (vcpu->mode == IN_GUEST_MODE))
4088                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4089                                 POSTED_INTR_VECTOR);
4090         else
4091 #endif
4092                 kvm_vcpu_kick(vcpu);
4093 }
4094
4095 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4096 {
4097         struct vcpu_vmx *vmx = to_vmx(vcpu);
4098
4099         if (!pi_test_and_clear_on(&vmx->pi_desc))
4100                 return;
4101
4102         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4103 }
4104
4105 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4106 {
4107         return;
4108 }
4109
4110 /*
4111  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4112  * will not change in the lifetime of the guest.
4113  * Note that host-state that does change is set elsewhere. E.g., host-state
4114  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4115  */
4116 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4117 {
4118         u32 low32, high32;
4119         unsigned long tmpl;
4120         struct desc_ptr dt;
4121
4122         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4123         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4124         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4125
4126         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4127 #ifdef CONFIG_X86_64
4128         /*
4129          * Load null selectors, so we can avoid reloading them in
4130          * __vmx_load_host_state(), in case userspace uses the null selectors
4131          * too (the expected case).
4132          */
4133         vmcs_write16(HOST_DS_SELECTOR, 0);
4134         vmcs_write16(HOST_ES_SELECTOR, 0);
4135 #else
4136         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4137         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4138 #endif
4139         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4140         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4141
4142         native_store_idt(&dt);
4143         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4144         vmx->host_idt_base = dt.address;
4145
4146         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4147
4148         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4149         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4150         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4151         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4152
4153         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4154                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4155                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4156         }
4157 }
4158
4159 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4160 {
4161         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4162         if (enable_ept)
4163                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4164         if (is_guest_mode(&vmx->vcpu))
4165                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4166                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4167         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4168 }
4169
4170 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4171 {
4172         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4173
4174         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4175                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4176         return pin_based_exec_ctrl;
4177 }
4178
4179 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4180 {
4181         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4182         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4183                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4184 #ifdef CONFIG_X86_64
4185                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4186                                 CPU_BASED_CR8_LOAD_EXITING;
4187 #endif
4188         }
4189         if (!enable_ept)
4190                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4191                                 CPU_BASED_CR3_LOAD_EXITING  |
4192                                 CPU_BASED_INVLPG_EXITING;
4193         return exec_control;
4194 }
4195
4196 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4197 {
4198         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4199         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4200                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4201         if (vmx->vpid == 0)
4202                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4203         if (!enable_ept) {
4204                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4205                 enable_unrestricted_guest = 0;
4206                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4207                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4208         }
4209         if (!enable_unrestricted_guest)
4210                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4211         if (!ple_gap)
4212                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4213         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4214                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4215                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4216         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4217         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4218            (handle_vmptrld).
4219            We can NOT enable shadow_vmcs here because we don't have yet
4220            a current VMCS12
4221         */
4222         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4223         return exec_control;
4224 }
4225
4226 static void ept_set_mmio_spte_mask(void)
4227 {
4228         /*
4229          * EPT Misconfigurations can be generated if the value of bits 2:0
4230          * of an EPT paging-structure entry is 110b (write/execute).
4231          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4232          * spte.
4233          */
4234         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4235 }
4236
4237 /*
4238  * Sets up the vmcs for emulated real mode.
4239  */
4240 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4241 {
4242 #ifdef CONFIG_X86_64
4243         unsigned long a;
4244 #endif
4245         int i;
4246
4247         /* I/O */
4248         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4249         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4250
4251         if (enable_shadow_vmcs) {
4252                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4253                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4254         }
4255         if (cpu_has_vmx_msr_bitmap())
4256                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4257
4258         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4259
4260         /* Control */
4261         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4262
4263         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4264
4265         if (cpu_has_secondary_exec_ctrls()) {
4266                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4267                                 vmx_secondary_exec_control(vmx));
4268         }
4269
4270         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4271                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4272                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4273                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4274                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4275
4276                 vmcs_write16(GUEST_INTR_STATUS, 0);
4277
4278                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4279                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4280         }
4281
4282         if (ple_gap) {
4283                 vmcs_write32(PLE_GAP, ple_gap);
4284                 vmcs_write32(PLE_WINDOW, ple_window);
4285         }
4286
4287         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4288         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4289         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4290
4291         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4292         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4293         vmx_set_constant_host_state(vmx);
4294 #ifdef CONFIG_X86_64
4295         rdmsrl(MSR_FS_BASE, a);
4296         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4297         rdmsrl(MSR_GS_BASE, a);
4298         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4299 #else
4300         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4301         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4302 #endif
4303
4304         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4305         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4306         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4307         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4308         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4309
4310         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4311                 u32 msr_low, msr_high;
4312                 u64 host_pat;
4313                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4314                 host_pat = msr_low | ((u64) msr_high << 32);
4315                 /* Write the default value follow host pat */
4316                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4317                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4318                 vmx->vcpu.arch.pat = host_pat;
4319         }
4320
4321         for (i = 0; i < NR_VMX_MSR; ++i) {
4322                 u32 index = vmx_msr_index[i];
4323                 u32 data_low, data_high;
4324                 int j = vmx->nmsrs;
4325
4326                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4327                         continue;
4328                 if (wrmsr_safe(index, data_low, data_high) < 0)
4329                         continue;
4330                 vmx->guest_msrs[j].index = i;
4331                 vmx->guest_msrs[j].data = 0;
4332                 vmx->guest_msrs[j].mask = -1ull;
4333                 ++vmx->nmsrs;
4334         }
4335
4336         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4337
4338         /* 22.2.1, 20.8.1 */
4339         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4340
4341         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4342         set_cr4_guest_host_mask(vmx);
4343
4344         return 0;
4345 }
4346
4347 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4348 {
4349         struct vcpu_vmx *vmx = to_vmx(vcpu);
4350         u64 msr;
4351
4352         vmx->rmode.vm86_active = 0;
4353
4354         vmx->soft_vnmi_blocked = 0;
4355
4356         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4357         kvm_set_cr8(&vmx->vcpu, 0);
4358         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4359         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4360                 msr |= MSR_IA32_APICBASE_BSP;
4361         kvm_set_apic_base(&vmx->vcpu, msr);
4362
4363         vmx_segment_cache_clear(vmx);
4364
4365         seg_setup(VCPU_SREG_CS);
4366         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4367         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4368
4369         seg_setup(VCPU_SREG_DS);
4370         seg_setup(VCPU_SREG_ES);
4371         seg_setup(VCPU_SREG_FS);
4372         seg_setup(VCPU_SREG_GS);
4373         seg_setup(VCPU_SREG_SS);
4374
4375         vmcs_write16(GUEST_TR_SELECTOR, 0);
4376         vmcs_writel(GUEST_TR_BASE, 0);
4377         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4378         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4379
4380         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4381         vmcs_writel(GUEST_LDTR_BASE, 0);
4382         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4383         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4384
4385         vmcs_write32(GUEST_SYSENTER_CS, 0);
4386         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4387         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4388
4389         vmcs_writel(GUEST_RFLAGS, 0x02);
4390         kvm_rip_write(vcpu, 0xfff0);
4391
4392         vmcs_writel(GUEST_GDTR_BASE, 0);
4393         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4394
4395         vmcs_writel(GUEST_IDTR_BASE, 0);
4396         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4397
4398         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4399         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4400         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4401
4402         /* Special registers */
4403         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4404
4405         setup_msrs(vmx);
4406
4407         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4408
4409         if (cpu_has_vmx_tpr_shadow()) {
4410                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4411                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4412                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4413                                      __pa(vmx->vcpu.arch.apic->regs));
4414                 vmcs_write32(TPR_THRESHOLD, 0);
4415         }
4416
4417         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4418                 vmcs_write64(APIC_ACCESS_ADDR,
4419                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4420
4421         if (vmx_vm_has_apicv(vcpu->kvm))
4422                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4423
4424         if (vmx->vpid != 0)
4425                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4426
4427         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4428         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4429         vmx_set_cr4(&vmx->vcpu, 0);
4430         vmx_set_efer(&vmx->vcpu, 0);
4431         vmx_fpu_activate(&vmx->vcpu);
4432         update_exception_bitmap(&vmx->vcpu);
4433
4434         vpid_sync_context(vmx);
4435 }
4436
4437 /*
4438  * In nested virtualization, check if L1 asked to exit on external interrupts.
4439  * For most existing hypervisors, this will always return true.
4440  */
4441 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4442 {
4443         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4444                 PIN_BASED_EXT_INTR_MASK;
4445 }
4446
4447 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4448 {
4449         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4450                 PIN_BASED_NMI_EXITING;
4451 }
4452
4453 static int enable_irq_window(struct kvm_vcpu *vcpu)
4454 {
4455         u32 cpu_based_vm_exec_control;
4456
4457         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4458                 /*
4459                  * We get here if vmx_interrupt_allowed() said we can't
4460                  * inject to L1 now because L2 must run. The caller will have
4461                  * to make L2 exit right after entry, so we can inject to L1
4462                  * more promptly.
4463                  */
4464                 return -EBUSY;
4465
4466         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4467         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4468         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4469         return 0;
4470 }
4471
4472 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4473 {
4474         u32 cpu_based_vm_exec_control;
4475
4476         if (!cpu_has_virtual_nmis())
4477                 return enable_irq_window(vcpu);
4478
4479         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4480                 return enable_irq_window(vcpu);
4481
4482         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4483         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4484         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4485         return 0;
4486 }
4487
4488 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4489 {
4490         struct vcpu_vmx *vmx = to_vmx(vcpu);
4491         uint32_t intr;
4492         int irq = vcpu->arch.interrupt.nr;
4493
4494         trace_kvm_inj_virq(irq);
4495
4496         ++vcpu->stat.irq_injections;
4497         if (vmx->rmode.vm86_active) {
4498                 int inc_eip = 0;
4499                 if (vcpu->arch.interrupt.soft)
4500                         inc_eip = vcpu->arch.event_exit_inst_len;
4501                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4502                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4503                 return;
4504         }
4505         intr = irq | INTR_INFO_VALID_MASK;
4506         if (vcpu->arch.interrupt.soft) {
4507                 intr |= INTR_TYPE_SOFT_INTR;
4508                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4509                              vmx->vcpu.arch.event_exit_inst_len);
4510         } else
4511                 intr |= INTR_TYPE_EXT_INTR;
4512         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4513 }
4514
4515 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4516 {
4517         struct vcpu_vmx *vmx = to_vmx(vcpu);
4518
4519         if (is_guest_mode(vcpu))
4520                 return;
4521
4522         if (!cpu_has_virtual_nmis()) {
4523                 /*
4524                  * Tracking the NMI-blocked state in software is built upon
4525                  * finding the next open IRQ window. This, in turn, depends on
4526                  * well-behaving guests: They have to keep IRQs disabled at
4527                  * least as long as the NMI handler runs. Otherwise we may
4528                  * cause NMI nesting, maybe breaking the guest. But as this is
4529                  * highly unlikely, we can live with the residual risk.
4530                  */
4531                 vmx->soft_vnmi_blocked = 1;
4532                 vmx->vnmi_blocked_time = 0;
4533         }
4534
4535         ++vcpu->stat.nmi_injections;
4536         vmx->nmi_known_unmasked = false;
4537         if (vmx->rmode.vm86_active) {
4538                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4539                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4540                 return;
4541         }
4542         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4543                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4544 }
4545
4546 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4547 {
4548         if (!cpu_has_virtual_nmis())
4549                 return to_vmx(vcpu)->soft_vnmi_blocked;
4550         if (to_vmx(vcpu)->nmi_known_unmasked)
4551                 return false;
4552         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4553 }
4554
4555 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4556 {
4557         struct vcpu_vmx *vmx = to_vmx(vcpu);
4558
4559         if (!cpu_has_virtual_nmis()) {
4560                 if (vmx->soft_vnmi_blocked != masked) {
4561                         vmx->soft_vnmi_blocked = masked;
4562                         vmx->vnmi_blocked_time = 0;
4563                 }
4564         } else {
4565                 vmx->nmi_known_unmasked = !masked;
4566                 if (masked)
4567                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4568                                       GUEST_INTR_STATE_NMI);
4569                 else
4570                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4571                                         GUEST_INTR_STATE_NMI);
4572         }
4573 }
4574
4575 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4576 {
4577         if (is_guest_mode(vcpu)) {
4578                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4579
4580                 if (to_vmx(vcpu)->nested.nested_run_pending)
4581                         return 0;
4582                 if (nested_exit_on_nmi(vcpu)) {
4583                         nested_vmx_vmexit(vcpu);
4584                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4585                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4586                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4587                         /*
4588                          * The NMI-triggered VM exit counts as injection:
4589                          * clear this one and block further NMIs.
4590                          */
4591                         vcpu->arch.nmi_pending = 0;
4592                         vmx_set_nmi_mask(vcpu, true);
4593                         return 0;
4594                 }
4595         }
4596
4597         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4598                 return 0;
4599
4600         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4601                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4602                    | GUEST_INTR_STATE_NMI));
4603 }
4604
4605 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4606 {
4607         if (is_guest_mode(vcpu)) {
4608                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4609
4610                 if (to_vmx(vcpu)->nested.nested_run_pending)
4611                         return 0;
4612                 if (nested_exit_on_intr(vcpu)) {
4613                         nested_vmx_vmexit(vcpu);
4614                         vmcs12->vm_exit_reason =
4615                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4616                         vmcs12->vm_exit_intr_info = 0;
4617                         /*
4618                          * fall through to normal code, but now in L1, not L2
4619                          */
4620                 }
4621         }
4622
4623         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4624                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4625                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4626 }
4627
4628 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4629 {
4630         int ret;
4631         struct kvm_userspace_memory_region tss_mem = {
4632                 .slot = TSS_PRIVATE_MEMSLOT,
4633                 .guest_phys_addr = addr,
4634                 .memory_size = PAGE_SIZE * 3,
4635                 .flags = 0,
4636         };
4637
4638         ret = kvm_set_memory_region(kvm, &tss_mem);
4639         if (ret)
4640                 return ret;
4641         kvm->arch.tss_addr = addr;
4642         if (!init_rmode_tss(kvm))
4643                 return  -ENOMEM;
4644
4645         return 0;
4646 }
4647
4648 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4649 {
4650         switch (vec) {
4651         case BP_VECTOR:
4652                 /*
4653                  * Update instruction length as we may reinject the exception
4654                  * from user space while in guest debugging mode.
4655                  */
4656                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4657                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4658                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4659                         return false;
4660                 /* fall through */
4661         case DB_VECTOR:
4662                 if (vcpu->guest_debug &
4663                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4664                         return false;
4665                 /* fall through */
4666         case DE_VECTOR:
4667         case OF_VECTOR:
4668         case BR_VECTOR:
4669         case UD_VECTOR:
4670         case DF_VECTOR:
4671         case SS_VECTOR:
4672         case GP_VECTOR:
4673         case MF_VECTOR:
4674                 return true;
4675         break;
4676         }
4677         return false;
4678 }
4679
4680 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4681                                   int vec, u32 err_code)
4682 {
4683         /*
4684          * Instruction with address size override prefix opcode 0x67
4685          * Cause the #SS fault with 0 error code in VM86 mode.
4686          */
4687         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4688                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4689                         if (vcpu->arch.halt_request) {
4690                                 vcpu->arch.halt_request = 0;
4691                                 return kvm_emulate_halt(vcpu);
4692                         }
4693                         return 1;
4694                 }
4695                 return 0;
4696         }
4697
4698         /*
4699          * Forward all other exceptions that are valid in real mode.
4700          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4701          *        the required debugging infrastructure rework.
4702          */
4703         kvm_queue_exception(vcpu, vec);
4704         return 1;
4705 }
4706
4707 /*
4708  * Trigger machine check on the host. We assume all the MSRs are already set up
4709  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4710  * We pass a fake environment to the machine check handler because we want
4711  * the guest to be always treated like user space, no matter what context
4712  * it used internally.
4713  */
4714 static void kvm_machine_check(void)
4715 {
4716 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4717         struct pt_regs regs = {
4718                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4719                 .flags = X86_EFLAGS_IF,
4720         };
4721
4722         do_machine_check(&regs, 0);
4723 #endif
4724 }
4725
4726 static int handle_machine_check(struct kvm_vcpu *vcpu)
4727 {
4728         /* already handled by vcpu_run */
4729         return 1;
4730 }
4731
4732 static int handle_exception(struct kvm_vcpu *vcpu)
4733 {
4734         struct vcpu_vmx *vmx = to_vmx(vcpu);
4735         struct kvm_run *kvm_run = vcpu->run;
4736         u32 intr_info, ex_no, error_code;
4737         unsigned long cr2, rip, dr6;
4738         u32 vect_info;
4739         enum emulation_result er;
4740
4741         vect_info = vmx->idt_vectoring_info;
4742         intr_info = vmx->exit_intr_info;
4743
4744         if (is_machine_check(intr_info))
4745                 return handle_machine_check(vcpu);
4746
4747         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4748                 return 1;  /* already handled by vmx_vcpu_run() */
4749
4750         if (is_no_device(intr_info)) {
4751                 vmx_fpu_activate(vcpu);
4752                 return 1;
4753         }
4754
4755         if (is_invalid_opcode(intr_info)) {
4756                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4757                 if (er != EMULATE_DONE)
4758                         kvm_queue_exception(vcpu, UD_VECTOR);
4759                 return 1;
4760         }
4761
4762         error_code = 0;
4763         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4764                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4765
4766         /*
4767          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4768          * MMIO, it is better to report an internal error.
4769          * See the comments in vmx_handle_exit.
4770          */
4771         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4772             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4773                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4774                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4775                 vcpu->run->internal.ndata = 2;
4776                 vcpu->run->internal.data[0] = vect_info;
4777                 vcpu->run->internal.data[1] = intr_info;
4778                 return 0;
4779         }
4780
4781         if (is_page_fault(intr_info)) {
4782                 /* EPT won't cause page fault directly */
4783                 BUG_ON(enable_ept);
4784                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4785                 trace_kvm_page_fault(cr2, error_code);
4786
4787                 if (kvm_event_needs_reinjection(vcpu))
4788                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4789                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4790         }
4791
4792         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4793
4794         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4795                 return handle_rmode_exception(vcpu, ex_no, error_code);
4796
4797         switch (ex_no) {
4798         case DB_VECTOR:
4799                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4800                 if (!(vcpu->guest_debug &
4801                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4802                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4803                         kvm_queue_exception(vcpu, DB_VECTOR);
4804                         return 1;
4805                 }
4806                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4807                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4808                 /* fall through */
4809         case BP_VECTOR:
4810                 /*
4811                  * Update instruction length as we may reinject #BP from
4812                  * user space while in guest debugging mode. Reading it for
4813                  * #DB as well causes no harm, it is not used in that case.
4814                  */
4815                 vmx->vcpu.arch.event_exit_inst_len =
4816                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4817                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4818                 rip = kvm_rip_read(vcpu);
4819                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4820                 kvm_run->debug.arch.exception = ex_no;
4821                 break;
4822         default:
4823                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4824                 kvm_run->ex.exception = ex_no;
4825                 kvm_run->ex.error_code = error_code;
4826                 break;
4827         }
4828         return 0;
4829 }
4830
4831 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4832 {
4833         ++vcpu->stat.irq_exits;
4834         return 1;
4835 }
4836
4837 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4838 {
4839         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4840         return 0;
4841 }
4842
4843 static int handle_io(struct kvm_vcpu *vcpu)
4844 {
4845         unsigned long exit_qualification;
4846         int size, in, string;
4847         unsigned port;
4848
4849         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4850         string = (exit_qualification & 16) != 0;
4851         in = (exit_qualification & 8) != 0;
4852
4853         ++vcpu->stat.io_exits;
4854
4855         if (string || in)
4856                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4857
4858         port = exit_qualification >> 16;
4859         size = (exit_qualification & 7) + 1;
4860         skip_emulated_instruction(vcpu);
4861
4862         return kvm_fast_pio_out(vcpu, size, port);
4863 }
4864
4865 static void
4866 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4867 {
4868         /*
4869          * Patch in the VMCALL instruction:
4870          */
4871         hypercall[0] = 0x0f;
4872         hypercall[1] = 0x01;
4873         hypercall[2] = 0xc1;
4874 }
4875
4876 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4877 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4878 {
4879         if (is_guest_mode(vcpu)) {
4880                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4881                 unsigned long orig_val = val;
4882
4883                 /*
4884                  * We get here when L2 changed cr0 in a way that did not change
4885                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4886                  * but did change L0 shadowed bits. So we first calculate the
4887                  * effective cr0 value that L1 would like to write into the
4888                  * hardware. It consists of the L2-owned bits from the new
4889                  * value combined with the L1-owned bits from L1's guest_cr0.
4890                  */
4891                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4892                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4893
4894                 /* TODO: will have to take unrestricted guest mode into
4895                  * account */
4896                 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4897                         return 1;
4898
4899                 if (kvm_set_cr0(vcpu, val))
4900                         return 1;
4901                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4902                 return 0;
4903         } else {
4904                 if (to_vmx(vcpu)->nested.vmxon &&
4905                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4906                         return 1;
4907                 return kvm_set_cr0(vcpu, val);
4908         }
4909 }
4910
4911 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4912 {
4913         if (is_guest_mode(vcpu)) {
4914                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4915                 unsigned long orig_val = val;
4916
4917                 /* analogously to handle_set_cr0 */
4918                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4919                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4920                 if (kvm_set_cr4(vcpu, val))
4921                         return 1;
4922                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4923                 return 0;
4924         } else
4925                 return kvm_set_cr4(vcpu, val);
4926 }
4927
4928 /* called to set cr0 as approriate for clts instruction exit. */
4929 static void handle_clts(struct kvm_vcpu *vcpu)
4930 {
4931         if (is_guest_mode(vcpu)) {
4932                 /*
4933                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4934                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4935                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4936                  */
4937                 vmcs_writel(CR0_READ_SHADOW,
4938                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4939                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4940         } else
4941                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4942 }
4943
4944 static int handle_cr(struct kvm_vcpu *vcpu)
4945 {
4946         unsigned long exit_qualification, val;
4947         int cr;
4948         int reg;
4949         int err;
4950
4951         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4952         cr = exit_qualification & 15;
4953         reg = (exit_qualification >> 8) & 15;
4954         switch ((exit_qualification >> 4) & 3) {
4955         case 0: /* mov to cr */
4956                 val = kvm_register_read(vcpu, reg);
4957                 trace_kvm_cr_write(cr, val);
4958                 switch (cr) {
4959                 case 0:
4960                         err = handle_set_cr0(vcpu, val);
4961                         kvm_complete_insn_gp(vcpu, err);
4962                         return 1;
4963                 case 3:
4964                         err = kvm_set_cr3(vcpu, val);
4965                         kvm_complete_insn_gp(vcpu, err);
4966                         return 1;
4967                 case 4:
4968                         err = handle_set_cr4(vcpu, val);
4969                         kvm_complete_insn_gp(vcpu, err);
4970                         return 1;
4971                 case 8: {
4972                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4973                                 u8 cr8 = kvm_register_read(vcpu, reg);
4974                                 err = kvm_set_cr8(vcpu, cr8);
4975                                 kvm_complete_insn_gp(vcpu, err);
4976                                 if (irqchip_in_kernel(vcpu->kvm))
4977                                         return 1;
4978                                 if (cr8_prev <= cr8)
4979                                         return 1;
4980                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4981                                 return 0;
4982                         }
4983                 }
4984                 break;
4985         case 2: /* clts */
4986                 handle_clts(vcpu);
4987                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4988                 skip_emulated_instruction(vcpu);
4989                 vmx_fpu_activate(vcpu);
4990                 return 1;
4991         case 1: /*mov from cr*/
4992                 switch (cr) {
4993                 case 3:
4994                         val = kvm_read_cr3(vcpu);
4995                         kvm_register_write(vcpu, reg, val);
4996                         trace_kvm_cr_read(cr, val);
4997                         skip_emulated_instruction(vcpu);
4998                         return 1;
4999                 case 8:
5000                         val = kvm_get_cr8(vcpu);
5001                         kvm_register_write(vcpu, reg, val);
5002                         trace_kvm_cr_read(cr, val);
5003                         skip_emulated_instruction(vcpu);
5004                         return 1;
5005                 }
5006                 break;
5007         case 3: /* lmsw */
5008                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5009                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5010                 kvm_lmsw(vcpu, val);
5011
5012                 skip_emulated_instruction(vcpu);
5013                 return 1;
5014         default:
5015                 break;
5016         }
5017         vcpu->run->exit_reason = 0;
5018         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5019                (int)(exit_qualification >> 4) & 3, cr);
5020         return 0;
5021 }
5022
5023 static int handle_dr(struct kvm_vcpu *vcpu)
5024 {
5025         unsigned long exit_qualification;
5026         int dr, reg;
5027
5028         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5029         if (!kvm_require_cpl(vcpu, 0))
5030                 return 1;
5031         dr = vmcs_readl(GUEST_DR7);
5032         if (dr & DR7_GD) {
5033                 /*
5034                  * As the vm-exit takes precedence over the debug trap, we
5035                  * need to emulate the latter, either for the host or the
5036                  * guest debugging itself.
5037                  */
5038                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5039                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5040                         vcpu->run->debug.arch.dr7 = dr;
5041                         vcpu->run->debug.arch.pc =
5042                                 vmcs_readl(GUEST_CS_BASE) +
5043                                 vmcs_readl(GUEST_RIP);
5044                         vcpu->run->debug.arch.exception = DB_VECTOR;
5045                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5046                         return 0;
5047                 } else {
5048                         vcpu->arch.dr7 &= ~DR7_GD;
5049                         vcpu->arch.dr6 |= DR6_BD;
5050                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5051                         kvm_queue_exception(vcpu, DB_VECTOR);
5052                         return 1;
5053                 }
5054         }
5055
5056         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5057         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5058         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5059         if (exit_qualification & TYPE_MOV_FROM_DR) {
5060                 unsigned long val;
5061                 if (!kvm_get_dr(vcpu, dr, &val))
5062                         kvm_register_write(vcpu, reg, val);
5063         } else
5064                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5065         skip_emulated_instruction(vcpu);
5066         return 1;
5067 }
5068
5069 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5070 {
5071         vmcs_writel(GUEST_DR7, val);
5072 }
5073
5074 static int handle_cpuid(struct kvm_vcpu *vcpu)
5075 {
5076         kvm_emulate_cpuid(vcpu);
5077         return 1;
5078 }
5079
5080 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5081 {
5082         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5083         u64 data;
5084
5085         if (vmx_get_msr(vcpu, ecx, &data)) {
5086                 trace_kvm_msr_read_ex(ecx);
5087                 kvm_inject_gp(vcpu, 0);
5088                 return 1;
5089         }
5090
5091         trace_kvm_msr_read(ecx, data);
5092
5093         /* FIXME: handling of bits 32:63 of rax, rdx */
5094         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5095         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5096         skip_emulated_instruction(vcpu);
5097         return 1;
5098 }
5099
5100 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5101 {
5102         struct msr_data msr;
5103         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5104         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5105                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5106
5107         msr.data = data;
5108         msr.index = ecx;
5109         msr.host_initiated = false;
5110         if (vmx_set_msr(vcpu, &msr) != 0) {
5111                 trace_kvm_msr_write_ex(ecx, data);
5112                 kvm_inject_gp(vcpu, 0);
5113                 return 1;
5114         }
5115
5116         trace_kvm_msr_write(ecx, data);
5117         skip_emulated_instruction(vcpu);
5118         return 1;
5119 }
5120
5121 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5122 {
5123         kvm_make_request(KVM_REQ_EVENT, vcpu);
5124         return 1;
5125 }
5126
5127 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5128 {
5129         u32 cpu_based_vm_exec_control;
5130
5131         /* clear pending irq */
5132         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5133         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5134         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5135
5136         kvm_make_request(KVM_REQ_EVENT, vcpu);
5137
5138         ++vcpu->stat.irq_window_exits;
5139
5140         /*
5141          * If the user space waits to inject interrupts, exit as soon as
5142          * possible
5143          */
5144         if (!irqchip_in_kernel(vcpu->kvm) &&
5145             vcpu->run->request_interrupt_window &&
5146             !kvm_cpu_has_interrupt(vcpu)) {
5147                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5148                 return 0;
5149         }
5150         return 1;
5151 }
5152
5153 static int handle_halt(struct kvm_vcpu *vcpu)
5154 {
5155         skip_emulated_instruction(vcpu);
5156         return kvm_emulate_halt(vcpu);
5157 }
5158
5159 static int handle_vmcall(struct kvm_vcpu *vcpu)
5160 {
5161         skip_emulated_instruction(vcpu);
5162         kvm_emulate_hypercall(vcpu);
5163         return 1;
5164 }
5165
5166 static int handle_invd(struct kvm_vcpu *vcpu)
5167 {
5168         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5169 }
5170
5171 static int handle_invlpg(struct kvm_vcpu *vcpu)
5172 {
5173         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5174
5175         kvm_mmu_invlpg(vcpu, exit_qualification);
5176         skip_emulated_instruction(vcpu);
5177         return 1;
5178 }
5179
5180 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5181 {
5182         int err;
5183
5184         err = kvm_rdpmc(vcpu);
5185         kvm_complete_insn_gp(vcpu, err);
5186
5187         return 1;
5188 }
5189
5190 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5191 {
5192         skip_emulated_instruction(vcpu);
5193         kvm_emulate_wbinvd(vcpu);
5194         return 1;
5195 }
5196
5197 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5198 {
5199         u64 new_bv = kvm_read_edx_eax(vcpu);
5200         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5201
5202         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5203                 skip_emulated_instruction(vcpu);
5204         return 1;
5205 }
5206
5207 static int handle_apic_access(struct kvm_vcpu *vcpu)
5208 {
5209         if (likely(fasteoi)) {
5210                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5211                 int access_type, offset;
5212
5213                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5214                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5215                 /*
5216                  * Sane guest uses MOV to write EOI, with written value
5217                  * not cared. So make a short-circuit here by avoiding
5218                  * heavy instruction emulation.
5219                  */
5220                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5221                     (offset == APIC_EOI)) {
5222                         kvm_lapic_set_eoi(vcpu);
5223                         skip_emulated_instruction(vcpu);
5224                         return 1;
5225                 }
5226         }
5227         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5228 }
5229
5230 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5231 {
5232         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5233         int vector = exit_qualification & 0xff;
5234
5235         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5236         kvm_apic_set_eoi_accelerated(vcpu, vector);
5237         return 1;
5238 }
5239
5240 static int handle_apic_write(struct kvm_vcpu *vcpu)
5241 {
5242         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5243         u32 offset = exit_qualification & 0xfff;
5244
5245         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5246         kvm_apic_write_nodecode(vcpu, offset);
5247         return 1;
5248 }
5249
5250 static int handle_task_switch(struct kvm_vcpu *vcpu)
5251 {
5252         struct vcpu_vmx *vmx = to_vmx(vcpu);
5253         unsigned long exit_qualification;
5254         bool has_error_code = false;
5255         u32 error_code = 0;
5256         u16 tss_selector;
5257         int reason, type, idt_v, idt_index;
5258
5259         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5260         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5261         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5262
5263         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5264
5265         reason = (u32)exit_qualification >> 30;
5266         if (reason == TASK_SWITCH_GATE && idt_v) {
5267                 switch (type) {
5268                 case INTR_TYPE_NMI_INTR:
5269                         vcpu->arch.nmi_injected = false;
5270                         vmx_set_nmi_mask(vcpu, true);
5271                         break;
5272                 case INTR_TYPE_EXT_INTR:
5273                 case INTR_TYPE_SOFT_INTR:
5274                         kvm_clear_interrupt_queue(vcpu);
5275                         break;
5276                 case INTR_TYPE_HARD_EXCEPTION:
5277                         if (vmx->idt_vectoring_info &
5278                             VECTORING_INFO_DELIVER_CODE_MASK) {
5279                                 has_error_code = true;
5280                                 error_code =
5281                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5282                         }
5283                         /* fall through */
5284                 case INTR_TYPE_SOFT_EXCEPTION:
5285                         kvm_clear_exception_queue(vcpu);
5286                         break;
5287                 default:
5288                         break;
5289                 }
5290         }
5291         tss_selector = exit_qualification;
5292
5293         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5294                        type != INTR_TYPE_EXT_INTR &&
5295                        type != INTR_TYPE_NMI_INTR))
5296                 skip_emulated_instruction(vcpu);
5297
5298         if (kvm_task_switch(vcpu, tss_selector,
5299                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5300                             has_error_code, error_code) == EMULATE_FAIL) {
5301                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5302                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5303                 vcpu->run->internal.ndata = 0;
5304                 return 0;
5305         }
5306
5307         /* clear all local breakpoint enable flags */
5308         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5309
5310         /*
5311          * TODO: What about debug traps on tss switch?
5312          *       Are we supposed to inject them and update dr6?
5313          */
5314
5315         return 1;
5316 }
5317
5318 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5319 {
5320         unsigned long exit_qualification;
5321         gpa_t gpa;
5322         u32 error_code;
5323         int gla_validity;
5324
5325         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5326
5327         gla_validity = (exit_qualification >> 7) & 0x3;
5328         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5329                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5330                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5331                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5332                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5333                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5334                         (long unsigned int)exit_qualification);
5335                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5336                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5337                 return 0;
5338         }
5339
5340         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5341         trace_kvm_page_fault(gpa, exit_qualification);
5342
5343         /* It is a write fault? */
5344         error_code = exit_qualification & (1U << 1);
5345         /* It is a fetch fault? */
5346         error_code |= (exit_qualification & (1U << 2)) << 2;
5347         /* ept page table is present? */
5348         error_code |= (exit_qualification >> 3) & 0x1;
5349
5350         vcpu->arch.exit_qualification = exit_qualification;
5351
5352         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5353 }
5354
5355 static u64 ept_rsvd_mask(u64 spte, int level)
5356 {
5357         int i;
5358         u64 mask = 0;
5359
5360         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5361                 mask |= (1ULL << i);
5362
5363         if (level > 2)
5364                 /* bits 7:3 reserved */
5365                 mask |= 0xf8;
5366         else if (level == 2) {
5367                 if (spte & (1ULL << 7))
5368                         /* 2MB ref, bits 20:12 reserved */
5369                         mask |= 0x1ff000;
5370                 else
5371                         /* bits 6:3 reserved */
5372                         mask |= 0x78;
5373         }
5374
5375         return mask;
5376 }
5377
5378 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5379                                        int level)
5380 {
5381         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5382
5383         /* 010b (write-only) */
5384         WARN_ON((spte & 0x7) == 0x2);
5385
5386         /* 110b (write/execute) */
5387         WARN_ON((spte & 0x7) == 0x6);
5388
5389         /* 100b (execute-only) and value not supported by logical processor */
5390         if (!cpu_has_vmx_ept_execute_only())
5391                 WARN_ON((spte & 0x7) == 0x4);
5392
5393         /* not 000b */
5394         if ((spte & 0x7)) {
5395                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5396
5397                 if (rsvd_bits != 0) {
5398                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5399                                          __func__, rsvd_bits);
5400                         WARN_ON(1);
5401                 }
5402
5403                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5404                         u64 ept_mem_type = (spte & 0x38) >> 3;
5405
5406                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5407                             ept_mem_type == 7) {
5408                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5409                                                 __func__, ept_mem_type);
5410                                 WARN_ON(1);
5411                         }
5412                 }
5413         }
5414 }
5415
5416 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5417 {
5418         u64 sptes[4];
5419         int nr_sptes, i, ret;
5420         gpa_t gpa;
5421
5422         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5423
5424         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5425         if (likely(ret == RET_MMIO_PF_EMULATE))
5426                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5427                                               EMULATE_DONE;
5428
5429         if (unlikely(ret == RET_MMIO_PF_INVALID))
5430                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5431
5432         if (unlikely(ret == RET_MMIO_PF_RETRY))
5433                 return 1;
5434
5435         /* It is the real ept misconfig */
5436         printk(KERN_ERR "EPT: Misconfiguration.\n");
5437         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5438
5439         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5440
5441         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5442                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5443
5444         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5445         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5446
5447         return 0;
5448 }
5449
5450 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5451 {
5452         u32 cpu_based_vm_exec_control;
5453
5454         /* clear pending NMI */
5455         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5456         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5457         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5458         ++vcpu->stat.nmi_window_exits;
5459         kvm_make_request(KVM_REQ_EVENT, vcpu);
5460
5461         return 1;
5462 }
5463
5464 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5465 {
5466         struct vcpu_vmx *vmx = to_vmx(vcpu);
5467         enum emulation_result err = EMULATE_DONE;
5468         int ret = 1;
5469         u32 cpu_exec_ctrl;
5470         bool intr_window_requested;
5471         unsigned count = 130;
5472
5473         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5474         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5475
5476         while (!guest_state_valid(vcpu) && count-- != 0) {
5477                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5478                         return handle_interrupt_window(&vmx->vcpu);
5479
5480                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5481                         return 1;
5482
5483                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5484
5485                 if (err == EMULATE_USER_EXIT) {
5486                         ret = 0;
5487                         goto out;
5488                 }
5489
5490                 if (err != EMULATE_DONE) {
5491                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5492                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5493                         vcpu->run->internal.ndata = 0;
5494                         return 0;
5495                 }
5496
5497                 if (vcpu->arch.halt_request) {
5498                         vcpu->arch.halt_request = 0;
5499                         ret = kvm_emulate_halt(vcpu);
5500                         goto out;
5501                 }
5502
5503                 if (signal_pending(current))
5504                         goto out;
5505                 if (need_resched())
5506                         schedule();
5507         }
5508
5509         vmx->emulation_required = emulation_required(vcpu);
5510 out:
5511         return ret;
5512 }
5513
5514 /*
5515  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5516  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5517  */
5518 static int handle_pause(struct kvm_vcpu *vcpu)
5519 {
5520         skip_emulated_instruction(vcpu);
5521         kvm_vcpu_on_spin(vcpu);
5522
5523         return 1;
5524 }
5525
5526 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5527 {
5528         kvm_queue_exception(vcpu, UD_VECTOR);
5529         return 1;
5530 }
5531
5532 /*
5533  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5534  * We could reuse a single VMCS for all the L2 guests, but we also want the
5535  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5536  * allows keeping them loaded on the processor, and in the future will allow
5537  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5538  * every entry if they never change.
5539  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5540  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5541  *
5542  * The following functions allocate and free a vmcs02 in this pool.
5543  */
5544
5545 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5546 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5547 {
5548         struct vmcs02_list *item;
5549         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5550                 if (item->vmptr == vmx->nested.current_vmptr) {
5551                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5552                         return &item->vmcs02;
5553                 }
5554
5555         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5556                 /* Recycle the least recently used VMCS. */
5557                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5558                         struct vmcs02_list, list);
5559                 item->vmptr = vmx->nested.current_vmptr;
5560                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5561                 return &item->vmcs02;
5562         }
5563
5564         /* Create a new VMCS */
5565         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5566         if (!item)
5567                 return NULL;
5568         item->vmcs02.vmcs = alloc_vmcs();
5569         if (!item->vmcs02.vmcs) {
5570                 kfree(item);
5571                 return NULL;
5572         }
5573         loaded_vmcs_init(&item->vmcs02);
5574         item->vmptr = vmx->nested.current_vmptr;
5575         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5576         vmx->nested.vmcs02_num++;
5577         return &item->vmcs02;
5578 }
5579
5580 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5581 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5582 {
5583         struct vmcs02_list *item;
5584         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5585                 if (item->vmptr == vmptr) {
5586                         free_loaded_vmcs(&item->vmcs02);
5587                         list_del(&item->list);
5588                         kfree(item);
5589                         vmx->nested.vmcs02_num--;
5590                         return;
5591                 }
5592 }
5593
5594 /*
5595  * Free all VMCSs saved for this vcpu, except the one pointed by
5596  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5597  * currently used, if running L2), and vmcs01 when running L2.
5598  */
5599 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5600 {
5601         struct vmcs02_list *item, *n;
5602         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5603                 if (vmx->loaded_vmcs != &item->vmcs02)
5604                         free_loaded_vmcs(&item->vmcs02);
5605                 list_del(&item->list);
5606                 kfree(item);
5607         }
5608         vmx->nested.vmcs02_num = 0;
5609
5610         if (vmx->loaded_vmcs != &vmx->vmcs01)
5611                 free_loaded_vmcs(&vmx->vmcs01);
5612 }
5613
5614 /*
5615  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5616  * set the success or error code of an emulated VMX instruction, as specified
5617  * by Vol 2B, VMX Instruction Reference, "Conventions".
5618  */
5619 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5620 {
5621         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5622                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5623                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5624 }
5625
5626 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5627 {
5628         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5629                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5630                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5631                         | X86_EFLAGS_CF);
5632 }
5633
5634 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5635                                         u32 vm_instruction_error)
5636 {
5637         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5638                 /*
5639                  * failValid writes the error number to the current VMCS, which
5640                  * can't be done there isn't a current VMCS.
5641                  */
5642                 nested_vmx_failInvalid(vcpu);
5643                 return;
5644         }
5645         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5646                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5647                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5648                         | X86_EFLAGS_ZF);
5649         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5650         /*
5651          * We don't need to force a shadow sync because
5652          * VM_INSTRUCTION_ERROR is not shadowed
5653          */
5654 }
5655
5656 /*
5657  * Emulate the VMXON instruction.
5658  * Currently, we just remember that VMX is active, and do not save or even
5659  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5660  * do not currently need to store anything in that guest-allocated memory
5661  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5662  * argument is different from the VMXON pointer (which the spec says they do).
5663  */
5664 static int handle_vmon(struct kvm_vcpu *vcpu)
5665 {
5666         struct kvm_segment cs;
5667         struct vcpu_vmx *vmx = to_vmx(vcpu);
5668         struct vmcs *shadow_vmcs;
5669         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5670                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5671
5672         /* The Intel VMX Instruction Reference lists a bunch of bits that
5673          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5674          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5675          * Otherwise, we should fail with #UD. We test these now:
5676          */
5677         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5678             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5679             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5680                 kvm_queue_exception(vcpu, UD_VECTOR);
5681                 return 1;
5682         }
5683
5684         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5685         if (is_long_mode(vcpu) && !cs.l) {
5686                 kvm_queue_exception(vcpu, UD_VECTOR);
5687                 return 1;
5688         }
5689
5690         if (vmx_get_cpl(vcpu)) {
5691                 kvm_inject_gp(vcpu, 0);
5692                 return 1;
5693         }
5694         if (vmx->nested.vmxon) {
5695                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5696                 skip_emulated_instruction(vcpu);
5697                 return 1;
5698         }
5699
5700         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5701                         != VMXON_NEEDED_FEATURES) {
5702                 kvm_inject_gp(vcpu, 0);
5703                 return 1;
5704         }
5705
5706         if (enable_shadow_vmcs) {
5707                 shadow_vmcs = alloc_vmcs();
5708                 if (!shadow_vmcs)
5709                         return -ENOMEM;
5710                 /* mark vmcs as shadow */
5711                 shadow_vmcs->revision_id |= (1u << 31);
5712                 /* init shadow vmcs */
5713                 vmcs_clear(shadow_vmcs);
5714                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5715         }
5716
5717         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5718         vmx->nested.vmcs02_num = 0;
5719
5720         vmx->nested.vmxon = true;
5721
5722         skip_emulated_instruction(vcpu);
5723         nested_vmx_succeed(vcpu);
5724         return 1;
5725 }
5726
5727 /*
5728  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5729  * for running VMX instructions (except VMXON, whose prerequisites are
5730  * slightly different). It also specifies what exception to inject otherwise.
5731  */
5732 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5733 {
5734         struct kvm_segment cs;
5735         struct vcpu_vmx *vmx = to_vmx(vcpu);
5736
5737         if (!vmx->nested.vmxon) {
5738                 kvm_queue_exception(vcpu, UD_VECTOR);
5739                 return 0;
5740         }
5741
5742         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5743         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5744             (is_long_mode(vcpu) && !cs.l)) {
5745                 kvm_queue_exception(vcpu, UD_VECTOR);
5746                 return 0;
5747         }
5748
5749         if (vmx_get_cpl(vcpu)) {
5750                 kvm_inject_gp(vcpu, 0);
5751                 return 0;
5752         }
5753
5754         return 1;
5755 }
5756
5757 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5758 {
5759         u32 exec_control;
5760         if (enable_shadow_vmcs) {
5761                 if (vmx->nested.current_vmcs12 != NULL) {
5762                         /* copy to memory all shadowed fields in case
5763                            they were modified */
5764                         copy_shadow_to_vmcs12(vmx);
5765                         vmx->nested.sync_shadow_vmcs = false;
5766                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5767                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5768                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5769                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5770                 }
5771         }
5772         kunmap(vmx->nested.current_vmcs12_page);
5773         nested_release_page(vmx->nested.current_vmcs12_page);
5774 }
5775
5776 /*
5777  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5778  * just stops using VMX.
5779  */
5780 static void free_nested(struct vcpu_vmx *vmx)
5781 {
5782         if (!vmx->nested.vmxon)
5783                 return;
5784         vmx->nested.vmxon = false;
5785         if (vmx->nested.current_vmptr != -1ull) {
5786                 nested_release_vmcs12(vmx);
5787                 vmx->nested.current_vmptr = -1ull;
5788                 vmx->nested.current_vmcs12 = NULL;
5789         }
5790         if (enable_shadow_vmcs)
5791                 free_vmcs(vmx->nested.current_shadow_vmcs);
5792         /* Unpin physical memory we referred to in current vmcs02 */
5793         if (vmx->nested.apic_access_page) {
5794                 nested_release_page(vmx->nested.apic_access_page);
5795                 vmx->nested.apic_access_page = 0;
5796         }
5797
5798         nested_free_all_saved_vmcss(vmx);
5799 }
5800
5801 /* Emulate the VMXOFF instruction */
5802 static int handle_vmoff(struct kvm_vcpu *vcpu)
5803 {
5804         if (!nested_vmx_check_permission(vcpu))
5805                 return 1;
5806         free_nested(to_vmx(vcpu));
5807         skip_emulated_instruction(vcpu);
5808         nested_vmx_succeed(vcpu);
5809         return 1;
5810 }
5811
5812 /*
5813  * Decode the memory-address operand of a vmx instruction, as recorded on an
5814  * exit caused by such an instruction (run by a guest hypervisor).
5815  * On success, returns 0. When the operand is invalid, returns 1 and throws
5816  * #UD or #GP.
5817  */
5818 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5819                                  unsigned long exit_qualification,
5820                                  u32 vmx_instruction_info, gva_t *ret)
5821 {
5822         /*
5823          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5824          * Execution", on an exit, vmx_instruction_info holds most of the
5825          * addressing components of the operand. Only the displacement part
5826          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5827          * For how an actual address is calculated from all these components,
5828          * refer to Vol. 1, "Operand Addressing".
5829          */
5830         int  scaling = vmx_instruction_info & 3;
5831         int  addr_size = (vmx_instruction_info >> 7) & 7;
5832         bool is_reg = vmx_instruction_info & (1u << 10);
5833         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5834         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5835         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5836         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5837         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5838
5839         if (is_reg) {
5840                 kvm_queue_exception(vcpu, UD_VECTOR);
5841                 return 1;
5842         }
5843
5844         /* Addr = segment_base + offset */
5845         /* offset = base + [index * scale] + displacement */
5846         *ret = vmx_get_segment_base(vcpu, seg_reg);
5847         if (base_is_valid)
5848                 *ret += kvm_register_read(vcpu, base_reg);
5849         if (index_is_valid)
5850                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5851         *ret += exit_qualification; /* holds the displacement */
5852
5853         if (addr_size == 1) /* 32 bit */
5854                 *ret &= 0xffffffff;
5855
5856         /*
5857          * TODO: throw #GP (and return 1) in various cases that the VM*
5858          * instructions require it - e.g., offset beyond segment limit,
5859          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5860          * address, and so on. Currently these are not checked.
5861          */
5862         return 0;
5863 }
5864
5865 /* Emulate the VMCLEAR instruction */
5866 static int handle_vmclear(struct kvm_vcpu *vcpu)
5867 {
5868         struct vcpu_vmx *vmx = to_vmx(vcpu);
5869         gva_t gva;
5870         gpa_t vmptr;
5871         struct vmcs12 *vmcs12;
5872         struct page *page;
5873         struct x86_exception e;
5874
5875         if (!nested_vmx_check_permission(vcpu))
5876                 return 1;
5877
5878         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5879                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5880                 return 1;
5881
5882         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5883                                 sizeof(vmptr), &e)) {
5884                 kvm_inject_page_fault(vcpu, &e);
5885                 return 1;
5886         }
5887
5888         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5889                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5890                 skip_emulated_instruction(vcpu);
5891                 return 1;
5892         }
5893
5894         if (vmptr == vmx->nested.current_vmptr) {
5895                 nested_release_vmcs12(vmx);
5896                 vmx->nested.current_vmptr = -1ull;
5897                 vmx->nested.current_vmcs12 = NULL;
5898         }
5899
5900         page = nested_get_page(vcpu, vmptr);
5901         if (page == NULL) {
5902                 /*
5903                  * For accurate processor emulation, VMCLEAR beyond available
5904                  * physical memory should do nothing at all. However, it is
5905                  * possible that a nested vmx bug, not a guest hypervisor bug,
5906                  * resulted in this case, so let's shut down before doing any
5907                  * more damage:
5908                  */
5909                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5910                 return 1;
5911         }
5912         vmcs12 = kmap(page);
5913         vmcs12->launch_state = 0;
5914         kunmap(page);
5915         nested_release_page(page);
5916
5917         nested_free_vmcs02(vmx, vmptr);
5918
5919         skip_emulated_instruction(vcpu);
5920         nested_vmx_succeed(vcpu);
5921         return 1;
5922 }
5923
5924 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5925
5926 /* Emulate the VMLAUNCH instruction */
5927 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5928 {
5929         return nested_vmx_run(vcpu, true);
5930 }
5931
5932 /* Emulate the VMRESUME instruction */
5933 static int handle_vmresume(struct kvm_vcpu *vcpu)
5934 {
5935
5936         return nested_vmx_run(vcpu, false);
5937 }
5938
5939 enum vmcs_field_type {
5940         VMCS_FIELD_TYPE_U16 = 0,
5941         VMCS_FIELD_TYPE_U64 = 1,
5942         VMCS_FIELD_TYPE_U32 = 2,
5943         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5944 };
5945
5946 static inline int vmcs_field_type(unsigned long field)
5947 {
5948         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5949                 return VMCS_FIELD_TYPE_U32;
5950         return (field >> 13) & 0x3 ;
5951 }
5952
5953 static inline int vmcs_field_readonly(unsigned long field)
5954 {
5955         return (((field >> 10) & 0x3) == 1);
5956 }
5957
5958 /*
5959  * Read a vmcs12 field. Since these can have varying lengths and we return
5960  * one type, we chose the biggest type (u64) and zero-extend the return value
5961  * to that size. Note that the caller, handle_vmread, might need to use only
5962  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5963  * 64-bit fields are to be returned).
5964  */
5965 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5966                                         unsigned long field, u64 *ret)
5967 {
5968         short offset = vmcs_field_to_offset(field);
5969         char *p;
5970
5971         if (offset < 0)
5972                 return 0;
5973
5974         p = ((char *)(get_vmcs12(vcpu))) + offset;
5975
5976         switch (vmcs_field_type(field)) {
5977         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5978                 *ret = *((natural_width *)p);
5979                 return 1;
5980         case VMCS_FIELD_TYPE_U16:
5981                 *ret = *((u16 *)p);
5982                 return 1;
5983         case VMCS_FIELD_TYPE_U32:
5984                 *ret = *((u32 *)p);
5985                 return 1;
5986         case VMCS_FIELD_TYPE_U64:
5987                 *ret = *((u64 *)p);
5988                 return 1;
5989         default:
5990                 return 0; /* can never happen. */
5991         }
5992 }
5993
5994
5995 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5996                                     unsigned long field, u64 field_value){
5997         short offset = vmcs_field_to_offset(field);
5998         char *p = ((char *) get_vmcs12(vcpu)) + offset;
5999         if (offset < 0)
6000                 return false;
6001
6002         switch (vmcs_field_type(field)) {
6003         case VMCS_FIELD_TYPE_U16:
6004                 *(u16 *)p = field_value;
6005                 return true;
6006         case VMCS_FIELD_TYPE_U32:
6007                 *(u32 *)p = field_value;
6008                 return true;
6009         case VMCS_FIELD_TYPE_U64:
6010                 *(u64 *)p = field_value;
6011                 return true;
6012         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6013                 *(natural_width *)p = field_value;
6014                 return true;
6015         default:
6016                 return false; /* can never happen. */
6017         }
6018
6019 }
6020
6021 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6022 {
6023         int i;
6024         unsigned long field;
6025         u64 field_value;
6026         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6027         const unsigned long *fields = shadow_read_write_fields;
6028         const int num_fields = max_shadow_read_write_fields;
6029
6030         vmcs_load(shadow_vmcs);
6031
6032         for (i = 0; i < num_fields; i++) {
6033                 field = fields[i];
6034                 switch (vmcs_field_type(field)) {
6035                 case VMCS_FIELD_TYPE_U16:
6036                         field_value = vmcs_read16(field);
6037                         break;
6038                 case VMCS_FIELD_TYPE_U32:
6039                         field_value = vmcs_read32(field);
6040                         break;
6041                 case VMCS_FIELD_TYPE_U64:
6042                         field_value = vmcs_read64(field);
6043                         break;
6044                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6045                         field_value = vmcs_readl(field);
6046                         break;
6047                 }
6048                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6049         }
6050
6051         vmcs_clear(shadow_vmcs);
6052         vmcs_load(vmx->loaded_vmcs->vmcs);
6053 }
6054
6055 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6056 {
6057         const unsigned long *fields[] = {
6058                 shadow_read_write_fields,
6059                 shadow_read_only_fields
6060         };
6061         const int max_fields[] = {
6062                 max_shadow_read_write_fields,
6063                 max_shadow_read_only_fields
6064         };
6065         int i, q;
6066         unsigned long field;
6067         u64 field_value = 0;
6068         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6069
6070         vmcs_load(shadow_vmcs);
6071
6072         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6073                 for (i = 0; i < max_fields[q]; i++) {
6074                         field = fields[q][i];
6075                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6076
6077                         switch (vmcs_field_type(field)) {
6078                         case VMCS_FIELD_TYPE_U16:
6079                                 vmcs_write16(field, (u16)field_value);
6080                                 break;
6081                         case VMCS_FIELD_TYPE_U32:
6082                                 vmcs_write32(field, (u32)field_value);
6083                                 break;
6084                         case VMCS_FIELD_TYPE_U64:
6085                                 vmcs_write64(field, (u64)field_value);
6086                                 break;
6087                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6088                                 vmcs_writel(field, (long)field_value);
6089                                 break;
6090                         }
6091                 }
6092         }
6093
6094         vmcs_clear(shadow_vmcs);
6095         vmcs_load(vmx->loaded_vmcs->vmcs);
6096 }
6097
6098 /*
6099  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6100  * used before) all generate the same failure when it is missing.
6101  */
6102 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6103 {
6104         struct vcpu_vmx *vmx = to_vmx(vcpu);
6105         if (vmx->nested.current_vmptr == -1ull) {
6106                 nested_vmx_failInvalid(vcpu);
6107                 skip_emulated_instruction(vcpu);
6108                 return 0;
6109         }
6110         return 1;
6111 }
6112
6113 static int handle_vmread(struct kvm_vcpu *vcpu)
6114 {
6115         unsigned long field;
6116         u64 field_value;
6117         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6118         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6119         gva_t gva = 0;
6120
6121         if (!nested_vmx_check_permission(vcpu) ||
6122             !nested_vmx_check_vmcs12(vcpu))
6123                 return 1;
6124
6125         /* Decode instruction info and find the field to read */
6126         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6127         /* Read the field, zero-extended to a u64 field_value */
6128         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6129                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6130                 skip_emulated_instruction(vcpu);
6131                 return 1;
6132         }
6133         /*
6134          * Now copy part of this value to register or memory, as requested.
6135          * Note that the number of bits actually copied is 32 or 64 depending
6136          * on the guest's mode (32 or 64 bit), not on the given field's length.
6137          */
6138         if (vmx_instruction_info & (1u << 10)) {
6139                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6140                         field_value);
6141         } else {
6142                 if (get_vmx_mem_address(vcpu, exit_qualification,
6143                                 vmx_instruction_info, &gva))
6144                         return 1;
6145                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6146                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6147                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6148         }
6149
6150         nested_vmx_succeed(vcpu);
6151         skip_emulated_instruction(vcpu);
6152         return 1;
6153 }
6154
6155
6156 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6157 {
6158         unsigned long field;
6159         gva_t gva;
6160         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6161         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6162         /* The value to write might be 32 or 64 bits, depending on L1's long
6163          * mode, and eventually we need to write that into a field of several
6164          * possible lengths. The code below first zero-extends the value to 64
6165          * bit (field_value), and then copies only the approriate number of
6166          * bits into the vmcs12 field.
6167          */
6168         u64 field_value = 0;
6169         struct x86_exception e;
6170
6171         if (!nested_vmx_check_permission(vcpu) ||
6172             !nested_vmx_check_vmcs12(vcpu))
6173                 return 1;
6174
6175         if (vmx_instruction_info & (1u << 10))
6176                 field_value = kvm_register_read(vcpu,
6177                         (((vmx_instruction_info) >> 3) & 0xf));
6178         else {
6179                 if (get_vmx_mem_address(vcpu, exit_qualification,
6180                                 vmx_instruction_info, &gva))
6181                         return 1;
6182                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6183                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6184                         kvm_inject_page_fault(vcpu, &e);
6185                         return 1;
6186                 }
6187         }
6188
6189
6190         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6191         if (vmcs_field_readonly(field)) {
6192                 nested_vmx_failValid(vcpu,
6193                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6194                 skip_emulated_instruction(vcpu);
6195                 return 1;
6196         }
6197
6198         if (!vmcs12_write_any(vcpu, field, field_value)) {
6199                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6200                 skip_emulated_instruction(vcpu);
6201                 return 1;
6202         }
6203
6204         nested_vmx_succeed(vcpu);
6205         skip_emulated_instruction(vcpu);
6206         return 1;
6207 }
6208
6209 /* Emulate the VMPTRLD instruction */
6210 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6211 {
6212         struct vcpu_vmx *vmx = to_vmx(vcpu);
6213         gva_t gva;
6214         gpa_t vmptr;
6215         struct x86_exception e;
6216         u32 exec_control;
6217
6218         if (!nested_vmx_check_permission(vcpu))
6219                 return 1;
6220
6221         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6222                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6223                 return 1;
6224
6225         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6226                                 sizeof(vmptr), &e)) {
6227                 kvm_inject_page_fault(vcpu, &e);
6228                 return 1;
6229         }
6230
6231         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6232                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6233                 skip_emulated_instruction(vcpu);
6234                 return 1;
6235         }
6236
6237         if (vmx->nested.current_vmptr != vmptr) {
6238                 struct vmcs12 *new_vmcs12;
6239                 struct page *page;
6240                 page = nested_get_page(vcpu, vmptr);
6241                 if (page == NULL) {
6242                         nested_vmx_failInvalid(vcpu);
6243                         skip_emulated_instruction(vcpu);
6244                         return 1;
6245                 }
6246                 new_vmcs12 = kmap(page);
6247                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6248                         kunmap(page);
6249                         nested_release_page_clean(page);
6250                         nested_vmx_failValid(vcpu,
6251                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6252                         skip_emulated_instruction(vcpu);
6253                         return 1;
6254                 }
6255                 if (vmx->nested.current_vmptr != -1ull)
6256                         nested_release_vmcs12(vmx);
6257
6258                 vmx->nested.current_vmptr = vmptr;
6259                 vmx->nested.current_vmcs12 = new_vmcs12;
6260                 vmx->nested.current_vmcs12_page = page;
6261                 if (enable_shadow_vmcs) {
6262                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6263                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6264                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6265                         vmcs_write64(VMCS_LINK_POINTER,
6266                                      __pa(vmx->nested.current_shadow_vmcs));
6267                         vmx->nested.sync_shadow_vmcs = true;
6268                 }
6269         }
6270
6271         nested_vmx_succeed(vcpu);
6272         skip_emulated_instruction(vcpu);
6273         return 1;
6274 }
6275
6276 /* Emulate the VMPTRST instruction */
6277 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6278 {
6279         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6280         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6281         gva_t vmcs_gva;
6282         struct x86_exception e;
6283
6284         if (!nested_vmx_check_permission(vcpu))
6285                 return 1;
6286
6287         if (get_vmx_mem_address(vcpu, exit_qualification,
6288                         vmx_instruction_info, &vmcs_gva))
6289                 return 1;
6290         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6291         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6292                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6293                                  sizeof(u64), &e)) {
6294                 kvm_inject_page_fault(vcpu, &e);
6295                 return 1;
6296         }
6297         nested_vmx_succeed(vcpu);
6298         skip_emulated_instruction(vcpu);
6299         return 1;
6300 }
6301
6302 /* Emulate the INVEPT instruction */
6303 static int handle_invept(struct kvm_vcpu *vcpu)
6304 {
6305         u32 vmx_instruction_info, types;
6306         unsigned long type;
6307         gva_t gva;
6308         struct x86_exception e;
6309         struct {
6310                 u64 eptp, gpa;
6311         } operand;
6312         u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6313
6314         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6315             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6316                 kvm_queue_exception(vcpu, UD_VECTOR);
6317                 return 1;
6318         }
6319
6320         if (!nested_vmx_check_permission(vcpu))
6321                 return 1;
6322
6323         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6324                 kvm_queue_exception(vcpu, UD_VECTOR);
6325                 return 1;
6326         }
6327
6328         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6329         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6330
6331         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6332
6333         if (!(types & (1UL << type))) {
6334                 nested_vmx_failValid(vcpu,
6335                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6336                 return 1;
6337         }
6338
6339         /* According to the Intel VMX instruction reference, the memory
6340          * operand is read even if it isn't needed (e.g., for type==global)
6341          */
6342         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6343                         vmx_instruction_info, &gva))
6344                 return 1;
6345         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6346                                 sizeof(operand), &e)) {
6347                 kvm_inject_page_fault(vcpu, &e);
6348                 return 1;
6349         }
6350
6351         switch (type) {
6352         case VMX_EPT_EXTENT_CONTEXT:
6353                 if ((operand.eptp & eptp_mask) !=
6354                                 (nested_ept_get_cr3(vcpu) & eptp_mask))
6355                         break;
6356         case VMX_EPT_EXTENT_GLOBAL:
6357                 kvm_mmu_sync_roots(vcpu);
6358                 kvm_mmu_flush_tlb(vcpu);
6359                 nested_vmx_succeed(vcpu);
6360                 break;
6361         default:
6362                 BUG_ON(1);
6363                 break;
6364         }
6365
6366         skip_emulated_instruction(vcpu);
6367         return 1;
6368 }
6369
6370 /*
6371  * The exit handlers return 1 if the exit was handled fully and guest execution
6372  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6373  * to be done to userspace and return 0.
6374  */
6375 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6376         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6377         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6378         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6379         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6380         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6381         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6382         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6383         [EXIT_REASON_CPUID]                   = handle_cpuid,
6384         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6385         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6386         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6387         [EXIT_REASON_HLT]                     = handle_halt,
6388         [EXIT_REASON_INVD]                    = handle_invd,
6389         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6390         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6391         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6392         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6393         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6394         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6395         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6396         [EXIT_REASON_VMREAD]                  = handle_vmread,
6397         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6398         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6399         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6400         [EXIT_REASON_VMON]                    = handle_vmon,
6401         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6402         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6403         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6404         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6405         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6406         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6407         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6408         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6409         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6410         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6411         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6412         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6413         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6414         [EXIT_REASON_INVEPT]                  = handle_invept,
6415 };
6416
6417 static const int kvm_vmx_max_exit_handlers =
6418         ARRAY_SIZE(kvm_vmx_exit_handlers);
6419
6420 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6421                                        struct vmcs12 *vmcs12)
6422 {
6423         unsigned long exit_qualification;
6424         gpa_t bitmap, last_bitmap;
6425         unsigned int port;
6426         int size;
6427         u8 b;
6428
6429         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6430                 return 1;
6431
6432         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6433                 return 0;
6434
6435         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6436
6437         port = exit_qualification >> 16;
6438         size = (exit_qualification & 7) + 1;
6439
6440         last_bitmap = (gpa_t)-1;
6441         b = -1;
6442
6443         while (size > 0) {
6444                 if (port < 0x8000)
6445                         bitmap = vmcs12->io_bitmap_a;
6446                 else if (port < 0x10000)
6447                         bitmap = vmcs12->io_bitmap_b;
6448                 else
6449                         return 1;
6450                 bitmap += (port & 0x7fff) / 8;
6451
6452                 if (last_bitmap != bitmap)
6453                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6454                                 return 1;
6455                 if (b & (1 << (port & 7)))
6456                         return 1;
6457
6458                 port++;
6459                 size--;
6460                 last_bitmap = bitmap;
6461         }
6462
6463         return 0;
6464 }
6465
6466 /*
6467  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6468  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6469  * disinterest in the current event (read or write a specific MSR) by using an
6470  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6471  */
6472 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6473         struct vmcs12 *vmcs12, u32 exit_reason)
6474 {
6475         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6476         gpa_t bitmap;
6477
6478         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6479                 return 1;
6480
6481         /*
6482          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6483          * for the four combinations of read/write and low/high MSR numbers.
6484          * First we need to figure out which of the four to use:
6485          */
6486         bitmap = vmcs12->msr_bitmap;
6487         if (exit_reason == EXIT_REASON_MSR_WRITE)
6488                 bitmap += 2048;
6489         if (msr_index >= 0xc0000000) {
6490                 msr_index -= 0xc0000000;
6491                 bitmap += 1024;
6492         }
6493
6494         /* Then read the msr_index'th bit from this bitmap: */
6495         if (msr_index < 1024*8) {
6496                 unsigned char b;
6497                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6498                         return 1;
6499                 return 1 & (b >> (msr_index & 7));
6500         } else
6501                 return 1; /* let L1 handle the wrong parameter */
6502 }
6503
6504 /*
6505  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6506  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6507  * intercept (via guest_host_mask etc.) the current event.
6508  */
6509 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6510         struct vmcs12 *vmcs12)
6511 {
6512         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6513         int cr = exit_qualification & 15;
6514         int reg = (exit_qualification >> 8) & 15;
6515         unsigned long val = kvm_register_read(vcpu, reg);
6516
6517         switch ((exit_qualification >> 4) & 3) {
6518         case 0: /* mov to cr */
6519                 switch (cr) {
6520                 case 0:
6521                         if (vmcs12->cr0_guest_host_mask &
6522                             (val ^ vmcs12->cr0_read_shadow))
6523                                 return 1;
6524                         break;
6525                 case 3:
6526                         if ((vmcs12->cr3_target_count >= 1 &&
6527                                         vmcs12->cr3_target_value0 == val) ||
6528                                 (vmcs12->cr3_target_count >= 2 &&
6529                                         vmcs12->cr3_target_value1 == val) ||
6530                                 (vmcs12->cr3_target_count >= 3 &&
6531                                         vmcs12->cr3_target_value2 == val) ||
6532                                 (vmcs12->cr3_target_count >= 4 &&
6533                                         vmcs12->cr3_target_value3 == val))
6534                                 return 0;
6535                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6536                                 return 1;
6537                         break;
6538                 case 4:
6539                         if (vmcs12->cr4_guest_host_mask &
6540                             (vmcs12->cr4_read_shadow ^ val))
6541                                 return 1;
6542                         break;
6543                 case 8:
6544                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6545                                 return 1;
6546                         break;
6547                 }
6548                 break;
6549         case 2: /* clts */
6550                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6551                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6552                         return 1;
6553                 break;
6554         case 1: /* mov from cr */
6555                 switch (cr) {
6556                 case 3:
6557                         if (vmcs12->cpu_based_vm_exec_control &
6558                             CPU_BASED_CR3_STORE_EXITING)
6559                                 return 1;
6560                         break;
6561                 case 8:
6562                         if (vmcs12->cpu_based_vm_exec_control &
6563                             CPU_BASED_CR8_STORE_EXITING)
6564                                 return 1;
6565                         break;
6566                 }
6567                 break;
6568         case 3: /* lmsw */
6569                 /*
6570                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6571                  * cr0. Other attempted changes are ignored, with no exit.
6572                  */
6573                 if (vmcs12->cr0_guest_host_mask & 0xe &
6574                     (val ^ vmcs12->cr0_read_shadow))
6575                         return 1;
6576                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6577                     !(vmcs12->cr0_read_shadow & 0x1) &&
6578                     (val & 0x1))
6579                         return 1;
6580                 break;
6581         }
6582         return 0;
6583 }
6584
6585 /*
6586  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6587  * should handle it ourselves in L0 (and then continue L2). Only call this
6588  * when in is_guest_mode (L2).
6589  */
6590 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6591 {
6592         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6593         struct vcpu_vmx *vmx = to_vmx(vcpu);
6594         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6595         u32 exit_reason = vmx->exit_reason;
6596
6597         if (vmx->nested.nested_run_pending)
6598                 return 0;
6599
6600         if (unlikely(vmx->fail)) {
6601                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6602                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6603                 return 1;
6604         }
6605
6606         switch (exit_reason) {
6607         case EXIT_REASON_EXCEPTION_NMI:
6608                 if (!is_exception(intr_info))
6609                         return 0;
6610                 else if (is_page_fault(intr_info))
6611                         return enable_ept;
6612                 return vmcs12->exception_bitmap &
6613                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6614         case EXIT_REASON_EXTERNAL_INTERRUPT:
6615                 return 0;
6616         case EXIT_REASON_TRIPLE_FAULT:
6617                 return 1;
6618         case EXIT_REASON_PENDING_INTERRUPT:
6619                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6620         case EXIT_REASON_NMI_WINDOW:
6621                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6622         case EXIT_REASON_TASK_SWITCH:
6623                 return 1;
6624         case EXIT_REASON_CPUID:
6625                 return 1;
6626         case EXIT_REASON_HLT:
6627                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6628         case EXIT_REASON_INVD:
6629                 return 1;
6630         case EXIT_REASON_INVLPG:
6631                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6632         case EXIT_REASON_RDPMC:
6633                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6634         case EXIT_REASON_RDTSC:
6635                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6636         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6637         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6638         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6639         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6640         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6641         case EXIT_REASON_INVEPT:
6642                 /*
6643                  * VMX instructions trap unconditionally. This allows L1 to
6644                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6645                  */
6646                 return 1;
6647         case EXIT_REASON_CR_ACCESS:
6648                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6649         case EXIT_REASON_DR_ACCESS:
6650                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6651         case EXIT_REASON_IO_INSTRUCTION:
6652                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6653         case EXIT_REASON_MSR_READ:
6654         case EXIT_REASON_MSR_WRITE:
6655                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6656         case EXIT_REASON_INVALID_STATE:
6657                 return 1;
6658         case EXIT_REASON_MWAIT_INSTRUCTION:
6659                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6660         case EXIT_REASON_MONITOR_INSTRUCTION:
6661                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6662         case EXIT_REASON_PAUSE_INSTRUCTION:
6663                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6664                         nested_cpu_has2(vmcs12,
6665                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6666         case EXIT_REASON_MCE_DURING_VMENTRY:
6667                 return 0;
6668         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6669                 return 1;
6670         case EXIT_REASON_APIC_ACCESS:
6671                 return nested_cpu_has2(vmcs12,
6672                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6673         case EXIT_REASON_EPT_VIOLATION:
6674                 /*
6675                  * L0 always deals with the EPT violation. If nested EPT is
6676                  * used, and the nested mmu code discovers that the address is
6677                  * missing in the guest EPT table (EPT12), the EPT violation
6678                  * will be injected with nested_ept_inject_page_fault()
6679                  */
6680                 return 0;
6681         case EXIT_REASON_EPT_MISCONFIG:
6682                 /*
6683                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6684                  * table (shadow on EPT) or a merged EPT table that L0 built
6685                  * (EPT on EPT). So any problems with the structure of the
6686                  * table is L0's fault.
6687                  */
6688                 return 0;
6689         case EXIT_REASON_PREEMPTION_TIMER:
6690                 return vmcs12->pin_based_vm_exec_control &
6691                         PIN_BASED_VMX_PREEMPTION_TIMER;
6692         case EXIT_REASON_WBINVD:
6693                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6694         case EXIT_REASON_XSETBV:
6695                 return 1;
6696         default:
6697                 return 1;
6698         }
6699 }
6700
6701 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6702 {
6703         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6704         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6705 }
6706
6707 /*
6708  * The guest has exited.  See if we can fix it or if we need userspace
6709  * assistance.
6710  */
6711 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6712 {
6713         struct vcpu_vmx *vmx = to_vmx(vcpu);
6714         u32 exit_reason = vmx->exit_reason;
6715         u32 vectoring_info = vmx->idt_vectoring_info;
6716
6717         /* If guest state is invalid, start emulating */
6718         if (vmx->emulation_required)
6719                 return handle_invalid_guest_state(vcpu);
6720
6721         /*
6722          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6723          * we did not inject a still-pending event to L1 now because of
6724          * nested_run_pending, we need to re-enable this bit.
6725          */
6726         if (vmx->nested.nested_run_pending)
6727                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6728
6729         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6730             exit_reason == EXIT_REASON_VMRESUME))
6731                 vmx->nested.nested_run_pending = 1;
6732         else
6733                 vmx->nested.nested_run_pending = 0;
6734
6735         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6736                 nested_vmx_vmexit(vcpu);
6737                 return 1;
6738         }
6739
6740         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6741                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6742                 vcpu->run->fail_entry.hardware_entry_failure_reason
6743                         = exit_reason;
6744                 return 0;
6745         }
6746
6747         if (unlikely(vmx->fail)) {
6748                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6749                 vcpu->run->fail_entry.hardware_entry_failure_reason
6750                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6751                 return 0;
6752         }
6753
6754         /*
6755          * Note:
6756          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6757          * delivery event since it indicates guest is accessing MMIO.
6758          * The vm-exit can be triggered again after return to guest that
6759          * will cause infinite loop.
6760          */
6761         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6762                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6763                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6764                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6765                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6766                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6767                 vcpu->run->internal.ndata = 2;
6768                 vcpu->run->internal.data[0] = vectoring_info;
6769                 vcpu->run->internal.data[1] = exit_reason;
6770                 return 0;
6771         }
6772
6773         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6774             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6775                                         get_vmcs12(vcpu))))) {
6776                 if (vmx_interrupt_allowed(vcpu)) {
6777                         vmx->soft_vnmi_blocked = 0;
6778                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6779                            vcpu->arch.nmi_pending) {
6780                         /*
6781                          * This CPU don't support us in finding the end of an
6782                          * NMI-blocked window if the guest runs with IRQs
6783                          * disabled. So we pull the trigger after 1 s of
6784                          * futile waiting, but inform the user about this.
6785                          */
6786                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6787                                "state on VCPU %d after 1 s timeout\n",
6788                                __func__, vcpu->vcpu_id);
6789                         vmx->soft_vnmi_blocked = 0;
6790                 }
6791         }
6792
6793         if (exit_reason < kvm_vmx_max_exit_handlers
6794             && kvm_vmx_exit_handlers[exit_reason])
6795                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6796         else {
6797                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6798                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6799         }
6800         return 0;
6801 }
6802
6803 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6804 {
6805         if (irr == -1 || tpr < irr) {
6806                 vmcs_write32(TPR_THRESHOLD, 0);
6807                 return;
6808         }
6809
6810         vmcs_write32(TPR_THRESHOLD, irr);
6811 }
6812
6813 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6814 {
6815         u32 sec_exec_control;
6816
6817         /*
6818          * There is not point to enable virtualize x2apic without enable
6819          * apicv
6820          */
6821         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6822                                 !vmx_vm_has_apicv(vcpu->kvm))
6823                 return;
6824
6825         if (!vm_need_tpr_shadow(vcpu->kvm))
6826                 return;
6827
6828         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6829
6830         if (set) {
6831                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6832                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6833         } else {
6834                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6835                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6836         }
6837         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6838
6839         vmx_set_msr_bitmap(vcpu);
6840 }
6841
6842 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6843 {
6844         u16 status;
6845         u8 old;
6846
6847         if (!vmx_vm_has_apicv(kvm))
6848                 return;
6849
6850         if (isr == -1)
6851                 isr = 0;
6852
6853         status = vmcs_read16(GUEST_INTR_STATUS);
6854         old = status >> 8;
6855         if (isr != old) {
6856                 status &= 0xff;
6857                 status |= isr << 8;
6858                 vmcs_write16(GUEST_INTR_STATUS, status);
6859         }
6860 }
6861
6862 static void vmx_set_rvi(int vector)
6863 {
6864         u16 status;
6865         u8 old;
6866
6867         status = vmcs_read16(GUEST_INTR_STATUS);
6868         old = (u8)status & 0xff;
6869         if ((u8)vector != old) {
6870                 status &= ~0xff;
6871                 status |= (u8)vector;
6872                 vmcs_write16(GUEST_INTR_STATUS, status);
6873         }
6874 }
6875
6876 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6877 {
6878         if (max_irr == -1)
6879                 return;
6880
6881         vmx_set_rvi(max_irr);
6882 }
6883
6884 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6885 {
6886         if (!vmx_vm_has_apicv(vcpu->kvm))
6887                 return;
6888
6889         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6890         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6891         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6892         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6893 }
6894
6895 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6896 {
6897         u32 exit_intr_info;
6898
6899         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6900               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6901                 return;
6902
6903         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6904         exit_intr_info = vmx->exit_intr_info;
6905
6906         /* Handle machine checks before interrupts are enabled */
6907         if (is_machine_check(exit_intr_info))
6908                 kvm_machine_check();
6909
6910         /* We need to handle NMIs before interrupts are enabled */
6911         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6912             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6913                 kvm_before_handle_nmi(&vmx->vcpu);
6914                 asm("int $2");
6915                 kvm_after_handle_nmi(&vmx->vcpu);
6916         }
6917 }
6918
6919 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6920 {
6921         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6922
6923         /*
6924          * If external interrupt exists, IF bit is set in rflags/eflags on the
6925          * interrupt stack frame, and interrupt will be enabled on a return
6926          * from interrupt handler.
6927          */
6928         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6929                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6930                 unsigned int vector;
6931                 unsigned long entry;
6932                 gate_desc *desc;
6933                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6934 #ifdef CONFIG_X86_64
6935                 unsigned long tmp;
6936 #endif
6937
6938                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6939                 desc = (gate_desc *)vmx->host_idt_base + vector;
6940                 entry = gate_offset(*desc);
6941                 asm volatile(
6942 #ifdef CONFIG_X86_64
6943                         "mov %%" _ASM_SP ", %[sp]\n\t"
6944                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6945                         "push $%c[ss]\n\t"
6946                         "push %[sp]\n\t"
6947 #endif
6948                         "pushf\n\t"
6949                         "orl $0x200, (%%" _ASM_SP ")\n\t"
6950                         __ASM_SIZE(push) " $%c[cs]\n\t"
6951                         "call *%[entry]\n\t"
6952                         :
6953 #ifdef CONFIG_X86_64
6954                         [sp]"=&r"(tmp)
6955 #endif
6956                         :
6957                         [entry]"r"(entry),
6958                         [ss]"i"(__KERNEL_DS),
6959                         [cs]"i"(__KERNEL_CS)
6960                         );
6961         } else
6962                 local_irq_enable();
6963 }
6964
6965 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6966 {
6967         u32 exit_intr_info;
6968         bool unblock_nmi;
6969         u8 vector;
6970         bool idtv_info_valid;
6971
6972         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6973
6974         if (cpu_has_virtual_nmis()) {
6975                 if (vmx->nmi_known_unmasked)
6976                         return;
6977                 /*
6978                  * Can't use vmx->exit_intr_info since we're not sure what
6979                  * the exit reason is.
6980                  */
6981                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6982                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6983                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6984                 /*
6985                  * SDM 3: 27.7.1.2 (September 2008)
6986                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6987                  * a guest IRET fault.
6988                  * SDM 3: 23.2.2 (September 2008)
6989                  * Bit 12 is undefined in any of the following cases:
6990                  *  If the VM exit sets the valid bit in the IDT-vectoring
6991                  *   information field.
6992                  *  If the VM exit is due to a double fault.
6993                  */
6994                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6995                     vector != DF_VECTOR && !idtv_info_valid)
6996                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6997                                       GUEST_INTR_STATE_NMI);
6998                 else
6999                         vmx->nmi_known_unmasked =
7000                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7001                                   & GUEST_INTR_STATE_NMI);
7002         } else if (unlikely(vmx->soft_vnmi_blocked))
7003                 vmx->vnmi_blocked_time +=
7004                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7005 }
7006
7007 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7008                                       u32 idt_vectoring_info,
7009                                       int instr_len_field,
7010                                       int error_code_field)
7011 {
7012         u8 vector;
7013         int type;
7014         bool idtv_info_valid;
7015
7016         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7017
7018         vcpu->arch.nmi_injected = false;
7019         kvm_clear_exception_queue(vcpu);
7020         kvm_clear_interrupt_queue(vcpu);
7021
7022         if (!idtv_info_valid)
7023                 return;
7024
7025         kvm_make_request(KVM_REQ_EVENT, vcpu);
7026
7027         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7028         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7029
7030         switch (type) {
7031         case INTR_TYPE_NMI_INTR:
7032                 vcpu->arch.nmi_injected = true;
7033                 /*
7034                  * SDM 3: 27.7.1.2 (September 2008)
7035                  * Clear bit "block by NMI" before VM entry if a NMI
7036                  * delivery faulted.
7037                  */
7038                 vmx_set_nmi_mask(vcpu, false);
7039                 break;
7040         case INTR_TYPE_SOFT_EXCEPTION:
7041                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7042                 /* fall through */
7043         case INTR_TYPE_HARD_EXCEPTION:
7044                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7045                         u32 err = vmcs_read32(error_code_field);
7046                         kvm_queue_exception_e(vcpu, vector, err);
7047                 } else
7048                         kvm_queue_exception(vcpu, vector);
7049                 break;
7050         case INTR_TYPE_SOFT_INTR:
7051                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7052                 /* fall through */
7053         case INTR_TYPE_EXT_INTR:
7054                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7055                 break;
7056         default:
7057                 break;
7058         }
7059 }
7060
7061 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7062 {
7063         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7064                                   VM_EXIT_INSTRUCTION_LEN,
7065                                   IDT_VECTORING_ERROR_CODE);
7066 }
7067
7068 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7069 {
7070         __vmx_complete_interrupts(vcpu,
7071                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7072                                   VM_ENTRY_INSTRUCTION_LEN,
7073                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7074
7075         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7076 }
7077
7078 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7079 {
7080         int i, nr_msrs;
7081         struct perf_guest_switch_msr *msrs;
7082
7083         msrs = perf_guest_get_msrs(&nr_msrs);
7084
7085         if (!msrs)
7086                 return;
7087
7088         for (i = 0; i < nr_msrs; i++)
7089                 if (msrs[i].host == msrs[i].guest)
7090                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7091                 else
7092                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7093                                         msrs[i].host);
7094 }
7095
7096 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7097 {
7098         struct vcpu_vmx *vmx = to_vmx(vcpu);
7099         unsigned long debugctlmsr;
7100
7101         /* Record the guest's net vcpu time for enforced NMI injections. */
7102         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7103                 vmx->entry_time = ktime_get();
7104
7105         /* Don't enter VMX if guest state is invalid, let the exit handler
7106            start emulation until we arrive back to a valid state */
7107         if (vmx->emulation_required)
7108                 return;
7109
7110         if (vmx->nested.sync_shadow_vmcs) {
7111                 copy_vmcs12_to_shadow(vmx);
7112                 vmx->nested.sync_shadow_vmcs = false;
7113         }
7114
7115         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7116                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7117         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7118                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7119
7120         /* When single-stepping over STI and MOV SS, we must clear the
7121          * corresponding interruptibility bits in the guest state. Otherwise
7122          * vmentry fails as it then expects bit 14 (BS) in pending debug
7123          * exceptions being set, but that's not correct for the guest debugging
7124          * case. */
7125         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7126                 vmx_set_interrupt_shadow(vcpu, 0);
7127
7128         atomic_switch_perf_msrs(vmx);
7129         debugctlmsr = get_debugctlmsr();
7130
7131         vmx->__launched = vmx->loaded_vmcs->launched;
7132         asm(
7133                 /* Store host registers */
7134                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7135                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7136                 "push %%" _ASM_CX " \n\t"
7137                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7138                 "je 1f \n\t"
7139                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7140                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7141                 "1: \n\t"
7142                 /* Reload cr2 if changed */
7143                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7144                 "mov %%cr2, %%" _ASM_DX " \n\t"
7145                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7146                 "je 2f \n\t"
7147                 "mov %%" _ASM_AX", %%cr2 \n\t"
7148                 "2: \n\t"
7149                 /* Check if vmlaunch of vmresume is needed */
7150                 "cmpl $0, %c[launched](%0) \n\t"
7151                 /* Load guest registers.  Don't clobber flags. */
7152                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7153                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7154                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7155                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7156                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7157                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7158 #ifdef CONFIG_X86_64
7159                 "mov %c[r8](%0),  %%r8  \n\t"
7160                 "mov %c[r9](%0),  %%r9  \n\t"
7161                 "mov %c[r10](%0), %%r10 \n\t"
7162                 "mov %c[r11](%0), %%r11 \n\t"
7163                 "mov %c[r12](%0), %%r12 \n\t"
7164                 "mov %c[r13](%0), %%r13 \n\t"
7165                 "mov %c[r14](%0), %%r14 \n\t"
7166                 "mov %c[r15](%0), %%r15 \n\t"
7167 #endif
7168                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7169
7170                 /* Enter guest mode */
7171                 "jne 1f \n\t"
7172                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7173                 "jmp 2f \n\t"
7174                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7175                 "2: "
7176                 /* Save guest registers, load host registers, keep flags */
7177                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7178                 "pop %0 \n\t"
7179                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7180                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7181                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7182                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7183                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7184                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7185                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7186 #ifdef CONFIG_X86_64
7187                 "mov %%r8,  %c[r8](%0) \n\t"
7188                 "mov %%r9,  %c[r9](%0) \n\t"
7189                 "mov %%r10, %c[r10](%0) \n\t"
7190                 "mov %%r11, %c[r11](%0) \n\t"
7191                 "mov %%r12, %c[r12](%0) \n\t"
7192                 "mov %%r13, %c[r13](%0) \n\t"
7193                 "mov %%r14, %c[r14](%0) \n\t"
7194                 "mov %%r15, %c[r15](%0) \n\t"
7195 #endif
7196                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7197                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7198
7199                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7200                 "setbe %c[fail](%0) \n\t"
7201                 ".pushsection .rodata \n\t"
7202                 ".global vmx_return \n\t"
7203                 "vmx_return: " _ASM_PTR " 2b \n\t"
7204                 ".popsection"
7205               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7206                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7207                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7208                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7209                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7210                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7211                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7212                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7213                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7214                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7215                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7216 #ifdef CONFIG_X86_64
7217                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7218                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7219                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7220                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7221                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7222                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7223                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7224                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7225 #endif
7226                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7227                 [wordsize]"i"(sizeof(ulong))
7228               : "cc", "memory"
7229 #ifdef CONFIG_X86_64
7230                 , "rax", "rbx", "rdi", "rsi"
7231                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7232 #else
7233                 , "eax", "ebx", "edi", "esi"
7234 #endif
7235               );
7236
7237         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7238         if (debugctlmsr)
7239                 update_debugctlmsr(debugctlmsr);
7240
7241 #ifndef CONFIG_X86_64
7242         /*
7243          * The sysexit path does not restore ds/es, so we must set them to
7244          * a reasonable value ourselves.
7245          *
7246          * We can't defer this to vmx_load_host_state() since that function
7247          * may be executed in interrupt context, which saves and restore segments
7248          * around it, nullifying its effect.
7249          */
7250         loadsegment(ds, __USER_DS);
7251         loadsegment(es, __USER_DS);
7252 #endif
7253
7254         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7255                                   | (1 << VCPU_EXREG_RFLAGS)
7256                                   | (1 << VCPU_EXREG_CPL)
7257                                   | (1 << VCPU_EXREG_PDPTR)
7258                                   | (1 << VCPU_EXREG_SEGMENTS)
7259                                   | (1 << VCPU_EXREG_CR3));
7260         vcpu->arch.regs_dirty = 0;
7261
7262         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7263
7264         vmx->loaded_vmcs->launched = 1;
7265
7266         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7267         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7268
7269         vmx_complete_atomic_exit(vmx);
7270         vmx_recover_nmi_blocking(vmx);
7271         vmx_complete_interrupts(vmx);
7272 }
7273
7274 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7275 {
7276         struct vcpu_vmx *vmx = to_vmx(vcpu);
7277
7278         free_vpid(vmx);
7279         free_nested(vmx);
7280         free_loaded_vmcs(vmx->loaded_vmcs);
7281         kfree(vmx->guest_msrs);
7282         kvm_vcpu_uninit(vcpu);
7283         kmem_cache_free(kvm_vcpu_cache, vmx);
7284 }
7285
7286 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7287 {
7288         int err;
7289         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7290         int cpu;
7291
7292         if (!vmx)
7293                 return ERR_PTR(-ENOMEM);
7294
7295         allocate_vpid(vmx);
7296
7297         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7298         if (err)
7299                 goto free_vcpu;
7300
7301         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7302         err = -ENOMEM;
7303         if (!vmx->guest_msrs) {
7304                 goto uninit_vcpu;
7305         }
7306
7307         vmx->loaded_vmcs = &vmx->vmcs01;
7308         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7309         if (!vmx->loaded_vmcs->vmcs)
7310                 goto free_msrs;
7311         if (!vmm_exclusive)
7312                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7313         loaded_vmcs_init(vmx->loaded_vmcs);
7314         if (!vmm_exclusive)
7315                 kvm_cpu_vmxoff();
7316
7317         cpu = get_cpu();
7318         vmx_vcpu_load(&vmx->vcpu, cpu);
7319         vmx->vcpu.cpu = cpu;
7320         err = vmx_vcpu_setup(vmx);
7321         vmx_vcpu_put(&vmx->vcpu);
7322         put_cpu();
7323         if (err)
7324                 goto free_vmcs;
7325         if (vm_need_virtualize_apic_accesses(kvm)) {
7326                 err = alloc_apic_access_page(kvm);
7327                 if (err)
7328                         goto free_vmcs;
7329         }
7330
7331         if (enable_ept) {
7332                 if (!kvm->arch.ept_identity_map_addr)
7333                         kvm->arch.ept_identity_map_addr =
7334                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7335                 err = -ENOMEM;
7336                 if (alloc_identity_pagetable(kvm) != 0)
7337                         goto free_vmcs;
7338                 if (!init_rmode_identity_map(kvm))
7339                         goto free_vmcs;
7340         }
7341
7342         vmx->nested.current_vmptr = -1ull;
7343         vmx->nested.current_vmcs12 = NULL;
7344
7345         return &vmx->vcpu;
7346
7347 free_vmcs:
7348         free_loaded_vmcs(vmx->loaded_vmcs);
7349 free_msrs:
7350         kfree(vmx->guest_msrs);
7351 uninit_vcpu:
7352         kvm_vcpu_uninit(&vmx->vcpu);
7353 free_vcpu:
7354         free_vpid(vmx);
7355         kmem_cache_free(kvm_vcpu_cache, vmx);
7356         return ERR_PTR(err);
7357 }
7358
7359 static void __init vmx_check_processor_compat(void *rtn)
7360 {
7361         struct vmcs_config vmcs_conf;
7362
7363         *(int *)rtn = 0;
7364         if (setup_vmcs_config(&vmcs_conf) < 0)
7365                 *(int *)rtn = -EIO;
7366         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7367                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7368                                 smp_processor_id());
7369                 *(int *)rtn = -EIO;
7370         }
7371 }
7372
7373 static int get_ept_level(void)
7374 {
7375         return VMX_EPT_DEFAULT_GAW + 1;
7376 }
7377
7378 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7379 {
7380         u64 ret;
7381
7382         /* For VT-d and EPT combination
7383          * 1. MMIO: always map as UC
7384          * 2. EPT with VT-d:
7385          *   a. VT-d without snooping control feature: can't guarantee the
7386          *      result, try to trust guest.
7387          *   b. VT-d with snooping control feature: snooping control feature of
7388          *      VT-d engine can guarantee the cache correctness. Just set it
7389          *      to WB to keep consistent with host. So the same as item 3.
7390          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7391          *    consistent with host MTRR
7392          */
7393         if (is_mmio)
7394                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7395         else if (vcpu->kvm->arch.iommu_domain &&
7396                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7397                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7398                       VMX_EPT_MT_EPTE_SHIFT;
7399         else
7400                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7401                         | VMX_EPT_IPAT_BIT;
7402
7403         return ret;
7404 }
7405
7406 static int vmx_get_lpage_level(void)
7407 {
7408         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7409                 return PT_DIRECTORY_LEVEL;
7410         else
7411                 /* For shadow and EPT supported 1GB page */
7412                 return PT_PDPE_LEVEL;
7413 }
7414
7415 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7416 {
7417         struct kvm_cpuid_entry2 *best;
7418         struct vcpu_vmx *vmx = to_vmx(vcpu);
7419         u32 exec_control;
7420
7421         vmx->rdtscp_enabled = false;
7422         if (vmx_rdtscp_supported()) {
7423                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7424                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7425                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7426                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7427                                 vmx->rdtscp_enabled = true;
7428                         else {
7429                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7430                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7431                                                 exec_control);
7432                         }
7433                 }
7434         }
7435
7436         /* Exposing INVPCID only when PCID is exposed */
7437         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7438         if (vmx_invpcid_supported() &&
7439             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7440             guest_cpuid_has_pcid(vcpu)) {
7441                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7442                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7443                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7444                              exec_control);
7445         } else {
7446                 if (cpu_has_secondary_exec_ctrls()) {
7447                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7448                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7449                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7450                                      exec_control);
7451                 }
7452                 if (best)
7453                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7454         }
7455 }
7456
7457 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7458 {
7459         if (func == 1 && nested)
7460                 entry->ecx |= bit(X86_FEATURE_VMX);
7461 }
7462
7463 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7464                 struct x86_exception *fault)
7465 {
7466         struct vmcs12 *vmcs12;
7467         nested_vmx_vmexit(vcpu);
7468         vmcs12 = get_vmcs12(vcpu);
7469
7470         if (fault->error_code & PFERR_RSVD_MASK)
7471                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7472         else
7473                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7474         vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7475         vmcs12->guest_physical_address = fault->address;
7476 }
7477
7478 /* Callbacks for nested_ept_init_mmu_context: */
7479
7480 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7481 {
7482         /* return the page table to be shadowed - in our case, EPT12 */
7483         return get_vmcs12(vcpu)->ept_pointer;
7484 }
7485
7486 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7487 {
7488         int r = kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7489                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7490
7491         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7492         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7493         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7494
7495         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7496
7497         return r;
7498 }
7499
7500 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7501 {
7502         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7503 }
7504
7505 /*
7506  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7507  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7508  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7509  * guest in a way that will both be appropriate to L1's requests, and our
7510  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7511  * function also has additional necessary side-effects, like setting various
7512  * vcpu->arch fields.
7513  */
7514 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7515 {
7516         struct vcpu_vmx *vmx = to_vmx(vcpu);
7517         u32 exec_control;
7518
7519         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7520         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7521         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7522         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7523         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7524         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7525         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7526         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7527         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7528         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7529         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7530         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7531         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7532         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7533         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7534         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7535         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7536         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7537         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7538         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7539         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7540         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7541         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7542         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7543         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7544         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7545         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7546         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7547         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7548         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7549         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7550         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7551         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7552         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7553         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7554         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7555
7556         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7557         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7558                 vmcs12->vm_entry_intr_info_field);
7559         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7560                 vmcs12->vm_entry_exception_error_code);
7561         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7562                 vmcs12->vm_entry_instruction_len);
7563         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7564                 vmcs12->guest_interruptibility_info);
7565         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7566         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7567         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7568         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7569                 vmcs12->guest_pending_dbg_exceptions);
7570         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7571         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7572
7573         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7574
7575         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7576                 (vmcs_config.pin_based_exec_ctrl |
7577                  vmcs12->pin_based_vm_exec_control));
7578
7579         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7580                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7581                              vmcs12->vmx_preemption_timer_value);
7582
7583         /*
7584          * Whether page-faults are trapped is determined by a combination of
7585          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7586          * If enable_ept, L0 doesn't care about page faults and we should
7587          * set all of these to L1's desires. However, if !enable_ept, L0 does
7588          * care about (at least some) page faults, and because it is not easy
7589          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7590          * to exit on each and every L2 page fault. This is done by setting
7591          * MASK=MATCH=0 and (see below) EB.PF=1.
7592          * Note that below we don't need special code to set EB.PF beyond the
7593          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7594          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7595          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7596          *
7597          * A problem with this approach (when !enable_ept) is that L1 may be
7598          * injected with more page faults than it asked for. This could have
7599          * caused problems, but in practice existing hypervisors don't care.
7600          * To fix this, we will need to emulate the PFEC checking (on the L1
7601          * page tables), using walk_addr(), when injecting PFs to L1.
7602          */
7603         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7604                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7605         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7606                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7607
7608         if (cpu_has_secondary_exec_ctrls()) {
7609                 u32 exec_control = vmx_secondary_exec_control(vmx);
7610                 if (!vmx->rdtscp_enabled)
7611                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7612                 /* Take the following fields only from vmcs12 */
7613                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7614                 if (nested_cpu_has(vmcs12,
7615                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7616                         exec_control |= vmcs12->secondary_vm_exec_control;
7617
7618                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7619                         /*
7620                          * Translate L1 physical address to host physical
7621                          * address for vmcs02. Keep the page pinned, so this
7622                          * physical address remains valid. We keep a reference
7623                          * to it so we can release it later.
7624                          */
7625                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7626                                 nested_release_page(vmx->nested.apic_access_page);
7627                         vmx->nested.apic_access_page =
7628                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7629                         /*
7630                          * If translation failed, no matter: This feature asks
7631                          * to exit when accessing the given address, and if it
7632                          * can never be accessed, this feature won't do
7633                          * anything anyway.
7634                          */
7635                         if (!vmx->nested.apic_access_page)
7636                                 exec_control &=
7637                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7638                         else
7639                                 vmcs_write64(APIC_ACCESS_ADDR,
7640                                   page_to_phys(vmx->nested.apic_access_page));
7641                 }
7642
7643                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7644         }
7645
7646
7647         /*
7648          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7649          * Some constant fields are set here by vmx_set_constant_host_state().
7650          * Other fields are different per CPU, and will be set later when
7651          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7652          */
7653         vmx_set_constant_host_state(vmx);
7654
7655         /*
7656          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7657          * entry, but only if the current (host) sp changed from the value
7658          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7659          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7660          * here we just force the write to happen on entry.
7661          */
7662         vmx->host_rsp = 0;
7663
7664         exec_control = vmx_exec_control(vmx); /* L0's desires */
7665         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7666         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7667         exec_control &= ~CPU_BASED_TPR_SHADOW;
7668         exec_control |= vmcs12->cpu_based_vm_exec_control;
7669         /*
7670          * Merging of IO and MSR bitmaps not currently supported.
7671          * Rather, exit every time.
7672          */
7673         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7674         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7675         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7676
7677         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7678
7679         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7680          * bitwise-or of what L1 wants to trap for L2, and what we want to
7681          * trap. Note that CR0.TS also needs updating - we do this later.
7682          */
7683         update_exception_bitmap(vcpu);
7684         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7685         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7686
7687         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7688          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7689          * bits are further modified by vmx_set_efer() below.
7690          */
7691         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7692
7693         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7694          * emulated by vmx_set_efer(), below.
7695          */
7696         vmcs_write32(VM_ENTRY_CONTROLS,
7697                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7698                         ~VM_ENTRY_IA32E_MODE) |
7699                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7700
7701         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7702                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7703                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7704         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7705                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7706
7707
7708         set_cr4_guest_host_mask(vmx);
7709
7710         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7711                 vmcs_write64(TSC_OFFSET,
7712                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7713         else
7714                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7715
7716         if (enable_vpid) {
7717                 /*
7718                  * Trivially support vpid by letting L2s share their parent
7719                  * L1's vpid. TODO: move to a more elaborate solution, giving
7720                  * each L2 its own vpid and exposing the vpid feature to L1.
7721                  */
7722                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7723                 vmx_flush_tlb(vcpu);
7724         }
7725
7726         if (nested_cpu_has_ept(vmcs12)) {
7727                 kvm_mmu_unload(vcpu);
7728                 nested_ept_init_mmu_context(vcpu);
7729         }
7730
7731         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7732                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7733         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7734                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7735         else
7736                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7737         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7738         vmx_set_efer(vcpu, vcpu->arch.efer);
7739
7740         /*
7741          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7742          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7743          * The CR0_READ_SHADOW is what L2 should have expected to read given
7744          * the specifications by L1; It's not enough to take
7745          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7746          * have more bits than L1 expected.
7747          */
7748         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7749         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7750
7751         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7752         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7753
7754         /* shadow page tables on either EPT or shadow page tables */
7755         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7756         kvm_mmu_reset_context(vcpu);
7757
7758         /*
7759          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7760          */
7761         if (enable_ept) {
7762                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7763                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7764                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7765                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7766         }
7767
7768         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7769         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7770 }
7771
7772 /*
7773  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7774  * for running an L2 nested guest.
7775  */
7776 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7777 {
7778         struct vmcs12 *vmcs12;
7779         struct vcpu_vmx *vmx = to_vmx(vcpu);
7780         int cpu;
7781         struct loaded_vmcs *vmcs02;
7782         bool ia32e;
7783
7784         if (!nested_vmx_check_permission(vcpu) ||
7785             !nested_vmx_check_vmcs12(vcpu))
7786                 return 1;
7787
7788         skip_emulated_instruction(vcpu);
7789         vmcs12 = get_vmcs12(vcpu);
7790
7791         if (enable_shadow_vmcs)
7792                 copy_shadow_to_vmcs12(vmx);
7793
7794         /*
7795          * The nested entry process starts with enforcing various prerequisites
7796          * on vmcs12 as required by the Intel SDM, and act appropriately when
7797          * they fail: As the SDM explains, some conditions should cause the
7798          * instruction to fail, while others will cause the instruction to seem
7799          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7800          * To speed up the normal (success) code path, we should avoid checking
7801          * for misconfigurations which will anyway be caught by the processor
7802          * when using the merged vmcs02.
7803          */
7804         if (vmcs12->launch_state == launch) {
7805                 nested_vmx_failValid(vcpu,
7806                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7807                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7808                 return 1;
7809         }
7810
7811         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7812                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7813                 return 1;
7814         }
7815
7816         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7817                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7818                 /*TODO: Also verify bits beyond physical address width are 0*/
7819                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7820                 return 1;
7821         }
7822
7823         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7824                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7825                 /*TODO: Also verify bits beyond physical address width are 0*/
7826                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7827                 return 1;
7828         }
7829
7830         if (vmcs12->vm_entry_msr_load_count > 0 ||
7831             vmcs12->vm_exit_msr_load_count > 0 ||
7832             vmcs12->vm_exit_msr_store_count > 0) {
7833                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7834                                     __func__);
7835                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7836                 return 1;
7837         }
7838
7839         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7840               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7841             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7842               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7843             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7844               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7845             !vmx_control_verify(vmcs12->vm_exit_controls,
7846               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7847             !vmx_control_verify(vmcs12->vm_entry_controls,
7848               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7849         {
7850                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7851                 return 1;
7852         }
7853
7854         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7855             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7856                 nested_vmx_failValid(vcpu,
7857                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7858                 return 1;
7859         }
7860
7861         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7862             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7863                 nested_vmx_entry_failure(vcpu, vmcs12,
7864                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7865                 return 1;
7866         }
7867         if (vmcs12->vmcs_link_pointer != -1ull) {
7868                 nested_vmx_entry_failure(vcpu, vmcs12,
7869                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7870                 return 1;
7871         }
7872
7873         /*
7874          * If the load IA32_EFER VM-entry control is 1, the following checks
7875          * are performed on the field for the IA32_EFER MSR:
7876          * - Bits reserved in the IA32_EFER MSR must be 0.
7877          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7878          *   the IA-32e mode guest VM-exit control. It must also be identical
7879          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7880          *   CR0.PG) is 1.
7881          */
7882         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7883                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7884                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7885                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7886                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7887                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7888                         nested_vmx_entry_failure(vcpu, vmcs12,
7889                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7890                         return 1;
7891                 }
7892         }
7893
7894         /*
7895          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7896          * IA32_EFER MSR must be 0 in the field for that register. In addition,
7897          * the values of the LMA and LME bits in the field must each be that of
7898          * the host address-space size VM-exit control.
7899          */
7900         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7901                 ia32e = (vmcs12->vm_exit_controls &
7902                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7903                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7904                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7905                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7906                         nested_vmx_entry_failure(vcpu, vmcs12,
7907                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7908                         return 1;
7909                 }
7910         }
7911
7912         /*
7913          * We're finally done with prerequisite checking, and can start with
7914          * the nested entry.
7915          */
7916
7917         vmcs02 = nested_get_current_vmcs02(vmx);
7918         if (!vmcs02)
7919                 return -ENOMEM;
7920
7921         enter_guest_mode(vcpu);
7922
7923         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7924
7925         cpu = get_cpu();
7926         vmx->loaded_vmcs = vmcs02;
7927         vmx_vcpu_put(vcpu);
7928         vmx_vcpu_load(vcpu, cpu);
7929         vcpu->cpu = cpu;
7930         put_cpu();
7931
7932         vmx_segment_cache_clear(vmx);
7933
7934         vmcs12->launch_state = 1;
7935
7936         prepare_vmcs02(vcpu, vmcs12);
7937
7938         /*
7939          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7940          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7941          * returned as far as L1 is concerned. It will only return (and set
7942          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7943          */
7944         return 1;
7945 }
7946
7947 /*
7948  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7949  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7950  * This function returns the new value we should put in vmcs12.guest_cr0.
7951  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7952  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7953  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7954  *     didn't trap the bit, because if L1 did, so would L0).
7955  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7956  *     been modified by L2, and L1 knows it. So just leave the old value of
7957  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7958  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7959  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7960  *     changed these bits, and therefore they need to be updated, but L0
7961  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7962  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7963  */
7964 static inline unsigned long
7965 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7966 {
7967         return
7968         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7969         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7970         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7971                         vcpu->arch.cr0_guest_owned_bits));
7972 }
7973
7974 static inline unsigned long
7975 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7976 {
7977         return
7978         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7979         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7980         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7981                         vcpu->arch.cr4_guest_owned_bits));
7982 }
7983
7984 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7985                                        struct vmcs12 *vmcs12)
7986 {
7987         u32 idt_vectoring;
7988         unsigned int nr;
7989
7990         if (vcpu->arch.exception.pending) {
7991                 nr = vcpu->arch.exception.nr;
7992                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7993
7994                 if (kvm_exception_is_soft(nr)) {
7995                         vmcs12->vm_exit_instruction_len =
7996                                 vcpu->arch.event_exit_inst_len;
7997                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7998                 } else
7999                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8000
8001                 if (vcpu->arch.exception.has_error_code) {
8002                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8003                         vmcs12->idt_vectoring_error_code =
8004                                 vcpu->arch.exception.error_code;
8005                 }
8006
8007                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8008         } else if (vcpu->arch.nmi_pending) {
8009                 vmcs12->idt_vectoring_info_field =
8010                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8011         } else if (vcpu->arch.interrupt.pending) {
8012                 nr = vcpu->arch.interrupt.nr;
8013                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8014
8015                 if (vcpu->arch.interrupt.soft) {
8016                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8017                         vmcs12->vm_entry_instruction_len =
8018                                 vcpu->arch.event_exit_inst_len;
8019                 } else
8020                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8021
8022                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8023         }
8024 }
8025
8026 /*
8027  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8028  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8029  * and this function updates it to reflect the changes to the guest state while
8030  * L2 was running (and perhaps made some exits which were handled directly by L0
8031  * without going back to L1), and to reflect the exit reason.
8032  * Note that we do not have to copy here all VMCS fields, just those that
8033  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8034  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8035  * which already writes to vmcs12 directly.
8036  */
8037 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8038 {
8039         /* update guest state fields: */
8040         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8041         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8042
8043         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8044         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8045         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8046         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8047
8048         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8049         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8050         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8051         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8052         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8053         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8054         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8055         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8056         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8057         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8058         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8059         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8060         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8061         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8062         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8063         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8064         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8065         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8066         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8067         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8068         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8069         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8070         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8071         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8072         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8073         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8074         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8075         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8076         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8077         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8078         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8079         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8080         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8081         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8082         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8083         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8084
8085         vmcs12->guest_interruptibility_info =
8086                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8087         vmcs12->guest_pending_dbg_exceptions =
8088                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8089
8090         /*
8091          * In some cases (usually, nested EPT), L2 is allowed to change its
8092          * own CR3 without exiting. If it has changed it, we must keep it.
8093          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8094          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8095          *
8096          * Additionally, restore L2's PDPTR to vmcs12.
8097          */
8098         if (enable_ept) {
8099                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8100                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8101                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8102                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8103                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8104         }
8105
8106         vmcs12->vm_entry_controls =
8107                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8108                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8109
8110         /* TODO: These cannot have changed unless we have MSR bitmaps and
8111          * the relevant bit asks not to trap the change */
8112         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8113         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8114                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8115         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8116         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8117         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8118
8119         /* update exit information fields: */
8120
8121         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
8122         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8123
8124         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8125         if ((vmcs12->vm_exit_intr_info &
8126              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8127             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8128                 vmcs12->vm_exit_intr_error_code =
8129                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8130         vmcs12->idt_vectoring_info_field = 0;
8131         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8132         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8133
8134         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8135                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8136                  * instead of reading the real value. */
8137                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8138
8139                 /*
8140                  * Transfer the event that L0 or L1 may wanted to inject into
8141                  * L2 to IDT_VECTORING_INFO_FIELD.
8142                  */
8143                 vmcs12_save_pending_event(vcpu, vmcs12);
8144         }
8145
8146         /*
8147          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8148          * preserved above and would only end up incorrectly in L1.
8149          */
8150         vcpu->arch.nmi_injected = false;
8151         kvm_clear_exception_queue(vcpu);
8152         kvm_clear_interrupt_queue(vcpu);
8153 }
8154
8155 /*
8156  * A part of what we need to when the nested L2 guest exits and we want to
8157  * run its L1 parent, is to reset L1's guest state to the host state specified
8158  * in vmcs12.
8159  * This function is to be called not only on normal nested exit, but also on
8160  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8161  * Failures During or After Loading Guest State").
8162  * This function should be called when the active VMCS is L1's (vmcs01).
8163  */
8164 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8165                                    struct vmcs12 *vmcs12)
8166 {
8167         struct kvm_segment seg;
8168
8169         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8170                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8171         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8172                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8173         else
8174                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8175         vmx_set_efer(vcpu, vcpu->arch.efer);
8176
8177         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8178         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8179         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8180         /*
8181          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8182          * actually changed, because it depends on the current state of
8183          * fpu_active (which may have changed).
8184          * Note that vmx_set_cr0 refers to efer set above.
8185          */
8186         kvm_set_cr0(vcpu, vmcs12->host_cr0);
8187         /*
8188          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8189          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8190          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8191          */
8192         update_exception_bitmap(vcpu);
8193         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8194         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8195
8196         /*
8197          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8198          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8199          */
8200         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8201         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8202
8203         if (nested_cpu_has_ept(vmcs12))
8204                 nested_ept_uninit_mmu_context(vcpu);
8205
8206         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8207         kvm_mmu_reset_context(vcpu);
8208
8209         if (enable_vpid) {
8210                 /*
8211                  * Trivially support vpid by letting L2s share their parent
8212                  * L1's vpid. TODO: move to a more elaborate solution, giving
8213                  * each L2 its own vpid and exposing the vpid feature to L1.
8214                  */
8215                 vmx_flush_tlb(vcpu);
8216         }
8217
8218
8219         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8220         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8221         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8222         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8223         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8224
8225         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8226                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8227                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8228         }
8229         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8230                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8231                         vmcs12->host_ia32_perf_global_ctrl);
8232
8233         /* Set L1 segment info according to Intel SDM
8234             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8235         seg = (struct kvm_segment) {
8236                 .base = 0,
8237                 .limit = 0xFFFFFFFF,
8238                 .selector = vmcs12->host_cs_selector,
8239                 .type = 11,
8240                 .present = 1,
8241                 .s = 1,
8242                 .g = 1
8243         };
8244         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8245                 seg.l = 1;
8246         else
8247                 seg.db = 1;
8248         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8249         seg = (struct kvm_segment) {
8250                 .base = 0,
8251                 .limit = 0xFFFFFFFF,
8252                 .type = 3,
8253                 .present = 1,
8254                 .s = 1,
8255                 .db = 1,
8256                 .g = 1
8257         };
8258         seg.selector = vmcs12->host_ds_selector;
8259         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8260         seg.selector = vmcs12->host_es_selector;
8261         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8262         seg.selector = vmcs12->host_ss_selector;
8263         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8264         seg.selector = vmcs12->host_fs_selector;
8265         seg.base = vmcs12->host_fs_base;
8266         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8267         seg.selector = vmcs12->host_gs_selector;
8268         seg.base = vmcs12->host_gs_base;
8269         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8270         seg = (struct kvm_segment) {
8271                 .base = vmcs12->host_tr_base,
8272                 .limit = 0x67,
8273                 .selector = vmcs12->host_tr_selector,
8274                 .type = 11,
8275                 .present = 1
8276         };
8277         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8278
8279         kvm_set_dr(vcpu, 7, 0x400);
8280         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8281 }
8282
8283 /*
8284  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8285  * and modify vmcs12 to make it see what it would expect to see there if
8286  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8287  */
8288 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8289 {
8290         struct vcpu_vmx *vmx = to_vmx(vcpu);
8291         int cpu;
8292         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8293
8294         /* trying to cancel vmlaunch/vmresume is a bug */
8295         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8296
8297         leave_guest_mode(vcpu);
8298         prepare_vmcs12(vcpu, vmcs12);
8299
8300         cpu = get_cpu();
8301         vmx->loaded_vmcs = &vmx->vmcs01;
8302         vmx_vcpu_put(vcpu);
8303         vmx_vcpu_load(vcpu, cpu);
8304         vcpu->cpu = cpu;
8305         put_cpu();
8306
8307         vmx_segment_cache_clear(vmx);
8308
8309         /* if no vmcs02 cache requested, remove the one we used */
8310         if (VMCS02_POOL_SIZE == 0)
8311                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8312
8313         load_vmcs12_host_state(vcpu, vmcs12);
8314
8315         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8316         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8317
8318         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8319         vmx->host_rsp = 0;
8320
8321         /* Unpin physical memory we referred to in vmcs02 */
8322         if (vmx->nested.apic_access_page) {
8323                 nested_release_page(vmx->nested.apic_access_page);
8324                 vmx->nested.apic_access_page = 0;
8325         }
8326
8327         /*
8328          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8329          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8330          * success or failure flag accordingly.
8331          */
8332         if (unlikely(vmx->fail)) {
8333                 vmx->fail = 0;
8334                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8335         } else
8336                 nested_vmx_succeed(vcpu);
8337         if (enable_shadow_vmcs)
8338                 vmx->nested.sync_shadow_vmcs = true;
8339 }
8340
8341 /*
8342  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8343  * 23.7 "VM-entry failures during or after loading guest state" (this also
8344  * lists the acceptable exit-reason and exit-qualification parameters).
8345  * It should only be called before L2 actually succeeded to run, and when
8346  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8347  */
8348 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8349                         struct vmcs12 *vmcs12,
8350                         u32 reason, unsigned long qualification)
8351 {
8352         load_vmcs12_host_state(vcpu, vmcs12);
8353         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8354         vmcs12->exit_qualification = qualification;
8355         nested_vmx_succeed(vcpu);
8356         if (enable_shadow_vmcs)
8357                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8358 }
8359
8360 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8361                                struct x86_instruction_info *info,
8362                                enum x86_intercept_stage stage)
8363 {
8364         return X86EMUL_CONTINUE;
8365 }
8366
8367 static struct kvm_x86_ops vmx_x86_ops = {
8368         .cpu_has_kvm_support = cpu_has_kvm_support,
8369         .disabled_by_bios = vmx_disabled_by_bios,
8370         .hardware_setup = hardware_setup,
8371         .hardware_unsetup = hardware_unsetup,
8372         .check_processor_compatibility = vmx_check_processor_compat,
8373         .hardware_enable = hardware_enable,
8374         .hardware_disable = hardware_disable,
8375         .cpu_has_accelerated_tpr = report_flexpriority,
8376
8377         .vcpu_create = vmx_create_vcpu,
8378         .vcpu_free = vmx_free_vcpu,
8379         .vcpu_reset = vmx_vcpu_reset,
8380
8381         .prepare_guest_switch = vmx_save_host_state,
8382         .vcpu_load = vmx_vcpu_load,
8383         .vcpu_put = vmx_vcpu_put,
8384
8385         .update_db_bp_intercept = update_exception_bitmap,
8386         .get_msr = vmx_get_msr,
8387         .set_msr = vmx_set_msr,
8388         .get_segment_base = vmx_get_segment_base,
8389         .get_segment = vmx_get_segment,
8390         .set_segment = vmx_set_segment,
8391         .get_cpl = vmx_get_cpl,
8392         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8393         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8394         .decache_cr3 = vmx_decache_cr3,
8395         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8396         .set_cr0 = vmx_set_cr0,
8397         .set_cr3 = vmx_set_cr3,
8398         .set_cr4 = vmx_set_cr4,
8399         .set_efer = vmx_set_efer,
8400         .get_idt = vmx_get_idt,
8401         .set_idt = vmx_set_idt,
8402         .get_gdt = vmx_get_gdt,
8403         .set_gdt = vmx_set_gdt,
8404         .set_dr7 = vmx_set_dr7,
8405         .cache_reg = vmx_cache_reg,
8406         .get_rflags = vmx_get_rflags,
8407         .set_rflags = vmx_set_rflags,
8408         .fpu_activate = vmx_fpu_activate,
8409         .fpu_deactivate = vmx_fpu_deactivate,
8410
8411         .tlb_flush = vmx_flush_tlb,
8412
8413         .run = vmx_vcpu_run,
8414         .handle_exit = vmx_handle_exit,
8415         .skip_emulated_instruction = skip_emulated_instruction,
8416         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8417         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8418         .patch_hypercall = vmx_patch_hypercall,
8419         .set_irq = vmx_inject_irq,
8420         .set_nmi = vmx_inject_nmi,
8421         .queue_exception = vmx_queue_exception,
8422         .cancel_injection = vmx_cancel_injection,
8423         .interrupt_allowed = vmx_interrupt_allowed,
8424         .nmi_allowed = vmx_nmi_allowed,
8425         .get_nmi_mask = vmx_get_nmi_mask,
8426         .set_nmi_mask = vmx_set_nmi_mask,
8427         .enable_nmi_window = enable_nmi_window,
8428         .enable_irq_window = enable_irq_window,
8429         .update_cr8_intercept = update_cr8_intercept,
8430         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8431         .vm_has_apicv = vmx_vm_has_apicv,
8432         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8433         .hwapic_irr_update = vmx_hwapic_irr_update,
8434         .hwapic_isr_update = vmx_hwapic_isr_update,
8435         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8436         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8437
8438         .set_tss_addr = vmx_set_tss_addr,
8439         .get_tdp_level = get_ept_level,
8440         .get_mt_mask = vmx_get_mt_mask,
8441
8442         .get_exit_info = vmx_get_exit_info,
8443
8444         .get_lpage_level = vmx_get_lpage_level,
8445
8446         .cpuid_update = vmx_cpuid_update,
8447
8448         .rdtscp_supported = vmx_rdtscp_supported,
8449         .invpcid_supported = vmx_invpcid_supported,
8450
8451         .set_supported_cpuid = vmx_set_supported_cpuid,
8452
8453         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8454
8455         .set_tsc_khz = vmx_set_tsc_khz,
8456         .read_tsc_offset = vmx_read_tsc_offset,
8457         .write_tsc_offset = vmx_write_tsc_offset,
8458         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8459         .compute_tsc_offset = vmx_compute_tsc_offset,
8460         .read_l1_tsc = vmx_read_l1_tsc,
8461
8462         .set_tdp_cr3 = vmx_set_cr3,
8463
8464         .check_intercept = vmx_check_intercept,
8465         .handle_external_intr = vmx_handle_external_intr,
8466 };
8467
8468 static int __init vmx_init(void)
8469 {
8470         int r, i, msr;
8471
8472         rdmsrl_safe(MSR_EFER, &host_efer);
8473
8474         for (i = 0; i < NR_VMX_MSR; ++i)
8475                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8476
8477         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8478         if (!vmx_io_bitmap_a)
8479                 return -ENOMEM;
8480
8481         r = -ENOMEM;
8482
8483         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8484         if (!vmx_io_bitmap_b)
8485                 goto out;
8486
8487         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8488         if (!vmx_msr_bitmap_legacy)
8489                 goto out1;
8490
8491         vmx_msr_bitmap_legacy_x2apic =
8492                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8493         if (!vmx_msr_bitmap_legacy_x2apic)
8494                 goto out2;
8495
8496         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8497         if (!vmx_msr_bitmap_longmode)
8498                 goto out3;
8499
8500         vmx_msr_bitmap_longmode_x2apic =
8501                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8502         if (!vmx_msr_bitmap_longmode_x2apic)
8503                 goto out4;
8504         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8505         if (!vmx_vmread_bitmap)
8506                 goto out5;
8507
8508         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8509         if (!vmx_vmwrite_bitmap)
8510                 goto out6;
8511
8512         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8513         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8514         /* shadowed read/write fields */
8515         for (i = 0; i < max_shadow_read_write_fields; i++) {
8516                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8517                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8518         }
8519         /* shadowed read only fields */
8520         for (i = 0; i < max_shadow_read_only_fields; i++)
8521                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8522
8523         /*
8524          * Allow direct access to the PC debug port (it is often used for I/O
8525          * delays, but the vmexits simply slow things down).
8526          */
8527         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8528         clear_bit(0x80, vmx_io_bitmap_a);
8529
8530         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8531
8532         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8533         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8534
8535         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8536
8537         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8538                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8539         if (r)
8540                 goto out7;
8541
8542 #ifdef CONFIG_KEXEC
8543         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8544                            crash_vmclear_local_loaded_vmcss);
8545 #endif
8546
8547         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8548         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8549         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8550         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8551         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8552         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8553         memcpy(vmx_msr_bitmap_legacy_x2apic,
8554                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8555         memcpy(vmx_msr_bitmap_longmode_x2apic,
8556                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8557
8558         if (enable_apicv) {
8559                 for (msr = 0x800; msr <= 0x8ff; msr++)
8560                         vmx_disable_intercept_msr_read_x2apic(msr);
8561
8562                 /* According SDM, in x2apic mode, the whole id reg is used.
8563                  * But in KVM, it only use the highest eight bits. Need to
8564                  * intercept it */
8565                 vmx_enable_intercept_msr_read_x2apic(0x802);
8566                 /* TMCCT */
8567                 vmx_enable_intercept_msr_read_x2apic(0x839);
8568                 /* TPR */
8569                 vmx_disable_intercept_msr_write_x2apic(0x808);
8570                 /* EOI */
8571                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8572                 /* SELF-IPI */
8573                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8574         }
8575
8576         if (enable_ept) {
8577                 kvm_mmu_set_mask_ptes(0ull,
8578                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8579                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8580                         0ull, VMX_EPT_EXECUTABLE_MASK);
8581                 ept_set_mmio_spte_mask();
8582                 kvm_enable_tdp();
8583         } else
8584                 kvm_disable_tdp();
8585
8586         return 0;
8587
8588 out7:
8589         free_page((unsigned long)vmx_vmwrite_bitmap);
8590 out6:
8591         free_page((unsigned long)vmx_vmread_bitmap);
8592 out5:
8593         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8594 out4:
8595         free_page((unsigned long)vmx_msr_bitmap_longmode);
8596 out3:
8597         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8598 out2:
8599         free_page((unsigned long)vmx_msr_bitmap_legacy);
8600 out1:
8601         free_page((unsigned long)vmx_io_bitmap_b);
8602 out:
8603         free_page((unsigned long)vmx_io_bitmap_a);
8604         return r;
8605 }
8606
8607 static void __exit vmx_exit(void)
8608 {
8609         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8610         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8611         free_page((unsigned long)vmx_msr_bitmap_legacy);
8612         free_page((unsigned long)vmx_msr_bitmap_longmode);
8613         free_page((unsigned long)vmx_io_bitmap_b);
8614         free_page((unsigned long)vmx_io_bitmap_a);
8615         free_page((unsigned long)vmx_vmwrite_bitmap);
8616         free_page((unsigned long)vmx_vmread_bitmap);
8617
8618 #ifdef CONFIG_KEXEC
8619         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8620         synchronize_rcu();
8621 #endif
8622
8623         kvm_exit();
8624 }
8625
8626 module_init(vmx_init)
8627 module_exit(vmx_exit)