Pileus Git - ~andy/linux/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 struct vmcs {
  65         u32 revision_id;
  66         u32 abort;
  67         char data[0];
  68 };
  69
  70 struct vcpu_vmx {
  71         struct kvm_vcpu       vcpu;
  72         struct list_head      local_vcpus_link;
  73         unsigned long         host_rsp;
  74         int                   launched;
  75         u8                    fail;
  76         u32                   idt_vectoring_info;
  77         struct kvm_msr_entry *guest_msrs;
  78         struct kvm_msr_entry *host_msrs;
  79         int                   nmsrs;
  80         int                   save_nmsrs;
  81         int                   msr_offset_efer;
  82 #ifdef CONFIG_X86_64
  83         int                   msr_offset_kernel_gs_base;
  84 #endif
  85         struct vmcs          *vmcs;
  86         struct {
  87                 int           loaded;
  88                 u16           fs_sel, gs_sel, ldt_sel;
  89                 int           gs_ldt_reload_needed;
  90                 int           fs_reload_needed;
  91                 int           guest_efer_loaded;
  92         } host_state;
  93         struct {
  94                 int vm86_active;
  95                 u8 save_iopl;
  96                 struct kvm_save_segment {
  97                         u16 selector;
  98                         unsigned long base;
  99                         u32 limit;
 100                         u32 ar;
 101                 } tr, es, ds, fs, gs;
 102                 struct {
 103                         bool pending;
 104                         u8 vector;
 105                         unsigned rip;
 106                 } irq;
 107         } rmode;
 108         int vpid;
 109         bool emulation_required;
 110         enum emulation_result invalid_state_emulation_result;
 111
 112         /* Support for vnmi-less CPUs */
 113         int soft_vnmi_blocked;
 114         ktime_t entry_time;
 115         s64 vnmi_blocked_time;
 116         u32 exit_reason;
 117 };
 118
 119 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 120 {
 121         return container_of(vcpu, struct vcpu_vmx, vcpu);
 122 }
 123
 124 static int init_rmode(struct kvm *kvm);
 125 static u64 construct_eptp(unsigned long root_hpa);
 126
 127 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 128 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 129 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 130
 131 static unsigned long *vmx_io_bitmap_a;
 132 static unsigned long *vmx_io_bitmap_b;
 133 static unsigned long *vmx_msr_bitmap_legacy;
 134 static unsigned long *vmx_msr_bitmap_longmode;
 135
 136 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 137 static DEFINE_SPINLOCK(vmx_vpid_lock);
 138
 139 static struct vmcs_config {
 140         int size;
 141         int order;
 142         u32 revision_id;
 143         u32 pin_based_exec_ctrl;
 144         u32 cpu_based_exec_ctrl;
 145         u32 cpu_based_2nd_exec_ctrl;
 146         u32 vmexit_ctrl;
 147         u32 vmentry_ctrl;
 148 } vmcs_config;
 149
 150 static struct vmx_capability {
 151         u32 ept;
 152         u32 vpid;
 153 } vmx_capability;
 154
 155 #define VMX_SEGMENT_FIELD(seg)                                  \
 156         [VCPU_SREG_##seg] = {                                   \
 157                 .selector = GUEST_##seg##_SELECTOR,             \
 158                 .base = GUEST_##seg##_BASE,                     \
 159                 .limit = GUEST_##seg##_LIMIT,                   \
 160                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 161         }
 162
 163 static struct kvm_vmx_segment_field {
 164         unsigned selector;
 165         unsigned base;
 166         unsigned limit;
 167         unsigned ar_bytes;
 168 } kvm_vmx_segment_fields[] = {
 169         VMX_SEGMENT_FIELD(CS),
 170         VMX_SEGMENT_FIELD(DS),
 171         VMX_SEGMENT_FIELD(ES),
 172         VMX_SEGMENT_FIELD(FS),
 173         VMX_SEGMENT_FIELD(GS),
 174         VMX_SEGMENT_FIELD(SS),
 175         VMX_SEGMENT_FIELD(TR),
 176         VMX_SEGMENT_FIELD(LDTR),
 177 };
 178
 179 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 180
 181 /*
 182  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 183  * away by decrementing the array size.
 184  */
 185 static const u32 vmx_msr_index[] = {
 186 #ifdef CONFIG_X86_64
 187         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 188 #endif
 189         MSR_EFER, MSR_K6_STAR,
 190 };
 191 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 192
 193 static void load_msrs(struct kvm_msr_entry *e, int n)
 194 {
 195         int i;
 196
 197         for (i = 0; i < n; ++i)
 198                 wrmsrl(e[i].index, e[i].data);
 199 }
 200
 201 static void save_msrs(struct kvm_msr_entry *e, int n)
 202 {
 203         int i;
 204
 205         for (i = 0; i < n; ++i)
 206                 rdmsrl(e[i].index, e[i].data);
 207 }
 208
 209 static inline int is_page_fault(u32 intr_info)
 210 {
 211         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 212                              INTR_INFO_VALID_MASK)) ==
 213                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 214 }
 215
 216 static inline int is_no_device(u32 intr_info)
 217 {
 218         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 219                              INTR_INFO_VALID_MASK)) ==
 220                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 221 }
 222
 223 static inline int is_invalid_opcode(u32 intr_info)
 224 {
 225         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 226                              INTR_INFO_VALID_MASK)) ==
 227                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 228 }
 229
 230 static inline int is_external_interrupt(u32 intr_info)
 231 {
 232         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 233                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 234 }
 235
 236 static inline int is_machine_check(u32 intr_info)
 237 {
 238         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 239                              INTR_INFO_VALID_MASK)) ==
 240                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 241 }
 242
 243 static inline int cpu_has_vmx_msr_bitmap(void)
 244 {
 245         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 246 }
 247
 248 static inline int cpu_has_vmx_tpr_shadow(void)
 249 {
 250         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 251 }
 252
 253 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 254 {
 255         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 256 }
 257
 258 static inline int cpu_has_secondary_exec_ctrls(void)
 259 {
 260         return vmcs_config.cpu_based_exec_ctrl &
 261                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 262 }
 263
 264 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 265 {
 266         return vmcs_config.cpu_based_2nd_exec_ctrl &
 267                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 268 }
 269
 270 static inline bool cpu_has_vmx_flexpriority(void)
 271 {
 272         return cpu_has_vmx_tpr_shadow() &&
 273                 cpu_has_vmx_virtualize_apic_accesses();
 274 }
 275
 276 static inline bool cpu_has_vmx_ept_execute_only(void)
 277 {
 278         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 279 }
 280
 281 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 282 {
 283         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 284 }
 285
 286 static inline bool cpu_has_vmx_eptp_writeback(void)
 287 {
 288         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 289 }
 290
 291 static inline bool cpu_has_vmx_ept_2m_page(void)
 292 {
 293         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 294 }
 295
 296 static inline int cpu_has_vmx_invept_individual_addr(void)
 297 {
 298         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 299 }
 300
 301 static inline int cpu_has_vmx_invept_context(void)
 302 {
 303         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 304 }
 305
 306 static inline int cpu_has_vmx_invept_global(void)
 307 {
 308         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 309 }
 310
 311 static inline int cpu_has_vmx_ept(void)
 312 {
 313         return vmcs_config.cpu_based_2nd_exec_ctrl &
 314                 SECONDARY_EXEC_ENABLE_EPT;
 315 }
 316
 317 static inline int cpu_has_vmx_unrestricted_guest(void)
 318 {
 319         return vmcs_config.cpu_based_2nd_exec_ctrl &
 320                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 321 }
 322
 323 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 324 {
 325         return flexpriority_enabled &&
 326                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 327                 (irqchip_in_kernel(kvm));
 328 }
 329
 330 static inline int cpu_has_vmx_vpid(void)
 331 {
 332         return vmcs_config.cpu_based_2nd_exec_ctrl &
 333                 SECONDARY_EXEC_ENABLE_VPID;
 334 }
 335
 336 static inline int cpu_has_virtual_nmis(void)
 337 {
 338         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 339 }
 340
 341 static inline bool report_flexpriority(void)
 342 {
 343         return flexpriority_enabled;
 344 }
 345
 346 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 347 {
 348         int i;
 349
 350         for (i = 0; i < vmx->nmsrs; ++i)
 351                 if (vmx->guest_msrs[i].index == msr)
 352                         return i;
 353         return -1;
 354 }
 355
 356 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 357 {
 358     struct {
 359         u64 vpid : 16;
 360         u64 rsvd : 48;
 361         u64 gva;
 362     } operand = { vpid, 0, gva };
 363
 364     asm volatile (__ex(ASM_VMX_INVVPID)
 365                   /* CF==1 or ZF==1 --> rc = -1 */
 366                   "; ja 1f ; ud2 ; 1:"
 367                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 368 }
 369
 370 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 371 {
 372         struct {
 373                 u64 eptp, gpa;
 374         } operand = {eptp, gpa};
 375
 376         asm volatile (__ex(ASM_VMX_INVEPT)
 377                         /* CF==1 or ZF==1 --> rc = -1 */
 378                         "; ja 1f ; ud2 ; 1:\n"
 379                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 380 }
 381
 382 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 383 {
 384         int i;
 385
 386         i = __find_msr_index(vmx, msr);
 387         if (i >= 0)
 388                 return &vmx->guest_msrs[i];
 389         return NULL;
 390 }
 391
 392 static void vmcs_clear(struct vmcs *vmcs)
 393 {
 394         u64 phys_addr = __pa(vmcs);
 395         u8 error;
 396
 397         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 398                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 399                       : "cc", "memory");
 400         if (error)
 401                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 402                        vmcs, phys_addr);
 403 }
 404
 405 static void __vcpu_clear(void *arg)
 406 {
 407         struct vcpu_vmx *vmx = arg;
 408         int cpu = raw_smp_processor_id();
 409
 410         if (vmx->vcpu.cpu == cpu)
 411                 vmcs_clear(vmx->vmcs);
 412         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 413                 per_cpu(current_vmcs, cpu) = NULL;
 414         rdtscll(vmx->vcpu.arch.host_tsc);
 415         list_del(&vmx->local_vcpus_link);
 416         vmx->vcpu.cpu = -1;
 417         vmx->launched = 0;
 418 }
 419
 420 static void vcpu_clear(struct vcpu_vmx *vmx)
 421 {
 422         if (vmx->vcpu.cpu == -1)
 423                 return;
 424         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 425 }
 426
 427 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 428 {
 429         if (vmx->vpid == 0)
 430                 return;
 431
 432         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 433 }
 434
 435 static inline void ept_sync_global(void)
 436 {
 437         if (cpu_has_vmx_invept_global())
 438                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 439 }
 440
 441 static inline void ept_sync_context(u64 eptp)
 442 {
 443         if (enable_ept) {
 444                 if (cpu_has_vmx_invept_context())
 445                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 446                 else
 447                         ept_sync_global();
 448         }
 449 }
 450
 451 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 452 {
 453         if (enable_ept) {
 454                 if (cpu_has_vmx_invept_individual_addr())
 455                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 456                                         eptp, gpa);
 457                 else
 458                         ept_sync_context(eptp);
 459         }
 460 }
 461
 462 static unsigned long vmcs_readl(unsigned long field)
 463 {
 464         unsigned long value;
 465
 466         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 467                       : "=a"(value) : "d"(field) : "cc");
 468         return value;
 469 }
 470
 471 static u16 vmcs_read16(unsigned long field)
 472 {
 473         return vmcs_readl(field);
 474 }
 475
 476 static u32 vmcs_read32(unsigned long field)
 477 {
 478         return vmcs_readl(field);
 479 }
 480
 481 static u64 vmcs_read64(unsigned long field)
 482 {
 483 #ifdef CONFIG_X86_64
 484         return vmcs_readl(field);
 485 #else
 486         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 487 #endif
 488 }
 489
 490 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 491 {
 492         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 493                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 494         dump_stack();
 495 }
 496
 497 static void vmcs_writel(unsigned long field, unsigned long value)
 498 {
 499         u8 error;
 500
 501         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 502                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 503         if (unlikely(error))
 504                 vmwrite_error(field, value);
 505 }
 506
 507 static void vmcs_write16(unsigned long field, u16 value)
 508 {
 509         vmcs_writel(field, value);
 510 }
 511
 512 static void vmcs_write32(unsigned long field, u32 value)
 513 {
 514         vmcs_writel(field, value);
 515 }
 516
 517 static void vmcs_write64(unsigned long field, u64 value)
 518 {
 519         vmcs_writel(field, value);
 520 #ifndef CONFIG_X86_64
 521         asm volatile ("");
 522         vmcs_writel(field+1, value >> 32);
 523 #endif
 524 }
 525
 526 static void vmcs_clear_bits(unsigned long field, u32 mask)
 527 {
 528         vmcs_writel(field, vmcs_readl(field) & ~mask);
 529 }
 530
 531 static void vmcs_set_bits(unsigned long field, u32 mask)
 532 {
 533         vmcs_writel(field, vmcs_readl(field) | mask);
 534 }
 535
 536 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 537 {
 538         u32 eb;
 539
 540         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
 541         if (!vcpu->fpu_active)
 542                 eb |= 1u << NM_VECTOR;
 543         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 544                 if (vcpu->guest_debug &
 545                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 546                         eb |= 1u << DB_VECTOR;
 547                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 548                         eb |= 1u << BP_VECTOR;
 549         }
 550         if (to_vmx(vcpu)->rmode.vm86_active)
 551                 eb = ~0;
 552         if (enable_ept)
 553                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 554         vmcs_write32(EXCEPTION_BITMAP, eb);
 555 }
 556
 557 static void reload_tss(void)
 558 {
 559         /*
 560          * VT restores TR but not its size.  Useless.
 561          */
 562         struct descriptor_table gdt;
 563         struct desc_struct *descs;
 564
 565         kvm_get_gdt(&gdt);
 566         descs = (void *)gdt.base;
 567         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 568         load_TR_desc();
 569 }
 570
 571 static void load_transition_efer(struct vcpu_vmx *vmx)
 572 {
 573         int efer_offset = vmx->msr_offset_efer;
 574         u64 host_efer;
 575         u64 guest_efer;
 576         u64 ignore_bits;
 577
 578         if (efer_offset < 0)
 579                 return;
 580         host_efer = vmx->host_msrs[efer_offset].data;
 581         guest_efer = vmx->guest_msrs[efer_offset].data;
 582
 583         /*
 584          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 585          * outside long mode
 586          */
 587         ignore_bits = EFER_NX | EFER_SCE;
 588 #ifdef CONFIG_X86_64
 589         ignore_bits |= EFER_LMA | EFER_LME;
 590         /* SCE is meaningful only in long mode on Intel */
 591         if (guest_efer & EFER_LMA)
 592                 ignore_bits &= ~(u64)EFER_SCE;
 593 #endif
 594         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 595                 return;
 596
 597         vmx->host_state.guest_efer_loaded = 1;
 598         guest_efer &= ~ignore_bits;
 599         guest_efer |= host_efer & ignore_bits;
 600         wrmsrl(MSR_EFER, guest_efer);
 601         vmx->vcpu.stat.efer_reload++;
 602 }
 603
 604 static void reload_host_efer(struct vcpu_vmx *vmx)
 605 {
 606         if (vmx->host_state.guest_efer_loaded) {
 607                 vmx->host_state.guest_efer_loaded = 0;
 608                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 609         }
 610 }
 611
 612 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 613 {
 614         struct vcpu_vmx *vmx = to_vmx(vcpu);
 615
 616         if (vmx->host_state.loaded)
 617                 return;
 618
 619         vmx->host_state.loaded = 1;
 620         /*
 621          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 622          * allow segment selectors with cpl > 0 or ti == 1.
 623          */
 624         vmx->host_state.ldt_sel = kvm_read_ldt();
 625         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 626         vmx->host_state.fs_sel = kvm_read_fs();
 627         if (!(vmx->host_state.fs_sel & 7)) {
 628                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 629                 vmx->host_state.fs_reload_needed = 0;
 630         } else {
 631                 vmcs_write16(HOST_FS_SELECTOR, 0);
 632                 vmx->host_state.fs_reload_needed = 1;
 633         }
 634         vmx->host_state.gs_sel = kvm_read_gs();
 635         if (!(vmx->host_state.gs_sel & 7))
 636                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 637         else {
 638                 vmcs_write16(HOST_GS_SELECTOR, 0);
 639                 vmx->host_state.gs_ldt_reload_needed = 1;
 640         }
 641
 642 #ifdef CONFIG_X86_64
 643         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 644         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 645 #else
 646         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 647         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 648 #endif
 649
 650 #ifdef CONFIG_X86_64
 651         if (is_long_mode(&vmx->vcpu))
 652                 save_msrs(vmx->host_msrs +
 653                           vmx->msr_offset_kernel_gs_base, 1);
 654
 655 #endif
 656         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 657         load_transition_efer(vmx);
 658 }
 659
 660 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 661 {
 662         unsigned long flags;
 663
 664         if (!vmx->host_state.loaded)
 665                 return;
 666
 667         ++vmx->vcpu.stat.host_state_reload;
 668         vmx->host_state.loaded = 0;
 669         if (vmx->host_state.fs_reload_needed)
 670                 kvm_load_fs(vmx->host_state.fs_sel);
 671         if (vmx->host_state.gs_ldt_reload_needed) {
 672                 kvm_load_ldt(vmx->host_state.ldt_sel);
 673                 /*
 674                  * If we have to reload gs, we must take care to
 675                  * preserve our gs base.
 676                  */
 677                 local_irq_save(flags);
 678                 kvm_load_gs(vmx->host_state.gs_sel);
 679 #ifdef CONFIG_X86_64
 680                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 681 #endif
 682                 local_irq_restore(flags);
 683         }
 684         reload_tss();
 685         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 686         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 687         reload_host_efer(vmx);
 688 }
 689
 690 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 691 {
 692         preempt_disable();
 693         __vmx_load_host_state(vmx);
 694         preempt_enable();
 695 }
 696
 697 /*
 698  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 699  * vcpu mutex is already taken.
 700  */
 701 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 702 {
 703         struct vcpu_vmx *vmx = to_vmx(vcpu);
 704         u64 phys_addr = __pa(vmx->vmcs);
 705         u64 tsc_this, delta, new_offset;
 706
 707         if (vcpu->cpu != cpu) {
 708                 vcpu_clear(vmx);
 709                 kvm_migrate_timers(vcpu);
 710                 vpid_sync_vcpu_all(vmx);
 711                 local_irq_disable();
 712                 list_add(&vmx->local_vcpus_link,
 713                          &per_cpu(vcpus_on_cpu, cpu));
 714                 local_irq_enable();
 715         }
 716
 717         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 718                 u8 error;
 719
 720                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 721                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 722                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 723                               : "cc");
 724                 if (error)
 725                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 726                                vmx->vmcs, phys_addr);
 727         }
 728
 729         if (vcpu->cpu != cpu) {
 730                 struct descriptor_table dt;
 731                 unsigned long sysenter_esp;
 732
 733                 vcpu->cpu = cpu;
 734                 /*
 735                  * Linux uses per-cpu TSS and GDT, so set these when switching
 736                  * processors.
 737                  */
 738                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 739                 kvm_get_gdt(&dt);
 740                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 741
 742                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 743                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 744
 745                 /*
 746                  * Make sure the time stamp counter is monotonous.
 747                  */
 748                 rdtscll(tsc_this);
 749                 if (tsc_this < vcpu->arch.host_tsc) {
 750                         delta = vcpu->arch.host_tsc - tsc_this;
 751                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 752                         vmcs_write64(TSC_OFFSET, new_offset);
 753                 }
 754         }
 755 }
 756
 757 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 758 {
 759         __vmx_load_host_state(to_vmx(vcpu));
 760 }
 761
 762 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 763 {
 764         if (vcpu->fpu_active)
 765                 return;
 766         vcpu->fpu_active = 1;
 767         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 768         if (vcpu->arch.cr0 & X86_CR0_TS)
 769                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 770         update_exception_bitmap(vcpu);
 771 }
 772
 773 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 774 {
 775         if (!vcpu->fpu_active)
 776                 return;
 777         vcpu->fpu_active = 0;
 778         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 779         update_exception_bitmap(vcpu);
 780 }
 781
 782 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 783 {
 784         unsigned long rflags;
 785
 786         rflags = vmcs_readl(GUEST_RFLAGS);
 787         if (to_vmx(vcpu)->rmode.vm86_active)
 788                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 789         return rflags;
 790 }
 791
 792 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 793 {
 794         if (to_vmx(vcpu)->rmode.vm86_active)
 795                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 796         vmcs_writel(GUEST_RFLAGS, rflags);
 797 }
 798
 799 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 800 {
 801         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 802         int ret = 0;
 803
 804         if (interruptibility & GUEST_INTR_STATE_STI)
 805                 ret |= X86_SHADOW_INT_STI;
 806         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 807                 ret |= X86_SHADOW_INT_MOV_SS;
 808
 809         return ret & mask;
 810 }
 811
 812 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 813 {
 814         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 815         u32 interruptibility = interruptibility_old;
 816
 817         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 818
 819         if (mask & X86_SHADOW_INT_MOV_SS)
 820                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 821         if (mask & X86_SHADOW_INT_STI)
 822                 interruptibility |= GUEST_INTR_STATE_STI;
 823
 824         if ((interruptibility != interruptibility_old))
 825                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 826 }
 827
 828 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 829 {
 830         unsigned long rip;
 831
 832         rip = kvm_rip_read(vcpu);
 833         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 834         kvm_rip_write(vcpu, rip);
 835
 836         /* skipping an emulated instruction also counts */
 837         vmx_set_interrupt_shadow(vcpu, 0);
 838 }
 839
 840 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 841                                 bool has_error_code, u32 error_code)
 842 {
 843         struct vcpu_vmx *vmx = to_vmx(vcpu);
 844         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 845
 846         if (has_error_code) {
 847                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 848                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 849         }
 850
 851         if (vmx->rmode.vm86_active) {
 852                 vmx->rmode.irq.pending = true;
 853                 vmx->rmode.irq.vector = nr;
 854                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 855                 if (kvm_exception_is_soft(nr))
 856                         vmx->rmode.irq.rip +=
 857                                 vmx->vcpu.arch.event_exit_inst_len;
 858                 intr_info |= INTR_TYPE_SOFT_INTR;
 859                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 860                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 861                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 862                 return;
 863         }
 864
 865         if (kvm_exception_is_soft(nr)) {
 866                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 867                              vmx->vcpu.arch.event_exit_inst_len);
 868                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 869         } else
 870                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 871
 872         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 873 }
 874
 875 /*
 876  * Swap MSR entry in host/guest MSR entry array.
 877  */
 878 #ifdef CONFIG_X86_64
 879 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 880 {
 881         struct kvm_msr_entry tmp;
 882
 883         tmp = vmx->guest_msrs[to];
 884         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 885         vmx->guest_msrs[from] = tmp;
 886         tmp = vmx->host_msrs[to];
 887         vmx->host_msrs[to] = vmx->host_msrs[from];
 888         vmx->host_msrs[from] = tmp;
 889 }
 890 #endif
 891
 892 /*
 893  * Set up the vmcs to automatically save and restore system
 894  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 895  * mode, as fiddling with msrs is very expensive.
 896  */
 897 static void setup_msrs(struct vcpu_vmx *vmx)
 898 {
 899         int save_nmsrs;
 900         unsigned long *msr_bitmap;
 901
 902         vmx_load_host_state(vmx);
 903         save_nmsrs = 0;
 904 #ifdef CONFIG_X86_64
 905         if (is_long_mode(&vmx->vcpu)) {
 906                 int index;
 907
 908                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 909                 if (index >= 0)
 910                         move_msr_up(vmx, index, save_nmsrs++);
 911                 index = __find_msr_index(vmx, MSR_LSTAR);
 912                 if (index >= 0)
 913                         move_msr_up(vmx, index, save_nmsrs++);
 914                 index = __find_msr_index(vmx, MSR_CSTAR);
 915                 if (index >= 0)
 916                         move_msr_up(vmx, index, save_nmsrs++);
 917                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 918                 if (index >= 0)
 919                         move_msr_up(vmx, index, save_nmsrs++);
 920                 /*
 921                  * MSR_K6_STAR is only needed on long mode guests, and only
 922                  * if efer.sce is enabled.
 923                  */
 924                 index = __find_msr_index(vmx, MSR_K6_STAR);
 925                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 926                         move_msr_up(vmx, index, save_nmsrs++);
 927         }
 928 #endif
 929         vmx->save_nmsrs = save_nmsrs;
 930
 931 #ifdef CONFIG_X86_64
 932         vmx->msr_offset_kernel_gs_base =
 933                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 934 #endif
 935         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 936
 937         if (cpu_has_vmx_msr_bitmap()) {
 938                 if (is_long_mode(&vmx->vcpu))
 939                         msr_bitmap = vmx_msr_bitmap_longmode;
 940                 else
 941                         msr_bitmap = vmx_msr_bitmap_legacy;
 942
 943                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 944         }
 945 }
 946
 947 /*
 948  * reads and returns guest's timestamp counter "register"
 949  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 950  */
 951 static u64 guest_read_tsc(void)
 952 {
 953         u64 host_tsc, tsc_offset;
 954
 955         rdtscll(host_tsc);
 956         tsc_offset = vmcs_read64(TSC_OFFSET);
 957         return host_tsc + tsc_offset;
 958 }
 959
 960 /*
 961  * writes 'guest_tsc' into guest's timestamp counter "register"
 962  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 963  */
 964 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 965 {
 966         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 967 }
 968
 969 /*
 970  * Reads an msr value (of 'msr_index') into 'pdata'.
 971  * Returns 0 on success, non-0 otherwise.
 972  * Assumes vcpu_load() was already called.
 973  */
 974 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 975 {
 976         u64 data;
 977         struct kvm_msr_entry *msr;
 978
 979         if (!pdata) {
 980                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 981                 return -EINVAL;
 982         }
 983
 984         switch (msr_index) {
 985 #ifdef CONFIG_X86_64
 986         case MSR_FS_BASE:
 987                 data = vmcs_readl(GUEST_FS_BASE);
 988                 break;
 989         case MSR_GS_BASE:
 990                 data = vmcs_readl(GUEST_GS_BASE);
 991                 break;
 992         case MSR_EFER:
 993                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 994 #endif
 995         case MSR_IA32_TSC:
 996                 data = guest_read_tsc();
 997                 break;
 998         case MSR_IA32_SYSENTER_CS:
 999                 data = vmcs_read32(GUEST_SYSENTER_CS);
1000                 break;
1001         case MSR_IA32_SYSENTER_EIP:
1002                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1003                 break;
1004         case MSR_IA32_SYSENTER_ESP:
1005                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1006                 break;
1007         default:
1008                 vmx_load_host_state(to_vmx(vcpu));
1009                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1010                 if (msr) {
1011                         data = msr->data;
1012                         break;
1013                 }
1014                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1015         }
1016
1017         *pdata = data;
1018         return 0;
1019 }
1020
1021 /*
1022  * Writes msr value into into the appropriate "register".
1023  * Returns 0 on success, non-0 otherwise.
1024  * Assumes vcpu_load() was already called.
1025  */
1026 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1027 {
1028         struct vcpu_vmx *vmx = to_vmx(vcpu);
1029         struct kvm_msr_entry *msr;
1030         u64 host_tsc;
1031         int ret = 0;
1032
1033         switch (msr_index) {
1034         case MSR_EFER:
1035                 vmx_load_host_state(vmx);
1036                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1037                 break;
1038 #ifdef CONFIG_X86_64
1039         case MSR_FS_BASE:
1040                 vmcs_writel(GUEST_FS_BASE, data);
1041                 break;
1042         case MSR_GS_BASE:
1043                 vmcs_writel(GUEST_GS_BASE, data);
1044                 break;
1045 #endif
1046         case MSR_IA32_SYSENTER_CS:
1047                 vmcs_write32(GUEST_SYSENTER_CS, data);
1048                 break;
1049         case MSR_IA32_SYSENTER_EIP:
1050                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1051                 break;
1052         case MSR_IA32_SYSENTER_ESP:
1053                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1054                 break;
1055         case MSR_IA32_TSC:
1056                 rdtscll(host_tsc);
1057                 guest_write_tsc(data, host_tsc);
1058                 break;
1059         case MSR_IA32_CR_PAT:
1060                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1061                         vmcs_write64(GUEST_IA32_PAT, data);
1062                         vcpu->arch.pat = data;
1063                         break;
1064                 }
1065                 /* Otherwise falls through to kvm_set_msr_common */
1066         default:
1067                 vmx_load_host_state(vmx);
1068                 msr = find_msr_entry(vmx, msr_index);
1069                 if (msr) {
1070                         msr->data = data;
1071                         break;
1072                 }
1073                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1074         }
1075
1076         return ret;
1077 }
1078
1079 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1080 {
1081         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1082         switch (reg) {
1083         case VCPU_REGS_RSP:
1084                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1085                 break;
1086         case VCPU_REGS_RIP:
1087                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1088                 break;
1089         case VCPU_EXREG_PDPTR:
1090                 if (enable_ept)
1091                         ept_save_pdptrs(vcpu);
1092                 break;
1093         default:
1094                 break;
1095         }
1096 }
1097
1098 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1099 {
1100         int old_debug = vcpu->guest_debug;
1101         unsigned long flags;
1102
1103         vcpu->guest_debug = dbg->control;
1104         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1105                 vcpu->guest_debug = 0;
1106
1107         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1108                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1109         else
1110                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1111
1112         flags = vmcs_readl(GUEST_RFLAGS);
1113         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1114                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1115         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1116                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1117         vmcs_writel(GUEST_RFLAGS, flags);
1118
1119         update_exception_bitmap(vcpu);
1120
1121         return 0;
1122 }
1123
1124 static __init int cpu_has_kvm_support(void)
1125 {
1126         return cpu_has_vmx();
1127 }
1128
1129 static __init int vmx_disabled_by_bios(void)
1130 {
1131         u64 msr;
1132
1133         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1134         return (msr & (FEATURE_CONTROL_LOCKED |
1135                        FEATURE_CONTROL_VMXON_ENABLED))
1136             == FEATURE_CONTROL_LOCKED;
1137         /* locked but not enabled */
1138 }
1139
1140 static void hardware_enable(void *garbage)
1141 {
1142         int cpu = raw_smp_processor_id();
1143         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1144         u64 old;
1145
1146         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1147         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1148         if ((old & (FEATURE_CONTROL_LOCKED |
1149                     FEATURE_CONTROL_VMXON_ENABLED))
1150             != (FEATURE_CONTROL_LOCKED |
1151                 FEATURE_CONTROL_VMXON_ENABLED))
1152                 /* enable and lock */
1153                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1154                        FEATURE_CONTROL_LOCKED |
1155                        FEATURE_CONTROL_VMXON_ENABLED);
1156         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1157         asm volatile (ASM_VMX_VMXON_RAX
1158                       : : "a"(&phys_addr), "m"(phys_addr)
1159                       : "memory", "cc");
1160 }
1161
1162 static void vmclear_local_vcpus(void)
1163 {
1164         int cpu = raw_smp_processor_id();
1165         struct vcpu_vmx *vmx, *n;
1166
1167         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1168                                  local_vcpus_link)
1169                 __vcpu_clear(vmx);
1170 }
1171
1172
1173 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1174  * tricks.
1175  */
1176 static void kvm_cpu_vmxoff(void)
1177 {
1178         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1179         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1180 }
1181
1182 static void hardware_disable(void *garbage)
1183 {
1184         vmclear_local_vcpus();
1185         kvm_cpu_vmxoff();
1186 }
1187
1188 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1189                                       u32 msr, u32 *result)
1190 {
1191         u32 vmx_msr_low, vmx_msr_high;
1192         u32 ctl = ctl_min | ctl_opt;
1193
1194         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1195
1196         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1197         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1198
1199         /* Ensure minimum (required) set of control bits are supported. */
1200         if (ctl_min & ~ctl)
1201                 return -EIO;
1202
1203         *result = ctl;
1204         return 0;
1205 }
1206
1207 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1208 {
1209         u32 vmx_msr_low, vmx_msr_high;
1210         u32 min, opt, min2, opt2;
1211         u32 _pin_based_exec_control = 0;
1212         u32 _cpu_based_exec_control = 0;
1213         u32 _cpu_based_2nd_exec_control = 0;
1214         u32 _vmexit_control = 0;
1215         u32 _vmentry_control = 0;
1216
1217         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1218         opt = PIN_BASED_VIRTUAL_NMIS;
1219         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1220                                 &_pin_based_exec_control) < 0)
1221                 return -EIO;
1222
1223         min = CPU_BASED_HLT_EXITING |
1224 #ifdef CONFIG_X86_64
1225               CPU_BASED_CR8_LOAD_EXITING |
1226               CPU_BASED_CR8_STORE_EXITING |
1227 #endif
1228               CPU_BASED_CR3_LOAD_EXITING |
1229               CPU_BASED_CR3_STORE_EXITING |
1230               CPU_BASED_USE_IO_BITMAPS |
1231               CPU_BASED_MOV_DR_EXITING |
1232               CPU_BASED_USE_TSC_OFFSETING |
1233               CPU_BASED_INVLPG_EXITING;
1234         opt = CPU_BASED_TPR_SHADOW |
1235               CPU_BASED_USE_MSR_BITMAPS |
1236               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1237         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1238                                 &_cpu_based_exec_control) < 0)
1239                 return -EIO;
1240 #ifdef CONFIG_X86_64
1241         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1242                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1243                                            ~CPU_BASED_CR8_STORE_EXITING;
1244 #endif
1245         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1246                 min2 = 0;
1247                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1248                         SECONDARY_EXEC_WBINVD_EXITING |
1249                         SECONDARY_EXEC_ENABLE_VPID |
1250                         SECONDARY_EXEC_ENABLE_EPT |
1251                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
1252                 if (adjust_vmx_controls(min2, opt2,
1253                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1254                                         &_cpu_based_2nd_exec_control) < 0)
1255                         return -EIO;
1256         }
1257 #ifndef CONFIG_X86_64
1258         if (!(_cpu_based_2nd_exec_control &
1259                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1260                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1261 #endif
1262         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1263                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1264                    enabled */
1265                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1266                          CPU_BASED_CR3_STORE_EXITING |
1267                          CPU_BASED_INVLPG_EXITING);
1268                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1269                                         &_cpu_based_exec_control) < 0)
1270                         return -EIO;
1271                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1272                       vmx_capability.ept, vmx_capability.vpid);
1273         }
1274
1275         min = 0;
1276 #ifdef CONFIG_X86_64
1277         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1278 #endif
1279         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1280         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1281                                 &_vmexit_control) < 0)
1282                 return -EIO;
1283
1284         min = 0;
1285         opt = VM_ENTRY_LOAD_IA32_PAT;
1286         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1287                                 &_vmentry_control) < 0)
1288                 return -EIO;
1289
1290         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1291
1292         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1293         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1294                 return -EIO;
1295
1296 #ifdef CONFIG_X86_64
1297         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1298         if (vmx_msr_high & (1u<<16))
1299                 return -EIO;
1300 #endif
1301
1302         /* Require Write-Back (WB) memory type for VMCS accesses. */
1303         if (((vmx_msr_high >> 18) & 15) != 6)
1304                 return -EIO;
1305
1306         vmcs_conf->size = vmx_msr_high & 0x1fff;
1307         vmcs_conf->order = get_order(vmcs_config.size);
1308         vmcs_conf->revision_id = vmx_msr_low;
1309
1310         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1311         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1312         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1313         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1314         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1315
1316         return 0;
1317 }
1318
1319 static struct vmcs *alloc_vmcs_cpu(int cpu)
1320 {
1321         int node = cpu_to_node(cpu);
1322         struct page *pages;
1323         struct vmcs *vmcs;
1324
1325         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1326         if (!pages)
1327                 return NULL;
1328         vmcs = page_address(pages);
1329         memset(vmcs, 0, vmcs_config.size);
1330         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1331         return vmcs;
1332 }
1333
1334 static struct vmcs *alloc_vmcs(void)
1335 {
1336         return alloc_vmcs_cpu(raw_smp_processor_id());
1337 }
1338
1339 static void free_vmcs(struct vmcs *vmcs)
1340 {
1341         free_pages((unsigned long)vmcs, vmcs_config.order);
1342 }
1343
1344 static void free_kvm_area(void)
1345 {
1346         int cpu;
1347
1348         for_each_online_cpu(cpu)
1349                 free_vmcs(per_cpu(vmxarea, cpu));
1350 }
1351
1352 static __init int alloc_kvm_area(void)
1353 {
1354         int cpu;
1355
1356         for_each_online_cpu(cpu) {
1357                 struct vmcs *vmcs;
1358
1359                 vmcs = alloc_vmcs_cpu(cpu);
1360                 if (!vmcs) {
1361                         free_kvm_area();
1362                         return -ENOMEM;
1363                 }
1364
1365                 per_cpu(vmxarea, cpu) = vmcs;
1366         }
1367         return 0;
1368 }
1369
1370 static __init int hardware_setup(void)
1371 {
1372         if (setup_vmcs_config(&vmcs_config) < 0)
1373                 return -EIO;
1374
1375         if (boot_cpu_has(X86_FEATURE_NX))
1376                 kvm_enable_efer_bits(EFER_NX);
1377
1378         if (!cpu_has_vmx_vpid())
1379                 enable_vpid = 0;
1380
1381         if (!cpu_has_vmx_ept()) {
1382                 enable_ept = 0;
1383                 enable_unrestricted_guest = 0;
1384         }
1385
1386         if (!cpu_has_vmx_unrestricted_guest())
1387                 enable_unrestricted_guest = 0;
1388
1389         if (!cpu_has_vmx_flexpriority())
1390                 flexpriority_enabled = 0;
1391
1392         if (!cpu_has_vmx_tpr_shadow())
1393                 kvm_x86_ops->update_cr8_intercept = NULL;
1394
1395         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1396                 kvm_disable_largepages();
1397
1398         return alloc_kvm_area();
1399 }
1400
1401 static __exit void hardware_unsetup(void)
1402 {
1403         free_kvm_area();
1404 }
1405
1406 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1407 {
1408         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1409
1410         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1411                 vmcs_write16(sf->selector, save->selector);
1412                 vmcs_writel(sf->base, save->base);
1413                 vmcs_write32(sf->limit, save->limit);
1414                 vmcs_write32(sf->ar_bytes, save->ar);
1415         } else {
1416                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1417                         << AR_DPL_SHIFT;
1418                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1419         }
1420 }
1421
1422 static void enter_pmode(struct kvm_vcpu *vcpu)
1423 {
1424         unsigned long flags;
1425         struct vcpu_vmx *vmx = to_vmx(vcpu);
1426
1427         vmx->emulation_required = 1;
1428         vmx->rmode.vm86_active = 0;
1429
1430         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1431         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1432         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1433
1434         flags = vmcs_readl(GUEST_RFLAGS);
1435         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1436         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1437         vmcs_writel(GUEST_RFLAGS, flags);
1438
1439         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1440                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1441
1442         update_exception_bitmap(vcpu);
1443
1444         if (emulate_invalid_guest_state)
1445                 return;
1446
1447         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1448         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1449         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1450         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1451
1452         vmcs_write16(GUEST_SS_SELECTOR, 0);
1453         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1454
1455         vmcs_write16(GUEST_CS_SELECTOR,
1456                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1457         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1458 }
1459
1460 static gva_t rmode_tss_base(struct kvm *kvm)
1461 {
1462         if (!kvm->arch.tss_addr) {
1463                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1464                                  kvm->memslots[0].npages - 3;
1465                 return base_gfn << PAGE_SHIFT;
1466         }
1467         return kvm->arch.tss_addr;
1468 }
1469
1470 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1471 {
1472         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1473
1474         save->selector = vmcs_read16(sf->selector);
1475         save->base = vmcs_readl(sf->base);
1476         save->limit = vmcs_read32(sf->limit);
1477         save->ar = vmcs_read32(sf->ar_bytes);
1478         vmcs_write16(sf->selector, save->base >> 4);
1479         vmcs_write32(sf->base, save->base & 0xfffff);
1480         vmcs_write32(sf->limit, 0xffff);
1481         vmcs_write32(sf->ar_bytes, 0xf3);
1482 }
1483
1484 static void enter_rmode(struct kvm_vcpu *vcpu)
1485 {
1486         unsigned long flags;
1487         struct vcpu_vmx *vmx = to_vmx(vcpu);
1488
1489         if (enable_unrestricted_guest)
1490                 return;
1491
1492         vmx->emulation_required = 1;
1493         vmx->rmode.vm86_active = 1;
1494
1495         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1496         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1497
1498         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1499         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1500
1501         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1502         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1503
1504         flags = vmcs_readl(GUEST_RFLAGS);
1505         vmx->rmode.save_iopl
1506                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1507
1508         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1509
1510         vmcs_writel(GUEST_RFLAGS, flags);
1511         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1512         update_exception_bitmap(vcpu);
1513
1514         if (emulate_invalid_guest_state)
1515                 goto continue_rmode;
1516
1517         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1518         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1519         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1520
1521         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1522         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1523         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1524                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1525         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1526
1527         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1528         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1529         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1530         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1531
1532 continue_rmode:
1533         kvm_mmu_reset_context(vcpu);
1534         init_rmode(vcpu->kvm);
1535 }
1536
1537 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1538 {
1539         struct vcpu_vmx *vmx = to_vmx(vcpu);
1540         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1541
1542         vcpu->arch.shadow_efer = efer;
1543         if (!msr)
1544                 return;
1545         if (efer & EFER_LMA) {
1546                 vmcs_write32(VM_ENTRY_CONTROLS,
1547                              vmcs_read32(VM_ENTRY_CONTROLS) |
1548                              VM_ENTRY_IA32E_MODE);
1549                 msr->data = efer;
1550         } else {
1551                 vmcs_write32(VM_ENTRY_CONTROLS,
1552                              vmcs_read32(VM_ENTRY_CONTROLS) &
1553                              ~VM_ENTRY_IA32E_MODE);
1554
1555                 msr->data = efer & ~EFER_LME;
1556         }
1557         setup_msrs(vmx);
1558 }
1559
1560 #ifdef CONFIG_X86_64
1561
1562 static void enter_lmode(struct kvm_vcpu *vcpu)
1563 {
1564         u32 guest_tr_ar;
1565
1566         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1567         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1568                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1569                        __func__);
1570                 vmcs_write32(GUEST_TR_AR_BYTES,
1571                              (guest_tr_ar & ~AR_TYPE_MASK)
1572                              | AR_TYPE_BUSY_64_TSS);
1573         }
1574         vcpu->arch.shadow_efer |= EFER_LMA;
1575         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1576 }
1577
1578 static void exit_lmode(struct kvm_vcpu *vcpu)
1579 {
1580         vcpu->arch.shadow_efer &= ~EFER_LMA;
1581
1582         vmcs_write32(VM_ENTRY_CONTROLS,
1583                      vmcs_read32(VM_ENTRY_CONTROLS)
1584                      & ~VM_ENTRY_IA32E_MODE);
1585 }
1586
1587 #endif
1588
1589 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1590 {
1591         vpid_sync_vcpu_all(to_vmx(vcpu));
1592         if (enable_ept)
1593                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1594 }
1595
1596 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1597 {
1598         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1599         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1600 }
1601
1602 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1603 {
1604         if (!test_bit(VCPU_EXREG_PDPTR,
1605                       (unsigned long *)&vcpu->arch.regs_dirty))
1606                 return;
1607
1608         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1609                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1610                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1611                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1612                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1613         }
1614 }
1615
1616 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1617 {
1618         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1619                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1620                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1621                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1622                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1623         }
1624
1625         __set_bit(VCPU_EXREG_PDPTR,
1626                   (unsigned long *)&vcpu->arch.regs_avail);
1627         __set_bit(VCPU_EXREG_PDPTR,
1628                   (unsigned long *)&vcpu->arch.regs_dirty);
1629 }
1630
1631 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1632
1633 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1634                                         unsigned long cr0,
1635                                         struct kvm_vcpu *vcpu)
1636 {
1637         if (!(cr0 & X86_CR0_PG)) {
1638                 /* From paging/starting to nonpaging */
1639                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1640                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1641                              (CPU_BASED_CR3_LOAD_EXITING |
1642                               CPU_BASED_CR3_STORE_EXITING));
1643                 vcpu->arch.cr0 = cr0;
1644                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1645                 *hw_cr0 &= ~X86_CR0_WP;
1646         } else if (!is_paging(vcpu)) {
1647                 /* From nonpaging to paging */
1648                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1649                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1650                              ~(CPU_BASED_CR3_LOAD_EXITING |
1651                                CPU_BASED_CR3_STORE_EXITING));
1652                 vcpu->arch.cr0 = cr0;
1653                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1654                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1655                         *hw_cr0 &= ~X86_CR0_WP;
1656         }
1657 }
1658
1659 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1660                                         struct kvm_vcpu *vcpu)
1661 {
1662         if (!is_paging(vcpu)) {
1663                 *hw_cr4 &= ~X86_CR4_PAE;
1664                 *hw_cr4 |= X86_CR4_PSE;
1665         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1666                 *hw_cr4 &= ~X86_CR4_PAE;
1667 }
1668
1669 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1670 {
1671         struct vcpu_vmx *vmx = to_vmx(vcpu);
1672         unsigned long hw_cr0;
1673
1674         if (enable_unrestricted_guest)
1675                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1676                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1677         else
1678                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1679
1680         vmx_fpu_deactivate(vcpu);
1681
1682         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1683                 enter_pmode(vcpu);
1684
1685         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1686                 enter_rmode(vcpu);
1687
1688 #ifdef CONFIG_X86_64
1689         if (vcpu->arch.shadow_efer & EFER_LME) {
1690                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1691                         enter_lmode(vcpu);
1692                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1693                         exit_lmode(vcpu);
1694         }
1695 #endif
1696
1697         if (enable_ept)
1698                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1699
1700         vmcs_writel(CR0_READ_SHADOW, cr0);
1701         vmcs_writel(GUEST_CR0, hw_cr0);
1702         vcpu->arch.cr0 = cr0;
1703
1704         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1705                 vmx_fpu_activate(vcpu);
1706 }
1707
1708 static u64 construct_eptp(unsigned long root_hpa)
1709 {
1710         u64 eptp;
1711
1712         /* TODO write the value reading from MSR */
1713         eptp = VMX_EPT_DEFAULT_MT |
1714                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1715         eptp |= (root_hpa & PAGE_MASK);
1716
1717         return eptp;
1718 }
1719
1720 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1721 {
1722         unsigned long guest_cr3;
1723         u64 eptp;
1724
1725         guest_cr3 = cr3;
1726         if (enable_ept) {
1727                 eptp = construct_eptp(cr3);
1728                 vmcs_write64(EPT_POINTER, eptp);
1729                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1730                         vcpu->kvm->arch.ept_identity_map_addr;
1731         }
1732
1733         vmx_flush_tlb(vcpu);
1734         vmcs_writel(GUEST_CR3, guest_cr3);
1735         if (vcpu->arch.cr0 & X86_CR0_PE)
1736                 vmx_fpu_deactivate(vcpu);
1737 }
1738
1739 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1740 {
1741         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1742                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1743
1744         vcpu->arch.cr4 = cr4;
1745         if (enable_ept)
1746                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1747
1748         vmcs_writel(CR4_READ_SHADOW, cr4);
1749         vmcs_writel(GUEST_CR4, hw_cr4);
1750 }
1751
1752 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1753 {
1754         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1755
1756         return vmcs_readl(sf->base);
1757 }
1758
1759 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1760                             struct kvm_segment *var, int seg)
1761 {
1762         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1763         u32 ar;
1764
1765         var->base = vmcs_readl(sf->base);
1766         var->limit = vmcs_read32(sf->limit);
1767         var->selector = vmcs_read16(sf->selector);
1768         ar = vmcs_read32(sf->ar_bytes);
1769         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1770                 ar = 0;
1771         var->type = ar & 15;
1772         var->s = (ar >> 4) & 1;
1773         var->dpl = (ar >> 5) & 3;
1774         var->present = (ar >> 7) & 1;
1775         var->avl = (ar >> 12) & 1;
1776         var->l = (ar >> 13) & 1;
1777         var->db = (ar >> 14) & 1;
1778         var->g = (ar >> 15) & 1;
1779         var->unusable = (ar >> 16) & 1;
1780 }
1781
1782 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1783 {
1784         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1785                 return 0;
1786
1787         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1788                 return 3;
1789
1790         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1791 }
1792
1793 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1794 {
1795         u32 ar;
1796
1797         if (var->unusable)
1798                 ar = 1 << 16;
1799         else {
1800                 ar = var->type & 15;
1801                 ar |= (var->s & 1) << 4;
1802                 ar |= (var->dpl & 3) << 5;
1803                 ar |= (var->present & 1) << 7;
1804                 ar |= (var->avl & 1) << 12;
1805                 ar |= (var->l & 1) << 13;
1806                 ar |= (var->db & 1) << 14;
1807                 ar |= (var->g & 1) << 15;
1808         }
1809         if (ar == 0) /* a 0 value means unusable */
1810                 ar = AR_UNUSABLE_MASK;
1811
1812         return ar;
1813 }
1814
1815 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1816                             struct kvm_segment *var, int seg)
1817 {
1818         struct vcpu_vmx *vmx = to_vmx(vcpu);
1819         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1820         u32 ar;
1821
1822         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1823                 vmx->rmode.tr.selector = var->selector;
1824                 vmx->rmode.tr.base = var->base;
1825                 vmx->rmode.tr.limit = var->limit;
1826                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1827                 return;
1828         }
1829         vmcs_writel(sf->base, var->base);
1830         vmcs_write32(sf->limit, var->limit);
1831         vmcs_write16(sf->selector, var->selector);
1832         if (vmx->rmode.vm86_active && var->s) {
1833                 /*
1834                  * Hack real-mode segments into vm86 compatibility.
1835                  */
1836                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1837                         vmcs_writel(sf->base, 0xf0000);
1838                 ar = 0xf3;
1839         } else
1840                 ar = vmx_segment_access_rights(var);
1841
1842         /*
1843          *   Fix the "Accessed" bit in AR field of segment registers for older
1844          * qemu binaries.
1845          *   IA32 arch specifies that at the time of processor reset the
1846          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1847          * is setting it to 0 in the usedland code. This causes invalid guest
1848          * state vmexit when "unrestricted guest" mode is turned on.
1849          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1850          * tree. Newer qemu binaries with that qemu fix would not need this
1851          * kvm hack.
1852          */
1853         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1854                 ar |= 0x1; /* Accessed */
1855
1856         vmcs_write32(sf->ar_bytes, ar);
1857 }
1858
1859 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1860 {
1861         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1862
1863         *db = (ar >> 14) & 1;
1864         *l = (ar >> 13) & 1;
1865 }
1866
1867 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1868 {
1869         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1870         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1871 }
1872
1873 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1874 {
1875         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1876         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1877 }
1878
1879 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1880 {
1881         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1882         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1883 }
1884
1885 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1886 {
1887         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1888         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1889 }
1890
1891 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1892 {
1893         struct kvm_segment var;
1894         u32 ar;
1895
1896         vmx_get_segment(vcpu, &var, seg);
1897         ar = vmx_segment_access_rights(&var);
1898
1899         if (var.base != (var.selector << 4))
1900                 return false;
1901         if (var.limit != 0xffff)
1902                 return false;
1903         if (ar != 0xf3)
1904                 return false;
1905
1906         return true;
1907 }
1908
1909 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1910 {
1911         struct kvm_segment cs;
1912         unsigned int cs_rpl;
1913
1914         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1915         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1916
1917         if (cs.unusable)
1918                 return false;
1919         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1920                 return false;
1921         if (!cs.s)
1922                 return false;
1923         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1924                 if (cs.dpl > cs_rpl)
1925                         return false;
1926         } else {
1927                 if (cs.dpl != cs_rpl)
1928                         return false;
1929         }
1930         if (!cs.present)
1931                 return false;
1932
1933         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1934         return true;
1935 }
1936
1937 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1938 {
1939         struct kvm_segment ss;
1940         unsigned int ss_rpl;
1941
1942         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1943         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1944
1945         if (ss.unusable)
1946                 return true;
1947         if (ss.type != 3 && ss.type != 7)
1948                 return false;
1949         if (!ss.s)
1950                 return false;
1951         if (ss.dpl != ss_rpl) /* DPL != RPL */
1952                 return false;
1953         if (!ss.present)
1954                 return false;
1955
1956         return true;
1957 }
1958
1959 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1960 {
1961         struct kvm_segment var;
1962         unsigned int rpl;
1963
1964         vmx_get_segment(vcpu, &var, seg);
1965         rpl = var.selector & SELECTOR_RPL_MASK;
1966
1967         if (var.unusable)
1968                 return true;
1969         if (!var.s)
1970                 return false;
1971         if (!var.present)
1972                 return false;
1973         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1974                 if (var.dpl < rpl) /* DPL < RPL */
1975                         return false;
1976         }
1977
1978         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1979          * rights flags
1980          */
1981         return true;
1982 }
1983
1984 static bool tr_valid(struct kvm_vcpu *vcpu)
1985 {
1986         struct kvm_segment tr;
1987
1988         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1989
1990         if (tr.unusable)
1991                 return false;
1992         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1993                 return false;
1994         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1995                 return false;
1996         if (!tr.present)
1997                 return false;
1998
1999         return true;
2000 }
2001
2002 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2003 {
2004         struct kvm_segment ldtr;
2005
2006         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2007
2008         if (ldtr.unusable)
2009                 return true;
2010         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2011                 return false;
2012         if (ldtr.type != 2)
2013                 return false;
2014         if (!ldtr.present)
2015                 return false;
2016
2017         return true;
2018 }
2019
2020 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2021 {
2022         struct kvm_segment cs, ss;
2023
2024         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2025         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2026
2027         return ((cs.selector & SELECTOR_RPL_MASK) ==
2028                  (ss.selector & SELECTOR_RPL_MASK));
2029 }
2030
2031 /*
2032  * Check if guest state is valid. Returns true if valid, false if
2033  * not.
2034  * We assume that registers are always usable
2035  */
2036 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2037 {
2038         /* real mode guest state checks */
2039         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2040                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2041                         return false;
2042                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2043                         return false;
2044                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2045                         return false;
2046                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2047                         return false;
2048                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2049                         return false;
2050                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2051                         return false;
2052         } else {
2053         /* protected mode guest state checks */
2054                 if (!cs_ss_rpl_check(vcpu))
2055                         return false;
2056                 if (!code_segment_valid(vcpu))
2057                         return false;
2058                 if (!stack_segment_valid(vcpu))
2059                         return false;
2060                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2061                         return false;
2062                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2063                         return false;
2064                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2065                         return false;
2066                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2067                         return false;
2068                 if (!tr_valid(vcpu))
2069                         return false;
2070                 if (!ldtr_valid(vcpu))
2071                         return false;
2072         }
2073         /* TODO:
2074          * - Add checks on RIP
2075          * - Add checks on RFLAGS
2076          */
2077
2078         return true;
2079 }
2080
2081 static int init_rmode_tss(struct kvm *kvm)
2082 {
2083         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2084         u16 data = 0;
2085         int ret = 0;
2086         int r;
2087
2088         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2089         if (r < 0)
2090                 goto out;
2091         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2092         r = kvm_write_guest_page(kvm, fn++, &data,
2093                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2094         if (r < 0)
2095                 goto out;
2096         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2097         if (r < 0)
2098                 goto out;
2099         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2100         if (r < 0)
2101                 goto out;
2102         data = ~0;
2103         r = kvm_write_guest_page(kvm, fn, &data,
2104                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2105                                  sizeof(u8));
2106         if (r < 0)
2107                 goto out;
2108
2109         ret = 1;
2110 out:
2111         return ret;
2112 }
2113
2114 static int init_rmode_identity_map(struct kvm *kvm)
2115 {
2116         int i, r, ret;
2117         pfn_t identity_map_pfn;
2118         u32 tmp;
2119
2120         if (!enable_ept)
2121                 return 1;
2122         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2123                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2124                         "haven't been allocated!\n");
2125                 return 0;
2126         }
2127         if (likely(kvm->arch.ept_identity_pagetable_done))
2128                 return 1;
2129         ret = 0;
2130         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2131         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2132         if (r < 0)
2133                 goto out;
2134         /* Set up identity-mapping pagetable for EPT in real mode */
2135         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2136                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2137                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2138                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2139                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2140                 if (r < 0)
2141                         goto out;
2142         }
2143         kvm->arch.ept_identity_pagetable_done = true;
2144         ret = 1;
2145 out:
2146         return ret;
2147 }
2148
2149 static void seg_setup(int seg)
2150 {
2151         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2152         unsigned int ar;
2153
2154         vmcs_write16(sf->selector, 0);
2155         vmcs_writel(sf->base, 0);
2156         vmcs_write32(sf->limit, 0xffff);
2157         if (enable_unrestricted_guest) {
2158                 ar = 0x93;
2159                 if (seg == VCPU_SREG_CS)
2160                         ar |= 0x08; /* code segment */
2161         } else
2162                 ar = 0xf3;
2163
2164         vmcs_write32(sf->ar_bytes, ar);
2165 }
2166
2167 static int alloc_apic_access_page(struct kvm *kvm)
2168 {
2169         struct kvm_userspace_memory_region kvm_userspace_mem;
2170         int r = 0;
2171
2172         down_write(&kvm->slots_lock);
2173         if (kvm->arch.apic_access_page)
2174                 goto out;
2175         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2176         kvm_userspace_mem.flags = 0;
2177         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2178         kvm_userspace_mem.memory_size = PAGE_SIZE;
2179         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2180         if (r)
2181                 goto out;
2182
2183         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2184 out:
2185         up_write(&kvm->slots_lock);
2186         return r;
2187 }
2188
2189 static int alloc_identity_pagetable(struct kvm *kvm)
2190 {
2191         struct kvm_userspace_memory_region kvm_userspace_mem;
2192         int r = 0;
2193
2194         down_write(&kvm->slots_lock);
2195         if (kvm->arch.ept_identity_pagetable)
2196                 goto out;
2197         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2198         kvm_userspace_mem.flags = 0;
2199         kvm_userspace_mem.guest_phys_addr =
2200                 kvm->arch.ept_identity_map_addr;
2201         kvm_userspace_mem.memory_size = PAGE_SIZE;
2202         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2203         if (r)
2204                 goto out;
2205
2206         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2207                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2208 out:
2209         up_write(&kvm->slots_lock);
2210         return r;
2211 }
2212
2213 static void allocate_vpid(struct vcpu_vmx *vmx)
2214 {
2215         int vpid;
2216
2217         vmx->vpid = 0;
2218         if (!enable_vpid)
2219                 return;
2220         spin_lock(&vmx_vpid_lock);
2221         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2222         if (vpid < VMX_NR_VPIDS) {
2223                 vmx->vpid = vpid;
2224                 __set_bit(vpid, vmx_vpid_bitmap);
2225         }
2226         spin_unlock(&vmx_vpid_lock);
2227 }
2228
2229 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2230 {
2231         int f = sizeof(unsigned long);
2232
2233         if (!cpu_has_vmx_msr_bitmap())
2234                 return;
2235
2236         /*
2237          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2238          * have the write-low and read-high bitmap offsets the wrong way round.
2239          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2240          */
2241         if (msr <= 0x1fff) {
2242                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2243                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2244         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2245                 msr &= 0x1fff;
2246                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2247                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2248         }
2249 }
2250
2251 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2252 {
2253         if (!longmode_only)
2254                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2255         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2256 }
2257
2258 /*
2259  * Sets up the vmcs for emulated real mode.
2260  */
2261 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2262 {
2263         u32 host_sysenter_cs, msr_low, msr_high;
2264         u32 junk;
2265         u64 host_pat, tsc_this, tsc_base;
2266         unsigned long a;
2267         struct descriptor_table dt;
2268         int i;
2269         unsigned long kvm_vmx_return;
2270         u32 exec_control;
2271
2272         /* I/O */
2273         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2274         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2275
2276         if (cpu_has_vmx_msr_bitmap())
2277                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2278
2279         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2280
2281         /* Control */
2282         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2283                 vmcs_config.pin_based_exec_ctrl);
2284
2285         exec_control = vmcs_config.cpu_based_exec_ctrl;
2286         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2287                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2288 #ifdef CONFIG_X86_64
2289                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2290                                 CPU_BASED_CR8_LOAD_EXITING;
2291 #endif
2292         }
2293         if (!enable_ept)
2294                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2295                                 CPU_BASED_CR3_LOAD_EXITING  |
2296                                 CPU_BASED_INVLPG_EXITING;
2297         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2298
2299         if (cpu_has_secondary_exec_ctrls()) {
2300                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2301                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2302                         exec_control &=
2303                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2304                 if (vmx->vpid == 0)
2305                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2306                 if (!enable_ept)
2307                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2308                 if (!enable_unrestricted_guest)
2309                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2310                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2311         }
2312
2313         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2314         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2315         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2316
2317         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2318         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2319         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2320
2321         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2322         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2323         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2324         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2325         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2326         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2327 #ifdef CONFIG_X86_64
2328         rdmsrl(MSR_FS_BASE, a);
2329         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2330         rdmsrl(MSR_GS_BASE, a);
2331         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2332 #else
2333         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2334         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2335 #endif
2336
2337         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2338
2339         kvm_get_idt(&dt);
2340         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2341
2342         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2343         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2344         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2345         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2346         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2347
2348         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2349         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2350         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2351         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2352         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2353         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2354
2355         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2356                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2357                 host_pat = msr_low | ((u64) msr_high << 32);
2358                 vmcs_write64(HOST_IA32_PAT, host_pat);
2359         }
2360         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2361                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2362                 host_pat = msr_low | ((u64) msr_high << 32);
2363                 /* Write the default value follow host pat */
2364                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2365                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2366                 vmx->vcpu.arch.pat = host_pat;
2367         }
2368
2369         for (i = 0; i < NR_VMX_MSR; ++i) {
2370                 u32 index = vmx_msr_index[i];
2371                 u32 data_low, data_high;
2372                 u64 data;
2373                 int j = vmx->nmsrs;
2374
2375                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2376                         continue;
2377                 if (wrmsr_safe(index, data_low, data_high) < 0)
2378                         continue;
2379                 data = data_low | ((u64)data_high << 32);
2380                 vmx->host_msrs[j].index = index;
2381                 vmx->host_msrs[j].reserved = 0;
2382                 vmx->host_msrs[j].data = data;
2383                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2384                 ++vmx->nmsrs;
2385         }
2386
2387         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2388
2389         /* 22.2.1, 20.8.1 */
2390         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2391
2392         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2393         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2394
2395         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2396         rdtscll(tsc_this);
2397         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2398                 tsc_base = tsc_this;
2399
2400         guest_write_tsc(0, tsc_base);
2401
2402         return 0;
2403 }
2404
2405 static int init_rmode(struct kvm *kvm)
2406 {
2407         if (!init_rmode_tss(kvm))
2408                 return 0;
2409         if (!init_rmode_identity_map(kvm))
2410                 return 0;
2411         return 1;
2412 }
2413
2414 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2415 {
2416         struct vcpu_vmx *vmx = to_vmx(vcpu);
2417         u64 msr;
2418         int ret;
2419
2420         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2421         down_read(&vcpu->kvm->slots_lock);
2422         if (!init_rmode(vmx->vcpu.kvm)) {
2423                 ret = -ENOMEM;
2424                 goto out;
2425         }
2426
2427         vmx->rmode.vm86_active = 0;
2428
2429         vmx->soft_vnmi_blocked = 0;
2430
2431         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2432         kvm_set_cr8(&vmx->vcpu, 0);
2433         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2434         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2435                 msr |= MSR_IA32_APICBASE_BSP;
2436         kvm_set_apic_base(&vmx->vcpu, msr);
2437
2438         fx_init(&vmx->vcpu);
2439
2440         seg_setup(VCPU_SREG_CS);
2441         /*
2442          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2443          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2444          */
2445         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2446                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2447                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2448         } else {
2449                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2450                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2451         }
2452
2453         seg_setup(VCPU_SREG_DS);
2454         seg_setup(VCPU_SREG_ES);
2455         seg_setup(VCPU_SREG_FS);
2456         seg_setup(VCPU_SREG_GS);
2457         seg_setup(VCPU_SREG_SS);
2458
2459         vmcs_write16(GUEST_TR_SELECTOR, 0);
2460         vmcs_writel(GUEST_TR_BASE, 0);
2461         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2462         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2463
2464         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2465         vmcs_writel(GUEST_LDTR_BASE, 0);
2466         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2467         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2468
2469         vmcs_write32(GUEST_SYSENTER_CS, 0);
2470         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2471         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2472
2473         vmcs_writel(GUEST_RFLAGS, 0x02);
2474         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2475                 kvm_rip_write(vcpu, 0xfff0);
2476         else
2477                 kvm_rip_write(vcpu, 0);
2478         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2479
2480         vmcs_writel(GUEST_DR7, 0x400);
2481
2482         vmcs_writel(GUEST_GDTR_BASE, 0);
2483         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2484
2485         vmcs_writel(GUEST_IDTR_BASE, 0);
2486         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2487
2488         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2489         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2490         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2491
2492         /* Special registers */
2493         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2494
2495         setup_msrs(vmx);
2496
2497         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2498
2499         if (cpu_has_vmx_tpr_shadow()) {
2500                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2501                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2502                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2503                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2504                 vmcs_write32(TPR_THRESHOLD, 0);
2505         }
2506
2507         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2508                 vmcs_write64(APIC_ACCESS_ADDR,
2509                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2510
2511         if (vmx->vpid != 0)
2512                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2513
2514         vmx->vcpu.arch.cr0 = 0x60000010;
2515         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2516         vmx_set_cr4(&vmx->vcpu, 0);
2517         vmx_set_efer(&vmx->vcpu, 0);
2518         vmx_fpu_activate(&vmx->vcpu);
2519         update_exception_bitmap(&vmx->vcpu);
2520
2521         vpid_sync_vcpu_all(vmx);
2522
2523         ret = 0;
2524
2525         /* HACK: Don't enable emulation on guest boot/reset */
2526         vmx->emulation_required = 0;
2527
2528 out:
2529         up_read(&vcpu->kvm->slots_lock);
2530         return ret;
2531 }
2532
2533 static void enable_irq_window(struct kvm_vcpu *vcpu)
2534 {
2535         u32 cpu_based_vm_exec_control;
2536
2537         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2538         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2539         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2540 }
2541
2542 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2543 {
2544         u32 cpu_based_vm_exec_control;
2545
2546         if (!cpu_has_virtual_nmis()) {
2547                 enable_irq_window(vcpu);
2548                 return;
2549         }
2550
2551         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2552         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2553         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2554 }
2555
2556 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2557 {
2558         struct vcpu_vmx *vmx = to_vmx(vcpu);
2559         uint32_t intr;
2560         int irq = vcpu->arch.interrupt.nr;
2561
2562         trace_kvm_inj_virq(irq);
2563
2564         ++vcpu->stat.irq_injections;
2565         if (vmx->rmode.vm86_active) {
2566                 vmx->rmode.irq.pending = true;
2567                 vmx->rmode.irq.vector = irq;
2568                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2569                 if (vcpu->arch.interrupt.soft)
2570                         vmx->rmode.irq.rip +=
2571                                 vmx->vcpu.arch.event_exit_inst_len;
2572                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2573                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2574                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2575                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2576                 return;
2577         }
2578         intr = irq | INTR_INFO_VALID_MASK;
2579         if (vcpu->arch.interrupt.soft) {
2580                 intr |= INTR_TYPE_SOFT_INTR;
2581                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2582                              vmx->vcpu.arch.event_exit_inst_len);
2583         } else
2584                 intr |= INTR_TYPE_EXT_INTR;
2585         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2586 }
2587
2588 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2589 {
2590         struct vcpu_vmx *vmx = to_vmx(vcpu);
2591
2592         if (!cpu_has_virtual_nmis()) {
2593                 /*
2594                  * Tracking the NMI-blocked state in software is built upon
2595                  * finding the next open IRQ window. This, in turn, depends on
2596                  * well-behaving guests: They have to keep IRQs disabled at
2597                  * least as long as the NMI handler runs. Otherwise we may
2598                  * cause NMI nesting, maybe breaking the guest. But as this is
2599                  * highly unlikely, we can live with the residual risk.
2600                  */
2601                 vmx->soft_vnmi_blocked = 1;
2602                 vmx->vnmi_blocked_time = 0;
2603         }
2604
2605         ++vcpu->stat.nmi_injections;
2606         if (vmx->rmode.vm86_active) {
2607                 vmx->rmode.irq.pending = true;
2608                 vmx->rmode.irq.vector = NMI_VECTOR;
2609                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2610                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2611                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2612                              INTR_INFO_VALID_MASK);
2613                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2614                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2615                 return;
2616         }
2617         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2618                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2619 }
2620
2621 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2622 {
2623         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2624                 return 0;
2625
2626         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2627                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2628                                 GUEST_INTR_STATE_NMI));
2629 }
2630
2631 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2632 {
2633         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2634                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2635                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2636 }
2637
2638 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2639 {
2640         int ret;
2641         struct kvm_userspace_memory_region tss_mem = {
2642                 .slot = TSS_PRIVATE_MEMSLOT,
2643                 .guest_phys_addr = addr,
2644                 .memory_size = PAGE_SIZE * 3,
2645                 .flags = 0,
2646         };
2647
2648         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2649         if (ret)
2650                 return ret;
2651         kvm->arch.tss_addr = addr;
2652         return 0;
2653 }
2654
2655 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2656                                   int vec, u32 err_code)
2657 {
2658         /*
2659          * Instruction with address size override prefix opcode 0x67
2660          * Cause the #SS fault with 0 error code in VM86 mode.
2661          */
2662         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2663                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2664                         return 1;
2665         /*
2666          * Forward all other exceptions that are valid in real mode.
2667          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2668          *        the required debugging infrastructure rework.
2669          */
2670         switch (vec) {
2671         case DB_VECTOR:
2672                 if (vcpu->guest_debug &
2673                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2674                         return 0;
2675                 kvm_queue_exception(vcpu, vec);
2676                 return 1;
2677         case BP_VECTOR:
2678                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2679                         return 0;
2680                 /* fall through */
2681         case DE_VECTOR:
2682         case OF_VECTOR:
2683         case BR_VECTOR:
2684         case UD_VECTOR:
2685         case DF_VECTOR:
2686         case SS_VECTOR:
2687         case GP_VECTOR:
2688         case MF_VECTOR:
2689                 kvm_queue_exception(vcpu, vec);
2690                 return 1;
2691         }
2692         return 0;
2693 }
2694
2695 /*
2696  * Trigger machine check on the host. We assume all the MSRs are already set up
2697  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2698  * We pass a fake environment to the machine check handler because we want
2699  * the guest to be always treated like user space, no matter what context
2700  * it used internally.
2701  */
2702 static void kvm_machine_check(void)
2703 {
2704 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2705         struct pt_regs regs = {
2706                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2707                 .flags = X86_EFLAGS_IF,
2708         };
2709
2710         do_machine_check(&regs, 0);
2711 #endif
2712 }
2713
2714 static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2715 {
2716         /* already handled by vcpu_run */
2717         return 1;
2718 }
2719
2720 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2721 {
2722         struct vcpu_vmx *vmx = to_vmx(vcpu);
2723         u32 intr_info, ex_no, error_code;
2724         unsigned long cr2, rip, dr6;
2725         u32 vect_info;
2726         enum emulation_result er;
2727
2728         vect_info = vmx->idt_vectoring_info;
2729         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2730
2731         if (is_machine_check(intr_info))
2732                 return handle_machine_check(vcpu, kvm_run);
2733
2734         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2735                                                 !is_page_fault(intr_info))
2736                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2737                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2738
2739         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2740                 return 1;  /* already handled by vmx_vcpu_run() */
2741
2742         if (is_no_device(intr_info)) {
2743                 vmx_fpu_activate(vcpu);
2744                 return 1;
2745         }
2746
2747         if (is_invalid_opcode(intr_info)) {
2748                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2749                 if (er != EMULATE_DONE)
2750                         kvm_queue_exception(vcpu, UD_VECTOR);
2751                 return 1;
2752         }
2753
2754         error_code = 0;
2755         rip = kvm_rip_read(vcpu);
2756         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2757                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2758         if (is_page_fault(intr_info)) {
2759                 /* EPT won't cause page fault directly */
2760                 if (enable_ept)
2761                         BUG();
2762                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2763                 trace_kvm_page_fault(cr2, error_code);
2764
2765                 if (kvm_event_needs_reinjection(vcpu))
2766                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2767                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2768         }
2769
2770         if (vmx->rmode.vm86_active &&
2771             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2772                                                                 error_code)) {
2773                 if (vcpu->arch.halt_request) {
2774                         vcpu->arch.halt_request = 0;
2775                         return kvm_emulate_halt(vcpu);
2776                 }
2777                 return 1;
2778         }
2779
2780         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2781         switch (ex_no) {
2782         case DB_VECTOR:
2783                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2784                 if (!(vcpu->guest_debug &
2785                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2786                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2787                         kvm_queue_exception(vcpu, DB_VECTOR);
2788                         return 1;
2789                 }
2790                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2791                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2792                 /* fall through */
2793         case BP_VECTOR:
2794                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2795                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2796                 kvm_run->debug.arch.exception = ex_no;
2797                 break;
2798         default:
2799                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2800                 kvm_run->ex.exception = ex_no;
2801                 kvm_run->ex.error_code = error_code;
2802                 break;
2803         }
2804         return 0;
2805 }
2806
2807 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2808                                      struct kvm_run *kvm_run)
2809 {
2810         ++vcpu->stat.irq_exits;
2811         return 1;
2812 }
2813
2814 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2815 {
2816         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2817         return 0;
2818 }
2819
2820 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2821 {
2822         unsigned long exit_qualification;
2823         int size, in, string;
2824         unsigned port;
2825
2826         ++vcpu->stat.io_exits;
2827         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2828         string = (exit_qualification & 16) != 0;
2829
2830         if (string) {
2831                 if (emulate_instruction(vcpu,
2832                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2833                         return 0;
2834                 return 1;
2835         }
2836
2837         size = (exit_qualification & 7) + 1;
2838         in = (exit_qualification & 8) != 0;
2839         port = exit_qualification >> 16;
2840
2841         skip_emulated_instruction(vcpu);
2842         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2843 }
2844
2845 static void
2846 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2847 {
2848         /*
2849          * Patch in the VMCALL instruction:
2850          */
2851         hypercall[0] = 0x0f;
2852         hypercall[1] = 0x01;
2853         hypercall[2] = 0xc1;
2854 }
2855
2856 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2857 {
2858         unsigned long exit_qualification, val;
2859         int cr;
2860         int reg;
2861
2862         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2863         cr = exit_qualification & 15;
2864         reg = (exit_qualification >> 8) & 15;
2865         switch ((exit_qualification >> 4) & 3) {
2866         case 0: /* mov to cr */
2867                 val = kvm_register_read(vcpu, reg);
2868                 trace_kvm_cr_write(cr, val);
2869                 switch (cr) {
2870                 case 0:
2871                         kvm_set_cr0(vcpu, val);
2872                         skip_emulated_instruction(vcpu);
2873                         return 1;
2874                 case 3:
2875                         kvm_set_cr3(vcpu, val);
2876                         skip_emulated_instruction(vcpu);
2877                         return 1;
2878                 case 4:
2879                         kvm_set_cr4(vcpu, val);
2880                         skip_emulated_instruction(vcpu);
2881                         return 1;
2882                 case 8: {
2883                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2884                                 u8 cr8 = kvm_register_read(vcpu, reg);
2885                                 kvm_set_cr8(vcpu, cr8);
2886                                 skip_emulated_instruction(vcpu);
2887                                 if (irqchip_in_kernel(vcpu->kvm))
2888                                         return 1;
2889                                 if (cr8_prev <= cr8)
2890                                         return 1;
2891                                 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2892                                 return 0;
2893                         }
2894                 };
2895                 break;
2896         case 2: /* clts */
2897                 vmx_fpu_deactivate(vcpu);
2898                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2899                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2900                 vmx_fpu_activate(vcpu);
2901                 skip_emulated_instruction(vcpu);
2902                 return 1;
2903         case 1: /*mov from cr*/
2904                 switch (cr) {
2905                 case 3:
2906                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2907                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
2908                         skip_emulated_instruction(vcpu);
2909                         return 1;
2910                 case 8:
2911                         val = kvm_get_cr8(vcpu);
2912                         kvm_register_write(vcpu, reg, val);
2913                         trace_kvm_cr_read(cr, val);
2914                         skip_emulated_instruction(vcpu);
2915                         return 1;
2916                 }
2917                 break;
2918         case 3: /* lmsw */
2919                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2920
2921                 skip_emulated_instruction(vcpu);
2922                 return 1;
2923         default:
2924                 break;
2925         }
2926         kvm_run->exit_reason = 0;
2927         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2928                (int)(exit_qualification >> 4) & 3, cr);
2929         return 0;
2930 }
2931
2932 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2933 {
2934         unsigned long exit_qualification;
2935         unsigned long val;
2936         int dr, reg;
2937
2938         dr = vmcs_readl(GUEST_DR7);
2939         if (dr & DR7_GD) {
2940                 /*
2941                  * As the vm-exit takes precedence over the debug trap, we
2942                  * need to emulate the latter, either for the host or the
2943                  * guest debugging itself.
2944                  */
2945                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2946                         kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2947                         kvm_run->debug.arch.dr7 = dr;
2948                         kvm_run->debug.arch.pc =
2949                                 vmcs_readl(GUEST_CS_BASE) +
2950                                 vmcs_readl(GUEST_RIP);
2951                         kvm_run->debug.arch.exception = DB_VECTOR;
2952                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2953                         return 0;
2954                 } else {
2955                         vcpu->arch.dr7 &= ~DR7_GD;
2956                         vcpu->arch.dr6 |= DR6_BD;
2957                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2958                         kvm_queue_exception(vcpu, DB_VECTOR);
2959                         return 1;
2960                 }
2961         }
2962
2963         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2964         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2965         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2966         if (exit_qualification & TYPE_MOV_FROM_DR) {
2967                 switch (dr) {
2968                 case 0 ... 3:
2969                         val = vcpu->arch.db[dr];
2970                         break;
2971                 case 6:
2972                         val = vcpu->arch.dr6;
2973                         break;
2974                 case 7:
2975                         val = vcpu->arch.dr7;
2976                         break;
2977                 default:
2978                         val = 0;
2979                 }
2980                 kvm_register_write(vcpu, reg, val);
2981         } else {
2982                 val = vcpu->arch.regs[reg];
2983                 switch (dr) {
2984                 case 0 ... 3:
2985                         vcpu->arch.db[dr] = val;
2986                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2987                                 vcpu->arch.eff_db[dr] = val;
2988                         break;
2989                 case 4 ... 5:
2990                         if (vcpu->arch.cr4 & X86_CR4_DE)
2991                                 kvm_queue_exception(vcpu, UD_VECTOR);
2992                         break;
2993                 case 6:
2994                         if (val & 0xffffffff00000000ULL) {
2995                                 kvm_queue_exception(vcpu, GP_VECTOR);
2996                                 break;
2997                         }
2998                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2999                         break;
3000                 case 7:
3001                         if (val & 0xffffffff00000000ULL) {
3002                                 kvm_queue_exception(vcpu, GP_VECTOR);
3003                                 break;
3004                         }
3005                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3006                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3007                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3008                                 vcpu->arch.switch_db_regs =
3009                                         (val & DR7_BP_EN_MASK);
3010                         }
3011                         break;
3012                 }
3013         }
3014         skip_emulated_instruction(vcpu);
3015         return 1;
3016 }
3017
3018 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3019 {
3020         kvm_emulate_cpuid(vcpu);
3021         return 1;
3022 }
3023
3024 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3025 {
3026         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3027         u64 data;
3028
3029         if (vmx_get_msr(vcpu, ecx, &data)) {
3030                 kvm_inject_gp(vcpu, 0);
3031                 return 1;
3032         }
3033
3034         trace_kvm_msr_read(ecx, data);
3035
3036         /* FIXME: handling of bits 32:63 of rax, rdx */
3037         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3038         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3039         skip_emulated_instruction(vcpu);
3040         return 1;
3041 }
3042
3043 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3044 {
3045         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3046         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3047                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3048
3049         trace_kvm_msr_write(ecx, data);
3050
3051         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3052                 kvm_inject_gp(vcpu, 0);
3053                 return 1;
3054         }
3055
3056         skip_emulated_instruction(vcpu);
3057         return 1;
3058 }
3059
3060 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
3061                                       struct kvm_run *kvm_run)
3062 {
3063         return 1;
3064 }
3065
3066 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
3067                                    struct kvm_run *kvm_run)
3068 {
3069         u32 cpu_based_vm_exec_control;
3070
3071         /* clear pending irq */
3072         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3073         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3074         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3075
3076         ++vcpu->stat.irq_window_exits;
3077
3078         /*
3079          * If the user space waits to inject interrupts, exit as soon as
3080          * possible
3081          */
3082         if (!irqchip_in_kernel(vcpu->kvm) &&
3083             kvm_run->request_interrupt_window &&
3084             !kvm_cpu_has_interrupt(vcpu)) {
3085                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3086                 return 0;
3087         }
3088         return 1;
3089 }
3090
3091 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3092 {
3093         skip_emulated_instruction(vcpu);
3094         return kvm_emulate_halt(vcpu);
3095 }
3096
3097 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3098 {
3099         skip_emulated_instruction(vcpu);
3100         kvm_emulate_hypercall(vcpu);
3101         return 1;
3102 }
3103
3104 static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3105 {
3106         kvm_queue_exception(vcpu, UD_VECTOR);
3107         return 1;
3108 }
3109
3110 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3111 {
3112         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3113
3114         kvm_mmu_invlpg(vcpu, exit_qualification);
3115         skip_emulated_instruction(vcpu);
3116         return 1;
3117 }
3118
3119 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3120 {
3121         skip_emulated_instruction(vcpu);
3122         /* TODO: Add support for VT-d/pass-through device */
3123         return 1;
3124 }
3125
3126 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3127 {
3128         unsigned long exit_qualification;
3129         enum emulation_result er;
3130         unsigned long offset;
3131
3132         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3133         offset = exit_qualification & 0xffful;
3134
3135         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3136
3137         if (er !=  EMULATE_DONE) {
3138                 printk(KERN_ERR
3139                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3140                        offset);
3141                 return -ENOEXEC;
3142         }
3143         return 1;
3144 }
3145
3146 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3147 {
3148         struct vcpu_vmx *vmx = to_vmx(vcpu);
3149         unsigned long exit_qualification;
3150         u16 tss_selector;
3151         int reason, type, idt_v;
3152
3153         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3154         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3155
3156         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3157
3158         reason = (u32)exit_qualification >> 30;
3159         if (reason == TASK_SWITCH_GATE && idt_v) {
3160                 switch (type) {
3161                 case INTR_TYPE_NMI_INTR:
3162                         vcpu->arch.nmi_injected = false;
3163                         if (cpu_has_virtual_nmis())
3164                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3165                                               GUEST_INTR_STATE_NMI);
3166                         break;
3167                 case INTR_TYPE_EXT_INTR:
3168                 case INTR_TYPE_SOFT_INTR:
3169                         kvm_clear_interrupt_queue(vcpu);
3170                         break;
3171                 case INTR_TYPE_HARD_EXCEPTION:
3172                 case INTR_TYPE_SOFT_EXCEPTION:
3173                         kvm_clear_exception_queue(vcpu);
3174                         break;
3175                 default:
3176                         break;
3177                 }
3178         }
3179         tss_selector = exit_qualification;
3180
3181         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3182                        type != INTR_TYPE_EXT_INTR &&
3183                        type != INTR_TYPE_NMI_INTR))
3184                 skip_emulated_instruction(vcpu);
3185
3186         if (!kvm_task_switch(vcpu, tss_selector, reason))
3187                 return 0;
3188
3189         /* clear all local breakpoint enable flags */
3190         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3191
3192         /*
3193          * TODO: What about debug traps on tss switch?
3194          *       Are we supposed to inject them and update dr6?
3195          */
3196
3197         return 1;
3198 }
3199
3200 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3201 {
3202         unsigned long exit_qualification;
3203         gpa_t gpa;
3204         int gla_validity;
3205
3206         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3207
3208         if (exit_qualification & (1 << 6)) {
3209                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3210                 return -EINVAL;
3211         }
3212
3213         gla_validity = (exit_qualification >> 7) & 0x3;
3214         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3215                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3216                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3217                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3218                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3219                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3220                         (long unsigned int)exit_qualification);
3221                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3222                 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3223                 return 0;
3224         }
3225
3226         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3227         trace_kvm_page_fault(gpa, exit_qualification);
3228         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3229 }
3230
3231 static u64 ept_rsvd_mask(u64 spte, int level)
3232 {
3233         int i;
3234         u64 mask = 0;
3235
3236         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3237                 mask |= (1ULL << i);
3238
3239         if (level > 2)
3240                 /* bits 7:3 reserved */
3241                 mask |= 0xf8;
3242         else if (level == 2) {
3243                 if (spte & (1ULL << 7))
3244                         /* 2MB ref, bits 20:12 reserved */
3245                         mask |= 0x1ff000;
3246                 else
3247                         /* bits 6:3 reserved */
3248                         mask |= 0x78;
3249         }
3250
3251         return mask;
3252 }
3253
3254 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3255                                        int level)
3256 {
3257         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3258
3259         /* 010b (write-only) */
3260         WARN_ON((spte & 0x7) == 0x2);
3261
3262         /* 110b (write/execute) */
3263         WARN_ON((spte & 0x7) == 0x6);
3264
3265         /* 100b (execute-only) and value not supported by logical processor */
3266         if (!cpu_has_vmx_ept_execute_only())
3267                 WARN_ON((spte & 0x7) == 0x4);
3268
3269         /* not 000b */
3270         if ((spte & 0x7)) {
3271                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3272
3273                 if (rsvd_bits != 0) {
3274                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3275                                          __func__, rsvd_bits);
3276                         WARN_ON(1);
3277                 }
3278
3279                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3280                         u64 ept_mem_type = (spte & 0x38) >> 3;
3281
3282                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3283                             ept_mem_type == 7) {
3284                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3285                                                 __func__, ept_mem_type);
3286                                 WARN_ON(1);
3287                         }
3288                 }
3289         }
3290 }
3291
3292 static int handle_ept_misconfig(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3293 {
3294         u64 sptes[4];
3295         int nr_sptes, i;
3296         gpa_t gpa;
3297
3298         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3299
3300         printk(KERN_ERR "EPT: Misconfiguration.\n");
3301         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3302
3303         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3304
3305         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3306                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3307
3308         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3309         kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3310
3311         return 0;
3312 }
3313
3314 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3315 {
3316         u32 cpu_based_vm_exec_control;
3317
3318         /* clear pending NMI */
3319         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3320         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3321         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3322         ++vcpu->stat.nmi_window_exits;
3323
3324         return 1;
3325 }
3326
3327 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3328                                 struct kvm_run *kvm_run)
3329 {
3330         struct vcpu_vmx *vmx = to_vmx(vcpu);
3331         enum emulation_result err = EMULATE_DONE;
3332
3333         local_irq_enable();
3334         preempt_enable();
3335
3336         while (!guest_state_valid(vcpu)) {
3337                 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3338
3339                 if (err == EMULATE_DO_MMIO)
3340                         break;
3341
3342                 if (err != EMULATE_DONE) {
3343                         kvm_report_emulation_failure(vcpu, "emulation failure");
3344                         break;
3345                 }
3346
3347                 if (signal_pending(current))
3348                         break;
3349                 if (need_resched())
3350                         schedule();
3351         }
3352
3353         preempt_disable();
3354         local_irq_disable();
3355
3356         vmx->invalid_state_emulation_result = err;
3357 }
3358
3359 /*
3360  * The exit handlers return 1 if the exit was handled fully and guest execution
3361  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3362  * to be done to userspace and return 0.
3363  */
3364 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3365                                       struct kvm_run *kvm_run) = {
3366         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3367         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3368         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3369         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3370         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3371         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3372         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3373         [EXIT_REASON_CPUID]                   = handle_cpuid,
3374         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3375         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3376         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3377         [EXIT_REASON_HLT]                     = handle_halt,
3378         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3379         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3380         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3381         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3382         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3383         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3384         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3385         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3386         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3387         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3388         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3389         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3390         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3391         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3392         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3393         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3394         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3395         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3396 };
3397
3398 static const int kvm_vmx_max_exit_handlers =
3399         ARRAY_SIZE(kvm_vmx_exit_handlers);
3400
3401 /*
3402  * The guest has exited.  See if we can fix it or if we need userspace
3403  * assistance.
3404  */
3405 static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3406 {
3407         struct vcpu_vmx *vmx = to_vmx(vcpu);
3408         u32 exit_reason = vmx->exit_reason;
3409         u32 vectoring_info = vmx->idt_vectoring_info;
3410
3411         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3412
3413         /* If we need to emulate an MMIO from handle_invalid_guest_state
3414          * we just return 0 */
3415         if (vmx->emulation_required && emulate_invalid_guest_state) {
3416                 if (guest_state_valid(vcpu))
3417                         vmx->emulation_required = 0;
3418                 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3419         }
3420
3421         /* Access CR3 don't cause VMExit in paging mode, so we need
3422          * to sync with guest real CR3. */
3423         if (enable_ept && is_paging(vcpu))
3424                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3425
3426         if (unlikely(vmx->fail)) {
3427                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3428                 kvm_run->fail_entry.hardware_entry_failure_reason
3429                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3430                 return 0;
3431         }
3432
3433         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3434                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3435                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3436                         exit_reason != EXIT_REASON_TASK_SWITCH))
3437                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3438                        "(0x%x) and exit reason is 0x%x\n",
3439                        __func__, vectoring_info, exit_reason);
3440
3441         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3442                 if (vmx_interrupt_allowed(vcpu)) {
3443                         vmx->soft_vnmi_blocked = 0;
3444                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3445                            vcpu->arch.nmi_pending) {
3446                         /*
3447                          * This CPU don't support us in finding the end of an
3448                          * NMI-blocked window if the guest runs with IRQs
3449                          * disabled. So we pull the trigger after 1 s of
3450                          * futile waiting, but inform the user about this.
3451                          */
3452                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3453                                "state on VCPU %d after 1 s timeout\n",
3454                                __func__, vcpu->vcpu_id);
3455                         vmx->soft_vnmi_blocked = 0;
3456                 }
3457         }
3458
3459         if (exit_reason < kvm_vmx_max_exit_handlers
3460             && kvm_vmx_exit_handlers[exit_reason])
3461                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3462         else {
3463                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3464                 kvm_run->hw.hardware_exit_reason = exit_reason;
3465         }
3466         return 0;
3467 }
3468
3469 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3470 {
3471         if (irr == -1 || tpr < irr) {
3472                 vmcs_write32(TPR_THRESHOLD, 0);
3473                 return;
3474         }
3475
3476         vmcs_write32(TPR_THRESHOLD, irr);
3477 }
3478
3479 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3480 {
3481         u32 exit_intr_info;
3482         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3483         bool unblock_nmi;
3484         u8 vector;
3485         int type;
3486         bool idtv_info_valid;
3487
3488         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3489
3490         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3491
3492         /* Handle machine checks before interrupts are enabled */
3493         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3494             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3495                 && is_machine_check(exit_intr_info)))
3496                 kvm_machine_check();
3497
3498         /* We need to handle NMIs before interrupts are enabled */
3499         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3500             (exit_intr_info & INTR_INFO_VALID_MASK))
3501                 asm("int $2");
3502
3503         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3504
3505         if (cpu_has_virtual_nmis()) {
3506                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3507                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3508                 /*
3509                  * SDM 3: 27.7.1.2 (September 2008)
3510                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3511                  * a guest IRET fault.
3512                  * SDM 3: 23.2.2 (September 2008)
3513                  * Bit 12 is undefined in any of the following cases:
3514                  *  If the VM exit sets the valid bit in the IDT-vectoring
3515                  *   information field.
3516                  *  If the VM exit is due to a double fault.
3517                  */
3518                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3519                     vector != DF_VECTOR && !idtv_info_valid)
3520                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3521                                       GUEST_INTR_STATE_NMI);
3522         } else if (unlikely(vmx->soft_vnmi_blocked))
3523                 vmx->vnmi_blocked_time +=
3524                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3525
3526         vmx->vcpu.arch.nmi_injected = false;
3527         kvm_clear_exception_queue(&vmx->vcpu);
3528         kvm_clear_interrupt_queue(&vmx->vcpu);
3529
3530         if (!idtv_info_valid)
3531                 return;
3532
3533         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3534         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3535
3536         switch (type) {
3537         case INTR_TYPE_NMI_INTR:
3538                 vmx->vcpu.arch.nmi_injected = true;
3539                 /*
3540                  * SDM 3: 27.7.1.2 (September 2008)
3541                  * Clear bit "block by NMI" before VM entry if a NMI
3542                  * delivery faulted.
3543                  */
3544                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3545                                 GUEST_INTR_STATE_NMI);
3546                 break;
3547         case INTR_TYPE_SOFT_EXCEPTION:
3548                 vmx->vcpu.arch.event_exit_inst_len =
3549                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3550                 /* fall through */
3551         case INTR_TYPE_HARD_EXCEPTION:
3552                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3553                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3554                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3555                 } else
3556                         kvm_queue_exception(&vmx->vcpu, vector);
3557                 break;
3558         case INTR_TYPE_SOFT_INTR:
3559                 vmx->vcpu.arch.event_exit_inst_len =
3560                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3561                 /* fall through */
3562         case INTR_TYPE_EXT_INTR:
3563                 kvm_queue_interrupt(&vmx->vcpu, vector,
3564                         type == INTR_TYPE_SOFT_INTR);
3565                 break;
3566         default:
3567                 break;
3568         }
3569 }
3570
3571 /*
3572  * Failure to inject an interrupt should give us the information
3573  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3574  * when fetching the interrupt redirection bitmap in the real-mode
3575  * tss, this doesn't happen.  So we do it ourselves.
3576  */
3577 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3578 {
3579         vmx->rmode.irq.pending = 0;
3580         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3581                 return;
3582         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3583         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3584                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3585                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3586                 return;
3587         }
3588         vmx->idt_vectoring_info =
3589                 VECTORING_INFO_VALID_MASK
3590                 | INTR_TYPE_EXT_INTR
3591                 | vmx->rmode.irq.vector;
3592 }
3593
3594 #ifdef CONFIG_X86_64
3595 #define R "r"
3596 #define Q "q"
3597 #else
3598 #define R "e"
3599 #define Q "l"
3600 #endif
3601
3602 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3603 {
3604         struct vcpu_vmx *vmx = to_vmx(vcpu);
3605
3606         if (enable_ept && is_paging(vcpu)) {
3607                 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3608                 ept_load_pdptrs(vcpu);
3609         }
3610         /* Record the guest's net vcpu time for enforced NMI injections. */
3611         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3612                 vmx->entry_time = ktime_get();
3613
3614         /* Handle invalid guest state instead of entering VMX */
3615         if (vmx->emulation_required && emulate_invalid_guest_state) {
3616                 handle_invalid_guest_state(vcpu, kvm_run);
3617                 return;
3618         }
3619
3620         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3621                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3622         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3623                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3624
3625         /* When single-stepping over STI and MOV SS, we must clear the
3626          * corresponding interruptibility bits in the guest state. Otherwise
3627          * vmentry fails as it then expects bit 14 (BS) in pending debug
3628          * exceptions being set, but that's not correct for the guest debugging
3629          * case. */
3630         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3631                 vmx_set_interrupt_shadow(vcpu, 0);
3632
3633         /*
3634          * Loading guest fpu may have cleared host cr0.ts
3635          */
3636         vmcs_writel(HOST_CR0, read_cr0());
3637
3638         set_debugreg(vcpu->arch.dr6, 6);
3639
3640         asm(
3641                 /* Store host registers */
3642                 "push %%"R"dx; push %%"R"bp;"
3643                 "push %%"R"cx \n\t"
3644                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3645                 "je 1f \n\t"
3646                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3647                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3648                 "1: \n\t"
3649                 /* Reload cr2 if changed */
3650                 "mov %c[cr2](%0), %%"R"ax \n\t"
3651                 "mov %%cr2, %%"R"dx \n\t"
3652                 "cmp %%"R"ax, %%"R"dx \n\t"
3653                 "je 2f \n\t"
3654                 "mov %%"R"ax, %%cr2 \n\t"
3655                 "2: \n\t"
3656                 /* Check if vmlaunch of vmresume is needed */
3657                 "cmpl $0, %c[launched](%0) \n\t"
3658                 /* Load guest registers.  Don't clobber flags. */
3659                 "mov %c[rax](%0), %%"R"ax \n\t"
3660                 "mov %c[rbx](%0), %%"R"bx \n\t"
3661                 "mov %c[rdx](%0), %%"R"dx \n\t"
3662                 "mov %c[rsi](%0), %%"R"si \n\t"
3663                 "mov %c[rdi](%0), %%"R"di \n\t"
3664                 "mov %c[rbp](%0), %%"R"bp \n\t"
3665 #ifdef CONFIG_X86_64
3666                 "mov %c[r8](%0),  %%r8  \n\t"
3667                 "mov %c[r9](%0),  %%r9  \n\t"
3668                 "mov %c[r10](%0), %%r10 \n\t"
3669                 "mov %c[r11](%0), %%r11 \n\t"
3670                 "mov %c[r12](%0), %%r12 \n\t"
3671                 "mov %c[r13](%0), %%r13 \n\t"
3672                 "mov %c[r14](%0), %%r14 \n\t"
3673                 "mov %c[r15](%0), %%r15 \n\t"
3674 #endif
3675                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3676
3677                 /* Enter guest mode */
3678                 "jne .Llaunched \n\t"
3679                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3680                 "jmp .Lkvm_vmx_return \n\t"
3681                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3682                 ".Lkvm_vmx_return: "
3683                 /* Save guest registers, load host registers, keep flags */
3684                 "xchg %0,     (%%"R"sp) \n\t"
3685                 "mov %%"R"ax, %c[rax](%0) \n\t"
3686                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3687                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3688                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3689                 "mov %%"R"si, %c[rsi](%0) \n\t"
3690                 "mov %%"R"di, %c[rdi](%0) \n\t"
3691                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3692 #ifdef CONFIG_X86_64
3693                 "mov %%r8,  %c[r8](%0) \n\t"
3694                 "mov %%r9,  %c[r9](%0) \n\t"
3695                 "mov %%r10, %c[r10](%0) \n\t"
3696                 "mov %%r11, %c[r11](%0) \n\t"
3697                 "mov %%r12, %c[r12](%0) \n\t"
3698                 "mov %%r13, %c[r13](%0) \n\t"
3699                 "mov %%r14, %c[r14](%0) \n\t"
3700                 "mov %%r15, %c[r15](%0) \n\t"
3701 #endif
3702                 "mov %%cr2, %%"R"ax   \n\t"
3703                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3704
3705                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3706                 "setbe %c[fail](%0) \n\t"
3707               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3708                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3709                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3710                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3711                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3712                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3713                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3714                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3715                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3716                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3717                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3718 #ifdef CONFIG_X86_64
3719                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3720                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3721                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3722                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3723                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3724                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3725                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3726                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3727 #endif
3728                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3729               : "cc", "memory"
3730                 , R"bx", R"di", R"si"
3731 #ifdef CONFIG_X86_64
3732                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3733 #endif
3734               );
3735
3736         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3737                                   | (1 << VCPU_EXREG_PDPTR));
3738         vcpu->arch.regs_dirty = 0;
3739
3740         get_debugreg(vcpu->arch.dr6, 6);
3741
3742         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3743         if (vmx->rmode.irq.pending)
3744                 fixup_rmode_irq(vmx);
3745
3746         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3747         vmx->launched = 1;
3748
3749         vmx_complete_interrupts(vmx);
3750 }
3751
3752 #undef R
3753 #undef Q
3754
3755 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3756 {
3757         struct vcpu_vmx *vmx = to_vmx(vcpu);
3758
3759         if (vmx->vmcs) {
3760                 vcpu_clear(vmx);
3761                 free_vmcs(vmx->vmcs);
3762                 vmx->vmcs = NULL;
3763         }
3764 }
3765
3766 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3767 {
3768         struct vcpu_vmx *vmx = to_vmx(vcpu);
3769
3770         spin_lock(&vmx_vpid_lock);
3771         if (vmx->vpid != 0)
3772                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3773         spin_unlock(&vmx_vpid_lock);
3774         vmx_free_vmcs(vcpu);
3775         kfree(vmx->host_msrs);
3776         kfree(vmx->guest_msrs);
3777         kvm_vcpu_uninit(vcpu);
3778         kmem_cache_free(kvm_vcpu_cache, vmx);
3779 }
3780
3781 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3782 {
3783         int err;
3784         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3785         int cpu;
3786
3787         if (!vmx)
3788                 return ERR_PTR(-ENOMEM);
3789
3790         allocate_vpid(vmx);
3791
3792         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3793         if (err)
3794                 goto free_vcpu;
3795
3796         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3797         if (!vmx->guest_msrs) {
3798                 err = -ENOMEM;
3799                 goto uninit_vcpu;
3800         }
3801
3802         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3803         if (!vmx->host_msrs)
3804                 goto free_guest_msrs;
3805
3806         vmx->vmcs = alloc_vmcs();
3807         if (!vmx->vmcs)
3808                 goto free_msrs;
3809
3810         vmcs_clear(vmx->vmcs);
3811
3812         cpu = get_cpu();
3813         vmx_vcpu_load(&vmx->vcpu, cpu);
3814         err = vmx_vcpu_setup(vmx);
3815         vmx_vcpu_put(&vmx->vcpu);
3816         put_cpu();
3817         if (err)
3818                 goto free_vmcs;
3819         if (vm_need_virtualize_apic_accesses(kvm))
3820                 if (alloc_apic_access_page(kvm) != 0)
3821                         goto free_vmcs;
3822
3823         if (enable_ept) {
3824                 if (!kvm->arch.ept_identity_map_addr)
3825                         kvm->arch.ept_identity_map_addr =
3826                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3827                 if (alloc_identity_pagetable(kvm) != 0)
3828                         goto free_vmcs;
3829         }
3830
3831         return &vmx->vcpu;
3832
3833 free_vmcs:
3834         free_vmcs(vmx->vmcs);
3835 free_msrs:
3836         kfree(vmx->host_msrs);
3837 free_guest_msrs:
3838         kfree(vmx->guest_msrs);
3839 uninit_vcpu:
3840         kvm_vcpu_uninit(&vmx->vcpu);
3841 free_vcpu:
3842         kmem_cache_free(kvm_vcpu_cache, vmx);
3843         return ERR_PTR(err);
3844 }
3845
3846 static void __init vmx_check_processor_compat(void *rtn)
3847 {
3848         struct vmcs_config vmcs_conf;
3849
3850         *(int *)rtn = 0;
3851         if (setup_vmcs_config(&vmcs_conf) < 0)
3852                 *(int *)rtn = -EIO;
3853         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3854                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3855                                 smp_processor_id());
3856                 *(int *)rtn = -EIO;
3857         }
3858 }
3859
3860 static int get_ept_level(void)
3861 {
3862         return VMX_EPT_DEFAULT_GAW + 1;
3863 }
3864
3865 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3866 {
3867         u64 ret;
3868
3869         /* For VT-d and EPT combination
3870          * 1. MMIO: always map as UC
3871          * 2. EPT with VT-d:
3872          *   a. VT-d without snooping control feature: can't guarantee the
3873          *      result, try to trust guest.
3874          *   b. VT-d with snooping control feature: snooping control feature of
3875          *      VT-d engine can guarantee the cache correctness. Just set it
3876          *      to WB to keep consistent with host. So the same as item 3.
3877          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3878          *    consistent with host MTRR
3879          */
3880         if (is_mmio)
3881                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3882         else if (vcpu->kvm->arch.iommu_domain &&
3883                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3884                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3885                       VMX_EPT_MT_EPTE_SHIFT;
3886         else
3887                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3888                         | VMX_EPT_IGMT_BIT;
3889
3890         return ret;
3891 }
3892
3893 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3894         { EXIT_REASON_EXCEPTION_NMI,           "exception" },
3895         { EXIT_REASON_EXTERNAL_INTERRUPT,      "ext_irq" },
3896         { EXIT_REASON_TRIPLE_FAULT,            "triple_fault" },
3897         { EXIT_REASON_NMI_WINDOW,              "nmi_window" },
3898         { EXIT_REASON_IO_INSTRUCTION,          "io_instruction" },
3899         { EXIT_REASON_CR_ACCESS,               "cr_access" },
3900         { EXIT_REASON_DR_ACCESS,               "dr_access" },
3901         { EXIT_REASON_CPUID,                   "cpuid" },
3902         { EXIT_REASON_MSR_READ,                "rdmsr" },
3903         { EXIT_REASON_MSR_WRITE,               "wrmsr" },
3904         { EXIT_REASON_PENDING_INTERRUPT,       "interrupt_window" },
3905         { EXIT_REASON_HLT,                     "halt" },
3906         { EXIT_REASON_INVLPG,                  "invlpg" },
3907         { EXIT_REASON_VMCALL,                  "hypercall" },
3908         { EXIT_REASON_TPR_BELOW_THRESHOLD,     "tpr_below_thres" },
3909         { EXIT_REASON_APIC_ACCESS,             "apic_access" },
3910         { EXIT_REASON_WBINVD,                  "wbinvd" },
3911         { EXIT_REASON_TASK_SWITCH,             "task_switch" },
3912         { EXIT_REASON_EPT_VIOLATION,           "ept_violation" },
3913         { -1, NULL }
3914 };
3915
3916 static bool vmx_gb_page_enable(void)
3917 {
3918         return false;
3919 }
3920
3921 static struct kvm_x86_ops vmx_x86_ops = {
3922         .cpu_has_kvm_support = cpu_has_kvm_support,
3923         .disabled_by_bios = vmx_disabled_by_bios,
3924         .hardware_setup = hardware_setup,
3925         .hardware_unsetup = hardware_unsetup,
3926         .check_processor_compatibility = vmx_check_processor_compat,
3927         .hardware_enable = hardware_enable,
3928         .hardware_disable = hardware_disable,
3929         .cpu_has_accelerated_tpr = report_flexpriority,
3930
3931         .vcpu_create = vmx_create_vcpu,
3932         .vcpu_free = vmx_free_vcpu,
3933         .vcpu_reset = vmx_vcpu_reset,
3934
3935         .prepare_guest_switch = vmx_save_host_state,
3936         .vcpu_load = vmx_vcpu_load,
3937         .vcpu_put = vmx_vcpu_put,
3938
3939         .set_guest_debug = set_guest_debug,
3940         .get_msr = vmx_get_msr,
3941         .set_msr = vmx_set_msr,
3942         .get_segment_base = vmx_get_segment_base,
3943         .get_segment = vmx_get_segment,
3944         .set_segment = vmx_set_segment,
3945         .get_cpl = vmx_get_cpl,
3946         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3947         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3948         .set_cr0 = vmx_set_cr0,
3949         .set_cr3 = vmx_set_cr3,
3950         .set_cr4 = vmx_set_cr4,
3951         .set_efer = vmx_set_efer,
3952         .get_idt = vmx_get_idt,
3953         .set_idt = vmx_set_idt,
3954         .get_gdt = vmx_get_gdt,
3955         .set_gdt = vmx_set_gdt,
3956         .cache_reg = vmx_cache_reg,
3957         .get_rflags = vmx_get_rflags,
3958         .set_rflags = vmx_set_rflags,
3959
3960         .tlb_flush = vmx_flush_tlb,
3961
3962         .run = vmx_vcpu_run,
3963         .handle_exit = vmx_handle_exit,
3964         .skip_emulated_instruction = skip_emulated_instruction,
3965         .set_interrupt_shadow = vmx_set_interrupt_shadow,
3966         .get_interrupt_shadow = vmx_get_interrupt_shadow,
3967         .patch_hypercall = vmx_patch_hypercall,
3968         .set_irq = vmx_inject_irq,
3969         .set_nmi = vmx_inject_nmi,
3970         .queue_exception = vmx_queue_exception,
3971         .interrupt_allowed = vmx_interrupt_allowed,
3972         .nmi_allowed = vmx_nmi_allowed,
3973         .enable_nmi_window = enable_nmi_window,
3974         .enable_irq_window = enable_irq_window,
3975         .update_cr8_intercept = update_cr8_intercept,
3976
3977         .set_tss_addr = vmx_set_tss_addr,
3978         .get_tdp_level = get_ept_level,
3979         .get_mt_mask = vmx_get_mt_mask,
3980
3981         .exit_reasons_str = vmx_exit_reasons_str,
3982         .gb_page_enable = vmx_gb_page_enable,
3983 };
3984
3985 static int __init vmx_init(void)
3986 {
3987         int r;
3988
3989         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3990         if (!vmx_io_bitmap_a)
3991                 return -ENOMEM;
3992
3993         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3994         if (!vmx_io_bitmap_b) {
3995                 r = -ENOMEM;
3996                 goto out;
3997         }
3998
3999         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4000         if (!vmx_msr_bitmap_legacy) {
4001                 r = -ENOMEM;
4002                 goto out1;
4003         }
4004
4005         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4006         if (!vmx_msr_bitmap_longmode) {
4007                 r = -ENOMEM;
4008                 goto out2;
4009         }
4010
4011         /*
4012          * Allow direct access to the PC debug port (it is often used for I/O
4013          * delays, but the vmexits simply slow things down).
4014          */
4015         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4016         clear_bit(0x80, vmx_io_bitmap_a);
4017
4018         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4019
4020         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4021         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4022
4023         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4024
4025         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4026         if (r)
4027                 goto out3;
4028
4029         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4030         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4031         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4032         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4033         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4034         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4035
4036         if (enable_ept) {
4037                 bypass_guest_pf = 0;
4038                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4039                         VMX_EPT_WRITABLE_MASK);
4040                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4041                                 VMX_EPT_EXECUTABLE_MASK);
4042                 kvm_enable_tdp();
4043         } else
4044                 kvm_disable_tdp();
4045
4046         if (bypass_guest_pf)
4047                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4048
4049         ept_sync_global();
4050
4051         return 0;
4052
4053 out3:
4054         free_page((unsigned long)vmx_msr_bitmap_longmode);
4055 out2:
4056         free_page((unsigned long)vmx_msr_bitmap_legacy);
4057 out1:
4058         free_page((unsigned long)vmx_io_bitmap_b);
4059 out:
4060         free_page((unsigned long)vmx_io_bitmap_a);
4061         return r;
4062 }
4063
4064 static void __exit vmx_exit(void)
4065 {
4066         free_page((unsigned long)vmx_msr_bitmap_legacy);
4067         free_page((unsigned long)vmx_msr_bitmap_longmode);
4068         free_page((unsigned long)vmx_io_bitmap_b);
4069         free_page((unsigned long)vmx_io_bitmap_a);
4070
4071         kvm_exit();
4072 }
4073
4074 module_init(vmx_init)
4075 module_exit(vmx_exit)