Pileus Git - ~andy/linux/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376         u64 msr_ia32_feature_control;
 377 };
 378
 379 #define POSTED_INTR_ON  0
 380 /* Posted-Interrupt Descriptor */
 381 struct pi_desc {
 382         u32 pir[8];     /* Posted interrupt requested */
 383         u32 control;    /* bit 0 of control is outstanding notification bit */
 384         u32 rsvd[7];
 385 } __aligned(64);
 386
 387 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 388 {
 389         return test_and_set_bit(POSTED_INTR_ON,
 390                         (unsigned long *)&pi_desc->control);
 391 }
 392
 393 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 394 {
 395         return test_and_clear_bit(POSTED_INTR_ON,
 396                         (unsigned long *)&pi_desc->control);
 397 }
 398
 399 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 400 {
 401         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 402 }
 403
 404 struct vcpu_vmx {
 405         struct kvm_vcpu       vcpu;
 406         unsigned long         host_rsp;
 407         u8                    fail;
 408         u8                    cpl;
 409         bool                  nmi_known_unmasked;
 410         u32                   exit_intr_info;
 411         u32                   idt_vectoring_info;
 412         ulong                 rflags;
 413         struct shared_msr_entry *guest_msrs;
 414         int                   nmsrs;
 415         int                   save_nmsrs;
 416         unsigned long         host_idt_base;
 417 #ifdef CONFIG_X86_64
 418         u64                   msr_host_kernel_gs_base;
 419         u64                   msr_guest_kernel_gs_base;
 420 #endif
 421         /*
 422          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 423          * non-nested (L1) guest, it always points to vmcs01. For a nested
 424          * guest (L2), it points to a different VMCS.
 425          */
 426         struct loaded_vmcs    vmcs01;
 427         struct loaded_vmcs   *loaded_vmcs;
 428         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 429         struct msr_autoload {
 430                 unsigned nr;
 431                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 432                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 433         } msr_autoload;
 434         struct {
 435                 int           loaded;
 436                 u16           fs_sel, gs_sel, ldt_sel;
 437 #ifdef CONFIG_X86_64
 438                 u16           ds_sel, es_sel;
 439 #endif
 440                 int           gs_ldt_reload_needed;
 441                 int           fs_reload_needed;
 442         } host_state;
 443         struct {
 444                 int vm86_active;
 445                 ulong save_rflags;
 446                 struct kvm_segment segs[8];
 447         } rmode;
 448         struct {
 449                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 450                 struct kvm_save_segment {
 451                         u16 selector;
 452                         unsigned long base;
 453                         u32 limit;
 454                         u32 ar;
 455                 } seg[8];
 456         } segment_cache;
 457         int vpid;
 458         bool emulation_required;
 459
 460         /* Support for vnmi-less CPUs */
 461         int soft_vnmi_blocked;
 462         ktime_t entry_time;
 463         s64 vnmi_blocked_time;
 464         u32 exit_reason;
 465
 466         bool rdtscp_enabled;
 467
 468         /* Posted interrupt descriptor */
 469         struct pi_desc pi_desc;
 470
 471         /* Support for a guest hypervisor (nested VMX) */
 472         struct nested_vmx nested;
 473 };
 474
 475 enum segment_cache_field {
 476         SEG_FIELD_SEL = 0,
 477         SEG_FIELD_BASE = 1,
 478         SEG_FIELD_LIMIT = 2,
 479         SEG_FIELD_AR = 3,
 480
 481         SEG_FIELD_NR = 4
 482 };
 483
 484 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 485 {
 486         return container_of(vcpu, struct vcpu_vmx, vcpu);
 487 }
 488
 489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 490 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 491 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 492                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 493
 494
 495 static const unsigned long shadow_read_only_fields[] = {
 496         /*
 497          * We do NOT shadow fields that are modified when L0
 498          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 499          * VMXON...) executed by L1.
 500          * For example, VM_INSTRUCTION_ERROR is read
 501          * by L1 if a vmx instruction fails (part of the error path).
 502          * Note the code assumes this logic. If for some reason
 503          * we start shadowing these fields then we need to
 504          * force a shadow sync when L0 emulates vmx instructions
 505          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 506          * by nested_vmx_failValid)
 507          */
 508         VM_EXIT_REASON,
 509         VM_EXIT_INTR_INFO,
 510         VM_EXIT_INSTRUCTION_LEN,
 511         IDT_VECTORING_INFO_FIELD,
 512         IDT_VECTORING_ERROR_CODE,
 513         VM_EXIT_INTR_ERROR_CODE,
 514         EXIT_QUALIFICATION,
 515         GUEST_LINEAR_ADDRESS,
 516         GUEST_PHYSICAL_ADDRESS
 517 };
 518 static const int max_shadow_read_only_fields =
 519         ARRAY_SIZE(shadow_read_only_fields);
 520
 521 static const unsigned long shadow_read_write_fields[] = {
 522         GUEST_RIP,
 523         GUEST_RSP,
 524         GUEST_CR0,
 525         GUEST_CR3,
 526         GUEST_CR4,
 527         GUEST_INTERRUPTIBILITY_INFO,
 528         GUEST_RFLAGS,
 529         GUEST_CS_SELECTOR,
 530         GUEST_CS_AR_BYTES,
 531         GUEST_CS_LIMIT,
 532         GUEST_CS_BASE,
 533         GUEST_ES_BASE,
 534         CR0_GUEST_HOST_MASK,
 535         CR0_READ_SHADOW,
 536         CR4_READ_SHADOW,
 537         TSC_OFFSET,
 538         EXCEPTION_BITMAP,
 539         CPU_BASED_VM_EXEC_CONTROL,
 540         VM_ENTRY_EXCEPTION_ERROR_CODE,
 541         VM_ENTRY_INTR_INFO_FIELD,
 542         VM_ENTRY_INSTRUCTION_LEN,
 543         VM_ENTRY_EXCEPTION_ERROR_CODE,
 544         HOST_FS_BASE,
 545         HOST_GS_BASE,
 546         HOST_FS_SELECTOR,
 547         HOST_GS_SELECTOR
 548 };
 549 static const int max_shadow_read_write_fields =
 550         ARRAY_SIZE(shadow_read_write_fields);
 551
 552 static const unsigned short vmcs_field_to_offset_table[] = {
 553         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 554         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 555         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 556         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 557         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 558         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 559         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 560         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 561         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 562         FIELD(HOST_ES_SELECTOR, host_es_selector),
 563         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 564         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 565         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 566         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 567         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 568         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 569         FIELD64(IO_BITMAP_A, io_bitmap_a),
 570         FIELD64(IO_BITMAP_B, io_bitmap_b),
 571         FIELD64(MSR_BITMAP, msr_bitmap),
 572         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 573         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 574         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 575         FIELD64(TSC_OFFSET, tsc_offset),
 576         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 577         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 578         FIELD64(EPT_POINTER, ept_pointer),
 579         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 580         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 581         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 582         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 583         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 584         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 585         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 586         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 587         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 588         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 589         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 590         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 591         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 592         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 593         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 594         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 595         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 596         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 597         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 598         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 599         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 600         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 601         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 602         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 603         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 604         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 605         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 606         FIELD(TPR_THRESHOLD, tpr_threshold),
 607         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 608         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 609         FIELD(VM_EXIT_REASON, vm_exit_reason),
 610         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 611         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 612         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 613         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 614         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 615         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 616         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 617         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 618         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 619         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 620         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 621         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 622         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 623         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 624         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 625         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 626         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 627         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 628         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 629         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 630         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 631         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 632         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 633         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 634         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 635         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 636         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 637         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 638         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 639         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 640         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 641         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 642         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 643         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 644         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 645         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 646         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 647         FIELD(EXIT_QUALIFICATION, exit_qualification),
 648         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 649         FIELD(GUEST_CR0, guest_cr0),
 650         FIELD(GUEST_CR3, guest_cr3),
 651         FIELD(GUEST_CR4, guest_cr4),
 652         FIELD(GUEST_ES_BASE, guest_es_base),
 653         FIELD(GUEST_CS_BASE, guest_cs_base),
 654         FIELD(GUEST_SS_BASE, guest_ss_base),
 655         FIELD(GUEST_DS_BASE, guest_ds_base),
 656         FIELD(GUEST_FS_BASE, guest_fs_base),
 657         FIELD(GUEST_GS_BASE, guest_gs_base),
 658         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 659         FIELD(GUEST_TR_BASE, guest_tr_base),
 660         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 661         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 662         FIELD(GUEST_DR7, guest_dr7),
 663         FIELD(GUEST_RSP, guest_rsp),
 664         FIELD(GUEST_RIP, guest_rip),
 665         FIELD(GUEST_RFLAGS, guest_rflags),
 666         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 667         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 668         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 669         FIELD(HOST_CR0, host_cr0),
 670         FIELD(HOST_CR3, host_cr3),
 671         FIELD(HOST_CR4, host_cr4),
 672         FIELD(HOST_FS_BASE, host_fs_base),
 673         FIELD(HOST_GS_BASE, host_gs_base),
 674         FIELD(HOST_TR_BASE, host_tr_base),
 675         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 676         FIELD(HOST_IDTR_BASE, host_idtr_base),
 677         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 678         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 679         FIELD(HOST_RSP, host_rsp),
 680         FIELD(HOST_RIP, host_rip),
 681 };
 682 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 683
 684 static inline short vmcs_field_to_offset(unsigned long field)
 685 {
 686         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 687                 return -1;
 688         return vmcs_field_to_offset_table[field];
 689 }
 690
 691 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 692 {
 693         return to_vmx(vcpu)->nested.current_vmcs12;
 694 }
 695
 696 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 697 {
 698         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 699         if (is_error_page(page))
 700                 return NULL;
 701
 702         return page;
 703 }
 704
 705 static void nested_release_page(struct page *page)
 706 {
 707         kvm_release_page_dirty(page);
 708 }
 709
 710 static void nested_release_page_clean(struct page *page)
 711 {
 712         kvm_release_page_clean(page);
 713 }
 714
 715 static u64 construct_eptp(unsigned long root_hpa);
 716 static void kvm_cpu_vmxon(u64 addr);
 717 static void kvm_cpu_vmxoff(void);
 718 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 719 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 720 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 721                             struct kvm_segment *var, int seg);
 722 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 723                             struct kvm_segment *var, int seg);
 724 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 725 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 726 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 727 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 728 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 729
 730 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 731 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 732 /*
 733  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 734  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 735  */
 736 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 737 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 738
 739 static unsigned long *vmx_io_bitmap_a;
 740 static unsigned long *vmx_io_bitmap_b;
 741 static unsigned long *vmx_msr_bitmap_legacy;
 742 static unsigned long *vmx_msr_bitmap_longmode;
 743 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 744 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 745 static unsigned long *vmx_vmread_bitmap;
 746 static unsigned long *vmx_vmwrite_bitmap;
 747
 748 static bool cpu_has_load_ia32_efer;
 749 static bool cpu_has_load_perf_global_ctrl;
 750
 751 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 752 static DEFINE_SPINLOCK(vmx_vpid_lock);
 753
 754 static struct vmcs_config {
 755         int size;
 756         int order;
 757         u32 revision_id;
 758         u32 pin_based_exec_ctrl;
 759         u32 cpu_based_exec_ctrl;
 760         u32 cpu_based_2nd_exec_ctrl;
 761         u32 vmexit_ctrl;
 762         u32 vmentry_ctrl;
 763 } vmcs_config;
 764
 765 static struct vmx_capability {
 766         u32 ept;
 767         u32 vpid;
 768 } vmx_capability;
 769
 770 #define VMX_SEGMENT_FIELD(seg)                                  \
 771         [VCPU_SREG_##seg] = {                                   \
 772                 .selector = GUEST_##seg##_SELECTOR,             \
 773                 .base = GUEST_##seg##_BASE,                     \
 774                 .limit = GUEST_##seg##_LIMIT,                   \
 775                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 776         }
 777
 778 static const struct kvm_vmx_segment_field {
 779         unsigned selector;
 780         unsigned base;
 781         unsigned limit;
 782         unsigned ar_bytes;
 783 } kvm_vmx_segment_fields[] = {
 784         VMX_SEGMENT_FIELD(CS),
 785         VMX_SEGMENT_FIELD(DS),
 786         VMX_SEGMENT_FIELD(ES),
 787         VMX_SEGMENT_FIELD(FS),
 788         VMX_SEGMENT_FIELD(GS),
 789         VMX_SEGMENT_FIELD(SS),
 790         VMX_SEGMENT_FIELD(TR),
 791         VMX_SEGMENT_FIELD(LDTR),
 792 };
 793
 794 static u64 host_efer;
 795
 796 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 797
 798 /*
 799  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 800  * away by decrementing the array size.
 801  */
 802 static const u32 vmx_msr_index[] = {
 803 #ifdef CONFIG_X86_64
 804         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 805 #endif
 806         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 807 };
 808 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 809
 810 static inline bool is_page_fault(u32 intr_info)
 811 {
 812         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 813                              INTR_INFO_VALID_MASK)) ==
 814                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 815 }
 816
 817 static inline bool is_no_device(u32 intr_info)
 818 {
 819         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 820                              INTR_INFO_VALID_MASK)) ==
 821                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 822 }
 823
 824 static inline bool is_invalid_opcode(u32 intr_info)
 825 {
 826         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 827                              INTR_INFO_VALID_MASK)) ==
 828                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 829 }
 830
 831 static inline bool is_external_interrupt(u32 intr_info)
 832 {
 833         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 834                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 835 }
 836
 837 static inline bool is_machine_check(u32 intr_info)
 838 {
 839         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 840                              INTR_INFO_VALID_MASK)) ==
 841                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 842 }
 843
 844 static inline bool cpu_has_vmx_msr_bitmap(void)
 845 {
 846         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 847 }
 848
 849 static inline bool cpu_has_vmx_tpr_shadow(void)
 850 {
 851         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 852 }
 853
 854 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 855 {
 856         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 857 }
 858
 859 static inline bool cpu_has_secondary_exec_ctrls(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl &
 862                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 863 }
 864
 865 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 866 {
 867         return vmcs_config.cpu_based_2nd_exec_ctrl &
 868                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 869 }
 870
 871 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 872 {
 873         return vmcs_config.cpu_based_2nd_exec_ctrl &
 874                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 875 }
 876
 877 static inline bool cpu_has_vmx_apic_register_virt(void)
 878 {
 879         return vmcs_config.cpu_based_2nd_exec_ctrl &
 880                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 881 }
 882
 883 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 884 {
 885         return vmcs_config.cpu_based_2nd_exec_ctrl &
 886                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 887 }
 888
 889 static inline bool cpu_has_vmx_posted_intr(void)
 890 {
 891         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 892 }
 893
 894 static inline bool cpu_has_vmx_apicv(void)
 895 {
 896         return cpu_has_vmx_apic_register_virt() &&
 897                 cpu_has_vmx_virtual_intr_delivery() &&
 898                 cpu_has_vmx_posted_intr();
 899 }
 900
 901 static inline bool cpu_has_vmx_flexpriority(void)
 902 {
 903         return cpu_has_vmx_tpr_shadow() &&
 904                 cpu_has_vmx_virtualize_apic_accesses();
 905 }
 906
 907 static inline bool cpu_has_vmx_ept_execute_only(void)
 908 {
 909         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 910 }
 911
 912 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 913 {
 914         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 915 }
 916
 917 static inline bool cpu_has_vmx_eptp_writeback(void)
 918 {
 919         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_2m_page(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_ept_1g_page(void)
 928 {
 929         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_ept_4levels(void)
 933 {
 934         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_ad_bits(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_AD_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_invept_context(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_invept_global(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_invvpid_single(void)
 953 {
 954         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invvpid_global(void)
 958 {
 959         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_ept(void)
 963 {
 964         return vmcs_config.cpu_based_2nd_exec_ctrl &
 965                 SECONDARY_EXEC_ENABLE_EPT;
 966 }
 967
 968 static inline bool cpu_has_vmx_unrestricted_guest(void)
 969 {
 970         return vmcs_config.cpu_based_2nd_exec_ctrl &
 971                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 972 }
 973
 974 static inline bool cpu_has_vmx_ple(void)
 975 {
 976         return vmcs_config.cpu_based_2nd_exec_ctrl &
 977                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 978 }
 979
 980 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 981 {
 982         return flexpriority_enabled && irqchip_in_kernel(kvm);
 983 }
 984
 985 static inline bool cpu_has_vmx_vpid(void)
 986 {
 987         return vmcs_config.cpu_based_2nd_exec_ctrl &
 988                 SECONDARY_EXEC_ENABLE_VPID;
 989 }
 990
 991 static inline bool cpu_has_vmx_rdtscp(void)
 992 {
 993         return vmcs_config.cpu_based_2nd_exec_ctrl &
 994                 SECONDARY_EXEC_RDTSCP;
 995 }
 996
 997 static inline bool cpu_has_vmx_invpcid(void)
 998 {
 999         return vmcs_config.cpu_based_2nd_exec_ctrl &
1000                 SECONDARY_EXEC_ENABLE_INVPCID;
1001 }
1002
1003 static inline bool cpu_has_virtual_nmis(void)
1004 {
1005         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006 }
1007
1008 static inline bool cpu_has_vmx_wbinvd_exit(void)
1009 {
1010         return vmcs_config.cpu_based_2nd_exec_ctrl &
1011                 SECONDARY_EXEC_WBINVD_EXITING;
1012 }
1013
1014 static inline bool cpu_has_vmx_shadow_vmcs(void)
1015 {
1016         u64 vmx_msr;
1017         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018         /* check if the cpu supports writing r/o exit information fields */
1019         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020                 return false;
1021
1022         return vmcs_config.cpu_based_2nd_exec_ctrl &
1023                 SECONDARY_EXEC_SHADOW_VMCS;
1024 }
1025
1026 static inline bool report_flexpriority(void)
1027 {
1028         return flexpriority_enabled;
1029 }
1030
1031 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032 {
1033         return vmcs12->cpu_based_vm_exec_control & bit;
1034 }
1035
1036 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037 {
1038         return (vmcs12->cpu_based_vm_exec_control &
1039                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040                 (vmcs12->secondary_vm_exec_control & bit);
1041 }
1042
1043 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1044         struct kvm_vcpu *vcpu)
1045 {
1046         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1047 }
1048
1049 static inline bool is_exception(u32 intr_info)
1050 {
1051         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1052                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1053 }
1054
1055 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1056 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1057                         struct vmcs12 *vmcs12,
1058                         u32 reason, unsigned long qualification);
1059
1060 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1061 {
1062         int i;
1063
1064         for (i = 0; i < vmx->nmsrs; ++i)
1065                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1066                         return i;
1067         return -1;
1068 }
1069
1070 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1071 {
1072     struct {
1073         u64 vpid : 16;
1074         u64 rsvd : 48;
1075         u64 gva;
1076     } operand = { vpid, 0, gva };
1077
1078     asm volatile (__ex(ASM_VMX_INVVPID)
1079                   /* CF==1 or ZF==1 --> rc = -1 */
1080                   "; ja 1f ; ud2 ; 1:"
1081                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1082 }
1083
1084 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1085 {
1086         struct {
1087                 u64 eptp, gpa;
1088         } operand = {eptp, gpa};
1089
1090         asm volatile (__ex(ASM_VMX_INVEPT)
1091                         /* CF==1 or ZF==1 --> rc = -1 */
1092                         "; ja 1f ; ud2 ; 1:\n"
1093                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1094 }
1095
1096 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1097 {
1098         int i;
1099
1100         i = __find_msr_index(vmx, msr);
1101         if (i >= 0)
1102                 return &vmx->guest_msrs[i];
1103         return NULL;
1104 }
1105
1106 static void vmcs_clear(struct vmcs *vmcs)
1107 {
1108         u64 phys_addr = __pa(vmcs);
1109         u8 error;
1110
1111         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1112                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1113                       : "cc", "memory");
1114         if (error)
1115                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1116                        vmcs, phys_addr);
1117 }
1118
1119 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1120 {
1121         vmcs_clear(loaded_vmcs->vmcs);
1122         loaded_vmcs->cpu = -1;
1123         loaded_vmcs->launched = 0;
1124 }
1125
1126 static void vmcs_load(struct vmcs *vmcs)
1127 {
1128         u64 phys_addr = __pa(vmcs);
1129         u8 error;
1130
1131         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1132                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1133                         : "cc", "memory");
1134         if (error)
1135                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1136                        vmcs, phys_addr);
1137 }
1138
1139 #ifdef CONFIG_KEXEC
1140 /*
1141  * This bitmap is used to indicate whether the vmclear
1142  * operation is enabled on all cpus. All disabled by
1143  * default.
1144  */
1145 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1146
1147 static inline void crash_enable_local_vmclear(int cpu)
1148 {
1149         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1150 }
1151
1152 static inline void crash_disable_local_vmclear(int cpu)
1153 {
1154         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1155 }
1156
1157 static inline int crash_local_vmclear_enabled(int cpu)
1158 {
1159         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1160 }
1161
1162 static void crash_vmclear_local_loaded_vmcss(void)
1163 {
1164         int cpu = raw_smp_processor_id();
1165         struct loaded_vmcs *v;
1166
1167         if (!crash_local_vmclear_enabled(cpu))
1168                 return;
1169
1170         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1171                             loaded_vmcss_on_cpu_link)
1172                 vmcs_clear(v->vmcs);
1173 }
1174 #else
1175 static inline void crash_enable_local_vmclear(int cpu) { }
1176 static inline void crash_disable_local_vmclear(int cpu) { }
1177 #endif /* CONFIG_KEXEC */
1178
1179 static void __loaded_vmcs_clear(void *arg)
1180 {
1181         struct loaded_vmcs *loaded_vmcs = arg;
1182         int cpu = raw_smp_processor_id();
1183
1184         if (loaded_vmcs->cpu != cpu)
1185                 return; /* vcpu migration can race with cpu offline */
1186         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1187                 per_cpu(current_vmcs, cpu) = NULL;
1188         crash_disable_local_vmclear(cpu);
1189         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1190
1191         /*
1192          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1193          * is before setting loaded_vmcs->vcpu to -1 which is done in
1194          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1195          * then adds the vmcs into percpu list before it is deleted.
1196          */
1197         smp_wmb();
1198
1199         loaded_vmcs_init(loaded_vmcs);
1200         crash_enable_local_vmclear(cpu);
1201 }
1202
1203 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1204 {
1205         int cpu = loaded_vmcs->cpu;
1206
1207         if (cpu != -1)
1208                 smp_call_function_single(cpu,
1209                          __loaded_vmcs_clear, loaded_vmcs, 1);
1210 }
1211
1212 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1213 {
1214         if (vmx->vpid == 0)
1215                 return;
1216
1217         if (cpu_has_vmx_invvpid_single())
1218                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1219 }
1220
1221 static inline void vpid_sync_vcpu_global(void)
1222 {
1223         if (cpu_has_vmx_invvpid_global())
1224                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1225 }
1226
1227 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1228 {
1229         if (cpu_has_vmx_invvpid_single())
1230                 vpid_sync_vcpu_single(vmx);
1231         else
1232                 vpid_sync_vcpu_global();
1233 }
1234
1235 static inline void ept_sync_global(void)
1236 {
1237         if (cpu_has_vmx_invept_global())
1238                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1239 }
1240
1241 static inline void ept_sync_context(u64 eptp)
1242 {
1243         if (enable_ept) {
1244                 if (cpu_has_vmx_invept_context())
1245                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1246                 else
1247                         ept_sync_global();
1248         }
1249 }
1250
1251 static __always_inline unsigned long vmcs_readl(unsigned long field)
1252 {
1253         unsigned long value;
1254
1255         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1256                       : "=a"(value) : "d"(field) : "cc");
1257         return value;
1258 }
1259
1260 static __always_inline u16 vmcs_read16(unsigned long field)
1261 {
1262         return vmcs_readl(field);
1263 }
1264
1265 static __always_inline u32 vmcs_read32(unsigned long field)
1266 {
1267         return vmcs_readl(field);
1268 }
1269
1270 static __always_inline u64 vmcs_read64(unsigned long field)
1271 {
1272 #ifdef CONFIG_X86_64
1273         return vmcs_readl(field);
1274 #else
1275         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1276 #endif
1277 }
1278
1279 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1280 {
1281         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1282                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1283         dump_stack();
1284 }
1285
1286 static void vmcs_writel(unsigned long field, unsigned long value)
1287 {
1288         u8 error;
1289
1290         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1291                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1292         if (unlikely(error))
1293                 vmwrite_error(field, value);
1294 }
1295
1296 static void vmcs_write16(unsigned long field, u16 value)
1297 {
1298         vmcs_writel(field, value);
1299 }
1300
1301 static void vmcs_write32(unsigned long field, u32 value)
1302 {
1303         vmcs_writel(field, value);
1304 }
1305
1306 static void vmcs_write64(unsigned long field, u64 value)
1307 {
1308         vmcs_writel(field, value);
1309 #ifndef CONFIG_X86_64
1310         asm volatile ("");
1311         vmcs_writel(field+1, value >> 32);
1312 #endif
1313 }
1314
1315 static void vmcs_clear_bits(unsigned long field, u32 mask)
1316 {
1317         vmcs_writel(field, vmcs_readl(field) & ~mask);
1318 }
1319
1320 static void vmcs_set_bits(unsigned long field, u32 mask)
1321 {
1322         vmcs_writel(field, vmcs_readl(field) | mask);
1323 }
1324
1325 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1326 {
1327         vmx->segment_cache.bitmask = 0;
1328 }
1329
1330 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1331                                        unsigned field)
1332 {
1333         bool ret;
1334         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1335
1336         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1337                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1338                 vmx->segment_cache.bitmask = 0;
1339         }
1340         ret = vmx->segment_cache.bitmask & mask;
1341         vmx->segment_cache.bitmask |= mask;
1342         return ret;
1343 }
1344
1345 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1346 {
1347         u16 *p = &vmx->segment_cache.seg[seg].selector;
1348
1349         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1350                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1351         return *p;
1352 }
1353
1354 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1355 {
1356         ulong *p = &vmx->segment_cache.seg[seg].base;
1357
1358         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1359                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1360         return *p;
1361 }
1362
1363 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1364 {
1365         u32 *p = &vmx->segment_cache.seg[seg].limit;
1366
1367         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1368                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1369         return *p;
1370 }
1371
1372 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1373 {
1374         u32 *p = &vmx->segment_cache.seg[seg].ar;
1375
1376         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1377                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1378         return *p;
1379 }
1380
1381 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1382 {
1383         u32 eb;
1384
1385         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1386              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1387         if ((vcpu->guest_debug &
1388              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1389             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1390                 eb |= 1u << BP_VECTOR;
1391         if (to_vmx(vcpu)->rmode.vm86_active)
1392                 eb = ~0;
1393         if (enable_ept)
1394                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1395         if (vcpu->fpu_active)
1396                 eb &= ~(1u << NM_VECTOR);
1397
1398         /* When we are running a nested L2 guest and L1 specified for it a
1399          * certain exception bitmap, we must trap the same exceptions and pass
1400          * them to L1. When running L2, we will only handle the exceptions
1401          * specified above if L1 did not want them.
1402          */
1403         if (is_guest_mode(vcpu))
1404                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1405
1406         vmcs_write32(EXCEPTION_BITMAP, eb);
1407 }
1408
1409 static void clear_atomic_switch_msr_special(unsigned long entry,
1410                 unsigned long exit)
1411 {
1412         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1413         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1414 }
1415
1416 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1417 {
1418         unsigned i;
1419         struct msr_autoload *m = &vmx->msr_autoload;
1420
1421         switch (msr) {
1422         case MSR_EFER:
1423                 if (cpu_has_load_ia32_efer) {
1424                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1425                                         VM_EXIT_LOAD_IA32_EFER);
1426                         return;
1427                 }
1428                 break;
1429         case MSR_CORE_PERF_GLOBAL_CTRL:
1430                 if (cpu_has_load_perf_global_ctrl) {
1431                         clear_atomic_switch_msr_special(
1432                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1433                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1434                         return;
1435                 }
1436                 break;
1437         }
1438
1439         for (i = 0; i < m->nr; ++i)
1440                 if (m->guest[i].index == msr)
1441                         break;
1442
1443         if (i == m->nr)
1444                 return;
1445         --m->nr;
1446         m->guest[i] = m->guest[m->nr];
1447         m->host[i] = m->host[m->nr];
1448         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1449         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1450 }
1451
1452 static void add_atomic_switch_msr_special(unsigned long entry,
1453                 unsigned long exit, unsigned long guest_val_vmcs,
1454                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1455 {
1456         vmcs_write64(guest_val_vmcs, guest_val);
1457         vmcs_write64(host_val_vmcs, host_val);
1458         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1459         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1460 }
1461
1462 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1463                                   u64 guest_val, u64 host_val)
1464 {
1465         unsigned i;
1466         struct msr_autoload *m = &vmx->msr_autoload;
1467
1468         switch (msr) {
1469         case MSR_EFER:
1470                 if (cpu_has_load_ia32_efer) {
1471                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1472                                         VM_EXIT_LOAD_IA32_EFER,
1473                                         GUEST_IA32_EFER,
1474                                         HOST_IA32_EFER,
1475                                         guest_val, host_val);
1476                         return;
1477                 }
1478                 break;
1479         case MSR_CORE_PERF_GLOBAL_CTRL:
1480                 if (cpu_has_load_perf_global_ctrl) {
1481                         add_atomic_switch_msr_special(
1482                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1483                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1484                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1485                                         HOST_IA32_PERF_GLOBAL_CTRL,
1486                                         guest_val, host_val);
1487                         return;
1488                 }
1489                 break;
1490         }
1491
1492         for (i = 0; i < m->nr; ++i)
1493                 if (m->guest[i].index == msr)
1494                         break;
1495
1496         if (i == NR_AUTOLOAD_MSRS) {
1497                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1498                                 "Can't add msr %x\n", msr);
1499                 return;
1500         } else if (i == m->nr) {
1501                 ++m->nr;
1502                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1503                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1504         }
1505
1506         m->guest[i].index = msr;
1507         m->guest[i].value = guest_val;
1508         m->host[i].index = msr;
1509         m->host[i].value = host_val;
1510 }
1511
1512 static void reload_tss(void)
1513 {
1514         /*
1515          * VT restores TR but not its size.  Useless.
1516          */
1517         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1518         struct desc_struct *descs;
1519
1520         descs = (void *)gdt->address;
1521         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1522         load_TR_desc();
1523 }
1524
1525 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1526 {
1527         u64 guest_efer;
1528         u64 ignore_bits;
1529
1530         guest_efer = vmx->vcpu.arch.efer;
1531
1532         /*
1533          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1534          * outside long mode
1535          */
1536         ignore_bits = EFER_NX | EFER_SCE;
1537 #ifdef CONFIG_X86_64
1538         ignore_bits |= EFER_LMA | EFER_LME;
1539         /* SCE is meaningful only in long mode on Intel */
1540         if (guest_efer & EFER_LMA)
1541                 ignore_bits &= ~(u64)EFER_SCE;
1542 #endif
1543         guest_efer &= ~ignore_bits;
1544         guest_efer |= host_efer & ignore_bits;
1545         vmx->guest_msrs[efer_offset].data = guest_efer;
1546         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1547
1548         clear_atomic_switch_msr(vmx, MSR_EFER);
1549         /* On ept, can't emulate nx, and must switch nx atomically */
1550         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1551                 guest_efer = vmx->vcpu.arch.efer;
1552                 if (!(guest_efer & EFER_LMA))
1553                         guest_efer &= ~EFER_LME;
1554                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1555                 return false;
1556         }
1557
1558         return true;
1559 }
1560
1561 static unsigned long segment_base(u16 selector)
1562 {
1563         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1564         struct desc_struct *d;
1565         unsigned long table_base;
1566         unsigned long v;
1567
1568         if (!(selector & ~3))
1569                 return 0;
1570
1571         table_base = gdt->address;
1572
1573         if (selector & 4) {           /* from ldt */
1574                 u16 ldt_selector = kvm_read_ldt();
1575
1576                 if (!(ldt_selector & ~3))
1577                         return 0;
1578
1579                 table_base = segment_base(ldt_selector);
1580         }
1581         d = (struct desc_struct *)(table_base + (selector & ~7));
1582         v = get_desc_base(d);
1583 #ifdef CONFIG_X86_64
1584        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1585                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1586 #endif
1587         return v;
1588 }
1589
1590 static inline unsigned long kvm_read_tr_base(void)
1591 {
1592         u16 tr;
1593         asm("str %0" : "=g"(tr));
1594         return segment_base(tr);
1595 }
1596
1597 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1598 {
1599         struct vcpu_vmx *vmx = to_vmx(vcpu);
1600         int i;
1601
1602         if (vmx->host_state.loaded)
1603                 return;
1604
1605         vmx->host_state.loaded = 1;
1606         /*
1607          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1608          * allow segment selectors with cpl > 0 or ti == 1.
1609          */
1610         vmx->host_state.ldt_sel = kvm_read_ldt();
1611         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1612         savesegment(fs, vmx->host_state.fs_sel);
1613         if (!(vmx->host_state.fs_sel & 7)) {
1614                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1615                 vmx->host_state.fs_reload_needed = 0;
1616         } else {
1617                 vmcs_write16(HOST_FS_SELECTOR, 0);
1618                 vmx->host_state.fs_reload_needed = 1;
1619         }
1620         savesegment(gs, vmx->host_state.gs_sel);
1621         if (!(vmx->host_state.gs_sel & 7))
1622                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1623         else {
1624                 vmcs_write16(HOST_GS_SELECTOR, 0);
1625                 vmx->host_state.gs_ldt_reload_needed = 1;
1626         }
1627
1628 #ifdef CONFIG_X86_64
1629         savesegment(ds, vmx->host_state.ds_sel);
1630         savesegment(es, vmx->host_state.es_sel);
1631 #endif
1632
1633 #ifdef CONFIG_X86_64
1634         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1635         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1636 #else
1637         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1638         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1639 #endif
1640
1641 #ifdef CONFIG_X86_64
1642         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1643         if (is_long_mode(&vmx->vcpu))
1644                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1645 #endif
1646         for (i = 0; i < vmx->save_nmsrs; ++i)
1647                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1648                                    vmx->guest_msrs[i].data,
1649                                    vmx->guest_msrs[i].mask);
1650 }
1651
1652 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1653 {
1654         if (!vmx->host_state.loaded)
1655                 return;
1656
1657         ++vmx->vcpu.stat.host_state_reload;
1658         vmx->host_state.loaded = 0;
1659 #ifdef CONFIG_X86_64
1660         if (is_long_mode(&vmx->vcpu))
1661                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1662 #endif
1663         if (vmx->host_state.gs_ldt_reload_needed) {
1664                 kvm_load_ldt(vmx->host_state.ldt_sel);
1665 #ifdef CONFIG_X86_64
1666                 load_gs_index(vmx->host_state.gs_sel);
1667 #else
1668                 loadsegment(gs, vmx->host_state.gs_sel);
1669 #endif
1670         }
1671         if (vmx->host_state.fs_reload_needed)
1672                 loadsegment(fs, vmx->host_state.fs_sel);
1673 #ifdef CONFIG_X86_64
1674         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1675                 loadsegment(ds, vmx->host_state.ds_sel);
1676                 loadsegment(es, vmx->host_state.es_sel);
1677         }
1678 #endif
1679         reload_tss();
1680 #ifdef CONFIG_X86_64
1681         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1682 #endif
1683         /*
1684          * If the FPU is not active (through the host task or
1685          * the guest vcpu), then restore the cr0.TS bit.
1686          */
1687         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1688                 stts();
1689         load_gdt(&__get_cpu_var(host_gdt));
1690 }
1691
1692 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1693 {
1694         preempt_disable();
1695         __vmx_load_host_state(vmx);
1696         preempt_enable();
1697 }
1698
1699 /*
1700  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1701  * vcpu mutex is already taken.
1702  */
1703 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1704 {
1705         struct vcpu_vmx *vmx = to_vmx(vcpu);
1706         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1707
1708         if (!vmm_exclusive)
1709                 kvm_cpu_vmxon(phys_addr);
1710         else if (vmx->loaded_vmcs->cpu != cpu)
1711                 loaded_vmcs_clear(vmx->loaded_vmcs);
1712
1713         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1714                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1715                 vmcs_load(vmx->loaded_vmcs->vmcs);
1716         }
1717
1718         if (vmx->loaded_vmcs->cpu != cpu) {
1719                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1720                 unsigned long sysenter_esp;
1721
1722                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1723                 local_irq_disable();
1724                 crash_disable_local_vmclear(cpu);
1725
1726                 /*
1727                  * Read loaded_vmcs->cpu should be before fetching
1728                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1729                  * See the comments in __loaded_vmcs_clear().
1730                  */
1731                 smp_rmb();
1732
1733                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1734                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1735                 crash_enable_local_vmclear(cpu);
1736                 local_irq_enable();
1737
1738                 /*
1739                  * Linux uses per-cpu TSS and GDT, so set these when switching
1740                  * processors.
1741                  */
1742                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1743                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1744
1745                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1746                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1747                 vmx->loaded_vmcs->cpu = cpu;
1748         }
1749 }
1750
1751 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1752 {
1753         __vmx_load_host_state(to_vmx(vcpu));
1754         if (!vmm_exclusive) {
1755                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1756                 vcpu->cpu = -1;
1757                 kvm_cpu_vmxoff();
1758         }
1759 }
1760
1761 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1762 {
1763         ulong cr0;
1764
1765         if (vcpu->fpu_active)
1766                 return;
1767         vcpu->fpu_active = 1;
1768         cr0 = vmcs_readl(GUEST_CR0);
1769         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1770         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1771         vmcs_writel(GUEST_CR0, cr0);
1772         update_exception_bitmap(vcpu);
1773         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1774         if (is_guest_mode(vcpu))
1775                 vcpu->arch.cr0_guest_owned_bits &=
1776                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1777         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1778 }
1779
1780 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1781
1782 /*
1783  * Return the cr0 value that a nested guest would read. This is a combination
1784  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1785  * its hypervisor (cr0_read_shadow).
1786  */
1787 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1788 {
1789         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1790                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1791 }
1792 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1793 {
1794         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1795                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1796 }
1797
1798 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1799 {
1800         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1801          * set this *before* calling this function.
1802          */
1803         vmx_decache_cr0_guest_bits(vcpu);
1804         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1805         update_exception_bitmap(vcpu);
1806         vcpu->arch.cr0_guest_owned_bits = 0;
1807         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1808         if (is_guest_mode(vcpu)) {
1809                 /*
1810                  * L1's specified read shadow might not contain the TS bit,
1811                  * so now that we turned on shadowing of this bit, we need to
1812                  * set this bit of the shadow. Like in nested_vmx_run we need
1813                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1814                  * up-to-date here because we just decached cr0.TS (and we'll
1815                  * only update vmcs12->guest_cr0 on nested exit).
1816                  */
1817                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1818                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1819                         (vcpu->arch.cr0 & X86_CR0_TS);
1820                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1821         } else
1822                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1823 }
1824
1825 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1826 {
1827         unsigned long rflags, save_rflags;
1828
1829         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1830                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1831                 rflags = vmcs_readl(GUEST_RFLAGS);
1832                 if (to_vmx(vcpu)->rmode.vm86_active) {
1833                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1834                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1835                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1836                 }
1837                 to_vmx(vcpu)->rflags = rflags;
1838         }
1839         return to_vmx(vcpu)->rflags;
1840 }
1841
1842 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1843 {
1844         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1845         to_vmx(vcpu)->rflags = rflags;
1846         if (to_vmx(vcpu)->rmode.vm86_active) {
1847                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1848                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1849         }
1850         vmcs_writel(GUEST_RFLAGS, rflags);
1851 }
1852
1853 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1854 {
1855         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1856         int ret = 0;
1857
1858         if (interruptibility & GUEST_INTR_STATE_STI)
1859                 ret |= KVM_X86_SHADOW_INT_STI;
1860         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1861                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1862
1863         return ret & mask;
1864 }
1865
1866 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1867 {
1868         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1869         u32 interruptibility = interruptibility_old;
1870
1871         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1872
1873         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1874                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1875         else if (mask & KVM_X86_SHADOW_INT_STI)
1876                 interruptibility |= GUEST_INTR_STATE_STI;
1877
1878         if ((interruptibility != interruptibility_old))
1879                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1880 }
1881
1882 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1883 {
1884         unsigned long rip;
1885
1886         rip = kvm_rip_read(vcpu);
1887         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1888         kvm_rip_write(vcpu, rip);
1889
1890         /* skipping an emulated instruction also counts */
1891         vmx_set_interrupt_shadow(vcpu, 0);
1892 }
1893
1894 /*
1895  * KVM wants to inject page-faults which it got to the guest. This function
1896  * checks whether in a nested guest, we need to inject them to L1 or L2.
1897  * This function assumes it is called with the exit reason in vmcs02 being
1898  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1899  * is running).
1900  */
1901 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1902 {
1903         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1904
1905         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1906         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1907                 return 0;
1908
1909         nested_vmx_vmexit(vcpu);
1910         return 1;
1911 }
1912
1913 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1914                                 bool has_error_code, u32 error_code,
1915                                 bool reinject)
1916 {
1917         struct vcpu_vmx *vmx = to_vmx(vcpu);
1918         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1919
1920         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1921             !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1922                 return;
1923
1924         if (has_error_code) {
1925                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1926                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1927         }
1928
1929         if (vmx->rmode.vm86_active) {
1930                 int inc_eip = 0;
1931                 if (kvm_exception_is_soft(nr))
1932                         inc_eip = vcpu->arch.event_exit_inst_len;
1933                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1934                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1935                 return;
1936         }
1937
1938         if (kvm_exception_is_soft(nr)) {
1939                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1940                              vmx->vcpu.arch.event_exit_inst_len);
1941                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1942         } else
1943                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1944
1945         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1946 }
1947
1948 static bool vmx_rdtscp_supported(void)
1949 {
1950         return cpu_has_vmx_rdtscp();
1951 }
1952
1953 static bool vmx_invpcid_supported(void)
1954 {
1955         return cpu_has_vmx_invpcid() && enable_ept;
1956 }
1957
1958 /*
1959  * Swap MSR entry in host/guest MSR entry array.
1960  */
1961 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1962 {
1963         struct shared_msr_entry tmp;
1964
1965         tmp = vmx->guest_msrs[to];
1966         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1967         vmx->guest_msrs[from] = tmp;
1968 }
1969
1970 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1971 {
1972         unsigned long *msr_bitmap;
1973
1974         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1975                 if (is_long_mode(vcpu))
1976                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1977                 else
1978                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1979         } else {
1980                 if (is_long_mode(vcpu))
1981                         msr_bitmap = vmx_msr_bitmap_longmode;
1982                 else
1983                         msr_bitmap = vmx_msr_bitmap_legacy;
1984         }
1985
1986         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1987 }
1988
1989 /*
1990  * Set up the vmcs to automatically save and restore system
1991  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1992  * mode, as fiddling with msrs is very expensive.
1993  */
1994 static void setup_msrs(struct vcpu_vmx *vmx)
1995 {
1996         int save_nmsrs, index;
1997
1998         save_nmsrs = 0;
1999 #ifdef CONFIG_X86_64
2000         if (is_long_mode(&vmx->vcpu)) {
2001                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2002                 if (index >= 0)
2003                         move_msr_up(vmx, index, save_nmsrs++);
2004                 index = __find_msr_index(vmx, MSR_LSTAR);
2005                 if (index >= 0)
2006                         move_msr_up(vmx, index, save_nmsrs++);
2007                 index = __find_msr_index(vmx, MSR_CSTAR);
2008                 if (index >= 0)
2009                         move_msr_up(vmx, index, save_nmsrs++);
2010                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2011                 if (index >= 0 && vmx->rdtscp_enabled)
2012                         move_msr_up(vmx, index, save_nmsrs++);
2013                 /*
2014                  * MSR_STAR is only needed on long mode guests, and only
2015                  * if efer.sce is enabled.
2016                  */
2017                 index = __find_msr_index(vmx, MSR_STAR);
2018                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2019                         move_msr_up(vmx, index, save_nmsrs++);
2020         }
2021 #endif
2022         index = __find_msr_index(vmx, MSR_EFER);
2023         if (index >= 0 && update_transition_efer(vmx, index))
2024                 move_msr_up(vmx, index, save_nmsrs++);
2025
2026         vmx->save_nmsrs = save_nmsrs;
2027
2028         if (cpu_has_vmx_msr_bitmap())
2029                 vmx_set_msr_bitmap(&vmx->vcpu);
2030 }
2031
2032 /*
2033  * reads and returns guest's timestamp counter "register"
2034  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2035  */
2036 static u64 guest_read_tsc(void)
2037 {
2038         u64 host_tsc, tsc_offset;
2039
2040         rdtscll(host_tsc);
2041         tsc_offset = vmcs_read64(TSC_OFFSET);
2042         return host_tsc + tsc_offset;
2043 }
2044
2045 /*
2046  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2047  * counter, even if a nested guest (L2) is currently running.
2048  */
2049 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2050 {
2051         u64 tsc_offset;
2052
2053         tsc_offset = is_guest_mode(vcpu) ?
2054                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2055                 vmcs_read64(TSC_OFFSET);
2056         return host_tsc + tsc_offset;
2057 }
2058
2059 /*
2060  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2061  * software catchup for faster rates on slower CPUs.
2062  */
2063 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2064 {
2065         if (!scale)
2066                 return;
2067
2068         if (user_tsc_khz > tsc_khz) {
2069                 vcpu->arch.tsc_catchup = 1;
2070                 vcpu->arch.tsc_always_catchup = 1;
2071         } else
2072                 WARN(1, "user requested TSC rate below hardware speed\n");
2073 }
2074
2075 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2076 {
2077         return vmcs_read64(TSC_OFFSET);
2078 }
2079
2080 /*
2081  * writes 'offset' into guest's timestamp counter offset register
2082  */
2083 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2084 {
2085         if (is_guest_mode(vcpu)) {
2086                 /*
2087                  * We're here if L1 chose not to trap WRMSR to TSC. According
2088                  * to the spec, this should set L1's TSC; The offset that L1
2089                  * set for L2 remains unchanged, and still needs to be added
2090                  * to the newly set TSC to get L2's TSC.
2091                  */
2092                 struct vmcs12 *vmcs12;
2093                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2094                 /* recalculate vmcs02.TSC_OFFSET: */
2095                 vmcs12 = get_vmcs12(vcpu);
2096                 vmcs_write64(TSC_OFFSET, offset +
2097                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2098                          vmcs12->tsc_offset : 0));
2099         } else {
2100                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2101                                            vmcs_read64(TSC_OFFSET), offset);
2102                 vmcs_write64(TSC_OFFSET, offset);
2103         }
2104 }
2105
2106 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2107 {
2108         u64 offset = vmcs_read64(TSC_OFFSET);
2109
2110         vmcs_write64(TSC_OFFSET, offset + adjustment);
2111         if (is_guest_mode(vcpu)) {
2112                 /* Even when running L2, the adjustment needs to apply to L1 */
2113                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2114         } else
2115                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2116                                            offset + adjustment);
2117 }
2118
2119 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2120 {
2121         return target_tsc - native_read_tsc();
2122 }
2123
2124 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2125 {
2126         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2127         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2128 }
2129
2130 /*
2131  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2132  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2133  * all guests if the "nested" module option is off, and can also be disabled
2134  * for a single guest by disabling its VMX cpuid bit.
2135  */
2136 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2137 {
2138         return nested && guest_cpuid_has_vmx(vcpu);
2139 }
2140
2141 /*
2142  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2143  * returned for the various VMX controls MSRs when nested VMX is enabled.
2144  * The same values should also be used to verify that vmcs12 control fields are
2145  * valid during nested entry from L1 to L2.
2146  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2147  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2148  * bit in the high half is on if the corresponding bit in the control field
2149  * may be on. See also vmx_control_verify().
2150  * TODO: allow these variables to be modified (downgraded) by module options
2151  * or other means.
2152  */
2153 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2154 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2155 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2156 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2157 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2158 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2159 static __init void nested_vmx_setup_ctls_msrs(void)
2160 {
2161         /*
2162          * Note that as a general rule, the high half of the MSRs (bits in
2163          * the control fields which may be 1) should be initialized by the
2164          * intersection of the underlying hardware's MSR (i.e., features which
2165          * can be supported) and the list of features we want to expose -
2166          * because they are known to be properly supported in our code.
2167          * Also, usually, the low half of the MSRs (bits which must be 1) can
2168          * be set to 0, meaning that L1 may turn off any of these bits. The
2169          * reason is that if one of these bits is necessary, it will appear
2170          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2171          * fields of vmcs01 and vmcs02, will turn these bits off - and
2172          * nested_vmx_exit_handled() will not pass related exits to L1.
2173          * These rules have exceptions below.
2174          */
2175
2176         /* pin-based controls */
2177         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2178               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2179         /*
2180          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2181          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2182          */
2183         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2184         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2185                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2186                 PIN_BASED_VMX_PREEMPTION_TIMER;
2187         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2188
2189         /*
2190          * Exit controls
2191          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2192          * 17 must be 1.
2193          */
2194         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2195         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2196 #ifdef CONFIG_X86_64
2197         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2198 #else
2199         nested_vmx_exit_ctls_high = 0;
2200 #endif
2201         nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2202                                       VM_EXIT_LOAD_IA32_EFER);
2203
2204         /* entry controls */
2205         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2206                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2207         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2208         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2209         nested_vmx_entry_ctls_high &=
2210                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2211         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2212                                        VM_ENTRY_LOAD_IA32_EFER);
2213         /* cpu-based controls */
2214         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2215                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2216         nested_vmx_procbased_ctls_low = 0;
2217         nested_vmx_procbased_ctls_high &=
2218                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2219                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2220                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2221                 CPU_BASED_CR3_STORE_EXITING |
2222 #ifdef CONFIG_X86_64
2223                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2224 #endif
2225                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2226                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2227                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2228                 CPU_BASED_PAUSE_EXITING |
2229                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2230         /*
2231          * We can allow some features even when not supported by the
2232          * hardware. For example, L1 can specify an MSR bitmap - and we
2233          * can use it to avoid exits to L1 - even when L0 runs L2
2234          * without MSR bitmaps.
2235          */
2236         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2237
2238         /* secondary cpu-based controls */
2239         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2240                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2241         nested_vmx_secondary_ctls_low = 0;
2242         nested_vmx_secondary_ctls_high &=
2243                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2244                 SECONDARY_EXEC_WBINVD_EXITING;
2245
2246         /* miscellaneous data */
2247         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2248         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2249                 VMX_MISC_SAVE_EFER_LMA;
2250         nested_vmx_misc_high = 0;
2251 }
2252
2253 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2254 {
2255         /*
2256          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2257          */
2258         return ((control & high) | low) == control;
2259 }
2260
2261 static inline u64 vmx_control_msr(u32 low, u32 high)
2262 {
2263         return low | ((u64)high << 32);
2264 }
2265
2266 /*
2267  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2268  * also let it use VMX-specific MSRs.
2269  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2270  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2271  * like all other MSRs).
2272  */
2273 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2274 {
2275         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2276                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2277                 /*
2278                  * According to the spec, processors which do not support VMX
2279                  * should throw a #GP(0) when VMX capability MSRs are read.
2280                  */
2281                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2282                 return 1;
2283         }
2284
2285         switch (msr_index) {
2286         case MSR_IA32_FEATURE_CONTROL:
2287                 if (nested_vmx_allowed(vcpu)) {
2288                         *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2289                         break;
2290                 }
2291                 return 0;
2292         case MSR_IA32_VMX_BASIC:
2293                 /*
2294                  * This MSR reports some information about VMX support. We
2295                  * should return information about the VMX we emulate for the
2296                  * guest, and the VMCS structure we give it - not about the
2297                  * VMX support of the underlying hardware.
2298                  */
2299                 *pdata = VMCS12_REVISION |
2300                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2301                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2302                 break;
2303         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2304         case MSR_IA32_VMX_PINBASED_CTLS:
2305                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2306                                         nested_vmx_pinbased_ctls_high);
2307                 break;
2308         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2309         case MSR_IA32_VMX_PROCBASED_CTLS:
2310                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2311                                         nested_vmx_procbased_ctls_high);
2312                 break;
2313         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2314         case MSR_IA32_VMX_EXIT_CTLS:
2315                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2316                                         nested_vmx_exit_ctls_high);
2317                 break;
2318         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2319         case MSR_IA32_VMX_ENTRY_CTLS:
2320                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2321                                         nested_vmx_entry_ctls_high);
2322                 break;
2323         case MSR_IA32_VMX_MISC:
2324                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2325                                          nested_vmx_misc_high);
2326                 break;
2327         /*
2328          * These MSRs specify bits which the guest must keep fixed (on or off)
2329          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2330          * We picked the standard core2 setting.
2331          */
2332 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2333 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2334         case MSR_IA32_VMX_CR0_FIXED0:
2335                 *pdata = VMXON_CR0_ALWAYSON;
2336                 break;
2337         case MSR_IA32_VMX_CR0_FIXED1:
2338                 *pdata = -1ULL;
2339                 break;
2340         case MSR_IA32_VMX_CR4_FIXED0:
2341                 *pdata = VMXON_CR4_ALWAYSON;
2342                 break;
2343         case MSR_IA32_VMX_CR4_FIXED1:
2344                 *pdata = -1ULL;
2345                 break;
2346         case MSR_IA32_VMX_VMCS_ENUM:
2347                 *pdata = 0x1f;
2348                 break;
2349         case MSR_IA32_VMX_PROCBASED_CTLS2:
2350                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2351                                         nested_vmx_secondary_ctls_high);
2352                 break;
2353         case MSR_IA32_VMX_EPT_VPID_CAP:
2354                 /* Currently, no nested ept or nested vpid */
2355                 *pdata = 0;
2356                 break;
2357         default:
2358                 return 0;
2359         }
2360
2361         return 1;
2362 }
2363
2364 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2365 {
2366         u32 msr_index = msr_info->index;
2367         u64 data = msr_info->data;
2368         bool host_initialized = msr_info->host_initiated;
2369
2370         if (!nested_vmx_allowed(vcpu))
2371                 return 0;
2372
2373         if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2374                 if (!host_initialized &&
2375                                 to_vmx(vcpu)->nested.msr_ia32_feature_control
2376                                 & FEATURE_CONTROL_LOCKED)
2377                         return 0;
2378                 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
2379                 return 1;
2380         }
2381
2382         /*
2383          * No need to treat VMX capability MSRs specially: If we don't handle
2384          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2385          */
2386         return 0;
2387 }
2388
2389 /*
2390  * Reads an msr value (of 'msr_index') into 'pdata'.
2391  * Returns 0 on success, non-0 otherwise.
2392  * Assumes vcpu_load() was already called.
2393  */
2394 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2395 {
2396         u64 data;
2397         struct shared_msr_entry *msr;
2398
2399         if (!pdata) {
2400                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2401                 return -EINVAL;
2402         }
2403
2404         switch (msr_index) {
2405 #ifdef CONFIG_X86_64
2406         case MSR_FS_BASE:
2407                 data = vmcs_readl(GUEST_FS_BASE);
2408                 break;
2409         case MSR_GS_BASE:
2410                 data = vmcs_readl(GUEST_GS_BASE);
2411                 break;
2412         case MSR_KERNEL_GS_BASE:
2413                 vmx_load_host_state(to_vmx(vcpu));
2414                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2415                 break;
2416 #endif
2417         case MSR_EFER:
2418                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2419         case MSR_IA32_TSC:
2420                 data = guest_read_tsc();
2421                 break;
2422         case MSR_IA32_SYSENTER_CS:
2423                 data = vmcs_read32(GUEST_SYSENTER_CS);
2424                 break;
2425         case MSR_IA32_SYSENTER_EIP:
2426                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2427                 break;
2428         case MSR_IA32_SYSENTER_ESP:
2429                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2430                 break;
2431         case MSR_TSC_AUX:
2432                 if (!to_vmx(vcpu)->rdtscp_enabled)
2433                         return 1;
2434                 /* Otherwise falls through */
2435         default:
2436                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2437                         return 0;
2438                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2439                 if (msr) {
2440                         data = msr->data;
2441                         break;
2442                 }
2443                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2444         }
2445
2446         *pdata = data;
2447         return 0;
2448 }
2449
2450 /*
2451  * Writes msr value into into the appropriate "register".
2452  * Returns 0 on success, non-0 otherwise.
2453  * Assumes vcpu_load() was already called.
2454  */
2455 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2456 {
2457         struct vcpu_vmx *vmx = to_vmx(vcpu);
2458         struct shared_msr_entry *msr;
2459         int ret = 0;
2460         u32 msr_index = msr_info->index;
2461         u64 data = msr_info->data;
2462
2463         switch (msr_index) {
2464         case MSR_EFER:
2465                 ret = kvm_set_msr_common(vcpu, msr_info);
2466                 break;
2467 #ifdef CONFIG_X86_64
2468         case MSR_FS_BASE:
2469                 vmx_segment_cache_clear(vmx);
2470                 vmcs_writel(GUEST_FS_BASE, data);
2471                 break;
2472         case MSR_GS_BASE:
2473                 vmx_segment_cache_clear(vmx);
2474                 vmcs_writel(GUEST_GS_BASE, data);
2475                 break;
2476         case MSR_KERNEL_GS_BASE:
2477                 vmx_load_host_state(vmx);
2478                 vmx->msr_guest_kernel_gs_base = data;
2479                 break;
2480 #endif
2481         case MSR_IA32_SYSENTER_CS:
2482                 vmcs_write32(GUEST_SYSENTER_CS, data);
2483                 break;
2484         case MSR_IA32_SYSENTER_EIP:
2485                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2486                 break;
2487         case MSR_IA32_SYSENTER_ESP:
2488                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2489                 break;
2490         case MSR_IA32_TSC:
2491                 kvm_write_tsc(vcpu, msr_info);
2492                 break;
2493         case MSR_IA32_CR_PAT:
2494                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2495                         vmcs_write64(GUEST_IA32_PAT, data);
2496                         vcpu->arch.pat = data;
2497                         break;
2498                 }
2499                 ret = kvm_set_msr_common(vcpu, msr_info);
2500                 break;
2501         case MSR_IA32_TSC_ADJUST:
2502                 ret = kvm_set_msr_common(vcpu, msr_info);
2503                 break;
2504         case MSR_TSC_AUX:
2505                 if (!vmx->rdtscp_enabled)
2506                         return 1;
2507                 /* Check reserved bit, higher 32 bits should be zero */
2508                 if ((data >> 32) != 0)
2509                         return 1;
2510                 /* Otherwise falls through */
2511         default:
2512                 if (vmx_set_vmx_msr(vcpu, msr_info))
2513                         break;
2514                 msr = find_msr_entry(vmx, msr_index);
2515                 if (msr) {
2516                         msr->data = data;
2517                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2518                                 preempt_disable();
2519                                 kvm_set_shared_msr(msr->index, msr->data,
2520                                                    msr->mask);
2521                                 preempt_enable();
2522                         }
2523                         break;
2524                 }
2525                 ret = kvm_set_msr_common(vcpu, msr_info);
2526         }
2527
2528         return ret;
2529 }
2530
2531 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2532 {
2533         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2534         switch (reg) {
2535         case VCPU_REGS_RSP:
2536                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2537                 break;
2538         case VCPU_REGS_RIP:
2539                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2540                 break;
2541         case VCPU_EXREG_PDPTR:
2542                 if (enable_ept)
2543                         ept_save_pdptrs(vcpu);
2544                 break;
2545         default:
2546                 break;
2547         }
2548 }
2549
2550 static __init int cpu_has_kvm_support(void)
2551 {
2552         return cpu_has_vmx();
2553 }
2554
2555 static __init int vmx_disabled_by_bios(void)
2556 {
2557         u64 msr;
2558
2559         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2560         if (msr & FEATURE_CONTROL_LOCKED) {
2561                 /* launched w/ TXT and VMX disabled */
2562                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2563                         && tboot_enabled())
2564                         return 1;
2565                 /* launched w/o TXT and VMX only enabled w/ TXT */
2566                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2567                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2568                         && !tboot_enabled()) {
2569                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2570                                 "activate TXT before enabling KVM\n");
2571                         return 1;
2572                 }
2573                 /* launched w/o TXT and VMX disabled */
2574                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2575                         && !tboot_enabled())
2576                         return 1;
2577         }
2578
2579         return 0;
2580 }
2581
2582 static void kvm_cpu_vmxon(u64 addr)
2583 {
2584         asm volatile (ASM_VMX_VMXON_RAX
2585                         : : "a"(&addr), "m"(addr)
2586                         : "memory", "cc");
2587 }
2588
2589 static int hardware_enable(void *garbage)
2590 {
2591         int cpu = raw_smp_processor_id();
2592         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2593         u64 old, test_bits;
2594
2595         if (read_cr4() & X86_CR4_VMXE)
2596                 return -EBUSY;
2597
2598         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2599
2600         /*
2601          * Now we can enable the vmclear operation in kdump
2602          * since the loaded_vmcss_on_cpu list on this cpu
2603          * has been initialized.
2604          *
2605          * Though the cpu is not in VMX operation now, there
2606          * is no problem to enable the vmclear operation
2607          * for the loaded_vmcss_on_cpu list is empty!
2608          */
2609         crash_enable_local_vmclear(cpu);
2610
2611         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2612
2613         test_bits = FEATURE_CONTROL_LOCKED;
2614         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2615         if (tboot_enabled())
2616                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2617
2618         if ((old & test_bits) != test_bits) {
2619                 /* enable and lock */
2620                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2621         }
2622         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2623
2624         if (vmm_exclusive) {
2625                 kvm_cpu_vmxon(phys_addr);
2626                 ept_sync_global();
2627         }
2628
2629         native_store_gdt(&__get_cpu_var(host_gdt));
2630
2631         return 0;
2632 }
2633
2634 static void vmclear_local_loaded_vmcss(void)
2635 {
2636         int cpu = raw_smp_processor_id();
2637         struct loaded_vmcs *v, *n;
2638
2639         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2640                                  loaded_vmcss_on_cpu_link)
2641                 __loaded_vmcs_clear(v);
2642 }
2643
2644
2645 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2646  * tricks.
2647  */
2648 static void kvm_cpu_vmxoff(void)
2649 {
2650         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2651 }
2652
2653 static void hardware_disable(void *garbage)
2654 {
2655         if (vmm_exclusive) {
2656                 vmclear_local_loaded_vmcss();
2657                 kvm_cpu_vmxoff();
2658         }
2659         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2660 }
2661
2662 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2663                                       u32 msr, u32 *result)
2664 {
2665         u32 vmx_msr_low, vmx_msr_high;
2666         u32 ctl = ctl_min | ctl_opt;
2667
2668         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2669
2670         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2671         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2672
2673         /* Ensure minimum (required) set of control bits are supported. */
2674         if (ctl_min & ~ctl)
2675                 return -EIO;
2676
2677         *result = ctl;
2678         return 0;
2679 }
2680
2681 static __init bool allow_1_setting(u32 msr, u32 ctl)
2682 {
2683         u32 vmx_msr_low, vmx_msr_high;
2684
2685         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2686         return vmx_msr_high & ctl;
2687 }
2688
2689 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2690 {
2691         u32 vmx_msr_low, vmx_msr_high;
2692         u32 min, opt, min2, opt2;
2693         u32 _pin_based_exec_control = 0;
2694         u32 _cpu_based_exec_control = 0;
2695         u32 _cpu_based_2nd_exec_control = 0;
2696         u32 _vmexit_control = 0;
2697         u32 _vmentry_control = 0;
2698
2699         min = CPU_BASED_HLT_EXITING |
2700 #ifdef CONFIG_X86_64
2701               CPU_BASED_CR8_LOAD_EXITING |
2702               CPU_BASED_CR8_STORE_EXITING |
2703 #endif
2704               CPU_BASED_CR3_LOAD_EXITING |
2705               CPU_BASED_CR3_STORE_EXITING |
2706               CPU_BASED_USE_IO_BITMAPS |
2707               CPU_BASED_MOV_DR_EXITING |
2708               CPU_BASED_USE_TSC_OFFSETING |
2709               CPU_BASED_MWAIT_EXITING |
2710               CPU_BASED_MONITOR_EXITING |
2711               CPU_BASED_INVLPG_EXITING |
2712               CPU_BASED_RDPMC_EXITING;
2713
2714         opt = CPU_BASED_TPR_SHADOW |
2715               CPU_BASED_USE_MSR_BITMAPS |
2716               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2717         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2718                                 &_cpu_based_exec_control) < 0)
2719                 return -EIO;
2720 #ifdef CONFIG_X86_64
2721         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2722                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2723                                            ~CPU_BASED_CR8_STORE_EXITING;
2724 #endif
2725         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2726                 min2 = 0;
2727                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2728                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2729                         SECONDARY_EXEC_WBINVD_EXITING |
2730                         SECONDARY_EXEC_ENABLE_VPID |
2731                         SECONDARY_EXEC_ENABLE_EPT |
2732                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2733                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2734                         SECONDARY_EXEC_RDTSCP |
2735                         SECONDARY_EXEC_ENABLE_INVPCID |
2736                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2737                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2738                         SECONDARY_EXEC_SHADOW_VMCS;
2739                 if (adjust_vmx_controls(min2, opt2,
2740                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2741                                         &_cpu_based_2nd_exec_control) < 0)
2742                         return -EIO;
2743         }
2744 #ifndef CONFIG_X86_64
2745         if (!(_cpu_based_2nd_exec_control &
2746                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2747                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2748 #endif
2749
2750         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2751                 _cpu_based_2nd_exec_control &= ~(
2752                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2753                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2754                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2755
2756         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2757                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2758                    enabled */
2759                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2760                                              CPU_BASED_CR3_STORE_EXITING |
2761                                              CPU_BASED_INVLPG_EXITING);
2762                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2763                       vmx_capability.ept, vmx_capability.vpid);
2764         }
2765
2766         min = 0;
2767 #ifdef CONFIG_X86_64
2768         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2769 #endif
2770         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2771                 VM_EXIT_ACK_INTR_ON_EXIT;
2772         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2773                                 &_vmexit_control) < 0)
2774                 return -EIO;
2775
2776         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2777         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2778         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2779                                 &_pin_based_exec_control) < 0)
2780                 return -EIO;
2781
2782         if (!(_cpu_based_2nd_exec_control &
2783                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2784                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2785                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2786
2787         min = 0;
2788         opt = VM_ENTRY_LOAD_IA32_PAT;
2789         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2790                                 &_vmentry_control) < 0)
2791                 return -EIO;
2792
2793         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2794
2795         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2796         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2797                 return -EIO;
2798
2799 #ifdef CONFIG_X86_64
2800         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2801         if (vmx_msr_high & (1u<<16))
2802                 return -EIO;
2803 #endif
2804
2805         /* Require Write-Back (WB) memory type for VMCS accesses. */
2806         if (((vmx_msr_high >> 18) & 15) != 6)
2807                 return -EIO;
2808
2809         vmcs_conf->size = vmx_msr_high & 0x1fff;
2810         vmcs_conf->order = get_order(vmcs_config.size);
2811         vmcs_conf->revision_id = vmx_msr_low;
2812
2813         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2814         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2815         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2816         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2817         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2818
2819         cpu_has_load_ia32_efer =
2820                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2821                                 VM_ENTRY_LOAD_IA32_EFER)
2822                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2823                                    VM_EXIT_LOAD_IA32_EFER);
2824
2825         cpu_has_load_perf_global_ctrl =
2826                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2827                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2828                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2829                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2830
2831         /*
2832          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2833          * but due to arrata below it can't be used. Workaround is to use
2834          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2835          *
2836          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2837          *
2838          * AAK155             (model 26)
2839          * AAP115             (model 30)
2840          * AAT100             (model 37)
2841          * BC86,AAY89,BD102   (model 44)
2842          * BA97               (model 46)
2843          *
2844          */
2845         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2846                 switch (boot_cpu_data.x86_model) {
2847                 case 26:
2848                 case 30:
2849                 case 37:
2850                 case 44:
2851                 case 46:
2852                         cpu_has_load_perf_global_ctrl = false;
2853                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2854                                         "does not work properly. Using workaround\n");
2855                         break;
2856                 default:
2857                         break;
2858                 }
2859         }
2860
2861         return 0;
2862 }
2863
2864 static struct vmcs *alloc_vmcs_cpu(int cpu)
2865 {
2866         int node = cpu_to_node(cpu);
2867         struct page *pages;
2868         struct vmcs *vmcs;
2869
2870         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2871         if (!pages)
2872                 return NULL;
2873         vmcs = page_address(pages);
2874         memset(vmcs, 0, vmcs_config.size);
2875         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2876         return vmcs;
2877 }
2878
2879 static struct vmcs *alloc_vmcs(void)
2880 {
2881         return alloc_vmcs_cpu(raw_smp_processor_id());
2882 }
2883
2884 static void free_vmcs(struct vmcs *vmcs)
2885 {
2886         free_pages((unsigned long)vmcs, vmcs_config.order);
2887 }
2888
2889 /*
2890  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2891  */
2892 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2893 {
2894         if (!loaded_vmcs->vmcs)
2895                 return;
2896         loaded_vmcs_clear(loaded_vmcs);
2897         free_vmcs(loaded_vmcs->vmcs);
2898         loaded_vmcs->vmcs = NULL;
2899 }
2900
2901 static void free_kvm_area(void)
2902 {
2903         int cpu;
2904
2905         for_each_possible_cpu(cpu) {
2906                 free_vmcs(per_cpu(vmxarea, cpu));
2907                 per_cpu(vmxarea, cpu) = NULL;
2908         }
2909 }
2910
2911 static __init int alloc_kvm_area(void)
2912 {
2913         int cpu;
2914
2915         for_each_possible_cpu(cpu) {
2916                 struct vmcs *vmcs;
2917
2918                 vmcs = alloc_vmcs_cpu(cpu);
2919                 if (!vmcs) {
2920                         free_kvm_area();
2921                         return -ENOMEM;
2922                 }
2923
2924                 per_cpu(vmxarea, cpu) = vmcs;
2925         }
2926         return 0;
2927 }
2928
2929 static __init int hardware_setup(void)
2930 {
2931         if (setup_vmcs_config(&vmcs_config) < 0)
2932                 return -EIO;
2933
2934         if (boot_cpu_has(X86_FEATURE_NX))
2935                 kvm_enable_efer_bits(EFER_NX);
2936
2937         if (!cpu_has_vmx_vpid())
2938                 enable_vpid = 0;
2939         if (!cpu_has_vmx_shadow_vmcs())
2940                 enable_shadow_vmcs = 0;
2941
2942         if (!cpu_has_vmx_ept() ||
2943             !cpu_has_vmx_ept_4levels()) {
2944                 enable_ept = 0;
2945                 enable_unrestricted_guest = 0;
2946                 enable_ept_ad_bits = 0;
2947         }
2948
2949         if (!cpu_has_vmx_ept_ad_bits())
2950                 enable_ept_ad_bits = 0;
2951
2952         if (!cpu_has_vmx_unrestricted_guest())
2953                 enable_unrestricted_guest = 0;
2954
2955         if (!cpu_has_vmx_flexpriority())
2956                 flexpriority_enabled = 0;
2957
2958         if (!cpu_has_vmx_tpr_shadow())
2959                 kvm_x86_ops->update_cr8_intercept = NULL;
2960
2961         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2962                 kvm_disable_largepages();
2963
2964         if (!cpu_has_vmx_ple())
2965                 ple_gap = 0;
2966
2967         if (!cpu_has_vmx_apicv())
2968                 enable_apicv = 0;
2969
2970         if (enable_apicv)
2971                 kvm_x86_ops->update_cr8_intercept = NULL;
2972         else {
2973                 kvm_x86_ops->hwapic_irr_update = NULL;
2974                 kvm_x86_ops->deliver_posted_interrupt = NULL;
2975                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2976         }
2977
2978         if (nested)
2979                 nested_vmx_setup_ctls_msrs();
2980
2981         return alloc_kvm_area();
2982 }
2983
2984 static __exit void hardware_unsetup(void)
2985 {
2986         free_kvm_area();
2987 }
2988
2989 static bool emulation_required(struct kvm_vcpu *vcpu)
2990 {
2991         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2992 }
2993
2994 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2995                 struct kvm_segment *save)
2996 {
2997         if (!emulate_invalid_guest_state) {
2998                 /*
2999                  * CS and SS RPL should be equal during guest entry according
3000                  * to VMX spec, but in reality it is not always so. Since vcpu
3001                  * is in the middle of the transition from real mode to
3002                  * protected mode it is safe to assume that RPL 0 is a good
3003                  * default value.
3004                  */
3005                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3006                         save->selector &= ~SELECTOR_RPL_MASK;
3007                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3008                 save->s = 1;
3009         }
3010         vmx_set_segment(vcpu, save, seg);
3011 }
3012
3013 static void enter_pmode(struct kvm_vcpu *vcpu)
3014 {
3015         unsigned long flags;
3016         struct vcpu_vmx *vmx = to_vmx(vcpu);
3017
3018         /*
3019          * Update real mode segment cache. It may be not up-to-date if sement
3020          * register was written while vcpu was in a guest mode.
3021          */
3022         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3023         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3024         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3025         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3026         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3027         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3028
3029         vmx->rmode.vm86_active = 0;
3030
3031         vmx_segment_cache_clear(vmx);
3032
3033         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3034
3035         flags = vmcs_readl(GUEST_RFLAGS);
3036         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3037         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3038         vmcs_writel(GUEST_RFLAGS, flags);
3039
3040         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3041                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3042
3043         update_exception_bitmap(vcpu);
3044
3045         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3046         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3047         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3048         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3049         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3050         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3051
3052         /* CPL is always 0 when CPU enters protected mode */
3053         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3054         vmx->cpl = 0;
3055 }
3056
3057 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3058 {
3059         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3060         struct kvm_segment var = *save;
3061
3062         var.dpl = 0x3;
3063         if (seg == VCPU_SREG_CS)
3064                 var.type = 0x3;
3065
3066         if (!emulate_invalid_guest_state) {
3067                 var.selector = var.base >> 4;
3068                 var.base = var.base & 0xffff0;
3069                 var.limit = 0xffff;
3070                 var.g = 0;
3071                 var.db = 0;
3072                 var.present = 1;
3073                 var.s = 1;
3074                 var.l = 0;
3075                 var.unusable = 0;
3076                 var.type = 0x3;
3077                 var.avl = 0;
3078                 if (save->base & 0xf)
3079                         printk_once(KERN_WARNING "kvm: segment base is not "
3080                                         "paragraph aligned when entering "
3081                                         "protected mode (seg=%d)", seg);
3082         }
3083
3084         vmcs_write16(sf->selector, var.selector);
3085         vmcs_write32(sf->base, var.base);
3086         vmcs_write32(sf->limit, var.limit);
3087         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3088 }
3089
3090 static void enter_rmode(struct kvm_vcpu *vcpu)
3091 {
3092         unsigned long flags;
3093         struct vcpu_vmx *vmx = to_vmx(vcpu);
3094
3095         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3096         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3097         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3098         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3099         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3100         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3101         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3102
3103         vmx->rmode.vm86_active = 1;
3104
3105         /*
3106          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3107          * vcpu. Warn the user that an update is overdue.
3108          */
3109         if (!vcpu->kvm->arch.tss_addr)
3110                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3111                              "called before entering vcpu\n");
3112
3113         vmx_segment_cache_clear(vmx);
3114
3115         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3116         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3117         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3118
3119         flags = vmcs_readl(GUEST_RFLAGS);
3120         vmx->rmode.save_rflags = flags;
3121
3122         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3123
3124         vmcs_writel(GUEST_RFLAGS, flags);
3125         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3126         update_exception_bitmap(vcpu);
3127
3128         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3129         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3130         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3131         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3132         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3133         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3134
3135         kvm_mmu_reset_context(vcpu);
3136 }
3137
3138 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3139 {
3140         struct vcpu_vmx *vmx = to_vmx(vcpu);
3141         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3142
3143         if (!msr)
3144                 return;
3145
3146         /*
3147          * Force kernel_gs_base reloading before EFER changes, as control
3148          * of this msr depends on is_long_mode().
3149          */
3150         vmx_load_host_state(to_vmx(vcpu));
3151         vcpu->arch.efer = efer;
3152         if (efer & EFER_LMA) {
3153                 vmcs_write32(VM_ENTRY_CONTROLS,
3154                              vmcs_read32(VM_ENTRY_CONTROLS) |
3155                              VM_ENTRY_IA32E_MODE);
3156                 msr->data = efer;
3157         } else {
3158                 vmcs_write32(VM_ENTRY_CONTROLS,
3159                              vmcs_read32(VM_ENTRY_CONTROLS) &
3160                              ~VM_ENTRY_IA32E_MODE);
3161
3162                 msr->data = efer & ~EFER_LME;
3163         }
3164         setup_msrs(vmx);
3165 }
3166
3167 #ifdef CONFIG_X86_64
3168
3169 static void enter_lmode(struct kvm_vcpu *vcpu)
3170 {
3171         u32 guest_tr_ar;
3172
3173         vmx_segment_cache_clear(to_vmx(vcpu));
3174
3175         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3176         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3177                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3178                                      __func__);
3179                 vmcs_write32(GUEST_TR_AR_BYTES,
3180                              (guest_tr_ar & ~AR_TYPE_MASK)
3181                              | AR_TYPE_BUSY_64_TSS);
3182         }
3183         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3184 }
3185
3186 static void exit_lmode(struct kvm_vcpu *vcpu)
3187 {
3188         vmcs_write32(VM_ENTRY_CONTROLS,
3189                      vmcs_read32(VM_ENTRY_CONTROLS)
3190                      & ~VM_ENTRY_IA32E_MODE);
3191         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3192 }
3193
3194 #endif
3195
3196 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3197 {
3198         vpid_sync_context(to_vmx(vcpu));
3199         if (enable_ept) {
3200                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3201                         return;
3202                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3203         }
3204 }
3205
3206 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3207 {
3208         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3209
3210         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3211         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3212 }
3213
3214 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3215 {
3216         if (enable_ept && is_paging(vcpu))
3217                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3218         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3219 }
3220
3221 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3222 {
3223         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3224
3225         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3226         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3227 }
3228
3229 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3230 {
3231         if (!test_bit(VCPU_EXREG_PDPTR,
3232                       (unsigned long *)&vcpu->arch.regs_dirty))
3233                 return;
3234
3235         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3236                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3237                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3238                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3239                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3240         }
3241 }
3242
3243 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3244 {
3245         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3246                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3247                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3248                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3249                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3250         }
3251
3252         __set_bit(VCPU_EXREG_PDPTR,
3253                   (unsigned long *)&vcpu->arch.regs_avail);
3254         __set_bit(VCPU_EXREG_PDPTR,
3255                   (unsigned long *)&vcpu->arch.regs_dirty);
3256 }
3257
3258 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3259
3260 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3261                                         unsigned long cr0,
3262                                         struct kvm_vcpu *vcpu)
3263 {
3264         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3265                 vmx_decache_cr3(vcpu);
3266         if (!(cr0 & X86_CR0_PG)) {
3267                 /* From paging/starting to nonpaging */
3268                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3269                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3270                              (CPU_BASED_CR3_LOAD_EXITING |
3271                               CPU_BASED_CR3_STORE_EXITING));
3272                 vcpu->arch.cr0 = cr0;
3273                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3274         } else if (!is_paging(vcpu)) {
3275                 /* From nonpaging to paging */
3276                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3277                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3278                              ~(CPU_BASED_CR3_LOAD_EXITING |
3279                                CPU_BASED_CR3_STORE_EXITING));
3280                 vcpu->arch.cr0 = cr0;
3281                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3282         }
3283
3284         if (!(cr0 & X86_CR0_WP))
3285                 *hw_cr0 &= ~X86_CR0_WP;
3286 }
3287
3288 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3289 {
3290         struct vcpu_vmx *vmx = to_vmx(vcpu);
3291         unsigned long hw_cr0;
3292
3293         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3294         if (enable_unrestricted_guest)
3295                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3296         else {
3297                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3298
3299                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3300                         enter_pmode(vcpu);
3301
3302                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3303                         enter_rmode(vcpu);
3304         }
3305
3306 #ifdef CONFIG_X86_64
3307         if (vcpu->arch.efer & EFER_LME) {
3308                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3309                         enter_lmode(vcpu);
3310                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3311                         exit_lmode(vcpu);
3312         }
3313 #endif
3314
3315         if (enable_ept)
3316                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3317
3318         if (!vcpu->fpu_active)
3319                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3320
3321         vmcs_writel(CR0_READ_SHADOW, cr0);
3322         vmcs_writel(GUEST_CR0, hw_cr0);
3323         vcpu->arch.cr0 = cr0;
3324
3325         /* depends on vcpu->arch.cr0 to be set to a new value */
3326         vmx->emulation_required = emulation_required(vcpu);
3327 }
3328
3329 static u64 construct_eptp(unsigned long root_hpa)
3330 {
3331         u64 eptp;
3332
3333         /* TODO write the value reading from MSR */
3334         eptp = VMX_EPT_DEFAULT_MT |
3335                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3336         if (enable_ept_ad_bits)
3337                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3338         eptp |= (root_hpa & PAGE_MASK);
3339
3340         return eptp;
3341 }
3342
3343 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3344 {
3345         unsigned long guest_cr3;
3346         u64 eptp;
3347
3348         guest_cr3 = cr3;
3349         if (enable_ept) {
3350                 eptp = construct_eptp(cr3);
3351                 vmcs_write64(EPT_POINTER, eptp);
3352                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3353                         vcpu->kvm->arch.ept_identity_map_addr;
3354                 ept_load_pdptrs(vcpu);
3355         }
3356
3357         vmx_flush_tlb(vcpu);
3358         vmcs_writel(GUEST_CR3, guest_cr3);
3359 }
3360
3361 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3362 {
3363         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3364                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3365
3366         if (cr4 & X86_CR4_VMXE) {
3367                 /*
3368                  * To use VMXON (and later other VMX instructions), a guest
3369                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3370                  * So basically the check on whether to allow nested VMX
3371                  * is here.
3372                  */
3373                 if (!nested_vmx_allowed(vcpu))
3374                         return 1;
3375         }
3376         if (to_vmx(vcpu)->nested.vmxon &&
3377             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3378                 return 1;
3379
3380         vcpu->arch.cr4 = cr4;
3381         if (enable_ept) {
3382                 if (!is_paging(vcpu)) {
3383                         hw_cr4 &= ~X86_CR4_PAE;
3384                         hw_cr4 |= X86_CR4_PSE;
3385                         /*
3386                          * SMEP is disabled if CPU is in non-paging mode in
3387                          * hardware. However KVM always uses paging mode to
3388                          * emulate guest non-paging mode with TDP.
3389                          * To emulate this behavior, SMEP needs to be manually
3390                          * disabled when guest switches to non-paging mode.
3391                          */
3392                         hw_cr4 &= ~X86_CR4_SMEP;
3393                 } else if (!(cr4 & X86_CR4_PAE)) {
3394                         hw_cr4 &= ~X86_CR4_PAE;
3395                 }
3396         }
3397
3398         vmcs_writel(CR4_READ_SHADOW, cr4);
3399         vmcs_writel(GUEST_CR4, hw_cr4);
3400         return 0;
3401 }
3402
3403 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3404                             struct kvm_segment *var, int seg)
3405 {
3406         struct vcpu_vmx *vmx = to_vmx(vcpu);
3407         u32 ar;
3408
3409         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3410                 *var = vmx->rmode.segs[seg];
3411                 if (seg == VCPU_SREG_TR
3412                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3413                         return;
3414                 var->base = vmx_read_guest_seg_base(vmx, seg);
3415                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3416                 return;
3417         }
3418         var->base = vmx_read_guest_seg_base(vmx, seg);
3419         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3420         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3421         ar = vmx_read_guest_seg_ar(vmx, seg);
3422         var->unusable = (ar >> 16) & 1;
3423         var->type = ar & 15;
3424         var->s = (ar >> 4) & 1;
3425         var->dpl = (ar >> 5) & 3;
3426         /*
3427          * Some userspaces do not preserve unusable property. Since usable
3428          * segment has to be present according to VMX spec we can use present
3429          * property to amend userspace bug by making unusable segment always
3430          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3431          * segment as unusable.
3432          */
3433         var->present = !var->unusable;
3434         var->avl = (ar >> 12) & 1;
3435         var->l = (ar >> 13) & 1;
3436         var->db = (ar >> 14) & 1;
3437         var->g = (ar >> 15) & 1;
3438 }
3439
3440 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3441 {
3442         struct kvm_segment s;
3443
3444         if (to_vmx(vcpu)->rmode.vm86_active) {
3445                 vmx_get_segment(vcpu, &s, seg);
3446                 return s.base;
3447         }
3448         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3449 }
3450
3451 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3452 {
3453         struct vcpu_vmx *vmx = to_vmx(vcpu);
3454
3455         if (!is_protmode(vcpu))
3456                 return 0;
3457
3458         if (!is_long_mode(vcpu)
3459             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3460                 return 3;
3461
3462         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3463                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3464                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3465         }
3466
3467         return vmx->cpl;
3468 }
3469
3470
3471 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3472 {
3473         u32 ar;
3474
3475         if (var->unusable || !var->present)
3476                 ar = 1 << 16;
3477         else {
3478                 ar = var->type & 15;
3479                 ar |= (var->s & 1) << 4;
3480                 ar |= (var->dpl & 3) << 5;
3481                 ar |= (var->present & 1) << 7;
3482                 ar |= (var->avl & 1) << 12;
3483                 ar |= (var->l & 1) << 13;
3484                 ar |= (var->db & 1) << 14;
3485                 ar |= (var->g & 1) << 15;
3486         }
3487
3488         return ar;
3489 }
3490
3491 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3492                             struct kvm_segment *var, int seg)
3493 {
3494         struct vcpu_vmx *vmx = to_vmx(vcpu);
3495         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3496
3497         vmx_segment_cache_clear(vmx);
3498         if (seg == VCPU_SREG_CS)
3499                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3500
3501         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3502                 vmx->rmode.segs[seg] = *var;
3503                 if (seg == VCPU_SREG_TR)
3504                         vmcs_write16(sf->selector, var->selector);
3505                 else if (var->s)
3506                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3507                 goto out;
3508         }
3509
3510         vmcs_writel(sf->base, var->base);
3511         vmcs_write32(sf->limit, var->limit);
3512         vmcs_write16(sf->selector, var->selector);
3513
3514         /*
3515          *   Fix the "Accessed" bit in AR field of segment registers for older
3516          * qemu binaries.
3517          *   IA32 arch specifies that at the time of processor reset the
3518          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3519          * is setting it to 0 in the userland code. This causes invalid guest
3520          * state vmexit when "unrestricted guest" mode is turned on.
3521          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3522          * tree. Newer qemu binaries with that qemu fix would not need this
3523          * kvm hack.
3524          */
3525         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3526                 var->type |= 0x1; /* Accessed */
3527
3528         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3529
3530 out:
3531         vmx->emulation_required |= emulation_required(vcpu);
3532 }
3533
3534 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3535 {
3536         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3537
3538         *db = (ar >> 14) & 1;
3539         *l = (ar >> 13) & 1;
3540 }
3541
3542 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3543 {
3544         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3545         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3546 }
3547
3548 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3549 {
3550         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3551         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3552 }
3553
3554 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3555 {
3556         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3557         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3558 }
3559
3560 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3561 {
3562         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3563         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3564 }
3565
3566 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3567 {
3568         struct kvm_segment var;
3569         u32 ar;
3570
3571         vmx_get_segment(vcpu, &var, seg);
3572         var.dpl = 0x3;
3573         if (seg == VCPU_SREG_CS)
3574                 var.type = 0x3;
3575         ar = vmx_segment_access_rights(&var);
3576
3577         if (var.base != (var.selector << 4))
3578                 return false;
3579         if (var.limit != 0xffff)
3580                 return false;
3581         if (ar != 0xf3)
3582                 return false;
3583
3584         return true;
3585 }
3586
3587 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3588 {
3589         struct kvm_segment cs;
3590         unsigned int cs_rpl;
3591
3592         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3593         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3594
3595         if (cs.unusable)
3596                 return false;
3597         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3598                 return false;
3599         if (!cs.s)
3600                 return false;
3601         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3602                 if (cs.dpl > cs_rpl)
3603                         return false;
3604         } else {
3605                 if (cs.dpl != cs_rpl)
3606                         return false;
3607         }
3608         if (!cs.present)
3609                 return false;
3610
3611         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3612         return true;
3613 }
3614
3615 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3616 {
3617         struct kvm_segment ss;
3618         unsigned int ss_rpl;
3619
3620         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3621         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3622
3623         if (ss.unusable)
3624                 return true;
3625         if (ss.type != 3 && ss.type != 7)
3626                 return false;
3627         if (!ss.s)
3628                 return false;
3629         if (ss.dpl != ss_rpl) /* DPL != RPL */
3630                 return false;
3631         if (!ss.present)
3632                 return false;
3633
3634         return true;
3635 }
3636
3637 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3638 {
3639         struct kvm_segment var;
3640         unsigned int rpl;
3641
3642         vmx_get_segment(vcpu, &var, seg);
3643         rpl = var.selector & SELECTOR_RPL_MASK;
3644
3645         if (var.unusable)
3646                 return true;
3647         if (!var.s)
3648                 return false;
3649         if (!var.present)
3650                 return false;
3651         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3652                 if (var.dpl < rpl) /* DPL < RPL */
3653                         return false;
3654         }
3655
3656         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3657          * rights flags
3658          */
3659         return true;
3660 }
3661
3662 static bool tr_valid(struct kvm_vcpu *vcpu)
3663 {
3664         struct kvm_segment tr;
3665
3666         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3667
3668         if (tr.unusable)
3669                 return false;
3670         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3671                 return false;
3672         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3673                 return false;
3674         if (!tr.present)
3675                 return false;
3676
3677         return true;
3678 }
3679
3680 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3681 {
3682         struct kvm_segment ldtr;
3683
3684         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3685
3686         if (ldtr.unusable)
3687                 return true;
3688         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3689                 return false;
3690         if (ldtr.type != 2)
3691                 return false;
3692         if (!ldtr.present)
3693                 return false;
3694
3695         return true;
3696 }
3697
3698 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3699 {
3700         struct kvm_segment cs, ss;
3701
3702         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3703         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3704
3705         return ((cs.selector & SELECTOR_RPL_MASK) ==
3706                  (ss.selector & SELECTOR_RPL_MASK));
3707 }
3708
3709 /*
3710  * Check if guest state is valid. Returns true if valid, false if
3711  * not.
3712  * We assume that registers are always usable
3713  */
3714 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3715 {
3716         if (enable_unrestricted_guest)
3717                 return true;
3718
3719         /* real mode guest state checks */
3720         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3721                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3722                         return false;
3723                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3724                         return false;
3725                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3726                         return false;
3727                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3728                         return false;
3729                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3730                         return false;
3731                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3732                         return false;
3733         } else {
3734         /* protected mode guest state checks */
3735                 if (!cs_ss_rpl_check(vcpu))
3736                         return false;
3737                 if (!code_segment_valid(vcpu))
3738                         return false;
3739                 if (!stack_segment_valid(vcpu))
3740                         return false;
3741                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3742                         return false;
3743                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3744                         return false;
3745                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3746                         return false;
3747                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3748                         return false;
3749                 if (!tr_valid(vcpu))
3750                         return false;
3751                 if (!ldtr_valid(vcpu))
3752                         return false;
3753         }
3754         /* TODO:
3755          * - Add checks on RIP
3756          * - Add checks on RFLAGS
3757          */
3758
3759         return true;
3760 }
3761
3762 static int init_rmode_tss(struct kvm *kvm)
3763 {
3764         gfn_t fn;
3765         u16 data = 0;
3766         int r, idx, ret = 0;
3767
3768         idx = srcu_read_lock(&kvm->srcu);
3769         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3770         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3771         if (r < 0)
3772                 goto out;
3773         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3774         r = kvm_write_guest_page(kvm, fn++, &data,
3775                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3776         if (r < 0)
3777                 goto out;
3778         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3779         if (r < 0)
3780                 goto out;
3781         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3782         if (r < 0)
3783                 goto out;
3784         data = ~0;
3785         r = kvm_write_guest_page(kvm, fn, &data,
3786                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3787                                  sizeof(u8));
3788         if (r < 0)
3789                 goto out;
3790
3791         ret = 1;
3792 out:
3793         srcu_read_unlock(&kvm->srcu, idx);
3794         return ret;
3795 }
3796
3797 static int init_rmode_identity_map(struct kvm *kvm)
3798 {
3799         int i, idx, r, ret;
3800         pfn_t identity_map_pfn;
3801         u32 tmp;
3802
3803         if (!enable_ept)
3804                 return 1;
3805         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3806                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3807                         "haven't been allocated!\n");
3808                 return 0;
3809         }
3810         if (likely(kvm->arch.ept_identity_pagetable_done))
3811                 return 1;
3812         ret = 0;
3813         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3814         idx = srcu_read_lock(&kvm->srcu);
3815         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3816         if (r < 0)
3817                 goto out;
3818         /* Set up identity-mapping pagetable for EPT in real mode */
3819         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3820                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3821                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3822                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3823                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3824                 if (r < 0)
3825                         goto out;
3826         }
3827         kvm->arch.ept_identity_pagetable_done = true;
3828         ret = 1;
3829 out:
3830         srcu_read_unlock(&kvm->srcu, idx);
3831         return ret;
3832 }
3833
3834 static void seg_setup(int seg)
3835 {
3836         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3837         unsigned int ar;
3838
3839         vmcs_write16(sf->selector, 0);
3840         vmcs_writel(sf->base, 0);
3841         vmcs_write32(sf->limit, 0xffff);
3842         ar = 0x93;
3843         if (seg == VCPU_SREG_CS)
3844                 ar |= 0x08; /* code segment */
3845
3846         vmcs_write32(sf->ar_bytes, ar);
3847 }
3848
3849 static int alloc_apic_access_page(struct kvm *kvm)
3850 {
3851         struct page *page;
3852         struct kvm_userspace_memory_region kvm_userspace_mem;
3853         int r = 0;
3854
3855         mutex_lock(&kvm->slots_lock);
3856         if (kvm->arch.apic_access_page)
3857                 goto out;
3858         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3859         kvm_userspace_mem.flags = 0;
3860         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3861         kvm_userspace_mem.memory_size = PAGE_SIZE;
3862         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3863         if (r)
3864                 goto out;
3865
3866         page = gfn_to_page(kvm, 0xfee00);
3867         if (is_error_page(page)) {
3868                 r = -EFAULT;
3869                 goto out;
3870         }
3871
3872         kvm->arch.apic_access_page = page;
3873 out:
3874         mutex_unlock(&kvm->slots_lock);
3875         return r;
3876 }
3877
3878 static int alloc_identity_pagetable(struct kvm *kvm)
3879 {
3880         struct page *page;
3881         struct kvm_userspace_memory_region kvm_userspace_mem;
3882         int r = 0;
3883
3884         mutex_lock(&kvm->slots_lock);
3885         if (kvm->arch.ept_identity_pagetable)
3886                 goto out;
3887         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3888         kvm_userspace_mem.flags = 0;
3889         kvm_userspace_mem.guest_phys_addr =
3890                 kvm->arch.ept_identity_map_addr;
3891         kvm_userspace_mem.memory_size = PAGE_SIZE;
3892         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3893         if (r)
3894                 goto out;
3895
3896         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3897         if (is_error_page(page)) {
3898                 r = -EFAULT;
3899                 goto out;
3900         }
3901
3902         kvm->arch.ept_identity_pagetable = page;
3903 out:
3904         mutex_unlock(&kvm->slots_lock);
3905         return r;
3906 }
3907
3908 static void allocate_vpid(struct vcpu_vmx *vmx)
3909 {
3910         int vpid;
3911
3912         vmx->vpid = 0;
3913         if (!enable_vpid)
3914                 return;
3915         spin_lock(&vmx_vpid_lock);
3916         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3917         if (vpid < VMX_NR_VPIDS) {
3918                 vmx->vpid = vpid;
3919                 __set_bit(vpid, vmx_vpid_bitmap);
3920         }
3921         spin_unlock(&vmx_vpid_lock);
3922 }
3923
3924 static void free_vpid(struct vcpu_vmx *vmx)
3925 {
3926         if (!enable_vpid)
3927                 return;
3928         spin_lock(&vmx_vpid_lock);
3929         if (vmx->vpid != 0)
3930                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3931         spin_unlock(&vmx_vpid_lock);
3932 }
3933
3934 #define MSR_TYPE_R      1
3935 #define MSR_TYPE_W      2
3936 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3937                                                 u32 msr, int type)
3938 {
3939         int f = sizeof(unsigned long);
3940
3941         if (!cpu_has_vmx_msr_bitmap())
3942                 return;
3943
3944         /*
3945          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3946          * have the write-low and read-high bitmap offsets the wrong way round.
3947          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3948          */
3949         if (msr <= 0x1fff) {
3950                 if (type & MSR_TYPE_R)
3951                         /* read-low */
3952                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3953
3954                 if (type & MSR_TYPE_W)
3955                         /* write-low */
3956                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3957
3958         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3959                 msr &= 0x1fff;
3960                 if (type & MSR_TYPE_R)
3961                         /* read-high */
3962                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3963
3964                 if (type & MSR_TYPE_W)
3965                         /* write-high */
3966                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3967
3968         }
3969 }
3970
3971 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3972                                                 u32 msr, int type)
3973 {
3974         int f = sizeof(unsigned long);
3975
3976         if (!cpu_has_vmx_msr_bitmap())
3977                 return;
3978
3979         /*
3980          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3981          * have the write-low and read-high bitmap offsets the wrong way round.
3982          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3983          */
3984         if (msr <= 0x1fff) {
3985                 if (type & MSR_TYPE_R)
3986                         /* read-low */
3987                         __set_bit(msr, msr_bitmap + 0x000 / f);
3988
3989                 if (type & MSR_TYPE_W)
3990                         /* write-low */
3991                         __set_bit(msr, msr_bitmap + 0x800 / f);
3992
3993         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3994                 msr &= 0x1fff;
3995                 if (type & MSR_TYPE_R)
3996                         /* read-high */
3997                         __set_bit(msr, msr_bitmap + 0x400 / f);
3998
3999                 if (type & MSR_TYPE_W)
4000                         /* write-high */
4001                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4002
4003         }
4004 }
4005
4006 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4007 {
4008         if (!longmode_only)
4009                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4010                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4011         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4012                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4013 }
4014
4015 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4016 {
4017         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4018                         msr, MSR_TYPE_R);
4019         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4020                         msr, MSR_TYPE_R);
4021 }
4022
4023 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4024 {
4025         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4026                         msr, MSR_TYPE_R);
4027         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4028                         msr, MSR_TYPE_R);
4029 }
4030
4031 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4032 {
4033         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4034                         msr, MSR_TYPE_W);
4035         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4036                         msr, MSR_TYPE_W);
4037 }
4038
4039 static int vmx_vm_has_apicv(struct kvm *kvm)
4040 {
4041         return enable_apicv && irqchip_in_kernel(kvm);
4042 }
4043
4044 /*
4045  * Send interrupt to vcpu via posted interrupt way.
4046  * 1. If target vcpu is running(non-root mode), send posted interrupt
4047  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4048  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4049  * interrupt from PIR in next vmentry.
4050  */
4051 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4052 {
4053         struct vcpu_vmx *vmx = to_vmx(vcpu);
4054         int r;
4055
4056         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4057                 return;
4058
4059         r = pi_test_and_set_on(&vmx->pi_desc);
4060         kvm_make_request(KVM_REQ_EVENT, vcpu);
4061 #ifdef CONFIG_SMP
4062         if (!r && (vcpu->mode == IN_GUEST_MODE))
4063                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4064                                 POSTED_INTR_VECTOR);
4065         else
4066 #endif
4067                 kvm_vcpu_kick(vcpu);
4068 }
4069
4070 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4071 {
4072         struct vcpu_vmx *vmx = to_vmx(vcpu);
4073
4074         if (!pi_test_and_clear_on(&vmx->pi_desc))
4075                 return;
4076
4077         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4078 }
4079
4080 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4081 {
4082         return;
4083 }
4084
4085 /*
4086  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4087  * will not change in the lifetime of the guest.
4088  * Note that host-state that does change is set elsewhere. E.g., host-state
4089  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4090  */
4091 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4092 {
4093         u32 low32, high32;
4094         unsigned long tmpl;
4095         struct desc_ptr dt;
4096
4097         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4098         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4099         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4100
4101         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4102 #ifdef CONFIG_X86_64
4103         /*
4104          * Load null selectors, so we can avoid reloading them in
4105          * __vmx_load_host_state(), in case userspace uses the null selectors
4106          * too (the expected case).
4107          */
4108         vmcs_write16(HOST_DS_SELECTOR, 0);
4109         vmcs_write16(HOST_ES_SELECTOR, 0);
4110 #else
4111         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4112         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4113 #endif
4114         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4115         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4116
4117         native_store_idt(&dt);
4118         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4119         vmx->host_idt_base = dt.address;
4120
4121         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4122
4123         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4124         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4125         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4126         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4127
4128         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4129                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4130                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4131         }
4132 }
4133
4134 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4135 {
4136         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4137         if (enable_ept)
4138                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4139         if (is_guest_mode(&vmx->vcpu))
4140                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4141                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4142         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4143 }
4144
4145 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4146 {
4147         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4148
4149         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4150                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4151         return pin_based_exec_ctrl;
4152 }
4153
4154 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4155 {
4156         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4157         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4158                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4159 #ifdef CONFIG_X86_64
4160                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4161                                 CPU_BASED_CR8_LOAD_EXITING;
4162 #endif
4163         }
4164         if (!enable_ept)
4165                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4166                                 CPU_BASED_CR3_LOAD_EXITING  |
4167                                 CPU_BASED_INVLPG_EXITING;
4168         return exec_control;
4169 }
4170
4171 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4172 {
4173         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4174         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4175                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4176         if (vmx->vpid == 0)
4177                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4178         if (!enable_ept) {
4179                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4180                 enable_unrestricted_guest = 0;
4181                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4182                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4183         }
4184         if (!enable_unrestricted_guest)
4185                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4186         if (!ple_gap)
4187                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4188         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4189                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4190                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4191         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4192         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4193            (handle_vmptrld).
4194            We can NOT enable shadow_vmcs here because we don't have yet
4195            a current VMCS12
4196         */
4197         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4198         return exec_control;
4199 }
4200
4201 static void ept_set_mmio_spte_mask(void)
4202 {
4203         /*
4204          * EPT Misconfigurations can be generated if the value of bits 2:0
4205          * of an EPT paging-structure entry is 110b (write/execute).
4206          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4207          * spte.
4208          */
4209         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4210 }
4211
4212 /*
4213  * Sets up the vmcs for emulated real mode.
4214  */
4215 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4216 {
4217 #ifdef CONFIG_X86_64
4218         unsigned long a;
4219 #endif
4220         int i;
4221
4222         /* I/O */
4223         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4224         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4225
4226         if (enable_shadow_vmcs) {
4227                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4228                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4229         }
4230         if (cpu_has_vmx_msr_bitmap())
4231                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4232
4233         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4234
4235         /* Control */
4236         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4237
4238         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4239
4240         if (cpu_has_secondary_exec_ctrls()) {
4241                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4242                                 vmx_secondary_exec_control(vmx));
4243         }
4244
4245         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4246                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4247                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4248                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4249                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4250
4251                 vmcs_write16(GUEST_INTR_STATUS, 0);
4252
4253                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4254                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4255         }
4256
4257         if (ple_gap) {
4258                 vmcs_write32(PLE_GAP, ple_gap);
4259                 vmcs_write32(PLE_WINDOW, ple_window);
4260         }
4261
4262         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4263         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4264         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4265
4266         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4267         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4268         vmx_set_constant_host_state(vmx);
4269 #ifdef CONFIG_X86_64
4270         rdmsrl(MSR_FS_BASE, a);
4271         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4272         rdmsrl(MSR_GS_BASE, a);
4273         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4274 #else
4275         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4276         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4277 #endif
4278
4279         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4280         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4281         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4282         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4283         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4284
4285         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4286                 u32 msr_low, msr_high;
4287                 u64 host_pat;
4288                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4289                 host_pat = msr_low | ((u64) msr_high << 32);
4290                 /* Write the default value follow host pat */
4291                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4292                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4293                 vmx->vcpu.arch.pat = host_pat;
4294         }
4295
4296         for (i = 0; i < NR_VMX_MSR; ++i) {
4297                 u32 index = vmx_msr_index[i];
4298                 u32 data_low, data_high;
4299                 int j = vmx->nmsrs;
4300
4301                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4302                         continue;
4303                 if (wrmsr_safe(index, data_low, data_high) < 0)
4304                         continue;
4305                 vmx->guest_msrs[j].index = i;
4306                 vmx->guest_msrs[j].data = 0;
4307                 vmx->guest_msrs[j].mask = -1ull;
4308                 ++vmx->nmsrs;
4309         }
4310
4311         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4312
4313         /* 22.2.1, 20.8.1 */
4314         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4315
4316         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4317         set_cr4_guest_host_mask(vmx);
4318
4319         return 0;
4320 }
4321
4322 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4323 {
4324         struct vcpu_vmx *vmx = to_vmx(vcpu);
4325         u64 msr;
4326
4327         vmx->rmode.vm86_active = 0;
4328
4329         vmx->soft_vnmi_blocked = 0;
4330
4331         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4332         kvm_set_cr8(&vmx->vcpu, 0);
4333         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4334         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4335                 msr |= MSR_IA32_APICBASE_BSP;
4336         kvm_set_apic_base(&vmx->vcpu, msr);
4337
4338         vmx_segment_cache_clear(vmx);
4339
4340         seg_setup(VCPU_SREG_CS);
4341         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4342         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4343
4344         seg_setup(VCPU_SREG_DS);
4345         seg_setup(VCPU_SREG_ES);
4346         seg_setup(VCPU_SREG_FS);
4347         seg_setup(VCPU_SREG_GS);
4348         seg_setup(VCPU_SREG_SS);
4349
4350         vmcs_write16(GUEST_TR_SELECTOR, 0);
4351         vmcs_writel(GUEST_TR_BASE, 0);
4352         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4353         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4354
4355         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4356         vmcs_writel(GUEST_LDTR_BASE, 0);
4357         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4358         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4359
4360         vmcs_write32(GUEST_SYSENTER_CS, 0);
4361         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4362         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4363
4364         vmcs_writel(GUEST_RFLAGS, 0x02);
4365         kvm_rip_write(vcpu, 0xfff0);
4366
4367         vmcs_writel(GUEST_GDTR_BASE, 0);
4368         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4369
4370         vmcs_writel(GUEST_IDTR_BASE, 0);
4371         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4372
4373         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4374         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4375         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4376
4377         /* Special registers */
4378         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4379
4380         setup_msrs(vmx);
4381
4382         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4383
4384         if (cpu_has_vmx_tpr_shadow()) {
4385                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4386                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4387                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4388                                      __pa(vmx->vcpu.arch.apic->regs));
4389                 vmcs_write32(TPR_THRESHOLD, 0);
4390         }
4391
4392         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4393                 vmcs_write64(APIC_ACCESS_ADDR,
4394                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4395
4396         if (vmx_vm_has_apicv(vcpu->kvm))
4397                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4398
4399         if (vmx->vpid != 0)
4400                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4401
4402         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4403         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4404         vmx_set_cr4(&vmx->vcpu, 0);
4405         vmx_set_efer(&vmx->vcpu, 0);
4406         vmx_fpu_activate(&vmx->vcpu);
4407         update_exception_bitmap(&vmx->vcpu);
4408
4409         vpid_sync_context(vmx);
4410 }
4411
4412 /*
4413  * In nested virtualization, check if L1 asked to exit on external interrupts.
4414  * For most existing hypervisors, this will always return true.
4415  */
4416 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4417 {
4418         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4419                 PIN_BASED_EXT_INTR_MASK;
4420 }
4421
4422 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4423 {
4424         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4425                 PIN_BASED_NMI_EXITING;
4426 }
4427
4428 static int enable_irq_window(struct kvm_vcpu *vcpu)
4429 {
4430         u32 cpu_based_vm_exec_control;
4431
4432         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4433                 /*
4434                  * We get here if vmx_interrupt_allowed() said we can't
4435                  * inject to L1 now because L2 must run. The caller will have
4436                  * to make L2 exit right after entry, so we can inject to L1
4437                  * more promptly.
4438                  */
4439                 return -EBUSY;
4440
4441         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4442         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4443         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4444         return 0;
4445 }
4446
4447 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4448 {
4449         u32 cpu_based_vm_exec_control;
4450
4451         if (!cpu_has_virtual_nmis())
4452                 return enable_irq_window(vcpu);
4453
4454         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4455                 return enable_irq_window(vcpu);
4456
4457         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4458         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4459         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4460         return 0;
4461 }
4462
4463 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4464 {
4465         struct vcpu_vmx *vmx = to_vmx(vcpu);
4466         uint32_t intr;
4467         int irq = vcpu->arch.interrupt.nr;
4468
4469         trace_kvm_inj_virq(irq);
4470
4471         ++vcpu->stat.irq_injections;
4472         if (vmx->rmode.vm86_active) {
4473                 int inc_eip = 0;
4474                 if (vcpu->arch.interrupt.soft)
4475                         inc_eip = vcpu->arch.event_exit_inst_len;
4476                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4477                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4478                 return;
4479         }
4480         intr = irq | INTR_INFO_VALID_MASK;
4481         if (vcpu->arch.interrupt.soft) {
4482                 intr |= INTR_TYPE_SOFT_INTR;
4483                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4484                              vmx->vcpu.arch.event_exit_inst_len);
4485         } else
4486                 intr |= INTR_TYPE_EXT_INTR;
4487         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4488 }
4489
4490 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4491 {
4492         struct vcpu_vmx *vmx = to_vmx(vcpu);
4493
4494         if (is_guest_mode(vcpu))
4495                 return;
4496
4497         if (!cpu_has_virtual_nmis()) {
4498                 /*
4499                  * Tracking the NMI-blocked state in software is built upon
4500                  * finding the next open IRQ window. This, in turn, depends on
4501                  * well-behaving guests: They have to keep IRQs disabled at
4502                  * least as long as the NMI handler runs. Otherwise we may
4503                  * cause NMI nesting, maybe breaking the guest. But as this is
4504                  * highly unlikely, we can live with the residual risk.
4505                  */
4506                 vmx->soft_vnmi_blocked = 1;
4507                 vmx->vnmi_blocked_time = 0;
4508         }
4509
4510         ++vcpu->stat.nmi_injections;
4511         vmx->nmi_known_unmasked = false;
4512         if (vmx->rmode.vm86_active) {
4513                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4514                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4515                 return;
4516         }
4517         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4518                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4519 }
4520
4521 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4522 {
4523         if (!cpu_has_virtual_nmis())
4524                 return to_vmx(vcpu)->soft_vnmi_blocked;
4525         if (to_vmx(vcpu)->nmi_known_unmasked)
4526                 return false;
4527         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4528 }
4529
4530 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4531 {
4532         struct vcpu_vmx *vmx = to_vmx(vcpu);
4533
4534         if (!cpu_has_virtual_nmis()) {
4535                 if (vmx->soft_vnmi_blocked != masked) {
4536                         vmx->soft_vnmi_blocked = masked;
4537                         vmx->vnmi_blocked_time = 0;
4538                 }
4539         } else {
4540                 vmx->nmi_known_unmasked = !masked;
4541                 if (masked)
4542                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4543                                       GUEST_INTR_STATE_NMI);
4544                 else
4545                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4546                                         GUEST_INTR_STATE_NMI);
4547         }
4548 }
4549
4550 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4551 {
4552         if (is_guest_mode(vcpu)) {
4553                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4554
4555                 if (to_vmx(vcpu)->nested.nested_run_pending)
4556                         return 0;
4557                 if (nested_exit_on_nmi(vcpu)) {
4558                         nested_vmx_vmexit(vcpu);
4559                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4560                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4561                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4562                         /*
4563                          * The NMI-triggered VM exit counts as injection:
4564                          * clear this one and block further NMIs.
4565                          */
4566                         vcpu->arch.nmi_pending = 0;
4567                         vmx_set_nmi_mask(vcpu, true);
4568                         return 0;
4569                 }
4570         }
4571
4572         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4573                 return 0;
4574
4575         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4576                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4577                    | GUEST_INTR_STATE_NMI));
4578 }
4579
4580 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4581 {
4582         if (is_guest_mode(vcpu)) {
4583                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4584
4585                 if (to_vmx(vcpu)->nested.nested_run_pending)
4586                         return 0;
4587                 if (nested_exit_on_intr(vcpu)) {
4588                         nested_vmx_vmexit(vcpu);
4589                         vmcs12->vm_exit_reason =
4590                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4591                         vmcs12->vm_exit_intr_info = 0;
4592                         /*
4593                          * fall through to normal code, but now in L1, not L2
4594                          */
4595                 }
4596         }
4597
4598         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4599                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4600                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4601 }
4602
4603 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4604 {
4605         int ret;
4606         struct kvm_userspace_memory_region tss_mem = {
4607                 .slot = TSS_PRIVATE_MEMSLOT,
4608                 .guest_phys_addr = addr,
4609                 .memory_size = PAGE_SIZE * 3,
4610                 .flags = 0,
4611         };
4612
4613         ret = kvm_set_memory_region(kvm, &tss_mem);
4614         if (ret)
4615                 return ret;
4616         kvm->arch.tss_addr = addr;
4617         if (!init_rmode_tss(kvm))
4618                 return  -ENOMEM;
4619
4620         return 0;
4621 }
4622
4623 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4624 {
4625         switch (vec) {
4626         case BP_VECTOR:
4627                 /*
4628                  * Update instruction length as we may reinject the exception
4629                  * from user space while in guest debugging mode.
4630                  */
4631                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4632                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4633                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4634                         return false;
4635                 /* fall through */
4636         case DB_VECTOR:
4637                 if (vcpu->guest_debug &
4638                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4639                         return false;
4640                 /* fall through */
4641         case DE_VECTOR:
4642         case OF_VECTOR:
4643         case BR_VECTOR:
4644         case UD_VECTOR:
4645         case DF_VECTOR:
4646         case SS_VECTOR:
4647         case GP_VECTOR:
4648         case MF_VECTOR:
4649                 return true;
4650         break;
4651         }
4652         return false;
4653 }
4654
4655 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4656                                   int vec, u32 err_code)
4657 {
4658         /*
4659          * Instruction with address size override prefix opcode 0x67
4660          * Cause the #SS fault with 0 error code in VM86 mode.
4661          */
4662         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4663                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4664                         if (vcpu->arch.halt_request) {
4665                                 vcpu->arch.halt_request = 0;
4666                                 return kvm_emulate_halt(vcpu);
4667                         }
4668                         return 1;
4669                 }
4670                 return 0;
4671         }
4672
4673         /*
4674          * Forward all other exceptions that are valid in real mode.
4675          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4676          *        the required debugging infrastructure rework.
4677          */
4678         kvm_queue_exception(vcpu, vec);
4679         return 1;
4680 }
4681
4682 /*
4683  * Trigger machine check on the host. We assume all the MSRs are already set up
4684  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4685  * We pass a fake environment to the machine check handler because we want
4686  * the guest to be always treated like user space, no matter what context
4687  * it used internally.
4688  */
4689 static void kvm_machine_check(void)
4690 {
4691 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4692         struct pt_regs regs = {
4693                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4694                 .flags = X86_EFLAGS_IF,
4695         };
4696
4697         do_machine_check(&regs, 0);
4698 #endif
4699 }
4700
4701 static int handle_machine_check(struct kvm_vcpu *vcpu)
4702 {
4703         /* already handled by vcpu_run */
4704         return 1;
4705 }
4706
4707 static int handle_exception(struct kvm_vcpu *vcpu)
4708 {
4709         struct vcpu_vmx *vmx = to_vmx(vcpu);
4710         struct kvm_run *kvm_run = vcpu->run;
4711         u32 intr_info, ex_no, error_code;
4712         unsigned long cr2, rip, dr6;
4713         u32 vect_info;
4714         enum emulation_result er;
4715
4716         vect_info = vmx->idt_vectoring_info;
4717         intr_info = vmx->exit_intr_info;
4718
4719         if (is_machine_check(intr_info))
4720                 return handle_machine_check(vcpu);
4721
4722         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4723                 return 1;  /* already handled by vmx_vcpu_run() */
4724
4725         if (is_no_device(intr_info)) {
4726                 vmx_fpu_activate(vcpu);
4727                 return 1;
4728         }
4729
4730         if (is_invalid_opcode(intr_info)) {
4731                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4732                 if (er != EMULATE_DONE)
4733                         kvm_queue_exception(vcpu, UD_VECTOR);
4734                 return 1;
4735         }
4736
4737         error_code = 0;
4738         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4739                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4740
4741         /*
4742          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4743          * MMIO, it is better to report an internal error.
4744          * See the comments in vmx_handle_exit.
4745          */
4746         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4747             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4748                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4749                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4750                 vcpu->run->internal.ndata = 2;
4751                 vcpu->run->internal.data[0] = vect_info;
4752                 vcpu->run->internal.data[1] = intr_info;
4753                 return 0;
4754         }
4755
4756         if (is_page_fault(intr_info)) {
4757                 /* EPT won't cause page fault directly */
4758                 BUG_ON(enable_ept);
4759                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4760                 trace_kvm_page_fault(cr2, error_code);
4761
4762                 if (kvm_event_needs_reinjection(vcpu))
4763                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4764                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4765         }
4766
4767         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4768
4769         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4770                 return handle_rmode_exception(vcpu, ex_no, error_code);
4771
4772         switch (ex_no) {
4773         case DB_VECTOR:
4774                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4775                 if (!(vcpu->guest_debug &
4776                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4777                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4778                         kvm_queue_exception(vcpu, DB_VECTOR);
4779                         return 1;
4780                 }
4781                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4782                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4783                 /* fall through */
4784         case BP_VECTOR:
4785                 /*
4786                  * Update instruction length as we may reinject #BP from
4787                  * user space while in guest debugging mode. Reading it for
4788                  * #DB as well causes no harm, it is not used in that case.
4789                  */
4790                 vmx->vcpu.arch.event_exit_inst_len =
4791                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4792                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4793                 rip = kvm_rip_read(vcpu);
4794                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4795                 kvm_run->debug.arch.exception = ex_no;
4796                 break;
4797         default:
4798                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4799                 kvm_run->ex.exception = ex_no;
4800                 kvm_run->ex.error_code = error_code;
4801                 break;
4802         }
4803         return 0;
4804 }
4805
4806 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4807 {
4808         ++vcpu->stat.irq_exits;
4809         return 1;
4810 }
4811
4812 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4813 {
4814         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4815         return 0;
4816 }
4817
4818 static int handle_io(struct kvm_vcpu *vcpu)
4819 {
4820         unsigned long exit_qualification;
4821         int size, in, string;
4822         unsigned port;
4823
4824         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4825         string = (exit_qualification & 16) != 0;
4826         in = (exit_qualification & 8) != 0;
4827
4828         ++vcpu->stat.io_exits;
4829
4830         if (string || in)
4831                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4832
4833         port = exit_qualification >> 16;
4834         size = (exit_qualification & 7) + 1;
4835         skip_emulated_instruction(vcpu);
4836
4837         return kvm_fast_pio_out(vcpu, size, port);
4838 }
4839
4840 static void
4841 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4842 {
4843         /*
4844          * Patch in the VMCALL instruction:
4845          */
4846         hypercall[0] = 0x0f;
4847         hypercall[1] = 0x01;
4848         hypercall[2] = 0xc1;
4849 }
4850
4851 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4852 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4853 {
4854         if (is_guest_mode(vcpu)) {
4855                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4856                 unsigned long orig_val = val;
4857
4858                 /*
4859                  * We get here when L2 changed cr0 in a way that did not change
4860                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4861                  * but did change L0 shadowed bits. So we first calculate the
4862                  * effective cr0 value that L1 would like to write into the
4863                  * hardware. It consists of the L2-owned bits from the new
4864                  * value combined with the L1-owned bits from L1's guest_cr0.
4865                  */
4866                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4867                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4868
4869                 /* TODO: will have to take unrestricted guest mode into
4870                  * account */
4871                 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4872                         return 1;
4873
4874                 if (kvm_set_cr0(vcpu, val))
4875                         return 1;
4876                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4877                 return 0;
4878         } else {
4879                 if (to_vmx(vcpu)->nested.vmxon &&
4880                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4881                         return 1;
4882                 return kvm_set_cr0(vcpu, val);
4883         }
4884 }
4885
4886 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4887 {
4888         if (is_guest_mode(vcpu)) {
4889                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4890                 unsigned long orig_val = val;
4891
4892                 /* analogously to handle_set_cr0 */
4893                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4894                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4895                 if (kvm_set_cr4(vcpu, val))
4896                         return 1;
4897                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4898                 return 0;
4899         } else
4900                 return kvm_set_cr4(vcpu, val);
4901 }
4902
4903 /* called to set cr0 as approriate for clts instruction exit. */
4904 static void handle_clts(struct kvm_vcpu *vcpu)
4905 {
4906         if (is_guest_mode(vcpu)) {
4907                 /*
4908                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4909                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4910                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4911                  */
4912                 vmcs_writel(CR0_READ_SHADOW,
4913                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4914                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4915         } else
4916                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4917 }
4918
4919 static int handle_cr(struct kvm_vcpu *vcpu)
4920 {
4921         unsigned long exit_qualification, val;
4922         int cr;
4923         int reg;
4924         int err;
4925
4926         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4927         cr = exit_qualification & 15;
4928         reg = (exit_qualification >> 8) & 15;
4929         switch ((exit_qualification >> 4) & 3) {
4930         case 0: /* mov to cr */
4931                 val = kvm_register_read(vcpu, reg);
4932                 trace_kvm_cr_write(cr, val);
4933                 switch (cr) {
4934                 case 0:
4935                         err = handle_set_cr0(vcpu, val);
4936                         kvm_complete_insn_gp(vcpu, err);
4937                         return 1;
4938                 case 3:
4939                         err = kvm_set_cr3(vcpu, val);
4940                         kvm_complete_insn_gp(vcpu, err);
4941                         return 1;
4942                 case 4:
4943                         err = handle_set_cr4(vcpu, val);
4944                         kvm_complete_insn_gp(vcpu, err);
4945                         return 1;
4946                 case 8: {
4947                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4948                                 u8 cr8 = kvm_register_read(vcpu, reg);
4949                                 err = kvm_set_cr8(vcpu, cr8);
4950                                 kvm_complete_insn_gp(vcpu, err);
4951                                 if (irqchip_in_kernel(vcpu->kvm))
4952                                         return 1;
4953                                 if (cr8_prev <= cr8)
4954                                         return 1;
4955                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4956                                 return 0;
4957                         }
4958                 }
4959                 break;
4960         case 2: /* clts */
4961                 handle_clts(vcpu);
4962                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4963                 skip_emulated_instruction(vcpu);
4964                 vmx_fpu_activate(vcpu);
4965                 return 1;
4966         case 1: /*mov from cr*/
4967                 switch (cr) {
4968                 case 3:
4969                         val = kvm_read_cr3(vcpu);
4970                         kvm_register_write(vcpu, reg, val);
4971                         trace_kvm_cr_read(cr, val);
4972                         skip_emulated_instruction(vcpu);
4973                         return 1;
4974                 case 8:
4975                         val = kvm_get_cr8(vcpu);
4976                         kvm_register_write(vcpu, reg, val);
4977                         trace_kvm_cr_read(cr, val);
4978                         skip_emulated_instruction(vcpu);
4979                         return 1;
4980                 }
4981                 break;
4982         case 3: /* lmsw */
4983                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4984                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4985                 kvm_lmsw(vcpu, val);
4986
4987                 skip_emulated_instruction(vcpu);
4988                 return 1;
4989         default:
4990                 break;
4991         }
4992         vcpu->run->exit_reason = 0;
4993         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4994                (int)(exit_qualification >> 4) & 3, cr);
4995         return 0;
4996 }
4997
4998 static int handle_dr(struct kvm_vcpu *vcpu)
4999 {
5000         unsigned long exit_qualification;
5001         int dr, reg;
5002
5003         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5004         if (!kvm_require_cpl(vcpu, 0))
5005                 return 1;
5006         dr = vmcs_readl(GUEST_DR7);
5007         if (dr & DR7_GD) {
5008                 /*
5009                  * As the vm-exit takes precedence over the debug trap, we
5010                  * need to emulate the latter, either for the host or the
5011                  * guest debugging itself.
5012                  */
5013                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5014                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5015                         vcpu->run->debug.arch.dr7 = dr;
5016                         vcpu->run->debug.arch.pc =
5017                                 vmcs_readl(GUEST_CS_BASE) +
5018                                 vmcs_readl(GUEST_RIP);
5019                         vcpu->run->debug.arch.exception = DB_VECTOR;
5020                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5021                         return 0;
5022                 } else {
5023                         vcpu->arch.dr7 &= ~DR7_GD;
5024                         vcpu->arch.dr6 |= DR6_BD;
5025                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5026                         kvm_queue_exception(vcpu, DB_VECTOR);
5027                         return 1;
5028                 }
5029         }
5030
5031         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5032         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5033         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5034         if (exit_qualification & TYPE_MOV_FROM_DR) {
5035                 unsigned long val;
5036                 if (!kvm_get_dr(vcpu, dr, &val))
5037                         kvm_register_write(vcpu, reg, val);
5038         } else
5039                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5040         skip_emulated_instruction(vcpu);
5041         return 1;
5042 }
5043
5044 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5045 {
5046         vmcs_writel(GUEST_DR7, val);
5047 }
5048
5049 static int handle_cpuid(struct kvm_vcpu *vcpu)
5050 {
5051         kvm_emulate_cpuid(vcpu);
5052         return 1;
5053 }
5054
5055 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5056 {
5057         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5058         u64 data;
5059
5060         if (vmx_get_msr(vcpu, ecx, &data)) {
5061                 trace_kvm_msr_read_ex(ecx);
5062                 kvm_inject_gp(vcpu, 0);
5063                 return 1;
5064         }
5065
5066         trace_kvm_msr_read(ecx, data);
5067
5068         /* FIXME: handling of bits 32:63 of rax, rdx */
5069         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5070         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5071         skip_emulated_instruction(vcpu);
5072         return 1;
5073 }
5074
5075 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5076 {
5077         struct msr_data msr;
5078         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5079         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5080                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5081
5082         msr.data = data;
5083         msr.index = ecx;
5084         msr.host_initiated = false;
5085         if (vmx_set_msr(vcpu, &msr) != 0) {
5086                 trace_kvm_msr_write_ex(ecx, data);
5087                 kvm_inject_gp(vcpu, 0);
5088                 return 1;
5089         }
5090
5091         trace_kvm_msr_write(ecx, data);
5092         skip_emulated_instruction(vcpu);
5093         return 1;
5094 }
5095
5096 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5097 {
5098         kvm_make_request(KVM_REQ_EVENT, vcpu);
5099         return 1;
5100 }
5101
5102 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5103 {
5104         u32 cpu_based_vm_exec_control;
5105
5106         /* clear pending irq */
5107         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5108         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5109         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5110
5111         kvm_make_request(KVM_REQ_EVENT, vcpu);
5112
5113         ++vcpu->stat.irq_window_exits;
5114
5115         /*
5116          * If the user space waits to inject interrupts, exit as soon as
5117          * possible
5118          */
5119         if (!irqchip_in_kernel(vcpu->kvm) &&
5120             vcpu->run->request_interrupt_window &&
5121             !kvm_cpu_has_interrupt(vcpu)) {
5122                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5123                 return 0;
5124         }
5125         return 1;
5126 }
5127
5128 static int handle_halt(struct kvm_vcpu *vcpu)
5129 {
5130         skip_emulated_instruction(vcpu);
5131         return kvm_emulate_halt(vcpu);
5132 }
5133
5134 static int handle_vmcall(struct kvm_vcpu *vcpu)
5135 {
5136         skip_emulated_instruction(vcpu);
5137         kvm_emulate_hypercall(vcpu);
5138         return 1;
5139 }
5140
5141 static int handle_invd(struct kvm_vcpu *vcpu)
5142 {
5143         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5144 }
5145
5146 static int handle_invlpg(struct kvm_vcpu *vcpu)
5147 {
5148         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5149
5150         kvm_mmu_invlpg(vcpu, exit_qualification);
5151         skip_emulated_instruction(vcpu);
5152         return 1;
5153 }
5154
5155 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5156 {
5157         int err;
5158
5159         err = kvm_rdpmc(vcpu);
5160         kvm_complete_insn_gp(vcpu, err);
5161
5162         return 1;
5163 }
5164
5165 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5166 {
5167         skip_emulated_instruction(vcpu);
5168         kvm_emulate_wbinvd(vcpu);
5169         return 1;
5170 }
5171
5172 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5173 {
5174         u64 new_bv = kvm_read_edx_eax(vcpu);
5175         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5176
5177         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5178                 skip_emulated_instruction(vcpu);
5179         return 1;
5180 }
5181
5182 static int handle_apic_access(struct kvm_vcpu *vcpu)
5183 {
5184         if (likely(fasteoi)) {
5185                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5186                 int access_type, offset;
5187
5188                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5189                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5190                 /*
5191                  * Sane guest uses MOV to write EOI, with written value
5192                  * not cared. So make a short-circuit here by avoiding
5193                  * heavy instruction emulation.
5194                  */
5195                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5196                     (offset == APIC_EOI)) {
5197                         kvm_lapic_set_eoi(vcpu);
5198                         skip_emulated_instruction(vcpu);
5199                         return 1;
5200                 }
5201         }
5202         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5203 }
5204
5205 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5206 {
5207         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5208         int vector = exit_qualification & 0xff;
5209
5210         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5211         kvm_apic_set_eoi_accelerated(vcpu, vector);
5212         return 1;
5213 }
5214
5215 static int handle_apic_write(struct kvm_vcpu *vcpu)
5216 {
5217         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5218         u32 offset = exit_qualification & 0xfff;
5219
5220         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5221         kvm_apic_write_nodecode(vcpu, offset);
5222         return 1;
5223 }
5224
5225 static int handle_task_switch(struct kvm_vcpu *vcpu)
5226 {
5227         struct vcpu_vmx *vmx = to_vmx(vcpu);
5228         unsigned long exit_qualification;
5229         bool has_error_code = false;
5230         u32 error_code = 0;
5231         u16 tss_selector;
5232         int reason, type, idt_v, idt_index;
5233
5234         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5235         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5236         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5237
5238         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5239
5240         reason = (u32)exit_qualification >> 30;
5241         if (reason == TASK_SWITCH_GATE && idt_v) {
5242                 switch (type) {
5243                 case INTR_TYPE_NMI_INTR:
5244                         vcpu->arch.nmi_injected = false;
5245                         vmx_set_nmi_mask(vcpu, true);
5246                         break;
5247                 case INTR_TYPE_EXT_INTR:
5248                 case INTR_TYPE_SOFT_INTR:
5249                         kvm_clear_interrupt_queue(vcpu);
5250                         break;
5251                 case INTR_TYPE_HARD_EXCEPTION:
5252                         if (vmx->idt_vectoring_info &
5253                             VECTORING_INFO_DELIVER_CODE_MASK) {
5254                                 has_error_code = true;
5255                                 error_code =
5256                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5257                         }
5258                         /* fall through */
5259                 case INTR_TYPE_SOFT_EXCEPTION:
5260                         kvm_clear_exception_queue(vcpu);
5261                         break;
5262                 default:
5263                         break;
5264                 }
5265         }
5266         tss_selector = exit_qualification;
5267
5268         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5269                        type != INTR_TYPE_EXT_INTR &&
5270                        type != INTR_TYPE_NMI_INTR))
5271                 skip_emulated_instruction(vcpu);
5272
5273         if (kvm_task_switch(vcpu, tss_selector,
5274                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5275                             has_error_code, error_code) == EMULATE_FAIL) {
5276                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5277                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5278                 vcpu->run->internal.ndata = 0;
5279                 return 0;
5280         }
5281
5282         /* clear all local breakpoint enable flags */
5283         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5284
5285         /*
5286          * TODO: What about debug traps on tss switch?
5287          *       Are we supposed to inject them and update dr6?
5288          */
5289
5290         return 1;
5291 }
5292
5293 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5294 {
5295         unsigned long exit_qualification;
5296         gpa_t gpa;
5297         u32 error_code;
5298         int gla_validity;
5299
5300         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5301
5302         gla_validity = (exit_qualification >> 7) & 0x3;
5303         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5304                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5305                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5306                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5307                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5308                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5309                         (long unsigned int)exit_qualification);
5310                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5311                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5312                 return 0;
5313         }
5314
5315         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5316         trace_kvm_page_fault(gpa, exit_qualification);
5317
5318         /* It is a write fault? */
5319         error_code = exit_qualification & (1U << 1);
5320         /* It is a fetch fault? */
5321         error_code |= (exit_qualification & (1U << 2)) << 2;
5322         /* ept page table is present? */
5323         error_code |= (exit_qualification >> 3) & 0x1;
5324
5325         vcpu->arch.exit_qualification = exit_qualification;
5326
5327         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5328 }
5329
5330 static u64 ept_rsvd_mask(u64 spte, int level)
5331 {
5332         int i;
5333         u64 mask = 0;
5334
5335         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5336                 mask |= (1ULL << i);
5337
5338         if (level > 2)
5339                 /* bits 7:3 reserved */
5340                 mask |= 0xf8;
5341         else if (level == 2) {
5342                 if (spte & (1ULL << 7))
5343                         /* 2MB ref, bits 20:12 reserved */
5344                         mask |= 0x1ff000;
5345                 else
5346                         /* bits 6:3 reserved */
5347                         mask |= 0x78;
5348         }
5349
5350         return mask;
5351 }
5352
5353 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5354                                        int level)
5355 {
5356         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5357
5358         /* 010b (write-only) */
5359         WARN_ON((spte & 0x7) == 0x2);
5360
5361         /* 110b (write/execute) */
5362         WARN_ON((spte & 0x7) == 0x6);
5363
5364         /* 100b (execute-only) and value not supported by logical processor */
5365         if (!cpu_has_vmx_ept_execute_only())
5366                 WARN_ON((spte & 0x7) == 0x4);
5367
5368         /* not 000b */
5369         if ((spte & 0x7)) {
5370                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5371
5372                 if (rsvd_bits != 0) {
5373                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5374                                          __func__, rsvd_bits);
5375                         WARN_ON(1);
5376                 }
5377
5378                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5379                         u64 ept_mem_type = (spte & 0x38) >> 3;
5380
5381                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5382                             ept_mem_type == 7) {
5383                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5384                                                 __func__, ept_mem_type);
5385                                 WARN_ON(1);
5386                         }
5387                 }
5388         }
5389 }
5390
5391 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5392 {
5393         u64 sptes[4];
5394         int nr_sptes, i, ret;
5395         gpa_t gpa;
5396
5397         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5398
5399         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5400         if (likely(ret == RET_MMIO_PF_EMULATE))
5401                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5402                                               EMULATE_DONE;
5403
5404         if (unlikely(ret == RET_MMIO_PF_INVALID))
5405                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5406
5407         if (unlikely(ret == RET_MMIO_PF_RETRY))
5408                 return 1;
5409
5410         /* It is the real ept misconfig */
5411         printk(KERN_ERR "EPT: Misconfiguration.\n");
5412         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5413
5414         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5415
5416         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5417                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5418
5419         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5420         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5421
5422         return 0;
5423 }
5424
5425 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5426 {
5427         u32 cpu_based_vm_exec_control;
5428
5429         /* clear pending NMI */
5430         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5431         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5432         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5433         ++vcpu->stat.nmi_window_exits;
5434         kvm_make_request(KVM_REQ_EVENT, vcpu);
5435
5436         return 1;
5437 }
5438
5439 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5440 {
5441         struct vcpu_vmx *vmx = to_vmx(vcpu);
5442         enum emulation_result err = EMULATE_DONE;
5443         int ret = 1;
5444         u32 cpu_exec_ctrl;
5445         bool intr_window_requested;
5446         unsigned count = 130;
5447
5448         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5449         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5450
5451         while (!guest_state_valid(vcpu) && count-- != 0) {
5452                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5453                         return handle_interrupt_window(&vmx->vcpu);
5454
5455                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5456                         return 1;
5457
5458                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5459
5460                 if (err == EMULATE_USER_EXIT) {
5461                         ret = 0;
5462                         goto out;
5463                 }
5464
5465                 if (err != EMULATE_DONE) {
5466                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5467                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5468                         vcpu->run->internal.ndata = 0;
5469                         return 0;
5470                 }
5471
5472                 if (vcpu->arch.halt_request) {
5473                         vcpu->arch.halt_request = 0;
5474                         ret = kvm_emulate_halt(vcpu);
5475                         goto out;
5476                 }
5477
5478                 if (signal_pending(current))
5479                         goto out;
5480                 if (need_resched())
5481                         schedule();
5482         }
5483
5484         vmx->emulation_required = emulation_required(vcpu);
5485 out:
5486         return ret;
5487 }
5488
5489 /*
5490  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5491  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5492  */
5493 static int handle_pause(struct kvm_vcpu *vcpu)
5494 {
5495         skip_emulated_instruction(vcpu);
5496         kvm_vcpu_on_spin(vcpu);
5497
5498         return 1;
5499 }
5500
5501 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5502 {
5503         kvm_queue_exception(vcpu, UD_VECTOR);
5504         return 1;
5505 }
5506
5507 /*
5508  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5509  * We could reuse a single VMCS for all the L2 guests, but we also want the
5510  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5511  * allows keeping them loaded on the processor, and in the future will allow
5512  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5513  * every entry if they never change.
5514  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5515  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5516  *
5517  * The following functions allocate and free a vmcs02 in this pool.
5518  */
5519
5520 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5521 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5522 {
5523         struct vmcs02_list *item;
5524         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5525                 if (item->vmptr == vmx->nested.current_vmptr) {
5526                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5527                         return &item->vmcs02;
5528                 }
5529
5530         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5531                 /* Recycle the least recently used VMCS. */
5532                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5533                         struct vmcs02_list, list);
5534                 item->vmptr = vmx->nested.current_vmptr;
5535                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5536                 return &item->vmcs02;
5537         }
5538
5539         /* Create a new VMCS */
5540         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5541         if (!item)
5542                 return NULL;
5543         item->vmcs02.vmcs = alloc_vmcs();
5544         if (!item->vmcs02.vmcs) {
5545                 kfree(item);
5546                 return NULL;
5547         }
5548         loaded_vmcs_init(&item->vmcs02);
5549         item->vmptr = vmx->nested.current_vmptr;
5550         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5551         vmx->nested.vmcs02_num++;
5552         return &item->vmcs02;
5553 }
5554
5555 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5556 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5557 {
5558         struct vmcs02_list *item;
5559         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5560                 if (item->vmptr == vmptr) {
5561                         free_loaded_vmcs(&item->vmcs02);
5562                         list_del(&item->list);
5563                         kfree(item);
5564                         vmx->nested.vmcs02_num--;
5565                         return;
5566                 }
5567 }
5568
5569 /*
5570  * Free all VMCSs saved for this vcpu, except the one pointed by
5571  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5572  * currently used, if running L2), and vmcs01 when running L2.
5573  */
5574 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5575 {
5576         struct vmcs02_list *item, *n;
5577         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5578                 if (vmx->loaded_vmcs != &item->vmcs02)
5579                         free_loaded_vmcs(&item->vmcs02);
5580                 list_del(&item->list);
5581                 kfree(item);
5582         }
5583         vmx->nested.vmcs02_num = 0;
5584
5585         if (vmx->loaded_vmcs != &vmx->vmcs01)
5586                 free_loaded_vmcs(&vmx->vmcs01);
5587 }
5588
5589 /*
5590  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5591  * set the success or error code of an emulated VMX instruction, as specified
5592  * by Vol 2B, VMX Instruction Reference, "Conventions".
5593  */
5594 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5595 {
5596         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5597                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5598                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5599 }
5600
5601 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5602 {
5603         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5604                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5605                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5606                         | X86_EFLAGS_CF);
5607 }
5608
5609 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5610                                         u32 vm_instruction_error)
5611 {
5612         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5613                 /*
5614                  * failValid writes the error number to the current VMCS, which
5615                  * can't be done there isn't a current VMCS.
5616                  */
5617                 nested_vmx_failInvalid(vcpu);
5618                 return;
5619         }
5620         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5621                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5622                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5623                         | X86_EFLAGS_ZF);
5624         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5625         /*
5626          * We don't need to force a shadow sync because
5627          * VM_INSTRUCTION_ERROR is not shadowed
5628          */
5629 }
5630
5631 /*
5632  * Emulate the VMXON instruction.
5633  * Currently, we just remember that VMX is active, and do not save or even
5634  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5635  * do not currently need to store anything in that guest-allocated memory
5636  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5637  * argument is different from the VMXON pointer (which the spec says they do).
5638  */
5639 static int handle_vmon(struct kvm_vcpu *vcpu)
5640 {
5641         struct kvm_segment cs;
5642         struct vcpu_vmx *vmx = to_vmx(vcpu);
5643         struct vmcs *shadow_vmcs;
5644         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5645                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5646
5647         /* The Intel VMX Instruction Reference lists a bunch of bits that
5648          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5649          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5650          * Otherwise, we should fail with #UD. We test these now:
5651          */
5652         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5653             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5654             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5655                 kvm_queue_exception(vcpu, UD_VECTOR);
5656                 return 1;
5657         }
5658
5659         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5660         if (is_long_mode(vcpu) && !cs.l) {
5661                 kvm_queue_exception(vcpu, UD_VECTOR);
5662                 return 1;
5663         }
5664
5665         if (vmx_get_cpl(vcpu)) {
5666                 kvm_inject_gp(vcpu, 0);
5667                 return 1;
5668         }
5669         if (vmx->nested.vmxon) {
5670                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5671                 skip_emulated_instruction(vcpu);
5672                 return 1;
5673         }
5674
5675         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5676                         != VMXON_NEEDED_FEATURES) {
5677                 kvm_inject_gp(vcpu, 0);
5678                 return 1;
5679         }
5680
5681         if (enable_shadow_vmcs) {
5682                 shadow_vmcs = alloc_vmcs();
5683                 if (!shadow_vmcs)
5684                         return -ENOMEM;
5685                 /* mark vmcs as shadow */
5686                 shadow_vmcs->revision_id |= (1u << 31);
5687                 /* init shadow vmcs */
5688                 vmcs_clear(shadow_vmcs);
5689                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5690         }
5691
5692         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5693         vmx->nested.vmcs02_num = 0;
5694
5695         vmx->nested.vmxon = true;
5696
5697         skip_emulated_instruction(vcpu);
5698         nested_vmx_succeed(vcpu);
5699         return 1;
5700 }
5701
5702 /*
5703  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5704  * for running VMX instructions (except VMXON, whose prerequisites are
5705  * slightly different). It also specifies what exception to inject otherwise.
5706  */
5707 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5708 {
5709         struct kvm_segment cs;
5710         struct vcpu_vmx *vmx = to_vmx(vcpu);
5711
5712         if (!vmx->nested.vmxon) {
5713                 kvm_queue_exception(vcpu, UD_VECTOR);
5714                 return 0;
5715         }
5716
5717         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5718         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5719             (is_long_mode(vcpu) && !cs.l)) {
5720                 kvm_queue_exception(vcpu, UD_VECTOR);
5721                 return 0;
5722         }
5723
5724         if (vmx_get_cpl(vcpu)) {
5725                 kvm_inject_gp(vcpu, 0);
5726                 return 0;
5727         }
5728
5729         return 1;
5730 }
5731
5732 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5733 {
5734         u32 exec_control;
5735         if (enable_shadow_vmcs) {
5736                 if (vmx->nested.current_vmcs12 != NULL) {
5737                         /* copy to memory all shadowed fields in case
5738                            they were modified */
5739                         copy_shadow_to_vmcs12(vmx);
5740                         vmx->nested.sync_shadow_vmcs = false;
5741                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5742                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5743                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5744                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5745                 }
5746         }
5747         kunmap(vmx->nested.current_vmcs12_page);
5748         nested_release_page(vmx->nested.current_vmcs12_page);
5749 }
5750
5751 /*
5752  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5753  * just stops using VMX.
5754  */
5755 static void free_nested(struct vcpu_vmx *vmx)
5756 {
5757         if (!vmx->nested.vmxon)
5758                 return;
5759         vmx->nested.vmxon = false;
5760         if (vmx->nested.current_vmptr != -1ull) {
5761                 nested_release_vmcs12(vmx);
5762                 vmx->nested.current_vmptr = -1ull;
5763                 vmx->nested.current_vmcs12 = NULL;
5764         }
5765         if (enable_shadow_vmcs)
5766                 free_vmcs(vmx->nested.current_shadow_vmcs);
5767         /* Unpin physical memory we referred to in current vmcs02 */
5768         if (vmx->nested.apic_access_page) {
5769                 nested_release_page(vmx->nested.apic_access_page);
5770                 vmx->nested.apic_access_page = 0;
5771         }
5772
5773         nested_free_all_saved_vmcss(vmx);
5774 }
5775
5776 /* Emulate the VMXOFF instruction */
5777 static int handle_vmoff(struct kvm_vcpu *vcpu)
5778 {
5779         if (!nested_vmx_check_permission(vcpu))
5780                 return 1;
5781         free_nested(to_vmx(vcpu));
5782         skip_emulated_instruction(vcpu);
5783         nested_vmx_succeed(vcpu);
5784         return 1;
5785 }
5786
5787 /*
5788  * Decode the memory-address operand of a vmx instruction, as recorded on an
5789  * exit caused by such an instruction (run by a guest hypervisor).
5790  * On success, returns 0. When the operand is invalid, returns 1 and throws
5791  * #UD or #GP.
5792  */
5793 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5794                                  unsigned long exit_qualification,
5795                                  u32 vmx_instruction_info, gva_t *ret)
5796 {
5797         /*
5798          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5799          * Execution", on an exit, vmx_instruction_info holds most of the
5800          * addressing components of the operand. Only the displacement part
5801          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5802          * For how an actual address is calculated from all these components,
5803          * refer to Vol. 1, "Operand Addressing".
5804          */
5805         int  scaling = vmx_instruction_info & 3;
5806         int  addr_size = (vmx_instruction_info >> 7) & 7;
5807         bool is_reg = vmx_instruction_info & (1u << 10);
5808         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5809         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5810         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5811         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5812         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5813
5814         if (is_reg) {
5815                 kvm_queue_exception(vcpu, UD_VECTOR);
5816                 return 1;
5817         }
5818
5819         /* Addr = segment_base + offset */
5820         /* offset = base + [index * scale] + displacement */
5821         *ret = vmx_get_segment_base(vcpu, seg_reg);
5822         if (base_is_valid)
5823                 *ret += kvm_register_read(vcpu, base_reg);
5824         if (index_is_valid)
5825                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5826         *ret += exit_qualification; /* holds the displacement */
5827
5828         if (addr_size == 1) /* 32 bit */
5829                 *ret &= 0xffffffff;
5830
5831         /*
5832          * TODO: throw #GP (and return 1) in various cases that the VM*
5833          * instructions require it - e.g., offset beyond segment limit,
5834          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5835          * address, and so on. Currently these are not checked.
5836          */
5837         return 0;
5838 }
5839
5840 /* Emulate the VMCLEAR instruction */
5841 static int handle_vmclear(struct kvm_vcpu *vcpu)
5842 {
5843         struct vcpu_vmx *vmx = to_vmx(vcpu);
5844         gva_t gva;
5845         gpa_t vmptr;
5846         struct vmcs12 *vmcs12;
5847         struct page *page;
5848         struct x86_exception e;
5849
5850         if (!nested_vmx_check_permission(vcpu))
5851                 return 1;
5852
5853         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5854                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5855                 return 1;
5856
5857         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5858                                 sizeof(vmptr), &e)) {
5859                 kvm_inject_page_fault(vcpu, &e);
5860                 return 1;
5861         }
5862
5863         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5864                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5865                 skip_emulated_instruction(vcpu);
5866                 return 1;
5867         }
5868
5869         if (vmptr == vmx->nested.current_vmptr) {
5870                 nested_release_vmcs12(vmx);
5871                 vmx->nested.current_vmptr = -1ull;
5872                 vmx->nested.current_vmcs12 = NULL;
5873         }
5874
5875         page = nested_get_page(vcpu, vmptr);
5876         if (page == NULL) {
5877                 /*
5878                  * For accurate processor emulation, VMCLEAR beyond available
5879                  * physical memory should do nothing at all. However, it is
5880                  * possible that a nested vmx bug, not a guest hypervisor bug,
5881                  * resulted in this case, so let's shut down before doing any
5882                  * more damage:
5883                  */
5884                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5885                 return 1;
5886         }
5887         vmcs12 = kmap(page);
5888         vmcs12->launch_state = 0;
5889         kunmap(page);
5890         nested_release_page(page);
5891
5892         nested_free_vmcs02(vmx, vmptr);
5893
5894         skip_emulated_instruction(vcpu);
5895         nested_vmx_succeed(vcpu);
5896         return 1;
5897 }
5898
5899 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5900
5901 /* Emulate the VMLAUNCH instruction */
5902 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5903 {
5904         return nested_vmx_run(vcpu, true);
5905 }
5906
5907 /* Emulate the VMRESUME instruction */
5908 static int handle_vmresume(struct kvm_vcpu *vcpu)
5909 {
5910
5911         return nested_vmx_run(vcpu, false);
5912 }
5913
5914 enum vmcs_field_type {
5915         VMCS_FIELD_TYPE_U16 = 0,
5916         VMCS_FIELD_TYPE_U64 = 1,
5917         VMCS_FIELD_TYPE_U32 = 2,
5918         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5919 };
5920
5921 static inline int vmcs_field_type(unsigned long field)
5922 {
5923         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5924                 return VMCS_FIELD_TYPE_U32;
5925         return (field >> 13) & 0x3 ;
5926 }
5927
5928 static inline int vmcs_field_readonly(unsigned long field)
5929 {
5930         return (((field >> 10) & 0x3) == 1);
5931 }
5932
5933 /*
5934  * Read a vmcs12 field. Since these can have varying lengths and we return
5935  * one type, we chose the biggest type (u64) and zero-extend the return value
5936  * to that size. Note that the caller, handle_vmread, might need to use only
5937  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5938  * 64-bit fields are to be returned).
5939  */
5940 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5941                                         unsigned long field, u64 *ret)
5942 {
5943         short offset = vmcs_field_to_offset(field);
5944         char *p;
5945
5946         if (offset < 0)
5947                 return 0;
5948
5949         p = ((char *)(get_vmcs12(vcpu))) + offset;
5950
5951         switch (vmcs_field_type(field)) {
5952         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5953                 *ret = *((natural_width *)p);
5954                 return 1;
5955         case VMCS_FIELD_TYPE_U16:
5956                 *ret = *((u16 *)p);
5957                 return 1;
5958         case VMCS_FIELD_TYPE_U32:
5959                 *ret = *((u32 *)p);
5960                 return 1;
5961         case VMCS_FIELD_TYPE_U64:
5962                 *ret = *((u64 *)p);
5963                 return 1;
5964         default:
5965                 return 0; /* can never happen. */
5966         }
5967 }
5968
5969
5970 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5971                                     unsigned long field, u64 field_value){
5972         short offset = vmcs_field_to_offset(field);
5973         char *p = ((char *) get_vmcs12(vcpu)) + offset;
5974         if (offset < 0)
5975                 return false;
5976
5977         switch (vmcs_field_type(field)) {
5978         case VMCS_FIELD_TYPE_U16:
5979                 *(u16 *)p = field_value;
5980                 return true;
5981         case VMCS_FIELD_TYPE_U32:
5982                 *(u32 *)p = field_value;
5983                 return true;
5984         case VMCS_FIELD_TYPE_U64:
5985                 *(u64 *)p = field_value;
5986                 return true;
5987         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5988                 *(natural_width *)p = field_value;
5989                 return true;
5990         default:
5991                 return false; /* can never happen. */
5992         }
5993
5994 }
5995
5996 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5997 {
5998         int i;
5999         unsigned long field;
6000         u64 field_value;
6001         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6002         const unsigned long *fields = shadow_read_write_fields;
6003         const int num_fields = max_shadow_read_write_fields;
6004
6005         vmcs_load(shadow_vmcs);
6006
6007         for (i = 0; i < num_fields; i++) {
6008                 field = fields[i];
6009                 switch (vmcs_field_type(field)) {
6010                 case VMCS_FIELD_TYPE_U16:
6011                         field_value = vmcs_read16(field);
6012                         break;
6013                 case VMCS_FIELD_TYPE_U32:
6014                         field_value = vmcs_read32(field);
6015                         break;
6016                 case VMCS_FIELD_TYPE_U64:
6017                         field_value = vmcs_read64(field);
6018                         break;
6019                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6020                         field_value = vmcs_readl(field);
6021                         break;
6022                 }
6023                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6024         }
6025
6026         vmcs_clear(shadow_vmcs);
6027         vmcs_load(vmx->loaded_vmcs->vmcs);
6028 }
6029
6030 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6031 {
6032         const unsigned long *fields[] = {
6033                 shadow_read_write_fields,
6034                 shadow_read_only_fields
6035         };
6036         const int max_fields[] = {
6037                 max_shadow_read_write_fields,
6038                 max_shadow_read_only_fields
6039         };
6040         int i, q;
6041         unsigned long field;
6042         u64 field_value = 0;
6043         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6044
6045         vmcs_load(shadow_vmcs);
6046
6047         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6048                 for (i = 0; i < max_fields[q]; i++) {
6049                         field = fields[q][i];
6050                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6051
6052                         switch (vmcs_field_type(field)) {
6053                         case VMCS_FIELD_TYPE_U16:
6054                                 vmcs_write16(field, (u16)field_value);
6055                                 break;
6056                         case VMCS_FIELD_TYPE_U32:
6057                                 vmcs_write32(field, (u32)field_value);
6058                                 break;
6059                         case VMCS_FIELD_TYPE_U64:
6060                                 vmcs_write64(field, (u64)field_value);
6061                                 break;
6062                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6063                                 vmcs_writel(field, (long)field_value);
6064                                 break;
6065                         }
6066                 }
6067         }
6068
6069         vmcs_clear(shadow_vmcs);
6070         vmcs_load(vmx->loaded_vmcs->vmcs);
6071 }
6072
6073 /*
6074  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6075  * used before) all generate the same failure when it is missing.
6076  */
6077 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6078 {
6079         struct vcpu_vmx *vmx = to_vmx(vcpu);
6080         if (vmx->nested.current_vmptr == -1ull) {
6081                 nested_vmx_failInvalid(vcpu);
6082                 skip_emulated_instruction(vcpu);
6083                 return 0;
6084         }
6085         return 1;
6086 }
6087
6088 static int handle_vmread(struct kvm_vcpu *vcpu)
6089 {
6090         unsigned long field;
6091         u64 field_value;
6092         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6093         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6094         gva_t gva = 0;
6095
6096         if (!nested_vmx_check_permission(vcpu) ||
6097             !nested_vmx_check_vmcs12(vcpu))
6098                 return 1;
6099
6100         /* Decode instruction info and find the field to read */
6101         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6102         /* Read the field, zero-extended to a u64 field_value */
6103         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6104                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6105                 skip_emulated_instruction(vcpu);
6106                 return 1;
6107         }
6108         /*
6109          * Now copy part of this value to register or memory, as requested.
6110          * Note that the number of bits actually copied is 32 or 64 depending
6111          * on the guest's mode (32 or 64 bit), not on the given field's length.
6112          */
6113         if (vmx_instruction_info & (1u << 10)) {
6114                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6115                         field_value);
6116         } else {
6117                 if (get_vmx_mem_address(vcpu, exit_qualification,
6118                                 vmx_instruction_info, &gva))
6119                         return 1;
6120                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6121                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6122                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6123         }
6124
6125         nested_vmx_succeed(vcpu);
6126         skip_emulated_instruction(vcpu);
6127         return 1;
6128 }
6129
6130
6131 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6132 {
6133         unsigned long field;
6134         gva_t gva;
6135         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6136         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6137         /* The value to write might be 32 or 64 bits, depending on L1's long
6138          * mode, and eventually we need to write that into a field of several
6139          * possible lengths. The code below first zero-extends the value to 64
6140          * bit (field_value), and then copies only the approriate number of
6141          * bits into the vmcs12 field.
6142          */
6143         u64 field_value = 0;
6144         struct x86_exception e;
6145
6146         if (!nested_vmx_check_permission(vcpu) ||
6147             !nested_vmx_check_vmcs12(vcpu))
6148                 return 1;
6149
6150         if (vmx_instruction_info & (1u << 10))
6151                 field_value = kvm_register_read(vcpu,
6152                         (((vmx_instruction_info) >> 3) & 0xf));
6153         else {
6154                 if (get_vmx_mem_address(vcpu, exit_qualification,
6155                                 vmx_instruction_info, &gva))
6156                         return 1;
6157                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6158                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6159                         kvm_inject_page_fault(vcpu, &e);
6160                         return 1;
6161                 }
6162         }
6163
6164
6165         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6166         if (vmcs_field_readonly(field)) {
6167                 nested_vmx_failValid(vcpu,
6168                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6169                 skip_emulated_instruction(vcpu);
6170                 return 1;
6171         }
6172
6173         if (!vmcs12_write_any(vcpu, field, field_value)) {
6174                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6175                 skip_emulated_instruction(vcpu);
6176                 return 1;
6177         }
6178
6179         nested_vmx_succeed(vcpu);
6180         skip_emulated_instruction(vcpu);
6181         return 1;
6182 }
6183
6184 /* Emulate the VMPTRLD instruction */
6185 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6186 {
6187         struct vcpu_vmx *vmx = to_vmx(vcpu);
6188         gva_t gva;
6189         gpa_t vmptr;
6190         struct x86_exception e;
6191         u32 exec_control;
6192
6193         if (!nested_vmx_check_permission(vcpu))
6194                 return 1;
6195
6196         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6197                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6198                 return 1;
6199
6200         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6201                                 sizeof(vmptr), &e)) {
6202                 kvm_inject_page_fault(vcpu, &e);
6203                 return 1;
6204         }
6205
6206         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6207                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6208                 skip_emulated_instruction(vcpu);
6209                 return 1;
6210         }
6211
6212         if (vmx->nested.current_vmptr != vmptr) {
6213                 struct vmcs12 *new_vmcs12;
6214                 struct page *page;
6215                 page = nested_get_page(vcpu, vmptr);
6216                 if (page == NULL) {
6217                         nested_vmx_failInvalid(vcpu);
6218                         skip_emulated_instruction(vcpu);
6219                         return 1;
6220                 }
6221                 new_vmcs12 = kmap(page);
6222                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6223                         kunmap(page);
6224                         nested_release_page_clean(page);
6225                         nested_vmx_failValid(vcpu,
6226                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6227                         skip_emulated_instruction(vcpu);
6228                         return 1;
6229                 }
6230                 if (vmx->nested.current_vmptr != -1ull)
6231                         nested_release_vmcs12(vmx);
6232
6233                 vmx->nested.current_vmptr = vmptr;
6234                 vmx->nested.current_vmcs12 = new_vmcs12;
6235                 vmx->nested.current_vmcs12_page = page;
6236                 if (enable_shadow_vmcs) {
6237                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6238                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6239                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6240                         vmcs_write64(VMCS_LINK_POINTER,
6241                                      __pa(vmx->nested.current_shadow_vmcs));
6242                         vmx->nested.sync_shadow_vmcs = true;
6243                 }
6244         }
6245
6246         nested_vmx_succeed(vcpu);
6247         skip_emulated_instruction(vcpu);
6248         return 1;
6249 }
6250
6251 /* Emulate the VMPTRST instruction */
6252 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6253 {
6254         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6255         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6256         gva_t vmcs_gva;
6257         struct x86_exception e;
6258
6259         if (!nested_vmx_check_permission(vcpu))
6260                 return 1;
6261
6262         if (get_vmx_mem_address(vcpu, exit_qualification,
6263                         vmx_instruction_info, &vmcs_gva))
6264                 return 1;
6265         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6266         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6267                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6268                                  sizeof(u64), &e)) {
6269                 kvm_inject_page_fault(vcpu, &e);
6270                 return 1;
6271         }
6272         nested_vmx_succeed(vcpu);
6273         skip_emulated_instruction(vcpu);
6274         return 1;
6275 }
6276
6277 /*
6278  * The exit handlers return 1 if the exit was handled fully and guest execution
6279  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6280  * to be done to userspace and return 0.
6281  */
6282 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6283         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6284         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6285         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6286         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6287         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6288         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6289         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6290         [EXIT_REASON_CPUID]                   = handle_cpuid,
6291         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6292         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6293         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6294         [EXIT_REASON_HLT]                     = handle_halt,
6295         [EXIT_REASON_INVD]                    = handle_invd,
6296         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6297         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6298         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6299         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6300         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6301         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6302         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6303         [EXIT_REASON_VMREAD]                  = handle_vmread,
6304         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6305         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6306         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6307         [EXIT_REASON_VMON]                    = handle_vmon,
6308         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6309         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6310         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6311         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6312         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6313         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6314         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6315         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6316         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6317         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6318         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6319         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6320         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6321 };
6322
6323 static const int kvm_vmx_max_exit_handlers =
6324         ARRAY_SIZE(kvm_vmx_exit_handlers);
6325
6326 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6327                                        struct vmcs12 *vmcs12)
6328 {
6329         unsigned long exit_qualification;
6330         gpa_t bitmap, last_bitmap;
6331         unsigned int port;
6332         int size;
6333         u8 b;
6334
6335         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6336                 return 1;
6337
6338         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6339                 return 0;
6340
6341         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6342
6343         port = exit_qualification >> 16;
6344         size = (exit_qualification & 7) + 1;
6345
6346         last_bitmap = (gpa_t)-1;
6347         b = -1;
6348
6349         while (size > 0) {
6350                 if (port < 0x8000)
6351                         bitmap = vmcs12->io_bitmap_a;
6352                 else if (port < 0x10000)
6353                         bitmap = vmcs12->io_bitmap_b;
6354                 else
6355                         return 1;
6356                 bitmap += (port & 0x7fff) / 8;
6357
6358                 if (last_bitmap != bitmap)
6359                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6360                                 return 1;
6361                 if (b & (1 << (port & 7)))
6362                         return 1;
6363
6364                 port++;
6365                 size--;
6366                 last_bitmap = bitmap;
6367         }
6368
6369         return 0;
6370 }
6371
6372 /*
6373  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6374  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6375  * disinterest in the current event (read or write a specific MSR) by using an
6376  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6377  */
6378 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6379         struct vmcs12 *vmcs12, u32 exit_reason)
6380 {
6381         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6382         gpa_t bitmap;
6383
6384         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6385                 return 1;
6386
6387         /*
6388          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6389          * for the four combinations of read/write and low/high MSR numbers.
6390          * First we need to figure out which of the four to use:
6391          */
6392         bitmap = vmcs12->msr_bitmap;
6393         if (exit_reason == EXIT_REASON_MSR_WRITE)
6394                 bitmap += 2048;
6395         if (msr_index >= 0xc0000000) {
6396                 msr_index -= 0xc0000000;
6397                 bitmap += 1024;
6398         }
6399
6400         /* Then read the msr_index'th bit from this bitmap: */
6401         if (msr_index < 1024*8) {
6402                 unsigned char b;
6403                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6404                         return 1;
6405                 return 1 & (b >> (msr_index & 7));
6406         } else
6407                 return 1; /* let L1 handle the wrong parameter */
6408 }
6409
6410 /*
6411  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6412  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6413  * intercept (via guest_host_mask etc.) the current event.
6414  */
6415 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6416         struct vmcs12 *vmcs12)
6417 {
6418         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6419         int cr = exit_qualification & 15;
6420         int reg = (exit_qualification >> 8) & 15;
6421         unsigned long val = kvm_register_read(vcpu, reg);
6422
6423         switch ((exit_qualification >> 4) & 3) {
6424         case 0: /* mov to cr */
6425                 switch (cr) {
6426                 case 0:
6427                         if (vmcs12->cr0_guest_host_mask &
6428                             (val ^ vmcs12->cr0_read_shadow))
6429                                 return 1;
6430                         break;
6431                 case 3:
6432                         if ((vmcs12->cr3_target_count >= 1 &&
6433                                         vmcs12->cr3_target_value0 == val) ||
6434                                 (vmcs12->cr3_target_count >= 2 &&
6435                                         vmcs12->cr3_target_value1 == val) ||
6436                                 (vmcs12->cr3_target_count >= 3 &&
6437                                         vmcs12->cr3_target_value2 == val) ||
6438                                 (vmcs12->cr3_target_count >= 4 &&
6439                                         vmcs12->cr3_target_value3 == val))
6440                                 return 0;
6441                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6442                                 return 1;
6443                         break;
6444                 case 4:
6445                         if (vmcs12->cr4_guest_host_mask &
6446                             (vmcs12->cr4_read_shadow ^ val))
6447                                 return 1;
6448                         break;
6449                 case 8:
6450                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6451                                 return 1;
6452                         break;
6453                 }
6454                 break;
6455         case 2: /* clts */
6456                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6457                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6458                         return 1;
6459                 break;
6460         case 1: /* mov from cr */
6461                 switch (cr) {
6462                 case 3:
6463                         if (vmcs12->cpu_based_vm_exec_control &
6464                             CPU_BASED_CR3_STORE_EXITING)
6465                                 return 1;
6466                         break;
6467                 case 8:
6468                         if (vmcs12->cpu_based_vm_exec_control &
6469                             CPU_BASED_CR8_STORE_EXITING)
6470                                 return 1;
6471                         break;
6472                 }
6473                 break;
6474         case 3: /* lmsw */
6475                 /*
6476                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6477                  * cr0. Other attempted changes are ignored, with no exit.
6478                  */
6479                 if (vmcs12->cr0_guest_host_mask & 0xe &
6480                     (val ^ vmcs12->cr0_read_shadow))
6481                         return 1;
6482                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6483                     !(vmcs12->cr0_read_shadow & 0x1) &&
6484                     (val & 0x1))
6485                         return 1;
6486                 break;
6487         }
6488         return 0;
6489 }
6490
6491 /*
6492  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6493  * should handle it ourselves in L0 (and then continue L2). Only call this
6494  * when in is_guest_mode (L2).
6495  */
6496 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6497 {
6498         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6499         struct vcpu_vmx *vmx = to_vmx(vcpu);
6500         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6501         u32 exit_reason = vmx->exit_reason;
6502
6503         if (vmx->nested.nested_run_pending)
6504                 return 0;
6505
6506         if (unlikely(vmx->fail)) {
6507                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6508                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6509                 return 1;
6510         }
6511
6512         switch (exit_reason) {
6513         case EXIT_REASON_EXCEPTION_NMI:
6514                 if (!is_exception(intr_info))
6515                         return 0;
6516                 else if (is_page_fault(intr_info))
6517                         return enable_ept;
6518                 return vmcs12->exception_bitmap &
6519                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6520         case EXIT_REASON_EXTERNAL_INTERRUPT:
6521                 return 0;
6522         case EXIT_REASON_TRIPLE_FAULT:
6523                 return 1;
6524         case EXIT_REASON_PENDING_INTERRUPT:
6525                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6526         case EXIT_REASON_NMI_WINDOW:
6527                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6528         case EXIT_REASON_TASK_SWITCH:
6529                 return 1;
6530         case EXIT_REASON_CPUID:
6531                 return 1;
6532         case EXIT_REASON_HLT:
6533                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6534         case EXIT_REASON_INVD:
6535                 return 1;
6536         case EXIT_REASON_INVLPG:
6537                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6538         case EXIT_REASON_RDPMC:
6539                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6540         case EXIT_REASON_RDTSC:
6541                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6542         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6543         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6544         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6545         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6546         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6547                 /*
6548                  * VMX instructions trap unconditionally. This allows L1 to
6549                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6550                  */
6551                 return 1;
6552         case EXIT_REASON_CR_ACCESS:
6553                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6554         case EXIT_REASON_DR_ACCESS:
6555                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6556         case EXIT_REASON_IO_INSTRUCTION:
6557                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6558         case EXIT_REASON_MSR_READ:
6559         case EXIT_REASON_MSR_WRITE:
6560                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6561         case EXIT_REASON_INVALID_STATE:
6562                 return 1;
6563         case EXIT_REASON_MWAIT_INSTRUCTION:
6564                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6565         case EXIT_REASON_MONITOR_INSTRUCTION:
6566                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6567         case EXIT_REASON_PAUSE_INSTRUCTION:
6568                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6569                         nested_cpu_has2(vmcs12,
6570                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6571         case EXIT_REASON_MCE_DURING_VMENTRY:
6572                 return 0;
6573         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6574                 return 1;
6575         case EXIT_REASON_APIC_ACCESS:
6576                 return nested_cpu_has2(vmcs12,
6577                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6578         case EXIT_REASON_EPT_VIOLATION:
6579         case EXIT_REASON_EPT_MISCONFIG:
6580                 return 0;
6581         case EXIT_REASON_PREEMPTION_TIMER:
6582                 return vmcs12->pin_based_vm_exec_control &
6583                         PIN_BASED_VMX_PREEMPTION_TIMER;
6584         case EXIT_REASON_WBINVD:
6585                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6586         case EXIT_REASON_XSETBV:
6587                 return 1;
6588         default:
6589                 return 1;
6590         }
6591 }
6592
6593 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6594 {
6595         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6596         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6597 }
6598
6599 /*
6600  * The guest has exited.  See if we can fix it or if we need userspace
6601  * assistance.
6602  */
6603 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6604 {
6605         struct vcpu_vmx *vmx = to_vmx(vcpu);
6606         u32 exit_reason = vmx->exit_reason;
6607         u32 vectoring_info = vmx->idt_vectoring_info;
6608
6609         /* If guest state is invalid, start emulating */
6610         if (vmx->emulation_required)
6611                 return handle_invalid_guest_state(vcpu);
6612
6613         /*
6614          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6615          * we did not inject a still-pending event to L1 now because of
6616          * nested_run_pending, we need to re-enable this bit.
6617          */
6618         if (vmx->nested.nested_run_pending)
6619                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6620
6621         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6622             exit_reason == EXIT_REASON_VMRESUME))
6623                 vmx->nested.nested_run_pending = 1;
6624         else
6625                 vmx->nested.nested_run_pending = 0;
6626
6627         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6628                 nested_vmx_vmexit(vcpu);
6629                 return 1;
6630         }
6631
6632         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6633                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6634                 vcpu->run->fail_entry.hardware_entry_failure_reason
6635                         = exit_reason;
6636                 return 0;
6637         }
6638
6639         if (unlikely(vmx->fail)) {
6640                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6641                 vcpu->run->fail_entry.hardware_entry_failure_reason
6642                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6643                 return 0;
6644         }
6645
6646         /*
6647          * Note:
6648          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6649          * delivery event since it indicates guest is accessing MMIO.
6650          * The vm-exit can be triggered again after return to guest that
6651          * will cause infinite loop.
6652          */
6653         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6654                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6655                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6656                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6657                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6658                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6659                 vcpu->run->internal.ndata = 2;
6660                 vcpu->run->internal.data[0] = vectoring_info;
6661                 vcpu->run->internal.data[1] = exit_reason;
6662                 return 0;
6663         }
6664
6665         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6666             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6667                                         get_vmcs12(vcpu), vcpu)))) {
6668                 if (vmx_interrupt_allowed(vcpu)) {
6669                         vmx->soft_vnmi_blocked = 0;
6670                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6671                            vcpu->arch.nmi_pending) {
6672                         /*
6673                          * This CPU don't support us in finding the end of an
6674                          * NMI-blocked window if the guest runs with IRQs
6675                          * disabled. So we pull the trigger after 1 s of
6676                          * futile waiting, but inform the user about this.
6677                          */
6678                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6679                                "state on VCPU %d after 1 s timeout\n",
6680                                __func__, vcpu->vcpu_id);
6681                         vmx->soft_vnmi_blocked = 0;
6682                 }
6683         }
6684
6685         if (exit_reason < kvm_vmx_max_exit_handlers
6686             && kvm_vmx_exit_handlers[exit_reason])
6687                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6688         else {
6689                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6690                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6691         }
6692         return 0;
6693 }
6694
6695 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6696 {
6697         if (irr == -1 || tpr < irr) {
6698                 vmcs_write32(TPR_THRESHOLD, 0);
6699                 return;
6700         }
6701
6702         vmcs_write32(TPR_THRESHOLD, irr);
6703 }
6704
6705 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6706 {
6707         u32 sec_exec_control;
6708
6709         /*
6710          * There is not point to enable virtualize x2apic without enable
6711          * apicv
6712          */
6713         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6714                                 !vmx_vm_has_apicv(vcpu->kvm))
6715                 return;
6716
6717         if (!vm_need_tpr_shadow(vcpu->kvm))
6718                 return;
6719
6720         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6721
6722         if (set) {
6723                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6724                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6725         } else {
6726                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6727                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6728         }
6729         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6730
6731         vmx_set_msr_bitmap(vcpu);
6732 }
6733
6734 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6735 {
6736         u16 status;
6737         u8 old;
6738
6739         if (!vmx_vm_has_apicv(kvm))
6740                 return;
6741
6742         if (isr == -1)
6743                 isr = 0;
6744
6745         status = vmcs_read16(GUEST_INTR_STATUS);
6746         old = status >> 8;
6747         if (isr != old) {
6748                 status &= 0xff;
6749                 status |= isr << 8;
6750                 vmcs_write16(GUEST_INTR_STATUS, status);
6751         }
6752 }
6753
6754 static void vmx_set_rvi(int vector)
6755 {
6756         u16 status;
6757         u8 old;
6758
6759         status = vmcs_read16(GUEST_INTR_STATUS);
6760         old = (u8)status & 0xff;
6761         if ((u8)vector != old) {
6762                 status &= ~0xff;
6763                 status |= (u8)vector;
6764                 vmcs_write16(GUEST_INTR_STATUS, status);
6765         }
6766 }
6767
6768 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6769 {
6770         if (max_irr == -1)
6771                 return;
6772
6773         vmx_set_rvi(max_irr);
6774 }
6775
6776 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6777 {
6778         if (!vmx_vm_has_apicv(vcpu->kvm))
6779                 return;
6780
6781         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6782         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6783         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6784         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6785 }
6786
6787 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6788 {
6789         u32 exit_intr_info;
6790
6791         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6792               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6793                 return;
6794
6795         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6796         exit_intr_info = vmx->exit_intr_info;
6797
6798         /* Handle machine checks before interrupts are enabled */
6799         if (is_machine_check(exit_intr_info))
6800                 kvm_machine_check();
6801
6802         /* We need to handle NMIs before interrupts are enabled */
6803         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6804             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6805                 kvm_before_handle_nmi(&vmx->vcpu);
6806                 asm("int $2");
6807                 kvm_after_handle_nmi(&vmx->vcpu);
6808         }
6809 }
6810
6811 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6812 {
6813         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6814
6815         /*
6816          * If external interrupt exists, IF bit is set in rflags/eflags on the
6817          * interrupt stack frame, and interrupt will be enabled on a return
6818          * from interrupt handler.
6819          */
6820         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6821                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6822                 unsigned int vector;
6823                 unsigned long entry;
6824                 gate_desc *desc;
6825                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6826 #ifdef CONFIG_X86_64
6827                 unsigned long tmp;
6828 #endif
6829
6830                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6831                 desc = (gate_desc *)vmx->host_idt_base + vector;
6832                 entry = gate_offset(*desc);
6833                 asm volatile(
6834 #ifdef CONFIG_X86_64
6835                         "mov %%" _ASM_SP ", %[sp]\n\t"
6836                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6837                         "push $%c[ss]\n\t"
6838                         "push %[sp]\n\t"
6839 #endif
6840                         "pushf\n\t"
6841                         "orl $0x200, (%%" _ASM_SP ")\n\t"
6842                         __ASM_SIZE(push) " $%c[cs]\n\t"
6843                         "call *%[entry]\n\t"
6844                         :
6845 #ifdef CONFIG_X86_64
6846                         [sp]"=&r"(tmp)
6847 #endif
6848                         :
6849                         [entry]"r"(entry),
6850                         [ss]"i"(__KERNEL_DS),
6851                         [cs]"i"(__KERNEL_CS)
6852                         );
6853         } else
6854                 local_irq_enable();
6855 }
6856
6857 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6858 {
6859         u32 exit_intr_info;
6860         bool unblock_nmi;
6861         u8 vector;
6862         bool idtv_info_valid;
6863
6864         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6865
6866         if (cpu_has_virtual_nmis()) {
6867                 if (vmx->nmi_known_unmasked)
6868                         return;
6869                 /*
6870                  * Can't use vmx->exit_intr_info since we're not sure what
6871                  * the exit reason is.
6872                  */
6873                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6874                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6875                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6876                 /*
6877                  * SDM 3: 27.7.1.2 (September 2008)
6878                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6879                  * a guest IRET fault.
6880                  * SDM 3: 23.2.2 (September 2008)
6881                  * Bit 12 is undefined in any of the following cases:
6882                  *  If the VM exit sets the valid bit in the IDT-vectoring
6883                  *   information field.
6884                  *  If the VM exit is due to a double fault.
6885                  */
6886                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6887                     vector != DF_VECTOR && !idtv_info_valid)
6888                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6889                                       GUEST_INTR_STATE_NMI);
6890                 else
6891                         vmx->nmi_known_unmasked =
6892                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6893                                   & GUEST_INTR_STATE_NMI);
6894         } else if (unlikely(vmx->soft_vnmi_blocked))
6895                 vmx->vnmi_blocked_time +=
6896                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6897 }
6898
6899 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6900                                       u32 idt_vectoring_info,
6901                                       int instr_len_field,
6902                                       int error_code_field)
6903 {
6904         u8 vector;
6905         int type;
6906         bool idtv_info_valid;
6907
6908         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6909
6910         vcpu->arch.nmi_injected = false;
6911         kvm_clear_exception_queue(vcpu);
6912         kvm_clear_interrupt_queue(vcpu);
6913
6914         if (!idtv_info_valid)
6915                 return;
6916
6917         kvm_make_request(KVM_REQ_EVENT, vcpu);
6918
6919         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6920         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6921
6922         switch (type) {
6923         case INTR_TYPE_NMI_INTR:
6924                 vcpu->arch.nmi_injected = true;
6925                 /*
6926                  * SDM 3: 27.7.1.2 (September 2008)
6927                  * Clear bit "block by NMI" before VM entry if a NMI
6928                  * delivery faulted.
6929                  */
6930                 vmx_set_nmi_mask(vcpu, false);
6931                 break;
6932         case INTR_TYPE_SOFT_EXCEPTION:
6933                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6934                 /* fall through */
6935         case INTR_TYPE_HARD_EXCEPTION:
6936                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6937                         u32 err = vmcs_read32(error_code_field);
6938                         kvm_queue_exception_e(vcpu, vector, err);
6939                 } else
6940                         kvm_queue_exception(vcpu, vector);
6941                 break;
6942         case INTR_TYPE_SOFT_INTR:
6943                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6944                 /* fall through */
6945         case INTR_TYPE_EXT_INTR:
6946                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6947                 break;
6948         default:
6949                 break;
6950         }
6951 }
6952
6953 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6954 {
6955         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6956                                   VM_EXIT_INSTRUCTION_LEN,
6957                                   IDT_VECTORING_ERROR_CODE);
6958 }
6959
6960 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6961 {
6962         __vmx_complete_interrupts(vcpu,
6963                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6964                                   VM_ENTRY_INSTRUCTION_LEN,
6965                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6966
6967         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6968 }
6969
6970 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6971 {
6972         int i, nr_msrs;
6973         struct perf_guest_switch_msr *msrs;
6974
6975         msrs = perf_guest_get_msrs(&nr_msrs);
6976
6977         if (!msrs)
6978                 return;
6979
6980         for (i = 0; i < nr_msrs; i++)
6981                 if (msrs[i].host == msrs[i].guest)
6982                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6983                 else
6984                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6985                                         msrs[i].host);
6986 }
6987
6988 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6989 {
6990         struct vcpu_vmx *vmx = to_vmx(vcpu);
6991         unsigned long debugctlmsr;
6992
6993         /* Record the guest's net vcpu time for enforced NMI injections. */
6994         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6995                 vmx->entry_time = ktime_get();
6996
6997         /* Don't enter VMX if guest state is invalid, let the exit handler
6998            start emulation until we arrive back to a valid state */
6999         if (vmx->emulation_required)
7000                 return;
7001
7002         if (vmx->nested.sync_shadow_vmcs) {
7003                 copy_vmcs12_to_shadow(vmx);
7004                 vmx->nested.sync_shadow_vmcs = false;
7005         }
7006
7007         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7008                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7009         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7010                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7011
7012         /* When single-stepping over STI and MOV SS, we must clear the
7013          * corresponding interruptibility bits in the guest state. Otherwise
7014          * vmentry fails as it then expects bit 14 (BS) in pending debug
7015          * exceptions being set, but that's not correct for the guest debugging
7016          * case. */
7017         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7018                 vmx_set_interrupt_shadow(vcpu, 0);
7019
7020         atomic_switch_perf_msrs(vmx);
7021         debugctlmsr = get_debugctlmsr();
7022
7023         vmx->__launched = vmx->loaded_vmcs->launched;
7024         asm(
7025                 /* Store host registers */
7026                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7027                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7028                 "push %%" _ASM_CX " \n\t"
7029                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7030                 "je 1f \n\t"
7031                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7032                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7033                 "1: \n\t"
7034                 /* Reload cr2 if changed */
7035                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7036                 "mov %%cr2, %%" _ASM_DX " \n\t"
7037                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7038                 "je 2f \n\t"
7039                 "mov %%" _ASM_AX", %%cr2 \n\t"
7040                 "2: \n\t"
7041                 /* Check if vmlaunch of vmresume is needed */
7042                 "cmpl $0, %c[launched](%0) \n\t"
7043                 /* Load guest registers.  Don't clobber flags. */
7044                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7045                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7046                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7047                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7048                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7049                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7050 #ifdef CONFIG_X86_64
7051                 "mov %c[r8](%0),  %%r8  \n\t"
7052                 "mov %c[r9](%0),  %%r9  \n\t"
7053                 "mov %c[r10](%0), %%r10 \n\t"
7054                 "mov %c[r11](%0), %%r11 \n\t"
7055                 "mov %c[r12](%0), %%r12 \n\t"
7056                 "mov %c[r13](%0), %%r13 \n\t"
7057                 "mov %c[r14](%0), %%r14 \n\t"
7058                 "mov %c[r15](%0), %%r15 \n\t"
7059 #endif
7060                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7061
7062                 /* Enter guest mode */
7063                 "jne 1f \n\t"
7064                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7065                 "jmp 2f \n\t"
7066                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7067                 "2: "
7068                 /* Save guest registers, load host registers, keep flags */
7069                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7070                 "pop %0 \n\t"
7071                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7072                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7073                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7074                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7075                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7076                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7077                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7078 #ifdef CONFIG_X86_64
7079                 "mov %%r8,  %c[r8](%0) \n\t"
7080                 "mov %%r9,  %c[r9](%0) \n\t"
7081                 "mov %%r10, %c[r10](%0) \n\t"
7082                 "mov %%r11, %c[r11](%0) \n\t"
7083                 "mov %%r12, %c[r12](%0) \n\t"
7084                 "mov %%r13, %c[r13](%0) \n\t"
7085                 "mov %%r14, %c[r14](%0) \n\t"
7086                 "mov %%r15, %c[r15](%0) \n\t"
7087 #endif
7088                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7089                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7090
7091                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7092                 "setbe %c[fail](%0) \n\t"
7093                 ".pushsection .rodata \n\t"
7094                 ".global vmx_return \n\t"
7095                 "vmx_return: " _ASM_PTR " 2b \n\t"
7096                 ".popsection"
7097               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7098                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7099                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7100                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7101                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7102                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7103                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7104                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7105                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7106                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7107                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7108 #ifdef CONFIG_X86_64
7109                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7110                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7111                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7112                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7113                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7114                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7115                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7116                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7117 #endif
7118                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7119                 [wordsize]"i"(sizeof(ulong))
7120               : "cc", "memory"
7121 #ifdef CONFIG_X86_64
7122                 , "rax", "rbx", "rdi", "rsi"
7123                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7124 #else
7125                 , "eax", "ebx", "edi", "esi"
7126 #endif
7127               );
7128
7129         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7130         if (debugctlmsr)
7131                 update_debugctlmsr(debugctlmsr);
7132
7133 #ifndef CONFIG_X86_64
7134         /*
7135          * The sysexit path does not restore ds/es, so we must set them to
7136          * a reasonable value ourselves.
7137          *
7138          * We can't defer this to vmx_load_host_state() since that function
7139          * may be executed in interrupt context, which saves and restore segments
7140          * around it, nullifying its effect.
7141          */
7142         loadsegment(ds, __USER_DS);
7143         loadsegment(es, __USER_DS);
7144 #endif
7145
7146         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7147                                   | (1 << VCPU_EXREG_RFLAGS)
7148                                   | (1 << VCPU_EXREG_CPL)
7149                                   | (1 << VCPU_EXREG_PDPTR)
7150                                   | (1 << VCPU_EXREG_SEGMENTS)
7151                                   | (1 << VCPU_EXREG_CR3));
7152         vcpu->arch.regs_dirty = 0;
7153
7154         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7155
7156         vmx->loaded_vmcs->launched = 1;
7157
7158         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7159         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7160
7161         vmx_complete_atomic_exit(vmx);
7162         vmx_recover_nmi_blocking(vmx);
7163         vmx_complete_interrupts(vmx);
7164 }
7165
7166 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7167 {
7168         struct vcpu_vmx *vmx = to_vmx(vcpu);
7169
7170         free_vpid(vmx);
7171         free_nested(vmx);
7172         free_loaded_vmcs(vmx->loaded_vmcs);
7173         kfree(vmx->guest_msrs);
7174         kvm_vcpu_uninit(vcpu);
7175         kmem_cache_free(kvm_vcpu_cache, vmx);
7176 }
7177
7178 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7179 {
7180         int err;
7181         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7182         int cpu;
7183
7184         if (!vmx)
7185                 return ERR_PTR(-ENOMEM);
7186
7187         allocate_vpid(vmx);
7188
7189         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7190         if (err)
7191                 goto free_vcpu;
7192
7193         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7194         err = -ENOMEM;
7195         if (!vmx->guest_msrs) {
7196                 goto uninit_vcpu;
7197         }
7198
7199         vmx->loaded_vmcs = &vmx->vmcs01;
7200         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7201         if (!vmx->loaded_vmcs->vmcs)
7202                 goto free_msrs;
7203         if (!vmm_exclusive)
7204                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7205         loaded_vmcs_init(vmx->loaded_vmcs);
7206         if (!vmm_exclusive)
7207                 kvm_cpu_vmxoff();
7208
7209         cpu = get_cpu();
7210         vmx_vcpu_load(&vmx->vcpu, cpu);
7211         vmx->vcpu.cpu = cpu;
7212         err = vmx_vcpu_setup(vmx);
7213         vmx_vcpu_put(&vmx->vcpu);
7214         put_cpu();
7215         if (err)
7216                 goto free_vmcs;
7217         if (vm_need_virtualize_apic_accesses(kvm)) {
7218                 err = alloc_apic_access_page(kvm);
7219                 if (err)
7220                         goto free_vmcs;
7221         }
7222
7223         if (enable_ept) {
7224                 if (!kvm->arch.ept_identity_map_addr)
7225                         kvm->arch.ept_identity_map_addr =
7226                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7227                 err = -ENOMEM;
7228                 if (alloc_identity_pagetable(kvm) != 0)
7229                         goto free_vmcs;
7230                 if (!init_rmode_identity_map(kvm))
7231                         goto free_vmcs;
7232         }
7233
7234         vmx->nested.current_vmptr = -1ull;
7235         vmx->nested.current_vmcs12 = NULL;
7236
7237         return &vmx->vcpu;
7238
7239 free_vmcs:
7240         free_loaded_vmcs(vmx->loaded_vmcs);
7241 free_msrs:
7242         kfree(vmx->guest_msrs);
7243 uninit_vcpu:
7244         kvm_vcpu_uninit(&vmx->vcpu);
7245 free_vcpu:
7246         free_vpid(vmx);
7247         kmem_cache_free(kvm_vcpu_cache, vmx);
7248         return ERR_PTR(err);
7249 }
7250
7251 static void __init vmx_check_processor_compat(void *rtn)
7252 {
7253         struct vmcs_config vmcs_conf;
7254
7255         *(int *)rtn = 0;
7256         if (setup_vmcs_config(&vmcs_conf) < 0)
7257                 *(int *)rtn = -EIO;
7258         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7259                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7260                                 smp_processor_id());
7261                 *(int *)rtn = -EIO;
7262         }
7263 }
7264
7265 static int get_ept_level(void)
7266 {
7267         return VMX_EPT_DEFAULT_GAW + 1;
7268 }
7269
7270 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7271 {
7272         u64 ret;
7273
7274         /* For VT-d and EPT combination
7275          * 1. MMIO: always map as UC
7276          * 2. EPT with VT-d:
7277          *   a. VT-d without snooping control feature: can't guarantee the
7278          *      result, try to trust guest.
7279          *   b. VT-d with snooping control feature: snooping control feature of
7280          *      VT-d engine can guarantee the cache correctness. Just set it
7281          *      to WB to keep consistent with host. So the same as item 3.
7282          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7283          *    consistent with host MTRR
7284          */
7285         if (is_mmio)
7286                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7287         else if (vcpu->kvm->arch.iommu_domain &&
7288                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7289                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7290                       VMX_EPT_MT_EPTE_SHIFT;
7291         else
7292                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7293                         | VMX_EPT_IPAT_BIT;
7294
7295         return ret;
7296 }
7297
7298 static int vmx_get_lpage_level(void)
7299 {
7300         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7301                 return PT_DIRECTORY_LEVEL;
7302         else
7303                 /* For shadow and EPT supported 1GB page */
7304                 return PT_PDPE_LEVEL;
7305 }
7306
7307 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7308 {
7309         struct kvm_cpuid_entry2 *best;
7310         struct vcpu_vmx *vmx = to_vmx(vcpu);
7311         u32 exec_control;
7312
7313         vmx->rdtscp_enabled = false;
7314         if (vmx_rdtscp_supported()) {
7315                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7316                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7317                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7318                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7319                                 vmx->rdtscp_enabled = true;
7320                         else {
7321                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7322                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7323                                                 exec_control);
7324                         }
7325                 }
7326         }
7327
7328         /* Exposing INVPCID only when PCID is exposed */
7329         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7330         if (vmx_invpcid_supported() &&
7331             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7332             guest_cpuid_has_pcid(vcpu)) {
7333                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7334                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7335                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7336                              exec_control);
7337         } else {
7338                 if (cpu_has_secondary_exec_ctrls()) {
7339                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7340                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7341                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7342                                      exec_control);
7343                 }
7344                 if (best)
7345                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7346         }
7347 }
7348
7349 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7350 {
7351         if (func == 1 && nested)
7352                 entry->ecx |= bit(X86_FEATURE_VMX);
7353 }
7354
7355 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7356                 struct x86_exception *fault)
7357 {
7358         struct vmcs12 *vmcs12;
7359         nested_vmx_vmexit(vcpu);
7360         vmcs12 = get_vmcs12(vcpu);
7361
7362         if (fault->error_code & PFERR_RSVD_MASK)
7363                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7364         else
7365                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7366         vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7367         vmcs12->guest_physical_address = fault->address;
7368 }
7369
7370 /*
7371  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7372  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7373  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7374  * guest in a way that will both be appropriate to L1's requests, and our
7375  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7376  * function also has additional necessary side-effects, like setting various
7377  * vcpu->arch fields.
7378  */
7379 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7380 {
7381         struct vcpu_vmx *vmx = to_vmx(vcpu);
7382         u32 exec_control;
7383
7384         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7385         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7386         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7387         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7388         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7389         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7390         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7391         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7392         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7393         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7394         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7395         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7396         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7397         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7398         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7399         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7400         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7401         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7402         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7403         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7404         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7405         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7406         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7407         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7408         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7409         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7410         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7411         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7412         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7413         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7414         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7415         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7416         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7417         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7418         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7419         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7420
7421         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7422         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7423                 vmcs12->vm_entry_intr_info_field);
7424         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7425                 vmcs12->vm_entry_exception_error_code);
7426         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7427                 vmcs12->vm_entry_instruction_len);
7428         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7429                 vmcs12->guest_interruptibility_info);
7430         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7431         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7432         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7433         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7434                 vmcs12->guest_pending_dbg_exceptions);
7435         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7436         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7437
7438         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7439
7440         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7441                 (vmcs_config.pin_based_exec_ctrl |
7442                  vmcs12->pin_based_vm_exec_control));
7443
7444         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7445                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7446                              vmcs12->vmx_preemption_timer_value);
7447
7448         /*
7449          * Whether page-faults are trapped is determined by a combination of
7450          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7451          * If enable_ept, L0 doesn't care about page faults and we should
7452          * set all of these to L1's desires. However, if !enable_ept, L0 does
7453          * care about (at least some) page faults, and because it is not easy
7454          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7455          * to exit on each and every L2 page fault. This is done by setting
7456          * MASK=MATCH=0 and (see below) EB.PF=1.
7457          * Note that below we don't need special code to set EB.PF beyond the
7458          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7459          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7460          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7461          *
7462          * A problem with this approach (when !enable_ept) is that L1 may be
7463          * injected with more page faults than it asked for. This could have
7464          * caused problems, but in practice existing hypervisors don't care.
7465          * To fix this, we will need to emulate the PFEC checking (on the L1
7466          * page tables), using walk_addr(), when injecting PFs to L1.
7467          */
7468         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7469                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7470         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7471                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7472
7473         if (cpu_has_secondary_exec_ctrls()) {
7474                 u32 exec_control = vmx_secondary_exec_control(vmx);
7475                 if (!vmx->rdtscp_enabled)
7476                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7477                 /* Take the following fields only from vmcs12 */
7478                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7479                 if (nested_cpu_has(vmcs12,
7480                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7481                         exec_control |= vmcs12->secondary_vm_exec_control;
7482
7483                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7484                         /*
7485                          * Translate L1 physical address to host physical
7486                          * address for vmcs02. Keep the page pinned, so this
7487                          * physical address remains valid. We keep a reference
7488                          * to it so we can release it later.
7489                          */
7490                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7491                                 nested_release_page(vmx->nested.apic_access_page);
7492                         vmx->nested.apic_access_page =
7493                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7494                         /*
7495                          * If translation failed, no matter: This feature asks
7496                          * to exit when accessing the given address, and if it
7497                          * can never be accessed, this feature won't do
7498                          * anything anyway.
7499                          */
7500                         if (!vmx->nested.apic_access_page)
7501                                 exec_control &=
7502                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7503                         else
7504                                 vmcs_write64(APIC_ACCESS_ADDR,
7505                                   page_to_phys(vmx->nested.apic_access_page));
7506                 }
7507
7508                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7509         }
7510
7511
7512         /*
7513          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7514          * Some constant fields are set here by vmx_set_constant_host_state().
7515          * Other fields are different per CPU, and will be set later when
7516          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7517          */
7518         vmx_set_constant_host_state(vmx);
7519
7520         /*
7521          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7522          * entry, but only if the current (host) sp changed from the value
7523          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7524          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7525          * here we just force the write to happen on entry.
7526          */
7527         vmx->host_rsp = 0;
7528
7529         exec_control = vmx_exec_control(vmx); /* L0's desires */
7530         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7531         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7532         exec_control &= ~CPU_BASED_TPR_SHADOW;
7533         exec_control |= vmcs12->cpu_based_vm_exec_control;
7534         /*
7535          * Merging of IO and MSR bitmaps not currently supported.
7536          * Rather, exit every time.
7537          */
7538         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7539         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7540         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7541
7542         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7543
7544         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7545          * bitwise-or of what L1 wants to trap for L2, and what we want to
7546          * trap. Note that CR0.TS also needs updating - we do this later.
7547          */
7548         update_exception_bitmap(vcpu);
7549         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7550         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7551
7552         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7553          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7554          * bits are further modified by vmx_set_efer() below.
7555          */
7556         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7557
7558         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7559          * emulated by vmx_set_efer(), below.
7560          */
7561         vmcs_write32(VM_ENTRY_CONTROLS,
7562                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7563                         ~VM_ENTRY_IA32E_MODE) |
7564                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7565
7566         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7567                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7568         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7569                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7570
7571
7572         set_cr4_guest_host_mask(vmx);
7573
7574         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7575                 vmcs_write64(TSC_OFFSET,
7576                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7577         else
7578                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7579
7580         if (enable_vpid) {
7581                 /*
7582                  * Trivially support vpid by letting L2s share their parent
7583                  * L1's vpid. TODO: move to a more elaborate solution, giving
7584                  * each L2 its own vpid and exposing the vpid feature to L1.
7585                  */
7586                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7587                 vmx_flush_tlb(vcpu);
7588         }
7589
7590         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7591                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7592         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7593                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7594         else
7595                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7596         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7597         vmx_set_efer(vcpu, vcpu->arch.efer);
7598
7599         /*
7600          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7601          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7602          * The CR0_READ_SHADOW is what L2 should have expected to read given
7603          * the specifications by L1; It's not enough to take
7604          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7605          * have more bits than L1 expected.
7606          */
7607         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7608         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7609
7610         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7611         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7612
7613         /* shadow page tables on either EPT or shadow page tables */
7614         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7615         kvm_mmu_reset_context(vcpu);
7616
7617         /*
7618          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7619          */
7620         if (enable_ept) {
7621                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7622                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7623                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7624                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7625         }
7626
7627         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7628         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7629 }
7630
7631 /*
7632  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7633  * for running an L2 nested guest.
7634  */
7635 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7636 {
7637         struct vmcs12 *vmcs12;
7638         struct vcpu_vmx *vmx = to_vmx(vcpu);
7639         int cpu;
7640         struct loaded_vmcs *vmcs02;
7641         bool ia32e;
7642
7643         if (!nested_vmx_check_permission(vcpu) ||
7644             !nested_vmx_check_vmcs12(vcpu))
7645                 return 1;
7646
7647         skip_emulated_instruction(vcpu);
7648         vmcs12 = get_vmcs12(vcpu);
7649
7650         if (enable_shadow_vmcs)
7651                 copy_shadow_to_vmcs12(vmx);
7652
7653         /*
7654          * The nested entry process starts with enforcing various prerequisites
7655          * on vmcs12 as required by the Intel SDM, and act appropriately when
7656          * they fail: As the SDM explains, some conditions should cause the
7657          * instruction to fail, while others will cause the instruction to seem
7658          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7659          * To speed up the normal (success) code path, we should avoid checking
7660          * for misconfigurations which will anyway be caught by the processor
7661          * when using the merged vmcs02.
7662          */
7663         if (vmcs12->launch_state == launch) {
7664                 nested_vmx_failValid(vcpu,
7665                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7666                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7667                 return 1;
7668         }
7669
7670         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7671                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7672                 return 1;
7673         }
7674
7675         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7676                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7677                 /*TODO: Also verify bits beyond physical address width are 0*/
7678                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7679                 return 1;
7680         }
7681
7682         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7683                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7684                 /*TODO: Also verify bits beyond physical address width are 0*/
7685                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7686                 return 1;
7687         }
7688
7689         if (vmcs12->vm_entry_msr_load_count > 0 ||
7690             vmcs12->vm_exit_msr_load_count > 0 ||
7691             vmcs12->vm_exit_msr_store_count > 0) {
7692                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7693                                     __func__);
7694                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7695                 return 1;
7696         }
7697
7698         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7699               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7700             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7701               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7702             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7703               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7704             !vmx_control_verify(vmcs12->vm_exit_controls,
7705               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7706             !vmx_control_verify(vmcs12->vm_entry_controls,
7707               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7708         {
7709                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7710                 return 1;
7711         }
7712
7713         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7714             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7715                 nested_vmx_failValid(vcpu,
7716                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7717                 return 1;
7718         }
7719
7720         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7721             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7722                 nested_vmx_entry_failure(vcpu, vmcs12,
7723                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7724                 return 1;
7725         }
7726         if (vmcs12->vmcs_link_pointer != -1ull) {
7727                 nested_vmx_entry_failure(vcpu, vmcs12,
7728                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7729                 return 1;
7730         }
7731
7732         /*
7733          * If the load IA32_EFER VM-entry control is 1, the following checks
7734          * are performed on the field for the IA32_EFER MSR:
7735          * - Bits reserved in the IA32_EFER MSR must be 0.
7736          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7737          *   the IA-32e mode guest VM-exit control. It must also be identical
7738          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7739          *   CR0.PG) is 1.
7740          */
7741         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7742                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7743                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7744                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7745                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7746                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7747                         nested_vmx_entry_failure(vcpu, vmcs12,
7748                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7749                         return 1;
7750                 }
7751         }
7752
7753         /*
7754          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7755          * IA32_EFER MSR must be 0 in the field for that register. In addition,
7756          * the values of the LMA and LME bits in the field must each be that of
7757          * the host address-space size VM-exit control.
7758          */
7759         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7760                 ia32e = (vmcs12->vm_exit_controls &
7761                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7762                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7763                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7764                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7765                         nested_vmx_entry_failure(vcpu, vmcs12,
7766                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7767                         return 1;
7768                 }
7769         }
7770
7771         /*
7772          * We're finally done with prerequisite checking, and can start with
7773          * the nested entry.
7774          */
7775
7776         vmcs02 = nested_get_current_vmcs02(vmx);
7777         if (!vmcs02)
7778                 return -ENOMEM;
7779
7780         enter_guest_mode(vcpu);
7781
7782         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7783
7784         cpu = get_cpu();
7785         vmx->loaded_vmcs = vmcs02;
7786         vmx_vcpu_put(vcpu);
7787         vmx_vcpu_load(vcpu, cpu);
7788         vcpu->cpu = cpu;
7789         put_cpu();
7790
7791         vmx_segment_cache_clear(vmx);
7792
7793         vmcs12->launch_state = 1;
7794
7795         prepare_vmcs02(vcpu, vmcs12);
7796
7797         /*
7798          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7799          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7800          * returned as far as L1 is concerned. It will only return (and set
7801          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7802          */
7803         return 1;
7804 }
7805
7806 /*
7807  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7808  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7809  * This function returns the new value we should put in vmcs12.guest_cr0.
7810  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7811  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7812  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7813  *     didn't trap the bit, because if L1 did, so would L0).
7814  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7815  *     been modified by L2, and L1 knows it. So just leave the old value of
7816  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7817  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7818  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7819  *     changed these bits, and therefore they need to be updated, but L0
7820  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7821  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7822  */
7823 static inline unsigned long
7824 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7825 {
7826         return
7827         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7828         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7829         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7830                         vcpu->arch.cr0_guest_owned_bits));
7831 }
7832
7833 static inline unsigned long
7834 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7835 {
7836         return
7837         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7838         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7839         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7840                         vcpu->arch.cr4_guest_owned_bits));
7841 }
7842
7843 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7844                                        struct vmcs12 *vmcs12)
7845 {
7846         u32 idt_vectoring;
7847         unsigned int nr;
7848
7849         if (vcpu->arch.exception.pending) {
7850                 nr = vcpu->arch.exception.nr;
7851                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7852
7853                 if (kvm_exception_is_soft(nr)) {
7854                         vmcs12->vm_exit_instruction_len =
7855                                 vcpu->arch.event_exit_inst_len;
7856                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7857                 } else
7858                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7859
7860                 if (vcpu->arch.exception.has_error_code) {
7861                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7862                         vmcs12->idt_vectoring_error_code =
7863                                 vcpu->arch.exception.error_code;
7864                 }
7865
7866                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7867         } else if (vcpu->arch.nmi_pending) {
7868                 vmcs12->idt_vectoring_info_field =
7869                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7870         } else if (vcpu->arch.interrupt.pending) {
7871                 nr = vcpu->arch.interrupt.nr;
7872                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7873
7874                 if (vcpu->arch.interrupt.soft) {
7875                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
7876                         vmcs12->vm_entry_instruction_len =
7877                                 vcpu->arch.event_exit_inst_len;
7878                 } else
7879                         idt_vectoring |= INTR_TYPE_EXT_INTR;
7880
7881                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7882         }
7883 }
7884
7885 /*
7886  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7887  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7888  * and this function updates it to reflect the changes to the guest state while
7889  * L2 was running (and perhaps made some exits which were handled directly by L0
7890  * without going back to L1), and to reflect the exit reason.
7891  * Note that we do not have to copy here all VMCS fields, just those that
7892  * could have changed by the L2 guest or the exit - i.e., the guest-state and
7893  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7894  * which already writes to vmcs12 directly.
7895  */
7896 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7897 {
7898         /* update guest state fields: */
7899         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7900         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7901
7902         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7903         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7904         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7905         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7906
7907         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7908         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7909         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7910         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7911         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7912         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7913         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7914         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7915         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7916         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7917         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7918         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7919         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7920         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7921         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7922         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7923         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7924         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7925         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7926         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7927         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7928         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7929         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7930         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7931         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7932         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7933         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7934         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7935         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7936         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7937         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7938         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7939         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7940         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7941         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7942         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7943
7944         vmcs12->guest_interruptibility_info =
7945                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7946         vmcs12->guest_pending_dbg_exceptions =
7947                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7948
7949         /*
7950          * In some cases (usually, nested EPT), L2 is allowed to change its
7951          * own CR3 without exiting. If it has changed it, we must keep it.
7952          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
7953          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
7954          *
7955          * Additionally, restore L2's PDPTR to vmcs12.
7956          */
7957         if (enable_ept) {
7958                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
7959                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
7960                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
7961                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
7962                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
7963         }
7964
7965         vmcs12->vm_entry_controls =
7966                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7967                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7968
7969         /* TODO: These cannot have changed unless we have MSR bitmaps and
7970          * the relevant bit asks not to trap the change */
7971         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7972         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
7973                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7974         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7975         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7976         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7977
7978         /* update exit information fields: */
7979
7980         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
7981         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7982
7983         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7984         if ((vmcs12->vm_exit_intr_info &
7985              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7986             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7987                 vmcs12->vm_exit_intr_error_code =
7988                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7989         vmcs12->idt_vectoring_info_field = 0;
7990         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7991         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7992
7993         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7994                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7995                  * instead of reading the real value. */
7996                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7997
7998                 /*
7999                  * Transfer the event that L0 or L1 may wanted to inject into
8000                  * L2 to IDT_VECTORING_INFO_FIELD.
8001                  */
8002                 vmcs12_save_pending_event(vcpu, vmcs12);
8003         }
8004
8005         /*
8006          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8007          * preserved above and would only end up incorrectly in L1.
8008          */
8009         vcpu->arch.nmi_injected = false;
8010         kvm_clear_exception_queue(vcpu);
8011         kvm_clear_interrupt_queue(vcpu);
8012 }
8013
8014 /*
8015  * A part of what we need to when the nested L2 guest exits and we want to
8016  * run its L1 parent, is to reset L1's guest state to the host state specified
8017  * in vmcs12.
8018  * This function is to be called not only on normal nested exit, but also on
8019  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8020  * Failures During or After Loading Guest State").
8021  * This function should be called when the active VMCS is L1's (vmcs01).
8022  */
8023 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8024                                    struct vmcs12 *vmcs12)
8025 {
8026         struct kvm_segment seg;
8027
8028         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8029                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8030         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8031                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8032         else
8033                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8034         vmx_set_efer(vcpu, vcpu->arch.efer);
8035
8036         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8037         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8038         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8039         /*
8040          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8041          * actually changed, because it depends on the current state of
8042          * fpu_active (which may have changed).
8043          * Note that vmx_set_cr0 refers to efer set above.
8044          */
8045         kvm_set_cr0(vcpu, vmcs12->host_cr0);
8046         /*
8047          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8048          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8049          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8050          */
8051         update_exception_bitmap(vcpu);
8052         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8053         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8054
8055         /*
8056          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8057          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8058          */
8059         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8060         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8061
8062         /* shadow page tables on either EPT or shadow page tables */
8063         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8064         kvm_mmu_reset_context(vcpu);
8065
8066         if (enable_vpid) {
8067                 /*
8068                  * Trivially support vpid by letting L2s share their parent
8069                  * L1's vpid. TODO: move to a more elaborate solution, giving
8070                  * each L2 its own vpid and exposing the vpid feature to L1.
8071                  */
8072                 vmx_flush_tlb(vcpu);
8073         }
8074
8075
8076         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8077         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8078         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8079         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8080         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8081
8082         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8083                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8084         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8085                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8086                         vmcs12->host_ia32_perf_global_ctrl);
8087
8088         /* Set L1 segment info according to Intel SDM
8089             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8090         seg = (struct kvm_segment) {
8091                 .base = 0,
8092                 .limit = 0xFFFFFFFF,
8093                 .selector = vmcs12->host_cs_selector,
8094                 .type = 11,
8095                 .present = 1,
8096                 .s = 1,
8097                 .g = 1
8098         };
8099         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8100                 seg.l = 1;
8101         else
8102                 seg.db = 1;
8103         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8104         seg = (struct kvm_segment) {
8105                 .base = 0,
8106                 .limit = 0xFFFFFFFF,
8107                 .type = 3,
8108                 .present = 1,
8109                 .s = 1,
8110                 .db = 1,
8111                 .g = 1
8112         };
8113         seg.selector = vmcs12->host_ds_selector;
8114         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8115         seg.selector = vmcs12->host_es_selector;
8116         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8117         seg.selector = vmcs12->host_ss_selector;
8118         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8119         seg.selector = vmcs12->host_fs_selector;
8120         seg.base = vmcs12->host_fs_base;
8121         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8122         seg.selector = vmcs12->host_gs_selector;
8123         seg.base = vmcs12->host_gs_base;
8124         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8125         seg = (struct kvm_segment) {
8126                 .base = vmcs12->host_tr_base,
8127                 .limit = 0x67,
8128                 .selector = vmcs12->host_tr_selector,
8129                 .type = 11,
8130                 .present = 1
8131         };
8132         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8133
8134         kvm_set_dr(vcpu, 7, 0x400);
8135         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8136 }
8137
8138 /*
8139  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8140  * and modify vmcs12 to make it see what it would expect to see there if
8141  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8142  */
8143 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8144 {
8145         struct vcpu_vmx *vmx = to_vmx(vcpu);
8146         int cpu;
8147         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8148
8149         /* trying to cancel vmlaunch/vmresume is a bug */
8150         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8151
8152         leave_guest_mode(vcpu);
8153         prepare_vmcs12(vcpu, vmcs12);
8154
8155         cpu = get_cpu();
8156         vmx->loaded_vmcs = &vmx->vmcs01;
8157         vmx_vcpu_put(vcpu);
8158         vmx_vcpu_load(vcpu, cpu);
8159         vcpu->cpu = cpu;
8160         put_cpu();
8161
8162         vmx_segment_cache_clear(vmx);
8163
8164         /* if no vmcs02 cache requested, remove the one we used */
8165         if (VMCS02_POOL_SIZE == 0)
8166                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8167
8168         load_vmcs12_host_state(vcpu, vmcs12);
8169
8170         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8171         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8172
8173         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8174         vmx->host_rsp = 0;
8175
8176         /* Unpin physical memory we referred to in vmcs02 */
8177         if (vmx->nested.apic_access_page) {
8178                 nested_release_page(vmx->nested.apic_access_page);
8179                 vmx->nested.apic_access_page = 0;
8180         }
8181
8182         /*
8183          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8184          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8185          * success or failure flag accordingly.
8186          */
8187         if (unlikely(vmx->fail)) {
8188                 vmx->fail = 0;
8189                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8190         } else
8191                 nested_vmx_succeed(vcpu);
8192         if (enable_shadow_vmcs)
8193                 vmx->nested.sync_shadow_vmcs = true;
8194 }
8195
8196 /*
8197  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8198  * 23.7 "VM-entry failures during or after loading guest state" (this also
8199  * lists the acceptable exit-reason and exit-qualification parameters).
8200  * It should only be called before L2 actually succeeded to run, and when
8201  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8202  */
8203 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8204                         struct vmcs12 *vmcs12,
8205                         u32 reason, unsigned long qualification)
8206 {
8207         load_vmcs12_host_state(vcpu, vmcs12);
8208         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8209         vmcs12->exit_qualification = qualification;
8210         nested_vmx_succeed(vcpu);
8211         if (enable_shadow_vmcs)
8212                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8213 }
8214
8215 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8216                                struct x86_instruction_info *info,
8217                                enum x86_intercept_stage stage)
8218 {
8219         return X86EMUL_CONTINUE;
8220 }
8221
8222 static struct kvm_x86_ops vmx_x86_ops = {
8223         .cpu_has_kvm_support = cpu_has_kvm_support,
8224         .disabled_by_bios = vmx_disabled_by_bios,
8225         .hardware_setup = hardware_setup,
8226         .hardware_unsetup = hardware_unsetup,
8227         .check_processor_compatibility = vmx_check_processor_compat,
8228         .hardware_enable = hardware_enable,
8229         .hardware_disable = hardware_disable,
8230         .cpu_has_accelerated_tpr = report_flexpriority,
8231
8232         .vcpu_create = vmx_create_vcpu,
8233         .vcpu_free = vmx_free_vcpu,
8234         .vcpu_reset = vmx_vcpu_reset,
8235
8236         .prepare_guest_switch = vmx_save_host_state,
8237         .vcpu_load = vmx_vcpu_load,
8238         .vcpu_put = vmx_vcpu_put,
8239
8240         .update_db_bp_intercept = update_exception_bitmap,
8241         .get_msr = vmx_get_msr,
8242         .set_msr = vmx_set_msr,
8243         .get_segment_base = vmx_get_segment_base,
8244         .get_segment = vmx_get_segment,
8245         .set_segment = vmx_set_segment,
8246         .get_cpl = vmx_get_cpl,
8247         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8248         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8249         .decache_cr3 = vmx_decache_cr3,
8250         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8251         .set_cr0 = vmx_set_cr0,
8252         .set_cr3 = vmx_set_cr3,
8253         .set_cr4 = vmx_set_cr4,
8254         .set_efer = vmx_set_efer,
8255         .get_idt = vmx_get_idt,
8256         .set_idt = vmx_set_idt,
8257         .get_gdt = vmx_get_gdt,
8258         .set_gdt = vmx_set_gdt,
8259         .set_dr7 = vmx_set_dr7,
8260         .cache_reg = vmx_cache_reg,
8261         .get_rflags = vmx_get_rflags,
8262         .set_rflags = vmx_set_rflags,
8263         .fpu_activate = vmx_fpu_activate,
8264         .fpu_deactivate = vmx_fpu_deactivate,
8265
8266         .tlb_flush = vmx_flush_tlb,
8267
8268         .run = vmx_vcpu_run,
8269         .handle_exit = vmx_handle_exit,
8270         .skip_emulated_instruction = skip_emulated_instruction,
8271         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8272         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8273         .patch_hypercall = vmx_patch_hypercall,
8274         .set_irq = vmx_inject_irq,
8275         .set_nmi = vmx_inject_nmi,
8276         .queue_exception = vmx_queue_exception,
8277         .cancel_injection = vmx_cancel_injection,
8278         .interrupt_allowed = vmx_interrupt_allowed,
8279         .nmi_allowed = vmx_nmi_allowed,
8280         .get_nmi_mask = vmx_get_nmi_mask,
8281         .set_nmi_mask = vmx_set_nmi_mask,
8282         .enable_nmi_window = enable_nmi_window,
8283         .enable_irq_window = enable_irq_window,
8284         .update_cr8_intercept = update_cr8_intercept,
8285         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8286         .vm_has_apicv = vmx_vm_has_apicv,
8287         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8288         .hwapic_irr_update = vmx_hwapic_irr_update,
8289         .hwapic_isr_update = vmx_hwapic_isr_update,
8290         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8291         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8292
8293         .set_tss_addr = vmx_set_tss_addr,
8294         .get_tdp_level = get_ept_level,
8295         .get_mt_mask = vmx_get_mt_mask,
8296
8297         .get_exit_info = vmx_get_exit_info,
8298
8299         .get_lpage_level = vmx_get_lpage_level,
8300
8301         .cpuid_update = vmx_cpuid_update,
8302
8303         .rdtscp_supported = vmx_rdtscp_supported,
8304         .invpcid_supported = vmx_invpcid_supported,
8305
8306         .set_supported_cpuid = vmx_set_supported_cpuid,
8307
8308         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8309
8310         .set_tsc_khz = vmx_set_tsc_khz,
8311         .read_tsc_offset = vmx_read_tsc_offset,
8312         .write_tsc_offset = vmx_write_tsc_offset,
8313         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8314         .compute_tsc_offset = vmx_compute_tsc_offset,
8315         .read_l1_tsc = vmx_read_l1_tsc,
8316
8317         .set_tdp_cr3 = vmx_set_cr3,
8318
8319         .check_intercept = vmx_check_intercept,
8320         .handle_external_intr = vmx_handle_external_intr,
8321 };
8322
8323 static int __init vmx_init(void)
8324 {
8325         int r, i, msr;
8326
8327         rdmsrl_safe(MSR_EFER, &host_efer);
8328
8329         for (i = 0; i < NR_VMX_MSR; ++i)
8330                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8331
8332         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8333         if (!vmx_io_bitmap_a)
8334                 return -ENOMEM;
8335
8336         r = -ENOMEM;
8337
8338         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8339         if (!vmx_io_bitmap_b)
8340                 goto out;
8341
8342         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8343         if (!vmx_msr_bitmap_legacy)
8344                 goto out1;
8345
8346         vmx_msr_bitmap_legacy_x2apic =
8347                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8348         if (!vmx_msr_bitmap_legacy_x2apic)
8349                 goto out2;
8350
8351         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8352         if (!vmx_msr_bitmap_longmode)
8353                 goto out3;
8354
8355         vmx_msr_bitmap_longmode_x2apic =
8356                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8357         if (!vmx_msr_bitmap_longmode_x2apic)
8358                 goto out4;
8359         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8360         if (!vmx_vmread_bitmap)
8361                 goto out5;
8362
8363         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8364         if (!vmx_vmwrite_bitmap)
8365                 goto out6;
8366
8367         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8368         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8369         /* shadowed read/write fields */
8370         for (i = 0; i < max_shadow_read_write_fields; i++) {
8371                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8372                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8373         }
8374         /* shadowed read only fields */
8375         for (i = 0; i < max_shadow_read_only_fields; i++)
8376                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8377
8378         /*
8379          * Allow direct access to the PC debug port (it is often used for I/O
8380          * delays, but the vmexits simply slow things down).
8381          */
8382         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8383         clear_bit(0x80, vmx_io_bitmap_a);
8384
8385         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8386
8387         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8388         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8389
8390         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8391
8392         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8393                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8394         if (r)
8395                 goto out7;
8396
8397 #ifdef CONFIG_KEXEC
8398         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8399                            crash_vmclear_local_loaded_vmcss);
8400 #endif
8401
8402         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8403         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8404         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8405         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8406         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8407         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8408         memcpy(vmx_msr_bitmap_legacy_x2apic,
8409                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8410         memcpy(vmx_msr_bitmap_longmode_x2apic,
8411                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8412
8413         if (enable_apicv) {
8414                 for (msr = 0x800; msr <= 0x8ff; msr++)
8415                         vmx_disable_intercept_msr_read_x2apic(msr);
8416
8417                 /* According SDM, in x2apic mode, the whole id reg is used.
8418                  * But in KVM, it only use the highest eight bits. Need to
8419                  * intercept it */
8420                 vmx_enable_intercept_msr_read_x2apic(0x802);
8421                 /* TMCCT */
8422                 vmx_enable_intercept_msr_read_x2apic(0x839);
8423                 /* TPR */
8424                 vmx_disable_intercept_msr_write_x2apic(0x808);
8425                 /* EOI */
8426                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8427                 /* SELF-IPI */
8428                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8429         }
8430
8431         if (enable_ept) {
8432                 kvm_mmu_set_mask_ptes(0ull,
8433                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8434                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8435                         0ull, VMX_EPT_EXECUTABLE_MASK);
8436                 ept_set_mmio_spte_mask();
8437                 kvm_enable_tdp();
8438         } else
8439                 kvm_disable_tdp();
8440
8441         return 0;
8442
8443 out7:
8444         free_page((unsigned long)vmx_vmwrite_bitmap);
8445 out6:
8446         free_page((unsigned long)vmx_vmread_bitmap);
8447 out5:
8448         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8449 out4:
8450         free_page((unsigned long)vmx_msr_bitmap_longmode);
8451 out3:
8452         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8453 out2:
8454         free_page((unsigned long)vmx_msr_bitmap_legacy);
8455 out1:
8456         free_page((unsigned long)vmx_io_bitmap_b);
8457 out:
8458         free_page((unsigned long)vmx_io_bitmap_a);
8459         return r;
8460 }
8461
8462 static void __exit vmx_exit(void)
8463 {
8464         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8465         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8466         free_page((unsigned long)vmx_msr_bitmap_legacy);
8467         free_page((unsigned long)vmx_msr_bitmap_longmode);
8468         free_page((unsigned long)vmx_io_bitmap_b);
8469         free_page((unsigned long)vmx_io_bitmap_a);
8470         free_page((unsigned long)vmx_vmwrite_bitmap);
8471         free_page((unsigned long)vmx_vmread_bitmap);
8472
8473 #ifdef CONFIG_KEXEC
8474         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8475         synchronize_rcu();
8476 #endif
8477
8478         kvm_exit();
8479 }
8480
8481 module_init(vmx_init)
8482 module_exit(vmx_exit)