Pileus Git - ~andy/linux/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376 };
 377
 378 #define POSTED_INTR_ON  0
 379 /* Posted-Interrupt Descriptor */
 380 struct pi_desc {
 381         u32 pir[8];     /* Posted interrupt requested */
 382         u32 control;    /* bit 0 of control is outstanding notification bit */
 383         u32 rsvd[7];
 384 } __aligned(64);
 385
 386 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 387 {
 388         return test_and_set_bit(POSTED_INTR_ON,
 389                         (unsigned long *)&pi_desc->control);
 390 }
 391
 392 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 393 {
 394         return test_and_clear_bit(POSTED_INTR_ON,
 395                         (unsigned long *)&pi_desc->control);
 396 }
 397
 398 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 399 {
 400         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 401 }
 402
 403 struct vcpu_vmx {
 404         struct kvm_vcpu       vcpu;
 405         unsigned long         host_rsp;
 406         u8                    fail;
 407         u8                    cpl;
 408         bool                  nmi_known_unmasked;
 409         u32                   exit_intr_info;
 410         u32                   idt_vectoring_info;
 411         ulong                 rflags;
 412         struct shared_msr_entry *guest_msrs;
 413         int                   nmsrs;
 414         int                   save_nmsrs;
 415         unsigned long         host_idt_base;
 416 #ifdef CONFIG_X86_64
 417         u64                   msr_host_kernel_gs_base;
 418         u64                   msr_guest_kernel_gs_base;
 419 #endif
 420         /*
 421          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 422          * non-nested (L1) guest, it always points to vmcs01. For a nested
 423          * guest (L2), it points to a different VMCS.
 424          */
 425         struct loaded_vmcs    vmcs01;
 426         struct loaded_vmcs   *loaded_vmcs;
 427         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 428         struct msr_autoload {
 429                 unsigned nr;
 430                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 431                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 432         } msr_autoload;
 433         struct {
 434                 int           loaded;
 435                 u16           fs_sel, gs_sel, ldt_sel;
 436 #ifdef CONFIG_X86_64
 437                 u16           ds_sel, es_sel;
 438 #endif
 439                 int           gs_ldt_reload_needed;
 440                 int           fs_reload_needed;
 441         } host_state;
 442         struct {
 443                 int vm86_active;
 444                 ulong save_rflags;
 445                 struct kvm_segment segs[8];
 446         } rmode;
 447         struct {
 448                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 449                 struct kvm_save_segment {
 450                         u16 selector;
 451                         unsigned long base;
 452                         u32 limit;
 453                         u32 ar;
 454                 } seg[8];
 455         } segment_cache;
 456         int vpid;
 457         bool emulation_required;
 458
 459         /* Support for vnmi-less CPUs */
 460         int soft_vnmi_blocked;
 461         ktime_t entry_time;
 462         s64 vnmi_blocked_time;
 463         u32 exit_reason;
 464
 465         bool rdtscp_enabled;
 466
 467         /* Posted interrupt descriptor */
 468         struct pi_desc pi_desc;
 469
 470         /* Support for a guest hypervisor (nested VMX) */
 471         struct nested_vmx nested;
 472 };
 473
 474 enum segment_cache_field {
 475         SEG_FIELD_SEL = 0,
 476         SEG_FIELD_BASE = 1,
 477         SEG_FIELD_LIMIT = 2,
 478         SEG_FIELD_AR = 3,
 479
 480         SEG_FIELD_NR = 4
 481 };
 482
 483 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 484 {
 485         return container_of(vcpu, struct vcpu_vmx, vcpu);
 486 }
 487
 488 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 489 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 490 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 491                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 492
 493
 494 static const unsigned long shadow_read_only_fields[] = {
 495         /*
 496          * We do NOT shadow fields that are modified when L0
 497          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 498          * VMXON...) executed by L1.
 499          * For example, VM_INSTRUCTION_ERROR is read
 500          * by L1 if a vmx instruction fails (part of the error path).
 501          * Note the code assumes this logic. If for some reason
 502          * we start shadowing these fields then we need to
 503          * force a shadow sync when L0 emulates vmx instructions
 504          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 505          * by nested_vmx_failValid)
 506          */
 507         VM_EXIT_REASON,
 508         VM_EXIT_INTR_INFO,
 509         VM_EXIT_INSTRUCTION_LEN,
 510         IDT_VECTORING_INFO_FIELD,
 511         IDT_VECTORING_ERROR_CODE,
 512         VM_EXIT_INTR_ERROR_CODE,
 513         EXIT_QUALIFICATION,
 514         GUEST_LINEAR_ADDRESS,
 515         GUEST_PHYSICAL_ADDRESS
 516 };
 517 static const int max_shadow_read_only_fields =
 518         ARRAY_SIZE(shadow_read_only_fields);
 519
 520 static const unsigned long shadow_read_write_fields[] = {
 521         GUEST_RIP,
 522         GUEST_RSP,
 523         GUEST_CR0,
 524         GUEST_CR3,
 525         GUEST_CR4,
 526         GUEST_INTERRUPTIBILITY_INFO,
 527         GUEST_RFLAGS,
 528         GUEST_CS_SELECTOR,
 529         GUEST_CS_AR_BYTES,
 530         GUEST_CS_LIMIT,
 531         GUEST_CS_BASE,
 532         GUEST_ES_BASE,
 533         CR0_GUEST_HOST_MASK,
 534         CR0_READ_SHADOW,
 535         CR4_READ_SHADOW,
 536         TSC_OFFSET,
 537         EXCEPTION_BITMAP,
 538         CPU_BASED_VM_EXEC_CONTROL,
 539         VM_ENTRY_EXCEPTION_ERROR_CODE,
 540         VM_ENTRY_INTR_INFO_FIELD,
 541         VM_ENTRY_INSTRUCTION_LEN,
 542         VM_ENTRY_EXCEPTION_ERROR_CODE,
 543         HOST_FS_BASE,
 544         HOST_GS_BASE,
 545         HOST_FS_SELECTOR,
 546         HOST_GS_SELECTOR
 547 };
 548 static const int max_shadow_read_write_fields =
 549         ARRAY_SIZE(shadow_read_write_fields);
 550
 551 static const unsigned short vmcs_field_to_offset_table[] = {
 552         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 553         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 554         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 555         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 556         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 557         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 558         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 559         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 560         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 561         FIELD(HOST_ES_SELECTOR, host_es_selector),
 562         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 563         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 564         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 565         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 566         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 567         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 568         FIELD64(IO_BITMAP_A, io_bitmap_a),
 569         FIELD64(IO_BITMAP_B, io_bitmap_b),
 570         FIELD64(MSR_BITMAP, msr_bitmap),
 571         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 572         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 573         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 574         FIELD64(TSC_OFFSET, tsc_offset),
 575         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 576         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 577         FIELD64(EPT_POINTER, ept_pointer),
 578         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 579         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 580         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 581         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 582         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 583         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 584         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 585         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 586         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 587         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 588         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 589         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 590         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 591         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 592         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 593         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 594         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 595         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 596         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 597         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 598         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 599         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 600         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 601         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 602         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 603         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 604         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 605         FIELD(TPR_THRESHOLD, tpr_threshold),
 606         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 607         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 608         FIELD(VM_EXIT_REASON, vm_exit_reason),
 609         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 610         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 611         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 612         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 613         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 614         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 615         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 616         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 617         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 618         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 619         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 620         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 621         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 622         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 623         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 624         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 625         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 626         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 627         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 628         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 629         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 630         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 631         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 632         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 633         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 634         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 635         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 636         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 637         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 638         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 639         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 640         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 641         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 642         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 643         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 644         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 645         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 646         FIELD(EXIT_QUALIFICATION, exit_qualification),
 647         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 648         FIELD(GUEST_CR0, guest_cr0),
 649         FIELD(GUEST_CR3, guest_cr3),
 650         FIELD(GUEST_CR4, guest_cr4),
 651         FIELD(GUEST_ES_BASE, guest_es_base),
 652         FIELD(GUEST_CS_BASE, guest_cs_base),
 653         FIELD(GUEST_SS_BASE, guest_ss_base),
 654         FIELD(GUEST_DS_BASE, guest_ds_base),
 655         FIELD(GUEST_FS_BASE, guest_fs_base),
 656         FIELD(GUEST_GS_BASE, guest_gs_base),
 657         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 658         FIELD(GUEST_TR_BASE, guest_tr_base),
 659         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 660         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 661         FIELD(GUEST_DR7, guest_dr7),
 662         FIELD(GUEST_RSP, guest_rsp),
 663         FIELD(GUEST_RIP, guest_rip),
 664         FIELD(GUEST_RFLAGS, guest_rflags),
 665         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 666         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 667         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 668         FIELD(HOST_CR0, host_cr0),
 669         FIELD(HOST_CR3, host_cr3),
 670         FIELD(HOST_CR4, host_cr4),
 671         FIELD(HOST_FS_BASE, host_fs_base),
 672         FIELD(HOST_GS_BASE, host_gs_base),
 673         FIELD(HOST_TR_BASE, host_tr_base),
 674         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 675         FIELD(HOST_IDTR_BASE, host_idtr_base),
 676         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 677         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 678         FIELD(HOST_RSP, host_rsp),
 679         FIELD(HOST_RIP, host_rip),
 680 };
 681 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 682
 683 static inline short vmcs_field_to_offset(unsigned long field)
 684 {
 685         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 686                 return -1;
 687         return vmcs_field_to_offset_table[field];
 688 }
 689
 690 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 691 {
 692         return to_vmx(vcpu)->nested.current_vmcs12;
 693 }
 694
 695 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 696 {
 697         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 698         if (is_error_page(page))
 699                 return NULL;
 700
 701         return page;
 702 }
 703
 704 static void nested_release_page(struct page *page)
 705 {
 706         kvm_release_page_dirty(page);
 707 }
 708
 709 static void nested_release_page_clean(struct page *page)
 710 {
 711         kvm_release_page_clean(page);
 712 }
 713
 714 static u64 construct_eptp(unsigned long root_hpa);
 715 static void kvm_cpu_vmxon(u64 addr);
 716 static void kvm_cpu_vmxoff(void);
 717 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 718 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 719 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 720                             struct kvm_segment *var, int seg);
 721 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 722                             struct kvm_segment *var, int seg);
 723 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 724 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 725 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 726 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 727 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 728
 729 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 730 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 731 /*
 732  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 733  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 734  */
 735 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 736 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 737
 738 static unsigned long *vmx_io_bitmap_a;
 739 static unsigned long *vmx_io_bitmap_b;
 740 static unsigned long *vmx_msr_bitmap_legacy;
 741 static unsigned long *vmx_msr_bitmap_longmode;
 742 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 743 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 744 static unsigned long *vmx_vmread_bitmap;
 745 static unsigned long *vmx_vmwrite_bitmap;
 746
 747 static bool cpu_has_load_ia32_efer;
 748 static bool cpu_has_load_perf_global_ctrl;
 749
 750 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 751 static DEFINE_SPINLOCK(vmx_vpid_lock);
 752
 753 static struct vmcs_config {
 754         int size;
 755         int order;
 756         u32 revision_id;
 757         u32 pin_based_exec_ctrl;
 758         u32 cpu_based_exec_ctrl;
 759         u32 cpu_based_2nd_exec_ctrl;
 760         u32 vmexit_ctrl;
 761         u32 vmentry_ctrl;
 762 } vmcs_config;
 763
 764 static struct vmx_capability {
 765         u32 ept;
 766         u32 vpid;
 767 } vmx_capability;
 768
 769 #define VMX_SEGMENT_FIELD(seg)                                  \
 770         [VCPU_SREG_##seg] = {                                   \
 771                 .selector = GUEST_##seg##_SELECTOR,             \
 772                 .base = GUEST_##seg##_BASE,                     \
 773                 .limit = GUEST_##seg##_LIMIT,                   \
 774                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 775         }
 776
 777 static const struct kvm_vmx_segment_field {
 778         unsigned selector;
 779         unsigned base;
 780         unsigned limit;
 781         unsigned ar_bytes;
 782 } kvm_vmx_segment_fields[] = {
 783         VMX_SEGMENT_FIELD(CS),
 784         VMX_SEGMENT_FIELD(DS),
 785         VMX_SEGMENT_FIELD(ES),
 786         VMX_SEGMENT_FIELD(FS),
 787         VMX_SEGMENT_FIELD(GS),
 788         VMX_SEGMENT_FIELD(SS),
 789         VMX_SEGMENT_FIELD(TR),
 790         VMX_SEGMENT_FIELD(LDTR),
 791 };
 792
 793 static u64 host_efer;
 794
 795 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 796
 797 /*
 798  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 799  * away by decrementing the array size.
 800  */
 801 static const u32 vmx_msr_index[] = {
 802 #ifdef CONFIG_X86_64
 803         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 804 #endif
 805         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 806 };
 807 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 808
 809 static inline bool is_page_fault(u32 intr_info)
 810 {
 811         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 812                              INTR_INFO_VALID_MASK)) ==
 813                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 814 }
 815
 816 static inline bool is_no_device(u32 intr_info)
 817 {
 818         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 819                              INTR_INFO_VALID_MASK)) ==
 820                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 821 }
 822
 823 static inline bool is_invalid_opcode(u32 intr_info)
 824 {
 825         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 826                              INTR_INFO_VALID_MASK)) ==
 827                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 828 }
 829
 830 static inline bool is_external_interrupt(u32 intr_info)
 831 {
 832         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 833                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 834 }
 835
 836 static inline bool is_machine_check(u32 intr_info)
 837 {
 838         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 839                              INTR_INFO_VALID_MASK)) ==
 840                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 841 }
 842
 843 static inline bool cpu_has_vmx_msr_bitmap(void)
 844 {
 845         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 846 }
 847
 848 static inline bool cpu_has_vmx_tpr_shadow(void)
 849 {
 850         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 851 }
 852
 853 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 854 {
 855         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 856 }
 857
 858 static inline bool cpu_has_secondary_exec_ctrls(void)
 859 {
 860         return vmcs_config.cpu_based_exec_ctrl &
 861                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 862 }
 863
 864 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 865 {
 866         return vmcs_config.cpu_based_2nd_exec_ctrl &
 867                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 868 }
 869
 870 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 871 {
 872         return vmcs_config.cpu_based_2nd_exec_ctrl &
 873                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 874 }
 875
 876 static inline bool cpu_has_vmx_apic_register_virt(void)
 877 {
 878         return vmcs_config.cpu_based_2nd_exec_ctrl &
 879                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 880 }
 881
 882 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 883 {
 884         return vmcs_config.cpu_based_2nd_exec_ctrl &
 885                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 886 }
 887
 888 static inline bool cpu_has_vmx_posted_intr(void)
 889 {
 890         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 891 }
 892
 893 static inline bool cpu_has_vmx_apicv(void)
 894 {
 895         return cpu_has_vmx_apic_register_virt() &&
 896                 cpu_has_vmx_virtual_intr_delivery() &&
 897                 cpu_has_vmx_posted_intr();
 898 }
 899
 900 static inline bool cpu_has_vmx_flexpriority(void)
 901 {
 902         return cpu_has_vmx_tpr_shadow() &&
 903                 cpu_has_vmx_virtualize_apic_accesses();
 904 }
 905
 906 static inline bool cpu_has_vmx_ept_execute_only(void)
 907 {
 908         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 909 }
 910
 911 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 912 {
 913         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 914 }
 915
 916 static inline bool cpu_has_vmx_eptp_writeback(void)
 917 {
 918         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 919 }
 920
 921 static inline bool cpu_has_vmx_ept_2m_page(void)
 922 {
 923         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 924 }
 925
 926 static inline bool cpu_has_vmx_ept_1g_page(void)
 927 {
 928         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 929 }
 930
 931 static inline bool cpu_has_vmx_ept_4levels(void)
 932 {
 933         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 934 }
 935
 936 static inline bool cpu_has_vmx_ept_ad_bits(void)
 937 {
 938         return vmx_capability.ept & VMX_EPT_AD_BIT;
 939 }
 940
 941 static inline bool cpu_has_vmx_invept_context(void)
 942 {
 943         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 944 }
 945
 946 static inline bool cpu_has_vmx_invept_global(void)
 947 {
 948         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 949 }
 950
 951 static inline bool cpu_has_vmx_invvpid_single(void)
 952 {
 953         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 954 }
 955
 956 static inline bool cpu_has_vmx_invvpid_global(void)
 957 {
 958         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 959 }
 960
 961 static inline bool cpu_has_vmx_ept(void)
 962 {
 963         return vmcs_config.cpu_based_2nd_exec_ctrl &
 964                 SECONDARY_EXEC_ENABLE_EPT;
 965 }
 966
 967 static inline bool cpu_has_vmx_unrestricted_guest(void)
 968 {
 969         return vmcs_config.cpu_based_2nd_exec_ctrl &
 970                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 971 }
 972
 973 static inline bool cpu_has_vmx_ple(void)
 974 {
 975         return vmcs_config.cpu_based_2nd_exec_ctrl &
 976                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 977 }
 978
 979 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 980 {
 981         return flexpriority_enabled && irqchip_in_kernel(kvm);
 982 }
 983
 984 static inline bool cpu_has_vmx_vpid(void)
 985 {
 986         return vmcs_config.cpu_based_2nd_exec_ctrl &
 987                 SECONDARY_EXEC_ENABLE_VPID;
 988 }
 989
 990 static inline bool cpu_has_vmx_rdtscp(void)
 991 {
 992         return vmcs_config.cpu_based_2nd_exec_ctrl &
 993                 SECONDARY_EXEC_RDTSCP;
 994 }
 995
 996 static inline bool cpu_has_vmx_invpcid(void)
 997 {
 998         return vmcs_config.cpu_based_2nd_exec_ctrl &
 999                 SECONDARY_EXEC_ENABLE_INVPCID;
1000 }
1001
1002 static inline bool cpu_has_virtual_nmis(void)
1003 {
1004         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1005 }
1006
1007 static inline bool cpu_has_vmx_wbinvd_exit(void)
1008 {
1009         return vmcs_config.cpu_based_2nd_exec_ctrl &
1010                 SECONDARY_EXEC_WBINVD_EXITING;
1011 }
1012
1013 static inline bool cpu_has_vmx_shadow_vmcs(void)
1014 {
1015         u64 vmx_msr;
1016         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1017         /* check if the cpu supports writing r/o exit information fields */
1018         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1019                 return false;
1020
1021         return vmcs_config.cpu_based_2nd_exec_ctrl &
1022                 SECONDARY_EXEC_SHADOW_VMCS;
1023 }
1024
1025 static inline bool report_flexpriority(void)
1026 {
1027         return flexpriority_enabled;
1028 }
1029
1030 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1031 {
1032         return vmcs12->cpu_based_vm_exec_control & bit;
1033 }
1034
1035 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1036 {
1037         return (vmcs12->cpu_based_vm_exec_control &
1038                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1039                 (vmcs12->secondary_vm_exec_control & bit);
1040 }
1041
1042 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1043         struct kvm_vcpu *vcpu)
1044 {
1045         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046 }
1047
1048 static inline bool is_exception(u32 intr_info)
1049 {
1050         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1051                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1052 }
1053
1054 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1055 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1056                         struct vmcs12 *vmcs12,
1057                         u32 reason, unsigned long qualification);
1058
1059 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1060 {
1061         int i;
1062
1063         for (i = 0; i < vmx->nmsrs; ++i)
1064                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1065                         return i;
1066         return -1;
1067 }
1068
1069 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1070 {
1071     struct {
1072         u64 vpid : 16;
1073         u64 rsvd : 48;
1074         u64 gva;
1075     } operand = { vpid, 0, gva };
1076
1077     asm volatile (__ex(ASM_VMX_INVVPID)
1078                   /* CF==1 or ZF==1 --> rc = -1 */
1079                   "; ja 1f ; ud2 ; 1:"
1080                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1081 }
1082
1083 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1084 {
1085         struct {
1086                 u64 eptp, gpa;
1087         } operand = {eptp, gpa};
1088
1089         asm volatile (__ex(ASM_VMX_INVEPT)
1090                         /* CF==1 or ZF==1 --> rc = -1 */
1091                         "; ja 1f ; ud2 ; 1:\n"
1092                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1093 }
1094
1095 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1096 {
1097         int i;
1098
1099         i = __find_msr_index(vmx, msr);
1100         if (i >= 0)
1101                 return &vmx->guest_msrs[i];
1102         return NULL;
1103 }
1104
1105 static void vmcs_clear(struct vmcs *vmcs)
1106 {
1107         u64 phys_addr = __pa(vmcs);
1108         u8 error;
1109
1110         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1111                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1112                       : "cc", "memory");
1113         if (error)
1114                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1115                        vmcs, phys_addr);
1116 }
1117
1118 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1119 {
1120         vmcs_clear(loaded_vmcs->vmcs);
1121         loaded_vmcs->cpu = -1;
1122         loaded_vmcs->launched = 0;
1123 }
1124
1125 static void vmcs_load(struct vmcs *vmcs)
1126 {
1127         u64 phys_addr = __pa(vmcs);
1128         u8 error;
1129
1130         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1131                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1132                         : "cc", "memory");
1133         if (error)
1134                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1135                        vmcs, phys_addr);
1136 }
1137
1138 #ifdef CONFIG_KEXEC
1139 /*
1140  * This bitmap is used to indicate whether the vmclear
1141  * operation is enabled on all cpus. All disabled by
1142  * default.
1143  */
1144 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1145
1146 static inline void crash_enable_local_vmclear(int cpu)
1147 {
1148         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1149 }
1150
1151 static inline void crash_disable_local_vmclear(int cpu)
1152 {
1153         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154 }
1155
1156 static inline int crash_local_vmclear_enabled(int cpu)
1157 {
1158         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159 }
1160
1161 static void crash_vmclear_local_loaded_vmcss(void)
1162 {
1163         int cpu = raw_smp_processor_id();
1164         struct loaded_vmcs *v;
1165
1166         if (!crash_local_vmclear_enabled(cpu))
1167                 return;
1168
1169         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1170                             loaded_vmcss_on_cpu_link)
1171                 vmcs_clear(v->vmcs);
1172 }
1173 #else
1174 static inline void crash_enable_local_vmclear(int cpu) { }
1175 static inline void crash_disable_local_vmclear(int cpu) { }
1176 #endif /* CONFIG_KEXEC */
1177
1178 static void __loaded_vmcs_clear(void *arg)
1179 {
1180         struct loaded_vmcs *loaded_vmcs = arg;
1181         int cpu = raw_smp_processor_id();
1182
1183         if (loaded_vmcs->cpu != cpu)
1184                 return; /* vcpu migration can race with cpu offline */
1185         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1186                 per_cpu(current_vmcs, cpu) = NULL;
1187         crash_disable_local_vmclear(cpu);
1188         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1189
1190         /*
1191          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1192          * is before setting loaded_vmcs->vcpu to -1 which is done in
1193          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1194          * then adds the vmcs into percpu list before it is deleted.
1195          */
1196         smp_wmb();
1197
1198         loaded_vmcs_init(loaded_vmcs);
1199         crash_enable_local_vmclear(cpu);
1200 }
1201
1202 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1203 {
1204         int cpu = loaded_vmcs->cpu;
1205
1206         if (cpu != -1)
1207                 smp_call_function_single(cpu,
1208                          __loaded_vmcs_clear, loaded_vmcs, 1);
1209 }
1210
1211 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1212 {
1213         if (vmx->vpid == 0)
1214                 return;
1215
1216         if (cpu_has_vmx_invvpid_single())
1217                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1218 }
1219
1220 static inline void vpid_sync_vcpu_global(void)
1221 {
1222         if (cpu_has_vmx_invvpid_global())
1223                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1224 }
1225
1226 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1227 {
1228         if (cpu_has_vmx_invvpid_single())
1229                 vpid_sync_vcpu_single(vmx);
1230         else
1231                 vpid_sync_vcpu_global();
1232 }
1233
1234 static inline void ept_sync_global(void)
1235 {
1236         if (cpu_has_vmx_invept_global())
1237                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1238 }
1239
1240 static inline void ept_sync_context(u64 eptp)
1241 {
1242         if (enable_ept) {
1243                 if (cpu_has_vmx_invept_context())
1244                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1245                 else
1246                         ept_sync_global();
1247         }
1248 }
1249
1250 static __always_inline unsigned long vmcs_readl(unsigned long field)
1251 {
1252         unsigned long value;
1253
1254         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1255                       : "=a"(value) : "d"(field) : "cc");
1256         return value;
1257 }
1258
1259 static __always_inline u16 vmcs_read16(unsigned long field)
1260 {
1261         return vmcs_readl(field);
1262 }
1263
1264 static __always_inline u32 vmcs_read32(unsigned long field)
1265 {
1266         return vmcs_readl(field);
1267 }
1268
1269 static __always_inline u64 vmcs_read64(unsigned long field)
1270 {
1271 #ifdef CONFIG_X86_64
1272         return vmcs_readl(field);
1273 #else
1274         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1275 #endif
1276 }
1277
1278 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1279 {
1280         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1281                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1282         dump_stack();
1283 }
1284
1285 static void vmcs_writel(unsigned long field, unsigned long value)
1286 {
1287         u8 error;
1288
1289         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1290                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1291         if (unlikely(error))
1292                 vmwrite_error(field, value);
1293 }
1294
1295 static void vmcs_write16(unsigned long field, u16 value)
1296 {
1297         vmcs_writel(field, value);
1298 }
1299
1300 static void vmcs_write32(unsigned long field, u32 value)
1301 {
1302         vmcs_writel(field, value);
1303 }
1304
1305 static void vmcs_write64(unsigned long field, u64 value)
1306 {
1307         vmcs_writel(field, value);
1308 #ifndef CONFIG_X86_64
1309         asm volatile ("");
1310         vmcs_writel(field+1, value >> 32);
1311 #endif
1312 }
1313
1314 static void vmcs_clear_bits(unsigned long field, u32 mask)
1315 {
1316         vmcs_writel(field, vmcs_readl(field) & ~mask);
1317 }
1318
1319 static void vmcs_set_bits(unsigned long field, u32 mask)
1320 {
1321         vmcs_writel(field, vmcs_readl(field) | mask);
1322 }
1323
1324 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1325 {
1326         vmx->segment_cache.bitmask = 0;
1327 }
1328
1329 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1330                                        unsigned field)
1331 {
1332         bool ret;
1333         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1334
1335         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1336                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1337                 vmx->segment_cache.bitmask = 0;
1338         }
1339         ret = vmx->segment_cache.bitmask & mask;
1340         vmx->segment_cache.bitmask |= mask;
1341         return ret;
1342 }
1343
1344 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1345 {
1346         u16 *p = &vmx->segment_cache.seg[seg].selector;
1347
1348         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1349                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1350         return *p;
1351 }
1352
1353 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1354 {
1355         ulong *p = &vmx->segment_cache.seg[seg].base;
1356
1357         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1358                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1359         return *p;
1360 }
1361
1362 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1363 {
1364         u32 *p = &vmx->segment_cache.seg[seg].limit;
1365
1366         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1367                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1368         return *p;
1369 }
1370
1371 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1372 {
1373         u32 *p = &vmx->segment_cache.seg[seg].ar;
1374
1375         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1376                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1377         return *p;
1378 }
1379
1380 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1381 {
1382         u32 eb;
1383
1384         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1385              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1386         if ((vcpu->guest_debug &
1387              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1388             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1389                 eb |= 1u << BP_VECTOR;
1390         if (to_vmx(vcpu)->rmode.vm86_active)
1391                 eb = ~0;
1392         if (enable_ept)
1393                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1394         if (vcpu->fpu_active)
1395                 eb &= ~(1u << NM_VECTOR);
1396
1397         /* When we are running a nested L2 guest and L1 specified for it a
1398          * certain exception bitmap, we must trap the same exceptions and pass
1399          * them to L1. When running L2, we will only handle the exceptions
1400          * specified above if L1 did not want them.
1401          */
1402         if (is_guest_mode(vcpu))
1403                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1404
1405         vmcs_write32(EXCEPTION_BITMAP, eb);
1406 }
1407
1408 static void clear_atomic_switch_msr_special(unsigned long entry,
1409                 unsigned long exit)
1410 {
1411         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1412         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1413 }
1414
1415 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1416 {
1417         unsigned i;
1418         struct msr_autoload *m = &vmx->msr_autoload;
1419
1420         switch (msr) {
1421         case MSR_EFER:
1422                 if (cpu_has_load_ia32_efer) {
1423                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1424                                         VM_EXIT_LOAD_IA32_EFER);
1425                         return;
1426                 }
1427                 break;
1428         case MSR_CORE_PERF_GLOBAL_CTRL:
1429                 if (cpu_has_load_perf_global_ctrl) {
1430                         clear_atomic_switch_msr_special(
1431                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1432                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1433                         return;
1434                 }
1435                 break;
1436         }
1437
1438         for (i = 0; i < m->nr; ++i)
1439                 if (m->guest[i].index == msr)
1440                         break;
1441
1442         if (i == m->nr)
1443                 return;
1444         --m->nr;
1445         m->guest[i] = m->guest[m->nr];
1446         m->host[i] = m->host[m->nr];
1447         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1448         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1449 }
1450
1451 static void add_atomic_switch_msr_special(unsigned long entry,
1452                 unsigned long exit, unsigned long guest_val_vmcs,
1453                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1454 {
1455         vmcs_write64(guest_val_vmcs, guest_val);
1456         vmcs_write64(host_val_vmcs, host_val);
1457         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1458         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1459 }
1460
1461 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1462                                   u64 guest_val, u64 host_val)
1463 {
1464         unsigned i;
1465         struct msr_autoload *m = &vmx->msr_autoload;
1466
1467         switch (msr) {
1468         case MSR_EFER:
1469                 if (cpu_has_load_ia32_efer) {
1470                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1471                                         VM_EXIT_LOAD_IA32_EFER,
1472                                         GUEST_IA32_EFER,
1473                                         HOST_IA32_EFER,
1474                                         guest_val, host_val);
1475                         return;
1476                 }
1477                 break;
1478         case MSR_CORE_PERF_GLOBAL_CTRL:
1479                 if (cpu_has_load_perf_global_ctrl) {
1480                         add_atomic_switch_msr_special(
1481                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1482                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1483                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1484                                         HOST_IA32_PERF_GLOBAL_CTRL,
1485                                         guest_val, host_val);
1486                         return;
1487                 }
1488                 break;
1489         }
1490
1491         for (i = 0; i < m->nr; ++i)
1492                 if (m->guest[i].index == msr)
1493                         break;
1494
1495         if (i == NR_AUTOLOAD_MSRS) {
1496                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1497                                 "Can't add msr %x\n", msr);
1498                 return;
1499         } else if (i == m->nr) {
1500                 ++m->nr;
1501                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1502                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1503         }
1504
1505         m->guest[i].index = msr;
1506         m->guest[i].value = guest_val;
1507         m->host[i].index = msr;
1508         m->host[i].value = host_val;
1509 }
1510
1511 static void reload_tss(void)
1512 {
1513         /*
1514          * VT restores TR but not its size.  Useless.
1515          */
1516         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1517         struct desc_struct *descs;
1518
1519         descs = (void *)gdt->address;
1520         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1521         load_TR_desc();
1522 }
1523
1524 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1525 {
1526         u64 guest_efer;
1527         u64 ignore_bits;
1528
1529         guest_efer = vmx->vcpu.arch.efer;
1530
1531         /*
1532          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1533          * outside long mode
1534          */
1535         ignore_bits = EFER_NX | EFER_SCE;
1536 #ifdef CONFIG_X86_64
1537         ignore_bits |= EFER_LMA | EFER_LME;
1538         /* SCE is meaningful only in long mode on Intel */
1539         if (guest_efer & EFER_LMA)
1540                 ignore_bits &= ~(u64)EFER_SCE;
1541 #endif
1542         guest_efer &= ~ignore_bits;
1543         guest_efer |= host_efer & ignore_bits;
1544         vmx->guest_msrs[efer_offset].data = guest_efer;
1545         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1546
1547         clear_atomic_switch_msr(vmx, MSR_EFER);
1548         /* On ept, can't emulate nx, and must switch nx atomically */
1549         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1550                 guest_efer = vmx->vcpu.arch.efer;
1551                 if (!(guest_efer & EFER_LMA))
1552                         guest_efer &= ~EFER_LME;
1553                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1554                 return false;
1555         }
1556
1557         return true;
1558 }
1559
1560 static unsigned long segment_base(u16 selector)
1561 {
1562         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1563         struct desc_struct *d;
1564         unsigned long table_base;
1565         unsigned long v;
1566
1567         if (!(selector & ~3))
1568                 return 0;
1569
1570         table_base = gdt->address;
1571
1572         if (selector & 4) {           /* from ldt */
1573                 u16 ldt_selector = kvm_read_ldt();
1574
1575                 if (!(ldt_selector & ~3))
1576                         return 0;
1577
1578                 table_base = segment_base(ldt_selector);
1579         }
1580         d = (struct desc_struct *)(table_base + (selector & ~7));
1581         v = get_desc_base(d);
1582 #ifdef CONFIG_X86_64
1583        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1584                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1585 #endif
1586         return v;
1587 }
1588
1589 static inline unsigned long kvm_read_tr_base(void)
1590 {
1591         u16 tr;
1592         asm("str %0" : "=g"(tr));
1593         return segment_base(tr);
1594 }
1595
1596 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1597 {
1598         struct vcpu_vmx *vmx = to_vmx(vcpu);
1599         int i;
1600
1601         if (vmx->host_state.loaded)
1602                 return;
1603
1604         vmx->host_state.loaded = 1;
1605         /*
1606          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1607          * allow segment selectors with cpl > 0 or ti == 1.
1608          */
1609         vmx->host_state.ldt_sel = kvm_read_ldt();
1610         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1611         savesegment(fs, vmx->host_state.fs_sel);
1612         if (!(vmx->host_state.fs_sel & 7)) {
1613                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1614                 vmx->host_state.fs_reload_needed = 0;
1615         } else {
1616                 vmcs_write16(HOST_FS_SELECTOR, 0);
1617                 vmx->host_state.fs_reload_needed = 1;
1618         }
1619         savesegment(gs, vmx->host_state.gs_sel);
1620         if (!(vmx->host_state.gs_sel & 7))
1621                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1622         else {
1623                 vmcs_write16(HOST_GS_SELECTOR, 0);
1624                 vmx->host_state.gs_ldt_reload_needed = 1;
1625         }
1626
1627 #ifdef CONFIG_X86_64
1628         savesegment(ds, vmx->host_state.ds_sel);
1629         savesegment(es, vmx->host_state.es_sel);
1630 #endif
1631
1632 #ifdef CONFIG_X86_64
1633         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1634         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1635 #else
1636         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1637         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1638 #endif
1639
1640 #ifdef CONFIG_X86_64
1641         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1642         if (is_long_mode(&vmx->vcpu))
1643                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1644 #endif
1645         for (i = 0; i < vmx->save_nmsrs; ++i)
1646                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1647                                    vmx->guest_msrs[i].data,
1648                                    vmx->guest_msrs[i].mask);
1649 }
1650
1651 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1652 {
1653         if (!vmx->host_state.loaded)
1654                 return;
1655
1656         ++vmx->vcpu.stat.host_state_reload;
1657         vmx->host_state.loaded = 0;
1658 #ifdef CONFIG_X86_64
1659         if (is_long_mode(&vmx->vcpu))
1660                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1661 #endif
1662         if (vmx->host_state.gs_ldt_reload_needed) {
1663                 kvm_load_ldt(vmx->host_state.ldt_sel);
1664 #ifdef CONFIG_X86_64
1665                 load_gs_index(vmx->host_state.gs_sel);
1666 #else
1667                 loadsegment(gs, vmx->host_state.gs_sel);
1668 #endif
1669         }
1670         if (vmx->host_state.fs_reload_needed)
1671                 loadsegment(fs, vmx->host_state.fs_sel);
1672 #ifdef CONFIG_X86_64
1673         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1674                 loadsegment(ds, vmx->host_state.ds_sel);
1675                 loadsegment(es, vmx->host_state.es_sel);
1676         }
1677 #endif
1678         reload_tss();
1679 #ifdef CONFIG_X86_64
1680         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1681 #endif
1682         /*
1683          * If the FPU is not active (through the host task or
1684          * the guest vcpu), then restore the cr0.TS bit.
1685          */
1686         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1687                 stts();
1688         load_gdt(&__get_cpu_var(host_gdt));
1689 }
1690
1691 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1692 {
1693         preempt_disable();
1694         __vmx_load_host_state(vmx);
1695         preempt_enable();
1696 }
1697
1698 /*
1699  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1700  * vcpu mutex is already taken.
1701  */
1702 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1703 {
1704         struct vcpu_vmx *vmx = to_vmx(vcpu);
1705         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1706
1707         if (!vmm_exclusive)
1708                 kvm_cpu_vmxon(phys_addr);
1709         else if (vmx->loaded_vmcs->cpu != cpu)
1710                 loaded_vmcs_clear(vmx->loaded_vmcs);
1711
1712         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1713                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1714                 vmcs_load(vmx->loaded_vmcs->vmcs);
1715         }
1716
1717         if (vmx->loaded_vmcs->cpu != cpu) {
1718                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1719                 unsigned long sysenter_esp;
1720
1721                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1722                 local_irq_disable();
1723                 crash_disable_local_vmclear(cpu);
1724
1725                 /*
1726                  * Read loaded_vmcs->cpu should be before fetching
1727                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1728                  * See the comments in __loaded_vmcs_clear().
1729                  */
1730                 smp_rmb();
1731
1732                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1733                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1734                 crash_enable_local_vmclear(cpu);
1735                 local_irq_enable();
1736
1737                 /*
1738                  * Linux uses per-cpu TSS and GDT, so set these when switching
1739                  * processors.
1740                  */
1741                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1742                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1743
1744                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1745                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1746                 vmx->loaded_vmcs->cpu = cpu;
1747         }
1748 }
1749
1750 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1751 {
1752         __vmx_load_host_state(to_vmx(vcpu));
1753         if (!vmm_exclusive) {
1754                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1755                 vcpu->cpu = -1;
1756                 kvm_cpu_vmxoff();
1757         }
1758 }
1759
1760 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1761 {
1762         ulong cr0;
1763
1764         if (vcpu->fpu_active)
1765                 return;
1766         vcpu->fpu_active = 1;
1767         cr0 = vmcs_readl(GUEST_CR0);
1768         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1769         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1770         vmcs_writel(GUEST_CR0, cr0);
1771         update_exception_bitmap(vcpu);
1772         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1773         if (is_guest_mode(vcpu))
1774                 vcpu->arch.cr0_guest_owned_bits &=
1775                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1776         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1777 }
1778
1779 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1780
1781 /*
1782  * Return the cr0 value that a nested guest would read. This is a combination
1783  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1784  * its hypervisor (cr0_read_shadow).
1785  */
1786 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1787 {
1788         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1789                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1790 }
1791 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1792 {
1793         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1794                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1795 }
1796
1797 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1798 {
1799         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1800          * set this *before* calling this function.
1801          */
1802         vmx_decache_cr0_guest_bits(vcpu);
1803         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1804         update_exception_bitmap(vcpu);
1805         vcpu->arch.cr0_guest_owned_bits = 0;
1806         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1807         if (is_guest_mode(vcpu)) {
1808                 /*
1809                  * L1's specified read shadow might not contain the TS bit,
1810                  * so now that we turned on shadowing of this bit, we need to
1811                  * set this bit of the shadow. Like in nested_vmx_run we need
1812                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1813                  * up-to-date here because we just decached cr0.TS (and we'll
1814                  * only update vmcs12->guest_cr0 on nested exit).
1815                  */
1816                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1817                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1818                         (vcpu->arch.cr0 & X86_CR0_TS);
1819                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1820         } else
1821                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1822 }
1823
1824 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1825 {
1826         unsigned long rflags, save_rflags;
1827
1828         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1829                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1830                 rflags = vmcs_readl(GUEST_RFLAGS);
1831                 if (to_vmx(vcpu)->rmode.vm86_active) {
1832                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1833                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1834                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1835                 }
1836                 to_vmx(vcpu)->rflags = rflags;
1837         }
1838         return to_vmx(vcpu)->rflags;
1839 }
1840
1841 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1842 {
1843         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1844         to_vmx(vcpu)->rflags = rflags;
1845         if (to_vmx(vcpu)->rmode.vm86_active) {
1846                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1847                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1848         }
1849         vmcs_writel(GUEST_RFLAGS, rflags);
1850 }
1851
1852 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1853 {
1854         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1855         int ret = 0;
1856
1857         if (interruptibility & GUEST_INTR_STATE_STI)
1858                 ret |= KVM_X86_SHADOW_INT_STI;
1859         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1860                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1861
1862         return ret & mask;
1863 }
1864
1865 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1866 {
1867         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1868         u32 interruptibility = interruptibility_old;
1869
1870         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1871
1872         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1873                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1874         else if (mask & KVM_X86_SHADOW_INT_STI)
1875                 interruptibility |= GUEST_INTR_STATE_STI;
1876
1877         if ((interruptibility != interruptibility_old))
1878                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1879 }
1880
1881 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1882 {
1883         unsigned long rip;
1884
1885         rip = kvm_rip_read(vcpu);
1886         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1887         kvm_rip_write(vcpu, rip);
1888
1889         /* skipping an emulated instruction also counts */
1890         vmx_set_interrupt_shadow(vcpu, 0);
1891 }
1892
1893 /*
1894  * KVM wants to inject page-faults which it got to the guest. This function
1895  * checks whether in a nested guest, we need to inject them to L1 or L2.
1896  * This function assumes it is called with the exit reason in vmcs02 being
1897  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1898  * is running).
1899  */
1900 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1901 {
1902         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1903
1904         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1905         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1906                 return 0;
1907
1908         nested_vmx_vmexit(vcpu);
1909         return 1;
1910 }
1911
1912 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1913                                 bool has_error_code, u32 error_code,
1914                                 bool reinject)
1915 {
1916         struct vcpu_vmx *vmx = to_vmx(vcpu);
1917         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1918
1919         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1920             !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1921                 return;
1922
1923         if (has_error_code) {
1924                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1925                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1926         }
1927
1928         if (vmx->rmode.vm86_active) {
1929                 int inc_eip = 0;
1930                 if (kvm_exception_is_soft(nr))
1931                         inc_eip = vcpu->arch.event_exit_inst_len;
1932                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1933                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1934                 return;
1935         }
1936
1937         if (kvm_exception_is_soft(nr)) {
1938                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1939                              vmx->vcpu.arch.event_exit_inst_len);
1940                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1941         } else
1942                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1943
1944         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1945 }
1946
1947 static bool vmx_rdtscp_supported(void)
1948 {
1949         return cpu_has_vmx_rdtscp();
1950 }
1951
1952 static bool vmx_invpcid_supported(void)
1953 {
1954         return cpu_has_vmx_invpcid() && enable_ept;
1955 }
1956
1957 /*
1958  * Swap MSR entry in host/guest MSR entry array.
1959  */
1960 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1961 {
1962         struct shared_msr_entry tmp;
1963
1964         tmp = vmx->guest_msrs[to];
1965         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1966         vmx->guest_msrs[from] = tmp;
1967 }
1968
1969 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1970 {
1971         unsigned long *msr_bitmap;
1972
1973         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1974                 if (is_long_mode(vcpu))
1975                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1976                 else
1977                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1978         } else {
1979                 if (is_long_mode(vcpu))
1980                         msr_bitmap = vmx_msr_bitmap_longmode;
1981                 else
1982                         msr_bitmap = vmx_msr_bitmap_legacy;
1983         }
1984
1985         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1986 }
1987
1988 /*
1989  * Set up the vmcs to automatically save and restore system
1990  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1991  * mode, as fiddling with msrs is very expensive.
1992  */
1993 static void setup_msrs(struct vcpu_vmx *vmx)
1994 {
1995         int save_nmsrs, index;
1996
1997         save_nmsrs = 0;
1998 #ifdef CONFIG_X86_64
1999         if (is_long_mode(&vmx->vcpu)) {
2000                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2001                 if (index >= 0)
2002                         move_msr_up(vmx, index, save_nmsrs++);
2003                 index = __find_msr_index(vmx, MSR_LSTAR);
2004                 if (index >= 0)
2005                         move_msr_up(vmx, index, save_nmsrs++);
2006                 index = __find_msr_index(vmx, MSR_CSTAR);
2007                 if (index >= 0)
2008                         move_msr_up(vmx, index, save_nmsrs++);
2009                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2010                 if (index >= 0 && vmx->rdtscp_enabled)
2011                         move_msr_up(vmx, index, save_nmsrs++);
2012                 /*
2013                  * MSR_STAR is only needed on long mode guests, and only
2014                  * if efer.sce is enabled.
2015                  */
2016                 index = __find_msr_index(vmx, MSR_STAR);
2017                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2018                         move_msr_up(vmx, index, save_nmsrs++);
2019         }
2020 #endif
2021         index = __find_msr_index(vmx, MSR_EFER);
2022         if (index >= 0 && update_transition_efer(vmx, index))
2023                 move_msr_up(vmx, index, save_nmsrs++);
2024
2025         vmx->save_nmsrs = save_nmsrs;
2026
2027         if (cpu_has_vmx_msr_bitmap())
2028                 vmx_set_msr_bitmap(&vmx->vcpu);
2029 }
2030
2031 /*
2032  * reads and returns guest's timestamp counter "register"
2033  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2034  */
2035 static u64 guest_read_tsc(void)
2036 {
2037         u64 host_tsc, tsc_offset;
2038
2039         rdtscll(host_tsc);
2040         tsc_offset = vmcs_read64(TSC_OFFSET);
2041         return host_tsc + tsc_offset;
2042 }
2043
2044 /*
2045  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2046  * counter, even if a nested guest (L2) is currently running.
2047  */
2048 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2049 {
2050         u64 tsc_offset;
2051
2052         tsc_offset = is_guest_mode(vcpu) ?
2053                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2054                 vmcs_read64(TSC_OFFSET);
2055         return host_tsc + tsc_offset;
2056 }
2057
2058 /*
2059  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2060  * software catchup for faster rates on slower CPUs.
2061  */
2062 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2063 {
2064         if (!scale)
2065                 return;
2066
2067         if (user_tsc_khz > tsc_khz) {
2068                 vcpu->arch.tsc_catchup = 1;
2069                 vcpu->arch.tsc_always_catchup = 1;
2070         } else
2071                 WARN(1, "user requested TSC rate below hardware speed\n");
2072 }
2073
2074 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2075 {
2076         return vmcs_read64(TSC_OFFSET);
2077 }
2078
2079 /*
2080  * writes 'offset' into guest's timestamp counter offset register
2081  */
2082 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2083 {
2084         if (is_guest_mode(vcpu)) {
2085                 /*
2086                  * We're here if L1 chose not to trap WRMSR to TSC. According
2087                  * to the spec, this should set L1's TSC; The offset that L1
2088                  * set for L2 remains unchanged, and still needs to be added
2089                  * to the newly set TSC to get L2's TSC.
2090                  */
2091                 struct vmcs12 *vmcs12;
2092                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2093                 /* recalculate vmcs02.TSC_OFFSET: */
2094                 vmcs12 = get_vmcs12(vcpu);
2095                 vmcs_write64(TSC_OFFSET, offset +
2096                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2097                          vmcs12->tsc_offset : 0));
2098         } else {
2099                 vmcs_write64(TSC_OFFSET, offset);
2100         }
2101 }
2102
2103 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2104 {
2105         u64 offset = vmcs_read64(TSC_OFFSET);
2106         vmcs_write64(TSC_OFFSET, offset + adjustment);
2107         if (is_guest_mode(vcpu)) {
2108                 /* Even when running L2, the adjustment needs to apply to L1 */
2109                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2110         }
2111 }
2112
2113 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2114 {
2115         return target_tsc - native_read_tsc();
2116 }
2117
2118 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2119 {
2120         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2121         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2122 }
2123
2124 /*
2125  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2126  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2127  * all guests if the "nested" module option is off, and can also be disabled
2128  * for a single guest by disabling its VMX cpuid bit.
2129  */
2130 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2131 {
2132         return nested && guest_cpuid_has_vmx(vcpu);
2133 }
2134
2135 /*
2136  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2137  * returned for the various VMX controls MSRs when nested VMX is enabled.
2138  * The same values should also be used to verify that vmcs12 control fields are
2139  * valid during nested entry from L1 to L2.
2140  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2141  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2142  * bit in the high half is on if the corresponding bit in the control field
2143  * may be on. See also vmx_control_verify().
2144  * TODO: allow these variables to be modified (downgraded) by module options
2145  * or other means.
2146  */
2147 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2148 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2149 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2150 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2151 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2152 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2153 static __init void nested_vmx_setup_ctls_msrs(void)
2154 {
2155         /*
2156          * Note that as a general rule, the high half of the MSRs (bits in
2157          * the control fields which may be 1) should be initialized by the
2158          * intersection of the underlying hardware's MSR (i.e., features which
2159          * can be supported) and the list of features we want to expose -
2160          * because they are known to be properly supported in our code.
2161          * Also, usually, the low half of the MSRs (bits which must be 1) can
2162          * be set to 0, meaning that L1 may turn off any of these bits. The
2163          * reason is that if one of these bits is necessary, it will appear
2164          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2165          * fields of vmcs01 and vmcs02, will turn these bits off - and
2166          * nested_vmx_exit_handled() will not pass related exits to L1.
2167          * These rules have exceptions below.
2168          */
2169
2170         /* pin-based controls */
2171         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2172               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2173         /*
2174          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2175          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2176          */
2177         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2178         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2179                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2180                 PIN_BASED_VMX_PREEMPTION_TIMER;
2181         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2182
2183         /*
2184          * Exit controls
2185          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2186          * 17 must be 1.
2187          */
2188         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2189         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2190 #ifdef CONFIG_X86_64
2191         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2192 #else
2193         nested_vmx_exit_ctls_high = 0;
2194 #endif
2195         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2196
2197         /* entry controls */
2198         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2199                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2200         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2201         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2202         nested_vmx_entry_ctls_high &=
2203                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2204         nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2205
2206         /* cpu-based controls */
2207         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2208                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2209         nested_vmx_procbased_ctls_low = 0;
2210         nested_vmx_procbased_ctls_high &=
2211                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2212                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2213                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2214                 CPU_BASED_CR3_STORE_EXITING |
2215 #ifdef CONFIG_X86_64
2216                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2217 #endif
2218                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2219                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2220                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2221                 CPU_BASED_PAUSE_EXITING |
2222                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2223         /*
2224          * We can allow some features even when not supported by the
2225          * hardware. For example, L1 can specify an MSR bitmap - and we
2226          * can use it to avoid exits to L1 - even when L0 runs L2
2227          * without MSR bitmaps.
2228          */
2229         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2230
2231         /* secondary cpu-based controls */
2232         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2233                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2234         nested_vmx_secondary_ctls_low = 0;
2235         nested_vmx_secondary_ctls_high &=
2236                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2237                 SECONDARY_EXEC_WBINVD_EXITING;
2238
2239         /* miscellaneous data */
2240         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2241         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2242                 VMX_MISC_SAVE_EFER_LMA;
2243         nested_vmx_misc_high = 0;
2244 }
2245
2246 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2247 {
2248         /*
2249          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2250          */
2251         return ((control & high) | low) == control;
2252 }
2253
2254 static inline u64 vmx_control_msr(u32 low, u32 high)
2255 {
2256         return low | ((u64)high << 32);
2257 }
2258
2259 /*
2260  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2261  * also let it use VMX-specific MSRs.
2262  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2263  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2264  * like all other MSRs).
2265  */
2266 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2267 {
2268         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2269                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2270                 /*
2271                  * According to the spec, processors which do not support VMX
2272                  * should throw a #GP(0) when VMX capability MSRs are read.
2273                  */
2274                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2275                 return 1;
2276         }
2277
2278         switch (msr_index) {
2279         case MSR_IA32_FEATURE_CONTROL:
2280                 *pdata = 0;
2281                 break;
2282         case MSR_IA32_VMX_BASIC:
2283                 /*
2284                  * This MSR reports some information about VMX support. We
2285                  * should return information about the VMX we emulate for the
2286                  * guest, and the VMCS structure we give it - not about the
2287                  * VMX support of the underlying hardware.
2288                  */
2289                 *pdata = VMCS12_REVISION |
2290                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2291                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2292                 break;
2293         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2294         case MSR_IA32_VMX_PINBASED_CTLS:
2295                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2296                                         nested_vmx_pinbased_ctls_high);
2297                 break;
2298         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2299         case MSR_IA32_VMX_PROCBASED_CTLS:
2300                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2301                                         nested_vmx_procbased_ctls_high);
2302                 break;
2303         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2304         case MSR_IA32_VMX_EXIT_CTLS:
2305                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2306                                         nested_vmx_exit_ctls_high);
2307                 break;
2308         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2309         case MSR_IA32_VMX_ENTRY_CTLS:
2310                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2311                                         nested_vmx_entry_ctls_high);
2312                 break;
2313         case MSR_IA32_VMX_MISC:
2314                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2315                                          nested_vmx_misc_high);
2316                 break;
2317         /*
2318          * These MSRs specify bits which the guest must keep fixed (on or off)
2319          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2320          * We picked the standard core2 setting.
2321          */
2322 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2323 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2324         case MSR_IA32_VMX_CR0_FIXED0:
2325                 *pdata = VMXON_CR0_ALWAYSON;
2326                 break;
2327         case MSR_IA32_VMX_CR0_FIXED1:
2328                 *pdata = -1ULL;
2329                 break;
2330         case MSR_IA32_VMX_CR4_FIXED0:
2331                 *pdata = VMXON_CR4_ALWAYSON;
2332                 break;
2333         case MSR_IA32_VMX_CR4_FIXED1:
2334                 *pdata = -1ULL;
2335                 break;
2336         case MSR_IA32_VMX_VMCS_ENUM:
2337                 *pdata = 0x1f;
2338                 break;
2339         case MSR_IA32_VMX_PROCBASED_CTLS2:
2340                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2341                                         nested_vmx_secondary_ctls_high);
2342                 break;
2343         case MSR_IA32_VMX_EPT_VPID_CAP:
2344                 /* Currently, no nested ept or nested vpid */
2345                 *pdata = 0;
2346                 break;
2347         default:
2348                 return 0;
2349         }
2350
2351         return 1;
2352 }
2353
2354 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2355 {
2356         if (!nested_vmx_allowed(vcpu))
2357                 return 0;
2358
2359         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2360                 /* TODO: the right thing. */
2361                 return 1;
2362         /*
2363          * No need to treat VMX capability MSRs specially: If we don't handle
2364          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2365          */
2366         return 0;
2367 }
2368
2369 /*
2370  * Reads an msr value (of 'msr_index') into 'pdata'.
2371  * Returns 0 on success, non-0 otherwise.
2372  * Assumes vcpu_load() was already called.
2373  */
2374 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2375 {
2376         u64 data;
2377         struct shared_msr_entry *msr;
2378
2379         if (!pdata) {
2380                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2381                 return -EINVAL;
2382         }
2383
2384         switch (msr_index) {
2385 #ifdef CONFIG_X86_64
2386         case MSR_FS_BASE:
2387                 data = vmcs_readl(GUEST_FS_BASE);
2388                 break;
2389         case MSR_GS_BASE:
2390                 data = vmcs_readl(GUEST_GS_BASE);
2391                 break;
2392         case MSR_KERNEL_GS_BASE:
2393                 vmx_load_host_state(to_vmx(vcpu));
2394                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2395                 break;
2396 #endif
2397         case MSR_EFER:
2398                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2399         case MSR_IA32_TSC:
2400                 data = guest_read_tsc();
2401                 break;
2402         case MSR_IA32_SYSENTER_CS:
2403                 data = vmcs_read32(GUEST_SYSENTER_CS);
2404                 break;
2405         case MSR_IA32_SYSENTER_EIP:
2406                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2407                 break;
2408         case MSR_IA32_SYSENTER_ESP:
2409                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2410                 break;
2411         case MSR_TSC_AUX:
2412                 if (!to_vmx(vcpu)->rdtscp_enabled)
2413                         return 1;
2414                 /* Otherwise falls through */
2415         default:
2416                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2417                         return 0;
2418                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2419                 if (msr) {
2420                         data = msr->data;
2421                         break;
2422                 }
2423                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2424         }
2425
2426         *pdata = data;
2427         return 0;
2428 }
2429
2430 /*
2431  * Writes msr value into into the appropriate "register".
2432  * Returns 0 on success, non-0 otherwise.
2433  * Assumes vcpu_load() was already called.
2434  */
2435 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2436 {
2437         struct vcpu_vmx *vmx = to_vmx(vcpu);
2438         struct shared_msr_entry *msr;
2439         int ret = 0;
2440         u32 msr_index = msr_info->index;
2441         u64 data = msr_info->data;
2442
2443         switch (msr_index) {
2444         case MSR_EFER:
2445                 ret = kvm_set_msr_common(vcpu, msr_info);
2446                 break;
2447 #ifdef CONFIG_X86_64
2448         case MSR_FS_BASE:
2449                 vmx_segment_cache_clear(vmx);
2450                 vmcs_writel(GUEST_FS_BASE, data);
2451                 break;
2452         case MSR_GS_BASE:
2453                 vmx_segment_cache_clear(vmx);
2454                 vmcs_writel(GUEST_GS_BASE, data);
2455                 break;
2456         case MSR_KERNEL_GS_BASE:
2457                 vmx_load_host_state(vmx);
2458                 vmx->msr_guest_kernel_gs_base = data;
2459                 break;
2460 #endif
2461         case MSR_IA32_SYSENTER_CS:
2462                 vmcs_write32(GUEST_SYSENTER_CS, data);
2463                 break;
2464         case MSR_IA32_SYSENTER_EIP:
2465                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2466                 break;
2467         case MSR_IA32_SYSENTER_ESP:
2468                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2469                 break;
2470         case MSR_IA32_TSC:
2471                 kvm_write_tsc(vcpu, msr_info);
2472                 break;
2473         case MSR_IA32_CR_PAT:
2474                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2475                         vmcs_write64(GUEST_IA32_PAT, data);
2476                         vcpu->arch.pat = data;
2477                         break;
2478                 }
2479                 ret = kvm_set_msr_common(vcpu, msr_info);
2480                 break;
2481         case MSR_IA32_TSC_ADJUST:
2482                 ret = kvm_set_msr_common(vcpu, msr_info);
2483                 break;
2484         case MSR_TSC_AUX:
2485                 if (!vmx->rdtscp_enabled)
2486                         return 1;
2487                 /* Check reserved bit, higher 32 bits should be zero */
2488                 if ((data >> 32) != 0)
2489                         return 1;
2490                 /* Otherwise falls through */
2491         default:
2492                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2493                         break;
2494                 msr = find_msr_entry(vmx, msr_index);
2495                 if (msr) {
2496                         msr->data = data;
2497                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2498                                 preempt_disable();
2499                                 kvm_set_shared_msr(msr->index, msr->data,
2500                                                    msr->mask);
2501                                 preempt_enable();
2502                         }
2503                         break;
2504                 }
2505                 ret = kvm_set_msr_common(vcpu, msr_info);
2506         }
2507
2508         return ret;
2509 }
2510
2511 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2512 {
2513         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2514         switch (reg) {
2515         case VCPU_REGS_RSP:
2516                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2517                 break;
2518         case VCPU_REGS_RIP:
2519                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2520                 break;
2521         case VCPU_EXREG_PDPTR:
2522                 if (enable_ept)
2523                         ept_save_pdptrs(vcpu);
2524                 break;
2525         default:
2526                 break;
2527         }
2528 }
2529
2530 static __init int cpu_has_kvm_support(void)
2531 {
2532         return cpu_has_vmx();
2533 }
2534
2535 static __init int vmx_disabled_by_bios(void)
2536 {
2537         u64 msr;
2538
2539         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2540         if (msr & FEATURE_CONTROL_LOCKED) {
2541                 /* launched w/ TXT and VMX disabled */
2542                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2543                         && tboot_enabled())
2544                         return 1;
2545                 /* launched w/o TXT and VMX only enabled w/ TXT */
2546                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2547                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2548                         && !tboot_enabled()) {
2549                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2550                                 "activate TXT before enabling KVM\n");
2551                         return 1;
2552                 }
2553                 /* launched w/o TXT and VMX disabled */
2554                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2555                         && !tboot_enabled())
2556                         return 1;
2557         }
2558
2559         return 0;
2560 }
2561
2562 static void kvm_cpu_vmxon(u64 addr)
2563 {
2564         asm volatile (ASM_VMX_VMXON_RAX
2565                         : : "a"(&addr), "m"(addr)
2566                         : "memory", "cc");
2567 }
2568
2569 static int hardware_enable(void *garbage)
2570 {
2571         int cpu = raw_smp_processor_id();
2572         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2573         u64 old, test_bits;
2574
2575         if (read_cr4() & X86_CR4_VMXE)
2576                 return -EBUSY;
2577
2578         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2579
2580         /*
2581          * Now we can enable the vmclear operation in kdump
2582          * since the loaded_vmcss_on_cpu list on this cpu
2583          * has been initialized.
2584          *
2585          * Though the cpu is not in VMX operation now, there
2586          * is no problem to enable the vmclear operation
2587          * for the loaded_vmcss_on_cpu list is empty!
2588          */
2589         crash_enable_local_vmclear(cpu);
2590
2591         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2592
2593         test_bits = FEATURE_CONTROL_LOCKED;
2594         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2595         if (tboot_enabled())
2596                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2597
2598         if ((old & test_bits) != test_bits) {
2599                 /* enable and lock */
2600                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2601         }
2602         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2603
2604         if (vmm_exclusive) {
2605                 kvm_cpu_vmxon(phys_addr);
2606                 ept_sync_global();
2607         }
2608
2609         native_store_gdt(&__get_cpu_var(host_gdt));
2610
2611         return 0;
2612 }
2613
2614 static void vmclear_local_loaded_vmcss(void)
2615 {
2616         int cpu = raw_smp_processor_id();
2617         struct loaded_vmcs *v, *n;
2618
2619         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2620                                  loaded_vmcss_on_cpu_link)
2621                 __loaded_vmcs_clear(v);
2622 }
2623
2624
2625 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2626  * tricks.
2627  */
2628 static void kvm_cpu_vmxoff(void)
2629 {
2630         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2631 }
2632
2633 static void hardware_disable(void *garbage)
2634 {
2635         if (vmm_exclusive) {
2636                 vmclear_local_loaded_vmcss();
2637                 kvm_cpu_vmxoff();
2638         }
2639         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2640 }
2641
2642 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2643                                       u32 msr, u32 *result)
2644 {
2645         u32 vmx_msr_low, vmx_msr_high;
2646         u32 ctl = ctl_min | ctl_opt;
2647
2648         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2649
2650         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2651         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2652
2653         /* Ensure minimum (required) set of control bits are supported. */
2654         if (ctl_min & ~ctl)
2655                 return -EIO;
2656
2657         *result = ctl;
2658         return 0;
2659 }
2660
2661 static __init bool allow_1_setting(u32 msr, u32 ctl)
2662 {
2663         u32 vmx_msr_low, vmx_msr_high;
2664
2665         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2666         return vmx_msr_high & ctl;
2667 }
2668
2669 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2670 {
2671         u32 vmx_msr_low, vmx_msr_high;
2672         u32 min, opt, min2, opt2;
2673         u32 _pin_based_exec_control = 0;
2674         u32 _cpu_based_exec_control = 0;
2675         u32 _cpu_based_2nd_exec_control = 0;
2676         u32 _vmexit_control = 0;
2677         u32 _vmentry_control = 0;
2678
2679         min = CPU_BASED_HLT_EXITING |
2680 #ifdef CONFIG_X86_64
2681               CPU_BASED_CR8_LOAD_EXITING |
2682               CPU_BASED_CR8_STORE_EXITING |
2683 #endif
2684               CPU_BASED_CR3_LOAD_EXITING |
2685               CPU_BASED_CR3_STORE_EXITING |
2686               CPU_BASED_USE_IO_BITMAPS |
2687               CPU_BASED_MOV_DR_EXITING |
2688               CPU_BASED_USE_TSC_OFFSETING |
2689               CPU_BASED_MWAIT_EXITING |
2690               CPU_BASED_MONITOR_EXITING |
2691               CPU_BASED_INVLPG_EXITING |
2692               CPU_BASED_RDPMC_EXITING;
2693
2694         opt = CPU_BASED_TPR_SHADOW |
2695               CPU_BASED_USE_MSR_BITMAPS |
2696               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2697         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2698                                 &_cpu_based_exec_control) < 0)
2699                 return -EIO;
2700 #ifdef CONFIG_X86_64
2701         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2702                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2703                                            ~CPU_BASED_CR8_STORE_EXITING;
2704 #endif
2705         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2706                 min2 = 0;
2707                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2708                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2709                         SECONDARY_EXEC_WBINVD_EXITING |
2710                         SECONDARY_EXEC_ENABLE_VPID |
2711                         SECONDARY_EXEC_ENABLE_EPT |
2712                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2713                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2714                         SECONDARY_EXEC_RDTSCP |
2715                         SECONDARY_EXEC_ENABLE_INVPCID |
2716                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2717                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2718                         SECONDARY_EXEC_SHADOW_VMCS;
2719                 if (adjust_vmx_controls(min2, opt2,
2720                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2721                                         &_cpu_based_2nd_exec_control) < 0)
2722                         return -EIO;
2723         }
2724 #ifndef CONFIG_X86_64
2725         if (!(_cpu_based_2nd_exec_control &
2726                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2727                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2728 #endif
2729
2730         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2731                 _cpu_based_2nd_exec_control &= ~(
2732                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2733                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2734                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2735
2736         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2737                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2738                    enabled */
2739                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2740                                              CPU_BASED_CR3_STORE_EXITING |
2741                                              CPU_BASED_INVLPG_EXITING);
2742                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2743                       vmx_capability.ept, vmx_capability.vpid);
2744         }
2745
2746         min = 0;
2747 #ifdef CONFIG_X86_64
2748         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2749 #endif
2750         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2751                 VM_EXIT_ACK_INTR_ON_EXIT;
2752         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2753                                 &_vmexit_control) < 0)
2754                 return -EIO;
2755
2756         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2757         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2758         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2759                                 &_pin_based_exec_control) < 0)
2760                 return -EIO;
2761
2762         if (!(_cpu_based_2nd_exec_control &
2763                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2764                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2765                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2766
2767         min = 0;
2768         opt = VM_ENTRY_LOAD_IA32_PAT;
2769         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2770                                 &_vmentry_control) < 0)
2771                 return -EIO;
2772
2773         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2774
2775         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2776         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2777                 return -EIO;
2778
2779 #ifdef CONFIG_X86_64
2780         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2781         if (vmx_msr_high & (1u<<16))
2782                 return -EIO;
2783 #endif
2784
2785         /* Require Write-Back (WB) memory type for VMCS accesses. */
2786         if (((vmx_msr_high >> 18) & 15) != 6)
2787                 return -EIO;
2788
2789         vmcs_conf->size = vmx_msr_high & 0x1fff;
2790         vmcs_conf->order = get_order(vmcs_config.size);
2791         vmcs_conf->revision_id = vmx_msr_low;
2792
2793         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2794         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2795         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2796         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2797         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2798
2799         cpu_has_load_ia32_efer =
2800                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2801                                 VM_ENTRY_LOAD_IA32_EFER)
2802                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2803                                    VM_EXIT_LOAD_IA32_EFER);
2804
2805         cpu_has_load_perf_global_ctrl =
2806                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2807                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2808                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2809                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2810
2811         /*
2812          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2813          * but due to arrata below it can't be used. Workaround is to use
2814          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2815          *
2816          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2817          *
2818          * AAK155             (model 26)
2819          * AAP115             (model 30)
2820          * AAT100             (model 37)
2821          * BC86,AAY89,BD102   (model 44)
2822          * BA97               (model 46)
2823          *
2824          */
2825         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2826                 switch (boot_cpu_data.x86_model) {
2827                 case 26:
2828                 case 30:
2829                 case 37:
2830                 case 44:
2831                 case 46:
2832                         cpu_has_load_perf_global_ctrl = false;
2833                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2834                                         "does not work properly. Using workaround\n");
2835                         break;
2836                 default:
2837                         break;
2838                 }
2839         }
2840
2841         return 0;
2842 }
2843
2844 static struct vmcs *alloc_vmcs_cpu(int cpu)
2845 {
2846         int node = cpu_to_node(cpu);
2847         struct page *pages;
2848         struct vmcs *vmcs;
2849
2850         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2851         if (!pages)
2852                 return NULL;
2853         vmcs = page_address(pages);
2854         memset(vmcs, 0, vmcs_config.size);
2855         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2856         return vmcs;
2857 }
2858
2859 static struct vmcs *alloc_vmcs(void)
2860 {
2861         return alloc_vmcs_cpu(raw_smp_processor_id());
2862 }
2863
2864 static void free_vmcs(struct vmcs *vmcs)
2865 {
2866         free_pages((unsigned long)vmcs, vmcs_config.order);
2867 }
2868
2869 /*
2870  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2871  */
2872 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2873 {
2874         if (!loaded_vmcs->vmcs)
2875                 return;
2876         loaded_vmcs_clear(loaded_vmcs);
2877         free_vmcs(loaded_vmcs->vmcs);
2878         loaded_vmcs->vmcs = NULL;
2879 }
2880
2881 static void free_kvm_area(void)
2882 {
2883         int cpu;
2884
2885         for_each_possible_cpu(cpu) {
2886                 free_vmcs(per_cpu(vmxarea, cpu));
2887                 per_cpu(vmxarea, cpu) = NULL;
2888         }
2889 }
2890
2891 static __init int alloc_kvm_area(void)
2892 {
2893         int cpu;
2894
2895         for_each_possible_cpu(cpu) {
2896                 struct vmcs *vmcs;
2897
2898                 vmcs = alloc_vmcs_cpu(cpu);
2899                 if (!vmcs) {
2900                         free_kvm_area();
2901                         return -ENOMEM;
2902                 }
2903
2904                 per_cpu(vmxarea, cpu) = vmcs;
2905         }
2906         return 0;
2907 }
2908
2909 static __init int hardware_setup(void)
2910 {
2911         if (setup_vmcs_config(&vmcs_config) < 0)
2912                 return -EIO;
2913
2914         if (boot_cpu_has(X86_FEATURE_NX))
2915                 kvm_enable_efer_bits(EFER_NX);
2916
2917         if (!cpu_has_vmx_vpid())
2918                 enable_vpid = 0;
2919         if (!cpu_has_vmx_shadow_vmcs())
2920                 enable_shadow_vmcs = 0;
2921
2922         if (!cpu_has_vmx_ept() ||
2923             !cpu_has_vmx_ept_4levels()) {
2924                 enable_ept = 0;
2925                 enable_unrestricted_guest = 0;
2926                 enable_ept_ad_bits = 0;
2927         }
2928
2929         if (!cpu_has_vmx_ept_ad_bits())
2930                 enable_ept_ad_bits = 0;
2931
2932         if (!cpu_has_vmx_unrestricted_guest())
2933                 enable_unrestricted_guest = 0;
2934
2935         if (!cpu_has_vmx_flexpriority())
2936                 flexpriority_enabled = 0;
2937
2938         if (!cpu_has_vmx_tpr_shadow())
2939                 kvm_x86_ops->update_cr8_intercept = NULL;
2940
2941         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2942                 kvm_disable_largepages();
2943
2944         if (!cpu_has_vmx_ple())
2945                 ple_gap = 0;
2946
2947         if (!cpu_has_vmx_apicv())
2948                 enable_apicv = 0;
2949
2950         if (enable_apicv)
2951                 kvm_x86_ops->update_cr8_intercept = NULL;
2952         else {
2953                 kvm_x86_ops->hwapic_irr_update = NULL;
2954                 kvm_x86_ops->deliver_posted_interrupt = NULL;
2955                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2956         }
2957
2958         if (nested)
2959                 nested_vmx_setup_ctls_msrs();
2960
2961         return alloc_kvm_area();
2962 }
2963
2964 static __exit void hardware_unsetup(void)
2965 {
2966         free_kvm_area();
2967 }
2968
2969 static bool emulation_required(struct kvm_vcpu *vcpu)
2970 {
2971         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2972 }
2973
2974 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2975                 struct kvm_segment *save)
2976 {
2977         if (!emulate_invalid_guest_state) {
2978                 /*
2979                  * CS and SS RPL should be equal during guest entry according
2980                  * to VMX spec, but in reality it is not always so. Since vcpu
2981                  * is in the middle of the transition from real mode to
2982                  * protected mode it is safe to assume that RPL 0 is a good
2983                  * default value.
2984                  */
2985                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2986                         save->selector &= ~SELECTOR_RPL_MASK;
2987                 save->dpl = save->selector & SELECTOR_RPL_MASK;
2988                 save->s = 1;
2989         }
2990         vmx_set_segment(vcpu, save, seg);
2991 }
2992
2993 static void enter_pmode(struct kvm_vcpu *vcpu)
2994 {
2995         unsigned long flags;
2996         struct vcpu_vmx *vmx = to_vmx(vcpu);
2997
2998         /*
2999          * Update real mode segment cache. It may be not up-to-date if sement
3000          * register was written while vcpu was in a guest mode.
3001          */
3002         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3003         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3004         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3005         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3006         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3007         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3008
3009         vmx->rmode.vm86_active = 0;
3010
3011         vmx_segment_cache_clear(vmx);
3012
3013         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3014
3015         flags = vmcs_readl(GUEST_RFLAGS);
3016         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3017         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3018         vmcs_writel(GUEST_RFLAGS, flags);
3019
3020         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3021                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3022
3023         update_exception_bitmap(vcpu);
3024
3025         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3026         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3027         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3028         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3029         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3030         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3031
3032         /* CPL is always 0 when CPU enters protected mode */
3033         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3034         vmx->cpl = 0;
3035 }
3036
3037 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3038 {
3039         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3040         struct kvm_segment var = *save;
3041
3042         var.dpl = 0x3;
3043         if (seg == VCPU_SREG_CS)
3044                 var.type = 0x3;
3045
3046         if (!emulate_invalid_guest_state) {
3047                 var.selector = var.base >> 4;
3048                 var.base = var.base & 0xffff0;
3049                 var.limit = 0xffff;
3050                 var.g = 0;
3051                 var.db = 0;
3052                 var.present = 1;
3053                 var.s = 1;
3054                 var.l = 0;
3055                 var.unusable = 0;
3056                 var.type = 0x3;
3057                 var.avl = 0;
3058                 if (save->base & 0xf)
3059                         printk_once(KERN_WARNING "kvm: segment base is not "
3060                                         "paragraph aligned when entering "
3061                                         "protected mode (seg=%d)", seg);
3062         }
3063
3064         vmcs_write16(sf->selector, var.selector);
3065         vmcs_write32(sf->base, var.base);
3066         vmcs_write32(sf->limit, var.limit);
3067         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3068 }
3069
3070 static void enter_rmode(struct kvm_vcpu *vcpu)
3071 {
3072         unsigned long flags;
3073         struct vcpu_vmx *vmx = to_vmx(vcpu);
3074
3075         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3076         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3077         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3078         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3079         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3080         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3081         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3082
3083         vmx->rmode.vm86_active = 1;
3084
3085         /*
3086          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3087          * vcpu. Warn the user that an update is overdue.
3088          */
3089         if (!vcpu->kvm->arch.tss_addr)
3090                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3091                              "called before entering vcpu\n");
3092
3093         vmx_segment_cache_clear(vmx);
3094
3095         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3096         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3097         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3098
3099         flags = vmcs_readl(GUEST_RFLAGS);
3100         vmx->rmode.save_rflags = flags;
3101
3102         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3103
3104         vmcs_writel(GUEST_RFLAGS, flags);
3105         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3106         update_exception_bitmap(vcpu);
3107
3108         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3109         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3110         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3111         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3112         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3113         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3114
3115         kvm_mmu_reset_context(vcpu);
3116 }
3117
3118 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3119 {
3120         struct vcpu_vmx *vmx = to_vmx(vcpu);
3121         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3122
3123         if (!msr)
3124                 return;
3125
3126         /*
3127          * Force kernel_gs_base reloading before EFER changes, as control
3128          * of this msr depends on is_long_mode().
3129          */
3130         vmx_load_host_state(to_vmx(vcpu));
3131         vcpu->arch.efer = efer;
3132         if (efer & EFER_LMA) {
3133                 vmcs_write32(VM_ENTRY_CONTROLS,
3134                              vmcs_read32(VM_ENTRY_CONTROLS) |
3135                              VM_ENTRY_IA32E_MODE);
3136                 msr->data = efer;
3137         } else {
3138                 vmcs_write32(VM_ENTRY_CONTROLS,
3139                              vmcs_read32(VM_ENTRY_CONTROLS) &
3140                              ~VM_ENTRY_IA32E_MODE);
3141
3142                 msr->data = efer & ~EFER_LME;
3143         }
3144         setup_msrs(vmx);
3145 }
3146
3147 #ifdef CONFIG_X86_64
3148
3149 static void enter_lmode(struct kvm_vcpu *vcpu)
3150 {
3151         u32 guest_tr_ar;
3152
3153         vmx_segment_cache_clear(to_vmx(vcpu));
3154
3155         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3156         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3157                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3158                                      __func__);
3159                 vmcs_write32(GUEST_TR_AR_BYTES,
3160                              (guest_tr_ar & ~AR_TYPE_MASK)
3161                              | AR_TYPE_BUSY_64_TSS);
3162         }
3163         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3164 }
3165
3166 static void exit_lmode(struct kvm_vcpu *vcpu)
3167 {
3168         vmcs_write32(VM_ENTRY_CONTROLS,
3169                      vmcs_read32(VM_ENTRY_CONTROLS)
3170                      & ~VM_ENTRY_IA32E_MODE);
3171         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3172 }
3173
3174 #endif
3175
3176 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3177 {
3178         vpid_sync_context(to_vmx(vcpu));
3179         if (enable_ept) {
3180                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3181                         return;
3182                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3183         }
3184 }
3185
3186 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3187 {
3188         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3189
3190         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3191         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3192 }
3193
3194 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3195 {
3196         if (enable_ept && is_paging(vcpu))
3197                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3198         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3199 }
3200
3201 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3202 {
3203         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3204
3205         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3206         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3207 }
3208
3209 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3210 {
3211         if (!test_bit(VCPU_EXREG_PDPTR,
3212                       (unsigned long *)&vcpu->arch.regs_dirty))
3213                 return;
3214
3215         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3216                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3217                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3218                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3219                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3220         }
3221 }
3222
3223 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3224 {
3225         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3226                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3227                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3228                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3229                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3230         }
3231
3232         __set_bit(VCPU_EXREG_PDPTR,
3233                   (unsigned long *)&vcpu->arch.regs_avail);
3234         __set_bit(VCPU_EXREG_PDPTR,
3235                   (unsigned long *)&vcpu->arch.regs_dirty);
3236 }
3237
3238 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3239
3240 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3241                                         unsigned long cr0,
3242                                         struct kvm_vcpu *vcpu)
3243 {
3244         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3245                 vmx_decache_cr3(vcpu);
3246         if (!(cr0 & X86_CR0_PG)) {
3247                 /* From paging/starting to nonpaging */
3248                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3249                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3250                              (CPU_BASED_CR3_LOAD_EXITING |
3251                               CPU_BASED_CR3_STORE_EXITING));
3252                 vcpu->arch.cr0 = cr0;
3253                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3254         } else if (!is_paging(vcpu)) {
3255                 /* From nonpaging to paging */
3256                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3257                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3258                              ~(CPU_BASED_CR3_LOAD_EXITING |
3259                                CPU_BASED_CR3_STORE_EXITING));
3260                 vcpu->arch.cr0 = cr0;
3261                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3262         }
3263
3264         if (!(cr0 & X86_CR0_WP))
3265                 *hw_cr0 &= ~X86_CR0_WP;
3266 }
3267
3268 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3269 {
3270         struct vcpu_vmx *vmx = to_vmx(vcpu);
3271         unsigned long hw_cr0;
3272
3273         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3274         if (enable_unrestricted_guest)
3275                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3276         else {
3277                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3278
3279                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3280                         enter_pmode(vcpu);
3281
3282                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3283                         enter_rmode(vcpu);
3284         }
3285
3286 #ifdef CONFIG_X86_64
3287         if (vcpu->arch.efer & EFER_LME) {
3288                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3289                         enter_lmode(vcpu);
3290                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3291                         exit_lmode(vcpu);
3292         }
3293 #endif
3294
3295         if (enable_ept)
3296                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3297
3298         if (!vcpu->fpu_active)
3299                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3300
3301         vmcs_writel(CR0_READ_SHADOW, cr0);
3302         vmcs_writel(GUEST_CR0, hw_cr0);
3303         vcpu->arch.cr0 = cr0;
3304
3305         /* depends on vcpu->arch.cr0 to be set to a new value */
3306         vmx->emulation_required = emulation_required(vcpu);
3307 }
3308
3309 static u64 construct_eptp(unsigned long root_hpa)
3310 {
3311         u64 eptp;
3312
3313         /* TODO write the value reading from MSR */
3314         eptp = VMX_EPT_DEFAULT_MT |
3315                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3316         if (enable_ept_ad_bits)
3317                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3318         eptp |= (root_hpa & PAGE_MASK);
3319
3320         return eptp;
3321 }
3322
3323 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3324 {
3325         unsigned long guest_cr3;
3326         u64 eptp;
3327
3328         guest_cr3 = cr3;
3329         if (enable_ept) {
3330                 eptp = construct_eptp(cr3);
3331                 vmcs_write64(EPT_POINTER, eptp);
3332                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3333                         vcpu->kvm->arch.ept_identity_map_addr;
3334                 ept_load_pdptrs(vcpu);
3335         }
3336
3337         vmx_flush_tlb(vcpu);
3338         vmcs_writel(GUEST_CR3, guest_cr3);
3339 }
3340
3341 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3342 {
3343         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3344                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3345
3346         if (cr4 & X86_CR4_VMXE) {
3347                 /*
3348                  * To use VMXON (and later other VMX instructions), a guest
3349                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3350                  * So basically the check on whether to allow nested VMX
3351                  * is here.
3352                  */
3353                 if (!nested_vmx_allowed(vcpu))
3354                         return 1;
3355         }
3356         if (to_vmx(vcpu)->nested.vmxon &&
3357             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3358                 return 1;
3359
3360         vcpu->arch.cr4 = cr4;
3361         if (enable_ept) {
3362                 if (!is_paging(vcpu)) {
3363                         hw_cr4 &= ~X86_CR4_PAE;
3364                         hw_cr4 |= X86_CR4_PSE;
3365                         /*
3366                          * SMEP is disabled if CPU is in non-paging mode in
3367                          * hardware. However KVM always uses paging mode to
3368                          * emulate guest non-paging mode with TDP.
3369                          * To emulate this behavior, SMEP needs to be manually
3370                          * disabled when guest switches to non-paging mode.
3371                          */
3372                         hw_cr4 &= ~X86_CR4_SMEP;
3373                 } else if (!(cr4 & X86_CR4_PAE)) {
3374                         hw_cr4 &= ~X86_CR4_PAE;
3375                 }
3376         }
3377
3378         vmcs_writel(CR4_READ_SHADOW, cr4);
3379         vmcs_writel(GUEST_CR4, hw_cr4);
3380         return 0;
3381 }
3382
3383 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3384                             struct kvm_segment *var, int seg)
3385 {
3386         struct vcpu_vmx *vmx = to_vmx(vcpu);
3387         u32 ar;
3388
3389         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3390                 *var = vmx->rmode.segs[seg];
3391                 if (seg == VCPU_SREG_TR
3392                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3393                         return;
3394                 var->base = vmx_read_guest_seg_base(vmx, seg);
3395                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3396                 return;
3397         }
3398         var->base = vmx_read_guest_seg_base(vmx, seg);
3399         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3400         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3401         ar = vmx_read_guest_seg_ar(vmx, seg);
3402         var->type = ar & 15;
3403         var->s = (ar >> 4) & 1;
3404         var->dpl = (ar >> 5) & 3;
3405         var->present = (ar >> 7) & 1;
3406         var->avl = (ar >> 12) & 1;
3407         var->l = (ar >> 13) & 1;
3408         var->db = (ar >> 14) & 1;
3409         var->g = (ar >> 15) & 1;
3410         var->unusable = (ar >> 16) & 1;
3411 }
3412
3413 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3414 {
3415         struct kvm_segment s;
3416
3417         if (to_vmx(vcpu)->rmode.vm86_active) {
3418                 vmx_get_segment(vcpu, &s, seg);
3419                 return s.base;
3420         }
3421         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3422 }
3423
3424 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3425 {
3426         struct vcpu_vmx *vmx = to_vmx(vcpu);
3427
3428         if (!is_protmode(vcpu))
3429                 return 0;
3430
3431         if (!is_long_mode(vcpu)
3432             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3433                 return 3;
3434
3435         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3436                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3437                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3438         }
3439
3440         return vmx->cpl;
3441 }
3442
3443
3444 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3445 {
3446         u32 ar;
3447
3448         if (var->unusable || !var->present)
3449                 ar = 1 << 16;
3450         else {
3451                 ar = var->type & 15;
3452                 ar |= (var->s & 1) << 4;
3453                 ar |= (var->dpl & 3) << 5;
3454                 ar |= (var->present & 1) << 7;
3455                 ar |= (var->avl & 1) << 12;
3456                 ar |= (var->l & 1) << 13;
3457                 ar |= (var->db & 1) << 14;
3458                 ar |= (var->g & 1) << 15;
3459         }
3460
3461         return ar;
3462 }
3463
3464 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3465                             struct kvm_segment *var, int seg)
3466 {
3467         struct vcpu_vmx *vmx = to_vmx(vcpu);
3468         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3469
3470         vmx_segment_cache_clear(vmx);
3471         if (seg == VCPU_SREG_CS)
3472                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3473
3474         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3475                 vmx->rmode.segs[seg] = *var;
3476                 if (seg == VCPU_SREG_TR)
3477                         vmcs_write16(sf->selector, var->selector);
3478                 else if (var->s)
3479                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3480                 goto out;
3481         }
3482
3483         vmcs_writel(sf->base, var->base);
3484         vmcs_write32(sf->limit, var->limit);
3485         vmcs_write16(sf->selector, var->selector);
3486
3487         /*
3488          *   Fix the "Accessed" bit in AR field of segment registers for older
3489          * qemu binaries.
3490          *   IA32 arch specifies that at the time of processor reset the
3491          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3492          * is setting it to 0 in the userland code. This causes invalid guest
3493          * state vmexit when "unrestricted guest" mode is turned on.
3494          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3495          * tree. Newer qemu binaries with that qemu fix would not need this
3496          * kvm hack.
3497          */
3498         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3499                 var->type |= 0x1; /* Accessed */
3500
3501         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3502
3503 out:
3504         vmx->emulation_required |= emulation_required(vcpu);
3505 }
3506
3507 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3508 {
3509         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3510
3511         *db = (ar >> 14) & 1;
3512         *l = (ar >> 13) & 1;
3513 }
3514
3515 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3516 {
3517         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3518         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3519 }
3520
3521 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3522 {
3523         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3524         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3525 }
3526
3527 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3528 {
3529         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3530         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3531 }
3532
3533 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3534 {
3535         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3536         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3537 }
3538
3539 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3540 {
3541         struct kvm_segment var;
3542         u32 ar;
3543
3544         vmx_get_segment(vcpu, &var, seg);
3545         var.dpl = 0x3;
3546         if (seg == VCPU_SREG_CS)
3547                 var.type = 0x3;
3548         ar = vmx_segment_access_rights(&var);
3549
3550         if (var.base != (var.selector << 4))
3551                 return false;
3552         if (var.limit != 0xffff)
3553                 return false;
3554         if (ar != 0xf3)
3555                 return false;
3556
3557         return true;
3558 }
3559
3560 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3561 {
3562         struct kvm_segment cs;
3563         unsigned int cs_rpl;
3564
3565         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3566         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3567
3568         if (cs.unusable)
3569                 return false;
3570         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3571                 return false;
3572         if (!cs.s)
3573                 return false;
3574         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3575                 if (cs.dpl > cs_rpl)
3576                         return false;
3577         } else {
3578                 if (cs.dpl != cs_rpl)
3579                         return false;
3580         }
3581         if (!cs.present)
3582                 return false;
3583
3584         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3585         return true;
3586 }
3587
3588 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3589 {
3590         struct kvm_segment ss;
3591         unsigned int ss_rpl;
3592
3593         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3594         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3595
3596         if (ss.unusable)
3597                 return true;
3598         if (ss.type != 3 && ss.type != 7)
3599                 return false;
3600         if (!ss.s)
3601                 return false;
3602         if (ss.dpl != ss_rpl) /* DPL != RPL */
3603                 return false;
3604         if (!ss.present)
3605                 return false;
3606
3607         return true;
3608 }
3609
3610 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3611 {
3612         struct kvm_segment var;
3613         unsigned int rpl;
3614
3615         vmx_get_segment(vcpu, &var, seg);
3616         rpl = var.selector & SELECTOR_RPL_MASK;
3617
3618         if (var.unusable)
3619                 return true;
3620         if (!var.s)
3621                 return false;
3622         if (!var.present)
3623                 return false;
3624         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3625                 if (var.dpl < rpl) /* DPL < RPL */
3626                         return false;
3627         }
3628
3629         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3630          * rights flags
3631          */
3632         return true;
3633 }
3634
3635 static bool tr_valid(struct kvm_vcpu *vcpu)
3636 {
3637         struct kvm_segment tr;
3638
3639         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3640
3641         if (tr.unusable)
3642                 return false;
3643         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3644                 return false;
3645         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3646                 return false;
3647         if (!tr.present)
3648                 return false;
3649
3650         return true;
3651 }
3652
3653 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3654 {
3655         struct kvm_segment ldtr;
3656
3657         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3658
3659         if (ldtr.unusable)
3660                 return true;
3661         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3662                 return false;
3663         if (ldtr.type != 2)
3664                 return false;
3665         if (!ldtr.present)
3666                 return false;
3667
3668         return true;
3669 }
3670
3671 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3672 {
3673         struct kvm_segment cs, ss;
3674
3675         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3676         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3677
3678         return ((cs.selector & SELECTOR_RPL_MASK) ==
3679                  (ss.selector & SELECTOR_RPL_MASK));
3680 }
3681
3682 /*
3683  * Check if guest state is valid. Returns true if valid, false if
3684  * not.
3685  * We assume that registers are always usable
3686  */
3687 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3688 {
3689         if (enable_unrestricted_guest)
3690                 return true;
3691
3692         /* real mode guest state checks */
3693         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3694                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3695                         return false;
3696                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3697                         return false;
3698                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3699                         return false;
3700                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3701                         return false;
3702                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3703                         return false;
3704                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3705                         return false;
3706         } else {
3707         /* protected mode guest state checks */
3708                 if (!cs_ss_rpl_check(vcpu))
3709                         return false;
3710                 if (!code_segment_valid(vcpu))
3711                         return false;
3712                 if (!stack_segment_valid(vcpu))
3713                         return false;
3714                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3715                         return false;
3716                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3717                         return false;
3718                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3719                         return false;
3720                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3721                         return false;
3722                 if (!tr_valid(vcpu))
3723                         return false;
3724                 if (!ldtr_valid(vcpu))
3725                         return false;
3726         }
3727         /* TODO:
3728          * - Add checks on RIP
3729          * - Add checks on RFLAGS
3730          */
3731
3732         return true;
3733 }
3734
3735 static int init_rmode_tss(struct kvm *kvm)
3736 {
3737         gfn_t fn;
3738         u16 data = 0;
3739         int r, idx, ret = 0;
3740
3741         idx = srcu_read_lock(&kvm->srcu);
3742         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3743         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3744         if (r < 0)
3745                 goto out;
3746         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3747         r = kvm_write_guest_page(kvm, fn++, &data,
3748                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3749         if (r < 0)
3750                 goto out;
3751         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3752         if (r < 0)
3753                 goto out;
3754         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3755         if (r < 0)
3756                 goto out;
3757         data = ~0;
3758         r = kvm_write_guest_page(kvm, fn, &data,
3759                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3760                                  sizeof(u8));
3761         if (r < 0)
3762                 goto out;
3763
3764         ret = 1;
3765 out:
3766         srcu_read_unlock(&kvm->srcu, idx);
3767         return ret;
3768 }
3769
3770 static int init_rmode_identity_map(struct kvm *kvm)
3771 {
3772         int i, idx, r, ret;
3773         pfn_t identity_map_pfn;
3774         u32 tmp;
3775
3776         if (!enable_ept)
3777                 return 1;
3778         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3779                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3780                         "haven't been allocated!\n");
3781                 return 0;
3782         }
3783         if (likely(kvm->arch.ept_identity_pagetable_done))
3784                 return 1;
3785         ret = 0;
3786         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3787         idx = srcu_read_lock(&kvm->srcu);
3788         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3789         if (r < 0)
3790                 goto out;
3791         /* Set up identity-mapping pagetable for EPT in real mode */
3792         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3793                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3794                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3795                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3796                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3797                 if (r < 0)
3798                         goto out;
3799         }
3800         kvm->arch.ept_identity_pagetable_done = true;
3801         ret = 1;
3802 out:
3803         srcu_read_unlock(&kvm->srcu, idx);
3804         return ret;
3805 }
3806
3807 static void seg_setup(int seg)
3808 {
3809         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3810         unsigned int ar;
3811
3812         vmcs_write16(sf->selector, 0);
3813         vmcs_writel(sf->base, 0);
3814         vmcs_write32(sf->limit, 0xffff);
3815         ar = 0x93;
3816         if (seg == VCPU_SREG_CS)
3817                 ar |= 0x08; /* code segment */
3818
3819         vmcs_write32(sf->ar_bytes, ar);
3820 }
3821
3822 static int alloc_apic_access_page(struct kvm *kvm)
3823 {
3824         struct page *page;
3825         struct kvm_userspace_memory_region kvm_userspace_mem;
3826         int r = 0;
3827
3828         mutex_lock(&kvm->slots_lock);
3829         if (kvm->arch.apic_access_page)
3830                 goto out;
3831         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3832         kvm_userspace_mem.flags = 0;
3833         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3834         kvm_userspace_mem.memory_size = PAGE_SIZE;
3835         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3836         if (r)
3837                 goto out;
3838
3839         page = gfn_to_page(kvm, 0xfee00);
3840         if (is_error_page(page)) {
3841                 r = -EFAULT;
3842                 goto out;
3843         }
3844
3845         kvm->arch.apic_access_page = page;
3846 out:
3847         mutex_unlock(&kvm->slots_lock);
3848         return r;
3849 }
3850
3851 static int alloc_identity_pagetable(struct kvm *kvm)
3852 {
3853         struct page *page;
3854         struct kvm_userspace_memory_region kvm_userspace_mem;
3855         int r = 0;
3856
3857         mutex_lock(&kvm->slots_lock);
3858         if (kvm->arch.ept_identity_pagetable)
3859                 goto out;
3860         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3861         kvm_userspace_mem.flags = 0;
3862         kvm_userspace_mem.guest_phys_addr =
3863                 kvm->arch.ept_identity_map_addr;
3864         kvm_userspace_mem.memory_size = PAGE_SIZE;
3865         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3866         if (r)
3867                 goto out;
3868
3869         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3870         if (is_error_page(page)) {
3871                 r = -EFAULT;
3872                 goto out;
3873         }
3874
3875         kvm->arch.ept_identity_pagetable = page;
3876 out:
3877         mutex_unlock(&kvm->slots_lock);
3878         return r;
3879 }
3880
3881 static void allocate_vpid(struct vcpu_vmx *vmx)
3882 {
3883         int vpid;
3884
3885         vmx->vpid = 0;
3886         if (!enable_vpid)
3887                 return;
3888         spin_lock(&vmx_vpid_lock);
3889         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3890         if (vpid < VMX_NR_VPIDS) {
3891                 vmx->vpid = vpid;
3892                 __set_bit(vpid, vmx_vpid_bitmap);
3893         }
3894         spin_unlock(&vmx_vpid_lock);
3895 }
3896
3897 static void free_vpid(struct vcpu_vmx *vmx)
3898 {
3899         if (!enable_vpid)
3900                 return;
3901         spin_lock(&vmx_vpid_lock);
3902         if (vmx->vpid != 0)
3903                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3904         spin_unlock(&vmx_vpid_lock);
3905 }
3906
3907 #define MSR_TYPE_R      1
3908 #define MSR_TYPE_W      2
3909 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3910                                                 u32 msr, int type)
3911 {
3912         int f = sizeof(unsigned long);
3913
3914         if (!cpu_has_vmx_msr_bitmap())
3915                 return;
3916
3917         /*
3918          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3919          * have the write-low and read-high bitmap offsets the wrong way round.
3920          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3921          */
3922         if (msr <= 0x1fff) {
3923                 if (type & MSR_TYPE_R)
3924                         /* read-low */
3925                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3926
3927                 if (type & MSR_TYPE_W)
3928                         /* write-low */
3929                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3930
3931         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3932                 msr &= 0x1fff;
3933                 if (type & MSR_TYPE_R)
3934                         /* read-high */
3935                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3936
3937                 if (type & MSR_TYPE_W)
3938                         /* write-high */
3939                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3940
3941         }
3942 }
3943
3944 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3945                                                 u32 msr, int type)
3946 {
3947         int f = sizeof(unsigned long);
3948
3949         if (!cpu_has_vmx_msr_bitmap())
3950                 return;
3951
3952         /*
3953          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3954          * have the write-low and read-high bitmap offsets the wrong way round.
3955          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3956          */
3957         if (msr <= 0x1fff) {
3958                 if (type & MSR_TYPE_R)
3959                         /* read-low */
3960                         __set_bit(msr, msr_bitmap + 0x000 / f);
3961
3962                 if (type & MSR_TYPE_W)
3963                         /* write-low */
3964                         __set_bit(msr, msr_bitmap + 0x800 / f);
3965
3966         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3967                 msr &= 0x1fff;
3968                 if (type & MSR_TYPE_R)
3969                         /* read-high */
3970                         __set_bit(msr, msr_bitmap + 0x400 / f);
3971
3972                 if (type & MSR_TYPE_W)
3973                         /* write-high */
3974                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3975
3976         }
3977 }
3978
3979 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3980 {
3981         if (!longmode_only)
3982                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3983                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3984         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3985                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3986 }
3987
3988 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3989 {
3990         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3991                         msr, MSR_TYPE_R);
3992         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3993                         msr, MSR_TYPE_R);
3994 }
3995
3996 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3997 {
3998         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3999                         msr, MSR_TYPE_R);
4000         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4001                         msr, MSR_TYPE_R);
4002 }
4003
4004 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4005 {
4006         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4007                         msr, MSR_TYPE_W);
4008         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4009                         msr, MSR_TYPE_W);
4010 }
4011
4012 static int vmx_vm_has_apicv(struct kvm *kvm)
4013 {
4014         return enable_apicv && irqchip_in_kernel(kvm);
4015 }
4016
4017 /*
4018  * Send interrupt to vcpu via posted interrupt way.
4019  * 1. If target vcpu is running(non-root mode), send posted interrupt
4020  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4021  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4022  * interrupt from PIR in next vmentry.
4023  */
4024 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4025 {
4026         struct vcpu_vmx *vmx = to_vmx(vcpu);
4027         int r;
4028
4029         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4030                 return;
4031
4032         r = pi_test_and_set_on(&vmx->pi_desc);
4033         kvm_make_request(KVM_REQ_EVENT, vcpu);
4034 #ifdef CONFIG_SMP
4035         if (!r && (vcpu->mode == IN_GUEST_MODE))
4036                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4037                                 POSTED_INTR_VECTOR);
4038         else
4039 #endif
4040                 kvm_vcpu_kick(vcpu);
4041 }
4042
4043 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4044 {
4045         struct vcpu_vmx *vmx = to_vmx(vcpu);
4046
4047         if (!pi_test_and_clear_on(&vmx->pi_desc))
4048                 return;
4049
4050         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4051 }
4052
4053 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4054 {
4055         return;
4056 }
4057
4058 /*
4059  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4060  * will not change in the lifetime of the guest.
4061  * Note that host-state that does change is set elsewhere. E.g., host-state
4062  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4063  */
4064 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4065 {
4066         u32 low32, high32;
4067         unsigned long tmpl;
4068         struct desc_ptr dt;
4069
4070         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4071         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4072         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4073
4074         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4075 #ifdef CONFIG_X86_64
4076         /*
4077          * Load null selectors, so we can avoid reloading them in
4078          * __vmx_load_host_state(), in case userspace uses the null selectors
4079          * too (the expected case).
4080          */
4081         vmcs_write16(HOST_DS_SELECTOR, 0);
4082         vmcs_write16(HOST_ES_SELECTOR, 0);
4083 #else
4084         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4085         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4086 #endif
4087         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4088         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4089
4090         native_store_idt(&dt);
4091         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4092         vmx->host_idt_base = dt.address;
4093
4094         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4095
4096         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4097         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4098         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4099         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4100
4101         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4102                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4103                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4104         }
4105 }
4106
4107 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4108 {
4109         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4110         if (enable_ept)
4111                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4112         if (is_guest_mode(&vmx->vcpu))
4113                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4114                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4115         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4116 }
4117
4118 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4119 {
4120         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4121
4122         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4123                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4124         return pin_based_exec_ctrl;
4125 }
4126
4127 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4128 {
4129         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4130         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4131                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4132 #ifdef CONFIG_X86_64
4133                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4134                                 CPU_BASED_CR8_LOAD_EXITING;
4135 #endif
4136         }
4137         if (!enable_ept)
4138                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4139                                 CPU_BASED_CR3_LOAD_EXITING  |
4140                                 CPU_BASED_INVLPG_EXITING;
4141         return exec_control;
4142 }
4143
4144 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4145 {
4146         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4147         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4148                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4149         if (vmx->vpid == 0)
4150                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4151         if (!enable_ept) {
4152                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4153                 enable_unrestricted_guest = 0;
4154                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4155                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4156         }
4157         if (!enable_unrestricted_guest)
4158                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4159         if (!ple_gap)
4160                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4161         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4162                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4163                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4164         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4165         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4166            (handle_vmptrld).
4167            We can NOT enable shadow_vmcs here because we don't have yet
4168            a current VMCS12
4169         */
4170         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4171         return exec_control;
4172 }
4173
4174 static void ept_set_mmio_spte_mask(void)
4175 {
4176         /*
4177          * EPT Misconfigurations can be generated if the value of bits 2:0
4178          * of an EPT paging-structure entry is 110b (write/execute).
4179          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
4180          * spte.
4181          */
4182         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
4183 }
4184
4185 /*
4186  * Sets up the vmcs for emulated real mode.
4187  */
4188 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4189 {
4190 #ifdef CONFIG_X86_64
4191         unsigned long a;
4192 #endif
4193         int i;
4194
4195         /* I/O */
4196         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4197         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4198
4199         if (enable_shadow_vmcs) {
4200                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4201                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4202         }
4203         if (cpu_has_vmx_msr_bitmap())
4204                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4205
4206         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4207
4208         /* Control */
4209         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4210
4211         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4212
4213         if (cpu_has_secondary_exec_ctrls()) {
4214                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4215                                 vmx_secondary_exec_control(vmx));
4216         }
4217
4218         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4219                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4220                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4221                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4222                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4223
4224                 vmcs_write16(GUEST_INTR_STATUS, 0);
4225
4226                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4227                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4228         }
4229
4230         if (ple_gap) {
4231                 vmcs_write32(PLE_GAP, ple_gap);
4232                 vmcs_write32(PLE_WINDOW, ple_window);
4233         }
4234
4235         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4236         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4237         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4238
4239         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4240         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4241         vmx_set_constant_host_state(vmx);
4242 #ifdef CONFIG_X86_64
4243         rdmsrl(MSR_FS_BASE, a);
4244         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4245         rdmsrl(MSR_GS_BASE, a);
4246         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4247 #else
4248         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4249         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4250 #endif
4251
4252         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4253         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4254         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4255         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4256         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4257
4258         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4259                 u32 msr_low, msr_high;
4260                 u64 host_pat;
4261                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4262                 host_pat = msr_low | ((u64) msr_high << 32);
4263                 /* Write the default value follow host pat */
4264                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4265                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4266                 vmx->vcpu.arch.pat = host_pat;
4267         }
4268
4269         for (i = 0; i < NR_VMX_MSR; ++i) {
4270                 u32 index = vmx_msr_index[i];
4271                 u32 data_low, data_high;
4272                 int j = vmx->nmsrs;
4273
4274                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4275                         continue;
4276                 if (wrmsr_safe(index, data_low, data_high) < 0)
4277                         continue;
4278                 vmx->guest_msrs[j].index = i;
4279                 vmx->guest_msrs[j].data = 0;
4280                 vmx->guest_msrs[j].mask = -1ull;
4281                 ++vmx->nmsrs;
4282         }
4283
4284         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4285
4286         /* 22.2.1, 20.8.1 */
4287         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4288
4289         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4290         set_cr4_guest_host_mask(vmx);
4291
4292         return 0;
4293 }
4294
4295 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4296 {
4297         struct vcpu_vmx *vmx = to_vmx(vcpu);
4298         u64 msr;
4299
4300         vmx->rmode.vm86_active = 0;
4301
4302         vmx->soft_vnmi_blocked = 0;
4303
4304         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4305         kvm_set_cr8(&vmx->vcpu, 0);
4306         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4307         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4308                 msr |= MSR_IA32_APICBASE_BSP;
4309         kvm_set_apic_base(&vmx->vcpu, msr);
4310
4311         vmx_segment_cache_clear(vmx);
4312
4313         seg_setup(VCPU_SREG_CS);
4314         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4315         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4316
4317         seg_setup(VCPU_SREG_DS);
4318         seg_setup(VCPU_SREG_ES);
4319         seg_setup(VCPU_SREG_FS);
4320         seg_setup(VCPU_SREG_GS);
4321         seg_setup(VCPU_SREG_SS);
4322
4323         vmcs_write16(GUEST_TR_SELECTOR, 0);
4324         vmcs_writel(GUEST_TR_BASE, 0);
4325         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4326         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4327
4328         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4329         vmcs_writel(GUEST_LDTR_BASE, 0);
4330         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4331         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4332
4333         vmcs_write32(GUEST_SYSENTER_CS, 0);
4334         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4335         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4336
4337         vmcs_writel(GUEST_RFLAGS, 0x02);
4338         kvm_rip_write(vcpu, 0xfff0);
4339
4340         vmcs_writel(GUEST_GDTR_BASE, 0);
4341         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4342
4343         vmcs_writel(GUEST_IDTR_BASE, 0);
4344         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4345
4346         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4347         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4348         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4349
4350         /* Special registers */
4351         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4352
4353         setup_msrs(vmx);
4354
4355         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4356
4357         if (cpu_has_vmx_tpr_shadow()) {
4358                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4359                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4360                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4361                                      __pa(vmx->vcpu.arch.apic->regs));
4362                 vmcs_write32(TPR_THRESHOLD, 0);
4363         }
4364
4365         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4366                 vmcs_write64(APIC_ACCESS_ADDR,
4367                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4368
4369         if (vmx_vm_has_apicv(vcpu->kvm))
4370                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4371
4372         if (vmx->vpid != 0)
4373                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4374
4375         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4376         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4377         vmx_set_cr4(&vmx->vcpu, 0);
4378         vmx_set_efer(&vmx->vcpu, 0);
4379         vmx_fpu_activate(&vmx->vcpu);
4380         update_exception_bitmap(&vmx->vcpu);
4381
4382         vpid_sync_context(vmx);
4383 }
4384
4385 /*
4386  * In nested virtualization, check if L1 asked to exit on external interrupts.
4387  * For most existing hypervisors, this will always return true.
4388  */
4389 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4390 {
4391         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4392                 PIN_BASED_EXT_INTR_MASK;
4393 }
4394
4395 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4396 {
4397         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4398                 PIN_BASED_NMI_EXITING;
4399 }
4400
4401 static int enable_irq_window(struct kvm_vcpu *vcpu)
4402 {
4403         u32 cpu_based_vm_exec_control;
4404
4405         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4406                 /*
4407                  * We get here if vmx_interrupt_allowed() said we can't
4408                  * inject to L1 now because L2 must run. The caller will have
4409                  * to make L2 exit right after entry, so we can inject to L1
4410                  * more promptly.
4411                  */
4412                 return -EBUSY;
4413
4414         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4415         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4416         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4417         return 0;
4418 }
4419
4420 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4421 {
4422         u32 cpu_based_vm_exec_control;
4423
4424         if (!cpu_has_virtual_nmis())
4425                 return enable_irq_window(vcpu);
4426
4427         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4428                 return enable_irq_window(vcpu);
4429
4430         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4431         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4432         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4433         return 0;
4434 }
4435
4436 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4437 {
4438         struct vcpu_vmx *vmx = to_vmx(vcpu);
4439         uint32_t intr;
4440         int irq = vcpu->arch.interrupt.nr;
4441
4442         trace_kvm_inj_virq(irq);
4443
4444         ++vcpu->stat.irq_injections;
4445         if (vmx->rmode.vm86_active) {
4446                 int inc_eip = 0;
4447                 if (vcpu->arch.interrupt.soft)
4448                         inc_eip = vcpu->arch.event_exit_inst_len;
4449                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4450                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4451                 return;
4452         }
4453         intr = irq | INTR_INFO_VALID_MASK;
4454         if (vcpu->arch.interrupt.soft) {
4455                 intr |= INTR_TYPE_SOFT_INTR;
4456                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4457                              vmx->vcpu.arch.event_exit_inst_len);
4458         } else
4459                 intr |= INTR_TYPE_EXT_INTR;
4460         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4461 }
4462
4463 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4464 {
4465         struct vcpu_vmx *vmx = to_vmx(vcpu);
4466
4467         if (is_guest_mode(vcpu))
4468                 return;
4469
4470         if (!cpu_has_virtual_nmis()) {
4471                 /*
4472                  * Tracking the NMI-blocked state in software is built upon
4473                  * finding the next open IRQ window. This, in turn, depends on
4474                  * well-behaving guests: They have to keep IRQs disabled at
4475                  * least as long as the NMI handler runs. Otherwise we may
4476                  * cause NMI nesting, maybe breaking the guest. But as this is
4477                  * highly unlikely, we can live with the residual risk.
4478                  */
4479                 vmx->soft_vnmi_blocked = 1;
4480                 vmx->vnmi_blocked_time = 0;
4481         }
4482
4483         ++vcpu->stat.nmi_injections;
4484         vmx->nmi_known_unmasked = false;
4485         if (vmx->rmode.vm86_active) {
4486                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4487                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4488                 return;
4489         }
4490         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4491                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4492 }
4493
4494 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4495 {
4496         if (!cpu_has_virtual_nmis())
4497                 return to_vmx(vcpu)->soft_vnmi_blocked;
4498         if (to_vmx(vcpu)->nmi_known_unmasked)
4499                 return false;
4500         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4501 }
4502
4503 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4504 {
4505         struct vcpu_vmx *vmx = to_vmx(vcpu);
4506
4507         if (!cpu_has_virtual_nmis()) {
4508                 if (vmx->soft_vnmi_blocked != masked) {
4509                         vmx->soft_vnmi_blocked = masked;
4510                         vmx->vnmi_blocked_time = 0;
4511                 }
4512         } else {
4513                 vmx->nmi_known_unmasked = !masked;
4514                 if (masked)
4515                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4516                                       GUEST_INTR_STATE_NMI);
4517                 else
4518                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4519                                         GUEST_INTR_STATE_NMI);
4520         }
4521 }
4522
4523 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4524 {
4525         if (is_guest_mode(vcpu)) {
4526                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4527
4528                 if (to_vmx(vcpu)->nested.nested_run_pending)
4529                         return 0;
4530                 if (nested_exit_on_nmi(vcpu)) {
4531                         nested_vmx_vmexit(vcpu);
4532                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4533                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4534                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4535                         /*
4536                          * The NMI-triggered VM exit counts as injection:
4537                          * clear this one and block further NMIs.
4538                          */
4539                         vcpu->arch.nmi_pending = 0;
4540                         vmx_set_nmi_mask(vcpu, true);
4541                         return 0;
4542                 }
4543         }
4544
4545         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4546                 return 0;
4547
4548         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4549                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4550                    | GUEST_INTR_STATE_NMI));
4551 }
4552
4553 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4554 {
4555         if (is_guest_mode(vcpu)) {
4556                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4557
4558                 if (to_vmx(vcpu)->nested.nested_run_pending)
4559                         return 0;
4560                 if (nested_exit_on_intr(vcpu)) {
4561                         nested_vmx_vmexit(vcpu);
4562                         vmcs12->vm_exit_reason =
4563                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4564                         vmcs12->vm_exit_intr_info = 0;
4565                         /*
4566                          * fall through to normal code, but now in L1, not L2
4567                          */
4568                 }
4569         }
4570
4571         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4572                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4573                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4574 }
4575
4576 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4577 {
4578         int ret;
4579         struct kvm_userspace_memory_region tss_mem = {
4580                 .slot = TSS_PRIVATE_MEMSLOT,
4581                 .guest_phys_addr = addr,
4582                 .memory_size = PAGE_SIZE * 3,
4583                 .flags = 0,
4584         };
4585
4586         ret = kvm_set_memory_region(kvm, &tss_mem);
4587         if (ret)
4588                 return ret;
4589         kvm->arch.tss_addr = addr;
4590         if (!init_rmode_tss(kvm))
4591                 return  -ENOMEM;
4592
4593         return 0;
4594 }
4595
4596 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4597 {
4598         switch (vec) {
4599         case BP_VECTOR:
4600                 /*
4601                  * Update instruction length as we may reinject the exception
4602                  * from user space while in guest debugging mode.
4603                  */
4604                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4605                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4606                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4607                         return false;
4608                 /* fall through */
4609         case DB_VECTOR:
4610                 if (vcpu->guest_debug &
4611                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4612                         return false;
4613                 /* fall through */
4614         case DE_VECTOR:
4615         case OF_VECTOR:
4616         case BR_VECTOR:
4617         case UD_VECTOR:
4618         case DF_VECTOR:
4619         case SS_VECTOR:
4620         case GP_VECTOR:
4621         case MF_VECTOR:
4622                 return true;
4623         break;
4624         }
4625         return false;
4626 }
4627
4628 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4629                                   int vec, u32 err_code)
4630 {
4631         /*
4632          * Instruction with address size override prefix opcode 0x67
4633          * Cause the #SS fault with 0 error code in VM86 mode.
4634          */
4635         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4636                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4637                         if (vcpu->arch.halt_request) {
4638                                 vcpu->arch.halt_request = 0;
4639                                 return kvm_emulate_halt(vcpu);
4640                         }
4641                         return 1;
4642                 }
4643                 return 0;
4644         }
4645
4646         /*
4647          * Forward all other exceptions that are valid in real mode.
4648          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4649          *        the required debugging infrastructure rework.
4650          */
4651         kvm_queue_exception(vcpu, vec);
4652         return 1;
4653 }
4654
4655 /*
4656  * Trigger machine check on the host. We assume all the MSRs are already set up
4657  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4658  * We pass a fake environment to the machine check handler because we want
4659  * the guest to be always treated like user space, no matter what context
4660  * it used internally.
4661  */
4662 static void kvm_machine_check(void)
4663 {
4664 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4665         struct pt_regs regs = {
4666                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4667                 .flags = X86_EFLAGS_IF,
4668         };
4669
4670         do_machine_check(&regs, 0);
4671 #endif
4672 }
4673
4674 static int handle_machine_check(struct kvm_vcpu *vcpu)
4675 {
4676         /* already handled by vcpu_run */
4677         return 1;
4678 }
4679
4680 static int handle_exception(struct kvm_vcpu *vcpu)
4681 {
4682         struct vcpu_vmx *vmx = to_vmx(vcpu);
4683         struct kvm_run *kvm_run = vcpu->run;
4684         u32 intr_info, ex_no, error_code;
4685         unsigned long cr2, rip, dr6;
4686         u32 vect_info;
4687         enum emulation_result er;
4688
4689         vect_info = vmx->idt_vectoring_info;
4690         intr_info = vmx->exit_intr_info;
4691
4692         if (is_machine_check(intr_info))
4693                 return handle_machine_check(vcpu);
4694
4695         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4696                 return 1;  /* already handled by vmx_vcpu_run() */
4697
4698         if (is_no_device(intr_info)) {
4699                 vmx_fpu_activate(vcpu);
4700                 return 1;
4701         }
4702
4703         if (is_invalid_opcode(intr_info)) {
4704                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4705                 if (er != EMULATE_DONE)
4706                         kvm_queue_exception(vcpu, UD_VECTOR);
4707                 return 1;
4708         }
4709
4710         error_code = 0;
4711         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4712                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4713
4714         /*
4715          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4716          * MMIO, it is better to report an internal error.
4717          * See the comments in vmx_handle_exit.
4718          */
4719         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4720             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4721                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4722                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4723                 vcpu->run->internal.ndata = 2;
4724                 vcpu->run->internal.data[0] = vect_info;
4725                 vcpu->run->internal.data[1] = intr_info;
4726                 return 0;
4727         }
4728
4729         if (is_page_fault(intr_info)) {
4730                 /* EPT won't cause page fault directly */
4731                 BUG_ON(enable_ept);
4732                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4733                 trace_kvm_page_fault(cr2, error_code);
4734
4735                 if (kvm_event_needs_reinjection(vcpu))
4736                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4737                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4738         }
4739
4740         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4741
4742         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4743                 return handle_rmode_exception(vcpu, ex_no, error_code);
4744
4745         switch (ex_no) {
4746         case DB_VECTOR:
4747                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4748                 if (!(vcpu->guest_debug &
4749                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4750                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4751                         kvm_queue_exception(vcpu, DB_VECTOR);
4752                         return 1;
4753                 }
4754                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4755                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4756                 /* fall through */
4757         case BP_VECTOR:
4758                 /*
4759                  * Update instruction length as we may reinject #BP from
4760                  * user space while in guest debugging mode. Reading it for
4761                  * #DB as well causes no harm, it is not used in that case.
4762                  */
4763                 vmx->vcpu.arch.event_exit_inst_len =
4764                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4765                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4766                 rip = kvm_rip_read(vcpu);
4767                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4768                 kvm_run->debug.arch.exception = ex_no;
4769                 break;
4770         default:
4771                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4772                 kvm_run->ex.exception = ex_no;
4773                 kvm_run->ex.error_code = error_code;
4774                 break;
4775         }
4776         return 0;
4777 }
4778
4779 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4780 {
4781         ++vcpu->stat.irq_exits;
4782         return 1;
4783 }
4784
4785 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4786 {
4787         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4788         return 0;
4789 }
4790
4791 static int handle_io(struct kvm_vcpu *vcpu)
4792 {
4793         unsigned long exit_qualification;
4794         int size, in, string;
4795         unsigned port;
4796
4797         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4798         string = (exit_qualification & 16) != 0;
4799         in = (exit_qualification & 8) != 0;
4800
4801         ++vcpu->stat.io_exits;
4802
4803         if (string || in)
4804                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4805
4806         port = exit_qualification >> 16;
4807         size = (exit_qualification & 7) + 1;
4808         skip_emulated_instruction(vcpu);
4809
4810         return kvm_fast_pio_out(vcpu, size, port);
4811 }
4812
4813 static void
4814 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4815 {
4816         /*
4817          * Patch in the VMCALL instruction:
4818          */
4819         hypercall[0] = 0x0f;
4820         hypercall[1] = 0x01;
4821         hypercall[2] = 0xc1;
4822 }
4823
4824 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4825 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4826 {
4827         if (is_guest_mode(vcpu)) {
4828                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4829                 unsigned long orig_val = val;
4830
4831                 /*
4832                  * We get here when L2 changed cr0 in a way that did not change
4833                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4834                  * but did change L0 shadowed bits. So we first calculate the
4835                  * effective cr0 value that L1 would like to write into the
4836                  * hardware. It consists of the L2-owned bits from the new
4837                  * value combined with the L1-owned bits from L1's guest_cr0.
4838                  */
4839                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4840                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4841
4842                 /* TODO: will have to take unrestricted guest mode into
4843                  * account */
4844                 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4845                         return 1;
4846
4847                 if (kvm_set_cr0(vcpu, val))
4848                         return 1;
4849                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4850                 return 0;
4851         } else {
4852                 if (to_vmx(vcpu)->nested.vmxon &&
4853                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4854                         return 1;
4855                 return kvm_set_cr0(vcpu, val);
4856         }
4857 }
4858
4859 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4860 {
4861         if (is_guest_mode(vcpu)) {
4862                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4863                 unsigned long orig_val = val;
4864
4865                 /* analogously to handle_set_cr0 */
4866                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4867                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4868                 if (kvm_set_cr4(vcpu, val))
4869                         return 1;
4870                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4871                 return 0;
4872         } else
4873                 return kvm_set_cr4(vcpu, val);
4874 }
4875
4876 /* called to set cr0 as approriate for clts instruction exit. */
4877 static void handle_clts(struct kvm_vcpu *vcpu)
4878 {
4879         if (is_guest_mode(vcpu)) {
4880                 /*
4881                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4882                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4883                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4884                  */
4885                 vmcs_writel(CR0_READ_SHADOW,
4886                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4887                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4888         } else
4889                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4890 }
4891
4892 static int handle_cr(struct kvm_vcpu *vcpu)
4893 {
4894         unsigned long exit_qualification, val;
4895         int cr;
4896         int reg;
4897         int err;
4898
4899         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4900         cr = exit_qualification & 15;
4901         reg = (exit_qualification >> 8) & 15;
4902         switch ((exit_qualification >> 4) & 3) {
4903         case 0: /* mov to cr */
4904                 val = kvm_register_read(vcpu, reg);
4905                 trace_kvm_cr_write(cr, val);
4906                 switch (cr) {
4907                 case 0:
4908                         err = handle_set_cr0(vcpu, val);
4909                         kvm_complete_insn_gp(vcpu, err);
4910                         return 1;
4911                 case 3:
4912                         err = kvm_set_cr3(vcpu, val);
4913                         kvm_complete_insn_gp(vcpu, err);
4914                         return 1;
4915                 case 4:
4916                         err = handle_set_cr4(vcpu, val);
4917                         kvm_complete_insn_gp(vcpu, err);
4918                         return 1;
4919                 case 8: {
4920                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4921                                 u8 cr8 = kvm_register_read(vcpu, reg);
4922                                 err = kvm_set_cr8(vcpu, cr8);
4923                                 kvm_complete_insn_gp(vcpu, err);
4924                                 if (irqchip_in_kernel(vcpu->kvm))
4925                                         return 1;
4926                                 if (cr8_prev <= cr8)
4927                                         return 1;
4928                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4929                                 return 0;
4930                         }
4931                 }
4932                 break;
4933         case 2: /* clts */
4934                 handle_clts(vcpu);
4935                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4936                 skip_emulated_instruction(vcpu);
4937                 vmx_fpu_activate(vcpu);
4938                 return 1;
4939         case 1: /*mov from cr*/
4940                 switch (cr) {
4941                 case 3:
4942                         val = kvm_read_cr3(vcpu);
4943                         kvm_register_write(vcpu, reg, val);
4944                         trace_kvm_cr_read(cr, val);
4945                         skip_emulated_instruction(vcpu);
4946                         return 1;
4947                 case 8:
4948                         val = kvm_get_cr8(vcpu);
4949                         kvm_register_write(vcpu, reg, val);
4950                         trace_kvm_cr_read(cr, val);
4951                         skip_emulated_instruction(vcpu);
4952                         return 1;
4953                 }
4954                 break;
4955         case 3: /* lmsw */
4956                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4957                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4958                 kvm_lmsw(vcpu, val);
4959
4960                 skip_emulated_instruction(vcpu);
4961                 return 1;
4962         default:
4963                 break;
4964         }
4965         vcpu->run->exit_reason = 0;
4966         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4967                (int)(exit_qualification >> 4) & 3, cr);
4968         return 0;
4969 }
4970
4971 static int handle_dr(struct kvm_vcpu *vcpu)
4972 {
4973         unsigned long exit_qualification;
4974         int dr, reg;
4975
4976         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4977         if (!kvm_require_cpl(vcpu, 0))
4978                 return 1;
4979         dr = vmcs_readl(GUEST_DR7);
4980         if (dr & DR7_GD) {
4981                 /*
4982                  * As the vm-exit takes precedence over the debug trap, we
4983                  * need to emulate the latter, either for the host or the
4984                  * guest debugging itself.
4985                  */
4986                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4987                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4988                         vcpu->run->debug.arch.dr7 = dr;
4989                         vcpu->run->debug.arch.pc =
4990                                 vmcs_readl(GUEST_CS_BASE) +
4991                                 vmcs_readl(GUEST_RIP);
4992                         vcpu->run->debug.arch.exception = DB_VECTOR;
4993                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4994                         return 0;
4995                 } else {
4996                         vcpu->arch.dr7 &= ~DR7_GD;
4997                         vcpu->arch.dr6 |= DR6_BD;
4998                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4999                         kvm_queue_exception(vcpu, DB_VECTOR);
5000                         return 1;
5001                 }
5002         }
5003
5004         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5005         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5006         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5007         if (exit_qualification & TYPE_MOV_FROM_DR) {
5008                 unsigned long val;
5009                 if (!kvm_get_dr(vcpu, dr, &val))
5010                         kvm_register_write(vcpu, reg, val);
5011         } else
5012                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5013         skip_emulated_instruction(vcpu);
5014         return 1;
5015 }
5016
5017 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5018 {
5019         vmcs_writel(GUEST_DR7, val);
5020 }
5021
5022 static int handle_cpuid(struct kvm_vcpu *vcpu)
5023 {
5024         kvm_emulate_cpuid(vcpu);
5025         return 1;
5026 }
5027
5028 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5029 {
5030         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5031         u64 data;
5032
5033         if (vmx_get_msr(vcpu, ecx, &data)) {
5034                 trace_kvm_msr_read_ex(ecx);
5035                 kvm_inject_gp(vcpu, 0);
5036                 return 1;
5037         }
5038
5039         trace_kvm_msr_read(ecx, data);
5040
5041         /* FIXME: handling of bits 32:63 of rax, rdx */
5042         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5043         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5044         skip_emulated_instruction(vcpu);
5045         return 1;
5046 }
5047
5048 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5049 {
5050         struct msr_data msr;
5051         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5052         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5053                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5054
5055         msr.data = data;
5056         msr.index = ecx;
5057         msr.host_initiated = false;
5058         if (vmx_set_msr(vcpu, &msr) != 0) {
5059                 trace_kvm_msr_write_ex(ecx, data);
5060                 kvm_inject_gp(vcpu, 0);
5061                 return 1;
5062         }
5063
5064         trace_kvm_msr_write(ecx, data);
5065         skip_emulated_instruction(vcpu);
5066         return 1;
5067 }
5068
5069 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5070 {
5071         kvm_make_request(KVM_REQ_EVENT, vcpu);
5072         return 1;
5073 }
5074
5075 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5076 {
5077         u32 cpu_based_vm_exec_control;
5078
5079         /* clear pending irq */
5080         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5081         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5082         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5083
5084         kvm_make_request(KVM_REQ_EVENT, vcpu);
5085
5086         ++vcpu->stat.irq_window_exits;
5087
5088         /*
5089          * If the user space waits to inject interrupts, exit as soon as
5090          * possible
5091          */
5092         if (!irqchip_in_kernel(vcpu->kvm) &&
5093             vcpu->run->request_interrupt_window &&
5094             !kvm_cpu_has_interrupt(vcpu)) {
5095                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5096                 return 0;
5097         }
5098         return 1;
5099 }
5100
5101 static int handle_halt(struct kvm_vcpu *vcpu)
5102 {
5103         skip_emulated_instruction(vcpu);
5104         return kvm_emulate_halt(vcpu);
5105 }
5106
5107 static int handle_vmcall(struct kvm_vcpu *vcpu)
5108 {
5109         skip_emulated_instruction(vcpu);
5110         kvm_emulate_hypercall(vcpu);
5111         return 1;
5112 }
5113
5114 static int handle_invd(struct kvm_vcpu *vcpu)
5115 {
5116         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5117 }
5118
5119 static int handle_invlpg(struct kvm_vcpu *vcpu)
5120 {
5121         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5122
5123         kvm_mmu_invlpg(vcpu, exit_qualification);
5124         skip_emulated_instruction(vcpu);
5125         return 1;
5126 }
5127
5128 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5129 {
5130         int err;
5131
5132         err = kvm_rdpmc(vcpu);
5133         kvm_complete_insn_gp(vcpu, err);
5134
5135         return 1;
5136 }
5137
5138 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5139 {
5140         skip_emulated_instruction(vcpu);
5141         kvm_emulate_wbinvd(vcpu);
5142         return 1;
5143 }
5144
5145 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5146 {
5147         u64 new_bv = kvm_read_edx_eax(vcpu);
5148         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5149
5150         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5151                 skip_emulated_instruction(vcpu);
5152         return 1;
5153 }
5154
5155 static int handle_apic_access(struct kvm_vcpu *vcpu)
5156 {
5157         if (likely(fasteoi)) {
5158                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5159                 int access_type, offset;
5160
5161                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5162                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5163                 /*
5164                  * Sane guest uses MOV to write EOI, with written value
5165                  * not cared. So make a short-circuit here by avoiding
5166                  * heavy instruction emulation.
5167                  */
5168                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5169                     (offset == APIC_EOI)) {
5170                         kvm_lapic_set_eoi(vcpu);
5171                         skip_emulated_instruction(vcpu);
5172                         return 1;
5173                 }
5174         }
5175         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5176 }
5177
5178 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5179 {
5180         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5181         int vector = exit_qualification & 0xff;
5182
5183         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5184         kvm_apic_set_eoi_accelerated(vcpu, vector);
5185         return 1;
5186 }
5187
5188 static int handle_apic_write(struct kvm_vcpu *vcpu)
5189 {
5190         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5191         u32 offset = exit_qualification & 0xfff;
5192
5193         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5194         kvm_apic_write_nodecode(vcpu, offset);
5195         return 1;
5196 }
5197
5198 static int handle_task_switch(struct kvm_vcpu *vcpu)
5199 {
5200         struct vcpu_vmx *vmx = to_vmx(vcpu);
5201         unsigned long exit_qualification;
5202         bool has_error_code = false;
5203         u32 error_code = 0;
5204         u16 tss_selector;
5205         int reason, type, idt_v, idt_index;
5206
5207         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5208         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5209         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5210
5211         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5212
5213         reason = (u32)exit_qualification >> 30;
5214         if (reason == TASK_SWITCH_GATE && idt_v) {
5215                 switch (type) {
5216                 case INTR_TYPE_NMI_INTR:
5217                         vcpu->arch.nmi_injected = false;
5218                         vmx_set_nmi_mask(vcpu, true);
5219                         break;
5220                 case INTR_TYPE_EXT_INTR:
5221                 case INTR_TYPE_SOFT_INTR:
5222                         kvm_clear_interrupt_queue(vcpu);
5223                         break;
5224                 case INTR_TYPE_HARD_EXCEPTION:
5225                         if (vmx->idt_vectoring_info &
5226                             VECTORING_INFO_DELIVER_CODE_MASK) {
5227                                 has_error_code = true;
5228                                 error_code =
5229                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5230                         }
5231                         /* fall through */
5232                 case INTR_TYPE_SOFT_EXCEPTION:
5233                         kvm_clear_exception_queue(vcpu);
5234                         break;
5235                 default:
5236                         break;
5237                 }
5238         }
5239         tss_selector = exit_qualification;
5240
5241         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5242                        type != INTR_TYPE_EXT_INTR &&
5243                        type != INTR_TYPE_NMI_INTR))
5244                 skip_emulated_instruction(vcpu);
5245
5246         if (kvm_task_switch(vcpu, tss_selector,
5247                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5248                             has_error_code, error_code) == EMULATE_FAIL) {
5249                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5250                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5251                 vcpu->run->internal.ndata = 0;
5252                 return 0;
5253         }
5254
5255         /* clear all local breakpoint enable flags */
5256         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5257
5258         /*
5259          * TODO: What about debug traps on tss switch?
5260          *       Are we supposed to inject them and update dr6?
5261          */
5262
5263         return 1;
5264 }
5265
5266 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5267 {
5268         unsigned long exit_qualification;
5269         gpa_t gpa;
5270         u32 error_code;
5271         int gla_validity;
5272
5273         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5274
5275         gla_validity = (exit_qualification >> 7) & 0x3;
5276         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5277                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5278                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5279                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5280                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5281                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5282                         (long unsigned int)exit_qualification);
5283                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5284                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5285                 return 0;
5286         }
5287
5288         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5289         trace_kvm_page_fault(gpa, exit_qualification);
5290
5291         /* It is a write fault? */
5292         error_code = exit_qualification & (1U << 1);
5293         /* ept page table is present? */
5294         error_code |= (exit_qualification >> 3) & 0x1;
5295
5296         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5297 }
5298
5299 static u64 ept_rsvd_mask(u64 spte, int level)
5300 {
5301         int i;
5302         u64 mask = 0;
5303
5304         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5305                 mask |= (1ULL << i);
5306
5307         if (level > 2)
5308                 /* bits 7:3 reserved */
5309                 mask |= 0xf8;
5310         else if (level == 2) {
5311                 if (spte & (1ULL << 7))
5312                         /* 2MB ref, bits 20:12 reserved */
5313                         mask |= 0x1ff000;
5314                 else
5315                         /* bits 6:3 reserved */
5316                         mask |= 0x78;
5317         }
5318
5319         return mask;
5320 }
5321
5322 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5323                                        int level)
5324 {
5325         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5326
5327         /* 010b (write-only) */
5328         WARN_ON((spte & 0x7) == 0x2);
5329
5330         /* 110b (write/execute) */
5331         WARN_ON((spte & 0x7) == 0x6);
5332
5333         /* 100b (execute-only) and value not supported by logical processor */
5334         if (!cpu_has_vmx_ept_execute_only())
5335                 WARN_ON((spte & 0x7) == 0x4);
5336
5337         /* not 000b */
5338         if ((spte & 0x7)) {
5339                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5340
5341                 if (rsvd_bits != 0) {
5342                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5343                                          __func__, rsvd_bits);
5344                         WARN_ON(1);
5345                 }
5346
5347                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5348                         u64 ept_mem_type = (spte & 0x38) >> 3;
5349
5350                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5351                             ept_mem_type == 7) {
5352                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5353                                                 __func__, ept_mem_type);
5354                                 WARN_ON(1);
5355                         }
5356                 }
5357         }
5358 }
5359
5360 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5361 {
5362         u64 sptes[4];
5363         int nr_sptes, i, ret;
5364         gpa_t gpa;
5365
5366         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5367
5368         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5369         if (likely(ret == 1))
5370                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5371                                               EMULATE_DONE;
5372         if (unlikely(!ret))
5373                 return 1;
5374
5375         /* It is the real ept misconfig */
5376         printk(KERN_ERR "EPT: Misconfiguration.\n");
5377         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5378
5379         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5380
5381         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5382                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5383
5384         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5385         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5386
5387         return 0;
5388 }
5389
5390 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5391 {
5392         u32 cpu_based_vm_exec_control;
5393
5394         /* clear pending NMI */
5395         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5396         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5397         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5398         ++vcpu->stat.nmi_window_exits;
5399         kvm_make_request(KVM_REQ_EVENT, vcpu);
5400
5401         return 1;
5402 }
5403
5404 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5405 {
5406         struct vcpu_vmx *vmx = to_vmx(vcpu);
5407         enum emulation_result err = EMULATE_DONE;
5408         int ret = 1;
5409         u32 cpu_exec_ctrl;
5410         bool intr_window_requested;
5411         unsigned count = 130;
5412
5413         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5414         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5415
5416         while (!guest_state_valid(vcpu) && count-- != 0) {
5417                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5418                         return handle_interrupt_window(&vmx->vcpu);
5419
5420                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5421                         return 1;
5422
5423                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5424
5425                 if (err == EMULATE_DO_MMIO) {
5426                         ret = 0;
5427                         goto out;
5428                 }
5429
5430                 if (err != EMULATE_DONE) {
5431                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5432                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5433                         vcpu->run->internal.ndata = 0;
5434                         return 0;
5435                 }
5436
5437                 if (signal_pending(current))
5438                         goto out;
5439                 if (need_resched())
5440                         schedule();
5441         }
5442
5443         vmx->emulation_required = emulation_required(vcpu);
5444 out:
5445         return ret;
5446 }
5447
5448 /*
5449  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5450  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5451  */
5452 static int handle_pause(struct kvm_vcpu *vcpu)
5453 {
5454         skip_emulated_instruction(vcpu);
5455         kvm_vcpu_on_spin(vcpu);
5456
5457         return 1;
5458 }
5459
5460 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5461 {
5462         kvm_queue_exception(vcpu, UD_VECTOR);
5463         return 1;
5464 }
5465
5466 /*
5467  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5468  * We could reuse a single VMCS for all the L2 guests, but we also want the
5469  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5470  * allows keeping them loaded on the processor, and in the future will allow
5471  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5472  * every entry if they never change.
5473  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5474  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5475  *
5476  * The following functions allocate and free a vmcs02 in this pool.
5477  */
5478
5479 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5480 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5481 {
5482         struct vmcs02_list *item;
5483         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5484                 if (item->vmptr == vmx->nested.current_vmptr) {
5485                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5486                         return &item->vmcs02;
5487                 }
5488
5489         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5490                 /* Recycle the least recently used VMCS. */
5491                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5492                         struct vmcs02_list, list);
5493                 item->vmptr = vmx->nested.current_vmptr;
5494                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5495                 return &item->vmcs02;
5496         }
5497
5498         /* Create a new VMCS */
5499         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5500         if (!item)
5501                 return NULL;
5502         item->vmcs02.vmcs = alloc_vmcs();
5503         if (!item->vmcs02.vmcs) {
5504                 kfree(item);
5505                 return NULL;
5506         }
5507         loaded_vmcs_init(&item->vmcs02);
5508         item->vmptr = vmx->nested.current_vmptr;
5509         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5510         vmx->nested.vmcs02_num++;
5511         return &item->vmcs02;
5512 }
5513
5514 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5515 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5516 {
5517         struct vmcs02_list *item;
5518         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5519                 if (item->vmptr == vmptr) {
5520                         free_loaded_vmcs(&item->vmcs02);
5521                         list_del(&item->list);
5522                         kfree(item);
5523                         vmx->nested.vmcs02_num--;
5524                         return;
5525                 }
5526 }
5527
5528 /*
5529  * Free all VMCSs saved for this vcpu, except the one pointed by
5530  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5531  * currently used, if running L2), and vmcs01 when running L2.
5532  */
5533 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5534 {
5535         struct vmcs02_list *item, *n;
5536         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5537                 if (vmx->loaded_vmcs != &item->vmcs02)
5538                         free_loaded_vmcs(&item->vmcs02);
5539                 list_del(&item->list);
5540                 kfree(item);
5541         }
5542         vmx->nested.vmcs02_num = 0;
5543
5544         if (vmx->loaded_vmcs != &vmx->vmcs01)
5545                 free_loaded_vmcs(&vmx->vmcs01);
5546 }
5547
5548 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5549                                  u32 vm_instruction_error);
5550
5551 /*
5552  * Emulate the VMXON instruction.
5553  * Currently, we just remember that VMX is active, and do not save or even
5554  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5555  * do not currently need to store anything in that guest-allocated memory
5556  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5557  * argument is different from the VMXON pointer (which the spec says they do).
5558  */
5559 static int handle_vmon(struct kvm_vcpu *vcpu)
5560 {
5561         struct kvm_segment cs;
5562         struct vcpu_vmx *vmx = to_vmx(vcpu);
5563         struct vmcs *shadow_vmcs;
5564
5565         /* The Intel VMX Instruction Reference lists a bunch of bits that
5566          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5567          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5568          * Otherwise, we should fail with #UD. We test these now:
5569          */
5570         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5571             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5572             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5573                 kvm_queue_exception(vcpu, UD_VECTOR);
5574                 return 1;
5575         }
5576
5577         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5578         if (is_long_mode(vcpu) && !cs.l) {
5579                 kvm_queue_exception(vcpu, UD_VECTOR);
5580                 return 1;
5581         }
5582
5583         if (vmx_get_cpl(vcpu)) {
5584                 kvm_inject_gp(vcpu, 0);
5585                 return 1;
5586         }
5587         if (vmx->nested.vmxon) {
5588                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5589                 skip_emulated_instruction(vcpu);
5590                 return 1;
5591         }
5592         if (enable_shadow_vmcs) {
5593                 shadow_vmcs = alloc_vmcs();
5594                 if (!shadow_vmcs)
5595                         return -ENOMEM;
5596                 /* mark vmcs as shadow */
5597                 shadow_vmcs->revision_id |= (1u << 31);
5598                 /* init shadow vmcs */
5599                 vmcs_clear(shadow_vmcs);
5600                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5601         }
5602
5603         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5604         vmx->nested.vmcs02_num = 0;
5605
5606         vmx->nested.vmxon = true;
5607
5608         skip_emulated_instruction(vcpu);
5609         return 1;
5610 }
5611
5612 /*
5613  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5614  * for running VMX instructions (except VMXON, whose prerequisites are
5615  * slightly different). It also specifies what exception to inject otherwise.
5616  */
5617 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5618 {
5619         struct kvm_segment cs;
5620         struct vcpu_vmx *vmx = to_vmx(vcpu);
5621
5622         if (!vmx->nested.vmxon) {
5623                 kvm_queue_exception(vcpu, UD_VECTOR);
5624                 return 0;
5625         }
5626
5627         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5628         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5629             (is_long_mode(vcpu) && !cs.l)) {
5630                 kvm_queue_exception(vcpu, UD_VECTOR);
5631                 return 0;
5632         }
5633
5634         if (vmx_get_cpl(vcpu)) {
5635                 kvm_inject_gp(vcpu, 0);
5636                 return 0;
5637         }
5638
5639         return 1;
5640 }
5641
5642 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5643 {
5644         u32 exec_control;
5645         if (enable_shadow_vmcs) {
5646                 if (vmx->nested.current_vmcs12 != NULL) {
5647                         /* copy to memory all shadowed fields in case
5648                            they were modified */
5649                         copy_shadow_to_vmcs12(vmx);
5650                         vmx->nested.sync_shadow_vmcs = false;
5651                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5652                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5653                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5654                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5655                 }
5656         }
5657         kunmap(vmx->nested.current_vmcs12_page);
5658         nested_release_page(vmx->nested.current_vmcs12_page);
5659 }
5660
5661 /*
5662  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5663  * just stops using VMX.
5664  */
5665 static void free_nested(struct vcpu_vmx *vmx)
5666 {
5667         if (!vmx->nested.vmxon)
5668                 return;
5669         vmx->nested.vmxon = false;
5670         if (vmx->nested.current_vmptr != -1ull) {
5671                 nested_release_vmcs12(vmx);
5672                 vmx->nested.current_vmptr = -1ull;
5673                 vmx->nested.current_vmcs12 = NULL;
5674         }
5675         if (enable_shadow_vmcs)
5676                 free_vmcs(vmx->nested.current_shadow_vmcs);
5677         /* Unpin physical memory we referred to in current vmcs02 */
5678         if (vmx->nested.apic_access_page) {
5679                 nested_release_page(vmx->nested.apic_access_page);
5680                 vmx->nested.apic_access_page = 0;
5681         }
5682
5683         nested_free_all_saved_vmcss(vmx);
5684 }
5685
5686 /* Emulate the VMXOFF instruction */
5687 static int handle_vmoff(struct kvm_vcpu *vcpu)
5688 {
5689         if (!nested_vmx_check_permission(vcpu))
5690                 return 1;
5691         free_nested(to_vmx(vcpu));
5692         skip_emulated_instruction(vcpu);
5693         return 1;
5694 }
5695
5696 /*
5697  * Decode the memory-address operand of a vmx instruction, as recorded on an
5698  * exit caused by such an instruction (run by a guest hypervisor).
5699  * On success, returns 0. When the operand is invalid, returns 1 and throws
5700  * #UD or #GP.
5701  */
5702 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5703                                  unsigned long exit_qualification,
5704                                  u32 vmx_instruction_info, gva_t *ret)
5705 {
5706         /*
5707          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5708          * Execution", on an exit, vmx_instruction_info holds most of the
5709          * addressing components of the operand. Only the displacement part
5710          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5711          * For how an actual address is calculated from all these components,
5712          * refer to Vol. 1, "Operand Addressing".
5713          */
5714         int  scaling = vmx_instruction_info & 3;
5715         int  addr_size = (vmx_instruction_info >> 7) & 7;
5716         bool is_reg = vmx_instruction_info & (1u << 10);
5717         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5718         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5719         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5720         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5721         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5722
5723         if (is_reg) {
5724                 kvm_queue_exception(vcpu, UD_VECTOR);
5725                 return 1;
5726         }
5727
5728         /* Addr = segment_base + offset */
5729         /* offset = base + [index * scale] + displacement */
5730         *ret = vmx_get_segment_base(vcpu, seg_reg);
5731         if (base_is_valid)
5732                 *ret += kvm_register_read(vcpu, base_reg);
5733         if (index_is_valid)
5734                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5735         *ret += exit_qualification; /* holds the displacement */
5736
5737         if (addr_size == 1) /* 32 bit */
5738                 *ret &= 0xffffffff;
5739
5740         /*
5741          * TODO: throw #GP (and return 1) in various cases that the VM*
5742          * instructions require it - e.g., offset beyond segment limit,
5743          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5744          * address, and so on. Currently these are not checked.
5745          */
5746         return 0;
5747 }
5748
5749 /*
5750  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5751  * set the success or error code of an emulated VMX instruction, as specified
5752  * by Vol 2B, VMX Instruction Reference, "Conventions".
5753  */
5754 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5755 {
5756         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5757                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5758                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5759 }
5760
5761 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5762 {
5763         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5764                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5765                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5766                         | X86_EFLAGS_CF);
5767 }
5768
5769 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5770                                         u32 vm_instruction_error)
5771 {
5772         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5773                 /*
5774                  * failValid writes the error number to the current VMCS, which
5775                  * can't be done there isn't a current VMCS.
5776                  */
5777                 nested_vmx_failInvalid(vcpu);
5778                 return;
5779         }
5780         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5781                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5782                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5783                         | X86_EFLAGS_ZF);
5784         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5785         /*
5786          * We don't need to force a shadow sync because
5787          * VM_INSTRUCTION_ERROR is not shadowed
5788          */
5789 }
5790
5791 /* Emulate the VMCLEAR instruction */
5792 static int handle_vmclear(struct kvm_vcpu *vcpu)
5793 {
5794         struct vcpu_vmx *vmx = to_vmx(vcpu);
5795         gva_t gva;
5796         gpa_t vmptr;
5797         struct vmcs12 *vmcs12;
5798         struct page *page;
5799         struct x86_exception e;
5800
5801         if (!nested_vmx_check_permission(vcpu))
5802                 return 1;
5803
5804         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5805                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5806                 return 1;
5807
5808         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5809                                 sizeof(vmptr), &e)) {
5810                 kvm_inject_page_fault(vcpu, &e);
5811                 return 1;
5812         }
5813
5814         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5815                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5816                 skip_emulated_instruction(vcpu);
5817                 return 1;
5818         }
5819
5820         if (vmptr == vmx->nested.current_vmptr) {
5821                 nested_release_vmcs12(vmx);
5822                 vmx->nested.current_vmptr = -1ull;
5823                 vmx->nested.current_vmcs12 = NULL;
5824         }
5825
5826         page = nested_get_page(vcpu, vmptr);
5827         if (page == NULL) {
5828                 /*
5829                  * For accurate processor emulation, VMCLEAR beyond available
5830                  * physical memory should do nothing at all. However, it is
5831                  * possible that a nested vmx bug, not a guest hypervisor bug,
5832                  * resulted in this case, so let's shut down before doing any
5833                  * more damage:
5834                  */
5835                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5836                 return 1;
5837         }
5838         vmcs12 = kmap(page);
5839         vmcs12->launch_state = 0;
5840         kunmap(page);
5841         nested_release_page(page);
5842
5843         nested_free_vmcs02(vmx, vmptr);
5844
5845         skip_emulated_instruction(vcpu);
5846         nested_vmx_succeed(vcpu);
5847         return 1;
5848 }
5849
5850 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5851
5852 /* Emulate the VMLAUNCH instruction */
5853 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5854 {
5855         return nested_vmx_run(vcpu, true);
5856 }
5857
5858 /* Emulate the VMRESUME instruction */
5859 static int handle_vmresume(struct kvm_vcpu *vcpu)
5860 {
5861
5862         return nested_vmx_run(vcpu, false);
5863 }
5864
5865 enum vmcs_field_type {
5866         VMCS_FIELD_TYPE_U16 = 0,
5867         VMCS_FIELD_TYPE_U64 = 1,
5868         VMCS_FIELD_TYPE_U32 = 2,
5869         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5870 };
5871
5872 static inline int vmcs_field_type(unsigned long field)
5873 {
5874         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5875                 return VMCS_FIELD_TYPE_U32;
5876         return (field >> 13) & 0x3 ;
5877 }
5878
5879 static inline int vmcs_field_readonly(unsigned long field)
5880 {
5881         return (((field >> 10) & 0x3) == 1);
5882 }
5883
5884 /*
5885  * Read a vmcs12 field. Since these can have varying lengths and we return
5886  * one type, we chose the biggest type (u64) and zero-extend the return value
5887  * to that size. Note that the caller, handle_vmread, might need to use only
5888  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5889  * 64-bit fields are to be returned).
5890  */
5891 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5892                                         unsigned long field, u64 *ret)
5893 {
5894         short offset = vmcs_field_to_offset(field);
5895         char *p;
5896
5897         if (offset < 0)
5898                 return 0;
5899
5900         p = ((char *)(get_vmcs12(vcpu))) + offset;
5901
5902         switch (vmcs_field_type(field)) {
5903         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5904                 *ret = *((natural_width *)p);
5905                 return 1;
5906         case VMCS_FIELD_TYPE_U16:
5907                 *ret = *((u16 *)p);
5908                 return 1;
5909         case VMCS_FIELD_TYPE_U32:
5910                 *ret = *((u32 *)p);
5911                 return 1;
5912         case VMCS_FIELD_TYPE_U64:
5913                 *ret = *((u64 *)p);
5914                 return 1;
5915         default:
5916                 return 0; /* can never happen. */
5917         }
5918 }
5919
5920
5921 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5922                                     unsigned long field, u64 field_value){
5923         short offset = vmcs_field_to_offset(field);
5924         char *p = ((char *) get_vmcs12(vcpu)) + offset;
5925         if (offset < 0)
5926                 return false;
5927
5928         switch (vmcs_field_type(field)) {
5929         case VMCS_FIELD_TYPE_U16:
5930                 *(u16 *)p = field_value;
5931                 return true;
5932         case VMCS_FIELD_TYPE_U32:
5933                 *(u32 *)p = field_value;
5934                 return true;
5935         case VMCS_FIELD_TYPE_U64:
5936                 *(u64 *)p = field_value;
5937                 return true;
5938         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5939                 *(natural_width *)p = field_value;
5940                 return true;
5941         default:
5942                 return false; /* can never happen. */
5943         }
5944
5945 }
5946
5947 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5948 {
5949         int i;
5950         unsigned long field;
5951         u64 field_value;
5952         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5953         unsigned long *fields = (unsigned long *)shadow_read_write_fields;
5954         int num_fields = max_shadow_read_write_fields;
5955
5956         vmcs_load(shadow_vmcs);
5957
5958         for (i = 0; i < num_fields; i++) {
5959                 field = fields[i];
5960                 switch (vmcs_field_type(field)) {
5961                 case VMCS_FIELD_TYPE_U16:
5962                         field_value = vmcs_read16(field);
5963                         break;
5964                 case VMCS_FIELD_TYPE_U32:
5965                         field_value = vmcs_read32(field);
5966                         break;
5967                 case VMCS_FIELD_TYPE_U64:
5968                         field_value = vmcs_read64(field);
5969                         break;
5970                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5971                         field_value = vmcs_readl(field);
5972                         break;
5973                 }
5974                 vmcs12_write_any(&vmx->vcpu, field, field_value);
5975         }
5976
5977         vmcs_clear(shadow_vmcs);
5978         vmcs_load(vmx->loaded_vmcs->vmcs);
5979 }
5980
5981 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
5982 {
5983         unsigned long *fields[] = {
5984                 (unsigned long *)shadow_read_write_fields,
5985                 (unsigned long *)shadow_read_only_fields
5986         };
5987         int num_lists =  ARRAY_SIZE(fields);
5988         int max_fields[] = {
5989                 max_shadow_read_write_fields,
5990                 max_shadow_read_only_fields
5991         };
5992         int i, q;
5993         unsigned long field;
5994         u64 field_value = 0;
5995         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5996
5997         vmcs_load(shadow_vmcs);
5998
5999         for (q = 0; q < num_lists; q++) {
6000                 for (i = 0; i < max_fields[q]; i++) {
6001                         field = fields[q][i];
6002                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6003
6004                         switch (vmcs_field_type(field)) {
6005                         case VMCS_FIELD_TYPE_U16:
6006                                 vmcs_write16(field, (u16)field_value);
6007                                 break;
6008                         case VMCS_FIELD_TYPE_U32:
6009                                 vmcs_write32(field, (u32)field_value);
6010                                 break;
6011                         case VMCS_FIELD_TYPE_U64:
6012                                 vmcs_write64(field, (u64)field_value);
6013                                 break;
6014                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6015                                 vmcs_writel(field, (long)field_value);
6016                                 break;
6017                         }
6018                 }
6019         }
6020
6021         vmcs_clear(shadow_vmcs);
6022         vmcs_load(vmx->loaded_vmcs->vmcs);
6023 }
6024
6025 /*
6026  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6027  * used before) all generate the same failure when it is missing.
6028  */
6029 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6030 {
6031         struct vcpu_vmx *vmx = to_vmx(vcpu);
6032         if (vmx->nested.current_vmptr == -1ull) {
6033                 nested_vmx_failInvalid(vcpu);
6034                 skip_emulated_instruction(vcpu);
6035                 return 0;
6036         }
6037         return 1;
6038 }
6039
6040 static int handle_vmread(struct kvm_vcpu *vcpu)
6041 {
6042         unsigned long field;
6043         u64 field_value;
6044         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6045         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6046         gva_t gva = 0;
6047
6048         if (!nested_vmx_check_permission(vcpu) ||
6049             !nested_vmx_check_vmcs12(vcpu))
6050                 return 1;
6051
6052         /* Decode instruction info and find the field to read */
6053         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6054         /* Read the field, zero-extended to a u64 field_value */
6055         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6056                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6057                 skip_emulated_instruction(vcpu);
6058                 return 1;
6059         }
6060         /*
6061          * Now copy part of this value to register or memory, as requested.
6062          * Note that the number of bits actually copied is 32 or 64 depending
6063          * on the guest's mode (32 or 64 bit), not on the given field's length.
6064          */
6065         if (vmx_instruction_info & (1u << 10)) {
6066                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6067                         field_value);
6068         } else {
6069                 if (get_vmx_mem_address(vcpu, exit_qualification,
6070                                 vmx_instruction_info, &gva))
6071                         return 1;
6072                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6073                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6074                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6075         }
6076
6077         nested_vmx_succeed(vcpu);
6078         skip_emulated_instruction(vcpu);
6079         return 1;
6080 }
6081
6082
6083 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6084 {
6085         unsigned long field;
6086         gva_t gva;
6087         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6088         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6089         /* The value to write might be 32 or 64 bits, depending on L1's long
6090          * mode, and eventually we need to write that into a field of several
6091          * possible lengths. The code below first zero-extends the value to 64
6092          * bit (field_value), and then copies only the approriate number of
6093          * bits into the vmcs12 field.
6094          */
6095         u64 field_value = 0;
6096         struct x86_exception e;
6097
6098         if (!nested_vmx_check_permission(vcpu) ||
6099             !nested_vmx_check_vmcs12(vcpu))
6100                 return 1;
6101
6102         if (vmx_instruction_info & (1u << 10))
6103                 field_value = kvm_register_read(vcpu,
6104                         (((vmx_instruction_info) >> 3) & 0xf));
6105         else {
6106                 if (get_vmx_mem_address(vcpu, exit_qualification,
6107                                 vmx_instruction_info, &gva))
6108                         return 1;
6109                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6110                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6111                         kvm_inject_page_fault(vcpu, &e);
6112                         return 1;
6113                 }
6114         }
6115
6116
6117         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6118         if (vmcs_field_readonly(field)) {
6119                 nested_vmx_failValid(vcpu,
6120                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6121                 skip_emulated_instruction(vcpu);
6122                 return 1;
6123         }
6124
6125         if (!vmcs12_write_any(vcpu, field, field_value)) {
6126                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6127                 skip_emulated_instruction(vcpu);
6128                 return 1;
6129         }
6130
6131         nested_vmx_succeed(vcpu);
6132         skip_emulated_instruction(vcpu);
6133         return 1;
6134 }
6135
6136 /* Emulate the VMPTRLD instruction */
6137 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6138 {
6139         struct vcpu_vmx *vmx = to_vmx(vcpu);
6140         gva_t gva;
6141         gpa_t vmptr;
6142         struct x86_exception e;
6143         u32 exec_control;
6144
6145         if (!nested_vmx_check_permission(vcpu))
6146                 return 1;
6147
6148         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6149                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6150                 return 1;
6151
6152         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6153                                 sizeof(vmptr), &e)) {
6154                 kvm_inject_page_fault(vcpu, &e);
6155                 return 1;
6156         }
6157
6158         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6159                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6160                 skip_emulated_instruction(vcpu);
6161                 return 1;
6162         }
6163
6164         if (vmx->nested.current_vmptr != vmptr) {
6165                 struct vmcs12 *new_vmcs12;
6166                 struct page *page;
6167                 page = nested_get_page(vcpu, vmptr);
6168                 if (page == NULL) {
6169                         nested_vmx_failInvalid(vcpu);
6170                         skip_emulated_instruction(vcpu);
6171                         return 1;
6172                 }
6173                 new_vmcs12 = kmap(page);
6174                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6175                         kunmap(page);
6176                         nested_release_page_clean(page);
6177                         nested_vmx_failValid(vcpu,
6178                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6179                         skip_emulated_instruction(vcpu);
6180                         return 1;
6181                 }
6182                 if (vmx->nested.current_vmptr != -1ull)
6183                         nested_release_vmcs12(vmx);
6184
6185                 vmx->nested.current_vmptr = vmptr;
6186                 vmx->nested.current_vmcs12 = new_vmcs12;
6187                 vmx->nested.current_vmcs12_page = page;
6188                 if (enable_shadow_vmcs) {
6189                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6190                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6191                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6192                         vmcs_write64(VMCS_LINK_POINTER,
6193                                      __pa(vmx->nested.current_shadow_vmcs));
6194                         vmx->nested.sync_shadow_vmcs = true;
6195                 }
6196         }
6197
6198         nested_vmx_succeed(vcpu);
6199         skip_emulated_instruction(vcpu);
6200         return 1;
6201 }
6202
6203 /* Emulate the VMPTRST instruction */
6204 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6205 {
6206         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6207         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6208         gva_t vmcs_gva;
6209         struct x86_exception e;
6210
6211         if (!nested_vmx_check_permission(vcpu))
6212                 return 1;
6213
6214         if (get_vmx_mem_address(vcpu, exit_qualification,
6215                         vmx_instruction_info, &vmcs_gva))
6216                 return 1;
6217         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6218         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6219                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6220                                  sizeof(u64), &e)) {
6221                 kvm_inject_page_fault(vcpu, &e);
6222                 return 1;
6223         }
6224         nested_vmx_succeed(vcpu);
6225         skip_emulated_instruction(vcpu);
6226         return 1;
6227 }
6228
6229 /*
6230  * The exit handlers return 1 if the exit was handled fully and guest execution
6231  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6232  * to be done to userspace and return 0.
6233  */
6234 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6235         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6236         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6237         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6238         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6239         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6240         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6241         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6242         [EXIT_REASON_CPUID]                   = handle_cpuid,
6243         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6244         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6245         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6246         [EXIT_REASON_HLT]                     = handle_halt,
6247         [EXIT_REASON_INVD]                    = handle_invd,
6248         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6249         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6250         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6251         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6252         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6253         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6254         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6255         [EXIT_REASON_VMREAD]                  = handle_vmread,
6256         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6257         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6258         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6259         [EXIT_REASON_VMON]                    = handle_vmon,
6260         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6261         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6262         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6263         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6264         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6265         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6266         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6267         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6268         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6269         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6270         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6271         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6272         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6273 };
6274
6275 static const int kvm_vmx_max_exit_handlers =
6276         ARRAY_SIZE(kvm_vmx_exit_handlers);
6277
6278 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6279                                        struct vmcs12 *vmcs12)
6280 {
6281         unsigned long exit_qualification;
6282         gpa_t bitmap, last_bitmap;
6283         unsigned int port;
6284         int size;
6285         u8 b;
6286
6287         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6288                 return 1;
6289
6290         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6291                 return 0;
6292
6293         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6294
6295         port = exit_qualification >> 16;
6296         size = (exit_qualification & 7) + 1;
6297
6298         last_bitmap = (gpa_t)-1;
6299         b = -1;
6300
6301         while (size > 0) {
6302                 if (port < 0x8000)
6303                         bitmap = vmcs12->io_bitmap_a;
6304                 else if (port < 0x10000)
6305                         bitmap = vmcs12->io_bitmap_b;
6306                 else
6307                         return 1;
6308                 bitmap += (port & 0x7fff) / 8;
6309
6310                 if (last_bitmap != bitmap)
6311                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6312                                 return 1;
6313                 if (b & (1 << (port & 7)))
6314                         return 1;
6315
6316                 port++;
6317                 size--;
6318                 last_bitmap = bitmap;
6319         }
6320
6321         return 0;
6322 }
6323
6324 /*
6325  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6326  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6327  * disinterest in the current event (read or write a specific MSR) by using an
6328  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6329  */
6330 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6331         struct vmcs12 *vmcs12, u32 exit_reason)
6332 {
6333         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6334         gpa_t bitmap;
6335
6336         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6337                 return 1;
6338
6339         /*
6340          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6341          * for the four combinations of read/write and low/high MSR numbers.
6342          * First we need to figure out which of the four to use:
6343          */
6344         bitmap = vmcs12->msr_bitmap;
6345         if (exit_reason == EXIT_REASON_MSR_WRITE)
6346                 bitmap += 2048;
6347         if (msr_index >= 0xc0000000) {
6348                 msr_index -= 0xc0000000;
6349                 bitmap += 1024;
6350         }
6351
6352         /* Then read the msr_index'th bit from this bitmap: */
6353         if (msr_index < 1024*8) {
6354                 unsigned char b;
6355                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6356                         return 1;
6357                 return 1 & (b >> (msr_index & 7));
6358         } else
6359                 return 1; /* let L1 handle the wrong parameter */
6360 }
6361
6362 /*
6363  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6364  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6365  * intercept (via guest_host_mask etc.) the current event.
6366  */
6367 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6368         struct vmcs12 *vmcs12)
6369 {
6370         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6371         int cr = exit_qualification & 15;
6372         int reg = (exit_qualification >> 8) & 15;
6373         unsigned long val = kvm_register_read(vcpu, reg);
6374
6375         switch ((exit_qualification >> 4) & 3) {
6376         case 0: /* mov to cr */
6377                 switch (cr) {
6378                 case 0:
6379                         if (vmcs12->cr0_guest_host_mask &
6380                             (val ^ vmcs12->cr0_read_shadow))
6381                                 return 1;
6382                         break;
6383                 case 3:
6384                         if ((vmcs12->cr3_target_count >= 1 &&
6385                                         vmcs12->cr3_target_value0 == val) ||
6386                                 (vmcs12->cr3_target_count >= 2 &&
6387                                         vmcs12->cr3_target_value1 == val) ||
6388                                 (vmcs12->cr3_target_count >= 3 &&
6389                                         vmcs12->cr3_target_value2 == val) ||
6390                                 (vmcs12->cr3_target_count >= 4 &&
6391                                         vmcs12->cr3_target_value3 == val))
6392                                 return 0;
6393                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6394                                 return 1;
6395                         break;
6396                 case 4:
6397                         if (vmcs12->cr4_guest_host_mask &
6398                             (vmcs12->cr4_read_shadow ^ val))
6399                                 return 1;
6400                         break;
6401                 case 8:
6402                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6403                                 return 1;
6404                         break;
6405                 }
6406                 break;
6407         case 2: /* clts */
6408                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6409                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6410                         return 1;
6411                 break;
6412         case 1: /* mov from cr */
6413                 switch (cr) {
6414                 case 3:
6415                         if (vmcs12->cpu_based_vm_exec_control &
6416                             CPU_BASED_CR3_STORE_EXITING)
6417                                 return 1;
6418                         break;
6419                 case 8:
6420                         if (vmcs12->cpu_based_vm_exec_control &
6421                             CPU_BASED_CR8_STORE_EXITING)
6422                                 return 1;
6423                         break;
6424                 }
6425                 break;
6426         case 3: /* lmsw */
6427                 /*
6428                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6429                  * cr0. Other attempted changes are ignored, with no exit.
6430                  */
6431                 if (vmcs12->cr0_guest_host_mask & 0xe &
6432                     (val ^ vmcs12->cr0_read_shadow))
6433                         return 1;
6434                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6435                     !(vmcs12->cr0_read_shadow & 0x1) &&
6436                     (val & 0x1))
6437                         return 1;
6438                 break;
6439         }
6440         return 0;
6441 }
6442
6443 /*
6444  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6445  * should handle it ourselves in L0 (and then continue L2). Only call this
6446  * when in is_guest_mode (L2).
6447  */
6448 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6449 {
6450         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6451         struct vcpu_vmx *vmx = to_vmx(vcpu);
6452         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6453         u32 exit_reason = vmx->exit_reason;
6454
6455         if (vmx->nested.nested_run_pending)
6456                 return 0;
6457
6458         if (unlikely(vmx->fail)) {
6459                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6460                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6461                 return 1;
6462         }
6463
6464         switch (exit_reason) {
6465         case EXIT_REASON_EXCEPTION_NMI:
6466                 if (!is_exception(intr_info))
6467                         return 0;
6468                 else if (is_page_fault(intr_info))
6469                         return enable_ept;
6470                 return vmcs12->exception_bitmap &
6471                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6472         case EXIT_REASON_EXTERNAL_INTERRUPT:
6473                 return 0;
6474         case EXIT_REASON_TRIPLE_FAULT:
6475                 return 1;
6476         case EXIT_REASON_PENDING_INTERRUPT:
6477                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6478         case EXIT_REASON_NMI_WINDOW:
6479                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6480         case EXIT_REASON_TASK_SWITCH:
6481                 return 1;
6482         case EXIT_REASON_CPUID:
6483                 return 1;
6484         case EXIT_REASON_HLT:
6485                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6486         case EXIT_REASON_INVD:
6487                 return 1;
6488         case EXIT_REASON_INVLPG:
6489                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6490         case EXIT_REASON_RDPMC:
6491                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6492         case EXIT_REASON_RDTSC:
6493                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6494         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6495         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6496         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6497         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6498         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6499                 /*
6500                  * VMX instructions trap unconditionally. This allows L1 to
6501                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6502                  */
6503                 return 1;
6504         case EXIT_REASON_CR_ACCESS:
6505                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6506         case EXIT_REASON_DR_ACCESS:
6507                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6508         case EXIT_REASON_IO_INSTRUCTION:
6509                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6510         case EXIT_REASON_MSR_READ:
6511         case EXIT_REASON_MSR_WRITE:
6512                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6513         case EXIT_REASON_INVALID_STATE:
6514                 return 1;
6515         case EXIT_REASON_MWAIT_INSTRUCTION:
6516                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6517         case EXIT_REASON_MONITOR_INSTRUCTION:
6518                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6519         case EXIT_REASON_PAUSE_INSTRUCTION:
6520                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6521                         nested_cpu_has2(vmcs12,
6522                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6523         case EXIT_REASON_MCE_DURING_VMENTRY:
6524                 return 0;
6525         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6526                 return 1;
6527         case EXIT_REASON_APIC_ACCESS:
6528                 return nested_cpu_has2(vmcs12,
6529                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6530         case EXIT_REASON_EPT_VIOLATION:
6531         case EXIT_REASON_EPT_MISCONFIG:
6532                 return 0;
6533         case EXIT_REASON_PREEMPTION_TIMER:
6534                 return vmcs12->pin_based_vm_exec_control &
6535                         PIN_BASED_VMX_PREEMPTION_TIMER;
6536         case EXIT_REASON_WBINVD:
6537                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6538         case EXIT_REASON_XSETBV:
6539                 return 1;
6540         default:
6541                 return 1;
6542         }
6543 }
6544
6545 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6546 {
6547         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6548         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6549 }
6550
6551 /*
6552  * The guest has exited.  See if we can fix it or if we need userspace
6553  * assistance.
6554  */
6555 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6556 {
6557         struct vcpu_vmx *vmx = to_vmx(vcpu);
6558         u32 exit_reason = vmx->exit_reason;
6559         u32 vectoring_info = vmx->idt_vectoring_info;
6560
6561         /* If guest state is invalid, start emulating */
6562         if (vmx->emulation_required)
6563                 return handle_invalid_guest_state(vcpu);
6564
6565         /*
6566          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6567          * we did not inject a still-pending event to L1 now because of
6568          * nested_run_pending, we need to re-enable this bit.
6569          */
6570         if (vmx->nested.nested_run_pending)
6571                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6572
6573         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6574             exit_reason == EXIT_REASON_VMRESUME))
6575                 vmx->nested.nested_run_pending = 1;
6576         else
6577                 vmx->nested.nested_run_pending = 0;
6578
6579         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6580                 nested_vmx_vmexit(vcpu);
6581                 return 1;
6582         }
6583
6584         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6585                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6586                 vcpu->run->fail_entry.hardware_entry_failure_reason
6587                         = exit_reason;
6588                 return 0;
6589         }
6590
6591         if (unlikely(vmx->fail)) {
6592                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6593                 vcpu->run->fail_entry.hardware_entry_failure_reason
6594                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6595                 return 0;
6596         }
6597
6598         /*
6599          * Note:
6600          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6601          * delivery event since it indicates guest is accessing MMIO.
6602          * The vm-exit can be triggered again after return to guest that
6603          * will cause infinite loop.
6604          */
6605         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6606                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6607                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6608                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6609                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6610                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6611                 vcpu->run->internal.ndata = 2;
6612                 vcpu->run->internal.data[0] = vectoring_info;
6613                 vcpu->run->internal.data[1] = exit_reason;
6614                 return 0;
6615         }
6616
6617         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6618             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6619                                         get_vmcs12(vcpu), vcpu)))) {
6620                 if (vmx_interrupt_allowed(vcpu)) {
6621                         vmx->soft_vnmi_blocked = 0;
6622                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6623                            vcpu->arch.nmi_pending) {
6624                         /*
6625                          * This CPU don't support us in finding the end of an
6626                          * NMI-blocked window if the guest runs with IRQs
6627                          * disabled. So we pull the trigger after 1 s of
6628                          * futile waiting, but inform the user about this.
6629                          */
6630                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6631                                "state on VCPU %d after 1 s timeout\n",
6632                                __func__, vcpu->vcpu_id);
6633                         vmx->soft_vnmi_blocked = 0;
6634                 }
6635         }
6636
6637         if (exit_reason < kvm_vmx_max_exit_handlers
6638             && kvm_vmx_exit_handlers[exit_reason])
6639                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6640         else {
6641                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6642                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6643         }
6644         return 0;
6645 }
6646
6647 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6648 {
6649         if (irr == -1 || tpr < irr) {
6650                 vmcs_write32(TPR_THRESHOLD, 0);
6651                 return;
6652         }
6653
6654         vmcs_write32(TPR_THRESHOLD, irr);
6655 }
6656
6657 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6658 {
6659         u32 sec_exec_control;
6660
6661         /*
6662          * There is not point to enable virtualize x2apic without enable
6663          * apicv
6664          */
6665         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6666                                 !vmx_vm_has_apicv(vcpu->kvm))
6667                 return;
6668
6669         if (!vm_need_tpr_shadow(vcpu->kvm))
6670                 return;
6671
6672         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6673
6674         if (set) {
6675                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6676                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6677         } else {
6678                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6679                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6680         }
6681         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6682
6683         vmx_set_msr_bitmap(vcpu);
6684 }
6685
6686 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6687 {
6688         u16 status;
6689         u8 old;
6690
6691         if (!vmx_vm_has_apicv(kvm))
6692                 return;
6693
6694         if (isr == -1)
6695                 isr = 0;
6696
6697         status = vmcs_read16(GUEST_INTR_STATUS);
6698         old = status >> 8;
6699         if (isr != old) {
6700                 status &= 0xff;
6701                 status |= isr << 8;
6702                 vmcs_write16(GUEST_INTR_STATUS, status);
6703         }
6704 }
6705
6706 static void vmx_set_rvi(int vector)
6707 {
6708         u16 status;
6709         u8 old;
6710
6711         status = vmcs_read16(GUEST_INTR_STATUS);
6712         old = (u8)status & 0xff;
6713         if ((u8)vector != old) {
6714                 status &= ~0xff;
6715                 status |= (u8)vector;
6716                 vmcs_write16(GUEST_INTR_STATUS, status);
6717         }
6718 }
6719
6720 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6721 {
6722         if (max_irr == -1)
6723                 return;
6724
6725         vmx_set_rvi(max_irr);
6726 }
6727
6728 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6729 {
6730         if (!vmx_vm_has_apicv(vcpu->kvm))
6731                 return;
6732
6733         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6734         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6735         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6736         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6737 }
6738
6739 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6740 {
6741         u32 exit_intr_info;
6742
6743         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6744               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6745                 return;
6746
6747         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6748         exit_intr_info = vmx->exit_intr_info;
6749
6750         /* Handle machine checks before interrupts are enabled */
6751         if (is_machine_check(exit_intr_info))
6752                 kvm_machine_check();
6753
6754         /* We need to handle NMIs before interrupts are enabled */
6755         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6756             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6757                 kvm_before_handle_nmi(&vmx->vcpu);
6758                 asm("int $2");
6759                 kvm_after_handle_nmi(&vmx->vcpu);
6760         }
6761 }
6762
6763 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6764 {
6765         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6766
6767         /*
6768          * If external interrupt exists, IF bit is set in rflags/eflags on the
6769          * interrupt stack frame, and interrupt will be enabled on a return
6770          * from interrupt handler.
6771          */
6772         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6773                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6774                 unsigned int vector;
6775                 unsigned long entry;
6776                 gate_desc *desc;
6777                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6778 #ifdef CONFIG_X86_64
6779                 unsigned long tmp;
6780 #endif
6781
6782                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6783                 desc = (gate_desc *)vmx->host_idt_base + vector;
6784                 entry = gate_offset(*desc);
6785                 asm volatile(
6786 #ifdef CONFIG_X86_64
6787                         "mov %%" _ASM_SP ", %[sp]\n\t"
6788                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6789                         "push $%c[ss]\n\t"
6790                         "push %[sp]\n\t"
6791 #endif
6792                         "pushf\n\t"
6793                         "orl $0x200, (%%" _ASM_SP ")\n\t"
6794                         __ASM_SIZE(push) " $%c[cs]\n\t"
6795                         "call *%[entry]\n\t"
6796                         :
6797 #ifdef CONFIG_X86_64
6798                         [sp]"=&r"(tmp)
6799 #endif
6800                         :
6801                         [entry]"r"(entry),
6802                         [ss]"i"(__KERNEL_DS),
6803                         [cs]"i"(__KERNEL_CS)
6804                         );
6805         } else
6806                 local_irq_enable();
6807 }
6808
6809 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6810 {
6811         u32 exit_intr_info;
6812         bool unblock_nmi;
6813         u8 vector;
6814         bool idtv_info_valid;
6815
6816         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6817
6818         if (cpu_has_virtual_nmis()) {
6819                 if (vmx->nmi_known_unmasked)
6820                         return;
6821                 /*
6822                  * Can't use vmx->exit_intr_info since we're not sure what
6823                  * the exit reason is.
6824                  */
6825                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6826                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6827                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6828                 /*
6829                  * SDM 3: 27.7.1.2 (September 2008)
6830                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6831                  * a guest IRET fault.
6832                  * SDM 3: 23.2.2 (September 2008)
6833                  * Bit 12 is undefined in any of the following cases:
6834                  *  If the VM exit sets the valid bit in the IDT-vectoring
6835                  *   information field.
6836                  *  If the VM exit is due to a double fault.
6837                  */
6838                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6839                     vector != DF_VECTOR && !idtv_info_valid)
6840                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6841                                       GUEST_INTR_STATE_NMI);
6842                 else
6843                         vmx->nmi_known_unmasked =
6844                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6845                                   & GUEST_INTR_STATE_NMI);
6846         } else if (unlikely(vmx->soft_vnmi_blocked))
6847                 vmx->vnmi_blocked_time +=
6848                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6849 }
6850
6851 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6852                                       u32 idt_vectoring_info,
6853                                       int instr_len_field,
6854                                       int error_code_field)
6855 {
6856         u8 vector;
6857         int type;
6858         bool idtv_info_valid;
6859
6860         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6861
6862         vcpu->arch.nmi_injected = false;
6863         kvm_clear_exception_queue(vcpu);
6864         kvm_clear_interrupt_queue(vcpu);
6865
6866         if (!idtv_info_valid)
6867                 return;
6868
6869         kvm_make_request(KVM_REQ_EVENT, vcpu);
6870
6871         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6872         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6873
6874         switch (type) {
6875         case INTR_TYPE_NMI_INTR:
6876                 vcpu->arch.nmi_injected = true;
6877                 /*
6878                  * SDM 3: 27.7.1.2 (September 2008)
6879                  * Clear bit "block by NMI" before VM entry if a NMI
6880                  * delivery faulted.
6881                  */
6882                 vmx_set_nmi_mask(vcpu, false);
6883                 break;
6884         case INTR_TYPE_SOFT_EXCEPTION:
6885                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6886                 /* fall through */
6887         case INTR_TYPE_HARD_EXCEPTION:
6888                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6889                         u32 err = vmcs_read32(error_code_field);
6890                         kvm_queue_exception_e(vcpu, vector, err);
6891                 } else
6892                         kvm_queue_exception(vcpu, vector);
6893                 break;
6894         case INTR_TYPE_SOFT_INTR:
6895                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6896                 /* fall through */
6897         case INTR_TYPE_EXT_INTR:
6898                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6899                 break;
6900         default:
6901                 break;
6902         }
6903 }
6904
6905 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6906 {
6907         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6908                                   VM_EXIT_INSTRUCTION_LEN,
6909                                   IDT_VECTORING_ERROR_CODE);
6910 }
6911
6912 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6913 {
6914         __vmx_complete_interrupts(vcpu,
6915                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6916                                   VM_ENTRY_INSTRUCTION_LEN,
6917                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6918
6919         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6920 }
6921
6922 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6923 {
6924         int i, nr_msrs;
6925         struct perf_guest_switch_msr *msrs;
6926
6927         msrs = perf_guest_get_msrs(&nr_msrs);
6928
6929         if (!msrs)
6930                 return;
6931
6932         for (i = 0; i < nr_msrs; i++)
6933                 if (msrs[i].host == msrs[i].guest)
6934                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6935                 else
6936                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6937                                         msrs[i].host);
6938 }
6939
6940 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6941 {
6942         struct vcpu_vmx *vmx = to_vmx(vcpu);
6943         unsigned long debugctlmsr;
6944
6945         /* Record the guest's net vcpu time for enforced NMI injections. */
6946         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6947                 vmx->entry_time = ktime_get();
6948
6949         /* Don't enter VMX if guest state is invalid, let the exit handler
6950            start emulation until we arrive back to a valid state */
6951         if (vmx->emulation_required)
6952                 return;
6953
6954         if (vmx->nested.sync_shadow_vmcs) {
6955                 copy_vmcs12_to_shadow(vmx);
6956                 vmx->nested.sync_shadow_vmcs = false;
6957         }
6958
6959         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6960                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6961         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6962                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6963
6964         /* When single-stepping over STI and MOV SS, we must clear the
6965          * corresponding interruptibility bits in the guest state. Otherwise
6966          * vmentry fails as it then expects bit 14 (BS) in pending debug
6967          * exceptions being set, but that's not correct for the guest debugging
6968          * case. */
6969         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6970                 vmx_set_interrupt_shadow(vcpu, 0);
6971
6972         atomic_switch_perf_msrs(vmx);
6973         debugctlmsr = get_debugctlmsr();
6974
6975         vmx->__launched = vmx->loaded_vmcs->launched;
6976         asm(
6977                 /* Store host registers */
6978                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6979                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6980                 "push %%" _ASM_CX " \n\t"
6981                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6982                 "je 1f \n\t"
6983                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6984                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6985                 "1: \n\t"
6986                 /* Reload cr2 if changed */
6987                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6988                 "mov %%cr2, %%" _ASM_DX " \n\t"
6989                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6990                 "je 2f \n\t"
6991                 "mov %%" _ASM_AX", %%cr2 \n\t"
6992                 "2: \n\t"
6993                 /* Check if vmlaunch of vmresume is needed */
6994                 "cmpl $0, %c[launched](%0) \n\t"
6995                 /* Load guest registers.  Don't clobber flags. */
6996                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6997                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6998                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6999                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7000                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7001                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7002 #ifdef CONFIG_X86_64
7003                 "mov %c[r8](%0),  %%r8  \n\t"
7004                 "mov %c[r9](%0),  %%r9  \n\t"
7005                 "mov %c[r10](%0), %%r10 \n\t"
7006                 "mov %c[r11](%0), %%r11 \n\t"
7007                 "mov %c[r12](%0), %%r12 \n\t"
7008                 "mov %c[r13](%0), %%r13 \n\t"
7009                 "mov %c[r14](%0), %%r14 \n\t"
7010                 "mov %c[r15](%0), %%r15 \n\t"
7011 #endif
7012                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7013
7014                 /* Enter guest mode */
7015                 "jne 1f \n\t"
7016                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7017                 "jmp 2f \n\t"
7018                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7019                 "2: "
7020                 /* Save guest registers, load host registers, keep flags */
7021                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7022                 "pop %0 \n\t"
7023                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7024                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7025                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7026                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7027                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7028                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7029                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7030 #ifdef CONFIG_X86_64
7031                 "mov %%r8,  %c[r8](%0) \n\t"
7032                 "mov %%r9,  %c[r9](%0) \n\t"
7033                 "mov %%r10, %c[r10](%0) \n\t"
7034                 "mov %%r11, %c[r11](%0) \n\t"
7035                 "mov %%r12, %c[r12](%0) \n\t"
7036                 "mov %%r13, %c[r13](%0) \n\t"
7037                 "mov %%r14, %c[r14](%0) \n\t"
7038                 "mov %%r15, %c[r15](%0) \n\t"
7039 #endif
7040                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7041                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7042
7043                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7044                 "setbe %c[fail](%0) \n\t"
7045                 ".pushsection .rodata \n\t"
7046                 ".global vmx_return \n\t"
7047                 "vmx_return: " _ASM_PTR " 2b \n\t"
7048                 ".popsection"
7049               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7050                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7051                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7052                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7053                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7054                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7055                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7056                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7057                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7058                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7059                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7060 #ifdef CONFIG_X86_64
7061                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7062                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7063                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7064                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7065                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7066                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7067                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7068                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7069 #endif
7070                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7071                 [wordsize]"i"(sizeof(ulong))
7072               : "cc", "memory"
7073 #ifdef CONFIG_X86_64
7074                 , "rax", "rbx", "rdi", "rsi"
7075                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7076 #else
7077                 , "eax", "ebx", "edi", "esi"
7078 #endif
7079               );
7080
7081         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7082         if (debugctlmsr)
7083                 update_debugctlmsr(debugctlmsr);
7084
7085 #ifndef CONFIG_X86_64
7086         /*
7087          * The sysexit path does not restore ds/es, so we must set them to
7088          * a reasonable value ourselves.
7089          *
7090          * We can't defer this to vmx_load_host_state() since that function
7091          * may be executed in interrupt context, which saves and restore segments
7092          * around it, nullifying its effect.
7093          */
7094         loadsegment(ds, __USER_DS);
7095         loadsegment(es, __USER_DS);
7096 #endif
7097
7098         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7099                                   | (1 << VCPU_EXREG_RFLAGS)
7100                                   | (1 << VCPU_EXREG_CPL)
7101                                   | (1 << VCPU_EXREG_PDPTR)
7102                                   | (1 << VCPU_EXREG_SEGMENTS)
7103                                   | (1 << VCPU_EXREG_CR3));
7104         vcpu->arch.regs_dirty = 0;
7105
7106         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7107
7108         vmx->loaded_vmcs->launched = 1;
7109
7110         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7111         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7112
7113         vmx_complete_atomic_exit(vmx);
7114         vmx_recover_nmi_blocking(vmx);
7115         vmx_complete_interrupts(vmx);
7116 }
7117
7118 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7119 {
7120         struct vcpu_vmx *vmx = to_vmx(vcpu);
7121
7122         free_vpid(vmx);
7123         free_nested(vmx);
7124         free_loaded_vmcs(vmx->loaded_vmcs);
7125         kfree(vmx->guest_msrs);
7126         kvm_vcpu_uninit(vcpu);
7127         kmem_cache_free(kvm_vcpu_cache, vmx);
7128 }
7129
7130 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7131 {
7132         int err;
7133         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7134         int cpu;
7135
7136         if (!vmx)
7137                 return ERR_PTR(-ENOMEM);
7138
7139         allocate_vpid(vmx);
7140
7141         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7142         if (err)
7143                 goto free_vcpu;
7144
7145         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7146         err = -ENOMEM;
7147         if (!vmx->guest_msrs) {
7148                 goto uninit_vcpu;
7149         }
7150
7151         vmx->loaded_vmcs = &vmx->vmcs01;
7152         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7153         if (!vmx->loaded_vmcs->vmcs)
7154                 goto free_msrs;
7155         if (!vmm_exclusive)
7156                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7157         loaded_vmcs_init(vmx->loaded_vmcs);
7158         if (!vmm_exclusive)
7159                 kvm_cpu_vmxoff();
7160
7161         cpu = get_cpu();
7162         vmx_vcpu_load(&vmx->vcpu, cpu);
7163         vmx->vcpu.cpu = cpu;
7164         err = vmx_vcpu_setup(vmx);
7165         vmx_vcpu_put(&vmx->vcpu);
7166         put_cpu();
7167         if (err)
7168                 goto free_vmcs;
7169         if (vm_need_virtualize_apic_accesses(kvm)) {
7170                 err = alloc_apic_access_page(kvm);
7171                 if (err)
7172                         goto free_vmcs;
7173         }
7174
7175         if (enable_ept) {
7176                 if (!kvm->arch.ept_identity_map_addr)
7177                         kvm->arch.ept_identity_map_addr =
7178                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7179                 err = -ENOMEM;
7180                 if (alloc_identity_pagetable(kvm) != 0)
7181                         goto free_vmcs;
7182                 if (!init_rmode_identity_map(kvm))
7183                         goto free_vmcs;
7184         }
7185
7186         vmx->nested.current_vmptr = -1ull;
7187         vmx->nested.current_vmcs12 = NULL;
7188
7189         return &vmx->vcpu;
7190
7191 free_vmcs:
7192         free_loaded_vmcs(vmx->loaded_vmcs);
7193 free_msrs:
7194         kfree(vmx->guest_msrs);
7195 uninit_vcpu:
7196         kvm_vcpu_uninit(&vmx->vcpu);
7197 free_vcpu:
7198         free_vpid(vmx);
7199         kmem_cache_free(kvm_vcpu_cache, vmx);
7200         return ERR_PTR(err);
7201 }
7202
7203 static void __init vmx_check_processor_compat(void *rtn)
7204 {
7205         struct vmcs_config vmcs_conf;
7206
7207         *(int *)rtn = 0;
7208         if (setup_vmcs_config(&vmcs_conf) < 0)
7209                 *(int *)rtn = -EIO;
7210         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7211                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7212                                 smp_processor_id());
7213                 *(int *)rtn = -EIO;
7214         }
7215 }
7216
7217 static int get_ept_level(void)
7218 {
7219         return VMX_EPT_DEFAULT_GAW + 1;
7220 }
7221
7222 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7223 {
7224         u64 ret;
7225
7226         /* For VT-d and EPT combination
7227          * 1. MMIO: always map as UC
7228          * 2. EPT with VT-d:
7229          *   a. VT-d without snooping control feature: can't guarantee the
7230          *      result, try to trust guest.
7231          *   b. VT-d with snooping control feature: snooping control feature of
7232          *      VT-d engine can guarantee the cache correctness. Just set it
7233          *      to WB to keep consistent with host. So the same as item 3.
7234          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7235          *    consistent with host MTRR
7236          */
7237         if (is_mmio)
7238                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7239         else if (vcpu->kvm->arch.iommu_domain &&
7240                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7241                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7242                       VMX_EPT_MT_EPTE_SHIFT;
7243         else
7244                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7245                         | VMX_EPT_IPAT_BIT;
7246
7247         return ret;
7248 }
7249
7250 static int vmx_get_lpage_level(void)
7251 {
7252         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7253                 return PT_DIRECTORY_LEVEL;
7254         else
7255                 /* For shadow and EPT supported 1GB page */
7256                 return PT_PDPE_LEVEL;
7257 }
7258
7259 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7260 {
7261         struct kvm_cpuid_entry2 *best;
7262         struct vcpu_vmx *vmx = to_vmx(vcpu);
7263         u32 exec_control;
7264
7265         vmx->rdtscp_enabled = false;
7266         if (vmx_rdtscp_supported()) {
7267                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7268                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7269                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7270                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7271                                 vmx->rdtscp_enabled = true;
7272                         else {
7273                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7274                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7275                                                 exec_control);
7276                         }
7277                 }
7278         }
7279
7280         /* Exposing INVPCID only when PCID is exposed */
7281         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7282         if (vmx_invpcid_supported() &&
7283             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7284             guest_cpuid_has_pcid(vcpu)) {
7285                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7286                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7287                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7288                              exec_control);
7289         } else {
7290                 if (cpu_has_secondary_exec_ctrls()) {
7291                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7292                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7293                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7294                                      exec_control);
7295                 }
7296                 if (best)
7297                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7298         }
7299 }
7300
7301 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7302 {
7303         if (func == 1 && nested)
7304                 entry->ecx |= bit(X86_FEATURE_VMX);
7305 }
7306
7307 /*
7308  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7309  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7310  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7311  * guest in a way that will both be appropriate to L1's requests, and our
7312  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7313  * function also has additional necessary side-effects, like setting various
7314  * vcpu->arch fields.
7315  */
7316 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7317 {
7318         struct vcpu_vmx *vmx = to_vmx(vcpu);
7319         u32 exec_control;
7320
7321         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7322         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7323         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7324         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7325         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7326         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7327         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7328         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7329         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7330         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7331         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7332         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7333         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7334         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7335         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7336         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7337         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7338         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7339         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7340         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7341         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7342         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7343         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7344         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7345         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7346         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7347         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7348         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7349         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7350         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7351         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7352         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7353         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7354         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7355         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7356         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7357
7358         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7359         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7360                 vmcs12->vm_entry_intr_info_field);
7361         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7362                 vmcs12->vm_entry_exception_error_code);
7363         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7364                 vmcs12->vm_entry_instruction_len);
7365         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7366                 vmcs12->guest_interruptibility_info);
7367         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7368         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7369         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7370         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7371                 vmcs12->guest_pending_dbg_exceptions);
7372         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7373         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7374
7375         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7376
7377         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7378                 (vmcs_config.pin_based_exec_ctrl |
7379                  vmcs12->pin_based_vm_exec_control));
7380
7381         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7382                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7383                              vmcs12->vmx_preemption_timer_value);
7384
7385         /*
7386          * Whether page-faults are trapped is determined by a combination of
7387          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7388          * If enable_ept, L0 doesn't care about page faults and we should
7389          * set all of these to L1's desires. However, if !enable_ept, L0 does
7390          * care about (at least some) page faults, and because it is not easy
7391          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7392          * to exit on each and every L2 page fault. This is done by setting
7393          * MASK=MATCH=0 and (see below) EB.PF=1.
7394          * Note that below we don't need special code to set EB.PF beyond the
7395          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7396          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7397          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7398          *
7399          * A problem with this approach (when !enable_ept) is that L1 may be
7400          * injected with more page faults than it asked for. This could have
7401          * caused problems, but in practice existing hypervisors don't care.
7402          * To fix this, we will need to emulate the PFEC checking (on the L1
7403          * page tables), using walk_addr(), when injecting PFs to L1.
7404          */
7405         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7406                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7407         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7408                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7409
7410         if (cpu_has_secondary_exec_ctrls()) {
7411                 u32 exec_control = vmx_secondary_exec_control(vmx);
7412                 if (!vmx->rdtscp_enabled)
7413                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7414                 /* Take the following fields only from vmcs12 */
7415                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7416                 if (nested_cpu_has(vmcs12,
7417                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7418                         exec_control |= vmcs12->secondary_vm_exec_control;
7419
7420                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7421                         /*
7422                          * Translate L1 physical address to host physical
7423                          * address for vmcs02. Keep the page pinned, so this
7424                          * physical address remains valid. We keep a reference
7425                          * to it so we can release it later.
7426                          */
7427                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7428                                 nested_release_page(vmx->nested.apic_access_page);
7429                         vmx->nested.apic_access_page =
7430                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7431                         /*
7432                          * If translation failed, no matter: This feature asks
7433                          * to exit when accessing the given address, and if it
7434                          * can never be accessed, this feature won't do
7435                          * anything anyway.
7436                          */
7437                         if (!vmx->nested.apic_access_page)
7438                                 exec_control &=
7439                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7440                         else
7441                                 vmcs_write64(APIC_ACCESS_ADDR,
7442                                   page_to_phys(vmx->nested.apic_access_page));
7443                 }
7444
7445                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7446         }
7447
7448
7449         /*
7450          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7451          * Some constant fields are set here by vmx_set_constant_host_state().
7452          * Other fields are different per CPU, and will be set later when
7453          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7454          */
7455         vmx_set_constant_host_state(vmx);
7456
7457         /*
7458          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7459          * entry, but only if the current (host) sp changed from the value
7460          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7461          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7462          * here we just force the write to happen on entry.
7463          */
7464         vmx->host_rsp = 0;
7465
7466         exec_control = vmx_exec_control(vmx); /* L0's desires */
7467         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7468         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7469         exec_control &= ~CPU_BASED_TPR_SHADOW;
7470         exec_control |= vmcs12->cpu_based_vm_exec_control;
7471         /*
7472          * Merging of IO and MSR bitmaps not currently supported.
7473          * Rather, exit every time.
7474          */
7475         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7476         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7477         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7478
7479         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7480
7481         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7482          * bitwise-or of what L1 wants to trap for L2, and what we want to
7483          * trap. Note that CR0.TS also needs updating - we do this later.
7484          */
7485         update_exception_bitmap(vcpu);
7486         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7487         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7488
7489         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7490         vmcs_write32(VM_EXIT_CONTROLS,
7491                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7492         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7493                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7494
7495         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7496                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7497         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7498                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7499
7500
7501         set_cr4_guest_host_mask(vmx);
7502
7503         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7504                 vmcs_write64(TSC_OFFSET,
7505                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7506         else
7507                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7508
7509         if (enable_vpid) {
7510                 /*
7511                  * Trivially support vpid by letting L2s share their parent
7512                  * L1's vpid. TODO: move to a more elaborate solution, giving
7513                  * each L2 its own vpid and exposing the vpid feature to L1.
7514                  */
7515                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7516                 vmx_flush_tlb(vcpu);
7517         }
7518
7519         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7520                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7521         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7522                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7523         else
7524                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7525         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7526         vmx_set_efer(vcpu, vcpu->arch.efer);
7527
7528         /*
7529          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7530          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7531          * The CR0_READ_SHADOW is what L2 should have expected to read given
7532          * the specifications by L1; It's not enough to take
7533          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7534          * have more bits than L1 expected.
7535          */
7536         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7537         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7538
7539         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7540         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7541
7542         /* shadow page tables on either EPT or shadow page tables */
7543         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7544         kvm_mmu_reset_context(vcpu);
7545
7546         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7547         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7548 }
7549
7550 /*
7551  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7552  * for running an L2 nested guest.
7553  */
7554 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7555 {
7556         struct vmcs12 *vmcs12;
7557         struct vcpu_vmx *vmx = to_vmx(vcpu);
7558         int cpu;
7559         struct loaded_vmcs *vmcs02;
7560         bool ia32e;
7561
7562         if (!nested_vmx_check_permission(vcpu) ||
7563             !nested_vmx_check_vmcs12(vcpu))
7564                 return 1;
7565
7566         skip_emulated_instruction(vcpu);
7567         vmcs12 = get_vmcs12(vcpu);
7568
7569         if (enable_shadow_vmcs)
7570                 copy_shadow_to_vmcs12(vmx);
7571
7572         /*
7573          * The nested entry process starts with enforcing various prerequisites
7574          * on vmcs12 as required by the Intel SDM, and act appropriately when
7575          * they fail: As the SDM explains, some conditions should cause the
7576          * instruction to fail, while others will cause the instruction to seem
7577          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7578          * To speed up the normal (success) code path, we should avoid checking
7579          * for misconfigurations which will anyway be caught by the processor
7580          * when using the merged vmcs02.
7581          */
7582         if (vmcs12->launch_state == launch) {
7583                 nested_vmx_failValid(vcpu,
7584                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7585                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7586                 return 1;
7587         }
7588
7589         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7590                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7591                 return 1;
7592         }
7593
7594         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7595                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7596                 /*TODO: Also verify bits beyond physical address width are 0*/
7597                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7598                 return 1;
7599         }
7600
7601         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7602                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7603                 /*TODO: Also verify bits beyond physical address width are 0*/
7604                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7605                 return 1;
7606         }
7607
7608         if (vmcs12->vm_entry_msr_load_count > 0 ||
7609             vmcs12->vm_exit_msr_load_count > 0 ||
7610             vmcs12->vm_exit_msr_store_count > 0) {
7611                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7612                                     __func__);
7613                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7614                 return 1;
7615         }
7616
7617         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7618               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7619             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7620               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7621             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7622               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7623             !vmx_control_verify(vmcs12->vm_exit_controls,
7624               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7625             !vmx_control_verify(vmcs12->vm_entry_controls,
7626               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7627         {
7628                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7629                 return 1;
7630         }
7631
7632         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7633             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7634                 nested_vmx_failValid(vcpu,
7635                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7636                 return 1;
7637         }
7638
7639         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7640             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7641                 nested_vmx_entry_failure(vcpu, vmcs12,
7642                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7643                 return 1;
7644         }
7645         if (vmcs12->vmcs_link_pointer != -1ull) {
7646                 nested_vmx_entry_failure(vcpu, vmcs12,
7647                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7648                 return 1;
7649         }
7650
7651         /*
7652          * If the load IA32_EFER VM-entry control is 1, the following checks
7653          * are performed on the field for the IA32_EFER MSR:
7654          * - Bits reserved in the IA32_EFER MSR must be 0.
7655          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7656          *   the IA-32e mode guest VM-exit control. It must also be identical
7657          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7658          *   CR0.PG) is 1.
7659          */
7660         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7661                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7662                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7663                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7664                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7665                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7666                         nested_vmx_entry_failure(vcpu, vmcs12,
7667                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7668                         return 1;
7669                 }
7670         }
7671
7672         /*
7673          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7674          * IA32_EFER MSR must be 0 in the field for that register. In addition,
7675          * the values of the LMA and LME bits in the field must each be that of
7676          * the host address-space size VM-exit control.
7677          */
7678         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7679                 ia32e = (vmcs12->vm_exit_controls &
7680                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7681                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7682                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7683                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7684                         nested_vmx_entry_failure(vcpu, vmcs12,
7685                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7686                         return 1;
7687                 }
7688         }
7689
7690         /*
7691          * We're finally done with prerequisite checking, and can start with
7692          * the nested entry.
7693          */
7694
7695         vmcs02 = nested_get_current_vmcs02(vmx);
7696         if (!vmcs02)
7697                 return -ENOMEM;
7698
7699         enter_guest_mode(vcpu);
7700
7701         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7702
7703         cpu = get_cpu();
7704         vmx->loaded_vmcs = vmcs02;
7705         vmx_vcpu_put(vcpu);
7706         vmx_vcpu_load(vcpu, cpu);
7707         vcpu->cpu = cpu;
7708         put_cpu();
7709
7710         vmx_segment_cache_clear(vmx);
7711
7712         vmcs12->launch_state = 1;
7713
7714         prepare_vmcs02(vcpu, vmcs12);
7715
7716         /*
7717          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7718          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7719          * returned as far as L1 is concerned. It will only return (and set
7720          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7721          */
7722         return 1;
7723 }
7724
7725 /*
7726  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7727  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7728  * This function returns the new value we should put in vmcs12.guest_cr0.
7729  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7730  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7731  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7732  *     didn't trap the bit, because if L1 did, so would L0).
7733  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7734  *     been modified by L2, and L1 knows it. So just leave the old value of
7735  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7736  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7737  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7738  *     changed these bits, and therefore they need to be updated, but L0
7739  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7740  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7741  */
7742 static inline unsigned long
7743 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7744 {
7745         return
7746         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7747         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7748         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7749                         vcpu->arch.cr0_guest_owned_bits));
7750 }
7751
7752 static inline unsigned long
7753 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7754 {
7755         return
7756         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7757         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7758         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7759                         vcpu->arch.cr4_guest_owned_bits));
7760 }
7761
7762 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7763                                        struct vmcs12 *vmcs12)
7764 {
7765         u32 idt_vectoring;
7766         unsigned int nr;
7767
7768         if (vcpu->arch.exception.pending) {
7769                 nr = vcpu->arch.exception.nr;
7770                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7771
7772                 if (kvm_exception_is_soft(nr)) {
7773                         vmcs12->vm_exit_instruction_len =
7774                                 vcpu->arch.event_exit_inst_len;
7775                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7776                 } else
7777                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7778
7779                 if (vcpu->arch.exception.has_error_code) {
7780                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7781                         vmcs12->idt_vectoring_error_code =
7782                                 vcpu->arch.exception.error_code;
7783                 }
7784
7785                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7786         } else if (vcpu->arch.nmi_pending) {
7787                 vmcs12->idt_vectoring_info_field =
7788                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7789         } else if (vcpu->arch.interrupt.pending) {
7790                 nr = vcpu->arch.interrupt.nr;
7791                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7792
7793                 if (vcpu->arch.interrupt.soft) {
7794                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
7795                         vmcs12->vm_entry_instruction_len =
7796                                 vcpu->arch.event_exit_inst_len;
7797                 } else
7798                         idt_vectoring |= INTR_TYPE_EXT_INTR;
7799
7800                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7801         }
7802 }
7803
7804 /*
7805  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7806  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7807  * and this function updates it to reflect the changes to the guest state while
7808  * L2 was running (and perhaps made some exits which were handled directly by L0
7809  * without going back to L1), and to reflect the exit reason.
7810  * Note that we do not have to copy here all VMCS fields, just those that
7811  * could have changed by the L2 guest or the exit - i.e., the guest-state and
7812  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7813  * which already writes to vmcs12 directly.
7814  */
7815 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7816 {
7817         /* update guest state fields: */
7818         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7819         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7820
7821         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7822         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7823         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7824         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7825
7826         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7827         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7828         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7829         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7830         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7831         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7832         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7833         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7834         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7835         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7836         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7837         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7838         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7839         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7840         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7841         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7842         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7843         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7844         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7845         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7846         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7847         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7848         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7849         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7850         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7851         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7852         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7853         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7854         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7855         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7856         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7857         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7858         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7859         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7860         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7861         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7862
7863         vmcs12->guest_interruptibility_info =
7864                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7865         vmcs12->guest_pending_dbg_exceptions =
7866                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7867
7868         vmcs12->vm_entry_controls =
7869                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7870                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7871
7872         /* TODO: These cannot have changed unless we have MSR bitmaps and
7873          * the relevant bit asks not to trap the change */
7874         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7875         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
7876                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7877         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7878         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7879         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7880
7881         /* update exit information fields: */
7882
7883         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
7884         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7885
7886         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7887         if ((vmcs12->vm_exit_intr_info &
7888              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7889             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7890                 vmcs12->vm_exit_intr_error_code =
7891                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7892         vmcs12->idt_vectoring_info_field = 0;
7893         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7894         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7895
7896         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7897                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7898                  * instead of reading the real value. */
7899                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7900
7901                 /*
7902                  * Transfer the event that L0 or L1 may wanted to inject into
7903                  * L2 to IDT_VECTORING_INFO_FIELD.
7904                  */
7905                 vmcs12_save_pending_event(vcpu, vmcs12);
7906         }
7907
7908         /*
7909          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7910          * preserved above and would only end up incorrectly in L1.
7911          */
7912         vcpu->arch.nmi_injected = false;
7913         kvm_clear_exception_queue(vcpu);
7914         kvm_clear_interrupt_queue(vcpu);
7915 }
7916
7917 /*
7918  * A part of what we need to when the nested L2 guest exits and we want to
7919  * run its L1 parent, is to reset L1's guest state to the host state specified
7920  * in vmcs12.
7921  * This function is to be called not only on normal nested exit, but also on
7922  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7923  * Failures During or After Loading Guest State").
7924  * This function should be called when the active VMCS is L1's (vmcs01).
7925  */
7926 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7927                                    struct vmcs12 *vmcs12)
7928 {
7929         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7930                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7931         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7932                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7933         else
7934                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7935         vmx_set_efer(vcpu, vcpu->arch.efer);
7936
7937         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7938         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7939         vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
7940         /*
7941          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7942          * actually changed, because it depends on the current state of
7943          * fpu_active (which may have changed).
7944          * Note that vmx_set_cr0 refers to efer set above.
7945          */
7946         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7947         /*
7948          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7949          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7950          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7951          */
7952         update_exception_bitmap(vcpu);
7953         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7954         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7955
7956         /*
7957          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7958          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7959          */
7960         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7961         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7962
7963         /* shadow page tables on either EPT or shadow page tables */
7964         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7965         kvm_mmu_reset_context(vcpu);
7966
7967         if (enable_vpid) {
7968                 /*
7969                  * Trivially support vpid by letting L2s share their parent
7970                  * L1's vpid. TODO: move to a more elaborate solution, giving
7971                  * each L2 its own vpid and exposing the vpid feature to L1.
7972                  */
7973                 vmx_flush_tlb(vcpu);
7974         }
7975
7976
7977         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7978         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7979         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7980         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7981         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7982         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7983         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7984         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7985         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7986         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7987         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7988         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7989         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7990         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7991         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7992
7993         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7994                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7995         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7996                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7997                         vmcs12->host_ia32_perf_global_ctrl);
7998
7999         kvm_set_dr(vcpu, 7, 0x400);
8000         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8001 }
8002
8003 /*
8004  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8005  * and modify vmcs12 to make it see what it would expect to see there if
8006  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8007  */
8008 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8009 {
8010         struct vcpu_vmx *vmx = to_vmx(vcpu);
8011         int cpu;
8012         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8013
8014         /* trying to cancel vmlaunch/vmresume is a bug */
8015         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8016
8017         leave_guest_mode(vcpu);
8018         prepare_vmcs12(vcpu, vmcs12);
8019
8020         cpu = get_cpu();
8021         vmx->loaded_vmcs = &vmx->vmcs01;
8022         vmx_vcpu_put(vcpu);
8023         vmx_vcpu_load(vcpu, cpu);
8024         vcpu->cpu = cpu;
8025         put_cpu();
8026
8027         vmx_segment_cache_clear(vmx);
8028
8029         /* if no vmcs02 cache requested, remove the one we used */
8030         if (VMCS02_POOL_SIZE == 0)
8031                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8032
8033         load_vmcs12_host_state(vcpu, vmcs12);
8034
8035         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8036         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8037
8038         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8039         vmx->host_rsp = 0;
8040
8041         /* Unpin physical memory we referred to in vmcs02 */
8042         if (vmx->nested.apic_access_page) {
8043                 nested_release_page(vmx->nested.apic_access_page);
8044                 vmx->nested.apic_access_page = 0;
8045         }
8046
8047         /*
8048          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8049          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8050          * success or failure flag accordingly.
8051          */
8052         if (unlikely(vmx->fail)) {
8053                 vmx->fail = 0;
8054                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8055         } else
8056                 nested_vmx_succeed(vcpu);
8057         if (enable_shadow_vmcs)
8058                 vmx->nested.sync_shadow_vmcs = true;
8059 }
8060
8061 /*
8062  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8063  * 23.7 "VM-entry failures during or after loading guest state" (this also
8064  * lists the acceptable exit-reason and exit-qualification parameters).
8065  * It should only be called before L2 actually succeeded to run, and when
8066  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8067  */
8068 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8069                         struct vmcs12 *vmcs12,
8070                         u32 reason, unsigned long qualification)
8071 {
8072         load_vmcs12_host_state(vcpu, vmcs12);
8073         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8074         vmcs12->exit_qualification = qualification;
8075         nested_vmx_succeed(vcpu);
8076         if (enable_shadow_vmcs)
8077                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8078 }
8079
8080 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8081                                struct x86_instruction_info *info,
8082                                enum x86_intercept_stage stage)
8083 {
8084         return X86EMUL_CONTINUE;
8085 }
8086
8087 static struct kvm_x86_ops vmx_x86_ops = {
8088         .cpu_has_kvm_support = cpu_has_kvm_support,
8089         .disabled_by_bios = vmx_disabled_by_bios,
8090         .hardware_setup = hardware_setup,
8091         .hardware_unsetup = hardware_unsetup,
8092         .check_processor_compatibility = vmx_check_processor_compat,
8093         .hardware_enable = hardware_enable,
8094         .hardware_disable = hardware_disable,
8095         .cpu_has_accelerated_tpr = report_flexpriority,
8096
8097         .vcpu_create = vmx_create_vcpu,
8098         .vcpu_free = vmx_free_vcpu,
8099         .vcpu_reset = vmx_vcpu_reset,
8100
8101         .prepare_guest_switch = vmx_save_host_state,
8102         .vcpu_load = vmx_vcpu_load,
8103         .vcpu_put = vmx_vcpu_put,
8104
8105         .update_db_bp_intercept = update_exception_bitmap,
8106         .get_msr = vmx_get_msr,
8107         .set_msr = vmx_set_msr,
8108         .get_segment_base = vmx_get_segment_base,
8109         .get_segment = vmx_get_segment,
8110         .set_segment = vmx_set_segment,
8111         .get_cpl = vmx_get_cpl,
8112         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8113         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8114         .decache_cr3 = vmx_decache_cr3,
8115         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8116         .set_cr0 = vmx_set_cr0,
8117         .set_cr3 = vmx_set_cr3,
8118         .set_cr4 = vmx_set_cr4,
8119         .set_efer = vmx_set_efer,
8120         .get_idt = vmx_get_idt,
8121         .set_idt = vmx_set_idt,
8122         .get_gdt = vmx_get_gdt,
8123         .set_gdt = vmx_set_gdt,
8124         .set_dr7 = vmx_set_dr7,
8125         .cache_reg = vmx_cache_reg,
8126         .get_rflags = vmx_get_rflags,
8127         .set_rflags = vmx_set_rflags,
8128         .fpu_activate = vmx_fpu_activate,
8129         .fpu_deactivate = vmx_fpu_deactivate,
8130
8131         .tlb_flush = vmx_flush_tlb,
8132
8133         .run = vmx_vcpu_run,
8134         .handle_exit = vmx_handle_exit,
8135         .skip_emulated_instruction = skip_emulated_instruction,
8136         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8137         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8138         .patch_hypercall = vmx_patch_hypercall,
8139         .set_irq = vmx_inject_irq,
8140         .set_nmi = vmx_inject_nmi,
8141         .queue_exception = vmx_queue_exception,
8142         .cancel_injection = vmx_cancel_injection,
8143         .interrupt_allowed = vmx_interrupt_allowed,
8144         .nmi_allowed = vmx_nmi_allowed,
8145         .get_nmi_mask = vmx_get_nmi_mask,
8146         .set_nmi_mask = vmx_set_nmi_mask,
8147         .enable_nmi_window = enable_nmi_window,
8148         .enable_irq_window = enable_irq_window,
8149         .update_cr8_intercept = update_cr8_intercept,
8150         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8151         .vm_has_apicv = vmx_vm_has_apicv,
8152         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8153         .hwapic_irr_update = vmx_hwapic_irr_update,
8154         .hwapic_isr_update = vmx_hwapic_isr_update,
8155         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8156         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8157
8158         .set_tss_addr = vmx_set_tss_addr,
8159         .get_tdp_level = get_ept_level,
8160         .get_mt_mask = vmx_get_mt_mask,
8161
8162         .get_exit_info = vmx_get_exit_info,
8163
8164         .get_lpage_level = vmx_get_lpage_level,
8165
8166         .cpuid_update = vmx_cpuid_update,
8167
8168         .rdtscp_supported = vmx_rdtscp_supported,
8169         .invpcid_supported = vmx_invpcid_supported,
8170
8171         .set_supported_cpuid = vmx_set_supported_cpuid,
8172
8173         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8174
8175         .set_tsc_khz = vmx_set_tsc_khz,
8176         .read_tsc_offset = vmx_read_tsc_offset,
8177         .write_tsc_offset = vmx_write_tsc_offset,
8178         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8179         .compute_tsc_offset = vmx_compute_tsc_offset,
8180         .read_l1_tsc = vmx_read_l1_tsc,
8181
8182         .set_tdp_cr3 = vmx_set_cr3,
8183
8184         .check_intercept = vmx_check_intercept,
8185         .handle_external_intr = vmx_handle_external_intr,
8186 };
8187
8188 static int __init vmx_init(void)
8189 {
8190         int r, i, msr;
8191
8192         rdmsrl_safe(MSR_EFER, &host_efer);
8193
8194         for (i = 0; i < NR_VMX_MSR; ++i)
8195                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8196
8197         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8198         if (!vmx_io_bitmap_a)
8199                 return -ENOMEM;
8200
8201         r = -ENOMEM;
8202
8203         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8204         if (!vmx_io_bitmap_b)
8205                 goto out;
8206
8207         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8208         if (!vmx_msr_bitmap_legacy)
8209                 goto out1;
8210
8211         vmx_msr_bitmap_legacy_x2apic =
8212                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8213         if (!vmx_msr_bitmap_legacy_x2apic)
8214                 goto out2;
8215
8216         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8217         if (!vmx_msr_bitmap_longmode)
8218                 goto out3;
8219
8220         vmx_msr_bitmap_longmode_x2apic =
8221                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8222         if (!vmx_msr_bitmap_longmode_x2apic)
8223                 goto out4;
8224         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8225         if (!vmx_vmread_bitmap)
8226                 goto out5;
8227
8228         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8229         if (!vmx_vmwrite_bitmap)
8230                 goto out6;
8231
8232         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8233         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8234         /* shadowed read/write fields */
8235         for (i = 0; i < max_shadow_read_write_fields; i++) {
8236                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8237                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8238         }
8239         /* shadowed read only fields */
8240         for (i = 0; i < max_shadow_read_only_fields; i++)
8241                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8242
8243         /*
8244          * Allow direct access to the PC debug port (it is often used for I/O
8245          * delays, but the vmexits simply slow things down).
8246          */
8247         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8248         clear_bit(0x80, vmx_io_bitmap_a);
8249
8250         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8251
8252         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8253         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8254
8255         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8256
8257         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8258                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8259         if (r)
8260                 goto out7;
8261
8262 #ifdef CONFIG_KEXEC
8263         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8264                            crash_vmclear_local_loaded_vmcss);
8265 #endif
8266
8267         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8268         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8269         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8270         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8271         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8272         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8273         memcpy(vmx_msr_bitmap_legacy_x2apic,
8274                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8275         memcpy(vmx_msr_bitmap_longmode_x2apic,
8276                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8277
8278         if (enable_apicv) {
8279                 for (msr = 0x800; msr <= 0x8ff; msr++)
8280                         vmx_disable_intercept_msr_read_x2apic(msr);
8281
8282                 /* According SDM, in x2apic mode, the whole id reg is used.
8283                  * But in KVM, it only use the highest eight bits. Need to
8284                  * intercept it */
8285                 vmx_enable_intercept_msr_read_x2apic(0x802);
8286                 /* TMCCT */
8287                 vmx_enable_intercept_msr_read_x2apic(0x839);
8288                 /* TPR */
8289                 vmx_disable_intercept_msr_write_x2apic(0x808);
8290                 /* EOI */
8291                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8292                 /* SELF-IPI */
8293                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8294         }
8295
8296         if (enable_ept) {
8297                 kvm_mmu_set_mask_ptes(0ull,
8298                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8299                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8300                         0ull, VMX_EPT_EXECUTABLE_MASK);
8301                 ept_set_mmio_spte_mask();
8302                 kvm_enable_tdp();
8303         } else
8304                 kvm_disable_tdp();
8305
8306         return 0;
8307
8308 out7:
8309         free_page((unsigned long)vmx_vmwrite_bitmap);
8310 out6:
8311         free_page((unsigned long)vmx_vmread_bitmap);
8312 out5:
8313         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8314 out4:
8315         free_page((unsigned long)vmx_msr_bitmap_longmode);
8316 out3:
8317         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8318 out2:
8319         free_page((unsigned long)vmx_msr_bitmap_legacy);
8320 out1:
8321         free_page((unsigned long)vmx_io_bitmap_b);
8322 out:
8323         free_page((unsigned long)vmx_io_bitmap_a);
8324         return r;
8325 }
8326
8327 static void __exit vmx_exit(void)
8328 {
8329         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8330         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8331         free_page((unsigned long)vmx_msr_bitmap_legacy);
8332         free_page((unsigned long)vmx_msr_bitmap_longmode);
8333         free_page((unsigned long)vmx_io_bitmap_b);
8334         free_page((unsigned long)vmx_io_bitmap_a);
8335         free_page((unsigned long)vmx_vmwrite_bitmap);
8336         free_page((unsigned long)vmx_vmread_bitmap);
8337
8338 #ifdef CONFIG_KEXEC
8339         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8340         synchronize_rcu();
8341 #endif
8342
8343         kvm_exit();
8344 }
8345
8346 module_init(vmx_init)
8347 module_exit(vmx_exit)