Pileus Git - ~andy/linux/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45
  46 #include "trace.h"
  47
  48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  49 #define __ex_clear(x, reg) \
  50         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  51
  52 MODULE_AUTHOR("Qumranet");
  53 MODULE_LICENSE("GPL");
  54
  55 static const struct x86_cpu_id vmx_cpu_id[] = {
  56         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  57         {}
  58 };
  59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  60
  61 static bool __read_mostly enable_vpid = 1;
  62 module_param_named(vpid, enable_vpid, bool, 0444);
  63
  64 static bool __read_mostly flexpriority_enabled = 1;
  65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  66
  67 static bool __read_mostly enable_ept = 1;
  68 module_param_named(ept, enable_ept, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_unrestricted_guest = 1;
  71 module_param_named(unrestricted_guest,
  72                         enable_unrestricted_guest, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept_ad_bits = 1;
  75 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  76
  77 static bool __read_mostly emulate_invalid_guest_state = true;
  78 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  79
  80 static bool __read_mostly vmm_exclusive = 1;
  81 module_param(vmm_exclusive, bool, S_IRUGO);
  82
  83 static bool __read_mostly fasteoi = 1;
  84 module_param(fasteoi, bool, S_IRUGO);
  85
  86 /*
  87  * If nested=1, nested virtualization is supported, i.e., guests may use
  88  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  89  * use VMX instructions.
  90  */
  91 static bool __read_mostly nested = 0;
  92 module_param(nested, bool, S_IRUGO);
  93
  94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  95         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  96 #define KVM_GUEST_CR0_MASK                                              \
  97         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  99         (X86_CR0_WP | X86_CR0_NE)
 100 #define KVM_VM_CR0_ALWAYS_ON                                            \
 101         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 102 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 103         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 104          | X86_CR4_OSXMMEXCPT)
 105
 106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 108
 109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 110
 111 /*
 112  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 113  * ple_gap:    upper bound on the amount of time between two successive
 114  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 115  *             According to test, this time is usually smaller than 128 cycles.
 116  * ple_window: upper bound on the amount of time a guest is allowed to execute
 117  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 118  *             less than 2^12 cycles
 119  * Time is measured based on a counter that runs at the same rate as the TSC,
 120  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 121  */
 122 #define KVM_VMX_DEFAULT_PLE_GAP    128
 123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 124 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 125 module_param(ple_gap, int, S_IRUGO);
 126
 127 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 128 module_param(ple_window, int, S_IRUGO);
 129
 130 #define NR_AUTOLOAD_MSRS 8
 131 #define VMCS02_POOL_SIZE 1
 132
 133 struct vmcs {
 134         u32 revision_id;
 135         u32 abort;
 136         char data[0];
 137 };
 138
 139 /*
 140  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 141  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 142  * loaded on this CPU (so we can clear them if the CPU goes down).
 143  */
 144 struct loaded_vmcs {
 145         struct vmcs *vmcs;
 146         int cpu;
 147         int launched;
 148         struct list_head loaded_vmcss_on_cpu_link;
 149 };
 150
 151 struct shared_msr_entry {
 152         unsigned index;
 153         u64 data;
 154         u64 mask;
 155 };
 156
 157 /*
 158  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 159  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 160  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 161  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 162  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 163  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 164  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 165  * underlying hardware which will be used to run L2.
 166  * This structure is packed to ensure that its layout is identical across
 167  * machines (necessary for live migration).
 168  * If there are changes in this struct, VMCS12_REVISION must be changed.
 169  */
 170 typedef u64 natural_width;
 171 struct __packed vmcs12 {
 172         /* According to the Intel spec, a VMCS region must start with the
 173          * following two fields. Then follow implementation-specific data.
 174          */
 175         u32 revision_id;
 176         u32 abort;
 177
 178         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 179         u32 padding[7]; /* room for future expansion */
 180
 181         u64 io_bitmap_a;
 182         u64 io_bitmap_b;
 183         u64 msr_bitmap;
 184         u64 vm_exit_msr_store_addr;
 185         u64 vm_exit_msr_load_addr;
 186         u64 vm_entry_msr_load_addr;
 187         u64 tsc_offset;
 188         u64 virtual_apic_page_addr;
 189         u64 apic_access_addr;
 190         u64 ept_pointer;
 191         u64 guest_physical_address;
 192         u64 vmcs_link_pointer;
 193         u64 guest_ia32_debugctl;
 194         u64 guest_ia32_pat;
 195         u64 guest_ia32_efer;
 196         u64 guest_ia32_perf_global_ctrl;
 197         u64 guest_pdptr0;
 198         u64 guest_pdptr1;
 199         u64 guest_pdptr2;
 200         u64 guest_pdptr3;
 201         u64 host_ia32_pat;
 202         u64 host_ia32_efer;
 203         u64 host_ia32_perf_global_ctrl;
 204         u64 padding64[8]; /* room for future expansion */
 205         /*
 206          * To allow migration of L1 (complete with its L2 guests) between
 207          * machines of different natural widths (32 or 64 bit), we cannot have
 208          * unsigned long fields with no explict size. We use u64 (aliased
 209          * natural_width) instead. Luckily, x86 is little-endian.
 210          */
 211         natural_width cr0_guest_host_mask;
 212         natural_width cr4_guest_host_mask;
 213         natural_width cr0_read_shadow;
 214         natural_width cr4_read_shadow;
 215         natural_width cr3_target_value0;
 216         natural_width cr3_target_value1;
 217         natural_width cr3_target_value2;
 218         natural_width cr3_target_value3;
 219         natural_width exit_qualification;
 220         natural_width guest_linear_address;
 221         natural_width guest_cr0;
 222         natural_width guest_cr3;
 223         natural_width guest_cr4;
 224         natural_width guest_es_base;
 225         natural_width guest_cs_base;
 226         natural_width guest_ss_base;
 227         natural_width guest_ds_base;
 228         natural_width guest_fs_base;
 229         natural_width guest_gs_base;
 230         natural_width guest_ldtr_base;
 231         natural_width guest_tr_base;
 232         natural_width guest_gdtr_base;
 233         natural_width guest_idtr_base;
 234         natural_width guest_dr7;
 235         natural_width guest_rsp;
 236         natural_width guest_rip;
 237         natural_width guest_rflags;
 238         natural_width guest_pending_dbg_exceptions;
 239         natural_width guest_sysenter_esp;
 240         natural_width guest_sysenter_eip;
 241         natural_width host_cr0;
 242         natural_width host_cr3;
 243         natural_width host_cr4;
 244         natural_width host_fs_base;
 245         natural_width host_gs_base;
 246         natural_width host_tr_base;
 247         natural_width host_gdtr_base;
 248         natural_width host_idtr_base;
 249         natural_width host_ia32_sysenter_esp;
 250         natural_width host_ia32_sysenter_eip;
 251         natural_width host_rsp;
 252         natural_width host_rip;
 253         natural_width paddingl[8]; /* room for future expansion */
 254         u32 pin_based_vm_exec_control;
 255         u32 cpu_based_vm_exec_control;
 256         u32 exception_bitmap;
 257         u32 page_fault_error_code_mask;
 258         u32 page_fault_error_code_match;
 259         u32 cr3_target_count;
 260         u32 vm_exit_controls;
 261         u32 vm_exit_msr_store_count;
 262         u32 vm_exit_msr_load_count;
 263         u32 vm_entry_controls;
 264         u32 vm_entry_msr_load_count;
 265         u32 vm_entry_intr_info_field;
 266         u32 vm_entry_exception_error_code;
 267         u32 vm_entry_instruction_len;
 268         u32 tpr_threshold;
 269         u32 secondary_vm_exec_control;
 270         u32 vm_instruction_error;
 271         u32 vm_exit_reason;
 272         u32 vm_exit_intr_info;
 273         u32 vm_exit_intr_error_code;
 274         u32 idt_vectoring_info_field;
 275         u32 idt_vectoring_error_code;
 276         u32 vm_exit_instruction_len;
 277         u32 vmx_instruction_info;
 278         u32 guest_es_limit;
 279         u32 guest_cs_limit;
 280         u32 guest_ss_limit;
 281         u32 guest_ds_limit;
 282         u32 guest_fs_limit;
 283         u32 guest_gs_limit;
 284         u32 guest_ldtr_limit;
 285         u32 guest_tr_limit;
 286         u32 guest_gdtr_limit;
 287         u32 guest_idtr_limit;
 288         u32 guest_es_ar_bytes;
 289         u32 guest_cs_ar_bytes;
 290         u32 guest_ss_ar_bytes;
 291         u32 guest_ds_ar_bytes;
 292         u32 guest_fs_ar_bytes;
 293         u32 guest_gs_ar_bytes;
 294         u32 guest_ldtr_ar_bytes;
 295         u32 guest_tr_ar_bytes;
 296         u32 guest_interruptibility_info;
 297         u32 guest_activity_state;
 298         u32 guest_sysenter_cs;
 299         u32 host_ia32_sysenter_cs;
 300         u32 padding32[8]; /* room for future expansion */
 301         u16 virtual_processor_id;
 302         u16 guest_es_selector;
 303         u16 guest_cs_selector;
 304         u16 guest_ss_selector;
 305         u16 guest_ds_selector;
 306         u16 guest_fs_selector;
 307         u16 guest_gs_selector;
 308         u16 guest_ldtr_selector;
 309         u16 guest_tr_selector;
 310         u16 host_es_selector;
 311         u16 host_cs_selector;
 312         u16 host_ss_selector;
 313         u16 host_ds_selector;
 314         u16 host_fs_selector;
 315         u16 host_gs_selector;
 316         u16 host_tr_selector;
 317 };
 318
 319 /*
 320  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 321  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 322  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 323  */
 324 #define VMCS12_REVISION 0x11e57ed0
 325
 326 /*
 327  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 328  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 329  * current implementation, 4K are reserved to avoid future complications.
 330  */
 331 #define VMCS12_SIZE 0x1000
 332
 333 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 334 struct vmcs02_list {
 335         struct list_head list;
 336         gpa_t vmptr;
 337         struct loaded_vmcs vmcs02;
 338 };
 339
 340 /*
 341  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 342  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 343  */
 344 struct nested_vmx {
 345         /* Has the level1 guest done vmxon? */
 346         bool vmxon;
 347
 348         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 349         gpa_t current_vmptr;
 350         /* The host-usable pointer to the above */
 351         struct page *current_vmcs12_page;
 352         struct vmcs12 *current_vmcs12;
 353
 354         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 355         struct list_head vmcs02_pool;
 356         int vmcs02_num;
 357         u64 vmcs01_tsc_offset;
 358         /* L2 must run next, and mustn't decide to exit to L1. */
 359         bool nested_run_pending;
 360         /*
 361          * Guest pages referred to in vmcs02 with host-physical pointers, so
 362          * we must keep them pinned while L2 runs.
 363          */
 364         struct page *apic_access_page;
 365 };
 366
 367 struct vcpu_vmx {
 368         struct kvm_vcpu       vcpu;
 369         unsigned long         host_rsp;
 370         u8                    fail;
 371         u8                    cpl;
 372         bool                  nmi_known_unmasked;
 373         u32                   exit_intr_info;
 374         u32                   idt_vectoring_info;
 375         ulong                 rflags;
 376         struct shared_msr_entry *guest_msrs;
 377         int                   nmsrs;
 378         int                   save_nmsrs;
 379 #ifdef CONFIG_X86_64
 380         u64                   msr_host_kernel_gs_base;
 381         u64                   msr_guest_kernel_gs_base;
 382 #endif
 383         /*
 384          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 385          * non-nested (L1) guest, it always points to vmcs01. For a nested
 386          * guest (L2), it points to a different VMCS.
 387          */
 388         struct loaded_vmcs    vmcs01;
 389         struct loaded_vmcs   *loaded_vmcs;
 390         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 391         struct msr_autoload {
 392                 unsigned nr;
 393                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 394                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 395         } msr_autoload;
 396         struct {
 397                 int           loaded;
 398                 u16           fs_sel, gs_sel, ldt_sel;
 399 #ifdef CONFIG_X86_64
 400                 u16           ds_sel, es_sel;
 401 #endif
 402                 int           gs_ldt_reload_needed;
 403                 int           fs_reload_needed;
 404         } host_state;
 405         struct {
 406                 int vm86_active;
 407                 ulong save_rflags;
 408                 struct kvm_save_segment {
 409                         u16 selector;
 410                         unsigned long base;
 411                         u32 limit;
 412                         u32 ar;
 413                 } tr, es, ds, fs, gs;
 414         } rmode;
 415         struct {
 416                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 417                 struct kvm_save_segment seg[8];
 418         } segment_cache;
 419         int vpid;
 420         bool emulation_required;
 421
 422         /* Support for vnmi-less CPUs */
 423         int soft_vnmi_blocked;
 424         ktime_t entry_time;
 425         s64 vnmi_blocked_time;
 426         u32 exit_reason;
 427
 428         bool rdtscp_enabled;
 429
 430         /* Support for a guest hypervisor (nested VMX) */
 431         struct nested_vmx nested;
 432 };
 433
 434 enum segment_cache_field {
 435         SEG_FIELD_SEL = 0,
 436         SEG_FIELD_BASE = 1,
 437         SEG_FIELD_LIMIT = 2,
 438         SEG_FIELD_AR = 3,
 439
 440         SEG_FIELD_NR = 4
 441 };
 442
 443 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 444 {
 445         return container_of(vcpu, struct vcpu_vmx, vcpu);
 446 }
 447
 448 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 449 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 450 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 451                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 452
 453 static unsigned short vmcs_field_to_offset_table[] = {
 454         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 455         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 456         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 457         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 458         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 459         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 460         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 461         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 462         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 463         FIELD(HOST_ES_SELECTOR, host_es_selector),
 464         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 465         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 466         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 467         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 468         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 469         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 470         FIELD64(IO_BITMAP_A, io_bitmap_a),
 471         FIELD64(IO_BITMAP_B, io_bitmap_b),
 472         FIELD64(MSR_BITMAP, msr_bitmap),
 473         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 474         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 475         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 476         FIELD64(TSC_OFFSET, tsc_offset),
 477         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 478         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 479         FIELD64(EPT_POINTER, ept_pointer),
 480         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 481         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 482         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 483         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 484         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 485         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 486         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 487         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 488         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 489         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 490         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 491         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 492         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 493         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 494         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 495         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 496         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 497         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 498         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 499         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 500         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 501         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 502         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 503         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 504         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 505         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 506         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 507         FIELD(TPR_THRESHOLD, tpr_threshold),
 508         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 509         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 510         FIELD(VM_EXIT_REASON, vm_exit_reason),
 511         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 512         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 513         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 514         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 515         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 516         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 517         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 518         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 519         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 520         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 521         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 522         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 523         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 524         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 525         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 526         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 527         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 528         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 529         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 530         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 531         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 532         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 533         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 534         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 535         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 536         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 537         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 538         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 539         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 540         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 541         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 542         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 543         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 544         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 545         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 546         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 547         FIELD(EXIT_QUALIFICATION, exit_qualification),
 548         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 549         FIELD(GUEST_CR0, guest_cr0),
 550         FIELD(GUEST_CR3, guest_cr3),
 551         FIELD(GUEST_CR4, guest_cr4),
 552         FIELD(GUEST_ES_BASE, guest_es_base),
 553         FIELD(GUEST_CS_BASE, guest_cs_base),
 554         FIELD(GUEST_SS_BASE, guest_ss_base),
 555         FIELD(GUEST_DS_BASE, guest_ds_base),
 556         FIELD(GUEST_FS_BASE, guest_fs_base),
 557         FIELD(GUEST_GS_BASE, guest_gs_base),
 558         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 559         FIELD(GUEST_TR_BASE, guest_tr_base),
 560         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 561         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 562         FIELD(GUEST_DR7, guest_dr7),
 563         FIELD(GUEST_RSP, guest_rsp),
 564         FIELD(GUEST_RIP, guest_rip),
 565         FIELD(GUEST_RFLAGS, guest_rflags),
 566         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 567         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 568         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 569         FIELD(HOST_CR0, host_cr0),
 570         FIELD(HOST_CR3, host_cr3),
 571         FIELD(HOST_CR4, host_cr4),
 572         FIELD(HOST_FS_BASE, host_fs_base),
 573         FIELD(HOST_GS_BASE, host_gs_base),
 574         FIELD(HOST_TR_BASE, host_tr_base),
 575         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 576         FIELD(HOST_IDTR_BASE, host_idtr_base),
 577         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 578         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 579         FIELD(HOST_RSP, host_rsp),
 580         FIELD(HOST_RIP, host_rip),
 581 };
 582 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 583
 584 static inline short vmcs_field_to_offset(unsigned long field)
 585 {
 586         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 587                 return -1;
 588         return vmcs_field_to_offset_table[field];
 589 }
 590
 591 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 592 {
 593         return to_vmx(vcpu)->nested.current_vmcs12;
 594 }
 595
 596 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 597 {
 598         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 599         if (is_error_page(page))
 600                 return NULL;
 601
 602         return page;
 603 }
 604
 605 static void nested_release_page(struct page *page)
 606 {
 607         kvm_release_page_dirty(page);
 608 }
 609
 610 static void nested_release_page_clean(struct page *page)
 611 {
 612         kvm_release_page_clean(page);
 613 }
 614
 615 static u64 construct_eptp(unsigned long root_hpa);
 616 static void kvm_cpu_vmxon(u64 addr);
 617 static void kvm_cpu_vmxoff(void);
 618 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 619 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 620 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 621                             struct kvm_segment *var, int seg);
 622 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 623                             struct kvm_segment *var, int seg);
 624
 625 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 626 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 627 /*
 628  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 629  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 630  */
 631 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 632 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 633
 634 static unsigned long *vmx_io_bitmap_a;
 635 static unsigned long *vmx_io_bitmap_b;
 636 static unsigned long *vmx_msr_bitmap_legacy;
 637 static unsigned long *vmx_msr_bitmap_longmode;
 638
 639 static bool cpu_has_load_ia32_efer;
 640 static bool cpu_has_load_perf_global_ctrl;
 641
 642 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 643 static DEFINE_SPINLOCK(vmx_vpid_lock);
 644
 645 static struct vmcs_config {
 646         int size;
 647         int order;
 648         u32 revision_id;
 649         u32 pin_based_exec_ctrl;
 650         u32 cpu_based_exec_ctrl;
 651         u32 cpu_based_2nd_exec_ctrl;
 652         u32 vmexit_ctrl;
 653         u32 vmentry_ctrl;
 654 } vmcs_config;
 655
 656 static struct vmx_capability {
 657         u32 ept;
 658         u32 vpid;
 659 } vmx_capability;
 660
 661 #define VMX_SEGMENT_FIELD(seg)                                  \
 662         [VCPU_SREG_##seg] = {                                   \
 663                 .selector = GUEST_##seg##_SELECTOR,             \
 664                 .base = GUEST_##seg##_BASE,                     \
 665                 .limit = GUEST_##seg##_LIMIT,                   \
 666                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 667         }
 668
 669 static struct kvm_vmx_segment_field {
 670         unsigned selector;
 671         unsigned base;
 672         unsigned limit;
 673         unsigned ar_bytes;
 674 } kvm_vmx_segment_fields[] = {
 675         VMX_SEGMENT_FIELD(CS),
 676         VMX_SEGMENT_FIELD(DS),
 677         VMX_SEGMENT_FIELD(ES),
 678         VMX_SEGMENT_FIELD(FS),
 679         VMX_SEGMENT_FIELD(GS),
 680         VMX_SEGMENT_FIELD(SS),
 681         VMX_SEGMENT_FIELD(TR),
 682         VMX_SEGMENT_FIELD(LDTR),
 683 };
 684
 685 static u64 host_efer;
 686
 687 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 688
 689 /*
 690  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 691  * away by decrementing the array size.
 692  */
 693 static const u32 vmx_msr_index[] = {
 694 #ifdef CONFIG_X86_64
 695         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 696 #endif
 697         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 698 };
 699 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 700
 701 static inline bool is_page_fault(u32 intr_info)
 702 {
 703         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 704                              INTR_INFO_VALID_MASK)) ==
 705                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 706 }
 707
 708 static inline bool is_no_device(u32 intr_info)
 709 {
 710         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 711                              INTR_INFO_VALID_MASK)) ==
 712                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 713 }
 714
 715 static inline bool is_invalid_opcode(u32 intr_info)
 716 {
 717         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 718                              INTR_INFO_VALID_MASK)) ==
 719                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 720 }
 721
 722 static inline bool is_external_interrupt(u32 intr_info)
 723 {
 724         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 725                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 726 }
 727
 728 static inline bool is_machine_check(u32 intr_info)
 729 {
 730         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 731                              INTR_INFO_VALID_MASK)) ==
 732                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 733 }
 734
 735 static inline bool cpu_has_vmx_msr_bitmap(void)
 736 {
 737         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 738 }
 739
 740 static inline bool cpu_has_vmx_tpr_shadow(void)
 741 {
 742         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 743 }
 744
 745 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 746 {
 747         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 748 }
 749
 750 static inline bool cpu_has_secondary_exec_ctrls(void)
 751 {
 752         return vmcs_config.cpu_based_exec_ctrl &
 753                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 754 }
 755
 756 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 757 {
 758         return vmcs_config.cpu_based_2nd_exec_ctrl &
 759                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 760 }
 761
 762 static inline bool cpu_has_vmx_flexpriority(void)
 763 {
 764         return cpu_has_vmx_tpr_shadow() &&
 765                 cpu_has_vmx_virtualize_apic_accesses();
 766 }
 767
 768 static inline bool cpu_has_vmx_ept_execute_only(void)
 769 {
 770         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 771 }
 772
 773 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 774 {
 775         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 776 }
 777
 778 static inline bool cpu_has_vmx_eptp_writeback(void)
 779 {
 780         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 781 }
 782
 783 static inline bool cpu_has_vmx_ept_2m_page(void)
 784 {
 785         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 786 }
 787
 788 static inline bool cpu_has_vmx_ept_1g_page(void)
 789 {
 790         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 791 }
 792
 793 static inline bool cpu_has_vmx_ept_4levels(void)
 794 {
 795         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 796 }
 797
 798 static inline bool cpu_has_vmx_ept_ad_bits(void)
 799 {
 800         return vmx_capability.ept & VMX_EPT_AD_BIT;
 801 }
 802
 803 static inline bool cpu_has_vmx_invept_individual_addr(void)
 804 {
 805         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 806 }
 807
 808 static inline bool cpu_has_vmx_invept_context(void)
 809 {
 810         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 811 }
 812
 813 static inline bool cpu_has_vmx_invept_global(void)
 814 {
 815         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 816 }
 817
 818 static inline bool cpu_has_vmx_invvpid_single(void)
 819 {
 820         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 821 }
 822
 823 static inline bool cpu_has_vmx_invvpid_global(void)
 824 {
 825         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 826 }
 827
 828 static inline bool cpu_has_vmx_ept(void)
 829 {
 830         return vmcs_config.cpu_based_2nd_exec_ctrl &
 831                 SECONDARY_EXEC_ENABLE_EPT;
 832 }
 833
 834 static inline bool cpu_has_vmx_unrestricted_guest(void)
 835 {
 836         return vmcs_config.cpu_based_2nd_exec_ctrl &
 837                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 838 }
 839
 840 static inline bool cpu_has_vmx_ple(void)
 841 {
 842         return vmcs_config.cpu_based_2nd_exec_ctrl &
 843                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 844 }
 845
 846 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 847 {
 848         return flexpriority_enabled && irqchip_in_kernel(kvm);
 849 }
 850
 851 static inline bool cpu_has_vmx_vpid(void)
 852 {
 853         return vmcs_config.cpu_based_2nd_exec_ctrl &
 854                 SECONDARY_EXEC_ENABLE_VPID;
 855 }
 856
 857 static inline bool cpu_has_vmx_rdtscp(void)
 858 {
 859         return vmcs_config.cpu_based_2nd_exec_ctrl &
 860                 SECONDARY_EXEC_RDTSCP;
 861 }
 862
 863 static inline bool cpu_has_vmx_invpcid(void)
 864 {
 865         return vmcs_config.cpu_based_2nd_exec_ctrl &
 866                 SECONDARY_EXEC_ENABLE_INVPCID;
 867 }
 868
 869 static inline bool cpu_has_virtual_nmis(void)
 870 {
 871         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 872 }
 873
 874 static inline bool cpu_has_vmx_wbinvd_exit(void)
 875 {
 876         return vmcs_config.cpu_based_2nd_exec_ctrl &
 877                 SECONDARY_EXEC_WBINVD_EXITING;
 878 }
 879
 880 static inline bool report_flexpriority(void)
 881 {
 882         return flexpriority_enabled;
 883 }
 884
 885 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 886 {
 887         return vmcs12->cpu_based_vm_exec_control & bit;
 888 }
 889
 890 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 891 {
 892         return (vmcs12->cpu_based_vm_exec_control &
 893                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 894                 (vmcs12->secondary_vm_exec_control & bit);
 895 }
 896
 897 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 898         struct kvm_vcpu *vcpu)
 899 {
 900         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 901 }
 902
 903 static inline bool is_exception(u32 intr_info)
 904 {
 905         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 906                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 907 }
 908
 909 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 910 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 911                         struct vmcs12 *vmcs12,
 912                         u32 reason, unsigned long qualification);
 913
 914 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 915 {
 916         int i;
 917
 918         for (i = 0; i < vmx->nmsrs; ++i)
 919                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 920                         return i;
 921         return -1;
 922 }
 923
 924 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 925 {
 926     struct {
 927         u64 vpid : 16;
 928         u64 rsvd : 48;
 929         u64 gva;
 930     } operand = { vpid, 0, gva };
 931
 932     asm volatile (__ex(ASM_VMX_INVVPID)
 933                   /* CF==1 or ZF==1 --> rc = -1 */
 934                   "; ja 1f ; ud2 ; 1:"
 935                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 936 }
 937
 938 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 939 {
 940         struct {
 941                 u64 eptp, gpa;
 942         } operand = {eptp, gpa};
 943
 944         asm volatile (__ex(ASM_VMX_INVEPT)
 945                         /* CF==1 or ZF==1 --> rc = -1 */
 946                         "; ja 1f ; ud2 ; 1:\n"
 947                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 948 }
 949
 950 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 951 {
 952         int i;
 953
 954         i = __find_msr_index(vmx, msr);
 955         if (i >= 0)
 956                 return &vmx->guest_msrs[i];
 957         return NULL;
 958 }
 959
 960 static void vmcs_clear(struct vmcs *vmcs)
 961 {
 962         u64 phys_addr = __pa(vmcs);
 963         u8 error;
 964
 965         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 966                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 967                       : "cc", "memory");
 968         if (error)
 969                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 970                        vmcs, phys_addr);
 971 }
 972
 973 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 974 {
 975         vmcs_clear(loaded_vmcs->vmcs);
 976         loaded_vmcs->cpu = -1;
 977         loaded_vmcs->launched = 0;
 978 }
 979
 980 static void vmcs_load(struct vmcs *vmcs)
 981 {
 982         u64 phys_addr = __pa(vmcs);
 983         u8 error;
 984
 985         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 986                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 987                         : "cc", "memory");
 988         if (error)
 989                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 990                        vmcs, phys_addr);
 991 }
 992
 993 static void __loaded_vmcs_clear(void *arg)
 994 {
 995         struct loaded_vmcs *loaded_vmcs = arg;
 996         int cpu = raw_smp_processor_id();
 997
 998         if (loaded_vmcs->cpu != cpu)
 999                 return; /* vcpu migration can race with cpu offline */
1000         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1001                 per_cpu(current_vmcs, cpu) = NULL;
1002         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1003         loaded_vmcs_init(loaded_vmcs);
1004 }
1005
1006 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1007 {
1008         if (loaded_vmcs->cpu != -1)
1009                 smp_call_function_single(
1010                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
1011 }
1012
1013 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1014 {
1015         if (vmx->vpid == 0)
1016                 return;
1017
1018         if (cpu_has_vmx_invvpid_single())
1019                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1020 }
1021
1022 static inline void vpid_sync_vcpu_global(void)
1023 {
1024         if (cpu_has_vmx_invvpid_global())
1025                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1026 }
1027
1028 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1029 {
1030         if (cpu_has_vmx_invvpid_single())
1031                 vpid_sync_vcpu_single(vmx);
1032         else
1033                 vpid_sync_vcpu_global();
1034 }
1035
1036 static inline void ept_sync_global(void)
1037 {
1038         if (cpu_has_vmx_invept_global())
1039                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1040 }
1041
1042 static inline void ept_sync_context(u64 eptp)
1043 {
1044         if (enable_ept) {
1045                 if (cpu_has_vmx_invept_context())
1046                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1047                 else
1048                         ept_sync_global();
1049         }
1050 }
1051
1052 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1053 {
1054         if (enable_ept) {
1055                 if (cpu_has_vmx_invept_individual_addr())
1056                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1057                                         eptp, gpa);
1058                 else
1059                         ept_sync_context(eptp);
1060         }
1061 }
1062
1063 static __always_inline unsigned long vmcs_readl(unsigned long field)
1064 {
1065         unsigned long value;
1066
1067         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1068                       : "=a"(value) : "d"(field) : "cc");
1069         return value;
1070 }
1071
1072 static __always_inline u16 vmcs_read16(unsigned long field)
1073 {
1074         return vmcs_readl(field);
1075 }
1076
1077 static __always_inline u32 vmcs_read32(unsigned long field)
1078 {
1079         return vmcs_readl(field);
1080 }
1081
1082 static __always_inline u64 vmcs_read64(unsigned long field)
1083 {
1084 #ifdef CONFIG_X86_64
1085         return vmcs_readl(field);
1086 #else
1087         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1088 #endif
1089 }
1090
1091 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1092 {
1093         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1094                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1095         dump_stack();
1096 }
1097
1098 static void vmcs_writel(unsigned long field, unsigned long value)
1099 {
1100         u8 error;
1101
1102         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1103                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1104         if (unlikely(error))
1105                 vmwrite_error(field, value);
1106 }
1107
1108 static void vmcs_write16(unsigned long field, u16 value)
1109 {
1110         vmcs_writel(field, value);
1111 }
1112
1113 static void vmcs_write32(unsigned long field, u32 value)
1114 {
1115         vmcs_writel(field, value);
1116 }
1117
1118 static void vmcs_write64(unsigned long field, u64 value)
1119 {
1120         vmcs_writel(field, value);
1121 #ifndef CONFIG_X86_64
1122         asm volatile ("");
1123         vmcs_writel(field+1, value >> 32);
1124 #endif
1125 }
1126
1127 static void vmcs_clear_bits(unsigned long field, u32 mask)
1128 {
1129         vmcs_writel(field, vmcs_readl(field) & ~mask);
1130 }
1131
1132 static void vmcs_set_bits(unsigned long field, u32 mask)
1133 {
1134         vmcs_writel(field, vmcs_readl(field) | mask);
1135 }
1136
1137 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1138 {
1139         vmx->segment_cache.bitmask = 0;
1140 }
1141
1142 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1143                                        unsigned field)
1144 {
1145         bool ret;
1146         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1147
1148         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1149                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1150                 vmx->segment_cache.bitmask = 0;
1151         }
1152         ret = vmx->segment_cache.bitmask & mask;
1153         vmx->segment_cache.bitmask |= mask;
1154         return ret;
1155 }
1156
1157 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1158 {
1159         u16 *p = &vmx->segment_cache.seg[seg].selector;
1160
1161         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1162                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1163         return *p;
1164 }
1165
1166 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1167 {
1168         ulong *p = &vmx->segment_cache.seg[seg].base;
1169
1170         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1171                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1172         return *p;
1173 }
1174
1175 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1176 {
1177         u32 *p = &vmx->segment_cache.seg[seg].limit;
1178
1179         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1180                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1181         return *p;
1182 }
1183
1184 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1185 {
1186         u32 *p = &vmx->segment_cache.seg[seg].ar;
1187
1188         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1189                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1190         return *p;
1191 }
1192
1193 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1194 {
1195         u32 eb;
1196
1197         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1198              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1199         if ((vcpu->guest_debug &
1200              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1201             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1202                 eb |= 1u << BP_VECTOR;
1203         if (to_vmx(vcpu)->rmode.vm86_active)
1204                 eb = ~0;
1205         if (enable_ept)
1206                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1207         if (vcpu->fpu_active)
1208                 eb &= ~(1u << NM_VECTOR);
1209
1210         /* When we are running a nested L2 guest and L1 specified for it a
1211          * certain exception bitmap, we must trap the same exceptions and pass
1212          * them to L1. When running L2, we will only handle the exceptions
1213          * specified above if L1 did not want them.
1214          */
1215         if (is_guest_mode(vcpu))
1216                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1217
1218         vmcs_write32(EXCEPTION_BITMAP, eb);
1219 }
1220
1221 static void clear_atomic_switch_msr_special(unsigned long entry,
1222                 unsigned long exit)
1223 {
1224         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1225         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1226 }
1227
1228 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1229 {
1230         unsigned i;
1231         struct msr_autoload *m = &vmx->msr_autoload;
1232
1233         switch (msr) {
1234         case MSR_EFER:
1235                 if (cpu_has_load_ia32_efer) {
1236                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1237                                         VM_EXIT_LOAD_IA32_EFER);
1238                         return;
1239                 }
1240                 break;
1241         case MSR_CORE_PERF_GLOBAL_CTRL:
1242                 if (cpu_has_load_perf_global_ctrl) {
1243                         clear_atomic_switch_msr_special(
1244                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1245                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1246                         return;
1247                 }
1248                 break;
1249         }
1250
1251         for (i = 0; i < m->nr; ++i)
1252                 if (m->guest[i].index == msr)
1253                         break;
1254
1255         if (i == m->nr)
1256                 return;
1257         --m->nr;
1258         m->guest[i] = m->guest[m->nr];
1259         m->host[i] = m->host[m->nr];
1260         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1261         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1262 }
1263
1264 static void add_atomic_switch_msr_special(unsigned long entry,
1265                 unsigned long exit, unsigned long guest_val_vmcs,
1266                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1267 {
1268         vmcs_write64(guest_val_vmcs, guest_val);
1269         vmcs_write64(host_val_vmcs, host_val);
1270         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1271         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1272 }
1273
1274 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1275                                   u64 guest_val, u64 host_val)
1276 {
1277         unsigned i;
1278         struct msr_autoload *m = &vmx->msr_autoload;
1279
1280         switch (msr) {
1281         case MSR_EFER:
1282                 if (cpu_has_load_ia32_efer) {
1283                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1284                                         VM_EXIT_LOAD_IA32_EFER,
1285                                         GUEST_IA32_EFER,
1286                                         HOST_IA32_EFER,
1287                                         guest_val, host_val);
1288                         return;
1289                 }
1290                 break;
1291         case MSR_CORE_PERF_GLOBAL_CTRL:
1292                 if (cpu_has_load_perf_global_ctrl) {
1293                         add_atomic_switch_msr_special(
1294                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1295                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1296                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1297                                         HOST_IA32_PERF_GLOBAL_CTRL,
1298                                         guest_val, host_val);
1299                         return;
1300                 }
1301                 break;
1302         }
1303
1304         for (i = 0; i < m->nr; ++i)
1305                 if (m->guest[i].index == msr)
1306                         break;
1307
1308         if (i == NR_AUTOLOAD_MSRS) {
1309                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1310                                 "Can't add msr %x\n", msr);
1311                 return;
1312         } else if (i == m->nr) {
1313                 ++m->nr;
1314                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1315                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1316         }
1317
1318         m->guest[i].index = msr;
1319         m->guest[i].value = guest_val;
1320         m->host[i].index = msr;
1321         m->host[i].value = host_val;
1322 }
1323
1324 static void reload_tss(void)
1325 {
1326         /*
1327          * VT restores TR but not its size.  Useless.
1328          */
1329         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1330         struct desc_struct *descs;
1331
1332         descs = (void *)gdt->address;
1333         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1334         load_TR_desc();
1335 }
1336
1337 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1338 {
1339         u64 guest_efer;
1340         u64 ignore_bits;
1341
1342         guest_efer = vmx->vcpu.arch.efer;
1343
1344         /*
1345          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1346          * outside long mode
1347          */
1348         ignore_bits = EFER_NX | EFER_SCE;
1349 #ifdef CONFIG_X86_64
1350         ignore_bits |= EFER_LMA | EFER_LME;
1351         /* SCE is meaningful only in long mode on Intel */
1352         if (guest_efer & EFER_LMA)
1353                 ignore_bits &= ~(u64)EFER_SCE;
1354 #endif
1355         guest_efer &= ~ignore_bits;
1356         guest_efer |= host_efer & ignore_bits;
1357         vmx->guest_msrs[efer_offset].data = guest_efer;
1358         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1359
1360         clear_atomic_switch_msr(vmx, MSR_EFER);
1361         /* On ept, can't emulate nx, and must switch nx atomically */
1362         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1363                 guest_efer = vmx->vcpu.arch.efer;
1364                 if (!(guest_efer & EFER_LMA))
1365                         guest_efer &= ~EFER_LME;
1366                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1367                 return false;
1368         }
1369
1370         return true;
1371 }
1372
1373 static unsigned long segment_base(u16 selector)
1374 {
1375         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1376         struct desc_struct *d;
1377         unsigned long table_base;
1378         unsigned long v;
1379
1380         if (!(selector & ~3))
1381                 return 0;
1382
1383         table_base = gdt->address;
1384
1385         if (selector & 4) {           /* from ldt */
1386                 u16 ldt_selector = kvm_read_ldt();
1387
1388                 if (!(ldt_selector & ~3))
1389                         return 0;
1390
1391                 table_base = segment_base(ldt_selector);
1392         }
1393         d = (struct desc_struct *)(table_base + (selector & ~7));
1394         v = get_desc_base(d);
1395 #ifdef CONFIG_X86_64
1396        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1397                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1398 #endif
1399         return v;
1400 }
1401
1402 static inline unsigned long kvm_read_tr_base(void)
1403 {
1404         u16 tr;
1405         asm("str %0" : "=g"(tr));
1406         return segment_base(tr);
1407 }
1408
1409 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1410 {
1411         struct vcpu_vmx *vmx = to_vmx(vcpu);
1412         int i;
1413
1414         if (vmx->host_state.loaded)
1415                 return;
1416
1417         vmx->host_state.loaded = 1;
1418         /*
1419          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1420          * allow segment selectors with cpl > 0 or ti == 1.
1421          */
1422         vmx->host_state.ldt_sel = kvm_read_ldt();
1423         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1424         savesegment(fs, vmx->host_state.fs_sel);
1425         if (!(vmx->host_state.fs_sel & 7)) {
1426                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1427                 vmx->host_state.fs_reload_needed = 0;
1428         } else {
1429                 vmcs_write16(HOST_FS_SELECTOR, 0);
1430                 vmx->host_state.fs_reload_needed = 1;
1431         }
1432         savesegment(gs, vmx->host_state.gs_sel);
1433         if (!(vmx->host_state.gs_sel & 7))
1434                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1435         else {
1436                 vmcs_write16(HOST_GS_SELECTOR, 0);
1437                 vmx->host_state.gs_ldt_reload_needed = 1;
1438         }
1439
1440 #ifdef CONFIG_X86_64
1441         savesegment(ds, vmx->host_state.ds_sel);
1442         savesegment(es, vmx->host_state.es_sel);
1443 #endif
1444
1445 #ifdef CONFIG_X86_64
1446         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1447         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1448 #else
1449         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1450         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1451 #endif
1452
1453 #ifdef CONFIG_X86_64
1454         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1455         if (is_long_mode(&vmx->vcpu))
1456                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1457 #endif
1458         for (i = 0; i < vmx->save_nmsrs; ++i)
1459                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1460                                    vmx->guest_msrs[i].data,
1461                                    vmx->guest_msrs[i].mask);
1462 }
1463
1464 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1465 {
1466         if (!vmx->host_state.loaded)
1467                 return;
1468
1469         ++vmx->vcpu.stat.host_state_reload;
1470         vmx->host_state.loaded = 0;
1471 #ifdef CONFIG_X86_64
1472         if (is_long_mode(&vmx->vcpu))
1473                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1474 #endif
1475         if (vmx->host_state.gs_ldt_reload_needed) {
1476                 kvm_load_ldt(vmx->host_state.ldt_sel);
1477 #ifdef CONFIG_X86_64
1478                 load_gs_index(vmx->host_state.gs_sel);
1479 #else
1480                 loadsegment(gs, vmx->host_state.gs_sel);
1481 #endif
1482         }
1483         if (vmx->host_state.fs_reload_needed)
1484                 loadsegment(fs, vmx->host_state.fs_sel);
1485 #ifdef CONFIG_X86_64
1486         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1487                 loadsegment(ds, vmx->host_state.ds_sel);
1488                 loadsegment(es, vmx->host_state.es_sel);
1489         }
1490 #endif
1491         reload_tss();
1492 #ifdef CONFIG_X86_64
1493         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1494 #endif
1495         if (user_has_fpu())
1496                 clts();
1497         load_gdt(&__get_cpu_var(host_gdt));
1498 }
1499
1500 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1501 {
1502         preempt_disable();
1503         __vmx_load_host_state(vmx);
1504         preempt_enable();
1505 }
1506
1507 /*
1508  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1509  * vcpu mutex is already taken.
1510  */
1511 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1512 {
1513         struct vcpu_vmx *vmx = to_vmx(vcpu);
1514         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1515
1516         if (!vmm_exclusive)
1517                 kvm_cpu_vmxon(phys_addr);
1518         else if (vmx->loaded_vmcs->cpu != cpu)
1519                 loaded_vmcs_clear(vmx->loaded_vmcs);
1520
1521         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1522                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1523                 vmcs_load(vmx->loaded_vmcs->vmcs);
1524         }
1525
1526         if (vmx->loaded_vmcs->cpu != cpu) {
1527                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1528                 unsigned long sysenter_esp;
1529
1530                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1531                 local_irq_disable();
1532                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1533                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1534                 local_irq_enable();
1535
1536                 /*
1537                  * Linux uses per-cpu TSS and GDT, so set these when switching
1538                  * processors.
1539                  */
1540                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1541                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1542
1543                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1544                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1545                 vmx->loaded_vmcs->cpu = cpu;
1546         }
1547 }
1548
1549 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1550 {
1551         __vmx_load_host_state(to_vmx(vcpu));
1552         if (!vmm_exclusive) {
1553                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1554                 vcpu->cpu = -1;
1555                 kvm_cpu_vmxoff();
1556         }
1557 }
1558
1559 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1560 {
1561         ulong cr0;
1562
1563         if (vcpu->fpu_active)
1564                 return;
1565         vcpu->fpu_active = 1;
1566         cr0 = vmcs_readl(GUEST_CR0);
1567         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1568         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1569         vmcs_writel(GUEST_CR0, cr0);
1570         update_exception_bitmap(vcpu);
1571         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1572         if (is_guest_mode(vcpu))
1573                 vcpu->arch.cr0_guest_owned_bits &=
1574                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1575         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1576 }
1577
1578 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1579
1580 /*
1581  * Return the cr0 value that a nested guest would read. This is a combination
1582  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1583  * its hypervisor (cr0_read_shadow).
1584  */
1585 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1586 {
1587         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1588                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1589 }
1590 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1591 {
1592         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1593                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1594 }
1595
1596 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1597 {
1598         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1599          * set this *before* calling this function.
1600          */
1601         vmx_decache_cr0_guest_bits(vcpu);
1602         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1603         update_exception_bitmap(vcpu);
1604         vcpu->arch.cr0_guest_owned_bits = 0;
1605         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1606         if (is_guest_mode(vcpu)) {
1607                 /*
1608                  * L1's specified read shadow might not contain the TS bit,
1609                  * so now that we turned on shadowing of this bit, we need to
1610                  * set this bit of the shadow. Like in nested_vmx_run we need
1611                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1612                  * up-to-date here because we just decached cr0.TS (and we'll
1613                  * only update vmcs12->guest_cr0 on nested exit).
1614                  */
1615                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1616                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1617                         (vcpu->arch.cr0 & X86_CR0_TS);
1618                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1619         } else
1620                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1621 }
1622
1623 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1624 {
1625         unsigned long rflags, save_rflags;
1626
1627         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1628                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1629                 rflags = vmcs_readl(GUEST_RFLAGS);
1630                 if (to_vmx(vcpu)->rmode.vm86_active) {
1631                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1632                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1633                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1634                 }
1635                 to_vmx(vcpu)->rflags = rflags;
1636         }
1637         return to_vmx(vcpu)->rflags;
1638 }
1639
1640 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1641 {
1642         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1643         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1644         to_vmx(vcpu)->rflags = rflags;
1645         if (to_vmx(vcpu)->rmode.vm86_active) {
1646                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1647                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1648         }
1649         vmcs_writel(GUEST_RFLAGS, rflags);
1650 }
1651
1652 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1653 {
1654         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1655         int ret = 0;
1656
1657         if (interruptibility & GUEST_INTR_STATE_STI)
1658                 ret |= KVM_X86_SHADOW_INT_STI;
1659         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1660                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1661
1662         return ret & mask;
1663 }
1664
1665 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1666 {
1667         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1668         u32 interruptibility = interruptibility_old;
1669
1670         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1671
1672         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1673                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1674         else if (mask & KVM_X86_SHADOW_INT_STI)
1675                 interruptibility |= GUEST_INTR_STATE_STI;
1676
1677         if ((interruptibility != interruptibility_old))
1678                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1679 }
1680
1681 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1682 {
1683         unsigned long rip;
1684
1685         rip = kvm_rip_read(vcpu);
1686         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1687         kvm_rip_write(vcpu, rip);
1688
1689         /* skipping an emulated instruction also counts */
1690         vmx_set_interrupt_shadow(vcpu, 0);
1691 }
1692
1693 /*
1694  * KVM wants to inject page-faults which it got to the guest. This function
1695  * checks whether in a nested guest, we need to inject them to L1 or L2.
1696  * This function assumes it is called with the exit reason in vmcs02 being
1697  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1698  * is running).
1699  */
1700 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1701 {
1702         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1703
1704         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1705         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1706                 return 0;
1707
1708         nested_vmx_vmexit(vcpu);
1709         return 1;
1710 }
1711
1712 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1713                                 bool has_error_code, u32 error_code,
1714                                 bool reinject)
1715 {
1716         struct vcpu_vmx *vmx = to_vmx(vcpu);
1717         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1718
1719         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1720                 nested_pf_handled(vcpu))
1721                 return;
1722
1723         if (has_error_code) {
1724                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1725                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1726         }
1727
1728         if (vmx->rmode.vm86_active) {
1729                 int inc_eip = 0;
1730                 if (kvm_exception_is_soft(nr))
1731                         inc_eip = vcpu->arch.event_exit_inst_len;
1732                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1733                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1734                 return;
1735         }
1736
1737         if (kvm_exception_is_soft(nr)) {
1738                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1739                              vmx->vcpu.arch.event_exit_inst_len);
1740                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1741         } else
1742                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1743
1744         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1745 }
1746
1747 static bool vmx_rdtscp_supported(void)
1748 {
1749         return cpu_has_vmx_rdtscp();
1750 }
1751
1752 static bool vmx_invpcid_supported(void)
1753 {
1754         return cpu_has_vmx_invpcid() && enable_ept;
1755 }
1756
1757 /*
1758  * Swap MSR entry in host/guest MSR entry array.
1759  */
1760 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1761 {
1762         struct shared_msr_entry tmp;
1763
1764         tmp = vmx->guest_msrs[to];
1765         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1766         vmx->guest_msrs[from] = tmp;
1767 }
1768
1769 /*
1770  * Set up the vmcs to automatically save and restore system
1771  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1772  * mode, as fiddling with msrs is very expensive.
1773  */
1774 static void setup_msrs(struct vcpu_vmx *vmx)
1775 {
1776         int save_nmsrs, index;
1777         unsigned long *msr_bitmap;
1778
1779         save_nmsrs = 0;
1780 #ifdef CONFIG_X86_64
1781         if (is_long_mode(&vmx->vcpu)) {
1782                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1783                 if (index >= 0)
1784                         move_msr_up(vmx, index, save_nmsrs++);
1785                 index = __find_msr_index(vmx, MSR_LSTAR);
1786                 if (index >= 0)
1787                         move_msr_up(vmx, index, save_nmsrs++);
1788                 index = __find_msr_index(vmx, MSR_CSTAR);
1789                 if (index >= 0)
1790                         move_msr_up(vmx, index, save_nmsrs++);
1791                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1792                 if (index >= 0 && vmx->rdtscp_enabled)
1793                         move_msr_up(vmx, index, save_nmsrs++);
1794                 /*
1795                  * MSR_STAR is only needed on long mode guests, and only
1796                  * if efer.sce is enabled.
1797                  */
1798                 index = __find_msr_index(vmx, MSR_STAR);
1799                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1800                         move_msr_up(vmx, index, save_nmsrs++);
1801         }
1802 #endif
1803         index = __find_msr_index(vmx, MSR_EFER);
1804         if (index >= 0 && update_transition_efer(vmx, index))
1805                 move_msr_up(vmx, index, save_nmsrs++);
1806
1807         vmx->save_nmsrs = save_nmsrs;
1808
1809         if (cpu_has_vmx_msr_bitmap()) {
1810                 if (is_long_mode(&vmx->vcpu))
1811                         msr_bitmap = vmx_msr_bitmap_longmode;
1812                 else
1813                         msr_bitmap = vmx_msr_bitmap_legacy;
1814
1815                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1816         }
1817 }
1818
1819 /*
1820  * reads and returns guest's timestamp counter "register"
1821  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1822  */
1823 static u64 guest_read_tsc(void)
1824 {
1825         u64 host_tsc, tsc_offset;
1826
1827         rdtscll(host_tsc);
1828         tsc_offset = vmcs_read64(TSC_OFFSET);
1829         return host_tsc + tsc_offset;
1830 }
1831
1832 /*
1833  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1834  * counter, even if a nested guest (L2) is currently running.
1835  */
1836 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1837 {
1838         u64 host_tsc, tsc_offset;
1839
1840         rdtscll(host_tsc);
1841         tsc_offset = is_guest_mode(vcpu) ?
1842                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1843                 vmcs_read64(TSC_OFFSET);
1844         return host_tsc + tsc_offset;
1845 }
1846
1847 /*
1848  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1849  * software catchup for faster rates on slower CPUs.
1850  */
1851 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1852 {
1853         if (!scale)
1854                 return;
1855
1856         if (user_tsc_khz > tsc_khz) {
1857                 vcpu->arch.tsc_catchup = 1;
1858                 vcpu->arch.tsc_always_catchup = 1;
1859         } else
1860                 WARN(1, "user requested TSC rate below hardware speed\n");
1861 }
1862
1863 /*
1864  * writes 'offset' into guest's timestamp counter offset register
1865  */
1866 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1867 {
1868         if (is_guest_mode(vcpu)) {
1869                 /*
1870                  * We're here if L1 chose not to trap WRMSR to TSC. According
1871                  * to the spec, this should set L1's TSC; The offset that L1
1872                  * set for L2 remains unchanged, and still needs to be added
1873                  * to the newly set TSC to get L2's TSC.
1874                  */
1875                 struct vmcs12 *vmcs12;
1876                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1877                 /* recalculate vmcs02.TSC_OFFSET: */
1878                 vmcs12 = get_vmcs12(vcpu);
1879                 vmcs_write64(TSC_OFFSET, offset +
1880                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1881                          vmcs12->tsc_offset : 0));
1882         } else {
1883                 vmcs_write64(TSC_OFFSET, offset);
1884         }
1885 }
1886
1887 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1888 {
1889         u64 offset = vmcs_read64(TSC_OFFSET);
1890         vmcs_write64(TSC_OFFSET, offset + adjustment);
1891         if (is_guest_mode(vcpu)) {
1892                 /* Even when running L2, the adjustment needs to apply to L1 */
1893                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1894         }
1895 }
1896
1897 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1898 {
1899         return target_tsc - native_read_tsc();
1900 }
1901
1902 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1903 {
1904         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1905         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1906 }
1907
1908 /*
1909  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1910  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1911  * all guests if the "nested" module option is off, and can also be disabled
1912  * for a single guest by disabling its VMX cpuid bit.
1913  */
1914 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1915 {
1916         return nested && guest_cpuid_has_vmx(vcpu);
1917 }
1918
1919 /*
1920  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1921  * returned for the various VMX controls MSRs when nested VMX is enabled.
1922  * The same values should also be used to verify that vmcs12 control fields are
1923  * valid during nested entry from L1 to L2.
1924  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1925  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1926  * bit in the high half is on if the corresponding bit in the control field
1927  * may be on. See also vmx_control_verify().
1928  * TODO: allow these variables to be modified (downgraded) by module options
1929  * or other means.
1930  */
1931 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1932 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1933 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1934 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1935 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1936 static __init void nested_vmx_setup_ctls_msrs(void)
1937 {
1938         /*
1939          * Note that as a general rule, the high half of the MSRs (bits in
1940          * the control fields which may be 1) should be initialized by the
1941          * intersection of the underlying hardware's MSR (i.e., features which
1942          * can be supported) and the list of features we want to expose -
1943          * because they are known to be properly supported in our code.
1944          * Also, usually, the low half of the MSRs (bits which must be 1) can
1945          * be set to 0, meaning that L1 may turn off any of these bits. The
1946          * reason is that if one of these bits is necessary, it will appear
1947          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1948          * fields of vmcs01 and vmcs02, will turn these bits off - and
1949          * nested_vmx_exit_handled() will not pass related exits to L1.
1950          * These rules have exceptions below.
1951          */
1952
1953         /* pin-based controls */
1954         /*
1955          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1956          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1957          */
1958         nested_vmx_pinbased_ctls_low = 0x16 ;
1959         nested_vmx_pinbased_ctls_high = 0x16 |
1960                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1961                 PIN_BASED_VIRTUAL_NMIS;
1962
1963         /* exit controls */
1964         nested_vmx_exit_ctls_low = 0;
1965         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1966 #ifdef CONFIG_X86_64
1967         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1968 #else
1969         nested_vmx_exit_ctls_high = 0;
1970 #endif
1971
1972         /* entry controls */
1973         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1974                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1975         nested_vmx_entry_ctls_low = 0;
1976         nested_vmx_entry_ctls_high &=
1977                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1978
1979         /* cpu-based controls */
1980         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1981                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1982         nested_vmx_procbased_ctls_low = 0;
1983         nested_vmx_procbased_ctls_high &=
1984                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1985                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1986                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1987                 CPU_BASED_CR3_STORE_EXITING |
1988 #ifdef CONFIG_X86_64
1989                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1990 #endif
1991                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1992                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1993                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
1994                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1995         /*
1996          * We can allow some features even when not supported by the
1997          * hardware. For example, L1 can specify an MSR bitmap - and we
1998          * can use it to avoid exits to L1 - even when L0 runs L2
1999          * without MSR bitmaps.
2000          */
2001         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2002
2003         /* secondary cpu-based controls */
2004         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2005                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2006         nested_vmx_secondary_ctls_low = 0;
2007         nested_vmx_secondary_ctls_high &=
2008                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2009 }
2010
2011 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2012 {
2013         /*
2014          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2015          */
2016         return ((control & high) | low) == control;
2017 }
2018
2019 static inline u64 vmx_control_msr(u32 low, u32 high)
2020 {
2021         return low | ((u64)high << 32);
2022 }
2023
2024 /*
2025  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2026  * also let it use VMX-specific MSRs.
2027  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2028  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2029  * like all other MSRs).
2030  */
2031 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2032 {
2033         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2034                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2035                 /*
2036                  * According to the spec, processors which do not support VMX
2037                  * should throw a #GP(0) when VMX capability MSRs are read.
2038                  */
2039                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2040                 return 1;
2041         }
2042
2043         switch (msr_index) {
2044         case MSR_IA32_FEATURE_CONTROL:
2045                 *pdata = 0;
2046                 break;
2047         case MSR_IA32_VMX_BASIC:
2048                 /*
2049                  * This MSR reports some information about VMX support. We
2050                  * should return information about the VMX we emulate for the
2051                  * guest, and the VMCS structure we give it - not about the
2052                  * VMX support of the underlying hardware.
2053                  */
2054                 *pdata = VMCS12_REVISION |
2055                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2056                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2057                 break;
2058         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2059         case MSR_IA32_VMX_PINBASED_CTLS:
2060                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2061                                         nested_vmx_pinbased_ctls_high);
2062                 break;
2063         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2064         case MSR_IA32_VMX_PROCBASED_CTLS:
2065                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2066                                         nested_vmx_procbased_ctls_high);
2067                 break;
2068         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2069         case MSR_IA32_VMX_EXIT_CTLS:
2070                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2071                                         nested_vmx_exit_ctls_high);
2072                 break;
2073         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2074         case MSR_IA32_VMX_ENTRY_CTLS:
2075                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2076                                         nested_vmx_entry_ctls_high);
2077                 break;
2078         case MSR_IA32_VMX_MISC:
2079                 *pdata = 0;
2080                 break;
2081         /*
2082          * These MSRs specify bits which the guest must keep fixed (on or off)
2083          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2084          * We picked the standard core2 setting.
2085          */
2086 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2087 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2088         case MSR_IA32_VMX_CR0_FIXED0:
2089                 *pdata = VMXON_CR0_ALWAYSON;
2090                 break;
2091         case MSR_IA32_VMX_CR0_FIXED1:
2092                 *pdata = -1ULL;
2093                 break;
2094         case MSR_IA32_VMX_CR4_FIXED0:
2095                 *pdata = VMXON_CR4_ALWAYSON;
2096                 break;
2097         case MSR_IA32_VMX_CR4_FIXED1:
2098                 *pdata = -1ULL;
2099                 break;
2100         case MSR_IA32_VMX_VMCS_ENUM:
2101                 *pdata = 0x1f;
2102                 break;
2103         case MSR_IA32_VMX_PROCBASED_CTLS2:
2104                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2105                                         nested_vmx_secondary_ctls_high);
2106                 break;
2107         case MSR_IA32_VMX_EPT_VPID_CAP:
2108                 /* Currently, no nested ept or nested vpid */
2109                 *pdata = 0;
2110                 break;
2111         default:
2112                 return 0;
2113         }
2114
2115         return 1;
2116 }
2117
2118 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2119 {
2120         if (!nested_vmx_allowed(vcpu))
2121                 return 0;
2122
2123         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2124                 /* TODO: the right thing. */
2125                 return 1;
2126         /*
2127          * No need to treat VMX capability MSRs specially: If we don't handle
2128          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2129          */
2130         return 0;
2131 }
2132
2133 /*
2134  * Reads an msr value (of 'msr_index') into 'pdata'.
2135  * Returns 0 on success, non-0 otherwise.
2136  * Assumes vcpu_load() was already called.
2137  */
2138 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2139 {
2140         u64 data;
2141         struct shared_msr_entry *msr;
2142
2143         if (!pdata) {
2144                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2145                 return -EINVAL;
2146         }
2147
2148         switch (msr_index) {
2149 #ifdef CONFIG_X86_64
2150         case MSR_FS_BASE:
2151                 data = vmcs_readl(GUEST_FS_BASE);
2152                 break;
2153         case MSR_GS_BASE:
2154                 data = vmcs_readl(GUEST_GS_BASE);
2155                 break;
2156         case MSR_KERNEL_GS_BASE:
2157                 vmx_load_host_state(to_vmx(vcpu));
2158                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2159                 break;
2160 #endif
2161         case MSR_EFER:
2162                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2163         case MSR_IA32_TSC:
2164                 data = guest_read_tsc();
2165                 break;
2166         case MSR_IA32_SYSENTER_CS:
2167                 data = vmcs_read32(GUEST_SYSENTER_CS);
2168                 break;
2169         case MSR_IA32_SYSENTER_EIP:
2170                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2171                 break;
2172         case MSR_IA32_SYSENTER_ESP:
2173                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2174                 break;
2175         case MSR_TSC_AUX:
2176                 if (!to_vmx(vcpu)->rdtscp_enabled)
2177                         return 1;
2178                 /* Otherwise falls through */
2179         default:
2180                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2181                         return 0;
2182                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2183                 if (msr) {
2184                         data = msr->data;
2185                         break;
2186                 }
2187                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2188         }
2189
2190         *pdata = data;
2191         return 0;
2192 }
2193
2194 /*
2195  * Writes msr value into into the appropriate "register".
2196  * Returns 0 on success, non-0 otherwise.
2197  * Assumes vcpu_load() was already called.
2198  */
2199 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2200 {
2201         struct vcpu_vmx *vmx = to_vmx(vcpu);
2202         struct shared_msr_entry *msr;
2203         int ret = 0;
2204
2205         switch (msr_index) {
2206         case MSR_EFER:
2207                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2208                 break;
2209 #ifdef CONFIG_X86_64
2210         case MSR_FS_BASE:
2211                 vmx_segment_cache_clear(vmx);
2212                 vmcs_writel(GUEST_FS_BASE, data);
2213                 break;
2214         case MSR_GS_BASE:
2215                 vmx_segment_cache_clear(vmx);
2216                 vmcs_writel(GUEST_GS_BASE, data);
2217                 break;
2218         case MSR_KERNEL_GS_BASE:
2219                 vmx_load_host_state(vmx);
2220                 vmx->msr_guest_kernel_gs_base = data;
2221                 break;
2222 #endif
2223         case MSR_IA32_SYSENTER_CS:
2224                 vmcs_write32(GUEST_SYSENTER_CS, data);
2225                 break;
2226         case MSR_IA32_SYSENTER_EIP:
2227                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2228                 break;
2229         case MSR_IA32_SYSENTER_ESP:
2230                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2231                 break;
2232         case MSR_IA32_TSC:
2233                 kvm_write_tsc(vcpu, data);
2234                 break;
2235         case MSR_IA32_CR_PAT:
2236                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2237                         vmcs_write64(GUEST_IA32_PAT, data);
2238                         vcpu->arch.pat = data;
2239                         break;
2240                 }
2241                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2242                 break;
2243         case MSR_TSC_AUX:
2244                 if (!vmx->rdtscp_enabled)
2245                         return 1;
2246                 /* Check reserved bit, higher 32 bits should be zero */
2247                 if ((data >> 32) != 0)
2248                         return 1;
2249                 /* Otherwise falls through */
2250         default:
2251                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2252                         break;
2253                 msr = find_msr_entry(vmx, msr_index);
2254                 if (msr) {
2255                         msr->data = data;
2256                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2257                                 preempt_disable();
2258                                 kvm_set_shared_msr(msr->index, msr->data,
2259                                                    msr->mask);
2260                                 preempt_enable();
2261                         }
2262                         break;
2263                 }
2264                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2265         }
2266
2267         return ret;
2268 }
2269
2270 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2271 {
2272         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2273         switch (reg) {
2274         case VCPU_REGS_RSP:
2275                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2276                 break;
2277         case VCPU_REGS_RIP:
2278                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2279                 break;
2280         case VCPU_EXREG_PDPTR:
2281                 if (enable_ept)
2282                         ept_save_pdptrs(vcpu);
2283                 break;
2284         default:
2285                 break;
2286         }
2287 }
2288
2289 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2290 {
2291         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2292                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2293         else
2294                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2295
2296         update_exception_bitmap(vcpu);
2297 }
2298
2299 static __init int cpu_has_kvm_support(void)
2300 {
2301         return cpu_has_vmx();
2302 }
2303
2304 static __init int vmx_disabled_by_bios(void)
2305 {
2306         u64 msr;
2307
2308         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2309         if (msr & FEATURE_CONTROL_LOCKED) {
2310                 /* launched w/ TXT and VMX disabled */
2311                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2312                         && tboot_enabled())
2313                         return 1;
2314                 /* launched w/o TXT and VMX only enabled w/ TXT */
2315                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2316                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2317                         && !tboot_enabled()) {
2318                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2319                                 "activate TXT before enabling KVM\n");
2320                         return 1;
2321                 }
2322                 /* launched w/o TXT and VMX disabled */
2323                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2324                         && !tboot_enabled())
2325                         return 1;
2326         }
2327
2328         return 0;
2329 }
2330
2331 static void kvm_cpu_vmxon(u64 addr)
2332 {
2333         asm volatile (ASM_VMX_VMXON_RAX
2334                         : : "a"(&addr), "m"(addr)
2335                         : "memory", "cc");
2336 }
2337
2338 static int hardware_enable(void *garbage)
2339 {
2340         int cpu = raw_smp_processor_id();
2341         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2342         u64 old, test_bits;
2343
2344         if (read_cr4() & X86_CR4_VMXE)
2345                 return -EBUSY;
2346
2347         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2348         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2349
2350         test_bits = FEATURE_CONTROL_LOCKED;
2351         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2352         if (tboot_enabled())
2353                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2354
2355         if ((old & test_bits) != test_bits) {
2356                 /* enable and lock */
2357                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2358         }
2359         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2360
2361         if (vmm_exclusive) {
2362                 kvm_cpu_vmxon(phys_addr);
2363                 ept_sync_global();
2364         }
2365
2366         store_gdt(&__get_cpu_var(host_gdt));
2367
2368         return 0;
2369 }
2370
2371 static void vmclear_local_loaded_vmcss(void)
2372 {
2373         int cpu = raw_smp_processor_id();
2374         struct loaded_vmcs *v, *n;
2375
2376         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2377                                  loaded_vmcss_on_cpu_link)
2378                 __loaded_vmcs_clear(v);
2379 }
2380
2381
2382 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2383  * tricks.
2384  */
2385 static void kvm_cpu_vmxoff(void)
2386 {
2387         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2388 }
2389
2390 static void hardware_disable(void *garbage)
2391 {
2392         if (vmm_exclusive) {
2393                 vmclear_local_loaded_vmcss();
2394                 kvm_cpu_vmxoff();
2395         }
2396         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2397 }
2398
2399 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2400                                       u32 msr, u32 *result)
2401 {
2402         u32 vmx_msr_low, vmx_msr_high;
2403         u32 ctl = ctl_min | ctl_opt;
2404
2405         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2406
2407         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2408         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2409
2410         /* Ensure minimum (required) set of control bits are supported. */
2411         if (ctl_min & ~ctl)
2412                 return -EIO;
2413
2414         *result = ctl;
2415         return 0;
2416 }
2417
2418 static __init bool allow_1_setting(u32 msr, u32 ctl)
2419 {
2420         u32 vmx_msr_low, vmx_msr_high;
2421
2422         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2423         return vmx_msr_high & ctl;
2424 }
2425
2426 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2427 {
2428         u32 vmx_msr_low, vmx_msr_high;
2429         u32 min, opt, min2, opt2;
2430         u32 _pin_based_exec_control = 0;
2431         u32 _cpu_based_exec_control = 0;
2432         u32 _cpu_based_2nd_exec_control = 0;
2433         u32 _vmexit_control = 0;
2434         u32 _vmentry_control = 0;
2435
2436         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2437         opt = PIN_BASED_VIRTUAL_NMIS;
2438         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2439                                 &_pin_based_exec_control) < 0)
2440                 return -EIO;
2441
2442         min = CPU_BASED_HLT_EXITING |
2443 #ifdef CONFIG_X86_64
2444               CPU_BASED_CR8_LOAD_EXITING |
2445               CPU_BASED_CR8_STORE_EXITING |
2446 #endif
2447               CPU_BASED_CR3_LOAD_EXITING |
2448               CPU_BASED_CR3_STORE_EXITING |
2449               CPU_BASED_USE_IO_BITMAPS |
2450               CPU_BASED_MOV_DR_EXITING |
2451               CPU_BASED_USE_TSC_OFFSETING |
2452               CPU_BASED_MWAIT_EXITING |
2453               CPU_BASED_MONITOR_EXITING |
2454               CPU_BASED_INVLPG_EXITING |
2455               CPU_BASED_RDPMC_EXITING;
2456
2457         opt = CPU_BASED_TPR_SHADOW |
2458               CPU_BASED_USE_MSR_BITMAPS |
2459               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2460         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2461                                 &_cpu_based_exec_control) < 0)
2462                 return -EIO;
2463 #ifdef CONFIG_X86_64
2464         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2465                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2466                                            ~CPU_BASED_CR8_STORE_EXITING;
2467 #endif
2468         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2469                 min2 = 0;
2470                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2471                         SECONDARY_EXEC_WBINVD_EXITING |
2472                         SECONDARY_EXEC_ENABLE_VPID |
2473                         SECONDARY_EXEC_ENABLE_EPT |
2474                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2475                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2476                         SECONDARY_EXEC_RDTSCP |
2477                         SECONDARY_EXEC_ENABLE_INVPCID;
2478                 if (adjust_vmx_controls(min2, opt2,
2479                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2480                                         &_cpu_based_2nd_exec_control) < 0)
2481                         return -EIO;
2482         }
2483 #ifndef CONFIG_X86_64
2484         if (!(_cpu_based_2nd_exec_control &
2485                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2486                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2487 #endif
2488         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2489                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2490                    enabled */
2491                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2492                                              CPU_BASED_CR3_STORE_EXITING |
2493                                              CPU_BASED_INVLPG_EXITING);
2494                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2495                       vmx_capability.ept, vmx_capability.vpid);
2496         }
2497
2498         min = 0;
2499 #ifdef CONFIG_X86_64
2500         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2501 #endif
2502         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2503         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2504                                 &_vmexit_control) < 0)
2505                 return -EIO;
2506
2507         min = 0;
2508         opt = VM_ENTRY_LOAD_IA32_PAT;
2509         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2510                                 &_vmentry_control) < 0)
2511                 return -EIO;
2512
2513         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2514
2515         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2516         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2517                 return -EIO;
2518
2519 #ifdef CONFIG_X86_64
2520         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2521         if (vmx_msr_high & (1u<<16))
2522                 return -EIO;
2523 #endif
2524
2525         /* Require Write-Back (WB) memory type for VMCS accesses. */
2526         if (((vmx_msr_high >> 18) & 15) != 6)
2527                 return -EIO;
2528
2529         vmcs_conf->size = vmx_msr_high & 0x1fff;
2530         vmcs_conf->order = get_order(vmcs_config.size);
2531         vmcs_conf->revision_id = vmx_msr_low;
2532
2533         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2534         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2535         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2536         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2537         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2538
2539         cpu_has_load_ia32_efer =
2540                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2541                                 VM_ENTRY_LOAD_IA32_EFER)
2542                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2543                                    VM_EXIT_LOAD_IA32_EFER);
2544
2545         cpu_has_load_perf_global_ctrl =
2546                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2547                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2548                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2549                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2550
2551         /*
2552          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2553          * but due to arrata below it can't be used. Workaround is to use
2554          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2555          *
2556          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2557          *
2558          * AAK155             (model 26)
2559          * AAP115             (model 30)
2560          * AAT100             (model 37)
2561          * BC86,AAY89,BD102   (model 44)
2562          * BA97               (model 46)
2563          *
2564          */
2565         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2566                 switch (boot_cpu_data.x86_model) {
2567                 case 26:
2568                 case 30:
2569                 case 37:
2570                 case 44:
2571                 case 46:
2572                         cpu_has_load_perf_global_ctrl = false;
2573                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2574                                         "does not work properly. Using workaround\n");
2575                         break;
2576                 default:
2577                         break;
2578                 }
2579         }
2580
2581         return 0;
2582 }
2583
2584 static struct vmcs *alloc_vmcs_cpu(int cpu)
2585 {
2586         int node = cpu_to_node(cpu);
2587         struct page *pages;
2588         struct vmcs *vmcs;
2589
2590         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2591         if (!pages)
2592                 return NULL;
2593         vmcs = page_address(pages);
2594         memset(vmcs, 0, vmcs_config.size);
2595         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2596         return vmcs;
2597 }
2598
2599 static struct vmcs *alloc_vmcs(void)
2600 {
2601         return alloc_vmcs_cpu(raw_smp_processor_id());
2602 }
2603
2604 static void free_vmcs(struct vmcs *vmcs)
2605 {
2606         free_pages((unsigned long)vmcs, vmcs_config.order);
2607 }
2608
2609 /*
2610  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2611  */
2612 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2613 {
2614         if (!loaded_vmcs->vmcs)
2615                 return;
2616         loaded_vmcs_clear(loaded_vmcs);
2617         free_vmcs(loaded_vmcs->vmcs);
2618         loaded_vmcs->vmcs = NULL;
2619 }
2620
2621 static void free_kvm_area(void)
2622 {
2623         int cpu;
2624
2625         for_each_possible_cpu(cpu) {
2626                 free_vmcs(per_cpu(vmxarea, cpu));
2627                 per_cpu(vmxarea, cpu) = NULL;
2628         }
2629 }
2630
2631 static __init int alloc_kvm_area(void)
2632 {
2633         int cpu;
2634
2635         for_each_possible_cpu(cpu) {
2636                 struct vmcs *vmcs;
2637
2638                 vmcs = alloc_vmcs_cpu(cpu);
2639                 if (!vmcs) {
2640                         free_kvm_area();
2641                         return -ENOMEM;
2642                 }
2643
2644                 per_cpu(vmxarea, cpu) = vmcs;
2645         }
2646         return 0;
2647 }
2648
2649 static __init int hardware_setup(void)
2650 {
2651         if (setup_vmcs_config(&vmcs_config) < 0)
2652                 return -EIO;
2653
2654         if (boot_cpu_has(X86_FEATURE_NX))
2655                 kvm_enable_efer_bits(EFER_NX);
2656
2657         if (!cpu_has_vmx_vpid())
2658                 enable_vpid = 0;
2659
2660         if (!cpu_has_vmx_ept() ||
2661             !cpu_has_vmx_ept_4levels()) {
2662                 enable_ept = 0;
2663                 enable_unrestricted_guest = 0;
2664                 enable_ept_ad_bits = 0;
2665         }
2666
2667         if (!cpu_has_vmx_ept_ad_bits())
2668                 enable_ept_ad_bits = 0;
2669
2670         if (!cpu_has_vmx_unrestricted_guest())
2671                 enable_unrestricted_guest = 0;
2672
2673         if (!cpu_has_vmx_flexpriority())
2674                 flexpriority_enabled = 0;
2675
2676         if (!cpu_has_vmx_tpr_shadow())
2677                 kvm_x86_ops->update_cr8_intercept = NULL;
2678
2679         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2680                 kvm_disable_largepages();
2681
2682         if (!cpu_has_vmx_ple())
2683                 ple_gap = 0;
2684
2685         if (nested)
2686                 nested_vmx_setup_ctls_msrs();
2687
2688         return alloc_kvm_area();
2689 }
2690
2691 static __exit void hardware_unsetup(void)
2692 {
2693         free_kvm_area();
2694 }
2695
2696 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2697 {
2698         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2699
2700         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2701                 vmcs_write16(sf->selector, save->selector);
2702                 vmcs_writel(sf->base, save->base);
2703                 vmcs_write32(sf->limit, save->limit);
2704                 vmcs_write32(sf->ar_bytes, save->ar);
2705         } else {
2706                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2707                         << AR_DPL_SHIFT;
2708                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2709         }
2710 }
2711
2712 static void enter_pmode(struct kvm_vcpu *vcpu)
2713 {
2714         unsigned long flags;
2715         struct vcpu_vmx *vmx = to_vmx(vcpu);
2716
2717         vmx->emulation_required = 1;
2718         vmx->rmode.vm86_active = 0;
2719
2720         vmx_segment_cache_clear(vmx);
2721
2722         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2723         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2724         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2725         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2726
2727         flags = vmcs_readl(GUEST_RFLAGS);
2728         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2729         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2730         vmcs_writel(GUEST_RFLAGS, flags);
2731
2732         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2733                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2734
2735         update_exception_bitmap(vcpu);
2736
2737         if (emulate_invalid_guest_state)
2738                 return;
2739
2740         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2741         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2742         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2743         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2744
2745         vmx_segment_cache_clear(vmx);
2746
2747         vmcs_write16(GUEST_SS_SELECTOR, 0);
2748         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2749
2750         vmcs_write16(GUEST_CS_SELECTOR,
2751                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2752         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2753 }
2754
2755 static gva_t rmode_tss_base(struct kvm *kvm)
2756 {
2757         if (!kvm->arch.tss_addr) {
2758                 struct kvm_memslots *slots;
2759                 struct kvm_memory_slot *slot;
2760                 gfn_t base_gfn;
2761
2762                 slots = kvm_memslots(kvm);
2763                 slot = id_to_memslot(slots, 0);
2764                 base_gfn = slot->base_gfn + slot->npages - 3;
2765
2766                 return base_gfn << PAGE_SHIFT;
2767         }
2768         return kvm->arch.tss_addr;
2769 }
2770
2771 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2772 {
2773         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2774
2775         save->selector = vmcs_read16(sf->selector);
2776         save->base = vmcs_readl(sf->base);
2777         save->limit = vmcs_read32(sf->limit);
2778         save->ar = vmcs_read32(sf->ar_bytes);
2779         vmcs_write16(sf->selector, save->base >> 4);
2780         vmcs_write32(sf->base, save->base & 0xffff0);
2781         vmcs_write32(sf->limit, 0xffff);
2782         vmcs_write32(sf->ar_bytes, 0xf3);
2783         if (save->base & 0xf)
2784                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2785                             " aligned when entering protected mode (seg=%d)",
2786                             seg);
2787 }
2788
2789 static void enter_rmode(struct kvm_vcpu *vcpu)
2790 {
2791         unsigned long flags;
2792         struct vcpu_vmx *vmx = to_vmx(vcpu);
2793         struct kvm_segment var;
2794
2795         if (enable_unrestricted_guest)
2796                 return;
2797
2798         vmx->emulation_required = 1;
2799         vmx->rmode.vm86_active = 1;
2800
2801         /*
2802          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2803          * vcpu. Call it here with phys address pointing 16M below 4G.
2804          */
2805         if (!vcpu->kvm->arch.tss_addr) {
2806                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2807                              "called before entering vcpu\n");
2808                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2809                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2810                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2811         }
2812
2813         vmx_segment_cache_clear(vmx);
2814
2815         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2816         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2817         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2818
2819         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2820         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2821
2822         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2823         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2824
2825         flags = vmcs_readl(GUEST_RFLAGS);
2826         vmx->rmode.save_rflags = flags;
2827
2828         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2829
2830         vmcs_writel(GUEST_RFLAGS, flags);
2831         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2832         update_exception_bitmap(vcpu);
2833
2834         if (emulate_invalid_guest_state)
2835                 goto continue_rmode;
2836
2837         vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2838         vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2839
2840         vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2841         vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2842
2843         vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2844         vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2845
2846         vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2847         vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2848
2849         vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2850         vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2851
2852         vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2853         vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2854
2855 continue_rmode:
2856         kvm_mmu_reset_context(vcpu);
2857 }
2858
2859 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2860 {
2861         struct vcpu_vmx *vmx = to_vmx(vcpu);
2862         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2863
2864         if (!msr)
2865                 return;
2866
2867         /*
2868          * Force kernel_gs_base reloading before EFER changes, as control
2869          * of this msr depends on is_long_mode().
2870          */
2871         vmx_load_host_state(to_vmx(vcpu));
2872         vcpu->arch.efer = efer;
2873         if (efer & EFER_LMA) {
2874                 vmcs_write32(VM_ENTRY_CONTROLS,
2875                              vmcs_read32(VM_ENTRY_CONTROLS) |
2876                              VM_ENTRY_IA32E_MODE);
2877                 msr->data = efer;
2878         } else {
2879                 vmcs_write32(VM_ENTRY_CONTROLS,
2880                              vmcs_read32(VM_ENTRY_CONTROLS) &
2881                              ~VM_ENTRY_IA32E_MODE);
2882
2883                 msr->data = efer & ~EFER_LME;
2884         }
2885         setup_msrs(vmx);
2886 }
2887
2888 #ifdef CONFIG_X86_64
2889
2890 static void enter_lmode(struct kvm_vcpu *vcpu)
2891 {
2892         u32 guest_tr_ar;
2893
2894         vmx_segment_cache_clear(to_vmx(vcpu));
2895
2896         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2897         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2898                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2899                                      __func__);
2900                 vmcs_write32(GUEST_TR_AR_BYTES,
2901                              (guest_tr_ar & ~AR_TYPE_MASK)
2902                              | AR_TYPE_BUSY_64_TSS);
2903         }
2904         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2905 }
2906
2907 static void exit_lmode(struct kvm_vcpu *vcpu)
2908 {
2909         vmcs_write32(VM_ENTRY_CONTROLS,
2910                      vmcs_read32(VM_ENTRY_CONTROLS)
2911                      & ~VM_ENTRY_IA32E_MODE);
2912         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2913 }
2914
2915 #endif
2916
2917 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2918 {
2919         vpid_sync_context(to_vmx(vcpu));
2920         if (enable_ept) {
2921                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2922                         return;
2923                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2924         }
2925 }
2926
2927 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2928 {
2929         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2930
2931         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2932         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2933 }
2934
2935 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2936 {
2937         if (enable_ept && is_paging(vcpu))
2938                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2939         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2940 }
2941
2942 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2943 {
2944         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2945
2946         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2947         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2948 }
2949
2950 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2951 {
2952         if (!test_bit(VCPU_EXREG_PDPTR,
2953                       (unsigned long *)&vcpu->arch.regs_dirty))
2954                 return;
2955
2956         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2957                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2958                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2959                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2960                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2961         }
2962 }
2963
2964 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2965 {
2966         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2967                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2968                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2969                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2970                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2971         }
2972
2973         __set_bit(VCPU_EXREG_PDPTR,
2974                   (unsigned long *)&vcpu->arch.regs_avail);
2975         __set_bit(VCPU_EXREG_PDPTR,
2976                   (unsigned long *)&vcpu->arch.regs_dirty);
2977 }
2978
2979 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2980
2981 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2982                                         unsigned long cr0,
2983                                         struct kvm_vcpu *vcpu)
2984 {
2985         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2986                 vmx_decache_cr3(vcpu);
2987         if (!(cr0 & X86_CR0_PG)) {
2988                 /* From paging/starting to nonpaging */
2989                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2990                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2991                              (CPU_BASED_CR3_LOAD_EXITING |
2992                               CPU_BASED_CR3_STORE_EXITING));
2993                 vcpu->arch.cr0 = cr0;
2994                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2995         } else if (!is_paging(vcpu)) {
2996                 /* From nonpaging to paging */
2997                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2998                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2999                              ~(CPU_BASED_CR3_LOAD_EXITING |
3000                                CPU_BASED_CR3_STORE_EXITING));
3001                 vcpu->arch.cr0 = cr0;
3002                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3003         }
3004
3005         if (!(cr0 & X86_CR0_WP))
3006                 *hw_cr0 &= ~X86_CR0_WP;
3007 }
3008
3009 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3010 {
3011         struct vcpu_vmx *vmx = to_vmx(vcpu);
3012         unsigned long hw_cr0;
3013
3014         if (enable_unrestricted_guest)
3015                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3016                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3017         else
3018                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3019
3020         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3021                 enter_pmode(vcpu);
3022
3023         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3024                 enter_rmode(vcpu);
3025
3026 #ifdef CONFIG_X86_64
3027         if (vcpu->arch.efer & EFER_LME) {
3028                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3029                         enter_lmode(vcpu);
3030                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3031                         exit_lmode(vcpu);
3032         }
3033 #endif
3034
3035         if (enable_ept)
3036                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3037
3038         if (!vcpu->fpu_active)
3039                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3040
3041         vmcs_writel(CR0_READ_SHADOW, cr0);
3042         vmcs_writel(GUEST_CR0, hw_cr0);
3043         vcpu->arch.cr0 = cr0;
3044         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3045 }
3046
3047 static u64 construct_eptp(unsigned long root_hpa)
3048 {
3049         u64 eptp;
3050
3051         /* TODO write the value reading from MSR */
3052         eptp = VMX_EPT_DEFAULT_MT |
3053                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3054         if (enable_ept_ad_bits)
3055                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3056         eptp |= (root_hpa & PAGE_MASK);
3057
3058         return eptp;
3059 }
3060
3061 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3062 {
3063         unsigned long guest_cr3;
3064         u64 eptp;
3065
3066         guest_cr3 = cr3;
3067         if (enable_ept) {
3068                 eptp = construct_eptp(cr3);
3069                 vmcs_write64(EPT_POINTER, eptp);
3070                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3071                         vcpu->kvm->arch.ept_identity_map_addr;
3072                 ept_load_pdptrs(vcpu);
3073         }
3074
3075         vmx_flush_tlb(vcpu);
3076         vmcs_writel(GUEST_CR3, guest_cr3);
3077 }
3078
3079 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3080 {
3081         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3082                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3083
3084         if (cr4 & X86_CR4_VMXE) {
3085                 /*
3086                  * To use VMXON (and later other VMX instructions), a guest
3087                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3088                  * So basically the check on whether to allow nested VMX
3089                  * is here.
3090                  */
3091                 if (!nested_vmx_allowed(vcpu))
3092                         return 1;
3093         } else if (to_vmx(vcpu)->nested.vmxon)
3094                 return 1;
3095
3096         vcpu->arch.cr4 = cr4;
3097         if (enable_ept) {
3098                 if (!is_paging(vcpu)) {
3099                         hw_cr4 &= ~X86_CR4_PAE;
3100                         hw_cr4 |= X86_CR4_PSE;
3101                 } else if (!(cr4 & X86_CR4_PAE)) {
3102                         hw_cr4 &= ~X86_CR4_PAE;
3103                 }
3104         }
3105
3106         vmcs_writel(CR4_READ_SHADOW, cr4);
3107         vmcs_writel(GUEST_CR4, hw_cr4);
3108         return 0;
3109 }
3110
3111 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3112                             struct kvm_segment *var, int seg)
3113 {
3114         struct vcpu_vmx *vmx = to_vmx(vcpu);
3115         struct kvm_save_segment *save;
3116         u32 ar;
3117
3118         if (vmx->rmode.vm86_active
3119             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3120                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3121                 || seg == VCPU_SREG_GS)
3122             && !emulate_invalid_guest_state) {
3123                 switch (seg) {
3124                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3125                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3126                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3127                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3128                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3129                 default: BUG();
3130                 }
3131                 var->selector = save->selector;
3132                 var->base = save->base;
3133                 var->limit = save->limit;
3134                 ar = save->ar;
3135                 if (seg == VCPU_SREG_TR
3136                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3137                         goto use_saved_rmode_seg;
3138         }
3139         var->base = vmx_read_guest_seg_base(vmx, seg);
3140         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3141         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3142         ar = vmx_read_guest_seg_ar(vmx, seg);
3143 use_saved_rmode_seg:
3144         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3145                 ar = 0;
3146         var->type = ar & 15;
3147         var->s = (ar >> 4) & 1;
3148         var->dpl = (ar >> 5) & 3;
3149         var->present = (ar >> 7) & 1;
3150         var->avl = (ar >> 12) & 1;
3151         var->l = (ar >> 13) & 1;
3152         var->db = (ar >> 14) & 1;
3153         var->g = (ar >> 15) & 1;
3154         var->unusable = (ar >> 16) & 1;
3155 }
3156
3157 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3158 {
3159         struct kvm_segment s;
3160
3161         if (to_vmx(vcpu)->rmode.vm86_active) {
3162                 vmx_get_segment(vcpu, &s, seg);
3163                 return s.base;
3164         }
3165         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3166 }
3167
3168 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3169 {
3170         if (!is_protmode(vcpu))
3171                 return 0;
3172
3173         if (!is_long_mode(vcpu)
3174             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3175                 return 3;
3176
3177         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3178 }
3179
3180 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3181 {
3182         struct vcpu_vmx *vmx = to_vmx(vcpu);
3183
3184         /*
3185          * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3186          * fail; use the cache instead.
3187          */
3188         if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3189                 return vmx->cpl;
3190         }
3191
3192         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3193                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3194                 vmx->cpl = __vmx_get_cpl(vcpu);
3195         }
3196
3197         return vmx->cpl;
3198 }
3199
3200
3201 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3202 {
3203         u32 ar;
3204
3205         if (var->unusable || !var->present)
3206                 ar = 1 << 16;
3207         else {
3208                 ar = var->type & 15;
3209                 ar |= (var->s & 1) << 4;
3210                 ar |= (var->dpl & 3) << 5;
3211                 ar |= (var->present & 1) << 7;
3212                 ar |= (var->avl & 1) << 12;
3213                 ar |= (var->l & 1) << 13;
3214                 ar |= (var->db & 1) << 14;
3215                 ar |= (var->g & 1) << 15;
3216         }
3217
3218         return ar;
3219 }
3220
3221 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3222                             struct kvm_segment *var, int seg)
3223 {
3224         struct vcpu_vmx *vmx = to_vmx(vcpu);
3225         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3226         u32 ar;
3227
3228         vmx_segment_cache_clear(vmx);
3229
3230         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3231                 vmcs_write16(sf->selector, var->selector);
3232                 vmx->rmode.tr.selector = var->selector;
3233                 vmx->rmode.tr.base = var->base;
3234                 vmx->rmode.tr.limit = var->limit;
3235                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3236                 return;
3237         }
3238         vmcs_writel(sf->base, var->base);
3239         vmcs_write32(sf->limit, var->limit);
3240         vmcs_write16(sf->selector, var->selector);
3241         if (vmx->rmode.vm86_active && var->s) {
3242                 /*
3243                  * Hack real-mode segments into vm86 compatibility.
3244                  */
3245                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3246                         vmcs_writel(sf->base, 0xf0000);
3247                 ar = 0xf3;
3248         } else
3249                 ar = vmx_segment_access_rights(var);
3250
3251         /*
3252          *   Fix the "Accessed" bit in AR field of segment registers for older
3253          * qemu binaries.
3254          *   IA32 arch specifies that at the time of processor reset the
3255          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3256          * is setting it to 0 in the userland code. This causes invalid guest
3257          * state vmexit when "unrestricted guest" mode is turned on.
3258          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3259          * tree. Newer qemu binaries with that qemu fix would not need this
3260          * kvm hack.
3261          */
3262         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3263                 ar |= 0x1; /* Accessed */
3264
3265         vmcs_write32(sf->ar_bytes, ar);
3266         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3267
3268         /*
3269          * Fix segments for real mode guest in hosts that don't have
3270          * "unrestricted_mode" or it was disabled.
3271          * This is done to allow migration of the guests from hosts with
3272          * unrestricted guest like Westmere to older host that don't have
3273          * unrestricted guest like Nehelem.
3274          */
3275         if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3276                 switch (seg) {
3277                 case VCPU_SREG_CS:
3278                         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3279                         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3280                         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3281                                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3282                         vmcs_write16(GUEST_CS_SELECTOR,
3283                                      vmcs_readl(GUEST_CS_BASE) >> 4);
3284                         break;
3285                 case VCPU_SREG_ES:
3286                         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3287                         break;
3288                 case VCPU_SREG_DS:
3289                         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3290                         break;
3291                 case VCPU_SREG_GS:
3292                         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3293                         break;
3294                 case VCPU_SREG_FS:
3295                         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3296                         break;
3297                 case VCPU_SREG_SS:
3298                         vmcs_write16(GUEST_SS_SELECTOR,
3299                                      vmcs_readl(GUEST_SS_BASE) >> 4);
3300                         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3301                         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3302                         break;
3303                 }
3304         }
3305 }
3306
3307 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3308 {
3309         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3310
3311         *db = (ar >> 14) & 1;
3312         *l = (ar >> 13) & 1;
3313 }
3314
3315 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3316 {
3317         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3318         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3319 }
3320
3321 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3322 {
3323         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3324         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3325 }
3326
3327 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3328 {
3329         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3330         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3331 }
3332
3333 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3334 {
3335         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3336         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3337 }
3338
3339 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3340 {
3341         struct kvm_segment var;
3342         u32 ar;
3343
3344         vmx_get_segment(vcpu, &var, seg);
3345         ar = vmx_segment_access_rights(&var);
3346
3347         if (var.base != (var.selector << 4))
3348                 return false;
3349         if (var.limit != 0xffff)
3350                 return false;
3351         if (ar != 0xf3)
3352                 return false;
3353
3354         return true;
3355 }
3356
3357 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3358 {
3359         struct kvm_segment cs;
3360         unsigned int cs_rpl;
3361
3362         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3363         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3364
3365         if (cs.unusable)
3366                 return false;
3367         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3368                 return false;
3369         if (!cs.s)
3370                 return false;
3371         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3372                 if (cs.dpl > cs_rpl)
3373                         return false;
3374         } else {
3375                 if (cs.dpl != cs_rpl)
3376                         return false;
3377         }
3378         if (!cs.present)
3379                 return false;
3380
3381         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3382         return true;
3383 }
3384
3385 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3386 {
3387         struct kvm_segment ss;
3388         unsigned int ss_rpl;
3389
3390         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3391         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3392
3393         if (ss.unusable)
3394                 return true;
3395         if (ss.type != 3 && ss.type != 7)
3396                 return false;
3397         if (!ss.s)
3398                 return false;
3399         if (ss.dpl != ss_rpl) /* DPL != RPL */
3400                 return false;
3401         if (!ss.present)
3402                 return false;
3403
3404         return true;
3405 }
3406
3407 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3408 {
3409         struct kvm_segment var;
3410         unsigned int rpl;
3411
3412         vmx_get_segment(vcpu, &var, seg);
3413         rpl = var.selector & SELECTOR_RPL_MASK;
3414
3415         if (var.unusable)
3416                 return true;
3417         if (!var.s)
3418                 return false;
3419         if (!var.present)
3420                 return false;
3421         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3422                 if (var.dpl < rpl) /* DPL < RPL */
3423                         return false;
3424         }
3425
3426         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3427          * rights flags
3428          */
3429         return true;
3430 }
3431
3432 static bool tr_valid(struct kvm_vcpu *vcpu)
3433 {
3434         struct kvm_segment tr;
3435
3436         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3437
3438         if (tr.unusable)
3439                 return false;
3440         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3441                 return false;
3442         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3443                 return false;
3444         if (!tr.present)
3445                 return false;
3446
3447         return true;
3448 }
3449
3450 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3451 {
3452         struct kvm_segment ldtr;
3453
3454         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3455
3456         if (ldtr.unusable)
3457                 return true;
3458         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3459                 return false;
3460         if (ldtr.type != 2)
3461                 return false;
3462         if (!ldtr.present)
3463                 return false;
3464
3465         return true;
3466 }
3467
3468 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3469 {
3470         struct kvm_segment cs, ss;
3471
3472         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3473         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3474
3475         return ((cs.selector & SELECTOR_RPL_MASK) ==
3476                  (ss.selector & SELECTOR_RPL_MASK));
3477 }
3478
3479 /*
3480  * Check if guest state is valid. Returns true if valid, false if
3481  * not.
3482  * We assume that registers are always usable
3483  */
3484 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3485 {
3486         /* real mode guest state checks */
3487         if (!is_protmode(vcpu)) {
3488                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3489                         return false;
3490                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3491                         return false;
3492                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3493                         return false;
3494                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3495                         return false;
3496                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3497                         return false;
3498                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3499                         return false;
3500         } else {
3501         /* protected mode guest state checks */
3502                 if (!cs_ss_rpl_check(vcpu))
3503                         return false;
3504                 if (!code_segment_valid(vcpu))
3505                         return false;
3506                 if (!stack_segment_valid(vcpu))
3507                         return false;
3508                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3509                         return false;
3510                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3511                         return false;
3512                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3513                         return false;
3514                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3515                         return false;
3516                 if (!tr_valid(vcpu))
3517                         return false;
3518                 if (!ldtr_valid(vcpu))
3519                         return false;
3520         }
3521         /* TODO:
3522          * - Add checks on RIP
3523          * - Add checks on RFLAGS
3524          */
3525
3526         return true;
3527 }
3528
3529 static int init_rmode_tss(struct kvm *kvm)
3530 {
3531         gfn_t fn;
3532         u16 data = 0;
3533         int r, idx, ret = 0;
3534
3535         idx = srcu_read_lock(&kvm->srcu);
3536         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3537         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3538         if (r < 0)
3539                 goto out;
3540         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3541         r = kvm_write_guest_page(kvm, fn++, &data,
3542                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3543         if (r < 0)
3544                 goto out;
3545         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3546         if (r < 0)
3547                 goto out;
3548         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3549         if (r < 0)
3550                 goto out;
3551         data = ~0;
3552         r = kvm_write_guest_page(kvm, fn, &data,
3553                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3554                                  sizeof(u8));
3555         if (r < 0)
3556                 goto out;
3557
3558         ret = 1;
3559 out:
3560         srcu_read_unlock(&kvm->srcu, idx);
3561         return ret;
3562 }
3563
3564 static int init_rmode_identity_map(struct kvm *kvm)
3565 {
3566         int i, idx, r, ret;
3567         pfn_t identity_map_pfn;
3568         u32 tmp;
3569
3570         if (!enable_ept)
3571                 return 1;
3572         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3573                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3574                         "haven't been allocated!\n");
3575                 return 0;
3576         }
3577         if (likely(kvm->arch.ept_identity_pagetable_done))
3578                 return 1;
3579         ret = 0;
3580         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3581         idx = srcu_read_lock(&kvm->srcu);
3582         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3583         if (r < 0)
3584                 goto out;
3585         /* Set up identity-mapping pagetable for EPT in real mode */
3586         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3587                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3588                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3589                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3590                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3591                 if (r < 0)
3592                         goto out;
3593         }
3594         kvm->arch.ept_identity_pagetable_done = true;
3595         ret = 1;
3596 out:
3597         srcu_read_unlock(&kvm->srcu, idx);
3598         return ret;
3599 }
3600
3601 static void seg_setup(int seg)
3602 {
3603         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3604         unsigned int ar;
3605
3606         vmcs_write16(sf->selector, 0);
3607         vmcs_writel(sf->base, 0);
3608         vmcs_write32(sf->limit, 0xffff);
3609         if (enable_unrestricted_guest) {
3610                 ar = 0x93;
3611                 if (seg == VCPU_SREG_CS)
3612                         ar |= 0x08; /* code segment */
3613         } else
3614                 ar = 0xf3;
3615
3616         vmcs_write32(sf->ar_bytes, ar);
3617 }
3618
3619 static int alloc_apic_access_page(struct kvm *kvm)
3620 {
3621         struct kvm_userspace_memory_region kvm_userspace_mem;
3622         int r = 0;
3623
3624         mutex_lock(&kvm->slots_lock);
3625         if (kvm->arch.apic_access_page)
3626                 goto out;
3627         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3628         kvm_userspace_mem.flags = 0;
3629         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3630         kvm_userspace_mem.memory_size = PAGE_SIZE;
3631         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3632         if (r)
3633                 goto out;
3634
3635         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3636 out:
3637         mutex_unlock(&kvm->slots_lock);
3638         return r;
3639 }
3640
3641 static int alloc_identity_pagetable(struct kvm *kvm)
3642 {
3643         struct kvm_userspace_memory_region kvm_userspace_mem;
3644         int r = 0;
3645
3646         mutex_lock(&kvm->slots_lock);
3647         if (kvm->arch.ept_identity_pagetable)
3648                 goto out;
3649         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3650         kvm_userspace_mem.flags = 0;
3651         kvm_userspace_mem.guest_phys_addr =
3652                 kvm->arch.ept_identity_map_addr;
3653         kvm_userspace_mem.memory_size = PAGE_SIZE;
3654         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3655         if (r)
3656                 goto out;
3657
3658         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3659                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3660 out:
3661         mutex_unlock(&kvm->slots_lock);
3662         return r;
3663 }
3664
3665 static void allocate_vpid(struct vcpu_vmx *vmx)
3666 {
3667         int vpid;
3668
3669         vmx->vpid = 0;
3670         if (!enable_vpid)
3671                 return;
3672         spin_lock(&vmx_vpid_lock);
3673         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3674         if (vpid < VMX_NR_VPIDS) {
3675                 vmx->vpid = vpid;
3676                 __set_bit(vpid, vmx_vpid_bitmap);
3677         }
3678         spin_unlock(&vmx_vpid_lock);
3679 }
3680
3681 static void free_vpid(struct vcpu_vmx *vmx)
3682 {
3683         if (!enable_vpid)
3684                 return;
3685         spin_lock(&vmx_vpid_lock);
3686         if (vmx->vpid != 0)
3687                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3688         spin_unlock(&vmx_vpid_lock);
3689 }
3690
3691 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3692 {
3693         int f = sizeof(unsigned long);
3694
3695         if (!cpu_has_vmx_msr_bitmap())
3696                 return;
3697
3698         /*
3699          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3700          * have the write-low and read-high bitmap offsets the wrong way round.
3701          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3702          */
3703         if (msr <= 0x1fff) {
3704                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3705                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3706         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3707                 msr &= 0x1fff;
3708                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3709                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3710         }
3711 }
3712
3713 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3714 {
3715         if (!longmode_only)
3716                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3717         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3718 }
3719
3720 /*
3721  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3722  * will not change in the lifetime of the guest.
3723  * Note that host-state that does change is set elsewhere. E.g., host-state
3724  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3725  */
3726 static void vmx_set_constant_host_state(void)
3727 {
3728         u32 low32, high32;
3729         unsigned long tmpl;
3730         struct desc_ptr dt;
3731
3732         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3733         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3734         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3735
3736         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3737 #ifdef CONFIG_X86_64
3738         /*
3739          * Load null selectors, so we can avoid reloading them in
3740          * __vmx_load_host_state(), in case userspace uses the null selectors
3741          * too (the expected case).
3742          */
3743         vmcs_write16(HOST_DS_SELECTOR, 0);
3744         vmcs_write16(HOST_ES_SELECTOR, 0);
3745 #else
3746         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3747         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3748 #endif
3749         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3750         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3751
3752         native_store_idt(&dt);
3753         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3754
3755         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3756         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3757
3758         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3759         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3760         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3761         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3762
3763         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3764                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3765                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3766         }
3767 }
3768
3769 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3770 {
3771         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3772         if (enable_ept)
3773                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3774         if (is_guest_mode(&vmx->vcpu))
3775                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3776                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3777         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3778 }
3779
3780 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3781 {
3782         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3783         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3784                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3785 #ifdef CONFIG_X86_64
3786                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3787                                 CPU_BASED_CR8_LOAD_EXITING;
3788 #endif
3789         }
3790         if (!enable_ept)
3791                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3792                                 CPU_BASED_CR3_LOAD_EXITING  |
3793                                 CPU_BASED_INVLPG_EXITING;
3794         return exec_control;
3795 }
3796
3797 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3798 {
3799         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3800         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3801                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3802         if (vmx->vpid == 0)
3803                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3804         if (!enable_ept) {
3805                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3806                 enable_unrestricted_guest = 0;
3807                 /* Enable INVPCID for non-ept guests may cause performance regression. */
3808                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3809         }
3810         if (!enable_unrestricted_guest)
3811                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3812         if (!ple_gap)
3813                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3814         return exec_control;
3815 }
3816
3817 static void ept_set_mmio_spte_mask(void)
3818 {
3819         /*
3820          * EPT Misconfigurations can be generated if the value of bits 2:0
3821          * of an EPT paging-structure entry is 110b (write/execute).
3822          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3823          * spte.
3824          */
3825         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3826 }
3827
3828 /*
3829  * Sets up the vmcs for emulated real mode.
3830  */
3831 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3832 {
3833 #ifdef CONFIG_X86_64
3834         unsigned long a;
3835 #endif
3836         int i;
3837
3838         /* I/O */
3839         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3840         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3841
3842         if (cpu_has_vmx_msr_bitmap())
3843                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3844
3845         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3846
3847         /* Control */
3848         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3849                 vmcs_config.pin_based_exec_ctrl);
3850
3851         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3852
3853         if (cpu_has_secondary_exec_ctrls()) {
3854                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3855                                 vmx_secondary_exec_control(vmx));
3856         }
3857
3858         if (ple_gap) {
3859                 vmcs_write32(PLE_GAP, ple_gap);
3860                 vmcs_write32(PLE_WINDOW, ple_window);
3861         }
3862
3863         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3864         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3865         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3866
3867         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3868         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3869         vmx_set_constant_host_state();
3870 #ifdef CONFIG_X86_64
3871         rdmsrl(MSR_FS_BASE, a);
3872         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3873         rdmsrl(MSR_GS_BASE, a);
3874         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3875 #else
3876         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3877         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3878 #endif
3879
3880         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3881         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3882         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3883         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3884         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3885
3886         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3887                 u32 msr_low, msr_high;
3888                 u64 host_pat;
3889                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3890                 host_pat = msr_low | ((u64) msr_high << 32);
3891                 /* Write the default value follow host pat */
3892                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3893                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3894                 vmx->vcpu.arch.pat = host_pat;
3895         }
3896
3897         for (i = 0; i < NR_VMX_MSR; ++i) {
3898                 u32 index = vmx_msr_index[i];
3899                 u32 data_low, data_high;
3900                 int j = vmx->nmsrs;
3901
3902                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3903                         continue;
3904                 if (wrmsr_safe(index, data_low, data_high) < 0)
3905                         continue;
3906                 vmx->guest_msrs[j].index = i;
3907                 vmx->guest_msrs[j].data = 0;
3908                 vmx->guest_msrs[j].mask = -1ull;
3909                 ++vmx->nmsrs;
3910         }
3911
3912         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3913
3914         /* 22.2.1, 20.8.1 */
3915         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3916
3917         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3918         set_cr4_guest_host_mask(vmx);
3919
3920         kvm_write_tsc(&vmx->vcpu, 0);
3921
3922         return 0;
3923 }
3924
3925 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3926 {
3927         struct vcpu_vmx *vmx = to_vmx(vcpu);
3928         u64 msr;
3929         int ret;
3930
3931         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3932
3933         vmx->rmode.vm86_active = 0;
3934
3935         vmx->soft_vnmi_blocked = 0;
3936
3937         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3938         kvm_set_cr8(&vmx->vcpu, 0);
3939         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3940         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3941                 msr |= MSR_IA32_APICBASE_BSP;
3942         kvm_set_apic_base(&vmx->vcpu, msr);
3943
3944         ret = fx_init(&vmx->vcpu);
3945         if (ret != 0)
3946                 goto out;
3947
3948         vmx_segment_cache_clear(vmx);
3949
3950         seg_setup(VCPU_SREG_CS);
3951         /*
3952          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3953          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3954          */
3955         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3956                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3957                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3958         } else {
3959                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3960                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3961         }
3962
3963         seg_setup(VCPU_SREG_DS);
3964         seg_setup(VCPU_SREG_ES);
3965         seg_setup(VCPU_SREG_FS);
3966         seg_setup(VCPU_SREG_GS);
3967         seg_setup(VCPU_SREG_SS);
3968
3969         vmcs_write16(GUEST_TR_SELECTOR, 0);
3970         vmcs_writel(GUEST_TR_BASE, 0);
3971         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3972         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3973
3974         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3975         vmcs_writel(GUEST_LDTR_BASE, 0);
3976         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3977         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3978
3979         vmcs_write32(GUEST_SYSENTER_CS, 0);
3980         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3981         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3982
3983         vmcs_writel(GUEST_RFLAGS, 0x02);
3984         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3985                 kvm_rip_write(vcpu, 0xfff0);
3986         else
3987                 kvm_rip_write(vcpu, 0);
3988         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3989
3990         vmcs_writel(GUEST_DR7, 0x400);
3991
3992         vmcs_writel(GUEST_GDTR_BASE, 0);
3993         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3994
3995         vmcs_writel(GUEST_IDTR_BASE, 0);
3996         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3997
3998         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3999         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4000         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4001
4002         /* Special registers */
4003         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4004
4005         setup_msrs(vmx);
4006
4007         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4008
4009         if (cpu_has_vmx_tpr_shadow()) {
4010                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4011                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4012                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4013                                      __pa(vmx->vcpu.arch.apic->regs));
4014                 vmcs_write32(TPR_THRESHOLD, 0);
4015         }
4016
4017         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4018                 vmcs_write64(APIC_ACCESS_ADDR,
4019                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4020
4021         if (vmx->vpid != 0)
4022                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4023
4024         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4025         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4026         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4027         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4028         vmx_set_cr4(&vmx->vcpu, 0);
4029         vmx_set_efer(&vmx->vcpu, 0);
4030         vmx_fpu_activate(&vmx->vcpu);
4031         update_exception_bitmap(&vmx->vcpu);
4032
4033         vpid_sync_context(vmx);
4034
4035         ret = 0;
4036
4037         /* HACK: Don't enable emulation on guest boot/reset */
4038         vmx->emulation_required = 0;
4039
4040 out:
4041         return ret;
4042 }
4043
4044 /*
4045  * In nested virtualization, check if L1 asked to exit on external interrupts.
4046  * For most existing hypervisors, this will always return true.
4047  */
4048 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4049 {
4050         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4051                 PIN_BASED_EXT_INTR_MASK;
4052 }
4053
4054 static void enable_irq_window(struct kvm_vcpu *vcpu)
4055 {
4056         u32 cpu_based_vm_exec_control;
4057         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4058                 /*
4059                  * We get here if vmx_interrupt_allowed() said we can't
4060                  * inject to L1 now because L2 must run. Ask L2 to exit
4061                  * right after entry, so we can inject to L1 more promptly.
4062                  */
4063                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4064                 return;
4065         }
4066
4067         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4068         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4069         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4070 }
4071
4072 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4073 {
4074         u32 cpu_based_vm_exec_control;
4075
4076         if (!cpu_has_virtual_nmis()) {
4077                 enable_irq_window(vcpu);
4078                 return;
4079         }
4080
4081         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4082                 enable_irq_window(vcpu);
4083                 return;
4084         }
4085         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4086         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4087         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4088 }
4089
4090 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4091 {
4092         struct vcpu_vmx *vmx = to_vmx(vcpu);
4093         uint32_t intr;
4094         int irq = vcpu->arch.interrupt.nr;
4095
4096         trace_kvm_inj_virq(irq);
4097
4098         ++vcpu->stat.irq_injections;
4099         if (vmx->rmode.vm86_active) {
4100                 int inc_eip = 0;
4101                 if (vcpu->arch.interrupt.soft)
4102                         inc_eip = vcpu->arch.event_exit_inst_len;
4103                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4104                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4105                 return;
4106         }
4107         intr = irq | INTR_INFO_VALID_MASK;
4108         if (vcpu->arch.interrupt.soft) {
4109                 intr |= INTR_TYPE_SOFT_INTR;
4110                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4111                              vmx->vcpu.arch.event_exit_inst_len);
4112         } else
4113                 intr |= INTR_TYPE_EXT_INTR;
4114         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4115 }
4116
4117 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4118 {
4119         struct vcpu_vmx *vmx = to_vmx(vcpu);
4120
4121         if (is_guest_mode(vcpu))
4122                 return;
4123
4124         if (!cpu_has_virtual_nmis()) {
4125                 /*
4126                  * Tracking the NMI-blocked state in software is built upon
4127                  * finding the next open IRQ window. This, in turn, depends on
4128                  * well-behaving guests: They have to keep IRQs disabled at
4129                  * least as long as the NMI handler runs. Otherwise we may
4130                  * cause NMI nesting, maybe breaking the guest. But as this is
4131                  * highly unlikely, we can live with the residual risk.
4132                  */
4133                 vmx->soft_vnmi_blocked = 1;
4134                 vmx->vnmi_blocked_time = 0;
4135         }
4136
4137         ++vcpu->stat.nmi_injections;
4138         vmx->nmi_known_unmasked = false;
4139         if (vmx->rmode.vm86_active) {
4140                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4141                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4142                 return;
4143         }
4144         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4145                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4146 }
4147
4148 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4149 {
4150         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4151                 return 0;
4152
4153         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4154                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4155                    | GUEST_INTR_STATE_NMI));
4156 }
4157
4158 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4159 {
4160         if (!cpu_has_virtual_nmis())
4161                 return to_vmx(vcpu)->soft_vnmi_blocked;
4162         if (to_vmx(vcpu)->nmi_known_unmasked)
4163                 return false;
4164         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4165 }
4166
4167 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4168 {
4169         struct vcpu_vmx *vmx = to_vmx(vcpu);
4170
4171         if (!cpu_has_virtual_nmis()) {
4172                 if (vmx->soft_vnmi_blocked != masked) {
4173                         vmx->soft_vnmi_blocked = masked;
4174                         vmx->vnmi_blocked_time = 0;
4175                 }
4176         } else {
4177                 vmx->nmi_known_unmasked = !masked;
4178                 if (masked)
4179                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4180                                       GUEST_INTR_STATE_NMI);
4181                 else
4182                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4183                                         GUEST_INTR_STATE_NMI);
4184         }
4185 }
4186
4187 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4188 {
4189         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4190                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4191                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4192                     (vmcs12->idt_vectoring_info_field &
4193                      VECTORING_INFO_VALID_MASK))
4194                         return 0;
4195                 nested_vmx_vmexit(vcpu);
4196                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4197                 vmcs12->vm_exit_intr_info = 0;
4198                 /* fall through to normal code, but now in L1, not L2 */
4199         }
4200
4201         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4202                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4203                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4204 }
4205
4206 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4207 {
4208         int ret;
4209         struct kvm_userspace_memory_region tss_mem = {
4210                 .slot = TSS_PRIVATE_MEMSLOT,
4211                 .guest_phys_addr = addr,
4212                 .memory_size = PAGE_SIZE * 3,
4213                 .flags = 0,
4214         };
4215
4216         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4217         if (ret)
4218                 return ret;
4219         kvm->arch.tss_addr = addr;
4220         if (!init_rmode_tss(kvm))
4221                 return  -ENOMEM;
4222
4223         return 0;
4224 }
4225
4226 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4227                                   int vec, u32 err_code)
4228 {
4229         /*
4230          * Instruction with address size override prefix opcode 0x67
4231          * Cause the #SS fault with 0 error code in VM86 mode.
4232          */
4233         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4234                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4235                         return 1;
4236         /*
4237          * Forward all other exceptions that are valid in real mode.
4238          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4239          *        the required debugging infrastructure rework.
4240          */
4241         switch (vec) {
4242         case DB_VECTOR:
4243                 if (vcpu->guest_debug &
4244                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4245                         return 0;
4246                 kvm_queue_exception(vcpu, vec);
4247                 return 1;
4248         case BP_VECTOR:
4249                 /*
4250                  * Update instruction length as we may reinject the exception
4251                  * from user space while in guest debugging mode.
4252                  */
4253                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4254                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4255                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4256                         return 0;
4257                 /* fall through */
4258         case DE_VECTOR:
4259         case OF_VECTOR:
4260         case BR_VECTOR:
4261         case UD_VECTOR:
4262         case DF_VECTOR:
4263         case SS_VECTOR:
4264         case GP_VECTOR:
4265         case MF_VECTOR:
4266                 kvm_queue_exception(vcpu, vec);
4267                 return 1;
4268         }
4269         return 0;
4270 }
4271
4272 /*
4273  * Trigger machine check on the host. We assume all the MSRs are already set up
4274  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4275  * We pass a fake environment to the machine check handler because we want
4276  * the guest to be always treated like user space, no matter what context
4277  * it used internally.
4278  */
4279 static void kvm_machine_check(void)
4280 {
4281 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4282         struct pt_regs regs = {
4283                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4284                 .flags = X86_EFLAGS_IF,
4285         };
4286
4287         do_machine_check(&regs, 0);
4288 #endif
4289 }
4290
4291 static int handle_machine_check(struct kvm_vcpu *vcpu)
4292 {
4293         /* already handled by vcpu_run */
4294         return 1;
4295 }
4296
4297 static int handle_exception(struct kvm_vcpu *vcpu)
4298 {
4299         struct vcpu_vmx *vmx = to_vmx(vcpu);
4300         struct kvm_run *kvm_run = vcpu->run;
4301         u32 intr_info, ex_no, error_code;
4302         unsigned long cr2, rip, dr6;
4303         u32 vect_info;
4304         enum emulation_result er;
4305
4306         vect_info = vmx->idt_vectoring_info;
4307         intr_info = vmx->exit_intr_info;
4308
4309         if (is_machine_check(intr_info))
4310                 return handle_machine_check(vcpu);
4311
4312         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4313             !is_page_fault(intr_info)) {
4314                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4315                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4316                 vcpu->run->internal.ndata = 2;
4317                 vcpu->run->internal.data[0] = vect_info;
4318                 vcpu->run->internal.data[1] = intr_info;
4319                 return 0;
4320         }
4321
4322         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4323                 return 1;  /* already handled by vmx_vcpu_run() */
4324
4325         if (is_no_device(intr_info)) {
4326                 vmx_fpu_activate(vcpu);
4327                 return 1;
4328         }
4329
4330         if (is_invalid_opcode(intr_info)) {
4331                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4332                 if (er != EMULATE_DONE)
4333                         kvm_queue_exception(vcpu, UD_VECTOR);
4334                 return 1;
4335         }
4336
4337         error_code = 0;
4338         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4339                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4340         if (is_page_fault(intr_info)) {
4341                 /* EPT won't cause page fault directly */
4342                 BUG_ON(enable_ept);
4343                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4344                 trace_kvm_page_fault(cr2, error_code);
4345
4346                 if (kvm_event_needs_reinjection(vcpu))
4347                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4348                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4349         }
4350
4351         if (vmx->rmode.vm86_active &&
4352             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4353                                                                 error_code)) {
4354                 if (vcpu->arch.halt_request) {
4355                         vcpu->arch.halt_request = 0;
4356                         return kvm_emulate_halt(vcpu);
4357                 }
4358                 return 1;
4359         }
4360
4361         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4362         switch (ex_no) {
4363         case DB_VECTOR:
4364                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4365                 if (!(vcpu->guest_debug &
4366                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4367                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4368                         kvm_queue_exception(vcpu, DB_VECTOR);
4369                         return 1;
4370                 }
4371                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4372                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4373                 /* fall through */
4374         case BP_VECTOR:
4375                 /*
4376                  * Update instruction length as we may reinject #BP from
4377                  * user space while in guest debugging mode. Reading it for
4378                  * #DB as well causes no harm, it is not used in that case.
4379                  */
4380                 vmx->vcpu.arch.event_exit_inst_len =
4381                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4382                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4383                 rip = kvm_rip_read(vcpu);
4384                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4385                 kvm_run->debug.arch.exception = ex_no;
4386                 break;
4387         default:
4388                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4389                 kvm_run->ex.exception = ex_no;
4390                 kvm_run->ex.error_code = error_code;
4391                 break;
4392         }
4393         return 0;
4394 }
4395
4396 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4397 {
4398         ++vcpu->stat.irq_exits;
4399         return 1;
4400 }
4401
4402 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4403 {
4404         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4405         return 0;
4406 }
4407
4408 static int handle_io(struct kvm_vcpu *vcpu)
4409 {
4410         unsigned long exit_qualification;
4411         int size, in, string;
4412         unsigned port;
4413
4414         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4415         string = (exit_qualification & 16) != 0;
4416         in = (exit_qualification & 8) != 0;
4417
4418         ++vcpu->stat.io_exits;
4419
4420         if (string || in)
4421                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4422
4423         port = exit_qualification >> 16;
4424         size = (exit_qualification & 7) + 1;
4425         skip_emulated_instruction(vcpu);
4426
4427         return kvm_fast_pio_out(vcpu, size, port);
4428 }
4429
4430 static void
4431 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4432 {
4433         /*
4434          * Patch in the VMCALL instruction:
4435          */
4436         hypercall[0] = 0x0f;
4437         hypercall[1] = 0x01;
4438         hypercall[2] = 0xc1;
4439 }
4440
4441 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4442 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4443 {
4444         if (to_vmx(vcpu)->nested.vmxon &&
4445             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4446                 return 1;
4447
4448         if (is_guest_mode(vcpu)) {
4449                 /*
4450                  * We get here when L2 changed cr0 in a way that did not change
4451                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4452                  * but did change L0 shadowed bits. This can currently happen
4453                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4454                  * loading) while pretending to allow the guest to change it.
4455                  */
4456                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4457                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4458                         return 1;
4459                 vmcs_writel(CR0_READ_SHADOW, val);
4460                 return 0;
4461         } else
4462                 return kvm_set_cr0(vcpu, val);
4463 }
4464
4465 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4466 {
4467         if (is_guest_mode(vcpu)) {
4468                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4469                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4470                         return 1;
4471                 vmcs_writel(CR4_READ_SHADOW, val);
4472                 return 0;
4473         } else
4474                 return kvm_set_cr4(vcpu, val);
4475 }
4476
4477 /* called to set cr0 as approriate for clts instruction exit. */
4478 static void handle_clts(struct kvm_vcpu *vcpu)
4479 {
4480         if (is_guest_mode(vcpu)) {
4481                 /*
4482                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4483                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4484                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4485                  */
4486                 vmcs_writel(CR0_READ_SHADOW,
4487                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4488                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4489         } else
4490                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4491 }
4492
4493 static int handle_cr(struct kvm_vcpu *vcpu)
4494 {
4495         unsigned long exit_qualification, val;
4496         int cr;
4497         int reg;
4498         int err;
4499
4500         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4501         cr = exit_qualification & 15;
4502         reg = (exit_qualification >> 8) & 15;
4503         switch ((exit_qualification >> 4) & 3) {
4504         case 0: /* mov to cr */
4505                 val = kvm_register_read(vcpu, reg);
4506                 trace_kvm_cr_write(cr, val);
4507                 switch (cr) {
4508                 case 0:
4509                         err = handle_set_cr0(vcpu, val);
4510                         kvm_complete_insn_gp(vcpu, err);
4511                         return 1;
4512                 case 3:
4513                         err = kvm_set_cr3(vcpu, val);
4514                         kvm_complete_insn_gp(vcpu, err);
4515                         return 1;
4516                 case 4:
4517                         err = handle_set_cr4(vcpu, val);
4518                         kvm_complete_insn_gp(vcpu, err);
4519                         return 1;
4520                 case 8: {
4521                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4522                                 u8 cr8 = kvm_register_read(vcpu, reg);
4523                                 err = kvm_set_cr8(vcpu, cr8);
4524                                 kvm_complete_insn_gp(vcpu, err);
4525                                 if (irqchip_in_kernel(vcpu->kvm))
4526                                         return 1;
4527                                 if (cr8_prev <= cr8)
4528                                         return 1;
4529                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4530                                 return 0;
4531                         }
4532                 };
4533                 break;
4534         case 2: /* clts */
4535                 handle_clts(vcpu);
4536                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4537                 skip_emulated_instruction(vcpu);
4538                 vmx_fpu_activate(vcpu);
4539                 return 1;
4540         case 1: /*mov from cr*/
4541                 switch (cr) {
4542                 case 3:
4543                         val = kvm_read_cr3(vcpu);
4544                         kvm_register_write(vcpu, reg, val);
4545                         trace_kvm_cr_read(cr, val);
4546                         skip_emulated_instruction(vcpu);
4547                         return 1;
4548                 case 8:
4549                         val = kvm_get_cr8(vcpu);
4550                         kvm_register_write(vcpu, reg, val);
4551                         trace_kvm_cr_read(cr, val);
4552                         skip_emulated_instruction(vcpu);
4553                         return 1;
4554                 }
4555                 break;
4556         case 3: /* lmsw */
4557                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4558                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4559                 kvm_lmsw(vcpu, val);
4560
4561                 skip_emulated_instruction(vcpu);
4562                 return 1;
4563         default:
4564                 break;
4565         }
4566         vcpu->run->exit_reason = 0;
4567         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4568                (int)(exit_qualification >> 4) & 3, cr);
4569         return 0;
4570 }
4571
4572 static int handle_dr(struct kvm_vcpu *vcpu)
4573 {
4574         unsigned long exit_qualification;
4575         int dr, reg;
4576
4577         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4578         if (!kvm_require_cpl(vcpu, 0))
4579                 return 1;
4580         dr = vmcs_readl(GUEST_DR7);
4581         if (dr & DR7_GD) {
4582                 /*
4583                  * As the vm-exit takes precedence over the debug trap, we
4584                  * need to emulate the latter, either for the host or the
4585                  * guest debugging itself.
4586                  */
4587                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4588                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4589                         vcpu->run->debug.arch.dr7 = dr;
4590                         vcpu->run->debug.arch.pc =
4591                                 vmcs_readl(GUEST_CS_BASE) +
4592                                 vmcs_readl(GUEST_RIP);
4593                         vcpu->run->debug.arch.exception = DB_VECTOR;
4594                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4595                         return 0;
4596                 } else {
4597                         vcpu->arch.dr7 &= ~DR7_GD;
4598                         vcpu->arch.dr6 |= DR6_BD;
4599                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4600                         kvm_queue_exception(vcpu, DB_VECTOR);
4601                         return 1;
4602                 }
4603         }
4604
4605         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4606         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4607         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4608         if (exit_qualification & TYPE_MOV_FROM_DR) {
4609                 unsigned long val;
4610                 if (!kvm_get_dr(vcpu, dr, &val))
4611                         kvm_register_write(vcpu, reg, val);
4612         } else
4613                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4614         skip_emulated_instruction(vcpu);
4615         return 1;
4616 }
4617
4618 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4619 {
4620         vmcs_writel(GUEST_DR7, val);
4621 }
4622
4623 static int handle_cpuid(struct kvm_vcpu *vcpu)
4624 {
4625         kvm_emulate_cpuid(vcpu);
4626         return 1;
4627 }
4628
4629 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4630 {
4631         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4632         u64 data;
4633
4634         if (vmx_get_msr(vcpu, ecx, &data)) {
4635                 trace_kvm_msr_read_ex(ecx);
4636                 kvm_inject_gp(vcpu, 0);
4637                 return 1;
4638         }
4639
4640         trace_kvm_msr_read(ecx, data);
4641
4642         /* FIXME: handling of bits 32:63 of rax, rdx */
4643         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4644         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4645         skip_emulated_instruction(vcpu);
4646         return 1;
4647 }
4648
4649 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4650 {
4651         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4652         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4653                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4654
4655         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4656                 trace_kvm_msr_write_ex(ecx, data);
4657                 kvm_inject_gp(vcpu, 0);
4658                 return 1;
4659         }
4660
4661         trace_kvm_msr_write(ecx, data);
4662         skip_emulated_instruction(vcpu);
4663         return 1;
4664 }
4665
4666 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4667 {
4668         kvm_make_request(KVM_REQ_EVENT, vcpu);
4669         return 1;
4670 }
4671
4672 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4673 {
4674         u32 cpu_based_vm_exec_control;
4675
4676         /* clear pending irq */
4677         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4678         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4679         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4680
4681         kvm_make_request(KVM_REQ_EVENT, vcpu);
4682
4683         ++vcpu->stat.irq_window_exits;
4684
4685         /*
4686          * If the user space waits to inject interrupts, exit as soon as
4687          * possible
4688          */
4689         if (!irqchip_in_kernel(vcpu->kvm) &&
4690             vcpu->run->request_interrupt_window &&
4691             !kvm_cpu_has_interrupt(vcpu)) {
4692                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4693                 return 0;
4694         }
4695         return 1;
4696 }
4697
4698 static int handle_halt(struct kvm_vcpu *vcpu)
4699 {
4700         skip_emulated_instruction(vcpu);
4701         return kvm_emulate_halt(vcpu);
4702 }
4703
4704 static int handle_vmcall(struct kvm_vcpu *vcpu)
4705 {
4706         skip_emulated_instruction(vcpu);
4707         kvm_emulate_hypercall(vcpu);
4708         return 1;
4709 }
4710
4711 static int handle_invd(struct kvm_vcpu *vcpu)
4712 {
4713         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4714 }
4715
4716 static int handle_invlpg(struct kvm_vcpu *vcpu)
4717 {
4718         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4719
4720         kvm_mmu_invlpg(vcpu, exit_qualification);
4721         skip_emulated_instruction(vcpu);
4722         return 1;
4723 }
4724
4725 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4726 {
4727         int err;
4728
4729         err = kvm_rdpmc(vcpu);
4730         kvm_complete_insn_gp(vcpu, err);
4731
4732         return 1;
4733 }
4734
4735 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4736 {
4737         skip_emulated_instruction(vcpu);
4738         kvm_emulate_wbinvd(vcpu);
4739         return 1;
4740 }
4741
4742 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4743 {
4744         u64 new_bv = kvm_read_edx_eax(vcpu);
4745         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4746
4747         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4748                 skip_emulated_instruction(vcpu);
4749         return 1;
4750 }
4751
4752 static int handle_apic_access(struct kvm_vcpu *vcpu)
4753 {
4754         if (likely(fasteoi)) {
4755                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4756                 int access_type, offset;
4757
4758                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4759                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4760                 /*
4761                  * Sane guest uses MOV to write EOI, with written value
4762                  * not cared. So make a short-circuit here by avoiding
4763                  * heavy instruction emulation.
4764                  */
4765                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4766                     (offset == APIC_EOI)) {
4767                         kvm_lapic_set_eoi(vcpu);
4768                         skip_emulated_instruction(vcpu);
4769                         return 1;
4770                 }
4771         }
4772         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4773 }
4774
4775 static int handle_task_switch(struct kvm_vcpu *vcpu)
4776 {
4777         struct vcpu_vmx *vmx = to_vmx(vcpu);
4778         unsigned long exit_qualification;
4779         bool has_error_code = false;
4780         u32 error_code = 0;
4781         u16 tss_selector;
4782         int reason, type, idt_v, idt_index;
4783
4784         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4785         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4786         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4787
4788         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4789
4790         reason = (u32)exit_qualification >> 30;
4791         if (reason == TASK_SWITCH_GATE && idt_v) {
4792                 switch (type) {
4793                 case INTR_TYPE_NMI_INTR:
4794                         vcpu->arch.nmi_injected = false;
4795                         vmx_set_nmi_mask(vcpu, true);
4796                         break;
4797                 case INTR_TYPE_EXT_INTR:
4798                 case INTR_TYPE_SOFT_INTR:
4799                         kvm_clear_interrupt_queue(vcpu);
4800                         break;
4801                 case INTR_TYPE_HARD_EXCEPTION:
4802                         if (vmx->idt_vectoring_info &
4803                             VECTORING_INFO_DELIVER_CODE_MASK) {
4804                                 has_error_code = true;
4805                                 error_code =
4806                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4807                         }
4808                         /* fall through */
4809                 case INTR_TYPE_SOFT_EXCEPTION:
4810                         kvm_clear_exception_queue(vcpu);
4811                         break;
4812                 default:
4813                         break;
4814                 }
4815         }
4816         tss_selector = exit_qualification;
4817
4818         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4819                        type != INTR_TYPE_EXT_INTR &&
4820                        type != INTR_TYPE_NMI_INTR))
4821                 skip_emulated_instruction(vcpu);
4822
4823         if (kvm_task_switch(vcpu, tss_selector,
4824                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4825                             has_error_code, error_code) == EMULATE_FAIL) {
4826                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4827                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4828                 vcpu->run->internal.ndata = 0;
4829                 return 0;
4830         }
4831
4832         /* clear all local breakpoint enable flags */
4833         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4834
4835         /*
4836          * TODO: What about debug traps on tss switch?
4837          *       Are we supposed to inject them and update dr6?
4838          */
4839
4840         return 1;
4841 }
4842
4843 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4844 {
4845         unsigned long exit_qualification;
4846         gpa_t gpa;
4847         u32 error_code;
4848         int gla_validity;
4849
4850         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4851
4852         if (exit_qualification & (1 << 6)) {
4853                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4854                 return -EINVAL;
4855         }
4856
4857         gla_validity = (exit_qualification >> 7) & 0x3;
4858         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4859                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4860                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4861                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4862                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4863                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4864                         (long unsigned int)exit_qualification);
4865                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4866                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4867                 return 0;
4868         }
4869
4870         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4871         trace_kvm_page_fault(gpa, exit_qualification);
4872
4873         /* It is a write fault? */
4874         error_code = exit_qualification & (1U << 1);
4875         /* ept page table is present? */
4876         error_code |= (exit_qualification >> 3) & 0x1;
4877
4878         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
4879 }
4880
4881 static u64 ept_rsvd_mask(u64 spte, int level)
4882 {
4883         int i;
4884         u64 mask = 0;
4885
4886         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4887                 mask |= (1ULL << i);
4888
4889         if (level > 2)
4890                 /* bits 7:3 reserved */
4891                 mask |= 0xf8;
4892         else if (level == 2) {
4893                 if (spte & (1ULL << 7))
4894                         /* 2MB ref, bits 20:12 reserved */
4895                         mask |= 0x1ff000;
4896                 else
4897                         /* bits 6:3 reserved */
4898                         mask |= 0x78;
4899         }
4900
4901         return mask;
4902 }
4903
4904 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4905                                        int level)
4906 {
4907         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4908
4909         /* 010b (write-only) */
4910         WARN_ON((spte & 0x7) == 0x2);
4911
4912         /* 110b (write/execute) */
4913         WARN_ON((spte & 0x7) == 0x6);
4914
4915         /* 100b (execute-only) and value not supported by logical processor */
4916         if (!cpu_has_vmx_ept_execute_only())
4917                 WARN_ON((spte & 0x7) == 0x4);
4918
4919         /* not 000b */
4920         if ((spte & 0x7)) {
4921                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4922
4923                 if (rsvd_bits != 0) {
4924                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4925                                          __func__, rsvd_bits);
4926                         WARN_ON(1);
4927                 }
4928
4929                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4930                         u64 ept_mem_type = (spte & 0x38) >> 3;
4931
4932                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4933                             ept_mem_type == 7) {
4934                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4935                                                 __func__, ept_mem_type);
4936                                 WARN_ON(1);
4937                         }
4938                 }
4939         }
4940 }
4941
4942 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4943 {
4944         u64 sptes[4];
4945         int nr_sptes, i, ret;
4946         gpa_t gpa;
4947
4948         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4949
4950         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4951         if (likely(ret == 1))
4952                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4953                                               EMULATE_DONE;
4954         if (unlikely(!ret))
4955                 return 1;
4956
4957         /* It is the real ept misconfig */
4958         printk(KERN_ERR "EPT: Misconfiguration.\n");
4959         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4960
4961         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4962
4963         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4964                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4965
4966         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4967         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4968
4969         return 0;
4970 }
4971
4972 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4973 {
4974         u32 cpu_based_vm_exec_control;
4975
4976         /* clear pending NMI */
4977         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4978         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4979         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4980         ++vcpu->stat.nmi_window_exits;
4981         kvm_make_request(KVM_REQ_EVENT, vcpu);
4982
4983         return 1;
4984 }
4985
4986 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4987 {
4988         struct vcpu_vmx *vmx = to_vmx(vcpu);
4989         enum emulation_result err = EMULATE_DONE;
4990         int ret = 1;
4991         u32 cpu_exec_ctrl;
4992         bool intr_window_requested;
4993         unsigned count = 130;
4994
4995         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4996         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4997
4998         while (!guest_state_valid(vcpu) && count-- != 0) {
4999                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5000                         return handle_interrupt_window(&vmx->vcpu);
5001
5002                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5003                         return 1;
5004
5005                 err = emulate_instruction(vcpu, 0);
5006
5007                 if (err == EMULATE_DO_MMIO) {
5008                         ret = 0;
5009                         goto out;
5010                 }
5011
5012                 if (err != EMULATE_DONE) {
5013                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5014                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5015                         vcpu->run->internal.ndata = 0;
5016                         return 0;
5017                 }
5018
5019                 if (signal_pending(current))
5020                         goto out;
5021                 if (need_resched())
5022                         schedule();
5023         }
5024
5025         vmx->emulation_required = !guest_state_valid(vcpu);
5026 out:
5027         return ret;
5028 }
5029
5030 /*
5031  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5032  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5033  */
5034 static int handle_pause(struct kvm_vcpu *vcpu)
5035 {
5036         skip_emulated_instruction(vcpu);
5037         kvm_vcpu_on_spin(vcpu);
5038
5039         return 1;
5040 }
5041
5042 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5043 {
5044         kvm_queue_exception(vcpu, UD_VECTOR);
5045         return 1;
5046 }
5047
5048 /*
5049  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5050  * We could reuse a single VMCS for all the L2 guests, but we also want the
5051  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5052  * allows keeping them loaded on the processor, and in the future will allow
5053  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5054  * every entry if they never change.
5055  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5056  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5057  *
5058  * The following functions allocate and free a vmcs02 in this pool.
5059  */
5060
5061 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5062 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5063 {
5064         struct vmcs02_list *item;
5065         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5066                 if (item->vmptr == vmx->nested.current_vmptr) {
5067                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5068                         return &item->vmcs02;
5069                 }
5070
5071         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5072                 /* Recycle the least recently used VMCS. */
5073                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5074                         struct vmcs02_list, list);
5075                 item->vmptr = vmx->nested.current_vmptr;
5076                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5077                 return &item->vmcs02;
5078         }
5079
5080         /* Create a new VMCS */
5081         item = (struct vmcs02_list *)
5082                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5083         if (!item)
5084                 return NULL;
5085         item->vmcs02.vmcs = alloc_vmcs();
5086         if (!item->vmcs02.vmcs) {
5087                 kfree(item);
5088                 return NULL;
5089         }
5090         loaded_vmcs_init(&item->vmcs02);
5091         item->vmptr = vmx->nested.current_vmptr;
5092         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5093         vmx->nested.vmcs02_num++;
5094         return &item->vmcs02;
5095 }
5096
5097 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5098 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5099 {
5100         struct vmcs02_list *item;
5101         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5102                 if (item->vmptr == vmptr) {
5103                         free_loaded_vmcs(&item->vmcs02);
5104                         list_del(&item->list);
5105                         kfree(item);
5106                         vmx->nested.vmcs02_num--;
5107                         return;
5108                 }
5109 }
5110
5111 /*
5112  * Free all VMCSs saved for this vcpu, except the one pointed by
5113  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5114  * currently used, if running L2), and vmcs01 when running L2.
5115  */
5116 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5117 {
5118         struct vmcs02_list *item, *n;
5119         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5120                 if (vmx->loaded_vmcs != &item->vmcs02)
5121                         free_loaded_vmcs(&item->vmcs02);
5122                 list_del(&item->list);
5123                 kfree(item);
5124         }
5125         vmx->nested.vmcs02_num = 0;
5126
5127         if (vmx->loaded_vmcs != &vmx->vmcs01)
5128                 free_loaded_vmcs(&vmx->vmcs01);
5129 }
5130
5131 /*
5132  * Emulate the VMXON instruction.
5133  * Currently, we just remember that VMX is active, and do not save or even
5134  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5135  * do not currently need to store anything in that guest-allocated memory
5136  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5137  * argument is different from the VMXON pointer (which the spec says they do).
5138  */
5139 static int handle_vmon(struct kvm_vcpu *vcpu)
5140 {
5141         struct kvm_segment cs;
5142         struct vcpu_vmx *vmx = to_vmx(vcpu);
5143
5144         /* The Intel VMX Instruction Reference lists a bunch of bits that
5145          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5146          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5147          * Otherwise, we should fail with #UD. We test these now:
5148          */
5149         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5150             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5151             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5152                 kvm_queue_exception(vcpu, UD_VECTOR);
5153                 return 1;
5154         }
5155
5156         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5157         if (is_long_mode(vcpu) && !cs.l) {
5158                 kvm_queue_exception(vcpu, UD_VECTOR);
5159                 return 1;
5160         }
5161
5162         if (vmx_get_cpl(vcpu)) {
5163                 kvm_inject_gp(vcpu, 0);
5164                 return 1;
5165         }
5166
5167         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5168         vmx->nested.vmcs02_num = 0;
5169
5170         vmx->nested.vmxon = true;
5171
5172         skip_emulated_instruction(vcpu);
5173         return 1;
5174 }
5175
5176 /*
5177  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5178  * for running VMX instructions (except VMXON, whose prerequisites are
5179  * slightly different). It also specifies what exception to inject otherwise.
5180  */
5181 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5182 {
5183         struct kvm_segment cs;
5184         struct vcpu_vmx *vmx = to_vmx(vcpu);
5185
5186         if (!vmx->nested.vmxon) {
5187                 kvm_queue_exception(vcpu, UD_VECTOR);
5188                 return 0;
5189         }
5190
5191         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5192         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5193             (is_long_mode(vcpu) && !cs.l)) {
5194                 kvm_queue_exception(vcpu, UD_VECTOR);
5195                 return 0;
5196         }
5197
5198         if (vmx_get_cpl(vcpu)) {
5199                 kvm_inject_gp(vcpu, 0);
5200                 return 0;
5201         }
5202
5203         return 1;
5204 }
5205
5206 /*
5207  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5208  * just stops using VMX.
5209  */
5210 static void free_nested(struct vcpu_vmx *vmx)
5211 {
5212         if (!vmx->nested.vmxon)
5213                 return;
5214         vmx->nested.vmxon = false;
5215         if (vmx->nested.current_vmptr != -1ull) {
5216                 kunmap(vmx->nested.current_vmcs12_page);
5217                 nested_release_page(vmx->nested.current_vmcs12_page);
5218                 vmx->nested.current_vmptr = -1ull;
5219                 vmx->nested.current_vmcs12 = NULL;
5220         }
5221         /* Unpin physical memory we referred to in current vmcs02 */
5222         if (vmx->nested.apic_access_page) {
5223                 nested_release_page(vmx->nested.apic_access_page);
5224                 vmx->nested.apic_access_page = 0;
5225         }
5226
5227         nested_free_all_saved_vmcss(vmx);
5228 }
5229
5230 /* Emulate the VMXOFF instruction */
5231 static int handle_vmoff(struct kvm_vcpu *vcpu)
5232 {
5233         if (!nested_vmx_check_permission(vcpu))
5234                 return 1;
5235         free_nested(to_vmx(vcpu));
5236         skip_emulated_instruction(vcpu);
5237         return 1;
5238 }
5239
5240 /*
5241  * Decode the memory-address operand of a vmx instruction, as recorded on an
5242  * exit caused by such an instruction (run by a guest hypervisor).
5243  * On success, returns 0. When the operand is invalid, returns 1 and throws
5244  * #UD or #GP.
5245  */
5246 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5247                                  unsigned long exit_qualification,
5248                                  u32 vmx_instruction_info, gva_t *ret)
5249 {
5250         /*
5251          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5252          * Execution", on an exit, vmx_instruction_info holds most of the
5253          * addressing components of the operand. Only the displacement part
5254          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5255          * For how an actual address is calculated from all these components,
5256          * refer to Vol. 1, "Operand Addressing".
5257          */
5258         int  scaling = vmx_instruction_info & 3;
5259         int  addr_size = (vmx_instruction_info >> 7) & 7;
5260         bool is_reg = vmx_instruction_info & (1u << 10);
5261         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5262         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5263         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5264         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5265         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5266
5267         if (is_reg) {
5268                 kvm_queue_exception(vcpu, UD_VECTOR);
5269                 return 1;
5270         }
5271
5272         /* Addr = segment_base + offset */
5273         /* offset = base + [index * scale] + displacement */
5274         *ret = vmx_get_segment_base(vcpu, seg_reg);
5275         if (base_is_valid)
5276                 *ret += kvm_register_read(vcpu, base_reg);
5277         if (index_is_valid)
5278                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5279         *ret += exit_qualification; /* holds the displacement */
5280
5281         if (addr_size == 1) /* 32 bit */
5282                 *ret &= 0xffffffff;
5283
5284         /*
5285          * TODO: throw #GP (and return 1) in various cases that the VM*
5286          * instructions require it - e.g., offset beyond segment limit,
5287          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5288          * address, and so on. Currently these are not checked.
5289          */
5290         return 0;
5291 }
5292
5293 /*
5294  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5295  * set the success or error code of an emulated VMX instruction, as specified
5296  * by Vol 2B, VMX Instruction Reference, "Conventions".
5297  */
5298 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5299 {
5300         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5301                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5302                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5303 }
5304
5305 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5306 {
5307         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5308                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5309                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5310                         | X86_EFLAGS_CF);
5311 }
5312
5313 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5314                                         u32 vm_instruction_error)
5315 {
5316         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5317                 /*
5318                  * failValid writes the error number to the current VMCS, which
5319                  * can't be done there isn't a current VMCS.
5320                  */
5321                 nested_vmx_failInvalid(vcpu);
5322                 return;
5323         }
5324         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5325                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5326                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5327                         | X86_EFLAGS_ZF);
5328         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5329 }
5330
5331 /* Emulate the VMCLEAR instruction */
5332 static int handle_vmclear(struct kvm_vcpu *vcpu)
5333 {
5334         struct vcpu_vmx *vmx = to_vmx(vcpu);
5335         gva_t gva;
5336         gpa_t vmptr;
5337         struct vmcs12 *vmcs12;
5338         struct page *page;
5339         struct x86_exception e;
5340
5341         if (!nested_vmx_check_permission(vcpu))
5342                 return 1;
5343
5344         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5345                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5346                 return 1;
5347
5348         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5349                                 sizeof(vmptr), &e)) {
5350                 kvm_inject_page_fault(vcpu, &e);
5351                 return 1;
5352         }
5353
5354         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5355                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5356                 skip_emulated_instruction(vcpu);
5357                 return 1;
5358         }
5359
5360         if (vmptr == vmx->nested.current_vmptr) {
5361                 kunmap(vmx->nested.current_vmcs12_page);
5362                 nested_release_page(vmx->nested.current_vmcs12_page);
5363                 vmx->nested.current_vmptr = -1ull;
5364                 vmx->nested.current_vmcs12 = NULL;
5365         }
5366
5367         page = nested_get_page(vcpu, vmptr);
5368         if (page == NULL) {
5369                 /*
5370                  * For accurate processor emulation, VMCLEAR beyond available
5371                  * physical memory should do nothing at all. However, it is
5372                  * possible that a nested vmx bug, not a guest hypervisor bug,
5373                  * resulted in this case, so let's shut down before doing any
5374                  * more damage:
5375                  */
5376                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5377                 return 1;
5378         }
5379         vmcs12 = kmap(page);
5380         vmcs12->launch_state = 0;
5381         kunmap(page);
5382         nested_release_page(page);
5383
5384         nested_free_vmcs02(vmx, vmptr);
5385
5386         skip_emulated_instruction(vcpu);
5387         nested_vmx_succeed(vcpu);
5388         return 1;
5389 }
5390
5391 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5392
5393 /* Emulate the VMLAUNCH instruction */
5394 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5395 {
5396         return nested_vmx_run(vcpu, true);
5397 }
5398
5399 /* Emulate the VMRESUME instruction */
5400 static int handle_vmresume(struct kvm_vcpu *vcpu)
5401 {
5402
5403         return nested_vmx_run(vcpu, false);
5404 }
5405
5406 enum vmcs_field_type {
5407         VMCS_FIELD_TYPE_U16 = 0,
5408         VMCS_FIELD_TYPE_U64 = 1,
5409         VMCS_FIELD_TYPE_U32 = 2,
5410         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5411 };
5412
5413 static inline int vmcs_field_type(unsigned long field)
5414 {
5415         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5416                 return VMCS_FIELD_TYPE_U32;
5417         return (field >> 13) & 0x3 ;
5418 }
5419
5420 static inline int vmcs_field_readonly(unsigned long field)
5421 {
5422         return (((field >> 10) & 0x3) == 1);
5423 }
5424
5425 /*
5426  * Read a vmcs12 field. Since these can have varying lengths and we return
5427  * one type, we chose the biggest type (u64) and zero-extend the return value
5428  * to that size. Note that the caller, handle_vmread, might need to use only
5429  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5430  * 64-bit fields are to be returned).
5431  */
5432 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5433                                         unsigned long field, u64 *ret)
5434 {
5435         short offset = vmcs_field_to_offset(field);
5436         char *p;
5437
5438         if (offset < 0)
5439                 return 0;
5440
5441         p = ((char *)(get_vmcs12(vcpu))) + offset;
5442
5443         switch (vmcs_field_type(field)) {
5444         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5445                 *ret = *((natural_width *)p);
5446                 return 1;
5447         case VMCS_FIELD_TYPE_U16:
5448                 *ret = *((u16 *)p);
5449                 return 1;
5450         case VMCS_FIELD_TYPE_U32:
5451                 *ret = *((u32 *)p);
5452                 return 1;
5453         case VMCS_FIELD_TYPE_U64:
5454                 *ret = *((u64 *)p);
5455                 return 1;
5456         default:
5457                 return 0; /* can never happen. */
5458         }
5459 }
5460
5461 /*
5462  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5463  * used before) all generate the same failure when it is missing.
5464  */
5465 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5466 {
5467         struct vcpu_vmx *vmx = to_vmx(vcpu);
5468         if (vmx->nested.current_vmptr == -1ull) {
5469                 nested_vmx_failInvalid(vcpu);
5470                 skip_emulated_instruction(vcpu);
5471                 return 0;
5472         }
5473         return 1;
5474 }
5475
5476 static int handle_vmread(struct kvm_vcpu *vcpu)
5477 {
5478         unsigned long field;
5479         u64 field_value;
5480         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5481         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5482         gva_t gva = 0;
5483
5484         if (!nested_vmx_check_permission(vcpu) ||
5485             !nested_vmx_check_vmcs12(vcpu))
5486                 return 1;
5487
5488         /* Decode instruction info and find the field to read */
5489         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5490         /* Read the field, zero-extended to a u64 field_value */
5491         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5492                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5493                 skip_emulated_instruction(vcpu);
5494                 return 1;
5495         }
5496         /*
5497          * Now copy part of this value to register or memory, as requested.
5498          * Note that the number of bits actually copied is 32 or 64 depending
5499          * on the guest's mode (32 or 64 bit), not on the given field's length.
5500          */
5501         if (vmx_instruction_info & (1u << 10)) {
5502                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5503                         field_value);
5504         } else {
5505                 if (get_vmx_mem_address(vcpu, exit_qualification,
5506                                 vmx_instruction_info, &gva))
5507                         return 1;
5508                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5509                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5510                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5511         }
5512
5513         nested_vmx_succeed(vcpu);
5514         skip_emulated_instruction(vcpu);
5515         return 1;
5516 }
5517
5518
5519 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5520 {
5521         unsigned long field;
5522         gva_t gva;
5523         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5524         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5525         char *p;
5526         short offset;
5527         /* The value to write might be 32 or 64 bits, depending on L1's long
5528          * mode, and eventually we need to write that into a field of several
5529          * possible lengths. The code below first zero-extends the value to 64
5530          * bit (field_value), and then copies only the approriate number of
5531          * bits into the vmcs12 field.
5532          */
5533         u64 field_value = 0;
5534         struct x86_exception e;
5535
5536         if (!nested_vmx_check_permission(vcpu) ||
5537             !nested_vmx_check_vmcs12(vcpu))
5538                 return 1;
5539
5540         if (vmx_instruction_info & (1u << 10))
5541                 field_value = kvm_register_read(vcpu,
5542                         (((vmx_instruction_info) >> 3) & 0xf));
5543         else {
5544                 if (get_vmx_mem_address(vcpu, exit_qualification,
5545                                 vmx_instruction_info, &gva))
5546                         return 1;
5547                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5548                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5549                         kvm_inject_page_fault(vcpu, &e);
5550                         return 1;
5551                 }
5552         }
5553
5554
5555         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5556         if (vmcs_field_readonly(field)) {
5557                 nested_vmx_failValid(vcpu,
5558                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5559                 skip_emulated_instruction(vcpu);
5560                 return 1;
5561         }
5562
5563         offset = vmcs_field_to_offset(field);
5564         if (offset < 0) {
5565                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5566                 skip_emulated_instruction(vcpu);
5567                 return 1;
5568         }
5569         p = ((char *) get_vmcs12(vcpu)) + offset;
5570
5571         switch (vmcs_field_type(field)) {
5572         case VMCS_FIELD_TYPE_U16:
5573                 *(u16 *)p = field_value;
5574                 break;
5575         case VMCS_FIELD_TYPE_U32:
5576                 *(u32 *)p = field_value;
5577                 break;
5578         case VMCS_FIELD_TYPE_U64:
5579                 *(u64 *)p = field_value;
5580                 break;
5581         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5582                 *(natural_width *)p = field_value;
5583                 break;
5584         default:
5585                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5586                 skip_emulated_instruction(vcpu);
5587                 return 1;
5588         }
5589
5590         nested_vmx_succeed(vcpu);
5591         skip_emulated_instruction(vcpu);
5592         return 1;
5593 }
5594
5595 /* Emulate the VMPTRLD instruction */
5596 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5597 {
5598         struct vcpu_vmx *vmx = to_vmx(vcpu);
5599         gva_t gva;
5600         gpa_t vmptr;
5601         struct x86_exception e;
5602
5603         if (!nested_vmx_check_permission(vcpu))
5604                 return 1;
5605
5606         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5607                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5608                 return 1;
5609
5610         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5611                                 sizeof(vmptr), &e)) {
5612                 kvm_inject_page_fault(vcpu, &e);
5613                 return 1;
5614         }
5615
5616         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5617                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5618                 skip_emulated_instruction(vcpu);
5619                 return 1;
5620         }
5621
5622         if (vmx->nested.current_vmptr != vmptr) {
5623                 struct vmcs12 *new_vmcs12;
5624                 struct page *page;
5625                 page = nested_get_page(vcpu, vmptr);
5626                 if (page == NULL) {
5627                         nested_vmx_failInvalid(vcpu);
5628                         skip_emulated_instruction(vcpu);
5629                         return 1;
5630                 }
5631                 new_vmcs12 = kmap(page);
5632                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5633                         kunmap(page);
5634                         nested_release_page_clean(page);
5635                         nested_vmx_failValid(vcpu,
5636                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5637                         skip_emulated_instruction(vcpu);
5638                         return 1;
5639                 }
5640                 if (vmx->nested.current_vmptr != -1ull) {
5641                         kunmap(vmx->nested.current_vmcs12_page);
5642                         nested_release_page(vmx->nested.current_vmcs12_page);
5643                 }
5644
5645                 vmx->nested.current_vmptr = vmptr;
5646                 vmx->nested.current_vmcs12 = new_vmcs12;
5647                 vmx->nested.current_vmcs12_page = page;
5648         }
5649
5650         nested_vmx_succeed(vcpu);
5651         skip_emulated_instruction(vcpu);
5652         return 1;
5653 }
5654
5655 /* Emulate the VMPTRST instruction */
5656 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5657 {
5658         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5659         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5660         gva_t vmcs_gva;
5661         struct x86_exception e;
5662
5663         if (!nested_vmx_check_permission(vcpu))
5664                 return 1;
5665
5666         if (get_vmx_mem_address(vcpu, exit_qualification,
5667                         vmx_instruction_info, &vmcs_gva))
5668                 return 1;
5669         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5670         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5671                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5672                                  sizeof(u64), &e)) {
5673                 kvm_inject_page_fault(vcpu, &e);
5674                 return 1;
5675         }
5676         nested_vmx_succeed(vcpu);
5677         skip_emulated_instruction(vcpu);
5678         return 1;
5679 }
5680
5681 /*
5682  * The exit handlers return 1 if the exit was handled fully and guest execution
5683  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5684  * to be done to userspace and return 0.
5685  */
5686 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5687         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5688         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5689         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5690         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5691         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5692         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5693         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5694         [EXIT_REASON_CPUID]                   = handle_cpuid,
5695         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5696         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5697         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5698         [EXIT_REASON_HLT]                     = handle_halt,
5699         [EXIT_REASON_INVD]                    = handle_invd,
5700         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5701         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5702         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5703         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5704         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5705         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5706         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5707         [EXIT_REASON_VMREAD]                  = handle_vmread,
5708         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5709         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5710         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5711         [EXIT_REASON_VMON]                    = handle_vmon,
5712         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5713         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5714         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5715         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5716         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5717         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5718         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5719         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5720         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5721         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5722         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5723 };
5724
5725 static const int kvm_vmx_max_exit_handlers =
5726         ARRAY_SIZE(kvm_vmx_exit_handlers);
5727
5728 /*
5729  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5730  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5731  * disinterest in the current event (read or write a specific MSR) by using an
5732  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5733  */
5734 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5735         struct vmcs12 *vmcs12, u32 exit_reason)
5736 {
5737         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5738         gpa_t bitmap;
5739
5740         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5741                 return 1;
5742
5743         /*
5744          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5745          * for the four combinations of read/write and low/high MSR numbers.
5746          * First we need to figure out which of the four to use:
5747          */
5748         bitmap = vmcs12->msr_bitmap;
5749         if (exit_reason == EXIT_REASON_MSR_WRITE)
5750                 bitmap += 2048;
5751         if (msr_index >= 0xc0000000) {
5752                 msr_index -= 0xc0000000;
5753                 bitmap += 1024;
5754         }
5755
5756         /* Then read the msr_index'th bit from this bitmap: */
5757         if (msr_index < 1024*8) {
5758                 unsigned char b;
5759                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5760                 return 1 & (b >> (msr_index & 7));
5761         } else
5762                 return 1; /* let L1 handle the wrong parameter */
5763 }
5764
5765 /*
5766  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5767  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5768  * intercept (via guest_host_mask etc.) the current event.
5769  */
5770 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5771         struct vmcs12 *vmcs12)
5772 {
5773         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5774         int cr = exit_qualification & 15;
5775         int reg = (exit_qualification >> 8) & 15;
5776         unsigned long val = kvm_register_read(vcpu, reg);
5777
5778         switch ((exit_qualification >> 4) & 3) {
5779         case 0: /* mov to cr */
5780                 switch (cr) {
5781                 case 0:
5782                         if (vmcs12->cr0_guest_host_mask &
5783                             (val ^ vmcs12->cr0_read_shadow))
5784                                 return 1;
5785                         break;
5786                 case 3:
5787                         if ((vmcs12->cr3_target_count >= 1 &&
5788                                         vmcs12->cr3_target_value0 == val) ||
5789                                 (vmcs12->cr3_target_count >= 2 &&
5790                                         vmcs12->cr3_target_value1 == val) ||
5791                                 (vmcs12->cr3_target_count >= 3 &&
5792                                         vmcs12->cr3_target_value2 == val) ||
5793                                 (vmcs12->cr3_target_count >= 4 &&
5794                                         vmcs12->cr3_target_value3 == val))
5795                                 return 0;
5796                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5797                                 return 1;
5798                         break;
5799                 case 4:
5800                         if (vmcs12->cr4_guest_host_mask &
5801                             (vmcs12->cr4_read_shadow ^ val))
5802                                 return 1;
5803                         break;
5804                 case 8:
5805                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5806                                 return 1;
5807                         break;
5808                 }
5809                 break;
5810         case 2: /* clts */
5811                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5812                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5813                         return 1;
5814                 break;
5815         case 1: /* mov from cr */
5816                 switch (cr) {
5817                 case 3:
5818                         if (vmcs12->cpu_based_vm_exec_control &
5819                             CPU_BASED_CR3_STORE_EXITING)
5820                                 return 1;
5821                         break;
5822                 case 8:
5823                         if (vmcs12->cpu_based_vm_exec_control &
5824                             CPU_BASED_CR8_STORE_EXITING)
5825                                 return 1;
5826                         break;
5827                 }
5828                 break;
5829         case 3: /* lmsw */
5830                 /*
5831                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5832                  * cr0. Other attempted changes are ignored, with no exit.
5833                  */
5834                 if (vmcs12->cr0_guest_host_mask & 0xe &
5835                     (val ^ vmcs12->cr0_read_shadow))
5836                         return 1;
5837                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5838                     !(vmcs12->cr0_read_shadow & 0x1) &&
5839                     (val & 0x1))
5840                         return 1;
5841                 break;
5842         }
5843         return 0;
5844 }
5845
5846 /*
5847  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5848  * should handle it ourselves in L0 (and then continue L2). Only call this
5849  * when in is_guest_mode (L2).
5850  */
5851 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5852 {
5853         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5854         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5855         struct vcpu_vmx *vmx = to_vmx(vcpu);
5856         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5857
5858         if (vmx->nested.nested_run_pending)
5859                 return 0;
5860
5861         if (unlikely(vmx->fail)) {
5862                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5863                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5864                 return 1;
5865         }
5866
5867         switch (exit_reason) {
5868         case EXIT_REASON_EXCEPTION_NMI:
5869                 if (!is_exception(intr_info))
5870                         return 0;
5871                 else if (is_page_fault(intr_info))
5872                         return enable_ept;
5873                 return vmcs12->exception_bitmap &
5874                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5875         case EXIT_REASON_EXTERNAL_INTERRUPT:
5876                 return 0;
5877         case EXIT_REASON_TRIPLE_FAULT:
5878                 return 1;
5879         case EXIT_REASON_PENDING_INTERRUPT:
5880         case EXIT_REASON_NMI_WINDOW:
5881                 /*
5882                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5883                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5884                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5885                  * Same for NMI Window Exiting.
5886                  */
5887                 return 1;
5888         case EXIT_REASON_TASK_SWITCH:
5889                 return 1;
5890         case EXIT_REASON_CPUID:
5891                 return 1;
5892         case EXIT_REASON_HLT:
5893                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5894         case EXIT_REASON_INVD:
5895                 return 1;
5896         case EXIT_REASON_INVLPG:
5897                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5898         case EXIT_REASON_RDPMC:
5899                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5900         case EXIT_REASON_RDTSC:
5901                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5902         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5903         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5904         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5905         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5906         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5907                 /*
5908                  * VMX instructions trap unconditionally. This allows L1 to
5909                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5910                  */
5911                 return 1;
5912         case EXIT_REASON_CR_ACCESS:
5913                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5914         case EXIT_REASON_DR_ACCESS:
5915                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5916         case EXIT_REASON_IO_INSTRUCTION:
5917                 /* TODO: support IO bitmaps */
5918                 return 1;
5919         case EXIT_REASON_MSR_READ:
5920         case EXIT_REASON_MSR_WRITE:
5921                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5922         case EXIT_REASON_INVALID_STATE:
5923                 return 1;
5924         case EXIT_REASON_MWAIT_INSTRUCTION:
5925                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5926         case EXIT_REASON_MONITOR_INSTRUCTION:
5927                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5928         case EXIT_REASON_PAUSE_INSTRUCTION:
5929                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5930                         nested_cpu_has2(vmcs12,
5931                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5932         case EXIT_REASON_MCE_DURING_VMENTRY:
5933                 return 0;
5934         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5935                 return 1;
5936         case EXIT_REASON_APIC_ACCESS:
5937                 return nested_cpu_has2(vmcs12,
5938                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5939         case EXIT_REASON_EPT_VIOLATION:
5940         case EXIT_REASON_EPT_MISCONFIG:
5941                 return 0;
5942         case EXIT_REASON_WBINVD:
5943                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5944         case EXIT_REASON_XSETBV:
5945                 return 1;
5946         default:
5947                 return 1;
5948         }
5949 }
5950
5951 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5952 {
5953         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5954         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5955 }
5956
5957 /*
5958  * The guest has exited.  See if we can fix it or if we need userspace
5959  * assistance.
5960  */
5961 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5962 {
5963         struct vcpu_vmx *vmx = to_vmx(vcpu);
5964         u32 exit_reason = vmx->exit_reason;
5965         u32 vectoring_info = vmx->idt_vectoring_info;
5966
5967         /* If guest state is invalid, start emulating */
5968         if (vmx->emulation_required && emulate_invalid_guest_state)
5969                 return handle_invalid_guest_state(vcpu);
5970
5971         /*
5972          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5973          * we did not inject a still-pending event to L1 now because of
5974          * nested_run_pending, we need to re-enable this bit.
5975          */
5976         if (vmx->nested.nested_run_pending)
5977                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5978
5979         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5980             exit_reason == EXIT_REASON_VMRESUME))
5981                 vmx->nested.nested_run_pending = 1;
5982         else
5983                 vmx->nested.nested_run_pending = 0;
5984
5985         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5986                 nested_vmx_vmexit(vcpu);
5987                 return 1;
5988         }
5989
5990         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5991                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5992                 vcpu->run->fail_entry.hardware_entry_failure_reason
5993                         = exit_reason;
5994                 return 0;
5995         }
5996
5997         if (unlikely(vmx->fail)) {
5998                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5999                 vcpu->run->fail_entry.hardware_entry_failure_reason
6000                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6001                 return 0;
6002         }
6003
6004         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6005                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6006                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6007                         exit_reason != EXIT_REASON_TASK_SWITCH))
6008                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
6009                        "(0x%x) and exit reason is 0x%x\n",
6010                        __func__, vectoring_info, exit_reason);
6011
6012         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6013             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6014                                         get_vmcs12(vcpu), vcpu)))) {
6015                 if (vmx_interrupt_allowed(vcpu)) {
6016                         vmx->soft_vnmi_blocked = 0;
6017                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6018                            vcpu->arch.nmi_pending) {
6019                         /*
6020                          * This CPU don't support us in finding the end of an
6021                          * NMI-blocked window if the guest runs with IRQs
6022                          * disabled. So we pull the trigger after 1 s of
6023                          * futile waiting, but inform the user about this.
6024                          */
6025                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6026                                "state on VCPU %d after 1 s timeout\n",
6027                                __func__, vcpu->vcpu_id);
6028                         vmx->soft_vnmi_blocked = 0;
6029                 }
6030         }
6031
6032         if (exit_reason < kvm_vmx_max_exit_handlers
6033             && kvm_vmx_exit_handlers[exit_reason])
6034                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6035         else {
6036                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6037                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6038         }
6039         return 0;
6040 }
6041
6042 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6043 {
6044         if (irr == -1 || tpr < irr) {
6045                 vmcs_write32(TPR_THRESHOLD, 0);
6046                 return;
6047         }
6048
6049         vmcs_write32(TPR_THRESHOLD, irr);
6050 }
6051
6052 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6053 {
6054         u32 exit_intr_info;
6055
6056         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6057               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6058                 return;
6059
6060         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6061         exit_intr_info = vmx->exit_intr_info;
6062
6063         /* Handle machine checks before interrupts are enabled */
6064         if (is_machine_check(exit_intr_info))
6065                 kvm_machine_check();
6066
6067         /* We need to handle NMIs before interrupts are enabled */
6068         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6069             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6070                 kvm_before_handle_nmi(&vmx->vcpu);
6071                 asm("int $2");
6072                 kvm_after_handle_nmi(&vmx->vcpu);
6073         }
6074 }
6075
6076 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6077 {
6078         u32 exit_intr_info;
6079         bool unblock_nmi;
6080         u8 vector;
6081         bool idtv_info_valid;
6082
6083         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6084
6085         if (cpu_has_virtual_nmis()) {
6086                 if (vmx->nmi_known_unmasked)
6087                         return;
6088                 /*
6089                  * Can't use vmx->exit_intr_info since we're not sure what
6090                  * the exit reason is.
6091                  */
6092                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6093                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6094                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6095                 /*
6096                  * SDM 3: 27.7.1.2 (September 2008)
6097                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6098                  * a guest IRET fault.
6099                  * SDM 3: 23.2.2 (September 2008)
6100                  * Bit 12 is undefined in any of the following cases:
6101                  *  If the VM exit sets the valid bit in the IDT-vectoring
6102                  *   information field.
6103                  *  If the VM exit is due to a double fault.
6104                  */
6105                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6106                     vector != DF_VECTOR && !idtv_info_valid)
6107                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6108                                       GUEST_INTR_STATE_NMI);
6109                 else
6110                         vmx->nmi_known_unmasked =
6111                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6112                                   & GUEST_INTR_STATE_NMI);
6113         } else if (unlikely(vmx->soft_vnmi_blocked))
6114                 vmx->vnmi_blocked_time +=
6115                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6116 }
6117
6118 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6119                                       u32 idt_vectoring_info,
6120                                       int instr_len_field,
6121                                       int error_code_field)
6122 {
6123         u8 vector;
6124         int type;
6125         bool idtv_info_valid;
6126
6127         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6128
6129         vmx->vcpu.arch.nmi_injected = false;
6130         kvm_clear_exception_queue(&vmx->vcpu);
6131         kvm_clear_interrupt_queue(&vmx->vcpu);
6132
6133         if (!idtv_info_valid)
6134                 return;
6135
6136         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6137
6138         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6139         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6140
6141         switch (type) {
6142         case INTR_TYPE_NMI_INTR:
6143                 vmx->vcpu.arch.nmi_injected = true;
6144                 /*
6145                  * SDM 3: 27.7.1.2 (September 2008)
6146                  * Clear bit "block by NMI" before VM entry if a NMI
6147                  * delivery faulted.
6148                  */
6149                 vmx_set_nmi_mask(&vmx->vcpu, false);
6150                 break;
6151         case INTR_TYPE_SOFT_EXCEPTION:
6152                 vmx->vcpu.arch.event_exit_inst_len =
6153                         vmcs_read32(instr_len_field);
6154                 /* fall through */
6155         case INTR_TYPE_HARD_EXCEPTION:
6156                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6157                         u32 err = vmcs_read32(error_code_field);
6158                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6159                 } else
6160                         kvm_queue_exception(&vmx->vcpu, vector);
6161                 break;
6162         case INTR_TYPE_SOFT_INTR:
6163                 vmx->vcpu.arch.event_exit_inst_len =
6164                         vmcs_read32(instr_len_field);
6165                 /* fall through */
6166         case INTR_TYPE_EXT_INTR:
6167                 kvm_queue_interrupt(&vmx->vcpu, vector,
6168                         type == INTR_TYPE_SOFT_INTR);
6169                 break;
6170         default:
6171                 break;
6172         }
6173 }
6174
6175 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6176 {
6177         if (is_guest_mode(&vmx->vcpu))
6178                 return;
6179         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6180                                   VM_EXIT_INSTRUCTION_LEN,
6181                                   IDT_VECTORING_ERROR_CODE);
6182 }
6183
6184 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6185 {
6186         if (is_guest_mode(vcpu))
6187                 return;
6188         __vmx_complete_interrupts(to_vmx(vcpu),
6189                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6190                                   VM_ENTRY_INSTRUCTION_LEN,
6191                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6192
6193         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6194 }
6195
6196 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6197 {
6198         int i, nr_msrs;
6199         struct perf_guest_switch_msr *msrs;
6200
6201         msrs = perf_guest_get_msrs(&nr_msrs);
6202
6203         if (!msrs)
6204                 return;
6205
6206         for (i = 0; i < nr_msrs; i++)
6207                 if (msrs[i].host == msrs[i].guest)
6208                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6209                 else
6210                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6211                                         msrs[i].host);
6212 }
6213
6214 #ifdef CONFIG_X86_64
6215 #define R "r"
6216 #define Q "q"
6217 #else
6218 #define R "e"
6219 #define Q "l"
6220 #endif
6221
6222 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6223 {
6224         struct vcpu_vmx *vmx = to_vmx(vcpu);
6225         unsigned long debugctlmsr;
6226
6227         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6228                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6229                 if (vmcs12->idt_vectoring_info_field &
6230                                 VECTORING_INFO_VALID_MASK) {
6231                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6232                                 vmcs12->idt_vectoring_info_field);
6233                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6234                                 vmcs12->vm_exit_instruction_len);
6235                         if (vmcs12->idt_vectoring_info_field &
6236                                         VECTORING_INFO_DELIVER_CODE_MASK)
6237                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6238                                         vmcs12->idt_vectoring_error_code);
6239                 }
6240         }
6241
6242         /* Record the guest's net vcpu time for enforced NMI injections. */
6243         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6244                 vmx->entry_time = ktime_get();
6245
6246         /* Don't enter VMX if guest state is invalid, let the exit handler
6247            start emulation until we arrive back to a valid state */
6248         if (vmx->emulation_required && emulate_invalid_guest_state)
6249                 return;
6250
6251         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6252                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6253         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6254                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6255
6256         /* When single-stepping over STI and MOV SS, we must clear the
6257          * corresponding interruptibility bits in the guest state. Otherwise
6258          * vmentry fails as it then expects bit 14 (BS) in pending debug
6259          * exceptions being set, but that's not correct for the guest debugging
6260          * case. */
6261         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6262                 vmx_set_interrupt_shadow(vcpu, 0);
6263
6264         atomic_switch_perf_msrs(vmx);
6265         debugctlmsr = get_debugctlmsr();
6266
6267         vmx->__launched = vmx->loaded_vmcs->launched;
6268         asm(
6269                 /* Store host registers */
6270                 "push %%"R"dx; push %%"R"bp;"
6271                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6272                 "push %%"R"cx \n\t"
6273                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6274                 "je 1f \n\t"
6275                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6276                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6277                 "1: \n\t"
6278                 /* Reload cr2 if changed */
6279                 "mov %c[cr2](%0), %%"R"ax \n\t"
6280                 "mov %%cr2, %%"R"dx \n\t"
6281                 "cmp %%"R"ax, %%"R"dx \n\t"
6282                 "je 2f \n\t"
6283                 "mov %%"R"ax, %%cr2 \n\t"
6284                 "2: \n\t"
6285                 /* Check if vmlaunch of vmresume is needed */
6286                 "cmpl $0, %c[launched](%0) \n\t"
6287                 /* Load guest registers.  Don't clobber flags. */
6288                 "mov %c[rax](%0), %%"R"ax \n\t"
6289                 "mov %c[rbx](%0), %%"R"bx \n\t"
6290                 "mov %c[rdx](%0), %%"R"dx \n\t"
6291                 "mov %c[rsi](%0), %%"R"si \n\t"
6292                 "mov %c[rdi](%0), %%"R"di \n\t"
6293                 "mov %c[rbp](%0), %%"R"bp \n\t"
6294 #ifdef CONFIG_X86_64
6295                 "mov %c[r8](%0),  %%r8  \n\t"
6296                 "mov %c[r9](%0),  %%r9  \n\t"
6297                 "mov %c[r10](%0), %%r10 \n\t"
6298                 "mov %c[r11](%0), %%r11 \n\t"
6299                 "mov %c[r12](%0), %%r12 \n\t"
6300                 "mov %c[r13](%0), %%r13 \n\t"
6301                 "mov %c[r14](%0), %%r14 \n\t"
6302                 "mov %c[r15](%0), %%r15 \n\t"
6303 #endif
6304                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6305
6306                 /* Enter guest mode */
6307                 "jne .Llaunched \n\t"
6308                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6309                 "jmp .Lkvm_vmx_return \n\t"
6310                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6311                 ".Lkvm_vmx_return: "
6312                 /* Save guest registers, load host registers, keep flags */
6313                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6314                 "pop %0 \n\t"
6315                 "mov %%"R"ax, %c[rax](%0) \n\t"
6316                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6317                 "pop"Q" %c[rcx](%0) \n\t"
6318                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6319                 "mov %%"R"si, %c[rsi](%0) \n\t"
6320                 "mov %%"R"di, %c[rdi](%0) \n\t"
6321                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6322 #ifdef CONFIG_X86_64
6323                 "mov %%r8,  %c[r8](%0) \n\t"
6324                 "mov %%r9,  %c[r9](%0) \n\t"
6325                 "mov %%r10, %c[r10](%0) \n\t"
6326                 "mov %%r11, %c[r11](%0) \n\t"
6327                 "mov %%r12, %c[r12](%0) \n\t"
6328                 "mov %%r13, %c[r13](%0) \n\t"
6329                 "mov %%r14, %c[r14](%0) \n\t"
6330                 "mov %%r15, %c[r15](%0) \n\t"
6331 #endif
6332                 "mov %%cr2, %%"R"ax   \n\t"
6333                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6334
6335                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6336                 "setbe %c[fail](%0) \n\t"
6337               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6338                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6339                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6340                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6341                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6342                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6343                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6344                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6345                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6346                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6347                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6348 #ifdef CONFIG_X86_64
6349                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6350                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6351                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6352                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6353                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6354                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6355                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6356                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6357 #endif
6358                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6359                 [wordsize]"i"(sizeof(ulong))
6360               : "cc", "memory"
6361                 , R"ax", R"bx", R"di", R"si"
6362 #ifdef CONFIG_X86_64
6363                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6364 #endif
6365               );
6366
6367         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6368         if (debugctlmsr)
6369                 update_debugctlmsr(debugctlmsr);
6370
6371 #ifndef CONFIG_X86_64
6372         /*
6373          * The sysexit path does not restore ds/es, so we must set them to
6374          * a reasonable value ourselves.
6375          *
6376          * We can't defer this to vmx_load_host_state() since that function
6377          * may be executed in interrupt context, which saves and restore segments
6378          * around it, nullifying its effect.
6379          */
6380         loadsegment(ds, __USER_DS);
6381         loadsegment(es, __USER_DS);
6382 #endif
6383
6384         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6385                                   | (1 << VCPU_EXREG_RFLAGS)
6386                                   | (1 << VCPU_EXREG_CPL)
6387                                   | (1 << VCPU_EXREG_PDPTR)
6388                                   | (1 << VCPU_EXREG_SEGMENTS)
6389                                   | (1 << VCPU_EXREG_CR3));
6390         vcpu->arch.regs_dirty = 0;
6391
6392         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6393
6394         if (is_guest_mode(vcpu)) {
6395                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6396                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6397                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6398                         vmcs12->idt_vectoring_error_code =
6399                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6400                         vmcs12->vm_exit_instruction_len =
6401                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6402                 }
6403         }
6404
6405         vmx->loaded_vmcs->launched = 1;
6406
6407         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6408         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6409
6410         vmx_complete_atomic_exit(vmx);
6411         vmx_recover_nmi_blocking(vmx);
6412         vmx_complete_interrupts(vmx);
6413 }
6414
6415 #undef R
6416 #undef Q
6417
6418 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6419 {
6420         struct vcpu_vmx *vmx = to_vmx(vcpu);
6421
6422         free_vpid(vmx);
6423         free_nested(vmx);
6424         free_loaded_vmcs(vmx->loaded_vmcs);
6425         kfree(vmx->guest_msrs);
6426         kvm_vcpu_uninit(vcpu);
6427         kmem_cache_free(kvm_vcpu_cache, vmx);
6428 }
6429
6430 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6431 {
6432         int err;
6433         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6434         int cpu;
6435
6436         if (!vmx)
6437                 return ERR_PTR(-ENOMEM);
6438
6439         allocate_vpid(vmx);
6440
6441         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6442         if (err)
6443                 goto free_vcpu;
6444
6445         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6446         err = -ENOMEM;
6447         if (!vmx->guest_msrs) {
6448                 goto uninit_vcpu;
6449         }
6450
6451         vmx->loaded_vmcs = &vmx->vmcs01;
6452         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6453         if (!vmx->loaded_vmcs->vmcs)
6454                 goto free_msrs;
6455         if (!vmm_exclusive)
6456                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6457         loaded_vmcs_init(vmx->loaded_vmcs);
6458         if (!vmm_exclusive)
6459                 kvm_cpu_vmxoff();
6460
6461         cpu = get_cpu();
6462         vmx_vcpu_load(&vmx->vcpu, cpu);
6463         vmx->vcpu.cpu = cpu;
6464         err = vmx_vcpu_setup(vmx);
6465         vmx_vcpu_put(&vmx->vcpu);
6466         put_cpu();
6467         if (err)
6468                 goto free_vmcs;
6469         if (vm_need_virtualize_apic_accesses(kvm))
6470                 err = alloc_apic_access_page(kvm);
6471                 if (err)
6472                         goto free_vmcs;
6473
6474         if (enable_ept) {
6475                 if (!kvm->arch.ept_identity_map_addr)
6476                         kvm->arch.ept_identity_map_addr =
6477                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6478                 err = -ENOMEM;
6479                 if (alloc_identity_pagetable(kvm) != 0)
6480                         goto free_vmcs;
6481                 if (!init_rmode_identity_map(kvm))
6482                         goto free_vmcs;
6483         }
6484
6485         vmx->nested.current_vmptr = -1ull;
6486         vmx->nested.current_vmcs12 = NULL;
6487
6488         return &vmx->vcpu;
6489
6490 free_vmcs:
6491         free_loaded_vmcs(vmx->loaded_vmcs);
6492 free_msrs:
6493         kfree(vmx->guest_msrs);
6494 uninit_vcpu:
6495         kvm_vcpu_uninit(&vmx->vcpu);
6496 free_vcpu:
6497         free_vpid(vmx);
6498         kmem_cache_free(kvm_vcpu_cache, vmx);
6499         return ERR_PTR(err);
6500 }
6501
6502 static void __init vmx_check_processor_compat(void *rtn)
6503 {
6504         struct vmcs_config vmcs_conf;
6505
6506         *(int *)rtn = 0;
6507         if (setup_vmcs_config(&vmcs_conf) < 0)
6508                 *(int *)rtn = -EIO;
6509         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6510                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6511                                 smp_processor_id());
6512                 *(int *)rtn = -EIO;
6513         }
6514 }
6515
6516 static int get_ept_level(void)
6517 {
6518         return VMX_EPT_DEFAULT_GAW + 1;
6519 }
6520
6521 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6522 {
6523         u64 ret;
6524
6525         /* For VT-d and EPT combination
6526          * 1. MMIO: always map as UC
6527          * 2. EPT with VT-d:
6528          *   a. VT-d without snooping control feature: can't guarantee the
6529          *      result, try to trust guest.
6530          *   b. VT-d with snooping control feature: snooping control feature of
6531          *      VT-d engine can guarantee the cache correctness. Just set it
6532          *      to WB to keep consistent with host. So the same as item 3.
6533          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6534          *    consistent with host MTRR
6535          */
6536         if (is_mmio)
6537                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6538         else if (vcpu->kvm->arch.iommu_domain &&
6539                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6540                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6541                       VMX_EPT_MT_EPTE_SHIFT;
6542         else
6543                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6544                         | VMX_EPT_IPAT_BIT;
6545
6546         return ret;
6547 }
6548
6549 static int vmx_get_lpage_level(void)
6550 {
6551         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6552                 return PT_DIRECTORY_LEVEL;
6553         else
6554                 /* For shadow and EPT supported 1GB page */
6555                 return PT_PDPE_LEVEL;
6556 }
6557
6558 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6559 {
6560         struct kvm_cpuid_entry2 *best;
6561         struct vcpu_vmx *vmx = to_vmx(vcpu);
6562         u32 exec_control;
6563
6564         vmx->rdtscp_enabled = false;
6565         if (vmx_rdtscp_supported()) {
6566                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6567                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6568                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6569                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6570                                 vmx->rdtscp_enabled = true;
6571                         else {
6572                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6573                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6574                                                 exec_control);
6575                         }
6576                 }
6577         }
6578
6579         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6580         /* Exposing INVPCID only when PCID is exposed */
6581         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6582         if (vmx_invpcid_supported() &&
6583             best && (best->ecx & bit(X86_FEATURE_INVPCID)) &&
6584             guest_cpuid_has_pcid(vcpu)) {
6585                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6586                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6587                              exec_control);
6588         } else {
6589                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6590                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6591                              exec_control);
6592                 if (best)
6593                         best->ecx &= ~bit(X86_FEATURE_INVPCID);
6594         }
6595 }
6596
6597 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6598 {
6599         if (func == 1 && nested)
6600                 entry->ecx |= bit(X86_FEATURE_VMX);
6601 }
6602
6603 /*
6604  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6605  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6606  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6607  * guest in a way that will both be appropriate to L1's requests, and our
6608  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6609  * function also has additional necessary side-effects, like setting various
6610  * vcpu->arch fields.
6611  */
6612 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6613 {
6614         struct vcpu_vmx *vmx = to_vmx(vcpu);
6615         u32 exec_control;
6616
6617         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6618         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6619         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6620         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6621         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6622         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6623         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6624         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6625         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6626         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6627         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6628         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6629         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6630         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6631         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6632         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6633         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6634         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6635         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6636         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6637         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6638         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6639         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6640         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6641         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6642         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6643         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6644         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6645         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6646         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6647         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6648         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6649         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6650         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6651         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6652         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6653
6654         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6655         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6656                 vmcs12->vm_entry_intr_info_field);
6657         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6658                 vmcs12->vm_entry_exception_error_code);
6659         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6660                 vmcs12->vm_entry_instruction_len);
6661         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6662                 vmcs12->guest_interruptibility_info);
6663         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6664         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6665         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6666         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6667         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6668                 vmcs12->guest_pending_dbg_exceptions);
6669         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6670         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6671
6672         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6673
6674         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6675                 (vmcs_config.pin_based_exec_ctrl |
6676                  vmcs12->pin_based_vm_exec_control));
6677
6678         /*
6679          * Whether page-faults are trapped is determined by a combination of
6680          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6681          * If enable_ept, L0 doesn't care about page faults and we should
6682          * set all of these to L1's desires. However, if !enable_ept, L0 does
6683          * care about (at least some) page faults, and because it is not easy
6684          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6685          * to exit on each and every L2 page fault. This is done by setting
6686          * MASK=MATCH=0 and (see below) EB.PF=1.
6687          * Note that below we don't need special code to set EB.PF beyond the
6688          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6689          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6690          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6691          *
6692          * A problem with this approach (when !enable_ept) is that L1 may be
6693          * injected with more page faults than it asked for. This could have
6694          * caused problems, but in practice existing hypervisors don't care.
6695          * To fix this, we will need to emulate the PFEC checking (on the L1
6696          * page tables), using walk_addr(), when injecting PFs to L1.
6697          */
6698         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6699                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6700         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6701                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6702
6703         if (cpu_has_secondary_exec_ctrls()) {
6704                 u32 exec_control = vmx_secondary_exec_control(vmx);
6705                 if (!vmx->rdtscp_enabled)
6706                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6707                 /* Take the following fields only from vmcs12 */
6708                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6709                 if (nested_cpu_has(vmcs12,
6710                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6711                         exec_control |= vmcs12->secondary_vm_exec_control;
6712
6713                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6714                         /*
6715                          * Translate L1 physical address to host physical
6716                          * address for vmcs02. Keep the page pinned, so this
6717                          * physical address remains valid. We keep a reference
6718                          * to it so we can release it later.
6719                          */
6720                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6721                                 nested_release_page(vmx->nested.apic_access_page);
6722                         vmx->nested.apic_access_page =
6723                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6724                         /*
6725                          * If translation failed, no matter: This feature asks
6726                          * to exit when accessing the given address, and if it
6727                          * can never be accessed, this feature won't do
6728                          * anything anyway.
6729                          */
6730                         if (!vmx->nested.apic_access_page)
6731                                 exec_control &=
6732                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6733                         else
6734                                 vmcs_write64(APIC_ACCESS_ADDR,
6735                                   page_to_phys(vmx->nested.apic_access_page));
6736                 }
6737
6738                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6739         }
6740
6741
6742         /*
6743          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6744          * Some constant fields are set here by vmx_set_constant_host_state().
6745          * Other fields are different per CPU, and will be set later when
6746          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6747          */
6748         vmx_set_constant_host_state();
6749
6750         /*
6751          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6752          * entry, but only if the current (host) sp changed from the value
6753          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6754          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6755          * here we just force the write to happen on entry.
6756          */
6757         vmx->host_rsp = 0;
6758
6759         exec_control = vmx_exec_control(vmx); /* L0's desires */
6760         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6761         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6762         exec_control &= ~CPU_BASED_TPR_SHADOW;
6763         exec_control |= vmcs12->cpu_based_vm_exec_control;
6764         /*
6765          * Merging of IO and MSR bitmaps not currently supported.
6766          * Rather, exit every time.
6767          */
6768         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6769         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6770         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6771
6772         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6773
6774         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6775          * bitwise-or of what L1 wants to trap for L2, and what we want to
6776          * trap. Note that CR0.TS also needs updating - we do this later.
6777          */
6778         update_exception_bitmap(vcpu);
6779         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6780         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6781
6782         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6783         vmcs_write32(VM_EXIT_CONTROLS,
6784                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6785         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6786                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6787
6788         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6789                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6790         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6791                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6792
6793
6794         set_cr4_guest_host_mask(vmx);
6795
6796         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6797                 vmcs_write64(TSC_OFFSET,
6798                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6799         else
6800                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6801
6802         if (enable_vpid) {
6803                 /*
6804                  * Trivially support vpid by letting L2s share their parent
6805                  * L1's vpid. TODO: move to a more elaborate solution, giving
6806                  * each L2 its own vpid and exposing the vpid feature to L1.
6807                  */
6808                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6809                 vmx_flush_tlb(vcpu);
6810         }
6811
6812         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6813                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6814         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6815                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6816         else
6817                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6818         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6819         vmx_set_efer(vcpu, vcpu->arch.efer);
6820
6821         /*
6822          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6823          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6824          * The CR0_READ_SHADOW is what L2 should have expected to read given
6825          * the specifications by L1; It's not enough to take
6826          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6827          * have more bits than L1 expected.
6828          */
6829         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6830         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6831
6832         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6833         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6834
6835         /* shadow page tables on either EPT or shadow page tables */
6836         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6837         kvm_mmu_reset_context(vcpu);
6838
6839         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6840         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6841 }
6842
6843 /*
6844  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6845  * for running an L2 nested guest.
6846  */
6847 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6848 {
6849         struct vmcs12 *vmcs12;
6850         struct vcpu_vmx *vmx = to_vmx(vcpu);
6851         int cpu;
6852         struct loaded_vmcs *vmcs02;
6853
6854         if (!nested_vmx_check_permission(vcpu) ||
6855             !nested_vmx_check_vmcs12(vcpu))
6856                 return 1;
6857
6858         skip_emulated_instruction(vcpu);
6859         vmcs12 = get_vmcs12(vcpu);
6860
6861         /*
6862          * The nested entry process starts with enforcing various prerequisites
6863          * on vmcs12 as required by the Intel SDM, and act appropriately when
6864          * they fail: As the SDM explains, some conditions should cause the
6865          * instruction to fail, while others will cause the instruction to seem
6866          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6867          * To speed up the normal (success) code path, we should avoid checking
6868          * for misconfigurations which will anyway be caught by the processor
6869          * when using the merged vmcs02.
6870          */
6871         if (vmcs12->launch_state == launch) {
6872                 nested_vmx_failValid(vcpu,
6873                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6874                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6875                 return 1;
6876         }
6877
6878         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6879                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6880                 /*TODO: Also verify bits beyond physical address width are 0*/
6881                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6882                 return 1;
6883         }
6884
6885         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6886                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6887                 /*TODO: Also verify bits beyond physical address width are 0*/
6888                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6889                 return 1;
6890         }
6891
6892         if (vmcs12->vm_entry_msr_load_count > 0 ||
6893             vmcs12->vm_exit_msr_load_count > 0 ||
6894             vmcs12->vm_exit_msr_store_count > 0) {
6895                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6896                                     __func__);
6897                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6898                 return 1;
6899         }
6900
6901         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6902               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6903             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6904               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6905             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6906               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6907             !vmx_control_verify(vmcs12->vm_exit_controls,
6908               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6909             !vmx_control_verify(vmcs12->vm_entry_controls,
6910               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6911         {
6912                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6913                 return 1;
6914         }
6915
6916         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6917             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6918                 nested_vmx_failValid(vcpu,
6919                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6920                 return 1;
6921         }
6922
6923         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6924             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6925                 nested_vmx_entry_failure(vcpu, vmcs12,
6926                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6927                 return 1;
6928         }
6929         if (vmcs12->vmcs_link_pointer != -1ull) {
6930                 nested_vmx_entry_failure(vcpu, vmcs12,
6931                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6932                 return 1;
6933         }
6934
6935         /*
6936          * We're finally done with prerequisite checking, and can start with
6937          * the nested entry.
6938          */
6939
6940         vmcs02 = nested_get_current_vmcs02(vmx);
6941         if (!vmcs02)
6942                 return -ENOMEM;
6943
6944         enter_guest_mode(vcpu);
6945
6946         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6947
6948         cpu = get_cpu();
6949         vmx->loaded_vmcs = vmcs02;
6950         vmx_vcpu_put(vcpu);
6951         vmx_vcpu_load(vcpu, cpu);
6952         vcpu->cpu = cpu;
6953         put_cpu();
6954
6955         vmcs12->launch_state = 1;
6956
6957         prepare_vmcs02(vcpu, vmcs12);
6958
6959         /*
6960          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6961          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6962          * returned as far as L1 is concerned. It will only return (and set
6963          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6964          */
6965         return 1;
6966 }
6967
6968 /*
6969  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6970  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6971  * This function returns the new value we should put in vmcs12.guest_cr0.
6972  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6973  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6974  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6975  *     didn't trap the bit, because if L1 did, so would L0).
6976  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6977  *     been modified by L2, and L1 knows it. So just leave the old value of
6978  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6979  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6980  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6981  *     changed these bits, and therefore they need to be updated, but L0
6982  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6983  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6984  */
6985 static inline unsigned long
6986 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6987 {
6988         return
6989         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6990         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6991         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6992                         vcpu->arch.cr0_guest_owned_bits));
6993 }
6994
6995 static inline unsigned long
6996 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6997 {
6998         return
6999         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7000         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7001         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7002                         vcpu->arch.cr4_guest_owned_bits));
7003 }
7004
7005 /*
7006  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7007  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7008  * and this function updates it to reflect the changes to the guest state while
7009  * L2 was running (and perhaps made some exits which were handled directly by L0
7010  * without going back to L1), and to reflect the exit reason.
7011  * Note that we do not have to copy here all VMCS fields, just those that
7012  * could have changed by the L2 guest or the exit - i.e., the guest-state and
7013  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7014  * which already writes to vmcs12 directly.
7015  */
7016 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7017 {
7018         /* update guest state fields: */
7019         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7020         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7021
7022         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7023         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7024         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7025         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7026
7027         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7028         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7029         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7030         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7031         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7032         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7033         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7034         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7035         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7036         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7037         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7038         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7039         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7040         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7041         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7042         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7043         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7044         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7045         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7046         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7047         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7048         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7049         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7050         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7051         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7052         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7053         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7054         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7055         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7056         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7057         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7058         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7059         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7060         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7061         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7062         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7063
7064         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7065         vmcs12->guest_interruptibility_info =
7066                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7067         vmcs12->guest_pending_dbg_exceptions =
7068                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7069
7070         /* TODO: These cannot have changed unless we have MSR bitmaps and
7071          * the relevant bit asks not to trap the change */
7072         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7073         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7074                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7075         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7076         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7077         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7078
7079         /* update exit information fields: */
7080
7081         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
7082         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7083
7084         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7085         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7086         vmcs12->idt_vectoring_info_field =
7087                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7088         vmcs12->idt_vectoring_error_code =
7089                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7090         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7091         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7092
7093         /* clear vm-entry fields which are to be cleared on exit */
7094         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7095                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7096 }
7097
7098 /*
7099  * A part of what we need to when the nested L2 guest exits and we want to
7100  * run its L1 parent, is to reset L1's guest state to the host state specified
7101  * in vmcs12.
7102  * This function is to be called not only on normal nested exit, but also on
7103  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7104  * Failures During or After Loading Guest State").
7105  * This function should be called when the active VMCS is L1's (vmcs01).
7106  */
7107 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7108 {
7109         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7110                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7111         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7112                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7113         else
7114                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7115         vmx_set_efer(vcpu, vcpu->arch.efer);
7116
7117         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7118         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7119         /*
7120          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7121          * actually changed, because it depends on the current state of
7122          * fpu_active (which may have changed).
7123          * Note that vmx_set_cr0 refers to efer set above.
7124          */
7125         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7126         /*
7127          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7128          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7129          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7130          */
7131         update_exception_bitmap(vcpu);
7132         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7133         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7134
7135         /*
7136          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7137          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7138          */
7139         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7140         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7141
7142         /* shadow page tables on either EPT or shadow page tables */
7143         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7144         kvm_mmu_reset_context(vcpu);
7145
7146         if (enable_vpid) {
7147                 /*
7148                  * Trivially support vpid by letting L2s share their parent
7149                  * L1's vpid. TODO: move to a more elaborate solution, giving
7150                  * each L2 its own vpid and exposing the vpid feature to L1.
7151                  */
7152                 vmx_flush_tlb(vcpu);
7153         }
7154
7155
7156         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7157         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7158         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7159         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7160         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7161         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7162         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7163         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7164         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7165         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7166         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7167         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7168         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7169         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7170         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7171
7172         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7173                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7174         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7175                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7176                         vmcs12->host_ia32_perf_global_ctrl);
7177 }
7178
7179 /*
7180  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7181  * and modify vmcs12 to make it see what it would expect to see there if
7182  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7183  */
7184 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7185 {
7186         struct vcpu_vmx *vmx = to_vmx(vcpu);
7187         int cpu;
7188         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7189
7190         leave_guest_mode(vcpu);
7191         prepare_vmcs12(vcpu, vmcs12);
7192
7193         cpu = get_cpu();
7194         vmx->loaded_vmcs = &vmx->vmcs01;
7195         vmx_vcpu_put(vcpu);
7196         vmx_vcpu_load(vcpu, cpu);
7197         vcpu->cpu = cpu;
7198         put_cpu();
7199
7200         /* if no vmcs02 cache requested, remove the one we used */
7201         if (VMCS02_POOL_SIZE == 0)
7202                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7203
7204         load_vmcs12_host_state(vcpu, vmcs12);
7205
7206         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7207         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7208
7209         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7210         vmx->host_rsp = 0;
7211
7212         /* Unpin physical memory we referred to in vmcs02 */
7213         if (vmx->nested.apic_access_page) {
7214                 nested_release_page(vmx->nested.apic_access_page);
7215                 vmx->nested.apic_access_page = 0;
7216         }
7217
7218         /*
7219          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7220          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7221          * success or failure flag accordingly.
7222          */
7223         if (unlikely(vmx->fail)) {
7224                 vmx->fail = 0;
7225                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7226         } else
7227                 nested_vmx_succeed(vcpu);
7228 }
7229
7230 /*
7231  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7232  * 23.7 "VM-entry failures during or after loading guest state" (this also
7233  * lists the acceptable exit-reason and exit-qualification parameters).
7234  * It should only be called before L2 actually succeeded to run, and when
7235  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7236  */
7237 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7238                         struct vmcs12 *vmcs12,
7239                         u32 reason, unsigned long qualification)
7240 {
7241         load_vmcs12_host_state(vcpu, vmcs12);
7242         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7243         vmcs12->exit_qualification = qualification;
7244         nested_vmx_succeed(vcpu);
7245 }
7246
7247 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7248                                struct x86_instruction_info *info,
7249                                enum x86_intercept_stage stage)
7250 {
7251         return X86EMUL_CONTINUE;
7252 }
7253
7254 static struct kvm_x86_ops vmx_x86_ops = {
7255         .cpu_has_kvm_support = cpu_has_kvm_support,
7256         .disabled_by_bios = vmx_disabled_by_bios,
7257         .hardware_setup = hardware_setup,
7258         .hardware_unsetup = hardware_unsetup,
7259         .check_processor_compatibility = vmx_check_processor_compat,
7260         .hardware_enable = hardware_enable,
7261         .hardware_disable = hardware_disable,
7262         .cpu_has_accelerated_tpr = report_flexpriority,
7263
7264         .vcpu_create = vmx_create_vcpu,
7265         .vcpu_free = vmx_free_vcpu,
7266         .vcpu_reset = vmx_vcpu_reset,
7267
7268         .prepare_guest_switch = vmx_save_host_state,
7269         .vcpu_load = vmx_vcpu_load,
7270         .vcpu_put = vmx_vcpu_put,
7271
7272         .set_guest_debug = set_guest_debug,
7273         .get_msr = vmx_get_msr,
7274         .set_msr = vmx_set_msr,
7275         .get_segment_base = vmx_get_segment_base,
7276         .get_segment = vmx_get_segment,
7277         .set_segment = vmx_set_segment,
7278         .get_cpl = vmx_get_cpl,
7279         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7280         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7281         .decache_cr3 = vmx_decache_cr3,
7282         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7283         .set_cr0 = vmx_set_cr0,
7284         .set_cr3 = vmx_set_cr3,
7285         .set_cr4 = vmx_set_cr4,
7286         .set_efer = vmx_set_efer,
7287         .get_idt = vmx_get_idt,
7288         .set_idt = vmx_set_idt,
7289         .get_gdt = vmx_get_gdt,
7290         .set_gdt = vmx_set_gdt,
7291         .set_dr7 = vmx_set_dr7,
7292         .cache_reg = vmx_cache_reg,
7293         .get_rflags = vmx_get_rflags,
7294         .set_rflags = vmx_set_rflags,
7295         .fpu_activate = vmx_fpu_activate,
7296         .fpu_deactivate = vmx_fpu_deactivate,
7297
7298         .tlb_flush = vmx_flush_tlb,
7299
7300         .run = vmx_vcpu_run,
7301         .handle_exit = vmx_handle_exit,
7302         .skip_emulated_instruction = skip_emulated_instruction,
7303         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7304         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7305         .patch_hypercall = vmx_patch_hypercall,
7306         .set_irq = vmx_inject_irq,
7307         .set_nmi = vmx_inject_nmi,
7308         .queue_exception = vmx_queue_exception,
7309         .cancel_injection = vmx_cancel_injection,
7310         .interrupt_allowed = vmx_interrupt_allowed,
7311         .nmi_allowed = vmx_nmi_allowed,
7312         .get_nmi_mask = vmx_get_nmi_mask,
7313         .set_nmi_mask = vmx_set_nmi_mask,
7314         .enable_nmi_window = enable_nmi_window,
7315         .enable_irq_window = enable_irq_window,
7316         .update_cr8_intercept = update_cr8_intercept,
7317
7318         .set_tss_addr = vmx_set_tss_addr,
7319         .get_tdp_level = get_ept_level,
7320         .get_mt_mask = vmx_get_mt_mask,
7321
7322         .get_exit_info = vmx_get_exit_info,
7323
7324         .get_lpage_level = vmx_get_lpage_level,
7325
7326         .cpuid_update = vmx_cpuid_update,
7327
7328         .rdtscp_supported = vmx_rdtscp_supported,
7329         .invpcid_supported = vmx_invpcid_supported,
7330
7331         .set_supported_cpuid = vmx_set_supported_cpuid,
7332
7333         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7334
7335         .set_tsc_khz = vmx_set_tsc_khz,
7336         .write_tsc_offset = vmx_write_tsc_offset,
7337         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7338         .compute_tsc_offset = vmx_compute_tsc_offset,
7339         .read_l1_tsc = vmx_read_l1_tsc,
7340
7341         .set_tdp_cr3 = vmx_set_cr3,
7342
7343         .check_intercept = vmx_check_intercept,
7344 };
7345
7346 static int __init vmx_init(void)
7347 {
7348         int r, i;
7349
7350         rdmsrl_safe(MSR_EFER, &host_efer);
7351
7352         for (i = 0; i < NR_VMX_MSR; ++i)
7353                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7354
7355         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7356         if (!vmx_io_bitmap_a)
7357                 return -ENOMEM;
7358
7359         r = -ENOMEM;
7360
7361         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7362         if (!vmx_io_bitmap_b)
7363                 goto out;
7364
7365         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7366         if (!vmx_msr_bitmap_legacy)
7367                 goto out1;
7368
7369
7370         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7371         if (!vmx_msr_bitmap_longmode)
7372                 goto out2;
7373
7374
7375         /*
7376          * Allow direct access to the PC debug port (it is often used for I/O
7377          * delays, but the vmexits simply slow things down).
7378          */
7379         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7380         clear_bit(0x80, vmx_io_bitmap_a);
7381
7382         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7383
7384         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7385         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7386
7387         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7388
7389         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7390                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7391         if (r)
7392                 goto out3;
7393
7394         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7395         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7396         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7397         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7398         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7399         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7400
7401         if (enable_ept) {
7402                 kvm_mmu_set_mask_ptes(0ull,
7403                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7404                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7405                         0ull, VMX_EPT_EXECUTABLE_MASK);
7406                 ept_set_mmio_spte_mask();
7407                 kvm_enable_tdp();
7408         } else
7409                 kvm_disable_tdp();
7410
7411         return 0;
7412
7413 out3:
7414         free_page((unsigned long)vmx_msr_bitmap_longmode);
7415 out2:
7416         free_page((unsigned long)vmx_msr_bitmap_legacy);
7417 out1:
7418         free_page((unsigned long)vmx_io_bitmap_b);
7419 out:
7420         free_page((unsigned long)vmx_io_bitmap_a);
7421         return r;
7422 }
7423
7424 static void __exit vmx_exit(void)
7425 {
7426         free_page((unsigned long)vmx_msr_bitmap_legacy);
7427         free_page((unsigned long)vmx_msr_bitmap_longmode);
7428         free_page((unsigned long)vmx_io_bitmap_b);
7429         free_page((unsigned long)vmx_io_bitmap_a);
7430
7431         kvm_exit();
7432 }
7433
7434 module_init(vmx_init)
7435 module_exit(vmx_exit)