Pileus Git - ~andy/linux/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34 #include <asm/kvm_para.h>
  35
  36 #include <asm/virtext.h>
  37 #include "trace.h"
  38
  39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  40
  41 MODULE_AUTHOR("Qumranet");
  42 MODULE_LICENSE("GPL");
  43
  44 #define IOPM_ALLOC_ORDER 2
  45 #define MSRPM_ALLOC_ORDER 1
  46
  47 #define SEG_TYPE_LDT 2
  48 #define SEG_TYPE_BUSY_TSS16 3
  49
  50 #define SVM_FEATURE_NPT            (1 <<  0)
  51 #define SVM_FEATURE_LBRV           (1 <<  1)
  52 #define SVM_FEATURE_SVML           (1 <<  2)
  53 #define SVM_FEATURE_NRIP           (1 <<  3)
  54 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  55
  56 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  57 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  58 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  59
  60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  61
  62 static bool erratum_383_found __read_mostly;
  63
  64 static const u32 host_save_user_msrs[] = {
  65 #ifdef CONFIG_X86_64
  66         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  67         MSR_FS_BASE,
  68 #endif
  69         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  70 };
  71
  72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  73
  74 struct kvm_vcpu;
  75
  76 struct nested_state {
  77         struct vmcb *hsave;
  78         u64 hsave_msr;
  79         u64 vm_cr_msr;
  80         u64 vmcb;
  81
  82         /* These are the merged vectors */
  83         u32 *msrpm;
  84
  85         /* gpa pointers to the real vectors */
  86         u64 vmcb_msrpm;
  87         u64 vmcb_iopm;
  88
  89         /* A VMEXIT is required but not yet emulated */
  90         bool exit_required;
  91
  92         /*
  93          * If we vmexit during an instruction emulation we need this to restore
  94          * the l1 guest rip after the emulation
  95          */
  96         unsigned long vmexit_rip;
  97         unsigned long vmexit_rsp;
  98         unsigned long vmexit_rax;
  99
 100         /* cache for intercepts of the guest */
 101         u16 intercept_cr_read;
 102         u16 intercept_cr_write;
 103         u16 intercept_dr_read;
 104         u16 intercept_dr_write;
 105         u32 intercept_exceptions;
 106         u64 intercept;
 107
 108         /* Nested Paging related state */
 109         u64 nested_cr3;
 110 };
 111
 112 #define MSRPM_OFFSETS   16
 113 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 114
 115 struct vcpu_svm {
 116         struct kvm_vcpu vcpu;
 117         struct vmcb *vmcb;
 118         unsigned long vmcb_pa;
 119         struct svm_cpu_data *svm_data;
 120         uint64_t asid_generation;
 121         uint64_t sysenter_esp;
 122         uint64_t sysenter_eip;
 123
 124         u64 next_rip;
 125
 126         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 127         struct {
 128                 u16 fs;
 129                 u16 gs;
 130                 u16 ldt;
 131                 u64 gs_base;
 132         } host;
 133
 134         u32 *msrpm;
 135
 136         struct nested_state nested;
 137
 138         bool nmi_singlestep;
 139
 140         unsigned int3_injected;
 141         unsigned long int3_rip;
 142         u32 apf_reason;
 143 };
 144
 145 #define MSR_INVALID                     0xffffffffU
 146
 147 static struct svm_direct_access_msrs {
 148         u32 index;   /* Index of the MSR */
 149         bool always; /* True if intercept is always on */
 150 } direct_access_msrs[] = {
 151         { .index = MSR_STAR,                            .always = true  },
 152         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 153 #ifdef CONFIG_X86_64
 154         { .index = MSR_GS_BASE,                         .always = true  },
 155         { .index = MSR_FS_BASE,                         .always = true  },
 156         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 157         { .index = MSR_LSTAR,                           .always = true  },
 158         { .index = MSR_CSTAR,                           .always = true  },
 159         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 160 #endif
 161         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 162         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 163         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 164         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 165         { .index = MSR_INVALID,                         .always = false },
 166 };
 167
 168 /* enable NPT for AMD64 and X86 with PAE */
 169 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 170 static bool npt_enabled = true;
 171 #else
 172 static bool npt_enabled;
 173 #endif
 174 static int npt = 1;
 175
 176 module_param(npt, int, S_IRUGO);
 177
 178 static int nested = 1;
 179 module_param(nested, int, S_IRUGO);
 180
 181 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 182 static void svm_complete_interrupts(struct vcpu_svm *svm);
 183
 184 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 185 static int nested_svm_intercept(struct vcpu_svm *svm);
 186 static int nested_svm_vmexit(struct vcpu_svm *svm);
 187 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 188                                       bool has_error_code, u32 error_code);
 189
 190 static void save_host_msrs(struct kvm_vcpu *vcpu);
 191 static void load_host_msrs(struct kvm_vcpu *vcpu);
 192
 193 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 194 {
 195         return container_of(vcpu, struct vcpu_svm, vcpu);
 196 }
 197
 198 static inline bool is_nested(struct vcpu_svm *svm)
 199 {
 200         return svm->nested.vmcb;
 201 }
 202
 203 static inline void enable_gif(struct vcpu_svm *svm)
 204 {
 205         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 206 }
 207
 208 static inline void disable_gif(struct vcpu_svm *svm)
 209 {
 210         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 211 }
 212
 213 static inline bool gif_set(struct vcpu_svm *svm)
 214 {
 215         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 216 }
 217
 218 static unsigned long iopm_base;
 219
 220 struct kvm_ldttss_desc {
 221         u16 limit0;
 222         u16 base0;
 223         unsigned base1:8, type:5, dpl:2, p:1;
 224         unsigned limit1:4, zero0:3, g:1, base2:8;
 225         u32 base3;
 226         u32 zero1;
 227 } __attribute__((packed));
 228
 229 struct svm_cpu_data {
 230         int cpu;
 231
 232         u64 asid_generation;
 233         u32 max_asid;
 234         u32 next_asid;
 235         struct kvm_ldttss_desc *tss_desc;
 236
 237         struct page *save_area;
 238 };
 239
 240 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 241 static uint32_t svm_features;
 242
 243 struct svm_init_data {
 244         int cpu;
 245         int r;
 246 };
 247
 248 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 249
 250 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 251 #define MSRS_RANGE_SIZE 2048
 252 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 253
 254 static u32 svm_msrpm_offset(u32 msr)
 255 {
 256         u32 offset;
 257         int i;
 258
 259         for (i = 0; i < NUM_MSR_MAPS; i++) {
 260                 if (msr < msrpm_ranges[i] ||
 261                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 262                         continue;
 263
 264                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 265                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 266
 267                 /* Now we have the u8 offset - but need the u32 offset */
 268                 return offset / 4;
 269         }
 270
 271         /* MSR not in any range */
 272         return MSR_INVALID;
 273 }
 274
 275 #define MAX_INST_SIZE 15
 276
 277 static inline u32 svm_has(u32 feat)
 278 {
 279         return svm_features & feat;
 280 }
 281
 282 static inline void clgi(void)
 283 {
 284         asm volatile (__ex(SVM_CLGI));
 285 }
 286
 287 static inline void stgi(void)
 288 {
 289         asm volatile (__ex(SVM_STGI));
 290 }
 291
 292 static inline void invlpga(unsigned long addr, u32 asid)
 293 {
 294         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 295 }
 296
 297 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 298 {
 299         to_svm(vcpu)->asid_generation--;
 300 }
 301
 302 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 303 {
 304         force_new_asid(vcpu);
 305 }
 306
 307 static int get_npt_level(void)
 308 {
 309 #ifdef CONFIG_X86_64
 310         return PT64_ROOT_LEVEL;
 311 #else
 312         return PT32E_ROOT_LEVEL;
 313 #endif
 314 }
 315
 316 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 317 {
 318         vcpu->arch.efer = efer;
 319         if (!npt_enabled && !(efer & EFER_LMA))
 320                 efer &= ~EFER_LME;
 321
 322         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 323 }
 324
 325 static int is_external_interrupt(u32 info)
 326 {
 327         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 328         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 329 }
 330
 331 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 332 {
 333         struct vcpu_svm *svm = to_svm(vcpu);
 334         u32 ret = 0;
 335
 336         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 337                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 338         return ret & mask;
 339 }
 340
 341 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 342 {
 343         struct vcpu_svm *svm = to_svm(vcpu);
 344
 345         if (mask == 0)
 346                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 347         else
 348                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 349
 350 }
 351
 352 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 353 {
 354         struct vcpu_svm *svm = to_svm(vcpu);
 355
 356         if (svm->vmcb->control.next_rip != 0)
 357                 svm->next_rip = svm->vmcb->control.next_rip;
 358
 359         if (!svm->next_rip) {
 360                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 361                                 EMULATE_DONE)
 362                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 363                 return;
 364         }
 365         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 366                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 367                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 368
 369         kvm_rip_write(vcpu, svm->next_rip);
 370         svm_set_interrupt_shadow(vcpu, 0);
 371 }
 372
 373 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 374                                 bool has_error_code, u32 error_code,
 375                                 bool reinject)
 376 {
 377         struct vcpu_svm *svm = to_svm(vcpu);
 378
 379         /*
 380          * If we are within a nested VM we'd better #VMEXIT and let the guest
 381          * handle the exception
 382          */
 383         if (!reinject &&
 384             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 385                 return;
 386
 387         if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
 388                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 389
 390                 /*
 391                  * For guest debugging where we have to reinject #BP if some
 392                  * INT3 is guest-owned:
 393                  * Emulate nRIP by moving RIP forward. Will fail if injection
 394                  * raises a fault that is not intercepted. Still better than
 395                  * failing in all cases.
 396                  */
 397                 skip_emulated_instruction(&svm->vcpu);
 398                 rip = kvm_rip_read(&svm->vcpu);
 399                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 400                 svm->int3_injected = rip - old_rip;
 401         }
 402
 403         svm->vmcb->control.event_inj = nr
 404                 | SVM_EVTINJ_VALID
 405                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 406                 | SVM_EVTINJ_TYPE_EXEPT;
 407         svm->vmcb->control.event_inj_err = error_code;
 408 }
 409
 410 static void svm_init_erratum_383(void)
 411 {
 412         u32 low, high;
 413         int err;
 414         u64 val;
 415
 416         if (!cpu_has_amd_erratum(amd_erratum_383))
 417                 return;
 418
 419         /* Use _safe variants to not break nested virtualization */
 420         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 421         if (err)
 422                 return;
 423
 424         val |= (1ULL << 47);
 425
 426         low  = lower_32_bits(val);
 427         high = upper_32_bits(val);
 428
 429         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 430
 431         erratum_383_found = true;
 432 }
 433
 434 static int has_svm(void)
 435 {
 436         const char *msg;
 437
 438         if (!cpu_has_svm(&msg)) {
 439                 printk(KERN_INFO "has_svm: %s\n", msg);
 440                 return 0;
 441         }
 442
 443         return 1;
 444 }
 445
 446 static void svm_hardware_disable(void *garbage)
 447 {
 448         cpu_svm_disable();
 449 }
 450
 451 static int svm_hardware_enable(void *garbage)
 452 {
 453
 454         struct svm_cpu_data *sd;
 455         uint64_t efer;
 456         struct desc_ptr gdt_descr;
 457         struct desc_struct *gdt;
 458         int me = raw_smp_processor_id();
 459
 460         rdmsrl(MSR_EFER, efer);
 461         if (efer & EFER_SVME)
 462                 return -EBUSY;
 463
 464         if (!has_svm()) {
 465                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 466                        me);
 467                 return -EINVAL;
 468         }
 469         sd = per_cpu(svm_data, me);
 470
 471         if (!sd) {
 472                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 473                        me);
 474                 return -EINVAL;
 475         }
 476
 477         sd->asid_generation = 1;
 478         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 479         sd->next_asid = sd->max_asid + 1;
 480
 481         native_store_gdt(&gdt_descr);
 482         gdt = (struct desc_struct *)gdt_descr.address;
 483         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 484
 485         wrmsrl(MSR_EFER, efer | EFER_SVME);
 486
 487         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 488
 489         svm_init_erratum_383();
 490
 491         return 0;
 492 }
 493
 494 static void svm_cpu_uninit(int cpu)
 495 {
 496         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 497
 498         if (!sd)
 499                 return;
 500
 501         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 502         __free_page(sd->save_area);
 503         kfree(sd);
 504 }
 505
 506 static int svm_cpu_init(int cpu)
 507 {
 508         struct svm_cpu_data *sd;
 509         int r;
 510
 511         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 512         if (!sd)
 513                 return -ENOMEM;
 514         sd->cpu = cpu;
 515         sd->save_area = alloc_page(GFP_KERNEL);
 516         r = -ENOMEM;
 517         if (!sd->save_area)
 518                 goto err_1;
 519
 520         per_cpu(svm_data, cpu) = sd;
 521
 522         return 0;
 523
 524 err_1:
 525         kfree(sd);
 526         return r;
 527
 528 }
 529
 530 static bool valid_msr_intercept(u32 index)
 531 {
 532         int i;
 533
 534         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 535                 if (direct_access_msrs[i].index == index)
 536                         return true;
 537
 538         return false;
 539 }
 540
 541 static void set_msr_interception(u32 *msrpm, unsigned msr,
 542                                  int read, int write)
 543 {
 544         u8 bit_read, bit_write;
 545         unsigned long tmp;
 546         u32 offset;
 547
 548         /*
 549          * If this warning triggers extend the direct_access_msrs list at the
 550          * beginning of the file
 551          */
 552         WARN_ON(!valid_msr_intercept(msr));
 553
 554         offset    = svm_msrpm_offset(msr);
 555         bit_read  = 2 * (msr & 0x0f);
 556         bit_write = 2 * (msr & 0x0f) + 1;
 557         tmp       = msrpm[offset];
 558
 559         BUG_ON(offset == MSR_INVALID);
 560
 561         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 562         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 563
 564         msrpm[offset] = tmp;
 565 }
 566
 567 static void svm_vcpu_init_msrpm(u32 *msrpm)
 568 {
 569         int i;
 570
 571         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 572
 573         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 574                 if (!direct_access_msrs[i].always)
 575                         continue;
 576
 577                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 578         }
 579 }
 580
 581 static void add_msr_offset(u32 offset)
 582 {
 583         int i;
 584
 585         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 586
 587                 /* Offset already in list? */
 588                 if (msrpm_offsets[i] == offset)
 589                         return;
 590
 591                 /* Slot used by another offset? */
 592                 if (msrpm_offsets[i] != MSR_INVALID)
 593                         continue;
 594
 595                 /* Add offset to list */
 596                 msrpm_offsets[i] = offset;
 597
 598                 return;
 599         }
 600
 601         /*
 602          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 603          * increase MSRPM_OFFSETS in this case.
 604          */
 605         BUG();
 606 }
 607
 608 static void init_msrpm_offsets(void)
 609 {
 610         int i;
 611
 612         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 613
 614         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 615                 u32 offset;
 616
 617                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 618                 BUG_ON(offset == MSR_INVALID);
 619
 620                 add_msr_offset(offset);
 621         }
 622 }
 623
 624 static void svm_enable_lbrv(struct vcpu_svm *svm)
 625 {
 626         u32 *msrpm = svm->msrpm;
 627
 628         svm->vmcb->control.lbr_ctl = 1;
 629         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 630         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 631         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 632         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 633 }
 634
 635 static void svm_disable_lbrv(struct vcpu_svm *svm)
 636 {
 637         u32 *msrpm = svm->msrpm;
 638
 639         svm->vmcb->control.lbr_ctl = 0;
 640         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 641         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 642         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 643         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 644 }
 645
 646 static __init int svm_hardware_setup(void)
 647 {
 648         int cpu;
 649         struct page *iopm_pages;
 650         void *iopm_va;
 651         int r;
 652
 653         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 654
 655         if (!iopm_pages)
 656                 return -ENOMEM;
 657
 658         iopm_va = page_address(iopm_pages);
 659         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 660         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 661
 662         init_msrpm_offsets();
 663
 664         if (boot_cpu_has(X86_FEATURE_NX))
 665                 kvm_enable_efer_bits(EFER_NX);
 666
 667         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 668                 kvm_enable_efer_bits(EFER_FFXSR);
 669
 670         if (nested) {
 671                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 672                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 673         }
 674
 675         for_each_possible_cpu(cpu) {
 676                 r = svm_cpu_init(cpu);
 677                 if (r)
 678                         goto err;
 679         }
 680
 681         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 682
 683         if (!svm_has(SVM_FEATURE_NPT))
 684                 npt_enabled = false;
 685
 686         if (npt_enabled && !npt) {
 687                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 688                 npt_enabled = false;
 689         }
 690
 691         if (npt_enabled) {
 692                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 693                 kvm_enable_tdp();
 694         } else
 695                 kvm_disable_tdp();
 696
 697         return 0;
 698
 699 err:
 700         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 701         iopm_base = 0;
 702         return r;
 703 }
 704
 705 static __exit void svm_hardware_unsetup(void)
 706 {
 707         int cpu;
 708
 709         for_each_possible_cpu(cpu)
 710                 svm_cpu_uninit(cpu);
 711
 712         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 713         iopm_base = 0;
 714 }
 715
 716 static void init_seg(struct vmcb_seg *seg)
 717 {
 718         seg->selector = 0;
 719         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 720                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 721         seg->limit = 0xffff;
 722         seg->base = 0;
 723 }
 724
 725 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 726 {
 727         seg->selector = 0;
 728         seg->attrib = SVM_SELECTOR_P_MASK | type;
 729         seg->limit = 0xffff;
 730         seg->base = 0;
 731 }
 732
 733 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 734 {
 735         struct vcpu_svm *svm = to_svm(vcpu);
 736         u64 g_tsc_offset = 0;
 737
 738         if (is_nested(svm)) {
 739                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 740                                svm->nested.hsave->control.tsc_offset;
 741                 svm->nested.hsave->control.tsc_offset = offset;
 742         }
 743
 744         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 745 }
 746
 747 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
 748 {
 749         struct vcpu_svm *svm = to_svm(vcpu);
 750
 751         svm->vmcb->control.tsc_offset += adjustment;
 752         if (is_nested(svm))
 753                 svm->nested.hsave->control.tsc_offset += adjustment;
 754 }
 755
 756 static void init_vmcb(struct vcpu_svm *svm)
 757 {
 758         struct vmcb_control_area *control = &svm->vmcb->control;
 759         struct vmcb_save_area *save = &svm->vmcb->save;
 760
 761         svm->vcpu.fpu_active = 1;
 762
 763         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 764                                         INTERCEPT_CR3_MASK |
 765                                         INTERCEPT_CR4_MASK;
 766
 767         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 768                                         INTERCEPT_CR3_MASK |
 769                                         INTERCEPT_CR4_MASK |
 770                                         INTERCEPT_CR8_MASK;
 771
 772         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 773                                         INTERCEPT_DR1_MASK |
 774                                         INTERCEPT_DR2_MASK |
 775                                         INTERCEPT_DR3_MASK |
 776                                         INTERCEPT_DR4_MASK |
 777                                         INTERCEPT_DR5_MASK |
 778                                         INTERCEPT_DR6_MASK |
 779                                         INTERCEPT_DR7_MASK;
 780
 781         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 782                                         INTERCEPT_DR1_MASK |
 783                                         INTERCEPT_DR2_MASK |
 784                                         INTERCEPT_DR3_MASK |
 785                                         INTERCEPT_DR4_MASK |
 786                                         INTERCEPT_DR5_MASK |
 787                                         INTERCEPT_DR6_MASK |
 788                                         INTERCEPT_DR7_MASK;
 789
 790         control->intercept_exceptions = (1 << PF_VECTOR) |
 791                                         (1 << UD_VECTOR) |
 792                                         (1 << MC_VECTOR);
 793
 794
 795         control->intercept =    (1ULL << INTERCEPT_INTR) |
 796                                 (1ULL << INTERCEPT_NMI) |
 797                                 (1ULL << INTERCEPT_SMI) |
 798                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 799                                 (1ULL << INTERCEPT_CPUID) |
 800                                 (1ULL << INTERCEPT_INVD) |
 801                                 (1ULL << INTERCEPT_HLT) |
 802                                 (1ULL << INTERCEPT_INVLPG) |
 803                                 (1ULL << INTERCEPT_INVLPGA) |
 804                                 (1ULL << INTERCEPT_IOIO_PROT) |
 805                                 (1ULL << INTERCEPT_MSR_PROT) |
 806                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 807                                 (1ULL << INTERCEPT_SHUTDOWN) |
 808                                 (1ULL << INTERCEPT_VMRUN) |
 809                                 (1ULL << INTERCEPT_VMMCALL) |
 810                                 (1ULL << INTERCEPT_VMLOAD) |
 811                                 (1ULL << INTERCEPT_VMSAVE) |
 812                                 (1ULL << INTERCEPT_STGI) |
 813                                 (1ULL << INTERCEPT_CLGI) |
 814                                 (1ULL << INTERCEPT_SKINIT) |
 815                                 (1ULL << INTERCEPT_WBINVD) |
 816                                 (1ULL << INTERCEPT_MONITOR) |
 817                                 (1ULL << INTERCEPT_MWAIT);
 818
 819         control->iopm_base_pa = iopm_base;
 820         control->msrpm_base_pa = __pa(svm->msrpm);
 821         control->int_ctl = V_INTR_MASKING_MASK;
 822
 823         init_seg(&save->es);
 824         init_seg(&save->ss);
 825         init_seg(&save->ds);
 826         init_seg(&save->fs);
 827         init_seg(&save->gs);
 828
 829         save->cs.selector = 0xf000;
 830         /* Executable/Readable Code Segment */
 831         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 832                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 833         save->cs.limit = 0xffff;
 834         /*
 835          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 836          * be consistent with it.
 837          *
 838          * Replace when we have real mode working for vmx.
 839          */
 840         save->cs.base = 0xf0000;
 841
 842         save->gdtr.limit = 0xffff;
 843         save->idtr.limit = 0xffff;
 844
 845         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 846         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 847
 848         svm_set_efer(&svm->vcpu, 0);
 849         save->dr6 = 0xffff0ff0;
 850         save->dr7 = 0x400;
 851         save->rflags = 2;
 852         save->rip = 0x0000fff0;
 853         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 854
 855         /*
 856          * This is the guest-visible cr0 value.
 857          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 858          */
 859         svm->vcpu.arch.cr0 = 0;
 860         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
 861
 862         save->cr4 = X86_CR4_PAE;
 863         /* rdx = ?? */
 864
 865         if (npt_enabled) {
 866                 /* Setup VMCB for Nested Paging */
 867                 control->nested_ctl = 1;
 868                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 869                                         (1ULL << INTERCEPT_INVLPG));
 870                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 871                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 872                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 873                 save->g_pat = 0x0007040600070406ULL;
 874                 save->cr3 = 0;
 875                 save->cr4 = 0;
 876         }
 877         force_new_asid(&svm->vcpu);
 878
 879         svm->nested.vmcb = 0;
 880         svm->vcpu.arch.hflags = 0;
 881
 882         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 883                 control->pause_filter_count = 3000;
 884                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 885         }
 886
 887         enable_gif(svm);
 888 }
 889
 890 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 891 {
 892         struct vcpu_svm *svm = to_svm(vcpu);
 893
 894         init_vmcb(svm);
 895
 896         if (!kvm_vcpu_is_bsp(vcpu)) {
 897                 kvm_rip_write(vcpu, 0);
 898                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 899                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 900         }
 901         vcpu->arch.regs_avail = ~0;
 902         vcpu->arch.regs_dirty = ~0;
 903
 904         return 0;
 905 }
 906
 907 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 908 {
 909         struct vcpu_svm *svm;
 910         struct page *page;
 911         struct page *msrpm_pages;
 912         struct page *hsave_page;
 913         struct page *nested_msrpm_pages;
 914         int err;
 915
 916         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 917         if (!svm) {
 918                 err = -ENOMEM;
 919                 goto out;
 920         }
 921
 922         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 923         if (err)
 924                 goto free_svm;
 925
 926         err = -ENOMEM;
 927         page = alloc_page(GFP_KERNEL);
 928         if (!page)
 929                 goto uninit;
 930
 931         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 932         if (!msrpm_pages)
 933                 goto free_page1;
 934
 935         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 936         if (!nested_msrpm_pages)
 937                 goto free_page2;
 938
 939         hsave_page = alloc_page(GFP_KERNEL);
 940         if (!hsave_page)
 941                 goto free_page3;
 942
 943         svm->nested.hsave = page_address(hsave_page);
 944
 945         svm->msrpm = page_address(msrpm_pages);
 946         svm_vcpu_init_msrpm(svm->msrpm);
 947
 948         svm->nested.msrpm = page_address(nested_msrpm_pages);
 949         svm_vcpu_init_msrpm(svm->nested.msrpm);
 950
 951         svm->vmcb = page_address(page);
 952         clear_page(svm->vmcb);
 953         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 954         svm->asid_generation = 0;
 955         init_vmcb(svm);
 956         kvm_write_tsc(&svm->vcpu, 0);
 957
 958         err = fx_init(&svm->vcpu);
 959         if (err)
 960                 goto free_page4;
 961
 962         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 963         if (kvm_vcpu_is_bsp(&svm->vcpu))
 964                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 965
 966         return &svm->vcpu;
 967
 968 free_page4:
 969         __free_page(hsave_page);
 970 free_page3:
 971         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 972 free_page2:
 973         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 974 free_page1:
 975         __free_page(page);
 976 uninit:
 977         kvm_vcpu_uninit(&svm->vcpu);
 978 free_svm:
 979         kmem_cache_free(kvm_vcpu_cache, svm);
 980 out:
 981         return ERR_PTR(err);
 982 }
 983
 984 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 985 {
 986         struct vcpu_svm *svm = to_svm(vcpu);
 987
 988         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 989         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 990         __free_page(virt_to_page(svm->nested.hsave));
 991         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 992         kvm_vcpu_uninit(vcpu);
 993         kmem_cache_free(kvm_vcpu_cache, svm);
 994 }
 995
 996 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 997 {
 998         struct vcpu_svm *svm = to_svm(vcpu);
 999         int i;
1000
1001         if (unlikely(cpu != vcpu->cpu)) {
1002                 svm->asid_generation = 0;
1003         }
1004
1005         save_host_msrs(vcpu);
1006         savesegment(fs, svm->host.fs);
1007         savesegment(gs, svm->host.gs);
1008         svm->host.ldt = kvm_read_ldt();
1009
1010         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1011                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1012 }
1013
1014 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1015 {
1016         struct vcpu_svm *svm = to_svm(vcpu);
1017         int i;
1018
1019         ++vcpu->stat.host_state_reload;
1020         kvm_load_ldt(svm->host.ldt);
1021 #ifdef CONFIG_X86_64
1022         loadsegment(fs, svm->host.fs);
1023         load_gs_index(svm->host.gs);
1024         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1025 #else
1026         loadsegment(gs, svm->host.gs);
1027 #endif
1028         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1029                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1030 }
1031
1032 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1033 {
1034         return to_svm(vcpu)->vmcb->save.rflags;
1035 }
1036
1037 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1038 {
1039         to_svm(vcpu)->vmcb->save.rflags = rflags;
1040 }
1041
1042 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1043 {
1044         switch (reg) {
1045         case VCPU_EXREG_PDPTR:
1046                 BUG_ON(!npt_enabled);
1047                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1048                 break;
1049         default:
1050                 BUG();
1051         }
1052 }
1053
1054 static void svm_set_vintr(struct vcpu_svm *svm)
1055 {
1056         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1057 }
1058
1059 static void svm_clear_vintr(struct vcpu_svm *svm)
1060 {
1061         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1062 }
1063
1064 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1065 {
1066         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1067
1068         switch (seg) {
1069         case VCPU_SREG_CS: return &save->cs;
1070         case VCPU_SREG_DS: return &save->ds;
1071         case VCPU_SREG_ES: return &save->es;
1072         case VCPU_SREG_FS: return &save->fs;
1073         case VCPU_SREG_GS: return &save->gs;
1074         case VCPU_SREG_SS: return &save->ss;
1075         case VCPU_SREG_TR: return &save->tr;
1076         case VCPU_SREG_LDTR: return &save->ldtr;
1077         }
1078         BUG();
1079         return NULL;
1080 }
1081
1082 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1083 {
1084         struct vmcb_seg *s = svm_seg(vcpu, seg);
1085
1086         return s->base;
1087 }
1088
1089 static void svm_get_segment(struct kvm_vcpu *vcpu,
1090                             struct kvm_segment *var, int seg)
1091 {
1092         struct vmcb_seg *s = svm_seg(vcpu, seg);
1093
1094         var->base = s->base;
1095         var->limit = s->limit;
1096         var->selector = s->selector;
1097         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1098         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1099         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1100         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1101         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1102         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1103         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1104         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1105
1106         /*
1107          * AMD's VMCB does not have an explicit unusable field, so emulate it
1108          * for cross vendor migration purposes by "not present"
1109          */
1110         var->unusable = !var->present || (var->type == 0);
1111
1112         switch (seg) {
1113         case VCPU_SREG_CS:
1114                 /*
1115                  * SVM always stores 0 for the 'G' bit in the CS selector in
1116                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1117                  * Intel's VMENTRY has a check on the 'G' bit.
1118                  */
1119                 var->g = s->limit > 0xfffff;
1120                 break;
1121         case VCPU_SREG_TR:
1122                 /*
1123                  * Work around a bug where the busy flag in the tr selector
1124                  * isn't exposed
1125                  */
1126                 var->type |= 0x2;
1127                 break;
1128         case VCPU_SREG_DS:
1129         case VCPU_SREG_ES:
1130         case VCPU_SREG_FS:
1131         case VCPU_SREG_GS:
1132                 /*
1133                  * The accessed bit must always be set in the segment
1134                  * descriptor cache, although it can be cleared in the
1135                  * descriptor, the cached bit always remains at 1. Since
1136                  * Intel has a check on this, set it here to support
1137                  * cross-vendor migration.
1138                  */
1139                 if (!var->unusable)
1140                         var->type |= 0x1;
1141                 break;
1142         case VCPU_SREG_SS:
1143                 /*
1144                  * On AMD CPUs sometimes the DB bit in the segment
1145                  * descriptor is left as 1, although the whole segment has
1146                  * been made unusable. Clear it here to pass an Intel VMX
1147                  * entry check when cross vendor migrating.
1148                  */
1149                 if (var->unusable)
1150                         var->db = 0;
1151                 break;
1152         }
1153 }
1154
1155 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1156 {
1157         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1158
1159         return save->cpl;
1160 }
1161
1162 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1163 {
1164         struct vcpu_svm *svm = to_svm(vcpu);
1165
1166         dt->size = svm->vmcb->save.idtr.limit;
1167         dt->address = svm->vmcb->save.idtr.base;
1168 }
1169
1170 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1171 {
1172         struct vcpu_svm *svm = to_svm(vcpu);
1173
1174         svm->vmcb->save.idtr.limit = dt->size;
1175         svm->vmcb->save.idtr.base = dt->address ;
1176 }
1177
1178 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1179 {
1180         struct vcpu_svm *svm = to_svm(vcpu);
1181
1182         dt->size = svm->vmcb->save.gdtr.limit;
1183         dt->address = svm->vmcb->save.gdtr.base;
1184 }
1185
1186 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1187 {
1188         struct vcpu_svm *svm = to_svm(vcpu);
1189
1190         svm->vmcb->save.gdtr.limit = dt->size;
1191         svm->vmcb->save.gdtr.base = dt->address ;
1192 }
1193
1194 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1195 {
1196 }
1197
1198 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1199 {
1200 }
1201
1202 static void update_cr0_intercept(struct vcpu_svm *svm)
1203 {
1204         struct vmcb *vmcb = svm->vmcb;
1205         ulong gcr0 = svm->vcpu.arch.cr0;
1206         u64 *hcr0 = &svm->vmcb->save.cr0;
1207
1208         if (!svm->vcpu.fpu_active)
1209                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1210         else
1211                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1212                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1213
1214
1215         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1216                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1217                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1218                 if (is_nested(svm)) {
1219                         struct vmcb *hsave = svm->nested.hsave;
1220
1221                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1222                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1223                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1224                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1225                 }
1226         } else {
1227                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1228                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1229                 if (is_nested(svm)) {
1230                         struct vmcb *hsave = svm->nested.hsave;
1231
1232                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1233                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1234                 }
1235         }
1236 }
1237
1238 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1239 {
1240         struct vcpu_svm *svm = to_svm(vcpu);
1241
1242         if (is_nested(svm)) {
1243                 /*
1244                  * We are here because we run in nested mode, the host kvm
1245                  * intercepts cr0 writes but the l1 hypervisor does not.
1246                  * But the L1 hypervisor may intercept selective cr0 writes.
1247                  * This needs to be checked here.
1248                  */
1249                 unsigned long old, new;
1250
1251                 /* Remove bits that would trigger a real cr0 write intercept */
1252                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1253                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1254
1255                 if (old == new) {
1256                         /* cr0 write with ts and mp unchanged */
1257                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1258                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1259                                 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1260                                 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1261                                 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1262                                 return;
1263                         }
1264                 }
1265         }
1266
1267 #ifdef CONFIG_X86_64
1268         if (vcpu->arch.efer & EFER_LME) {
1269                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1270                         vcpu->arch.efer |= EFER_LMA;
1271                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1272                 }
1273
1274                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1275                         vcpu->arch.efer &= ~EFER_LMA;
1276                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1277                 }
1278         }
1279 #endif
1280         vcpu->arch.cr0 = cr0;
1281
1282         if (!npt_enabled)
1283                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1284
1285         if (!vcpu->fpu_active)
1286                 cr0 |= X86_CR0_TS;
1287         /*
1288          * re-enable caching here because the QEMU bios
1289          * does not do it - this results in some delay at
1290          * reboot
1291          */
1292         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1293         svm->vmcb->save.cr0 = cr0;
1294         update_cr0_intercept(svm);
1295 }
1296
1297 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1298 {
1299         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1300         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1301
1302         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1303                 force_new_asid(vcpu);
1304
1305         vcpu->arch.cr4 = cr4;
1306         if (!npt_enabled)
1307                 cr4 |= X86_CR4_PAE;
1308         cr4 |= host_cr4_mce;
1309         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1310 }
1311
1312 static void svm_set_segment(struct kvm_vcpu *vcpu,
1313                             struct kvm_segment *var, int seg)
1314 {
1315         struct vcpu_svm *svm = to_svm(vcpu);
1316         struct vmcb_seg *s = svm_seg(vcpu, seg);
1317
1318         s->base = var->base;
1319         s->limit = var->limit;
1320         s->selector = var->selector;
1321         if (var->unusable)
1322                 s->attrib = 0;
1323         else {
1324                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1325                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1326                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1327                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1328                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1329                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1330                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1331                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1332         }
1333         if (seg == VCPU_SREG_CS)
1334                 svm->vmcb->save.cpl
1335                         = (svm->vmcb->save.cs.attrib
1336                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1337
1338 }
1339
1340 static void update_db_intercept(struct kvm_vcpu *vcpu)
1341 {
1342         struct vcpu_svm *svm = to_svm(vcpu);
1343
1344         svm->vmcb->control.intercept_exceptions &=
1345                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1346
1347         if (svm->nmi_singlestep)
1348                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1349
1350         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1351                 if (vcpu->guest_debug &
1352                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1353                         svm->vmcb->control.intercept_exceptions |=
1354                                 1 << DB_VECTOR;
1355                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1356                         svm->vmcb->control.intercept_exceptions |=
1357                                 1 << BP_VECTOR;
1358         } else
1359                 vcpu->guest_debug = 0;
1360 }
1361
1362 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1363 {
1364         struct vcpu_svm *svm = to_svm(vcpu);
1365
1366         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1367                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1368         else
1369                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1370
1371         update_db_intercept(vcpu);
1372 }
1373
1374 static void load_host_msrs(struct kvm_vcpu *vcpu)
1375 {
1376 #ifdef CONFIG_X86_64
1377         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1378 #endif
1379 }
1380
1381 static void save_host_msrs(struct kvm_vcpu *vcpu)
1382 {
1383 #ifdef CONFIG_X86_64
1384         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1385 #endif
1386 }
1387
1388 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1389 {
1390         if (sd->next_asid > sd->max_asid) {
1391                 ++sd->asid_generation;
1392                 sd->next_asid = 1;
1393                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1394         }
1395
1396         svm->asid_generation = sd->asid_generation;
1397         svm->vmcb->control.asid = sd->next_asid++;
1398 }
1399
1400 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1401 {
1402         struct vcpu_svm *svm = to_svm(vcpu);
1403
1404         svm->vmcb->save.dr7 = value;
1405 }
1406
1407 static int pf_interception(struct vcpu_svm *svm)
1408 {
1409         u64 fault_address = svm->vmcb->control.exit_info_2;
1410         u32 error_code;
1411         int r = 1;
1412
1413         switch (svm->apf_reason) {
1414         default:
1415                 error_code = svm->vmcb->control.exit_info_1;
1416
1417                 trace_kvm_page_fault(fault_address, error_code);
1418                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1419                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1420                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1421                 break;
1422         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1423                 svm->apf_reason = 0;
1424                 local_irq_disable();
1425                 kvm_async_pf_task_wait(fault_address);
1426                 local_irq_enable();
1427                 break;
1428         case KVM_PV_REASON_PAGE_READY:
1429                 svm->apf_reason = 0;
1430                 local_irq_disable();
1431                 kvm_async_pf_task_wake(fault_address);
1432                 local_irq_enable();
1433                 break;
1434         }
1435         return r;
1436 }
1437
1438 static int db_interception(struct vcpu_svm *svm)
1439 {
1440         struct kvm_run *kvm_run = svm->vcpu.run;
1441
1442         if (!(svm->vcpu.guest_debug &
1443               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1444                 !svm->nmi_singlestep) {
1445                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1446                 return 1;
1447         }
1448
1449         if (svm->nmi_singlestep) {
1450                 svm->nmi_singlestep = false;
1451                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1452                         svm->vmcb->save.rflags &=
1453                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1454                 update_db_intercept(&svm->vcpu);
1455         }
1456
1457         if (svm->vcpu.guest_debug &
1458             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1459                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1460                 kvm_run->debug.arch.pc =
1461                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1462                 kvm_run->debug.arch.exception = DB_VECTOR;
1463                 return 0;
1464         }
1465
1466         return 1;
1467 }
1468
1469 static int bp_interception(struct vcpu_svm *svm)
1470 {
1471         struct kvm_run *kvm_run = svm->vcpu.run;
1472
1473         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1474         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1475         kvm_run->debug.arch.exception = BP_VECTOR;
1476         return 0;
1477 }
1478
1479 static int ud_interception(struct vcpu_svm *svm)
1480 {
1481         int er;
1482
1483         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1484         if (er != EMULATE_DONE)
1485                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1486         return 1;
1487 }
1488
1489 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1490 {
1491         struct vcpu_svm *svm = to_svm(vcpu);
1492         u32 excp;
1493
1494         if (is_nested(svm)) {
1495                 u32 h_excp, n_excp;
1496
1497                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1498                 n_excp  = svm->nested.intercept_exceptions;
1499                 h_excp &= ~(1 << NM_VECTOR);
1500                 excp    = h_excp | n_excp;
1501         } else {
1502                 excp  = svm->vmcb->control.intercept_exceptions;
1503                 excp &= ~(1 << NM_VECTOR);
1504         }
1505
1506         svm->vmcb->control.intercept_exceptions = excp;
1507
1508         svm->vcpu.fpu_active = 1;
1509         update_cr0_intercept(svm);
1510 }
1511
1512 static int nm_interception(struct vcpu_svm *svm)
1513 {
1514         svm_fpu_activate(&svm->vcpu);
1515         return 1;
1516 }
1517
1518 static bool is_erratum_383(void)
1519 {
1520         int err, i;
1521         u64 value;
1522
1523         if (!erratum_383_found)
1524                 return false;
1525
1526         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1527         if (err)
1528                 return false;
1529
1530         /* Bit 62 may or may not be set for this mce */
1531         value &= ~(1ULL << 62);
1532
1533         if (value != 0xb600000000010015ULL)
1534                 return false;
1535
1536         /* Clear MCi_STATUS registers */
1537         for (i = 0; i < 6; ++i)
1538                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1539
1540         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1541         if (!err) {
1542                 u32 low, high;
1543
1544                 value &= ~(1ULL << 2);
1545                 low    = lower_32_bits(value);
1546                 high   = upper_32_bits(value);
1547
1548                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1549         }
1550
1551         /* Flush tlb to evict multi-match entries */
1552         __flush_tlb_all();
1553
1554         return true;
1555 }
1556
1557 static void svm_handle_mce(struct vcpu_svm *svm)
1558 {
1559         if (is_erratum_383()) {
1560                 /*
1561                  * Erratum 383 triggered. Guest state is corrupt so kill the
1562                  * guest.
1563                  */
1564                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1565
1566                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1567
1568                 return;
1569         }
1570
1571         /*
1572          * On an #MC intercept the MCE handler is not called automatically in
1573          * the host. So do it by hand here.
1574          */
1575         asm volatile (
1576                 "int $0x12\n");
1577         /* not sure if we ever come back to this point */
1578
1579         return;
1580 }
1581
1582 static int mc_interception(struct vcpu_svm *svm)
1583 {
1584         return 1;
1585 }
1586
1587 static int shutdown_interception(struct vcpu_svm *svm)
1588 {
1589         struct kvm_run *kvm_run = svm->vcpu.run;
1590
1591         /*
1592          * VMCB is undefined after a SHUTDOWN intercept
1593          * so reinitialize it.
1594          */
1595         clear_page(svm->vmcb);
1596         init_vmcb(svm);
1597
1598         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1599         return 0;
1600 }
1601
1602 static int io_interception(struct vcpu_svm *svm)
1603 {
1604         struct kvm_vcpu *vcpu = &svm->vcpu;
1605         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1606         int size, in, string;
1607         unsigned port;
1608
1609         ++svm->vcpu.stat.io_exits;
1610         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1611         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1612         if (string || in)
1613                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1614
1615         port = io_info >> 16;
1616         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1617         svm->next_rip = svm->vmcb->control.exit_info_2;
1618         skip_emulated_instruction(&svm->vcpu);
1619
1620         return kvm_fast_pio_out(vcpu, size, port);
1621 }
1622
1623 static int nmi_interception(struct vcpu_svm *svm)
1624 {
1625         return 1;
1626 }
1627
1628 static int intr_interception(struct vcpu_svm *svm)
1629 {
1630         ++svm->vcpu.stat.irq_exits;
1631         return 1;
1632 }
1633
1634 static int nop_on_interception(struct vcpu_svm *svm)
1635 {
1636         return 1;
1637 }
1638
1639 static int halt_interception(struct vcpu_svm *svm)
1640 {
1641         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1642         skip_emulated_instruction(&svm->vcpu);
1643         return kvm_emulate_halt(&svm->vcpu);
1644 }
1645
1646 static int vmmcall_interception(struct vcpu_svm *svm)
1647 {
1648         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1649         skip_emulated_instruction(&svm->vcpu);
1650         kvm_emulate_hypercall(&svm->vcpu);
1651         return 1;
1652 }
1653
1654 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1655 {
1656         struct vcpu_svm *svm = to_svm(vcpu);
1657
1658         return svm->nested.nested_cr3;
1659 }
1660
1661 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1662                                    unsigned long root)
1663 {
1664         struct vcpu_svm *svm = to_svm(vcpu);
1665
1666         svm->vmcb->control.nested_cr3 = root;
1667         force_new_asid(vcpu);
1668 }
1669
1670 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu)
1671 {
1672         struct vcpu_svm *svm = to_svm(vcpu);
1673
1674         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1675         svm->vmcb->control.exit_code_hi = 0;
1676         svm->vmcb->control.exit_info_1 = vcpu->arch.fault.error_code;
1677         svm->vmcb->control.exit_info_2 = vcpu->arch.fault.address;
1678
1679         nested_svm_vmexit(svm);
1680 }
1681
1682 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1683 {
1684         int r;
1685
1686         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1687
1688         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1689         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1690         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1691         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1692         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1693
1694         return r;
1695 }
1696
1697 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1698 {
1699         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1700 }
1701
1702 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1703 {
1704         if (!(svm->vcpu.arch.efer & EFER_SVME)
1705             || !is_paging(&svm->vcpu)) {
1706                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1707                 return 1;
1708         }
1709
1710         if (svm->vmcb->save.cpl) {
1711                 kvm_inject_gp(&svm->vcpu, 0);
1712                 return 1;
1713         }
1714
1715        return 0;
1716 }
1717
1718 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1719                                       bool has_error_code, u32 error_code)
1720 {
1721         int vmexit;
1722
1723         if (!is_nested(svm))
1724                 return 0;
1725
1726         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1727         svm->vmcb->control.exit_code_hi = 0;
1728         svm->vmcb->control.exit_info_1 = error_code;
1729         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1730
1731         vmexit = nested_svm_intercept(svm);
1732         if (vmexit == NESTED_EXIT_DONE)
1733                 svm->nested.exit_required = true;
1734
1735         return vmexit;
1736 }
1737
1738 /* This function returns true if it is save to enable the irq window */
1739 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1740 {
1741         if (!is_nested(svm))
1742                 return true;
1743
1744         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1745                 return true;
1746
1747         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1748                 return false;
1749
1750         /*
1751          * if vmexit was already requested (by intercepted exception
1752          * for instance) do not overwrite it with "external interrupt"
1753          * vmexit.
1754          */
1755         if (svm->nested.exit_required)
1756                 return false;
1757
1758         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1759         svm->vmcb->control.exit_info_1 = 0;
1760         svm->vmcb->control.exit_info_2 = 0;
1761
1762         if (svm->nested.intercept & 1ULL) {
1763                 /*
1764                  * The #vmexit can't be emulated here directly because this
1765                  * code path runs with irqs and preemtion disabled. A
1766                  * #vmexit emulation might sleep. Only signal request for
1767                  * the #vmexit here.
1768                  */
1769                 svm->nested.exit_required = true;
1770                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1771                 return false;
1772         }
1773
1774         return true;
1775 }
1776
1777 /* This function returns true if it is save to enable the nmi window */
1778 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1779 {
1780         if (!is_nested(svm))
1781                 return true;
1782
1783         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1784                 return true;
1785
1786         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1787         svm->nested.exit_required = true;
1788
1789         return false;
1790 }
1791
1792 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1793 {
1794         struct page *page;
1795
1796         might_sleep();
1797
1798         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1799         if (is_error_page(page))
1800                 goto error;
1801
1802         *_page = page;
1803
1804         return kmap(page);
1805
1806 error:
1807         kvm_release_page_clean(page);
1808         kvm_inject_gp(&svm->vcpu, 0);
1809
1810         return NULL;
1811 }
1812
1813 static void nested_svm_unmap(struct page *page)
1814 {
1815         kunmap(page);
1816         kvm_release_page_dirty(page);
1817 }
1818
1819 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1820 {
1821         unsigned port;
1822         u8 val, bit;
1823         u64 gpa;
1824
1825         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1826                 return NESTED_EXIT_HOST;
1827
1828         port = svm->vmcb->control.exit_info_1 >> 16;
1829         gpa  = svm->nested.vmcb_iopm + (port / 8);
1830         bit  = port % 8;
1831         val  = 0;
1832
1833         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1834                 val &= (1 << bit);
1835
1836         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1837 }
1838
1839 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1840 {
1841         u32 offset, msr, value;
1842         int write, mask;
1843
1844         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1845                 return NESTED_EXIT_HOST;
1846
1847         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1848         offset = svm_msrpm_offset(msr);
1849         write  = svm->vmcb->control.exit_info_1 & 1;
1850         mask   = 1 << ((2 * (msr & 0xf)) + write);
1851
1852         if (offset == MSR_INVALID)
1853                 return NESTED_EXIT_DONE;
1854
1855         /* Offset is in 32 bit units but need in 8 bit units */
1856         offset *= 4;
1857
1858         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1859                 return NESTED_EXIT_DONE;
1860
1861         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1862 }
1863
1864 static int nested_svm_exit_special(struct vcpu_svm *svm)
1865 {
1866         u32 exit_code = svm->vmcb->control.exit_code;
1867
1868         switch (exit_code) {
1869         case SVM_EXIT_INTR:
1870         case SVM_EXIT_NMI:
1871         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1872                 return NESTED_EXIT_HOST;
1873         case SVM_EXIT_NPF:
1874                 /* For now we are always handling NPFs when using them */
1875                 if (npt_enabled)
1876                         return NESTED_EXIT_HOST;
1877                 break;
1878         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1879                 /* When we're shadowing, trap PFs, but not async PF */
1880                 if (!npt_enabled && svm->apf_reason == 0)
1881                         return NESTED_EXIT_HOST;
1882                 break;
1883         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1884                 nm_interception(svm);
1885                 break;
1886         default:
1887                 break;
1888         }
1889
1890         return NESTED_EXIT_CONTINUE;
1891 }
1892
1893 /*
1894  * If this function returns true, this #vmexit was already handled
1895  */
1896 static int nested_svm_intercept(struct vcpu_svm *svm)
1897 {
1898         u32 exit_code = svm->vmcb->control.exit_code;
1899         int vmexit = NESTED_EXIT_HOST;
1900
1901         switch (exit_code) {
1902         case SVM_EXIT_MSR:
1903                 vmexit = nested_svm_exit_handled_msr(svm);
1904                 break;
1905         case SVM_EXIT_IOIO:
1906                 vmexit = nested_svm_intercept_ioio(svm);
1907                 break;
1908         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1909                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1910                 if (svm->nested.intercept_cr_read & cr_bits)
1911                         vmexit = NESTED_EXIT_DONE;
1912                 break;
1913         }
1914         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1915                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1916                 if (svm->nested.intercept_cr_write & cr_bits)
1917                         vmexit = NESTED_EXIT_DONE;
1918                 break;
1919         }
1920         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1921                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1922                 if (svm->nested.intercept_dr_read & dr_bits)
1923                         vmexit = NESTED_EXIT_DONE;
1924                 break;
1925         }
1926         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1927                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1928                 if (svm->nested.intercept_dr_write & dr_bits)
1929                         vmexit = NESTED_EXIT_DONE;
1930                 break;
1931         }
1932         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1933                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1934                 if (svm->nested.intercept_exceptions & excp_bits)
1935                         vmexit = NESTED_EXIT_DONE;
1936                 /* async page fault always cause vmexit */
1937                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
1938                          svm->apf_reason != 0)
1939                         vmexit = NESTED_EXIT_DONE;
1940                 break;
1941         }
1942         case SVM_EXIT_ERR: {
1943                 vmexit = NESTED_EXIT_DONE;
1944                 break;
1945         }
1946         default: {
1947                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1948                 if (svm->nested.intercept & exit_bits)
1949                         vmexit = NESTED_EXIT_DONE;
1950         }
1951         }
1952
1953         return vmexit;
1954 }
1955
1956 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1957 {
1958         int vmexit;
1959
1960         vmexit = nested_svm_intercept(svm);
1961
1962         if (vmexit == NESTED_EXIT_DONE)
1963                 nested_svm_vmexit(svm);
1964
1965         return vmexit;
1966 }
1967
1968 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1969 {
1970         struct vmcb_control_area *dst  = &dst_vmcb->control;
1971         struct vmcb_control_area *from = &from_vmcb->control;
1972
1973         dst->intercept_cr_read    = from->intercept_cr_read;
1974         dst->intercept_cr_write   = from->intercept_cr_write;
1975         dst->intercept_dr_read    = from->intercept_dr_read;
1976         dst->intercept_dr_write   = from->intercept_dr_write;
1977         dst->intercept_exceptions = from->intercept_exceptions;
1978         dst->intercept            = from->intercept;
1979         dst->iopm_base_pa         = from->iopm_base_pa;
1980         dst->msrpm_base_pa        = from->msrpm_base_pa;
1981         dst->tsc_offset           = from->tsc_offset;
1982         dst->asid                 = from->asid;
1983         dst->tlb_ctl              = from->tlb_ctl;
1984         dst->int_ctl              = from->int_ctl;
1985         dst->int_vector           = from->int_vector;
1986         dst->int_state            = from->int_state;
1987         dst->exit_code            = from->exit_code;
1988         dst->exit_code_hi         = from->exit_code_hi;
1989         dst->exit_info_1          = from->exit_info_1;
1990         dst->exit_info_2          = from->exit_info_2;
1991         dst->exit_int_info        = from->exit_int_info;
1992         dst->exit_int_info_err    = from->exit_int_info_err;
1993         dst->nested_ctl           = from->nested_ctl;
1994         dst->event_inj            = from->event_inj;
1995         dst->event_inj_err        = from->event_inj_err;
1996         dst->nested_cr3           = from->nested_cr3;
1997         dst->lbr_ctl              = from->lbr_ctl;
1998 }
1999
2000 static int nested_svm_vmexit(struct vcpu_svm *svm)
2001 {
2002         struct vmcb *nested_vmcb;
2003         struct vmcb *hsave = svm->nested.hsave;
2004         struct vmcb *vmcb = svm->vmcb;
2005         struct page *page;
2006
2007         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2008                                        vmcb->control.exit_info_1,
2009                                        vmcb->control.exit_info_2,
2010                                        vmcb->control.exit_int_info,
2011                                        vmcb->control.exit_int_info_err);
2012
2013         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2014         if (!nested_vmcb)
2015                 return 1;
2016
2017         /* Exit nested SVM mode */
2018         svm->nested.vmcb = 0;
2019
2020         /* Give the current vmcb to the guest */
2021         disable_gif(svm);
2022
2023         nested_vmcb->save.es     = vmcb->save.es;
2024         nested_vmcb->save.cs     = vmcb->save.cs;
2025         nested_vmcb->save.ss     = vmcb->save.ss;
2026         nested_vmcb->save.ds     = vmcb->save.ds;
2027         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2028         nested_vmcb->save.idtr   = vmcb->save.idtr;
2029         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2030         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2031         nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
2032         nested_vmcb->save.cr2    = vmcb->save.cr2;
2033         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2034         nested_vmcb->save.rflags = vmcb->save.rflags;
2035         nested_vmcb->save.rip    = vmcb->save.rip;
2036         nested_vmcb->save.rsp    = vmcb->save.rsp;
2037         nested_vmcb->save.rax    = vmcb->save.rax;
2038         nested_vmcb->save.dr7    = vmcb->save.dr7;
2039         nested_vmcb->save.dr6    = vmcb->save.dr6;
2040         nested_vmcb->save.cpl    = vmcb->save.cpl;
2041
2042         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2043         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2044         nested_vmcb->control.int_state         = vmcb->control.int_state;
2045         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2046         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2047         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2048         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2049         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2050         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2051         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2052
2053         /*
2054          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2055          * to make sure that we do not lose injected events. So check event_inj
2056          * here and copy it to exit_int_info if it is valid.
2057          * Exit_int_info and event_inj can't be both valid because the case
2058          * below only happens on a VMRUN instruction intercept which has
2059          * no valid exit_int_info set.
2060          */
2061         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2062                 struct vmcb_control_area *nc = &nested_vmcb->control;
2063
2064                 nc->exit_int_info     = vmcb->control.event_inj;
2065                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2066         }
2067
2068         nested_vmcb->control.tlb_ctl           = 0;
2069         nested_vmcb->control.event_inj         = 0;
2070         nested_vmcb->control.event_inj_err     = 0;
2071
2072         /* We always set V_INTR_MASKING and remember the old value in hflags */
2073         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2074                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2075
2076         /* Restore the original control entries */
2077         copy_vmcb_control_area(vmcb, hsave);
2078
2079         kvm_clear_exception_queue(&svm->vcpu);
2080         kvm_clear_interrupt_queue(&svm->vcpu);
2081
2082         svm->nested.nested_cr3 = 0;
2083
2084         /* Restore selected save entries */
2085         svm->vmcb->save.es = hsave->save.es;
2086         svm->vmcb->save.cs = hsave->save.cs;
2087         svm->vmcb->save.ss = hsave->save.ss;
2088         svm->vmcb->save.ds = hsave->save.ds;
2089         svm->vmcb->save.gdtr = hsave->save.gdtr;
2090         svm->vmcb->save.idtr = hsave->save.idtr;
2091         svm->vmcb->save.rflags = hsave->save.rflags;
2092         svm_set_efer(&svm->vcpu, hsave->save.efer);
2093         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2094         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2095         if (npt_enabled) {
2096                 svm->vmcb->save.cr3 = hsave->save.cr3;
2097                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2098         } else {
2099                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2100         }
2101         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2102         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2103         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2104         svm->vmcb->save.dr7 = 0;
2105         svm->vmcb->save.cpl = 0;
2106         svm->vmcb->control.exit_int_info = 0;
2107
2108         nested_svm_unmap(page);
2109
2110         nested_svm_uninit_mmu_context(&svm->vcpu);
2111         kvm_mmu_reset_context(&svm->vcpu);
2112         kvm_mmu_load(&svm->vcpu);
2113
2114         return 0;
2115 }
2116
2117 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2118 {
2119         /*
2120          * This function merges the msr permission bitmaps of kvm and the
2121          * nested vmcb. It is omptimized in that it only merges the parts where
2122          * the kvm msr permission bitmap may contain zero bits
2123          */
2124         int i;
2125
2126         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2127                 return true;
2128
2129         for (i = 0; i < MSRPM_OFFSETS; i++) {
2130                 u32 value, p;
2131                 u64 offset;
2132
2133                 if (msrpm_offsets[i] == 0xffffffff)
2134                         break;
2135
2136                 p      = msrpm_offsets[i];
2137                 offset = svm->nested.vmcb_msrpm + (p * 4);
2138
2139                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2140                         return false;
2141
2142                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2143         }
2144
2145         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2146
2147         return true;
2148 }
2149
2150 static bool nested_vmcb_checks(struct vmcb *vmcb)
2151 {
2152         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2153                 return false;
2154
2155         if (vmcb->control.asid == 0)
2156                 return false;
2157
2158         if (vmcb->control.nested_ctl && !npt_enabled)
2159                 return false;
2160
2161         return true;
2162 }
2163
2164 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2165 {
2166         struct vmcb *nested_vmcb;
2167         struct vmcb *hsave = svm->nested.hsave;
2168         struct vmcb *vmcb = svm->vmcb;
2169         struct page *page;
2170         u64 vmcb_gpa;
2171
2172         vmcb_gpa = svm->vmcb->save.rax;
2173
2174         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2175         if (!nested_vmcb)
2176                 return false;
2177
2178         if (!nested_vmcb_checks(nested_vmcb)) {
2179                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2180                 nested_vmcb->control.exit_code_hi = 0;
2181                 nested_vmcb->control.exit_info_1  = 0;
2182                 nested_vmcb->control.exit_info_2  = 0;
2183
2184                 nested_svm_unmap(page);
2185
2186                 return false;
2187         }
2188
2189         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2190                                nested_vmcb->save.rip,
2191                                nested_vmcb->control.int_ctl,
2192                                nested_vmcb->control.event_inj,
2193                                nested_vmcb->control.nested_ctl);
2194
2195         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2196                                     nested_vmcb->control.intercept_cr_write,
2197                                     nested_vmcb->control.intercept_exceptions,
2198                                     nested_vmcb->control.intercept);
2199
2200         /* Clear internal status */
2201         kvm_clear_exception_queue(&svm->vcpu);
2202         kvm_clear_interrupt_queue(&svm->vcpu);
2203
2204         /*
2205          * Save the old vmcb, so we don't need to pick what we save, but can
2206          * restore everything when a VMEXIT occurs
2207          */
2208         hsave->save.es     = vmcb->save.es;
2209         hsave->save.cs     = vmcb->save.cs;
2210         hsave->save.ss     = vmcb->save.ss;
2211         hsave->save.ds     = vmcb->save.ds;
2212         hsave->save.gdtr   = vmcb->save.gdtr;
2213         hsave->save.idtr   = vmcb->save.idtr;
2214         hsave->save.efer   = svm->vcpu.arch.efer;
2215         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2216         hsave->save.cr4    = svm->vcpu.arch.cr4;
2217         hsave->save.rflags = vmcb->save.rflags;
2218         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2219         hsave->save.rsp    = vmcb->save.rsp;
2220         hsave->save.rax    = vmcb->save.rax;
2221         if (npt_enabled)
2222                 hsave->save.cr3    = vmcb->save.cr3;
2223         else
2224                 hsave->save.cr3    = svm->vcpu.arch.cr3;
2225
2226         copy_vmcb_control_area(hsave, vmcb);
2227
2228         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2229                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2230         else
2231                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2232
2233         if (nested_vmcb->control.nested_ctl) {
2234                 kvm_mmu_unload(&svm->vcpu);
2235                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2236                 nested_svm_init_mmu_context(&svm->vcpu);
2237         }
2238
2239         /* Load the nested guest state */
2240         svm->vmcb->save.es = nested_vmcb->save.es;
2241         svm->vmcb->save.cs = nested_vmcb->save.cs;
2242         svm->vmcb->save.ss = nested_vmcb->save.ss;
2243         svm->vmcb->save.ds = nested_vmcb->save.ds;
2244         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2245         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2246         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2247         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2248         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2249         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2250         if (npt_enabled) {
2251                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2252                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2253         } else
2254                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2255
2256         /* Guest paging mode is active - reset mmu */
2257         kvm_mmu_reset_context(&svm->vcpu);
2258
2259         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2260         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2261         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2262         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2263
2264         /* In case we don't even reach vcpu_run, the fields are not updated */
2265         svm->vmcb->save.rax = nested_vmcb->save.rax;
2266         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2267         svm->vmcb->save.rip = nested_vmcb->save.rip;
2268         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2269         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2270         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2271
2272         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2273         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2274
2275         /* cache intercepts */
2276         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
2277         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
2278         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
2279         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
2280         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2281         svm->nested.intercept            = nested_vmcb->control.intercept;
2282
2283         force_new_asid(&svm->vcpu);
2284         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2285         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2286                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2287         else
2288                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2289
2290         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2291                 /* We only want the cr8 intercept bits of the guest */
2292                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2293                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2294         }
2295
2296         /* We don't want to see VMMCALLs from a nested guest */
2297         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2298
2299         /*
2300          * We don't want a nested guest to be more powerful than the guest, so
2301          * all intercepts are ORed
2302          */
2303         svm->vmcb->control.intercept_cr_read |=
2304                 nested_vmcb->control.intercept_cr_read;
2305         svm->vmcb->control.intercept_cr_write |=
2306                 nested_vmcb->control.intercept_cr_write;
2307         svm->vmcb->control.intercept_dr_read |=
2308                 nested_vmcb->control.intercept_dr_read;
2309         svm->vmcb->control.intercept_dr_write |=
2310                 nested_vmcb->control.intercept_dr_write;
2311         svm->vmcb->control.intercept_exceptions |=
2312                 nested_vmcb->control.intercept_exceptions;
2313
2314         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2315
2316         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2317         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2318         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2319         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2320         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2321         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2322
2323         nested_svm_unmap(page);
2324
2325         /* nested_vmcb is our indicator if nested SVM is activated */
2326         svm->nested.vmcb = vmcb_gpa;
2327
2328         enable_gif(svm);
2329
2330         return true;
2331 }
2332
2333 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2334 {
2335         to_vmcb->save.fs = from_vmcb->save.fs;
2336         to_vmcb->save.gs = from_vmcb->save.gs;
2337         to_vmcb->save.tr = from_vmcb->save.tr;
2338         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2339         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2340         to_vmcb->save.star = from_vmcb->save.star;
2341         to_vmcb->save.lstar = from_vmcb->save.lstar;
2342         to_vmcb->save.cstar = from_vmcb->save.cstar;
2343         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2344         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2345         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2346         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2347 }
2348
2349 static int vmload_interception(struct vcpu_svm *svm)
2350 {
2351         struct vmcb *nested_vmcb;
2352         struct page *page;
2353
2354         if (nested_svm_check_permissions(svm))
2355                 return 1;
2356
2357         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2358         skip_emulated_instruction(&svm->vcpu);
2359
2360         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2361         if (!nested_vmcb)
2362                 return 1;
2363
2364         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2365         nested_svm_unmap(page);
2366
2367         return 1;
2368 }
2369
2370 static int vmsave_interception(struct vcpu_svm *svm)
2371 {
2372         struct vmcb *nested_vmcb;
2373         struct page *page;
2374
2375         if (nested_svm_check_permissions(svm))
2376                 return 1;
2377
2378         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2379         skip_emulated_instruction(&svm->vcpu);
2380
2381         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2382         if (!nested_vmcb)
2383                 return 1;
2384
2385         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2386         nested_svm_unmap(page);
2387
2388         return 1;
2389 }
2390
2391 static int vmrun_interception(struct vcpu_svm *svm)
2392 {
2393         if (nested_svm_check_permissions(svm))
2394                 return 1;
2395
2396         /* Save rip after vmrun instruction */
2397         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2398
2399         if (!nested_svm_vmrun(svm))
2400                 return 1;
2401
2402         if (!nested_svm_vmrun_msrpm(svm))
2403                 goto failed;
2404
2405         return 1;
2406
2407 failed:
2408
2409         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2410         svm->vmcb->control.exit_code_hi = 0;
2411         svm->vmcb->control.exit_info_1  = 0;
2412         svm->vmcb->control.exit_info_2  = 0;
2413
2414         nested_svm_vmexit(svm);
2415
2416         return 1;
2417 }
2418
2419 static int stgi_interception(struct vcpu_svm *svm)
2420 {
2421         if (nested_svm_check_permissions(svm))
2422                 return 1;
2423
2424         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2425         skip_emulated_instruction(&svm->vcpu);
2426         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2427
2428         enable_gif(svm);
2429
2430         return 1;
2431 }
2432
2433 static int clgi_interception(struct vcpu_svm *svm)
2434 {
2435         if (nested_svm_check_permissions(svm))
2436                 return 1;
2437
2438         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2439         skip_emulated_instruction(&svm->vcpu);
2440
2441         disable_gif(svm);
2442
2443         /* After a CLGI no interrupts should come */
2444         svm_clear_vintr(svm);
2445         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2446
2447         return 1;
2448 }
2449
2450 static int invlpga_interception(struct vcpu_svm *svm)
2451 {
2452         struct kvm_vcpu *vcpu = &svm->vcpu;
2453
2454         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2455                           vcpu->arch.regs[VCPU_REGS_RAX]);
2456
2457         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2458         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2459
2460         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2461         skip_emulated_instruction(&svm->vcpu);
2462         return 1;
2463 }
2464
2465 static int skinit_interception(struct vcpu_svm *svm)
2466 {
2467         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2468
2469         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2470         return 1;
2471 }
2472
2473 static int invalid_op_interception(struct vcpu_svm *svm)
2474 {
2475         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2476         return 1;
2477 }
2478
2479 static int task_switch_interception(struct vcpu_svm *svm)
2480 {
2481         u16 tss_selector;
2482         int reason;
2483         int int_type = svm->vmcb->control.exit_int_info &
2484                 SVM_EXITINTINFO_TYPE_MASK;
2485         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2486         uint32_t type =
2487                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2488         uint32_t idt_v =
2489                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2490         bool has_error_code = false;
2491         u32 error_code = 0;
2492
2493         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2494
2495         if (svm->vmcb->control.exit_info_2 &
2496             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2497                 reason = TASK_SWITCH_IRET;
2498         else if (svm->vmcb->control.exit_info_2 &
2499                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2500                 reason = TASK_SWITCH_JMP;
2501         else if (idt_v)
2502                 reason = TASK_SWITCH_GATE;
2503         else
2504                 reason = TASK_SWITCH_CALL;
2505
2506         if (reason == TASK_SWITCH_GATE) {
2507                 switch (type) {
2508                 case SVM_EXITINTINFO_TYPE_NMI:
2509                         svm->vcpu.arch.nmi_injected = false;
2510                         break;
2511                 case SVM_EXITINTINFO_TYPE_EXEPT:
2512                         if (svm->vmcb->control.exit_info_2 &
2513                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2514                                 has_error_code = true;
2515                                 error_code =
2516                                         (u32)svm->vmcb->control.exit_info_2;
2517                         }
2518                         kvm_clear_exception_queue(&svm->vcpu);
2519                         break;
2520                 case SVM_EXITINTINFO_TYPE_INTR:
2521                         kvm_clear_interrupt_queue(&svm->vcpu);
2522                         break;
2523                 default:
2524                         break;
2525                 }
2526         }
2527
2528         if (reason != TASK_SWITCH_GATE ||
2529             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2530             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2531              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2532                 skip_emulated_instruction(&svm->vcpu);
2533
2534         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2535                                 has_error_code, error_code) == EMULATE_FAIL) {
2536                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2537                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2538                 svm->vcpu.run->internal.ndata = 0;
2539                 return 0;
2540         }
2541         return 1;
2542 }
2543
2544 static int cpuid_interception(struct vcpu_svm *svm)
2545 {
2546         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2547         kvm_emulate_cpuid(&svm->vcpu);
2548         return 1;
2549 }
2550
2551 static int iret_interception(struct vcpu_svm *svm)
2552 {
2553         ++svm->vcpu.stat.nmi_window_exits;
2554         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2555         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2556         return 1;
2557 }
2558
2559 static int invlpg_interception(struct vcpu_svm *svm)
2560 {
2561         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2562 }
2563
2564 static int emulate_on_interception(struct vcpu_svm *svm)
2565 {
2566         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2567 }
2568
2569 static int cr0_write_interception(struct vcpu_svm *svm)
2570 {
2571         struct kvm_vcpu *vcpu = &svm->vcpu;
2572         int r;
2573
2574         r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2575
2576         if (svm->nested.vmexit_rip) {
2577                 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2578                 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2579                 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2580                 svm->nested.vmexit_rip = 0;
2581         }
2582
2583         return r == EMULATE_DONE;
2584 }
2585
2586 static int cr8_write_interception(struct vcpu_svm *svm)
2587 {
2588         struct kvm_run *kvm_run = svm->vcpu.run;
2589
2590         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2591         /* instruction emulation calls kvm_set_cr8() */
2592         emulate_instruction(&svm->vcpu, 0, 0, 0);
2593         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2594                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2595                 return 1;
2596         }
2597         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2598                 return 1;
2599         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2600         return 0;
2601 }
2602
2603 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2604 {
2605         struct vcpu_svm *svm = to_svm(vcpu);
2606
2607         switch (ecx) {
2608         case MSR_IA32_TSC: {
2609                 u64 tsc_offset;
2610
2611                 if (is_nested(svm))
2612                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2613                 else
2614                         tsc_offset = svm->vmcb->control.tsc_offset;
2615
2616                 *data = tsc_offset + native_read_tsc();
2617                 break;
2618         }
2619         case MSR_STAR:
2620                 *data = svm->vmcb->save.star;
2621                 break;
2622 #ifdef CONFIG_X86_64
2623         case MSR_LSTAR:
2624                 *data = svm->vmcb->save.lstar;
2625                 break;
2626         case MSR_CSTAR:
2627                 *data = svm->vmcb->save.cstar;
2628                 break;
2629         case MSR_KERNEL_GS_BASE:
2630                 *data = svm->vmcb->save.kernel_gs_base;
2631                 break;
2632         case MSR_SYSCALL_MASK:
2633                 *data = svm->vmcb->save.sfmask;
2634                 break;
2635 #endif
2636         case MSR_IA32_SYSENTER_CS:
2637                 *data = svm->vmcb->save.sysenter_cs;
2638                 break;
2639         case MSR_IA32_SYSENTER_EIP:
2640                 *data = svm->sysenter_eip;
2641                 break;
2642         case MSR_IA32_SYSENTER_ESP:
2643                 *data = svm->sysenter_esp;
2644                 break;
2645         /*
2646          * Nobody will change the following 5 values in the VMCB so we can
2647          * safely return them on rdmsr. They will always be 0 until LBRV is
2648          * implemented.
2649          */
2650         case MSR_IA32_DEBUGCTLMSR:
2651                 *data = svm->vmcb->save.dbgctl;
2652                 break;
2653         case MSR_IA32_LASTBRANCHFROMIP:
2654                 *data = svm->vmcb->save.br_from;
2655                 break;
2656         case MSR_IA32_LASTBRANCHTOIP:
2657                 *data = svm->vmcb->save.br_to;
2658                 break;
2659         case MSR_IA32_LASTINTFROMIP:
2660                 *data = svm->vmcb->save.last_excp_from;
2661                 break;
2662         case MSR_IA32_LASTINTTOIP:
2663                 *data = svm->vmcb->save.last_excp_to;
2664                 break;
2665         case MSR_VM_HSAVE_PA:
2666                 *data = svm->nested.hsave_msr;
2667                 break;
2668         case MSR_VM_CR:
2669                 *data = svm->nested.vm_cr_msr;
2670                 break;
2671         case MSR_IA32_UCODE_REV:
2672                 *data = 0x01000065;
2673                 break;
2674         default:
2675                 return kvm_get_msr_common(vcpu, ecx, data);
2676         }
2677         return 0;
2678 }
2679
2680 static int rdmsr_interception(struct vcpu_svm *svm)
2681 {
2682         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2683         u64 data;
2684
2685         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2686                 trace_kvm_msr_read_ex(ecx);
2687                 kvm_inject_gp(&svm->vcpu, 0);
2688         } else {
2689                 trace_kvm_msr_read(ecx, data);
2690
2691                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2692                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2693                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2694                 skip_emulated_instruction(&svm->vcpu);
2695         }
2696         return 1;
2697 }
2698
2699 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2700 {
2701         struct vcpu_svm *svm = to_svm(vcpu);
2702         int svm_dis, chg_mask;
2703
2704         if (data & ~SVM_VM_CR_VALID_MASK)
2705                 return 1;
2706
2707         chg_mask = SVM_VM_CR_VALID_MASK;
2708
2709         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2710                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2711
2712         svm->nested.vm_cr_msr &= ~chg_mask;
2713         svm->nested.vm_cr_msr |= (data & chg_mask);
2714
2715         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2716
2717         /* check for svm_disable while efer.svme is set */
2718         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2719                 return 1;
2720
2721         return 0;
2722 }
2723
2724 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2725 {
2726         struct vcpu_svm *svm = to_svm(vcpu);
2727
2728         switch (ecx) {
2729         case MSR_IA32_TSC:
2730                 kvm_write_tsc(vcpu, data);
2731                 break;
2732         case MSR_STAR:
2733                 svm->vmcb->save.star = data;
2734                 break;
2735 #ifdef CONFIG_X86_64
2736         case MSR_LSTAR:
2737                 svm->vmcb->save.lstar = data;
2738                 break;
2739         case MSR_CSTAR:
2740                 svm->vmcb->save.cstar = data;
2741                 break;
2742         case MSR_KERNEL_GS_BASE:
2743                 svm->vmcb->save.kernel_gs_base = data;
2744                 break;
2745         case MSR_SYSCALL_MASK:
2746                 svm->vmcb->save.sfmask = data;
2747                 break;
2748 #endif
2749         case MSR_IA32_SYSENTER_CS:
2750                 svm->vmcb->save.sysenter_cs = data;
2751                 break;
2752         case MSR_IA32_SYSENTER_EIP:
2753                 svm->sysenter_eip = data;
2754                 svm->vmcb->save.sysenter_eip = data;
2755                 break;
2756         case MSR_IA32_SYSENTER_ESP:
2757                 svm->sysenter_esp = data;
2758                 svm->vmcb->save.sysenter_esp = data;
2759                 break;
2760         case MSR_IA32_DEBUGCTLMSR:
2761                 if (!svm_has(SVM_FEATURE_LBRV)) {
2762                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2763                                         __func__, data);
2764                         break;
2765                 }
2766                 if (data & DEBUGCTL_RESERVED_BITS)
2767                         return 1;
2768
2769                 svm->vmcb->save.dbgctl = data;
2770                 if (data & (1ULL<<0))
2771                         svm_enable_lbrv(svm);
2772                 else
2773                         svm_disable_lbrv(svm);
2774                 break;
2775         case MSR_VM_HSAVE_PA:
2776                 svm->nested.hsave_msr = data;
2777                 break;
2778         case MSR_VM_CR:
2779                 return svm_set_vm_cr(vcpu, data);
2780         case MSR_VM_IGNNE:
2781                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2782                 break;
2783         default:
2784                 return kvm_set_msr_common(vcpu, ecx, data);
2785         }
2786         return 0;
2787 }
2788
2789 static int wrmsr_interception(struct vcpu_svm *svm)
2790 {
2791         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2792         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2793                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2794
2795
2796         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2797         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2798                 trace_kvm_msr_write_ex(ecx, data);
2799                 kvm_inject_gp(&svm->vcpu, 0);
2800         } else {
2801                 trace_kvm_msr_write(ecx, data);
2802                 skip_emulated_instruction(&svm->vcpu);
2803         }
2804         return 1;
2805 }
2806
2807 static int msr_interception(struct vcpu_svm *svm)
2808 {
2809         if (svm->vmcb->control.exit_info_1)
2810                 return wrmsr_interception(svm);
2811         else
2812                 return rdmsr_interception(svm);
2813 }
2814
2815 static int interrupt_window_interception(struct vcpu_svm *svm)
2816 {
2817         struct kvm_run *kvm_run = svm->vcpu.run;
2818
2819         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2820         svm_clear_vintr(svm);
2821         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2822         /*
2823          * If the user space waits to inject interrupts, exit as soon as
2824          * possible
2825          */
2826         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2827             kvm_run->request_interrupt_window &&
2828             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2829                 ++svm->vcpu.stat.irq_window_exits;
2830                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2831                 return 0;
2832         }
2833
2834         return 1;
2835 }
2836
2837 static int pause_interception(struct vcpu_svm *svm)
2838 {
2839         kvm_vcpu_on_spin(&(svm->vcpu));
2840         return 1;
2841 }
2842
2843 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2844         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2845         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2846         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2847         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2848         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2849         [SVM_EXIT_WRITE_CR0]                    = cr0_write_interception,
2850         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2851         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2852         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2853         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2854         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2855         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2856         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2857         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2858         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2859         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2860         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2861         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2862         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2863         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2864         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2865         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2866         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2867         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2868         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2869         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2870         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2871         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2872         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2873         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2874         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2875         [SVM_EXIT_INTR]                         = intr_interception,
2876         [SVM_EXIT_NMI]                          = nmi_interception,
2877         [SVM_EXIT_SMI]                          = nop_on_interception,
2878         [SVM_EXIT_INIT]                         = nop_on_interception,
2879         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2880         [SVM_EXIT_CPUID]                        = cpuid_interception,
2881         [SVM_EXIT_IRET]                         = iret_interception,
2882         [SVM_EXIT_INVD]                         = emulate_on_interception,
2883         [SVM_EXIT_PAUSE]                        = pause_interception,
2884         [SVM_EXIT_HLT]                          = halt_interception,
2885         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2886         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2887         [SVM_EXIT_IOIO]                         = io_interception,
2888         [SVM_EXIT_MSR]                          = msr_interception,
2889         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2890         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2891         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2892         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2893         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2894         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2895         [SVM_EXIT_STGI]                         = stgi_interception,
2896         [SVM_EXIT_CLGI]                         = clgi_interception,
2897         [SVM_EXIT_SKINIT]                       = skinit_interception,
2898         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2899         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2900         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2901         [SVM_EXIT_NPF]                          = pf_interception,
2902 };
2903
2904 void dump_vmcb(struct kvm_vcpu *vcpu)
2905 {
2906         struct vcpu_svm *svm = to_svm(vcpu);
2907         struct vmcb_control_area *control = &svm->vmcb->control;
2908         struct vmcb_save_area *save = &svm->vmcb->save;
2909
2910         pr_err("VMCB Control Area:\n");
2911         pr_err("cr_read:            %04x\n", control->intercept_cr_read);
2912         pr_err("cr_write:           %04x\n", control->intercept_cr_write);
2913         pr_err("dr_read:            %04x\n", control->intercept_dr_read);
2914         pr_err("dr_write:           %04x\n", control->intercept_dr_write);
2915         pr_err("exceptions:         %08x\n", control->intercept_exceptions);
2916         pr_err("intercepts:         %016llx\n", control->intercept);
2917         pr_err("pause filter count: %d\n", control->pause_filter_count);
2918         pr_err("iopm_base_pa:       %016llx\n", control->iopm_base_pa);
2919         pr_err("msrpm_base_pa:      %016llx\n", control->msrpm_base_pa);
2920         pr_err("tsc_offset:         %016llx\n", control->tsc_offset);
2921         pr_err("asid:               %d\n", control->asid);
2922         pr_err("tlb_ctl:            %d\n", control->tlb_ctl);
2923         pr_err("int_ctl:            %08x\n", control->int_ctl);
2924         pr_err("int_vector:         %08x\n", control->int_vector);
2925         pr_err("int_state:          %08x\n", control->int_state);
2926         pr_err("exit_code:          %08x\n", control->exit_code);
2927         pr_err("exit_info1:         %016llx\n", control->exit_info_1);
2928         pr_err("exit_info2:         %016llx\n", control->exit_info_2);
2929         pr_err("exit_int_info:      %08x\n", control->exit_int_info);
2930         pr_err("exit_int_info_err:  %08x\n", control->exit_int_info_err);
2931         pr_err("nested_ctl:         %lld\n", control->nested_ctl);
2932         pr_err("nested_cr3:         %016llx\n", control->nested_cr3);
2933         pr_err("event_inj:          %08x\n", control->event_inj);
2934         pr_err("event_inj_err:      %08x\n", control->event_inj_err);
2935         pr_err("lbr_ctl:            %lld\n", control->lbr_ctl);
2936         pr_err("next_rip:           %016llx\n", control->next_rip);
2937         pr_err("VMCB State Save Area:\n");
2938         pr_err("es:   s: %04x a: %04x l: %08x b: %016llx\n",
2939                 save->es.selector, save->es.attrib,
2940                 save->es.limit, save->es.base);
2941         pr_err("cs:   s: %04x a: %04x l: %08x b: %016llx\n",
2942                 save->cs.selector, save->cs.attrib,
2943                 save->cs.limit, save->cs.base);
2944         pr_err("ss:   s: %04x a: %04x l: %08x b: %016llx\n",
2945                 save->ss.selector, save->ss.attrib,
2946                 save->ss.limit, save->ss.base);
2947         pr_err("ds:   s: %04x a: %04x l: %08x b: %016llx\n",
2948                 save->ds.selector, save->ds.attrib,
2949                 save->ds.limit, save->ds.base);
2950         pr_err("fs:   s: %04x a: %04x l: %08x b: %016llx\n",
2951                 save->fs.selector, save->fs.attrib,
2952                 save->fs.limit, save->fs.base);
2953         pr_err("gs:   s: %04x a: %04x l: %08x b: %016llx\n",
2954                 save->gs.selector, save->gs.attrib,
2955                 save->gs.limit, save->gs.base);
2956         pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2957                 save->gdtr.selector, save->gdtr.attrib,
2958                 save->gdtr.limit, save->gdtr.base);
2959         pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2960                 save->ldtr.selector, save->ldtr.attrib,
2961                 save->ldtr.limit, save->ldtr.base);
2962         pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2963                 save->idtr.selector, save->idtr.attrib,
2964                 save->idtr.limit, save->idtr.base);
2965         pr_err("tr:   s: %04x a: %04x l: %08x b: %016llx\n",
2966                 save->tr.selector, save->tr.attrib,
2967                 save->tr.limit, save->tr.base);
2968         pr_err("cpl:            %d                efer:         %016llx\n",
2969                 save->cpl, save->efer);
2970         pr_err("cr0:            %016llx cr2:          %016llx\n",
2971                 save->cr0, save->cr2);
2972         pr_err("cr3:            %016llx cr4:          %016llx\n",
2973                 save->cr3, save->cr4);
2974         pr_err("dr6:            %016llx dr7:          %016llx\n",
2975                 save->dr6, save->dr7);
2976         pr_err("rip:            %016llx rflags:       %016llx\n",
2977                 save->rip, save->rflags);
2978         pr_err("rsp:            %016llx rax:          %016llx\n",
2979                 save->rsp, save->rax);
2980         pr_err("star:           %016llx lstar:        %016llx\n",
2981                 save->star, save->lstar);
2982         pr_err("cstar:          %016llx sfmask:       %016llx\n",
2983                 save->cstar, save->sfmask);
2984         pr_err("kernel_gs_base: %016llx sysenter_cs:  %016llx\n",
2985                 save->kernel_gs_base, save->sysenter_cs);
2986         pr_err("sysenter_esp:   %016llx sysenter_eip: %016llx\n",
2987                 save->sysenter_esp, save->sysenter_eip);
2988         pr_err("gpat:           %016llx dbgctl:       %016llx\n",
2989                 save->g_pat, save->dbgctl);
2990         pr_err("br_from:        %016llx br_to:        %016llx\n",
2991                 save->br_from, save->br_to);
2992         pr_err("excp_from:      %016llx excp_to:      %016llx\n",
2993                 save->last_excp_from, save->last_excp_to);
2994
2995 }
2996
2997 static int handle_exit(struct kvm_vcpu *vcpu)
2998 {
2999         struct vcpu_svm *svm = to_svm(vcpu);
3000         struct kvm_run *kvm_run = vcpu->run;
3001         u32 exit_code = svm->vmcb->control.exit_code;
3002
3003         trace_kvm_exit(exit_code, vcpu);
3004
3005         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
3006                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3007         if (npt_enabled)
3008                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3009
3010         if (unlikely(svm->nested.exit_required)) {
3011                 nested_svm_vmexit(svm);
3012                 svm->nested.exit_required = false;
3013
3014                 return 1;
3015         }
3016
3017         if (is_nested(svm)) {
3018                 int vmexit;
3019
3020                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3021                                         svm->vmcb->control.exit_info_1,
3022                                         svm->vmcb->control.exit_info_2,
3023                                         svm->vmcb->control.exit_int_info,
3024                                         svm->vmcb->control.exit_int_info_err);
3025
3026                 vmexit = nested_svm_exit_special(svm);
3027
3028                 if (vmexit == NESTED_EXIT_CONTINUE)
3029                         vmexit = nested_svm_exit_handled(svm);
3030
3031                 if (vmexit == NESTED_EXIT_DONE)
3032                         return 1;
3033         }
3034
3035         svm_complete_interrupts(svm);
3036
3037         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3038                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3039                 kvm_run->fail_entry.hardware_entry_failure_reason
3040                         = svm->vmcb->control.exit_code;
3041                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3042                 dump_vmcb(vcpu);
3043                 return 0;
3044         }
3045
3046         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3047             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3048             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3049             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3050                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3051                        "exit_code 0x%x\n",
3052                        __func__, svm->vmcb->control.exit_int_info,
3053                        exit_code);
3054
3055         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3056             || !svm_exit_handlers[exit_code]) {
3057                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3058                 kvm_run->hw.hardware_exit_reason = exit_code;
3059                 return 0;
3060         }
3061
3062         return svm_exit_handlers[exit_code](svm);
3063 }
3064
3065 static void reload_tss(struct kvm_vcpu *vcpu)
3066 {
3067         int cpu = raw_smp_processor_id();
3068
3069         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3070         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3071         load_TR_desc();
3072 }
3073
3074 static void pre_svm_run(struct vcpu_svm *svm)
3075 {
3076         int cpu = raw_smp_processor_id();
3077
3078         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3079
3080         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3081         /* FIXME: handle wraparound of asid_generation */
3082         if (svm->asid_generation != sd->asid_generation)
3083                 new_asid(svm, sd);
3084 }
3085
3086 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3087 {
3088         struct vcpu_svm *svm = to_svm(vcpu);
3089
3090         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3091         vcpu->arch.hflags |= HF_NMI_MASK;
3092         svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3093         ++vcpu->stat.nmi_injections;
3094 }
3095
3096 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3097 {
3098         struct vmcb_control_area *control;
3099
3100         control = &svm->vmcb->control;
3101         control->int_vector = irq;
3102         control->int_ctl &= ~V_INTR_PRIO_MASK;
3103         control->int_ctl |= V_IRQ_MASK |
3104                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3105 }
3106
3107 static void svm_set_irq(struct kvm_vcpu *vcpu)
3108 {
3109         struct vcpu_svm *svm = to_svm(vcpu);
3110
3111         BUG_ON(!(gif_set(svm)));
3112
3113         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3114         ++vcpu->stat.irq_injections;
3115
3116         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3117                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3118 }
3119
3120 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3121 {
3122         struct vcpu_svm *svm = to_svm(vcpu);
3123
3124         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3125                 return;
3126
3127         if (irr == -1)
3128                 return;
3129
3130         if (tpr >= irr)
3131                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3132 }
3133
3134 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3135 {
3136         struct vcpu_svm *svm = to_svm(vcpu);
3137         struct vmcb *vmcb = svm->vmcb;
3138         int ret;
3139         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3140               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3141         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3142
3143         return ret;
3144 }
3145
3146 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3147 {
3148         struct vcpu_svm *svm = to_svm(vcpu);
3149
3150         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3151 }
3152
3153 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3154 {
3155         struct vcpu_svm *svm = to_svm(vcpu);
3156
3157         if (masked) {
3158                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3159                 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3160         } else {
3161                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3162                 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3163         }
3164 }
3165
3166 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3167 {
3168         struct vcpu_svm *svm = to_svm(vcpu);
3169         struct vmcb *vmcb = svm->vmcb;
3170         int ret;
3171
3172         if (!gif_set(svm) ||
3173              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3174                 return 0;
3175
3176         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3177
3178         if (is_nested(svm))
3179                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3180
3181         return ret;
3182 }
3183
3184 static void enable_irq_window(struct kvm_vcpu *vcpu)
3185 {
3186         struct vcpu_svm *svm = to_svm(vcpu);
3187
3188         /*
3189          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3190          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3191          * get that intercept, this function will be called again though and
3192          * we'll get the vintr intercept.
3193          */
3194         if (gif_set(svm) && nested_svm_intr(svm)) {
3195                 svm_set_vintr(svm);
3196                 svm_inject_irq(svm, 0x0);
3197         }
3198 }
3199
3200 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3201 {
3202         struct vcpu_svm *svm = to_svm(vcpu);
3203
3204         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3205             == HF_NMI_MASK)
3206                 return; /* IRET will cause a vm exit */
3207
3208         /*
3209          * Something prevents NMI from been injected. Single step over possible
3210          * problem (IRET or exception injection or interrupt shadow)
3211          */
3212         svm->nmi_singlestep = true;
3213         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3214         update_db_intercept(vcpu);
3215 }
3216
3217 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3218 {
3219         return 0;
3220 }
3221
3222 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3223 {
3224         force_new_asid(vcpu);
3225 }
3226
3227 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3228 {
3229 }
3230
3231 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3232 {
3233         struct vcpu_svm *svm = to_svm(vcpu);
3234
3235         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3236                 return;
3237
3238         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3239                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3240                 kvm_set_cr8(vcpu, cr8);
3241         }
3242 }
3243
3244 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3245 {
3246         struct vcpu_svm *svm = to_svm(vcpu);
3247         u64 cr8;
3248
3249         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3250                 return;
3251
3252         cr8 = kvm_get_cr8(vcpu);
3253         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3254         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3255 }
3256
3257 static void svm_complete_interrupts(struct vcpu_svm *svm)
3258 {
3259         u8 vector;
3260         int type;
3261         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3262         unsigned int3_injected = svm->int3_injected;
3263
3264         svm->int3_injected = 0;
3265
3266         if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3267                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3268                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3269         }
3270
3271         svm->vcpu.arch.nmi_injected = false;
3272         kvm_clear_exception_queue(&svm->vcpu);
3273         kvm_clear_interrupt_queue(&svm->vcpu);
3274
3275         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3276                 return;
3277
3278         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3279
3280         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3281         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3282
3283         switch (type) {
3284         case SVM_EXITINTINFO_TYPE_NMI:
3285                 svm->vcpu.arch.nmi_injected = true;
3286                 break;
3287         case SVM_EXITINTINFO_TYPE_EXEPT:
3288                 /*
3289                  * In case of software exceptions, do not reinject the vector,
3290                  * but re-execute the instruction instead. Rewind RIP first
3291                  * if we emulated INT3 before.
3292                  */
3293                 if (kvm_exception_is_soft(vector)) {
3294                         if (vector == BP_VECTOR && int3_injected &&
3295                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3296                                 kvm_rip_write(&svm->vcpu,
3297                                               kvm_rip_read(&svm->vcpu) -
3298                                               int3_injected);
3299                         break;
3300                 }
3301                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3302                         u32 err = svm->vmcb->control.exit_int_info_err;
3303                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3304
3305                 } else
3306                         kvm_requeue_exception(&svm->vcpu, vector);
3307                 break;
3308         case SVM_EXITINTINFO_TYPE_INTR:
3309                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3310                 break;
3311         default:
3312                 break;
3313         }
3314 }
3315
3316 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3317 {
3318         struct vcpu_svm *svm = to_svm(vcpu);
3319         struct vmcb_control_area *control = &svm->vmcb->control;
3320
3321         control->exit_int_info = control->event_inj;
3322         control->exit_int_info_err = control->event_inj_err;
3323         control->event_inj = 0;
3324         svm_complete_interrupts(svm);
3325 }
3326
3327 #ifdef CONFIG_X86_64
3328 #define R "r"
3329 #else
3330 #define R "e"
3331 #endif
3332
3333 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3334 {
3335         struct vcpu_svm *svm = to_svm(vcpu);
3336
3337         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3338         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3339         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3340
3341         /*
3342          * A vmexit emulation is required before the vcpu can be executed
3343          * again.
3344          */
3345         if (unlikely(svm->nested.exit_required))
3346                 return;
3347
3348         pre_svm_run(svm);
3349
3350         sync_lapic_to_cr8(vcpu);
3351
3352         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3353
3354         clgi();
3355
3356         local_irq_enable();
3357
3358         asm volatile (
3359                 "push %%"R"bp; \n\t"
3360                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3361                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3362                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3363                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3364                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3365                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3366 #ifdef CONFIG_X86_64
3367                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3368                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3369                 "mov %c[r10](%[svm]), %%r10 \n\t"
3370                 "mov %c[r11](%[svm]), %%r11 \n\t"
3371                 "mov %c[r12](%[svm]), %%r12 \n\t"
3372                 "mov %c[r13](%[svm]), %%r13 \n\t"
3373                 "mov %c[r14](%[svm]), %%r14 \n\t"
3374                 "mov %c[r15](%[svm]), %%r15 \n\t"
3375 #endif
3376
3377                 /* Enter guest mode */
3378                 "push %%"R"ax \n\t"
3379                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3380                 __ex(SVM_VMLOAD) "\n\t"
3381                 __ex(SVM_VMRUN) "\n\t"
3382                 __ex(SVM_VMSAVE) "\n\t"
3383                 "pop %%"R"ax \n\t"
3384
3385                 /* Save guest registers, load host registers */
3386                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3387                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3388                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3389                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3390                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3391                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3392 #ifdef CONFIG_X86_64
3393                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3394                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3395                 "mov %%r10, %c[r10](%[svm]) \n\t"
3396                 "mov %%r11, %c[r11](%[svm]) \n\t"
3397                 "mov %%r12, %c[r12](%[svm]) \n\t"
3398                 "mov %%r13, %c[r13](%[svm]) \n\t"
3399                 "mov %%r14, %c[r14](%[svm]) \n\t"
3400                 "mov %%r15, %c[r15](%[svm]) \n\t"
3401 #endif
3402                 "pop %%"R"bp"
3403                 :
3404                 : [svm]"a"(svm),
3405                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3406                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3407                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3408                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3409                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3410                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3411                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3412 #ifdef CONFIG_X86_64
3413                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3414                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3415                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3416                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3417                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3418                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3419                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3420                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3421 #endif
3422                 : "cc", "memory"
3423                 , R"bx", R"cx", R"dx", R"si", R"di"
3424 #ifdef CONFIG_X86_64
3425                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3426 #endif
3427                 );
3428
3429         load_host_msrs(vcpu);
3430 #ifndef CONFIG_X86_64
3431         loadsegment(fs, svm->host.fs);
3432 #endif
3433
3434         reload_tss(vcpu);
3435
3436         local_irq_disable();
3437
3438         stgi();
3439
3440         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3441         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3442         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3443         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3444
3445         sync_cr8_to_lapic(vcpu);
3446
3447         svm->next_rip = 0;
3448
3449         /* if exit due to PF check for async PF */
3450         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3451                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3452
3453         if (npt_enabled) {
3454                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3455                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3456         }
3457
3458         /*
3459          * We need to handle MC intercepts here before the vcpu has a chance to
3460          * change the physical cpu
3461          */
3462         if (unlikely(svm->vmcb->control.exit_code ==
3463                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3464                 svm_handle_mce(svm);
3465 }
3466
3467 #undef R
3468
3469 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3470 {
3471         struct vcpu_svm *svm = to_svm(vcpu);
3472
3473         svm->vmcb->save.cr3 = root;
3474         force_new_asid(vcpu);
3475 }
3476
3477 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3478 {
3479         struct vcpu_svm *svm = to_svm(vcpu);
3480
3481         svm->vmcb->control.nested_cr3 = root;
3482
3483         /* Also sync guest cr3 here in case we live migrate */
3484         svm->vmcb->save.cr3 = vcpu->arch.cr3;
3485
3486         force_new_asid(vcpu);
3487 }
3488
3489 static int is_disabled(void)
3490 {
3491         u64 vm_cr;
3492
3493         rdmsrl(MSR_VM_CR, vm_cr);
3494         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3495                 return 1;
3496
3497         return 0;
3498 }
3499
3500 static void
3501 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3502 {
3503         /*
3504          * Patch in the VMMCALL instruction:
3505          */
3506         hypercall[0] = 0x0f;
3507         hypercall[1] = 0x01;
3508         hypercall[2] = 0xd9;
3509 }
3510
3511 static void svm_check_processor_compat(void *rtn)
3512 {
3513         *(int *)rtn = 0;
3514 }
3515
3516 static bool svm_cpu_has_accelerated_tpr(void)
3517 {
3518         return false;
3519 }
3520
3521 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3522 {
3523         return 0;
3524 }
3525
3526 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3527 {
3528 }
3529
3530 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3531 {
3532         switch (func) {
3533         case 0x00000001:
3534                 /* Mask out xsave bit as long as it is not supported by SVM */
3535                 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3536                 break;
3537         case 0x80000001:
3538                 if (nested)
3539                         entry->ecx |= (1 << 2); /* Set SVM bit */
3540                 break;
3541         case 0x8000000A:
3542                 entry->eax = 1; /* SVM revision 1 */
3543                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3544                                    ASID emulation to nested SVM */
3545                 entry->ecx = 0; /* Reserved */
3546                 entry->edx = 0; /* Per default do not support any
3547                                    additional features */
3548
3549                 /* Support next_rip if host supports it */
3550                 if (svm_has(SVM_FEATURE_NRIP))
3551                         entry->edx |= SVM_FEATURE_NRIP;
3552
3553                 /* Support NPT for the guest if enabled */
3554                 if (npt_enabled)
3555                         entry->edx |= SVM_FEATURE_NPT;
3556
3557                 break;
3558         }
3559 }
3560
3561 static const struct trace_print_flags svm_exit_reasons_str[] = {
3562         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3563         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3564         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3565         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3566         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3567         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3568         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3569         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3570         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3571         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3572         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3573         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3574         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3575         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3576         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3577         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3578         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3579         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3580         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3581         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3582         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3583         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3584         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3585         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3586         { SVM_EXIT_INTR,                        "interrupt" },
3587         { SVM_EXIT_NMI,                         "nmi" },
3588         { SVM_EXIT_SMI,                         "smi" },
3589         { SVM_EXIT_INIT,                        "init" },
3590         { SVM_EXIT_VINTR,                       "vintr" },
3591         { SVM_EXIT_CPUID,                       "cpuid" },
3592         { SVM_EXIT_INVD,                        "invd" },
3593         { SVM_EXIT_HLT,                         "hlt" },
3594         { SVM_EXIT_INVLPG,                      "invlpg" },
3595         { SVM_EXIT_INVLPGA,                     "invlpga" },
3596         { SVM_EXIT_IOIO,                        "io" },
3597         { SVM_EXIT_MSR,                         "msr" },
3598         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3599         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3600         { SVM_EXIT_VMRUN,                       "vmrun" },
3601         { SVM_EXIT_VMMCALL,                     "hypercall" },
3602         { SVM_EXIT_VMLOAD,                      "vmload" },
3603         { SVM_EXIT_VMSAVE,                      "vmsave" },
3604         { SVM_EXIT_STGI,                        "stgi" },
3605         { SVM_EXIT_CLGI,                        "clgi" },
3606         { SVM_EXIT_SKINIT,                      "skinit" },
3607         { SVM_EXIT_WBINVD,                      "wbinvd" },
3608         { SVM_EXIT_MONITOR,                     "monitor" },
3609         { SVM_EXIT_MWAIT,                       "mwait" },
3610         { SVM_EXIT_NPF,                         "npf" },
3611         { -1, NULL }
3612 };
3613
3614 static int svm_get_lpage_level(void)
3615 {
3616         return PT_PDPE_LEVEL;
3617 }
3618
3619 static bool svm_rdtscp_supported(void)
3620 {
3621         return false;
3622 }
3623
3624 static bool svm_has_wbinvd_exit(void)
3625 {
3626         return true;
3627 }
3628
3629 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3630 {
3631         struct vcpu_svm *svm = to_svm(vcpu);
3632
3633         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3634         if (is_nested(svm))
3635                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3636         update_cr0_intercept(svm);
3637 }
3638
3639 static struct kvm_x86_ops svm_x86_ops = {
3640         .cpu_has_kvm_support = has_svm,
3641         .disabled_by_bios = is_disabled,
3642         .hardware_setup = svm_hardware_setup,
3643         .hardware_unsetup = svm_hardware_unsetup,
3644         .check_processor_compatibility = svm_check_processor_compat,
3645         .hardware_enable = svm_hardware_enable,
3646         .hardware_disable = svm_hardware_disable,
3647         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3648
3649         .vcpu_create = svm_create_vcpu,
3650         .vcpu_free = svm_free_vcpu,
3651         .vcpu_reset = svm_vcpu_reset,
3652
3653         .prepare_guest_switch = svm_prepare_guest_switch,
3654         .vcpu_load = svm_vcpu_load,
3655         .vcpu_put = svm_vcpu_put,
3656
3657         .set_guest_debug = svm_guest_debug,
3658         .get_msr = svm_get_msr,
3659         .set_msr = svm_set_msr,
3660         .get_segment_base = svm_get_segment_base,
3661         .get_segment = svm_get_segment,
3662         .set_segment = svm_set_segment,
3663         .get_cpl = svm_get_cpl,
3664         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3665         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3666         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3667         .set_cr0 = svm_set_cr0,
3668         .set_cr3 = svm_set_cr3,
3669         .set_cr4 = svm_set_cr4,
3670         .set_efer = svm_set_efer,
3671         .get_idt = svm_get_idt,
3672         .set_idt = svm_set_idt,
3673         .get_gdt = svm_get_gdt,
3674         .set_gdt = svm_set_gdt,
3675         .set_dr7 = svm_set_dr7,
3676         .cache_reg = svm_cache_reg,
3677         .get_rflags = svm_get_rflags,
3678         .set_rflags = svm_set_rflags,
3679         .fpu_activate = svm_fpu_activate,
3680         .fpu_deactivate = svm_fpu_deactivate,
3681
3682         .tlb_flush = svm_flush_tlb,
3683
3684         .run = svm_vcpu_run,
3685         .handle_exit = handle_exit,
3686         .skip_emulated_instruction = skip_emulated_instruction,
3687         .set_interrupt_shadow = svm_set_interrupt_shadow,
3688         .get_interrupt_shadow = svm_get_interrupt_shadow,
3689         .patch_hypercall = svm_patch_hypercall,
3690         .set_irq = svm_set_irq,
3691         .set_nmi = svm_inject_nmi,
3692         .queue_exception = svm_queue_exception,
3693         .cancel_injection = svm_cancel_injection,
3694         .interrupt_allowed = svm_interrupt_allowed,
3695         .nmi_allowed = svm_nmi_allowed,
3696         .get_nmi_mask = svm_get_nmi_mask,
3697         .set_nmi_mask = svm_set_nmi_mask,
3698         .enable_nmi_window = enable_nmi_window,
3699         .enable_irq_window = enable_irq_window,
3700         .update_cr8_intercept = update_cr8_intercept,
3701
3702         .set_tss_addr = svm_set_tss_addr,
3703         .get_tdp_level = get_npt_level,
3704         .get_mt_mask = svm_get_mt_mask,
3705
3706         .exit_reasons_str = svm_exit_reasons_str,
3707         .get_lpage_level = svm_get_lpage_level,
3708
3709         .cpuid_update = svm_cpuid_update,
3710
3711         .rdtscp_supported = svm_rdtscp_supported,
3712
3713         .set_supported_cpuid = svm_set_supported_cpuid,
3714
3715         .has_wbinvd_exit = svm_has_wbinvd_exit,
3716
3717         .write_tsc_offset = svm_write_tsc_offset,
3718         .adjust_tsc_offset = svm_adjust_tsc_offset,
3719
3720         .set_tdp_cr3 = set_tdp_cr3,
3721 };
3722
3723 static int __init svm_init(void)
3724 {
3725         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3726                         __alignof__(struct vcpu_svm), THIS_MODULE);
3727 }
3728
3729 static void __exit svm_exit(void)
3730 {
3731         kvm_exit();
3732 }
3733
3734 module_init(svm_init)
3735 module_exit(svm_exit)