2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled = false;
55 AUDIT_POST_PAGE_FAULT,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc {
157 u64 *sptes[PTE_LIST_EXT];
158 struct pte_list_desc *more;
161 struct kvm_shadow_walk_iterator {
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
196 shadow_mmio_mask = mmio_mask;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
201 * spte bits of bit 3 ~ bit 11 are used as low 9 bits of generation number,
202 * the bits of bits 52 ~ bit 61 are used as high 10 bits of generation
205 #define MMIO_SPTE_GEN_LOW_SHIFT 3
206 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
208 #define MMIO_GEN_SHIFT 19
209 #define MMIO_GEN_LOW_SHIFT 9
210 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 1)
211 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
212 #define MMIO_MAX_GEN ((1 << MMIO_GEN_SHIFT) - 1)
214 static u64 generation_mmio_spte_mask(unsigned int gen)
218 WARN_ON(gen > MMIO_MAX_GEN);
220 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
221 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
225 static unsigned int get_mmio_spte_generation(u64 spte)
229 spte &= ~shadow_mmio_mask;
231 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
232 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
236 static unsigned int kvm_current_mmio_generation(struct kvm *kvm)
238 return kvm_memslots(kvm)->generation & MMIO_GEN_MASK;
241 static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn,
244 struct kvm_mmu_page *sp = page_header(__pa(sptep));
245 unsigned int gen = kvm_current_mmio_generation(kvm);
246 u64 mask = generation_mmio_spte_mask(gen);
248 access &= ACC_WRITE_MASK | ACC_USER_MASK;
249 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
250 sp->mmio_cached = true;
252 trace_mark_mmio_spte(sptep, gfn, access, gen);
253 mmu_spte_set(sptep, mask);
256 static bool is_mmio_spte(u64 spte)
258 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
261 static gfn_t get_mmio_spte_gfn(u64 spte)
263 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
264 return (spte & ~mask) >> PAGE_SHIFT;
267 static unsigned get_mmio_spte_access(u64 spte)
269 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
270 return (spte & ~mask) & ~PAGE_MASK;
273 static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
274 pfn_t pfn, unsigned access)
276 if (unlikely(is_noslot_pfn(pfn))) {
277 mark_mmio_spte(kvm, sptep, gfn, access);
284 static bool check_mmio_spte(struct kvm *kvm, u64 spte)
286 return likely(get_mmio_spte_generation(spte) ==
287 kvm_current_mmio_generation(kvm));
290 static inline u64 rsvd_bits(int s, int e)
292 return ((1ULL << (e - s + 1)) - 1) << s;
295 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
296 u64 dirty_mask, u64 nx_mask, u64 x_mask)
298 shadow_user_mask = user_mask;
299 shadow_accessed_mask = accessed_mask;
300 shadow_dirty_mask = dirty_mask;
301 shadow_nx_mask = nx_mask;
302 shadow_x_mask = x_mask;
304 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
306 static int is_cpuid_PSE36(void)
311 static int is_nx(struct kvm_vcpu *vcpu)
313 return vcpu->arch.efer & EFER_NX;
316 static int is_shadow_present_pte(u64 pte)
318 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
321 static int is_large_pte(u64 pte)
323 return pte & PT_PAGE_SIZE_MASK;
326 static int is_dirty_gpte(unsigned long pte)
328 return pte & PT_DIRTY_MASK;
331 static int is_rmap_spte(u64 pte)
333 return is_shadow_present_pte(pte);
336 static int is_last_spte(u64 pte, int level)
338 if (level == PT_PAGE_TABLE_LEVEL)
340 if (is_large_pte(pte))
345 static pfn_t spte_to_pfn(u64 pte)
347 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
350 static gfn_t pse36_gfn_delta(u32 gpte)
352 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
354 return (gpte & PT32_DIR_PSE36_MASK) << shift;
358 static void __set_spte(u64 *sptep, u64 spte)
363 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
368 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
370 return xchg(sptep, spte);
373 static u64 __get_spte_lockless(u64 *sptep)
375 return ACCESS_ONCE(*sptep);
378 static bool __check_direct_spte_mmio_pf(u64 spte)
380 /* It is valid if the spte is zapped. */
392 static void count_spte_clear(u64 *sptep, u64 spte)
394 struct kvm_mmu_page *sp = page_header(__pa(sptep));
396 if (is_shadow_present_pte(spte))
399 /* Ensure the spte is completely set before we increase the count */
401 sp->clear_spte_count++;
404 static void __set_spte(u64 *sptep, u64 spte)
406 union split_spte *ssptep, sspte;
408 ssptep = (union split_spte *)sptep;
409 sspte = (union split_spte)spte;
411 ssptep->spte_high = sspte.spte_high;
414 * If we map the spte from nonpresent to present, We should store
415 * the high bits firstly, then set present bit, so cpu can not
416 * fetch this spte while we are setting the spte.
420 ssptep->spte_low = sspte.spte_low;
423 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
425 union split_spte *ssptep, sspte;
427 ssptep = (union split_spte *)sptep;
428 sspte = (union split_spte)spte;
430 ssptep->spte_low = sspte.spte_low;
433 * If we map the spte from present to nonpresent, we should clear
434 * present bit firstly to avoid vcpu fetch the old high bits.
438 ssptep->spte_high = sspte.spte_high;
439 count_spte_clear(sptep, spte);
442 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
444 union split_spte *ssptep, sspte, orig;
446 ssptep = (union split_spte *)sptep;
447 sspte = (union split_spte)spte;
449 /* xchg acts as a barrier before the setting of the high bits */
450 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
451 orig.spte_high = ssptep->spte_high;
452 ssptep->spte_high = sspte.spte_high;
453 count_spte_clear(sptep, spte);
459 * The idea using the light way get the spte on x86_32 guest is from
460 * gup_get_pte(arch/x86/mm/gup.c).
461 * The difference is we can not catch the spte tlb flush if we leave
462 * guest mode, so we emulate it by increase clear_spte_count when spte
465 static u64 __get_spte_lockless(u64 *sptep)
467 struct kvm_mmu_page *sp = page_header(__pa(sptep));
468 union split_spte spte, *orig = (union split_spte *)sptep;
472 count = sp->clear_spte_count;
475 spte.spte_low = orig->spte_low;
478 spte.spte_high = orig->spte_high;
481 if (unlikely(spte.spte_low != orig->spte_low ||
482 count != sp->clear_spte_count))
488 static bool __check_direct_spte_mmio_pf(u64 spte)
490 union split_spte sspte = (union split_spte)spte;
491 u32 high_mmio_mask = shadow_mmio_mask >> 32;
493 /* It is valid if the spte is zapped. */
497 /* It is valid if the spte is being zapped. */
498 if (sspte.spte_low == 0ull &&
499 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
506 static bool spte_is_locklessly_modifiable(u64 spte)
508 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
509 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
512 static bool spte_has_volatile_bits(u64 spte)
515 * Always atomicly update spte if it can be updated
516 * out of mmu-lock, it can ensure dirty bit is not lost,
517 * also, it can help us to get a stable is_writable_pte()
518 * to ensure tlb flush is not missed.
520 if (spte_is_locklessly_modifiable(spte))
523 if (!shadow_accessed_mask)
526 if (!is_shadow_present_pte(spte))
529 if ((spte & shadow_accessed_mask) &&
530 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
536 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
538 return (old_spte & bit_mask) && !(new_spte & bit_mask);
541 /* Rules for using mmu_spte_set:
542 * Set the sptep from nonpresent to present.
543 * Note: the sptep being assigned *must* be either not present
544 * or in a state where the hardware will not attempt to update
547 static void mmu_spte_set(u64 *sptep, u64 new_spte)
549 WARN_ON(is_shadow_present_pte(*sptep));
550 __set_spte(sptep, new_spte);
553 /* Rules for using mmu_spte_update:
554 * Update the state bits, it means the mapped pfn is not changged.
556 * Whenever we overwrite a writable spte with a read-only one we
557 * should flush remote TLBs. Otherwise rmap_write_protect
558 * will find a read-only spte, even though the writable spte
559 * might be cached on a CPU's TLB, the return value indicates this
562 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
564 u64 old_spte = *sptep;
567 WARN_ON(!is_rmap_spte(new_spte));
569 if (!is_shadow_present_pte(old_spte)) {
570 mmu_spte_set(sptep, new_spte);
574 if (!spte_has_volatile_bits(old_spte))
575 __update_clear_spte_fast(sptep, new_spte);
577 old_spte = __update_clear_spte_slow(sptep, new_spte);
580 * For the spte updated out of mmu-lock is safe, since
581 * we always atomicly update it, see the comments in
582 * spte_has_volatile_bits().
584 if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
587 if (!shadow_accessed_mask)
590 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
591 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
592 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
593 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
599 * Rules for using mmu_spte_clear_track_bits:
600 * It sets the sptep from present to nonpresent, and track the
601 * state bits, it is used to clear the last level sptep.
603 static int mmu_spte_clear_track_bits(u64 *sptep)
606 u64 old_spte = *sptep;
608 if (!spte_has_volatile_bits(old_spte))
609 __update_clear_spte_fast(sptep, 0ull);
611 old_spte = __update_clear_spte_slow(sptep, 0ull);
613 if (!is_rmap_spte(old_spte))
616 pfn = spte_to_pfn(old_spte);
619 * KVM does not hold the refcount of the page used by
620 * kvm mmu, before reclaiming the page, we should
621 * unmap it from mmu first.
623 WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
625 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
626 kvm_set_pfn_accessed(pfn);
627 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
628 kvm_set_pfn_dirty(pfn);
633 * Rules for using mmu_spte_clear_no_track:
634 * Directly clear spte without caring the state bits of sptep,
635 * it is used to set the upper level spte.
637 static void mmu_spte_clear_no_track(u64 *sptep)
639 __update_clear_spte_fast(sptep, 0ull);
642 static u64 mmu_spte_get_lockless(u64 *sptep)
644 return __get_spte_lockless(sptep);
647 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
650 * Prevent page table teardown by making any free-er wait during
651 * kvm_flush_remote_tlbs() IPI to all active vcpus.
654 vcpu->mode = READING_SHADOW_PAGE_TABLES;
656 * Make sure a following spte read is not reordered ahead of the write
662 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
665 * Make sure the write to vcpu->mode is not reordered in front of
666 * reads to sptes. If it does, kvm_commit_zap_page() can see us
667 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
670 vcpu->mode = OUTSIDE_GUEST_MODE;
674 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
675 struct kmem_cache *base_cache, int min)
679 if (cache->nobjs >= min)
681 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
682 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
685 cache->objects[cache->nobjs++] = obj;
690 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
695 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
696 struct kmem_cache *cache)
699 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
702 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
707 if (cache->nobjs >= min)
709 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
710 page = (void *)__get_free_page(GFP_KERNEL);
713 cache->objects[cache->nobjs++] = page;
718 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
721 free_page((unsigned long)mc->objects[--mc->nobjs]);
724 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
728 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
729 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
732 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
735 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
736 mmu_page_header_cache, 4);
741 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
743 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
744 pte_list_desc_cache);
745 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
746 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
747 mmu_page_header_cache);
750 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
755 p = mc->objects[--mc->nobjs];
759 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
761 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
764 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
766 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
769 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
771 if (!sp->role.direct)
772 return sp->gfns[index];
774 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
777 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
780 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
782 sp->gfns[index] = gfn;
786 * Return the pointer to the large page information for a given gfn,
787 * handling slots that are not large page aligned.
789 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
790 struct kvm_memory_slot *slot,
795 idx = gfn_to_index(gfn, slot->base_gfn, level);
796 return &slot->arch.lpage_info[level - 2][idx];
799 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
801 struct kvm_memory_slot *slot;
802 struct kvm_lpage_info *linfo;
805 slot = gfn_to_memslot(kvm, gfn);
806 for (i = PT_DIRECTORY_LEVEL;
807 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
808 linfo = lpage_info_slot(gfn, slot, i);
809 linfo->write_count += 1;
811 kvm->arch.indirect_shadow_pages++;
814 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
816 struct kvm_memory_slot *slot;
817 struct kvm_lpage_info *linfo;
820 slot = gfn_to_memslot(kvm, gfn);
821 for (i = PT_DIRECTORY_LEVEL;
822 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
823 linfo = lpage_info_slot(gfn, slot, i);
824 linfo->write_count -= 1;
825 WARN_ON(linfo->write_count < 0);
827 kvm->arch.indirect_shadow_pages--;
830 static int has_wrprotected_page(struct kvm *kvm,
834 struct kvm_memory_slot *slot;
835 struct kvm_lpage_info *linfo;
837 slot = gfn_to_memslot(kvm, gfn);
839 linfo = lpage_info_slot(gfn, slot, level);
840 return linfo->write_count;
846 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
848 unsigned long page_size;
851 page_size = kvm_host_page_size(kvm, gfn);
853 for (i = PT_PAGE_TABLE_LEVEL;
854 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
855 if (page_size >= KVM_HPAGE_SIZE(i))
864 static struct kvm_memory_slot *
865 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
868 struct kvm_memory_slot *slot;
870 slot = gfn_to_memslot(vcpu->kvm, gfn);
871 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
872 (no_dirty_log && slot->dirty_bitmap))
878 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
880 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
883 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
885 int host_level, level, max_level;
887 host_level = host_mapping_level(vcpu->kvm, large_gfn);
889 if (host_level == PT_PAGE_TABLE_LEVEL)
892 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
894 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
895 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
902 * Pte mapping structures:
904 * If pte_list bit zero is zero, then pte_list point to the spte.
906 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
907 * pte_list_desc containing more mappings.
909 * Returns the number of pte entries before the spte was added or zero if
910 * the spte was not added.
913 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
914 unsigned long *pte_list)
916 struct pte_list_desc *desc;
920 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
921 *pte_list = (unsigned long)spte;
922 } else if (!(*pte_list & 1)) {
923 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
924 desc = mmu_alloc_pte_list_desc(vcpu);
925 desc->sptes[0] = (u64 *)*pte_list;
926 desc->sptes[1] = spte;
927 *pte_list = (unsigned long)desc | 1;
930 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
931 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
932 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
934 count += PTE_LIST_EXT;
936 if (desc->sptes[PTE_LIST_EXT-1]) {
937 desc->more = mmu_alloc_pte_list_desc(vcpu);
940 for (i = 0; desc->sptes[i]; ++i)
942 desc->sptes[i] = spte;
948 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
949 int i, struct pte_list_desc *prev_desc)
953 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
955 desc->sptes[i] = desc->sptes[j];
956 desc->sptes[j] = NULL;
959 if (!prev_desc && !desc->more)
960 *pte_list = (unsigned long)desc->sptes[0];
963 prev_desc->more = desc->more;
965 *pte_list = (unsigned long)desc->more | 1;
966 mmu_free_pte_list_desc(desc);
969 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
971 struct pte_list_desc *desc;
972 struct pte_list_desc *prev_desc;
976 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
978 } else if (!(*pte_list & 1)) {
979 rmap_printk("pte_list_remove: %p 1->0\n", spte);
980 if ((u64 *)*pte_list != spte) {
981 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
986 rmap_printk("pte_list_remove: %p many->many\n", spte);
987 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
990 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
991 if (desc->sptes[i] == spte) {
992 pte_list_desc_remove_entry(pte_list,
1000 pr_err("pte_list_remove: %p many->many\n", spte);
1005 typedef void (*pte_list_walk_fn) (u64 *spte);
1006 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
1008 struct pte_list_desc *desc;
1014 if (!(*pte_list & 1))
1015 return fn((u64 *)*pte_list);
1017 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1019 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1025 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
1026 struct kvm_memory_slot *slot)
1030 idx = gfn_to_index(gfn, slot->base_gfn, level);
1031 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1035 * Take gfn and return the reverse mapping to it.
1037 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
1039 struct kvm_memory_slot *slot;
1041 slot = gfn_to_memslot(kvm, gfn);
1042 return __gfn_to_rmap(gfn, level, slot);
1045 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1047 struct kvm_mmu_memory_cache *cache;
1049 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1050 return mmu_memory_cache_free_objects(cache);
1053 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1055 struct kvm_mmu_page *sp;
1056 unsigned long *rmapp;
1058 sp = page_header(__pa(spte));
1059 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1060 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1061 return pte_list_add(vcpu, spte, rmapp);
1064 static void rmap_remove(struct kvm *kvm, u64 *spte)
1066 struct kvm_mmu_page *sp;
1068 unsigned long *rmapp;
1070 sp = page_header(__pa(spte));
1071 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1072 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1073 pte_list_remove(spte, rmapp);
1077 * Used by the following functions to iterate through the sptes linked by a
1078 * rmap. All fields are private and not assumed to be used outside.
1080 struct rmap_iterator {
1081 /* private fields */
1082 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1083 int pos; /* index of the sptep */
1087 * Iteration must be started by this function. This should also be used after
1088 * removing/dropping sptes from the rmap link because in such cases the
1089 * information in the itererator may not be valid.
1091 * Returns sptep if found, NULL otherwise.
1093 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1103 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1105 return iter->desc->sptes[iter->pos];
1109 * Must be used with a valid iterator: e.g. after rmap_get_first().
1111 * Returns sptep if found, NULL otherwise.
1113 static u64 *rmap_get_next(struct rmap_iterator *iter)
1116 if (iter->pos < PTE_LIST_EXT - 1) {
1120 sptep = iter->desc->sptes[iter->pos];
1125 iter->desc = iter->desc->more;
1129 /* desc->sptes[0] cannot be NULL */
1130 return iter->desc->sptes[iter->pos];
1137 static void drop_spte(struct kvm *kvm, u64 *sptep)
1139 if (mmu_spte_clear_track_bits(sptep))
1140 rmap_remove(kvm, sptep);
1144 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1146 if (is_large_pte(*sptep)) {
1147 WARN_ON(page_header(__pa(sptep))->role.level ==
1148 PT_PAGE_TABLE_LEVEL);
1149 drop_spte(kvm, sptep);
1157 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1159 if (__drop_large_spte(vcpu->kvm, sptep))
1160 kvm_flush_remote_tlbs(vcpu->kvm);
1164 * Write-protect on the specified @sptep, @pt_protect indicates whether
1165 * spte writ-protection is caused by protecting shadow page table.
1166 * @flush indicates whether tlb need be flushed.
1168 * Note: write protection is difference between drity logging and spte
1170 * - for dirty logging, the spte can be set to writable at anytime if
1171 * its dirty bitmap is properly set.
1172 * - for spte protection, the spte can be writable only after unsync-ing
1175 * Return true if the spte is dropped.
1178 spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1182 if (!is_writable_pte(spte) &&
1183 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1186 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1188 if (__drop_large_spte(kvm, sptep)) {
1194 spte &= ~SPTE_MMU_WRITEABLE;
1195 spte = spte & ~PT_WRITABLE_MASK;
1197 *flush |= mmu_spte_update(sptep, spte);
1201 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1205 struct rmap_iterator iter;
1208 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1209 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1210 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1211 sptep = rmap_get_first(*rmapp, &iter);
1215 sptep = rmap_get_next(&iter);
1222 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1223 * @kvm: kvm instance
1224 * @slot: slot to protect
1225 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1226 * @mask: indicates which pages we should protect
1228 * Used when we do not need to care about huge page mappings: e.g. during dirty
1229 * logging we do not have any such mappings.
1231 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1232 struct kvm_memory_slot *slot,
1233 gfn_t gfn_offset, unsigned long mask)
1235 unsigned long *rmapp;
1238 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1239 PT_PAGE_TABLE_LEVEL, slot);
1240 __rmap_write_protect(kvm, rmapp, false);
1242 /* clear the first set bit */
1247 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1249 struct kvm_memory_slot *slot;
1250 unsigned long *rmapp;
1252 bool write_protected = false;
1254 slot = gfn_to_memslot(kvm, gfn);
1256 for (i = PT_PAGE_TABLE_LEVEL;
1257 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1258 rmapp = __gfn_to_rmap(gfn, i, slot);
1259 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1262 return write_protected;
1265 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1266 struct kvm_memory_slot *slot, unsigned long data)
1269 struct rmap_iterator iter;
1270 int need_tlb_flush = 0;
1272 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1273 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1274 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1276 drop_spte(kvm, sptep);
1280 return need_tlb_flush;
1283 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1284 struct kvm_memory_slot *slot, unsigned long data)
1287 struct rmap_iterator iter;
1290 pte_t *ptep = (pte_t *)data;
1293 WARN_ON(pte_huge(*ptep));
1294 new_pfn = pte_pfn(*ptep);
1296 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1297 BUG_ON(!is_shadow_present_pte(*sptep));
1298 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1302 if (pte_write(*ptep)) {
1303 drop_spte(kvm, sptep);
1304 sptep = rmap_get_first(*rmapp, &iter);
1306 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1307 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1309 new_spte &= ~PT_WRITABLE_MASK;
1310 new_spte &= ~SPTE_HOST_WRITEABLE;
1311 new_spte &= ~shadow_accessed_mask;
1313 mmu_spte_clear_track_bits(sptep);
1314 mmu_spte_set(sptep, new_spte);
1315 sptep = rmap_get_next(&iter);
1320 kvm_flush_remote_tlbs(kvm);
1325 static int kvm_handle_hva_range(struct kvm *kvm,
1326 unsigned long start,
1329 int (*handler)(struct kvm *kvm,
1330 unsigned long *rmapp,
1331 struct kvm_memory_slot *slot,
1332 unsigned long data))
1336 struct kvm_memslots *slots;
1337 struct kvm_memory_slot *memslot;
1339 slots = kvm_memslots(kvm);
1341 kvm_for_each_memslot(memslot, slots) {
1342 unsigned long hva_start, hva_end;
1343 gfn_t gfn_start, gfn_end;
1345 hva_start = max(start, memslot->userspace_addr);
1346 hva_end = min(end, memslot->userspace_addr +
1347 (memslot->npages << PAGE_SHIFT));
1348 if (hva_start >= hva_end)
1351 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1352 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1354 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1355 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1357 for (j = PT_PAGE_TABLE_LEVEL;
1358 j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1359 unsigned long idx, idx_end;
1360 unsigned long *rmapp;
1363 * {idx(page_j) | page_j intersects with
1364 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1366 idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1367 idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1369 rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1371 for (; idx <= idx_end; ++idx)
1372 ret |= handler(kvm, rmapp++, memslot, data);
1379 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1381 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1382 struct kvm_memory_slot *slot,
1383 unsigned long data))
1385 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1388 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1390 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1393 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1395 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1398 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1400 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1403 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1404 struct kvm_memory_slot *slot, unsigned long data)
1407 struct rmap_iterator uninitialized_var(iter);
1411 * In case of absence of EPT Access and Dirty Bits supports,
1412 * emulate the accessed bit for EPT, by checking if this page has
1413 * an EPT mapping, and clearing it if it does. On the next access,
1414 * a new EPT mapping will be established.
1415 * This has some overhead, but not as much as the cost of swapping
1416 * out actively used pages or breaking up actively used hugepages.
1418 if (!shadow_accessed_mask) {
1419 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1423 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1424 sptep = rmap_get_next(&iter)) {
1425 BUG_ON(!is_shadow_present_pte(*sptep));
1427 if (*sptep & shadow_accessed_mask) {
1429 clear_bit((ffs(shadow_accessed_mask) - 1),
1430 (unsigned long *)sptep);
1434 /* @data has hva passed to kvm_age_hva(). */
1435 trace_kvm_age_page(data, slot, young);
1439 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1440 struct kvm_memory_slot *slot, unsigned long data)
1443 struct rmap_iterator iter;
1447 * If there's no access bit in the secondary pte set by the
1448 * hardware it's up to gup-fast/gup to set the access bit in
1449 * the primary pte or in the page structure.
1451 if (!shadow_accessed_mask)
1454 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1455 sptep = rmap_get_next(&iter)) {
1456 BUG_ON(!is_shadow_present_pte(*sptep));
1458 if (*sptep & shadow_accessed_mask) {
1467 #define RMAP_RECYCLE_THRESHOLD 1000
1469 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1471 unsigned long *rmapp;
1472 struct kvm_mmu_page *sp;
1474 sp = page_header(__pa(spte));
1476 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1478 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1479 kvm_flush_remote_tlbs(vcpu->kvm);
1482 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1484 return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1487 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1489 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1493 static int is_empty_shadow_page(u64 *spt)
1498 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1499 if (is_shadow_present_pte(*pos)) {
1500 printk(KERN_ERR "%s: %p %llx\n", __func__,
1509 * This value is the sum of all of the kvm instances's
1510 * kvm->arch.n_used_mmu_pages values. We need a global,
1511 * aggregate version in order to make the slab shrinker
1514 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1516 kvm->arch.n_used_mmu_pages += nr;
1517 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1520 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1522 ASSERT(is_empty_shadow_page(sp->spt));
1523 hlist_del(&sp->hash_link);
1524 list_del(&sp->link);
1525 free_page((unsigned long)sp->spt);
1526 if (!sp->role.direct)
1527 free_page((unsigned long)sp->gfns);
1528 kmem_cache_free(mmu_page_header_cache, sp);
1531 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1533 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1536 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1537 struct kvm_mmu_page *sp, u64 *parent_pte)
1542 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1545 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1548 pte_list_remove(parent_pte, &sp->parent_ptes);
1551 static void drop_parent_pte(struct kvm_mmu_page *sp,
1554 mmu_page_remove_parent_pte(sp, parent_pte);
1555 mmu_spte_clear_no_track(parent_pte);
1558 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1559 u64 *parent_pte, int direct)
1561 struct kvm_mmu_page *sp;
1563 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1564 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1566 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1567 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1570 * The active_mmu_pages list is the FIFO list, do not move the
1571 * page until it is zapped. kvm_zap_obsolete_pages depends on
1572 * this feature. See the comments in kvm_zap_obsolete_pages().
1574 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1575 sp->parent_ptes = 0;
1576 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1577 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1581 static void mark_unsync(u64 *spte);
1582 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1584 pte_list_walk(&sp->parent_ptes, mark_unsync);
1587 static void mark_unsync(u64 *spte)
1589 struct kvm_mmu_page *sp;
1592 sp = page_header(__pa(spte));
1593 index = spte - sp->spt;
1594 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1596 if (sp->unsync_children++)
1598 kvm_mmu_mark_parents_unsync(sp);
1601 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1602 struct kvm_mmu_page *sp)
1607 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1611 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1612 struct kvm_mmu_page *sp, u64 *spte,
1618 #define KVM_PAGE_ARRAY_NR 16
1620 struct kvm_mmu_pages {
1621 struct mmu_page_and_offset {
1622 struct kvm_mmu_page *sp;
1624 } page[KVM_PAGE_ARRAY_NR];
1628 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1634 for (i=0; i < pvec->nr; i++)
1635 if (pvec->page[i].sp == sp)
1638 pvec->page[pvec->nr].sp = sp;
1639 pvec->page[pvec->nr].idx = idx;
1641 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1644 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1645 struct kvm_mmu_pages *pvec)
1647 int i, ret, nr_unsync_leaf = 0;
1649 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1650 struct kvm_mmu_page *child;
1651 u64 ent = sp->spt[i];
1653 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1654 goto clear_child_bitmap;
1656 child = page_header(ent & PT64_BASE_ADDR_MASK);
1658 if (child->unsync_children) {
1659 if (mmu_pages_add(pvec, child, i))
1662 ret = __mmu_unsync_walk(child, pvec);
1664 goto clear_child_bitmap;
1666 nr_unsync_leaf += ret;
1669 } else if (child->unsync) {
1671 if (mmu_pages_add(pvec, child, i))
1674 goto clear_child_bitmap;
1679 __clear_bit(i, sp->unsync_child_bitmap);
1680 sp->unsync_children--;
1681 WARN_ON((int)sp->unsync_children < 0);
1685 return nr_unsync_leaf;
1688 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1689 struct kvm_mmu_pages *pvec)
1691 if (!sp->unsync_children)
1694 mmu_pages_add(pvec, sp, 0);
1695 return __mmu_unsync_walk(sp, pvec);
1698 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1700 WARN_ON(!sp->unsync);
1701 trace_kvm_mmu_sync_page(sp);
1703 --kvm->stat.mmu_unsync;
1706 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1707 struct list_head *invalid_list);
1708 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1709 struct list_head *invalid_list);
1712 * NOTE: we should pay more attention on the zapped-obsolete page
1713 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1714 * since it has been deleted from active_mmu_pages but still can be found
1717 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1718 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1719 * all the obsolete pages.
1721 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1722 hlist_for_each_entry(_sp, \
1723 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1724 if ((_sp)->gfn != (_gfn)) {} else
1726 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1727 for_each_gfn_sp(_kvm, _sp, _gfn) \
1728 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1730 /* @sp->gfn should be write-protected at the call site */
1731 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1732 struct list_head *invalid_list, bool clear_unsync)
1734 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1735 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1740 kvm_unlink_unsync_page(vcpu->kvm, sp);
1742 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1743 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1747 kvm_mmu_flush_tlb(vcpu);
1751 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1752 struct kvm_mmu_page *sp)
1754 LIST_HEAD(invalid_list);
1757 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1759 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1764 #ifdef CONFIG_KVM_MMU_AUDIT
1765 #include "mmu_audit.c"
1767 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1768 static void mmu_audit_disable(void) { }
1771 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1772 struct list_head *invalid_list)
1774 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1777 /* @gfn should be write-protected at the call site */
1778 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1780 struct kvm_mmu_page *s;
1781 LIST_HEAD(invalid_list);
1784 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1788 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1789 kvm_unlink_unsync_page(vcpu->kvm, s);
1790 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1791 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1792 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1798 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1800 kvm_mmu_flush_tlb(vcpu);
1803 struct mmu_page_path {
1804 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1805 unsigned int idx[PT64_ROOT_LEVEL-1];
1808 #define for_each_sp(pvec, sp, parents, i) \
1809 for (i = mmu_pages_next(&pvec, &parents, -1), \
1810 sp = pvec.page[i].sp; \
1811 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1812 i = mmu_pages_next(&pvec, &parents, i))
1814 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1815 struct mmu_page_path *parents,
1820 for (n = i+1; n < pvec->nr; n++) {
1821 struct kvm_mmu_page *sp = pvec->page[n].sp;
1823 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1824 parents->idx[0] = pvec->page[n].idx;
1828 parents->parent[sp->role.level-2] = sp;
1829 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1835 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1837 struct kvm_mmu_page *sp;
1838 unsigned int level = 0;
1841 unsigned int idx = parents->idx[level];
1843 sp = parents->parent[level];
1847 --sp->unsync_children;
1848 WARN_ON((int)sp->unsync_children < 0);
1849 __clear_bit(idx, sp->unsync_child_bitmap);
1851 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1854 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1855 struct mmu_page_path *parents,
1856 struct kvm_mmu_pages *pvec)
1858 parents->parent[parent->role.level-1] = NULL;
1862 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1863 struct kvm_mmu_page *parent)
1866 struct kvm_mmu_page *sp;
1867 struct mmu_page_path parents;
1868 struct kvm_mmu_pages pages;
1869 LIST_HEAD(invalid_list);
1871 kvm_mmu_pages_init(parent, &parents, &pages);
1872 while (mmu_unsync_walk(parent, &pages)) {
1873 bool protected = false;
1875 for_each_sp(pages, sp, parents, i)
1876 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1879 kvm_flush_remote_tlbs(vcpu->kvm);
1881 for_each_sp(pages, sp, parents, i) {
1882 kvm_sync_page(vcpu, sp, &invalid_list);
1883 mmu_pages_clear_parents(&parents);
1885 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1886 cond_resched_lock(&vcpu->kvm->mmu_lock);
1887 kvm_mmu_pages_init(parent, &parents, &pages);
1891 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1895 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1899 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1901 sp->write_flooding_count = 0;
1904 static void clear_sp_write_flooding_count(u64 *spte)
1906 struct kvm_mmu_page *sp = page_header(__pa(spte));
1908 __clear_sp_write_flooding_count(sp);
1911 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1913 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1916 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1924 union kvm_mmu_page_role role;
1926 struct kvm_mmu_page *sp;
1927 bool need_sync = false;
1929 role = vcpu->arch.mmu.base_role;
1931 role.direct = direct;
1934 role.access = access;
1935 if (!vcpu->arch.mmu.direct_map
1936 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1937 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1938 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1939 role.quadrant = quadrant;
1941 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
1942 if (is_obsolete_sp(vcpu->kvm, sp))
1945 if (!need_sync && sp->unsync)
1948 if (sp->role.word != role.word)
1951 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1954 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1955 if (sp->unsync_children) {
1956 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1957 kvm_mmu_mark_parents_unsync(sp);
1958 } else if (sp->unsync)
1959 kvm_mmu_mark_parents_unsync(sp);
1961 __clear_sp_write_flooding_count(sp);
1962 trace_kvm_mmu_get_page(sp, false);
1965 ++vcpu->kvm->stat.mmu_cache_miss;
1966 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1971 hlist_add_head(&sp->hash_link,
1972 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1974 if (rmap_write_protect(vcpu->kvm, gfn))
1975 kvm_flush_remote_tlbs(vcpu->kvm);
1976 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1977 kvm_sync_pages(vcpu, gfn);
1979 account_shadowed(vcpu->kvm, gfn);
1981 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1982 init_shadow_page_table(sp);
1983 trace_kvm_mmu_get_page(sp, true);
1987 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1988 struct kvm_vcpu *vcpu, u64 addr)
1990 iterator->addr = addr;
1991 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1992 iterator->level = vcpu->arch.mmu.shadow_root_level;
1994 if (iterator->level == PT64_ROOT_LEVEL &&
1995 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1996 !vcpu->arch.mmu.direct_map)
1999 if (iterator->level == PT32E_ROOT_LEVEL) {
2000 iterator->shadow_addr
2001 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2002 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2004 if (!iterator->shadow_addr)
2005 iterator->level = 0;
2009 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2011 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2014 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2015 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2019 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2022 if (is_last_spte(spte, iterator->level)) {
2023 iterator->level = 0;
2027 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2031 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2033 return __shadow_walk_next(iterator, *iterator->sptep);
2036 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
2040 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2041 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
2043 mmu_spte_set(sptep, spte);
2046 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2047 unsigned direct_access)
2049 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2050 struct kvm_mmu_page *child;
2053 * For the direct sp, if the guest pte's dirty bit
2054 * changed form clean to dirty, it will corrupt the
2055 * sp's access: allow writable in the read-only sp,
2056 * so we should update the spte at this point to get
2057 * a new sp with the correct access.
2059 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2060 if (child->role.access == direct_access)
2063 drop_parent_pte(child, sptep);
2064 kvm_flush_remote_tlbs(vcpu->kvm);
2068 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2072 struct kvm_mmu_page *child;
2075 if (is_shadow_present_pte(pte)) {
2076 if (is_last_spte(pte, sp->role.level)) {
2077 drop_spte(kvm, spte);
2078 if (is_large_pte(pte))
2081 child = page_header(pte & PT64_BASE_ADDR_MASK);
2082 drop_parent_pte(child, spte);
2087 if (is_mmio_spte(pte))
2088 mmu_spte_clear_no_track(spte);
2093 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2094 struct kvm_mmu_page *sp)
2098 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2099 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2102 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2104 mmu_page_remove_parent_pte(sp, parent_pte);
2107 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2110 struct rmap_iterator iter;
2112 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2113 drop_parent_pte(sp, sptep);
2116 static int mmu_zap_unsync_children(struct kvm *kvm,
2117 struct kvm_mmu_page *parent,
2118 struct list_head *invalid_list)
2121 struct mmu_page_path parents;
2122 struct kvm_mmu_pages pages;
2124 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2127 kvm_mmu_pages_init(parent, &parents, &pages);
2128 while (mmu_unsync_walk(parent, &pages)) {
2129 struct kvm_mmu_page *sp;
2131 for_each_sp(pages, sp, parents, i) {
2132 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2133 mmu_pages_clear_parents(&parents);
2136 kvm_mmu_pages_init(parent, &parents, &pages);
2142 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2143 struct list_head *invalid_list)
2147 trace_kvm_mmu_prepare_zap_page(sp);
2148 ++kvm->stat.mmu_shadow_zapped;
2149 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2150 kvm_mmu_page_unlink_children(kvm, sp);
2151 kvm_mmu_unlink_parents(kvm, sp);
2153 if (!sp->role.invalid && !sp->role.direct)
2154 unaccount_shadowed(kvm, sp->gfn);
2157 kvm_unlink_unsync_page(kvm, sp);
2158 if (!sp->root_count) {
2161 list_move(&sp->link, invalid_list);
2162 kvm_mod_used_mmu_pages(kvm, -1);
2164 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2167 * The obsolete pages can not be used on any vcpus.
2168 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2170 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2171 kvm_reload_remote_mmus(kvm);
2174 sp->role.invalid = 1;
2178 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2179 struct list_head *invalid_list)
2181 struct kvm_mmu_page *sp, *nsp;
2183 if (list_empty(invalid_list))
2187 * wmb: make sure everyone sees our modifications to the page tables
2188 * rmb: make sure we see changes to vcpu->mode
2193 * Wait for all vcpus to exit guest mode and/or lockless shadow
2196 kvm_flush_remote_tlbs(kvm);
2198 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2199 WARN_ON(!sp->role.invalid || sp->root_count);
2200 kvm_mmu_free_page(sp);
2204 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2205 struct list_head *invalid_list)
2207 struct kvm_mmu_page *sp;
2209 if (list_empty(&kvm->arch.active_mmu_pages))
2212 sp = list_entry(kvm->arch.active_mmu_pages.prev,
2213 struct kvm_mmu_page, link);
2214 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2220 * Changing the number of mmu pages allocated to the vm
2221 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2223 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2225 LIST_HEAD(invalid_list);
2227 spin_lock(&kvm->mmu_lock);
2229 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2230 /* Need to free some mmu pages to achieve the goal. */
2231 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2232 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2235 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2236 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2239 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2241 spin_unlock(&kvm->mmu_lock);
2244 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2246 struct kvm_mmu_page *sp;
2247 LIST_HEAD(invalid_list);
2250 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2252 spin_lock(&kvm->mmu_lock);
2253 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2254 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2257 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2259 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2260 spin_unlock(&kvm->mmu_lock);
2264 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2267 * The function is based on mtrr_type_lookup() in
2268 * arch/x86/kernel/cpu/mtrr/generic.c
2270 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2275 u8 prev_match, curr_match;
2276 int num_var_ranges = KVM_NR_VAR_MTRR;
2278 if (!mtrr_state->enabled)
2281 /* Make end inclusive end, instead of exclusive */
2284 /* Look in fixed ranges. Just return the type as per start */
2285 if (mtrr_state->have_fixed && (start < 0x100000)) {
2288 if (start < 0x80000) {
2290 idx += (start >> 16);
2291 return mtrr_state->fixed_ranges[idx];
2292 } else if (start < 0xC0000) {
2294 idx += ((start - 0x80000) >> 14);
2295 return mtrr_state->fixed_ranges[idx];
2296 } else if (start < 0x1000000) {
2298 idx += ((start - 0xC0000) >> 12);
2299 return mtrr_state->fixed_ranges[idx];
2304 * Look in variable ranges
2305 * Look of multiple ranges matching this address and pick type
2306 * as per MTRR precedence
2308 if (!(mtrr_state->enabled & 2))
2309 return mtrr_state->def_type;
2312 for (i = 0; i < num_var_ranges; ++i) {
2313 unsigned short start_state, end_state;
2315 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2318 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2319 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2320 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2321 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2323 start_state = ((start & mask) == (base & mask));
2324 end_state = ((end & mask) == (base & mask));
2325 if (start_state != end_state)
2328 if ((start & mask) != (base & mask))
2331 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2332 if (prev_match == 0xFF) {
2333 prev_match = curr_match;
2337 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2338 curr_match == MTRR_TYPE_UNCACHABLE)
2339 return MTRR_TYPE_UNCACHABLE;
2341 if ((prev_match == MTRR_TYPE_WRBACK &&
2342 curr_match == MTRR_TYPE_WRTHROUGH) ||
2343 (prev_match == MTRR_TYPE_WRTHROUGH &&
2344 curr_match == MTRR_TYPE_WRBACK)) {
2345 prev_match = MTRR_TYPE_WRTHROUGH;
2346 curr_match = MTRR_TYPE_WRTHROUGH;
2349 if (prev_match != curr_match)
2350 return MTRR_TYPE_UNCACHABLE;
2353 if (prev_match != 0xFF)
2356 return mtrr_state->def_type;
2359 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2363 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2364 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2365 if (mtrr == 0xfe || mtrr == 0xff)
2366 mtrr = MTRR_TYPE_WRBACK;
2369 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2371 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2373 trace_kvm_mmu_unsync_page(sp);
2374 ++vcpu->kvm->stat.mmu_unsync;
2377 kvm_mmu_mark_parents_unsync(sp);
2380 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2382 struct kvm_mmu_page *s;
2384 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2387 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2388 __kvm_unsync_page(vcpu, s);
2392 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2395 struct kvm_mmu_page *s;
2396 bool need_unsync = false;
2398 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2402 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2409 kvm_unsync_pages(vcpu, gfn);
2413 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2414 unsigned pte_access, int level,
2415 gfn_t gfn, pfn_t pfn, bool speculative,
2416 bool can_unsync, bool host_writable)
2421 if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access))
2424 spte = PT_PRESENT_MASK;
2426 spte |= shadow_accessed_mask;
2428 if (pte_access & ACC_EXEC_MASK)
2429 spte |= shadow_x_mask;
2431 spte |= shadow_nx_mask;
2433 if (pte_access & ACC_USER_MASK)
2434 spte |= shadow_user_mask;
2436 if (level > PT_PAGE_TABLE_LEVEL)
2437 spte |= PT_PAGE_SIZE_MASK;
2439 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2440 kvm_is_mmio_pfn(pfn));
2443 spte |= SPTE_HOST_WRITEABLE;
2445 pte_access &= ~ACC_WRITE_MASK;
2447 spte |= (u64)pfn << PAGE_SHIFT;
2449 if (pte_access & ACC_WRITE_MASK) {
2452 * Other vcpu creates new sp in the window between
2453 * mapping_level() and acquiring mmu-lock. We can
2454 * allow guest to retry the access, the mapping can
2455 * be fixed if guest refault.
2457 if (level > PT_PAGE_TABLE_LEVEL &&
2458 has_wrprotected_page(vcpu->kvm, gfn, level))
2461 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2464 * Optimization: for pte sync, if spte was writable the hash
2465 * lookup is unnecessary (and expensive). Write protection
2466 * is responsibility of mmu_get_page / kvm_sync_page.
2467 * Same reasoning can be applied to dirty page accounting.
2469 if (!can_unsync && is_writable_pte(*sptep))
2472 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2473 pgprintk("%s: found shadow page for %llx, marking ro\n",
2476 pte_access &= ~ACC_WRITE_MASK;
2477 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2481 if (pte_access & ACC_WRITE_MASK)
2482 mark_page_dirty(vcpu->kvm, gfn);
2485 if (mmu_spte_update(sptep, spte))
2486 kvm_flush_remote_tlbs(vcpu->kvm);
2491 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2492 unsigned pte_access, int write_fault, int *emulate,
2493 int level, gfn_t gfn, pfn_t pfn, bool speculative,
2496 int was_rmapped = 0;
2499 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2500 *sptep, write_fault, gfn);
2502 if (is_rmap_spte(*sptep)) {
2504 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2505 * the parent of the now unreachable PTE.
2507 if (level > PT_PAGE_TABLE_LEVEL &&
2508 !is_large_pte(*sptep)) {
2509 struct kvm_mmu_page *child;
2512 child = page_header(pte & PT64_BASE_ADDR_MASK);
2513 drop_parent_pte(child, sptep);
2514 kvm_flush_remote_tlbs(vcpu->kvm);
2515 } else if (pfn != spte_to_pfn(*sptep)) {
2516 pgprintk("hfn old %llx new %llx\n",
2517 spte_to_pfn(*sptep), pfn);
2518 drop_spte(vcpu->kvm, sptep);
2519 kvm_flush_remote_tlbs(vcpu->kvm);
2524 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2525 true, host_writable)) {
2528 kvm_mmu_flush_tlb(vcpu);
2531 if (unlikely(is_mmio_spte(*sptep) && emulate))
2534 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2535 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2536 is_large_pte(*sptep)? "2MB" : "4kB",
2537 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2539 if (!was_rmapped && is_large_pte(*sptep))
2540 ++vcpu->kvm->stat.lpages;
2542 if (is_shadow_present_pte(*sptep)) {
2544 rmap_count = rmap_add(vcpu, sptep, gfn);
2545 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2546 rmap_recycle(vcpu, sptep, gfn);
2550 kvm_release_pfn_clean(pfn);
2553 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2555 mmu_free_roots(vcpu);
2558 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2562 bit7 = (gpte >> 7) & 1;
2563 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2566 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2569 struct kvm_memory_slot *slot;
2571 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2573 return KVM_PFN_ERR_FAULT;
2575 return gfn_to_pfn_memslot_atomic(slot, gfn);
2578 static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu,
2579 struct kvm_mmu_page *sp, u64 *spte,
2582 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
2585 if (!is_present_gpte(gpte))
2588 if (!(gpte & PT_ACCESSED_MASK))
2594 drop_spte(vcpu->kvm, spte);
2598 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2599 struct kvm_mmu_page *sp,
2600 u64 *start, u64 *end)
2602 struct page *pages[PTE_PREFETCH_NUM];
2603 unsigned access = sp->role.access;
2607 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2608 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2611 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2615 for (i = 0; i < ret; i++, gfn++, start++)
2616 mmu_set_spte(vcpu, start, access, 0, NULL,
2617 sp->role.level, gfn, page_to_pfn(pages[i]),
2623 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2624 struct kvm_mmu_page *sp, u64 *sptep)
2626 u64 *spte, *start = NULL;
2629 WARN_ON(!sp->role.direct);
2631 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2634 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2635 if (is_shadow_present_pte(*spte) || spte == sptep) {
2638 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2646 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2648 struct kvm_mmu_page *sp;
2651 * Since it's no accessed bit on EPT, it's no way to
2652 * distinguish between actually accessed translations
2653 * and prefetched, so disable pte prefetch if EPT is
2656 if (!shadow_accessed_mask)
2659 sp = page_header(__pa(sptep));
2660 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2663 __direct_pte_prefetch(vcpu, sp, sptep);
2666 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2667 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2670 struct kvm_shadow_walk_iterator iterator;
2671 struct kvm_mmu_page *sp;
2675 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2676 if (iterator.level == level) {
2677 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2678 write, &emulate, level, gfn, pfn,
2679 prefault, map_writable);
2680 direct_pte_prefetch(vcpu, iterator.sptep);
2681 ++vcpu->stat.pf_fixed;
2685 if (!is_shadow_present_pte(*iterator.sptep)) {
2686 u64 base_addr = iterator.addr;
2688 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2689 pseudo_gfn = base_addr >> PAGE_SHIFT;
2690 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2692 1, ACC_ALL, iterator.sptep);
2694 link_shadow_page(iterator.sptep, sp);
2700 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2704 info.si_signo = SIGBUS;
2706 info.si_code = BUS_MCEERR_AR;
2707 info.si_addr = (void __user *)address;
2708 info.si_addr_lsb = PAGE_SHIFT;
2710 send_sig_info(SIGBUS, &info, tsk);
2713 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2716 * Do not cache the mmio info caused by writing the readonly gfn
2717 * into the spte otherwise read access on readonly gfn also can
2718 * caused mmio page fault and treat it as mmio access.
2719 * Return 1 to tell kvm to emulate it.
2721 if (pfn == KVM_PFN_ERR_RO_FAULT)
2724 if (pfn == KVM_PFN_ERR_HWPOISON) {
2725 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2732 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2733 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2737 int level = *levelp;
2740 * Check if it's a transparent hugepage. If this would be an
2741 * hugetlbfs page, level wouldn't be set to
2742 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2745 if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2746 level == PT_PAGE_TABLE_LEVEL &&
2747 PageTransCompound(pfn_to_page(pfn)) &&
2748 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2751 * mmu_notifier_retry was successful and we hold the
2752 * mmu_lock here, so the pmd can't become splitting
2753 * from under us, and in turn
2754 * __split_huge_page_refcount() can't run from under
2755 * us and we can safely transfer the refcount from
2756 * PG_tail to PG_head as we switch the pfn to tail to
2759 *levelp = level = PT_DIRECTORY_LEVEL;
2760 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2761 VM_BUG_ON((gfn & mask) != (pfn & mask));
2765 kvm_release_pfn_clean(pfn);
2773 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2774 pfn_t pfn, unsigned access, int *ret_val)
2778 /* The pfn is invalid, report the error! */
2779 if (unlikely(is_error_pfn(pfn))) {
2780 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2784 if (unlikely(is_noslot_pfn(pfn)))
2785 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2792 static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
2795 * #PF can be fast only if the shadow page table is present and it
2796 * is caused by write-protect, that means we just need change the
2797 * W bit of the spte which can be done out of mmu-lock.
2799 if (!(error_code & PFERR_PRESENT_MASK) ||
2800 !(error_code & PFERR_WRITE_MASK))
2807 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2809 struct kvm_mmu_page *sp = page_header(__pa(sptep));
2812 WARN_ON(!sp->role.direct);
2815 * The gfn of direct spte is stable since it is calculated
2818 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2820 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2821 mark_page_dirty(vcpu->kvm, gfn);
2828 * - true: let the vcpu to access on the same address again.
2829 * - false: let the real page fault path to fix it.
2831 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2834 struct kvm_shadow_walk_iterator iterator;
2838 if (!page_fault_can_be_fast(vcpu, error_code))
2841 walk_shadow_page_lockless_begin(vcpu);
2842 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2843 if (!is_shadow_present_pte(spte) || iterator.level < level)
2847 * If the mapping has been changed, let the vcpu fault on the
2848 * same address again.
2850 if (!is_rmap_spte(spte)) {
2855 if (!is_last_spte(spte, level))
2859 * Check if it is a spurious fault caused by TLB lazily flushed.
2861 * Need not check the access of upper level table entries since
2862 * they are always ACC_ALL.
2864 if (is_writable_pte(spte)) {
2870 * Currently, to simplify the code, only the spte write-protected
2871 * by dirty-log can be fast fixed.
2873 if (!spte_is_locklessly_modifiable(spte))
2877 * Currently, fast page fault only works for direct mapping since
2878 * the gfn is not stable for indirect shadow page.
2879 * See Documentation/virtual/kvm/locking.txt to get more detail.
2881 ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2883 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2885 walk_shadow_page_lockless_end(vcpu);
2890 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2891 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2892 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
2894 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2895 gfn_t gfn, bool prefault)
2901 unsigned long mmu_seq;
2902 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2904 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2905 if (likely(!force_pt_level)) {
2906 level = mapping_level(vcpu, gfn);
2908 * This path builds a PAE pagetable - so we can map
2909 * 2mb pages at maximum. Therefore check if the level
2910 * is larger than that.
2912 if (level > PT_DIRECTORY_LEVEL)
2913 level = PT_DIRECTORY_LEVEL;
2915 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2917 level = PT_PAGE_TABLE_LEVEL;
2919 if (fast_page_fault(vcpu, v, level, error_code))
2922 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2925 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2928 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2931 spin_lock(&vcpu->kvm->mmu_lock);
2932 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2934 make_mmu_pages_available(vcpu);
2935 if (likely(!force_pt_level))
2936 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2937 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2939 spin_unlock(&vcpu->kvm->mmu_lock);
2945 spin_unlock(&vcpu->kvm->mmu_lock);
2946 kvm_release_pfn_clean(pfn);
2951 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2954 struct kvm_mmu_page *sp;
2955 LIST_HEAD(invalid_list);
2957 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2960 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2961 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2962 vcpu->arch.mmu.direct_map)) {
2963 hpa_t root = vcpu->arch.mmu.root_hpa;
2965 spin_lock(&vcpu->kvm->mmu_lock);
2966 sp = page_header(root);
2968 if (!sp->root_count && sp->role.invalid) {
2969 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2970 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2972 spin_unlock(&vcpu->kvm->mmu_lock);
2973 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2977 spin_lock(&vcpu->kvm->mmu_lock);
2978 for (i = 0; i < 4; ++i) {
2979 hpa_t root = vcpu->arch.mmu.pae_root[i];
2982 root &= PT64_BASE_ADDR_MASK;
2983 sp = page_header(root);
2985 if (!sp->root_count && sp->role.invalid)
2986 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2989 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2991 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2992 spin_unlock(&vcpu->kvm->mmu_lock);
2993 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2996 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3000 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3001 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3008 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3010 struct kvm_mmu_page *sp;
3013 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3014 spin_lock(&vcpu->kvm->mmu_lock);
3015 make_mmu_pages_available(vcpu);
3016 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
3019 spin_unlock(&vcpu->kvm->mmu_lock);
3020 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3021 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3022 for (i = 0; i < 4; ++i) {
3023 hpa_t root = vcpu->arch.mmu.pae_root[i];
3025 ASSERT(!VALID_PAGE(root));
3026 spin_lock(&vcpu->kvm->mmu_lock);
3027 make_mmu_pages_available(vcpu);
3028 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3030 PT32_ROOT_LEVEL, 1, ACC_ALL,
3032 root = __pa(sp->spt);
3034 spin_unlock(&vcpu->kvm->mmu_lock);
3035 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3037 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3044 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3046 struct kvm_mmu_page *sp;
3051 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3053 if (mmu_check_root(vcpu, root_gfn))
3057 * Do we shadow a long mode page table? If so we need to
3058 * write-protect the guests page table root.
3060 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3061 hpa_t root = vcpu->arch.mmu.root_hpa;
3063 ASSERT(!VALID_PAGE(root));
3065 spin_lock(&vcpu->kvm->mmu_lock);
3066 make_mmu_pages_available(vcpu);
3067 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3069 root = __pa(sp->spt);
3071 spin_unlock(&vcpu->kvm->mmu_lock);
3072 vcpu->arch.mmu.root_hpa = root;
3077 * We shadow a 32 bit page table. This may be a legacy 2-level
3078 * or a PAE 3-level page table. In either case we need to be aware that
3079 * the shadow page table may be a PAE or a long mode page table.
3081 pm_mask = PT_PRESENT_MASK;
3082 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3083 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3085 for (i = 0; i < 4; ++i) {
3086 hpa_t root = vcpu->arch.mmu.pae_root[i];
3088 ASSERT(!VALID_PAGE(root));
3089 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3090 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3091 if (!is_present_gpte(pdptr)) {
3092 vcpu->arch.mmu.pae_root[i] = 0;
3095 root_gfn = pdptr >> PAGE_SHIFT;
3096 if (mmu_check_root(vcpu, root_gfn))
3099 spin_lock(&vcpu->kvm->mmu_lock);
3100 make_mmu_pages_available(vcpu);
3101 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3104 root = __pa(sp->spt);
3106 spin_unlock(&vcpu->kvm->mmu_lock);
3108 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3110 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3113 * If we shadow a 32 bit page table with a long mode page
3114 * table we enter this path.
3116 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3117 if (vcpu->arch.mmu.lm_root == NULL) {
3119 * The additional page necessary for this is only
3120 * allocated on demand.
3125 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3126 if (lm_root == NULL)
3129 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3131 vcpu->arch.mmu.lm_root = lm_root;
3134 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3140 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3142 if (vcpu->arch.mmu.direct_map)
3143 return mmu_alloc_direct_roots(vcpu);
3145 return mmu_alloc_shadow_roots(vcpu);
3148 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3151 struct kvm_mmu_page *sp;
3153 if (vcpu->arch.mmu.direct_map)
3156 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3159 vcpu_clear_mmio_info(vcpu, ~0ul);
3160 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3161 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3162 hpa_t root = vcpu->arch.mmu.root_hpa;
3163 sp = page_header(root);
3164 mmu_sync_children(vcpu, sp);
3165 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3168 for (i = 0; i < 4; ++i) {
3169 hpa_t root = vcpu->arch.mmu.pae_root[i];
3171 if (root && VALID_PAGE(root)) {
3172 root &= PT64_BASE_ADDR_MASK;
3173 sp = page_header(root);
3174 mmu_sync_children(vcpu, sp);
3177 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3180 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3182 spin_lock(&vcpu->kvm->mmu_lock);
3183 mmu_sync_roots(vcpu);
3184 spin_unlock(&vcpu->kvm->mmu_lock);
3187 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3188 u32 access, struct x86_exception *exception)
3191 exception->error_code = 0;
3195 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3197 struct x86_exception *exception)
3200 exception->error_code = 0;
3201 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3204 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3207 return vcpu_match_mmio_gpa(vcpu, addr);
3209 return vcpu_match_mmio_gva(vcpu, addr);
3214 * On direct hosts, the last spte is only allows two states
3215 * for mmio page fault:
3216 * - It is the mmio spte
3217 * - It is zapped or it is being zapped.
3219 * This function completely checks the spte when the last spte
3220 * is not the mmio spte.
3222 static bool check_direct_spte_mmio_pf(u64 spte)
3224 return __check_direct_spte_mmio_pf(spte);
3227 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3229 struct kvm_shadow_walk_iterator iterator;
3232 walk_shadow_page_lockless_begin(vcpu);
3233 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3234 if (!is_shadow_present_pte(spte))
3236 walk_shadow_page_lockless_end(vcpu);
3241 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3245 if (quickly_check_mmio_pf(vcpu, addr, direct))
3246 return RET_MMIO_PF_EMULATE;
3248 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3250 if (is_mmio_spte(spte)) {
3251 gfn_t gfn = get_mmio_spte_gfn(spte);
3252 unsigned access = get_mmio_spte_access(spte);
3254 if (!check_mmio_spte(vcpu->kvm, spte))
3255 return RET_MMIO_PF_INVALID;
3260 trace_handle_mmio_page_fault(addr, gfn, access);
3261 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3262 return RET_MMIO_PF_EMULATE;
3266 * It's ok if the gva is remapped by other cpus on shadow guest,
3267 * it's a BUG if the gfn is not a mmio page.
3269 if (direct && !check_direct_spte_mmio_pf(spte))
3270 return RET_MMIO_PF_BUG;
3273 * If the page table is zapped by other cpus, let CPU fault again on
3276 return RET_MMIO_PF_RETRY;
3278 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3280 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3281 u32 error_code, bool direct)
3285 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3286 WARN_ON(ret == RET_MMIO_PF_BUG);
3290 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3291 u32 error_code, bool prefault)
3296 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3298 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3299 r = handle_mmio_page_fault(vcpu, gva, error_code, true);
3301 if (likely(r != RET_MMIO_PF_INVALID))
3305 r = mmu_topup_memory_caches(vcpu);
3310 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3312 gfn = gva >> PAGE_SHIFT;
3314 return nonpaging_map(vcpu, gva & PAGE_MASK,
3315 error_code, gfn, prefault);
3318 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3320 struct kvm_arch_async_pf arch;
3322 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3324 arch.direct_map = vcpu->arch.mmu.direct_map;
3325 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3327 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3330 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3332 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3333 kvm_event_needs_reinjection(vcpu)))
3336 return kvm_x86_ops->interrupt_allowed(vcpu);
3339 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3340 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3344 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3347 return false; /* *pfn has correct page already */
3349 if (!prefault && can_do_async_pf(vcpu)) {
3350 trace_kvm_try_async_get_page(gva, gfn);
3351 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3352 trace_kvm_async_pf_doublefault(gva, gfn);
3353 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3355 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3359 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3364 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3371 gfn_t gfn = gpa >> PAGE_SHIFT;
3372 unsigned long mmu_seq;
3373 int write = error_code & PFERR_WRITE_MASK;
3377 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3379 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3380 r = handle_mmio_page_fault(vcpu, gpa, error_code, true);
3382 if (likely(r != RET_MMIO_PF_INVALID))
3386 r = mmu_topup_memory_caches(vcpu);
3390 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3391 if (likely(!force_pt_level)) {
3392 level = mapping_level(vcpu, gfn);
3393 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3395 level = PT_PAGE_TABLE_LEVEL;
3397 if (fast_page_fault(vcpu, gpa, level, error_code))
3400 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3403 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3406 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3409 spin_lock(&vcpu->kvm->mmu_lock);
3410 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3412 make_mmu_pages_available(vcpu);
3413 if (likely(!force_pt_level))
3414 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3415 r = __direct_map(vcpu, gpa, write, map_writable,
3416 level, gfn, pfn, prefault);
3417 spin_unlock(&vcpu->kvm->mmu_lock);
3422 spin_unlock(&vcpu->kvm->mmu_lock);
3423 kvm_release_pfn_clean(pfn);
3427 static void nonpaging_free(struct kvm_vcpu *vcpu)
3429 mmu_free_roots(vcpu);
3432 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3433 struct kvm_mmu *context)
3435 context->new_cr3 = nonpaging_new_cr3;
3436 context->page_fault = nonpaging_page_fault;
3437 context->gva_to_gpa = nonpaging_gva_to_gpa;
3438 context->free = nonpaging_free;
3439 context->sync_page = nonpaging_sync_page;
3440 context->invlpg = nonpaging_invlpg;
3441 context->update_pte = nonpaging_update_pte;
3442 context->root_level = 0;
3443 context->shadow_root_level = PT32E_ROOT_LEVEL;
3444 context->root_hpa = INVALID_PAGE;
3445 context->direct_map = true;
3446 context->nx = false;
3450 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3452 ++vcpu->stat.tlb_flush;
3453 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3456 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3458 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3459 mmu_free_roots(vcpu);
3462 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3464 return kvm_read_cr3(vcpu);
3467 static void inject_page_fault(struct kvm_vcpu *vcpu,
3468 struct x86_exception *fault)
3470 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3473 static void paging_free(struct kvm_vcpu *vcpu)
3475 nonpaging_free(vcpu);
3478 static inline void protect_clean_gpte(unsigned *access, unsigned gpte)
3482 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
3484 mask = (unsigned)~ACC_WRITE_MASK;
3485 /* Allow write access to dirty gptes */
3486 mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK;
3490 static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
3491 unsigned access, int *nr_present)
3493 if (unlikely(is_mmio_spte(*sptep))) {
3494 if (gfn != get_mmio_spte_gfn(*sptep)) {
3495 mmu_spte_clear_no_track(sptep);
3500 mark_mmio_spte(kvm, sptep, gfn, access);
3507 static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte)
3511 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
3512 access &= ~(gpte >> PT64_NX_SHIFT);
3517 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3522 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3523 return mmu->last_pte_bitmap & (1 << index);
3527 #include "paging_tmpl.h"
3531 #include "paging_tmpl.h"
3534 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3535 struct kvm_mmu *context)
3537 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3538 u64 exb_bit_rsvd = 0;
3541 exb_bit_rsvd = rsvd_bits(63, 63);
3542 switch (context->root_level) {
3543 case PT32_ROOT_LEVEL:
3544 /* no rsvd bits for 2 level 4K page table entries */
3545 context->rsvd_bits_mask[0][1] = 0;
3546 context->rsvd_bits_mask[0][0] = 0;
3547 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3549 if (!is_pse(vcpu)) {
3550 context->rsvd_bits_mask[1][1] = 0;
3554 if (is_cpuid_PSE36())
3555 /* 36bits PSE 4MB page */
3556 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3558 /* 32 bits PSE 4MB page */
3559 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3561 case PT32E_ROOT_LEVEL:
3562 context->rsvd_bits_mask[0][2] =
3563 rsvd_bits(maxphyaddr, 63) |
3564 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3565 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3566 rsvd_bits(maxphyaddr, 62); /* PDE */
3567 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3568 rsvd_bits(maxphyaddr, 62); /* PTE */
3569 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3570 rsvd_bits(maxphyaddr, 62) |
3571 rsvd_bits(13, 20); /* large page */
3572 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3574 case PT64_ROOT_LEVEL:
3575 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3576 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3577 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3578 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3579 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3580 rsvd_bits(maxphyaddr, 51);
3581 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3582 rsvd_bits(maxphyaddr, 51);
3583 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3584 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3585 rsvd_bits(maxphyaddr, 51) |
3587 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3588 rsvd_bits(maxphyaddr, 51) |
3589 rsvd_bits(13, 20); /* large page */
3590 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3595 static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3597 unsigned bit, byte, pfec;
3599 bool fault, x, w, u, wf, uf, ff, smep;
3601 smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3602 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3605 wf = pfec & PFERR_WRITE_MASK;
3606 uf = pfec & PFERR_USER_MASK;
3607 ff = pfec & PFERR_FETCH_MASK;
3608 for (bit = 0; bit < 8; ++bit) {
3609 x = bit & ACC_EXEC_MASK;
3610 w = bit & ACC_WRITE_MASK;
3611 u = bit & ACC_USER_MASK;
3613 /* Not really needed: !nx will cause pte.nx to fault */
3615 /* Allow supervisor writes if !cr0.wp */
3616 w |= !is_write_protection(vcpu) && !uf;
3617 /* Disallow supervisor fetches of user code if cr4.smep */
3618 x &= !(smep && u && !uf);
3620 fault = (ff && !x) || (uf && !u) || (wf && !w);
3621 map |= fault << bit;
3623 mmu->permissions[byte] = map;
3627 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3630 unsigned level, root_level = mmu->root_level;
3631 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3633 if (root_level == PT32E_ROOT_LEVEL)
3635 /* PT_PAGE_TABLE_LEVEL always terminates */
3636 map = 1 | (1 << ps_set_index);
3637 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3638 if (level <= PT_PDPE_LEVEL
3639 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3640 map |= 1 << (ps_set_index | (level - 1));
3642 mmu->last_pte_bitmap = map;
3645 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3646 struct kvm_mmu *context,
3649 context->nx = is_nx(vcpu);
3650 context->root_level = level;
3652 reset_rsvds_bits_mask(vcpu, context);
3653 update_permission_bitmask(vcpu, context);
3654 update_last_pte_bitmap(vcpu, context);
3656 ASSERT(is_pae(vcpu));
3657 context->new_cr3 = paging_new_cr3;
3658 context->page_fault = paging64_page_fault;
3659 context->gva_to_gpa = paging64_gva_to_gpa;
3660 context->sync_page = paging64_sync_page;
3661 context->invlpg = paging64_invlpg;
3662 context->update_pte = paging64_update_pte;
3663 context->free = paging_free;
3664 context->shadow_root_level = level;
3665 context->root_hpa = INVALID_PAGE;
3666 context->direct_map = false;
3670 static int paging64_init_context(struct kvm_vcpu *vcpu,
3671 struct kvm_mmu *context)
3673 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3676 static int paging32_init_context(struct kvm_vcpu *vcpu,
3677 struct kvm_mmu *context)
3679 context->nx = false;
3680 context->root_level = PT32_ROOT_LEVEL;
3682 reset_rsvds_bits_mask(vcpu, context);
3683 update_permission_bitmask(vcpu, context);
3684 update_last_pte_bitmap(vcpu, context);
3686 context->new_cr3 = paging_new_cr3;
3687 context->page_fault = paging32_page_fault;
3688 context->gva_to_gpa = paging32_gva_to_gpa;
3689 context->free = paging_free;
3690 context->sync_page = paging32_sync_page;
3691 context->invlpg = paging32_invlpg;
3692 context->update_pte = paging32_update_pte;
3693 context->shadow_root_level = PT32E_ROOT_LEVEL;
3694 context->root_hpa = INVALID_PAGE;
3695 context->direct_map = false;
3699 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3700 struct kvm_mmu *context)
3702 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3705 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3707 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3709 context->base_role.word = 0;
3710 context->new_cr3 = nonpaging_new_cr3;
3711 context->page_fault = tdp_page_fault;
3712 context->free = nonpaging_free;
3713 context->sync_page = nonpaging_sync_page;
3714 context->invlpg = nonpaging_invlpg;
3715 context->update_pte = nonpaging_update_pte;
3716 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3717 context->root_hpa = INVALID_PAGE;
3718 context->direct_map = true;
3719 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3720 context->get_cr3 = get_cr3;
3721 context->get_pdptr = kvm_pdptr_read;
3722 context->inject_page_fault = kvm_inject_page_fault;
3724 if (!is_paging(vcpu)) {
3725 context->nx = false;
3726 context->gva_to_gpa = nonpaging_gva_to_gpa;
3727 context->root_level = 0;
3728 } else if (is_long_mode(vcpu)) {
3729 context->nx = is_nx(vcpu);
3730 context->root_level = PT64_ROOT_LEVEL;
3731 reset_rsvds_bits_mask(vcpu, context);
3732 context->gva_to_gpa = paging64_gva_to_gpa;
3733 } else if (is_pae(vcpu)) {
3734 context->nx = is_nx(vcpu);
3735 context->root_level = PT32E_ROOT_LEVEL;
3736 reset_rsvds_bits_mask(vcpu, context);
3737 context->gva_to_gpa = paging64_gva_to_gpa;
3739 context->nx = false;
3740 context->root_level = PT32_ROOT_LEVEL;
3741 reset_rsvds_bits_mask(vcpu, context);
3742 context->gva_to_gpa = paging32_gva_to_gpa;
3745 update_permission_bitmask(vcpu, context);
3746 update_last_pte_bitmap(vcpu, context);
3751 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3754 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3756 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3758 if (!is_paging(vcpu))
3759 r = nonpaging_init_context(vcpu, context);
3760 else if (is_long_mode(vcpu))
3761 r = paging64_init_context(vcpu, context);
3762 else if (is_pae(vcpu))
3763 r = paging32E_init_context(vcpu, context);
3765 r = paging32_init_context(vcpu, context);
3767 vcpu->arch.mmu.base_role.nxe = is_nx(vcpu);
3768 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3769 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3770 vcpu->arch.mmu.base_role.smep_andnot_wp
3771 = smep && !is_write_protection(vcpu);
3775 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3777 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3779 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3781 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3782 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3783 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3784 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3789 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3791 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3793 g_context->get_cr3 = get_cr3;
3794 g_context->get_pdptr = kvm_pdptr_read;
3795 g_context->inject_page_fault = kvm_inject_page_fault;
3798 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3799 * translation of l2_gpa to l1_gpa addresses is done using the
3800 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3801 * functions between mmu and nested_mmu are swapped.
3803 if (!is_paging(vcpu)) {
3804 g_context->nx = false;
3805 g_context->root_level = 0;
3806 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3807 } else if (is_long_mode(vcpu)) {
3808 g_context->nx = is_nx(vcpu);
3809 g_context->root_level = PT64_ROOT_LEVEL;
3810 reset_rsvds_bits_mask(vcpu, g_context);
3811 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3812 } else if (is_pae(vcpu)) {
3813 g_context->nx = is_nx(vcpu);
3814 g_context->root_level = PT32E_ROOT_LEVEL;
3815 reset_rsvds_bits_mask(vcpu, g_context);
3816 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3818 g_context->nx = false;
3819 g_context->root_level = PT32_ROOT_LEVEL;
3820 reset_rsvds_bits_mask(vcpu, g_context);
3821 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3824 update_permission_bitmask(vcpu, g_context);
3825 update_last_pte_bitmap(vcpu, g_context);
3830 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3832 if (mmu_is_nested(vcpu))
3833 return init_kvm_nested_mmu(vcpu);
3834 else if (tdp_enabled)
3835 return init_kvm_tdp_mmu(vcpu);
3837 return init_kvm_softmmu(vcpu);
3840 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3843 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3844 /* mmu.free() should set root_hpa = INVALID_PAGE */
3845 vcpu->arch.mmu.free(vcpu);
3848 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3850 destroy_kvm_mmu(vcpu);
3851 return init_kvm_mmu(vcpu);
3853 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3855 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3859 r = mmu_topup_memory_caches(vcpu);
3862 r = mmu_alloc_roots(vcpu);
3863 kvm_mmu_sync_roots(vcpu);
3866 /* set_cr3() should ensure TLB has been flushed */
3867 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3871 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3873 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3875 mmu_free_roots(vcpu);
3877 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3879 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3880 struct kvm_mmu_page *sp, u64 *spte,
3883 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3884 ++vcpu->kvm->stat.mmu_pde_zapped;
3888 ++vcpu->kvm->stat.mmu_pte_updated;
3889 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3892 static bool need_remote_flush(u64 old, u64 new)
3894 if (!is_shadow_present_pte(old))
3896 if (!is_shadow_present_pte(new))
3898 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3900 old ^= PT64_NX_MASK;
3901 new ^= PT64_NX_MASK;
3902 return (old & ~new & PT64_PERM_MASK) != 0;
3905 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3906 bool remote_flush, bool local_flush)
3912 kvm_flush_remote_tlbs(vcpu->kvm);
3913 else if (local_flush)
3914 kvm_mmu_flush_tlb(vcpu);
3917 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3918 const u8 *new, int *bytes)
3924 * Assume that the pte write on a page table of the same type
3925 * as the current vcpu paging mode since we update the sptes only
3926 * when they have the same mode.
3928 if (is_pae(vcpu) && *bytes == 4) {
3929 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3932 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8);
3935 new = (const u8 *)&gentry;
3940 gentry = *(const u32 *)new;
3943 gentry = *(const u64 *)new;
3954 * If we're seeing too many writes to a page, it may no longer be a page table,
3955 * or we may be forking, in which case it is better to unmap the page.
3957 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3960 * Skip write-flooding detected for the sp whose level is 1, because
3961 * it can become unsync, then the guest page is not write-protected.
3963 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3966 return ++sp->write_flooding_count >= 3;
3970 * Misaligned accesses are too much trouble to fix up; also, they usually
3971 * indicate a page is not used as a page table.
3973 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3976 unsigned offset, pte_size, misaligned;
3978 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3979 gpa, bytes, sp->role.word);
3981 offset = offset_in_page(gpa);
3982 pte_size = sp->role.cr4_pae ? 8 : 4;
3985 * Sometimes, the OS only writes the last one bytes to update status
3986 * bits, for example, in linux, andb instruction is used in clear_bit().
3988 if (!(offset & (pte_size - 1)) && bytes == 1)
3991 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3992 misaligned |= bytes < 4;
3997 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3999 unsigned page_offset, quadrant;
4003 page_offset = offset_in_page(gpa);
4004 level = sp->role.level;
4006 if (!sp->role.cr4_pae) {
4007 page_offset <<= 1; /* 32->64 */
4009 * A 32-bit pde maps 4MB while the shadow pdes map
4010 * only 2MB. So we need to double the offset again
4011 * and zap two pdes instead of one.
4013 if (level == PT32_ROOT_LEVEL) {
4014 page_offset &= ~7; /* kill rounding error */
4018 quadrant = page_offset >> PAGE_SHIFT;
4019 page_offset &= ~PAGE_MASK;
4020 if (quadrant != sp->role.quadrant)
4024 spte = &sp->spt[page_offset / sizeof(*spte)];
4028 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4029 const u8 *new, int bytes)
4031 gfn_t gfn = gpa >> PAGE_SHIFT;
4032 union kvm_mmu_page_role mask = { .word = 0 };
4033 struct kvm_mmu_page *sp;
4034 LIST_HEAD(invalid_list);
4035 u64 entry, gentry, *spte;
4037 bool remote_flush, local_flush, zap_page;
4040 * If we don't have indirect shadow pages, it means no page is
4041 * write-protected, so we can exit simply.
4043 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4046 zap_page = remote_flush = local_flush = false;
4048 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4050 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4053 * No need to care whether allocation memory is successful
4054 * or not since pte prefetch is skiped if it does not have
4055 * enough objects in the cache.
4057 mmu_topup_memory_caches(vcpu);
4059 spin_lock(&vcpu->kvm->mmu_lock);
4060 ++vcpu->kvm->stat.mmu_pte_write;
4061 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4063 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
4064 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4065 if (detect_write_misaligned(sp, gpa, bytes) ||
4066 detect_write_flooding(sp)) {
4067 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
4069 ++vcpu->kvm->stat.mmu_flooded;
4073 spte = get_written_sptes(sp, gpa, &npte);
4080 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4082 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4083 & mask.word) && rmap_can_add(vcpu))
4084 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4085 if (need_remote_flush(entry, *spte))
4086 remote_flush = true;
4090 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
4091 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4092 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4093 spin_unlock(&vcpu->kvm->mmu_lock);
4096 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4101 if (vcpu->arch.mmu.direct_map)
4104 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4106 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4110 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4112 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4114 LIST_HEAD(invalid_list);
4116 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4119 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4120 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4123 ++vcpu->kvm->stat.mmu_recycled;
4125 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4128 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4130 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4131 return vcpu_match_mmio_gpa(vcpu, addr);
4133 return vcpu_match_mmio_gva(vcpu, addr);
4136 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4137 void *insn, int insn_len)
4139 int r, emulation_type = EMULTYPE_RETRY;
4140 enum emulation_result er;
4142 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4151 if (is_mmio_page_fault(vcpu, cr2))
4154 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4159 case EMULATE_DO_MMIO:
4160 ++vcpu->stat.mmio_exits;
4170 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4172 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4174 vcpu->arch.mmu.invlpg(vcpu, gva);
4175 kvm_mmu_flush_tlb(vcpu);
4176 ++vcpu->stat.invlpg;
4178 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4180 void kvm_enable_tdp(void)
4184 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4186 void kvm_disable_tdp(void)
4188 tdp_enabled = false;
4190 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4192 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4194 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4195 if (vcpu->arch.mmu.lm_root != NULL)
4196 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4199 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4207 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4208 * Therefore we need to allocate shadow page tables in the first
4209 * 4GB of memory, which happens to fit the DMA32 zone.
4211 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4215 vcpu->arch.mmu.pae_root = page_address(page);
4216 for (i = 0; i < 4; ++i)
4217 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4222 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4226 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4227 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4228 vcpu->arch.mmu.translate_gpa = translate_gpa;
4229 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4231 return alloc_mmu_pages(vcpu);
4234 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
4237 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4239 return init_kvm_mmu(vcpu);
4242 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4244 struct kvm_memory_slot *memslot;
4248 memslot = id_to_memslot(kvm->memslots, slot);
4249 last_gfn = memslot->base_gfn + memslot->npages - 1;
4251 spin_lock(&kvm->mmu_lock);
4253 for (i = PT_PAGE_TABLE_LEVEL;
4254 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
4255 unsigned long *rmapp;
4256 unsigned long last_index, index;
4258 rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL];
4259 last_index = gfn_to_index(last_gfn, memslot->base_gfn, i);
4261 for (index = 0; index <= last_index; ++index, ++rmapp) {
4263 __rmap_write_protect(kvm, rmapp, false);
4265 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4266 kvm_flush_remote_tlbs(kvm);
4267 cond_resched_lock(&kvm->mmu_lock);
4272 kvm_flush_remote_tlbs(kvm);
4273 spin_unlock(&kvm->mmu_lock);
4276 #define BATCH_ZAP_PAGES 10
4277 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4279 struct kvm_mmu_page *sp, *node;
4283 list_for_each_entry_safe_reverse(sp, node,
4284 &kvm->arch.active_mmu_pages, link) {
4288 * No obsolete page exists before new created page since
4289 * active_mmu_pages is the FIFO list.
4291 if (!is_obsolete_sp(kvm, sp))
4295 * Since we are reversely walking the list and the invalid
4296 * list will be moved to the head, skip the invalid page
4297 * can help us to avoid the infinity list walking.
4299 if (sp->role.invalid)
4303 * Need not flush tlb since we only zap the sp with invalid
4304 * generation number.
4306 if (batch >= BATCH_ZAP_PAGES &&
4307 cond_resched_lock(&kvm->mmu_lock)) {
4312 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4313 &kvm->arch.zapped_obsolete_pages);
4321 * Should flush tlb before free page tables since lockless-walking
4322 * may use the pages.
4324 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4328 * Fast invalidate all shadow pages and use lock-break technique
4329 * to zap obsolete pages.
4331 * It's required when memslot is being deleted or VM is being
4332 * destroyed, in these cases, we should ensure that KVM MMU does
4333 * not use any resource of the being-deleted slot or all slots
4334 * after calling the function.
4336 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4338 spin_lock(&kvm->mmu_lock);
4339 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4340 kvm->arch.mmu_valid_gen++;
4343 * Notify all vcpus to reload its shadow page table
4344 * and flush TLB. Then all vcpus will switch to new
4345 * shadow page table with the new mmu_valid_gen.
4347 * Note: we should do this under the protection of
4348 * mmu-lock, otherwise, vcpu would purge shadow page
4349 * but miss tlb flush.
4351 kvm_reload_remote_mmus(kvm);
4353 kvm_zap_obsolete_pages(kvm);
4354 spin_unlock(&kvm->mmu_lock);
4357 static void kvm_mmu_zap_mmio_sptes(struct kvm *kvm)
4359 struct kvm_mmu_page *sp, *node;
4360 LIST_HEAD(invalid_list);
4362 spin_lock(&kvm->mmu_lock);
4364 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
4365 if (!sp->mmio_cached)
4367 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
4371 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4372 spin_unlock(&kvm->mmu_lock);
4375 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4377 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4380 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm)
4383 * The very rare case: if the generation-number is round,
4384 * zap all shadow pages.
4386 * The max value is MMIO_MAX_GEN - 1 since it is not called
4387 * when mark memslot invalid.
4389 if (unlikely(kvm_current_mmio_generation(kvm) >= (MMIO_MAX_GEN - 1)))
4390 kvm_mmu_zap_mmio_sptes(kvm);
4393 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
4396 int nr_to_scan = sc->nr_to_scan;
4398 if (nr_to_scan == 0)
4401 raw_spin_lock(&kvm_lock);
4403 list_for_each_entry(kvm, &vm_list, vm_list) {
4405 LIST_HEAD(invalid_list);
4408 * Never scan more than sc->nr_to_scan VM instances.
4409 * Will not hit this condition practically since we do not try
4410 * to shrink more than one VM and it is very unlikely to see
4411 * !n_used_mmu_pages so many times.
4416 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4417 * here. We may skip a VM instance errorneosly, but we do not
4418 * want to shrink a VM that only started to populate its MMU
4421 if (!kvm->arch.n_used_mmu_pages &&
4422 !kvm_has_zapped_obsolete_pages(kvm))
4425 idx = srcu_read_lock(&kvm->srcu);
4426 spin_lock(&kvm->mmu_lock);
4428 if (kvm_has_zapped_obsolete_pages(kvm)) {
4429 kvm_mmu_commit_zap_page(kvm,
4430 &kvm->arch.zapped_obsolete_pages);
4434 prepare_zap_oldest_mmu_page(kvm, &invalid_list);
4435 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4438 spin_unlock(&kvm->mmu_lock);
4439 srcu_read_unlock(&kvm->srcu, idx);
4441 list_move_tail(&kvm->vm_list, &vm_list);
4445 raw_spin_unlock(&kvm_lock);
4448 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4451 static struct shrinker mmu_shrinker = {
4452 .shrink = mmu_shrink,
4453 .seeks = DEFAULT_SEEKS * 10,
4456 static void mmu_destroy_caches(void)
4458 if (pte_list_desc_cache)
4459 kmem_cache_destroy(pte_list_desc_cache);
4460 if (mmu_page_header_cache)
4461 kmem_cache_destroy(mmu_page_header_cache);
4464 int kvm_mmu_module_init(void)
4466 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4467 sizeof(struct pte_list_desc),
4469 if (!pte_list_desc_cache)
4472 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4473 sizeof(struct kvm_mmu_page),
4475 if (!mmu_page_header_cache)
4478 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4481 register_shrinker(&mmu_shrinker);
4486 mmu_destroy_caches();
4491 * Caculate mmu pages needed for kvm.
4493 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4495 unsigned int nr_mmu_pages;
4496 unsigned int nr_pages = 0;
4497 struct kvm_memslots *slots;
4498 struct kvm_memory_slot *memslot;
4500 slots = kvm_memslots(kvm);
4502 kvm_for_each_memslot(memslot, slots)
4503 nr_pages += memslot->npages;
4505 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4506 nr_mmu_pages = max(nr_mmu_pages,
4507 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4509 return nr_mmu_pages;
4512 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4514 struct kvm_shadow_walk_iterator iterator;
4518 walk_shadow_page_lockless_begin(vcpu);
4519 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4520 sptes[iterator.level-1] = spte;
4522 if (!is_shadow_present_pte(spte))
4525 walk_shadow_page_lockless_end(vcpu);
4529 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4531 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4535 destroy_kvm_mmu(vcpu);
4536 free_mmu_pages(vcpu);
4537 mmu_free_memory_caches(vcpu);
4540 void kvm_mmu_module_exit(void)
4542 mmu_destroy_caches();
4543 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4544 unregister_shrinker(&mmu_shrinker);
4545 mmu_audit_disable();