2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled = false;
55 AUDIT_POST_PAGE_FAULT,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc {
157 u64 *sptes[PTE_LIST_EXT];
158 struct pte_list_desc *more;
161 struct kvm_shadow_walk_iterator {
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
196 shadow_mmio_mask = mmio_mask;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
201 * spte bits of bit 3 ~ bit 11 are used as low 9 bits of generation number,
202 * the bits of bits 52 ~ bit 61 are used as high 10 bits of generation
205 #define MMIO_SPTE_GEN_LOW_SHIFT 3
206 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
208 #define MMIO_GEN_SHIFT 19
209 #define MMIO_GEN_LOW_SHIFT 9
210 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 1)
211 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
212 #define MMIO_MAX_GEN ((1 << MMIO_GEN_SHIFT) - 1)
214 static u64 generation_mmio_spte_mask(unsigned int gen)
218 WARN_ON(gen > MMIO_MAX_GEN);
220 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
221 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
225 static unsigned int get_mmio_spte_generation(u64 spte)
229 spte &= ~shadow_mmio_mask;
231 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
232 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
236 static unsigned int kvm_current_mmio_generation(struct kvm *kvm)
239 * Init kvm generation close to MMIO_MAX_GEN to easily test the
240 * code of handling generation number wrap-around.
242 return (kvm_memslots(kvm)->generation +
243 MMIO_MAX_GEN - 150) & MMIO_GEN_MASK;
246 static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn,
249 unsigned int gen = kvm_current_mmio_generation(kvm);
250 u64 mask = generation_mmio_spte_mask(gen);
252 access &= ACC_WRITE_MASK | ACC_USER_MASK;
253 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
255 trace_mark_mmio_spte(sptep, gfn, access, gen);
256 mmu_spte_set(sptep, mask);
259 static bool is_mmio_spte(u64 spte)
261 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
264 static gfn_t get_mmio_spte_gfn(u64 spte)
266 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
267 return (spte & ~mask) >> PAGE_SHIFT;
270 static unsigned get_mmio_spte_access(u64 spte)
272 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
273 return (spte & ~mask) & ~PAGE_MASK;
276 static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
277 pfn_t pfn, unsigned access)
279 if (unlikely(is_noslot_pfn(pfn))) {
280 mark_mmio_spte(kvm, sptep, gfn, access);
287 static bool check_mmio_spte(struct kvm *kvm, u64 spte)
289 unsigned int kvm_gen, spte_gen;
291 kvm_gen = kvm_current_mmio_generation(kvm);
292 spte_gen = get_mmio_spte_generation(spte);
294 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
295 return likely(kvm_gen == spte_gen);
298 static inline u64 rsvd_bits(int s, int e)
300 return ((1ULL << (e - s + 1)) - 1) << s;
303 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
304 u64 dirty_mask, u64 nx_mask, u64 x_mask)
306 shadow_user_mask = user_mask;
307 shadow_accessed_mask = accessed_mask;
308 shadow_dirty_mask = dirty_mask;
309 shadow_nx_mask = nx_mask;
310 shadow_x_mask = x_mask;
312 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
314 static int is_cpuid_PSE36(void)
319 static int is_nx(struct kvm_vcpu *vcpu)
321 return vcpu->arch.efer & EFER_NX;
324 static int is_shadow_present_pte(u64 pte)
326 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
329 static int is_large_pte(u64 pte)
331 return pte & PT_PAGE_SIZE_MASK;
334 static int is_dirty_gpte(unsigned long pte)
336 return pte & PT_DIRTY_MASK;
339 static int is_rmap_spte(u64 pte)
341 return is_shadow_present_pte(pte);
344 static int is_last_spte(u64 pte, int level)
346 if (level == PT_PAGE_TABLE_LEVEL)
348 if (is_large_pte(pte))
353 static pfn_t spte_to_pfn(u64 pte)
355 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
358 static gfn_t pse36_gfn_delta(u32 gpte)
360 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
362 return (gpte & PT32_DIR_PSE36_MASK) << shift;
366 static void __set_spte(u64 *sptep, u64 spte)
371 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
376 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
378 return xchg(sptep, spte);
381 static u64 __get_spte_lockless(u64 *sptep)
383 return ACCESS_ONCE(*sptep);
386 static bool __check_direct_spte_mmio_pf(u64 spte)
388 /* It is valid if the spte is zapped. */
400 static void count_spte_clear(u64 *sptep, u64 spte)
402 struct kvm_mmu_page *sp = page_header(__pa(sptep));
404 if (is_shadow_present_pte(spte))
407 /* Ensure the spte is completely set before we increase the count */
409 sp->clear_spte_count++;
412 static void __set_spte(u64 *sptep, u64 spte)
414 union split_spte *ssptep, sspte;
416 ssptep = (union split_spte *)sptep;
417 sspte = (union split_spte)spte;
419 ssptep->spte_high = sspte.spte_high;
422 * If we map the spte from nonpresent to present, We should store
423 * the high bits firstly, then set present bit, so cpu can not
424 * fetch this spte while we are setting the spte.
428 ssptep->spte_low = sspte.spte_low;
431 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
433 union split_spte *ssptep, sspte;
435 ssptep = (union split_spte *)sptep;
436 sspte = (union split_spte)spte;
438 ssptep->spte_low = sspte.spte_low;
441 * If we map the spte from present to nonpresent, we should clear
442 * present bit firstly to avoid vcpu fetch the old high bits.
446 ssptep->spte_high = sspte.spte_high;
447 count_spte_clear(sptep, spte);
450 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
452 union split_spte *ssptep, sspte, orig;
454 ssptep = (union split_spte *)sptep;
455 sspte = (union split_spte)spte;
457 /* xchg acts as a barrier before the setting of the high bits */
458 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
459 orig.spte_high = ssptep->spte_high;
460 ssptep->spte_high = sspte.spte_high;
461 count_spte_clear(sptep, spte);
467 * The idea using the light way get the spte on x86_32 guest is from
468 * gup_get_pte(arch/x86/mm/gup.c).
469 * The difference is we can not catch the spte tlb flush if we leave
470 * guest mode, so we emulate it by increase clear_spte_count when spte
473 static u64 __get_spte_lockless(u64 *sptep)
475 struct kvm_mmu_page *sp = page_header(__pa(sptep));
476 union split_spte spte, *orig = (union split_spte *)sptep;
480 count = sp->clear_spte_count;
483 spte.spte_low = orig->spte_low;
486 spte.spte_high = orig->spte_high;
489 if (unlikely(spte.spte_low != orig->spte_low ||
490 count != sp->clear_spte_count))
496 static bool __check_direct_spte_mmio_pf(u64 spte)
498 union split_spte sspte = (union split_spte)spte;
499 u32 high_mmio_mask = shadow_mmio_mask >> 32;
501 /* It is valid if the spte is zapped. */
505 /* It is valid if the spte is being zapped. */
506 if (sspte.spte_low == 0ull &&
507 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
514 static bool spte_is_locklessly_modifiable(u64 spte)
516 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
517 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
520 static bool spte_has_volatile_bits(u64 spte)
523 * Always atomicly update spte if it can be updated
524 * out of mmu-lock, it can ensure dirty bit is not lost,
525 * also, it can help us to get a stable is_writable_pte()
526 * to ensure tlb flush is not missed.
528 if (spte_is_locklessly_modifiable(spte))
531 if (!shadow_accessed_mask)
534 if (!is_shadow_present_pte(spte))
537 if ((spte & shadow_accessed_mask) &&
538 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
544 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
546 return (old_spte & bit_mask) && !(new_spte & bit_mask);
549 /* Rules for using mmu_spte_set:
550 * Set the sptep from nonpresent to present.
551 * Note: the sptep being assigned *must* be either not present
552 * or in a state where the hardware will not attempt to update
555 static void mmu_spte_set(u64 *sptep, u64 new_spte)
557 WARN_ON(is_shadow_present_pte(*sptep));
558 __set_spte(sptep, new_spte);
561 /* Rules for using mmu_spte_update:
562 * Update the state bits, it means the mapped pfn is not changged.
564 * Whenever we overwrite a writable spte with a read-only one we
565 * should flush remote TLBs. Otherwise rmap_write_protect
566 * will find a read-only spte, even though the writable spte
567 * might be cached on a CPU's TLB, the return value indicates this
570 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
572 u64 old_spte = *sptep;
575 WARN_ON(!is_rmap_spte(new_spte));
577 if (!is_shadow_present_pte(old_spte)) {
578 mmu_spte_set(sptep, new_spte);
582 if (!spte_has_volatile_bits(old_spte))
583 __update_clear_spte_fast(sptep, new_spte);
585 old_spte = __update_clear_spte_slow(sptep, new_spte);
588 * For the spte updated out of mmu-lock is safe, since
589 * we always atomicly update it, see the comments in
590 * spte_has_volatile_bits().
592 if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
595 if (!shadow_accessed_mask)
598 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
599 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
600 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
601 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
607 * Rules for using mmu_spte_clear_track_bits:
608 * It sets the sptep from present to nonpresent, and track the
609 * state bits, it is used to clear the last level sptep.
611 static int mmu_spte_clear_track_bits(u64 *sptep)
614 u64 old_spte = *sptep;
616 if (!spte_has_volatile_bits(old_spte))
617 __update_clear_spte_fast(sptep, 0ull);
619 old_spte = __update_clear_spte_slow(sptep, 0ull);
621 if (!is_rmap_spte(old_spte))
624 pfn = spte_to_pfn(old_spte);
627 * KVM does not hold the refcount of the page used by
628 * kvm mmu, before reclaiming the page, we should
629 * unmap it from mmu first.
631 WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
633 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
634 kvm_set_pfn_accessed(pfn);
635 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
636 kvm_set_pfn_dirty(pfn);
641 * Rules for using mmu_spte_clear_no_track:
642 * Directly clear spte without caring the state bits of sptep,
643 * it is used to set the upper level spte.
645 static void mmu_spte_clear_no_track(u64 *sptep)
647 __update_clear_spte_fast(sptep, 0ull);
650 static u64 mmu_spte_get_lockless(u64 *sptep)
652 return __get_spte_lockless(sptep);
655 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
658 * Prevent page table teardown by making any free-er wait during
659 * kvm_flush_remote_tlbs() IPI to all active vcpus.
662 vcpu->mode = READING_SHADOW_PAGE_TABLES;
664 * Make sure a following spte read is not reordered ahead of the write
670 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
673 * Make sure the write to vcpu->mode is not reordered in front of
674 * reads to sptes. If it does, kvm_commit_zap_page() can see us
675 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
678 vcpu->mode = OUTSIDE_GUEST_MODE;
682 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
683 struct kmem_cache *base_cache, int min)
687 if (cache->nobjs >= min)
689 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
690 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
693 cache->objects[cache->nobjs++] = obj;
698 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
703 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
704 struct kmem_cache *cache)
707 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
710 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
715 if (cache->nobjs >= min)
717 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
718 page = (void *)__get_free_page(GFP_KERNEL);
721 cache->objects[cache->nobjs++] = page;
726 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
729 free_page((unsigned long)mc->objects[--mc->nobjs]);
732 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
736 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
737 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
740 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
743 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
744 mmu_page_header_cache, 4);
749 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
751 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
752 pte_list_desc_cache);
753 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
754 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
755 mmu_page_header_cache);
758 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
763 p = mc->objects[--mc->nobjs];
767 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
769 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
772 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
774 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
777 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
779 if (!sp->role.direct)
780 return sp->gfns[index];
782 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
785 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
788 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
790 sp->gfns[index] = gfn;
794 * Return the pointer to the large page information for a given gfn,
795 * handling slots that are not large page aligned.
797 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
798 struct kvm_memory_slot *slot,
803 idx = gfn_to_index(gfn, slot->base_gfn, level);
804 return &slot->arch.lpage_info[level - 2][idx];
807 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
809 struct kvm_memory_slot *slot;
810 struct kvm_lpage_info *linfo;
813 slot = gfn_to_memslot(kvm, gfn);
814 for (i = PT_DIRECTORY_LEVEL;
815 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
816 linfo = lpage_info_slot(gfn, slot, i);
817 linfo->write_count += 1;
819 kvm->arch.indirect_shadow_pages++;
822 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
824 struct kvm_memory_slot *slot;
825 struct kvm_lpage_info *linfo;
828 slot = gfn_to_memslot(kvm, gfn);
829 for (i = PT_DIRECTORY_LEVEL;
830 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
831 linfo = lpage_info_slot(gfn, slot, i);
832 linfo->write_count -= 1;
833 WARN_ON(linfo->write_count < 0);
835 kvm->arch.indirect_shadow_pages--;
838 static int has_wrprotected_page(struct kvm *kvm,
842 struct kvm_memory_slot *slot;
843 struct kvm_lpage_info *linfo;
845 slot = gfn_to_memslot(kvm, gfn);
847 linfo = lpage_info_slot(gfn, slot, level);
848 return linfo->write_count;
854 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
856 unsigned long page_size;
859 page_size = kvm_host_page_size(kvm, gfn);
861 for (i = PT_PAGE_TABLE_LEVEL;
862 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
863 if (page_size >= KVM_HPAGE_SIZE(i))
872 static struct kvm_memory_slot *
873 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
876 struct kvm_memory_slot *slot;
878 slot = gfn_to_memslot(vcpu->kvm, gfn);
879 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
880 (no_dirty_log && slot->dirty_bitmap))
886 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
888 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
891 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
893 int host_level, level, max_level;
895 host_level = host_mapping_level(vcpu->kvm, large_gfn);
897 if (host_level == PT_PAGE_TABLE_LEVEL)
900 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
902 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
903 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
910 * Pte mapping structures:
912 * If pte_list bit zero is zero, then pte_list point to the spte.
914 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
915 * pte_list_desc containing more mappings.
917 * Returns the number of pte entries before the spte was added or zero if
918 * the spte was not added.
921 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
922 unsigned long *pte_list)
924 struct pte_list_desc *desc;
928 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
929 *pte_list = (unsigned long)spte;
930 } else if (!(*pte_list & 1)) {
931 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
932 desc = mmu_alloc_pte_list_desc(vcpu);
933 desc->sptes[0] = (u64 *)*pte_list;
934 desc->sptes[1] = spte;
935 *pte_list = (unsigned long)desc | 1;
938 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
939 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
940 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
942 count += PTE_LIST_EXT;
944 if (desc->sptes[PTE_LIST_EXT-1]) {
945 desc->more = mmu_alloc_pte_list_desc(vcpu);
948 for (i = 0; desc->sptes[i]; ++i)
950 desc->sptes[i] = spte;
956 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
957 int i, struct pte_list_desc *prev_desc)
961 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
963 desc->sptes[i] = desc->sptes[j];
964 desc->sptes[j] = NULL;
967 if (!prev_desc && !desc->more)
968 *pte_list = (unsigned long)desc->sptes[0];
971 prev_desc->more = desc->more;
973 *pte_list = (unsigned long)desc->more | 1;
974 mmu_free_pte_list_desc(desc);
977 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
979 struct pte_list_desc *desc;
980 struct pte_list_desc *prev_desc;
984 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
986 } else if (!(*pte_list & 1)) {
987 rmap_printk("pte_list_remove: %p 1->0\n", spte);
988 if ((u64 *)*pte_list != spte) {
989 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
994 rmap_printk("pte_list_remove: %p many->many\n", spte);
995 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
998 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
999 if (desc->sptes[i] == spte) {
1000 pte_list_desc_remove_entry(pte_list,
1008 pr_err("pte_list_remove: %p many->many\n", spte);
1013 typedef void (*pte_list_walk_fn) (u64 *spte);
1014 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
1016 struct pte_list_desc *desc;
1022 if (!(*pte_list & 1))
1023 return fn((u64 *)*pte_list);
1025 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1027 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1033 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
1034 struct kvm_memory_slot *slot)
1038 idx = gfn_to_index(gfn, slot->base_gfn, level);
1039 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1043 * Take gfn and return the reverse mapping to it.
1045 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
1047 struct kvm_memory_slot *slot;
1049 slot = gfn_to_memslot(kvm, gfn);
1050 return __gfn_to_rmap(gfn, level, slot);
1053 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1055 struct kvm_mmu_memory_cache *cache;
1057 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1058 return mmu_memory_cache_free_objects(cache);
1061 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1063 struct kvm_mmu_page *sp;
1064 unsigned long *rmapp;
1066 sp = page_header(__pa(spte));
1067 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1068 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1069 return pte_list_add(vcpu, spte, rmapp);
1072 static void rmap_remove(struct kvm *kvm, u64 *spte)
1074 struct kvm_mmu_page *sp;
1076 unsigned long *rmapp;
1078 sp = page_header(__pa(spte));
1079 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1080 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1081 pte_list_remove(spte, rmapp);
1085 * Used by the following functions to iterate through the sptes linked by a
1086 * rmap. All fields are private and not assumed to be used outside.
1088 struct rmap_iterator {
1089 /* private fields */
1090 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1091 int pos; /* index of the sptep */
1095 * Iteration must be started by this function. This should also be used after
1096 * removing/dropping sptes from the rmap link because in such cases the
1097 * information in the itererator may not be valid.
1099 * Returns sptep if found, NULL otherwise.
1101 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1111 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1113 return iter->desc->sptes[iter->pos];
1117 * Must be used with a valid iterator: e.g. after rmap_get_first().
1119 * Returns sptep if found, NULL otherwise.
1121 static u64 *rmap_get_next(struct rmap_iterator *iter)
1124 if (iter->pos < PTE_LIST_EXT - 1) {
1128 sptep = iter->desc->sptes[iter->pos];
1133 iter->desc = iter->desc->more;
1137 /* desc->sptes[0] cannot be NULL */
1138 return iter->desc->sptes[iter->pos];
1145 static void drop_spte(struct kvm *kvm, u64 *sptep)
1147 if (mmu_spte_clear_track_bits(sptep))
1148 rmap_remove(kvm, sptep);
1152 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1154 if (is_large_pte(*sptep)) {
1155 WARN_ON(page_header(__pa(sptep))->role.level ==
1156 PT_PAGE_TABLE_LEVEL);
1157 drop_spte(kvm, sptep);
1165 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1167 if (__drop_large_spte(vcpu->kvm, sptep))
1168 kvm_flush_remote_tlbs(vcpu->kvm);
1172 * Write-protect on the specified @sptep, @pt_protect indicates whether
1173 * spte writ-protection is caused by protecting shadow page table.
1174 * @flush indicates whether tlb need be flushed.
1176 * Note: write protection is difference between drity logging and spte
1178 * - for dirty logging, the spte can be set to writable at anytime if
1179 * its dirty bitmap is properly set.
1180 * - for spte protection, the spte can be writable only after unsync-ing
1183 * Return true if the spte is dropped.
1186 spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1190 if (!is_writable_pte(spte) &&
1191 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1194 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1196 if (__drop_large_spte(kvm, sptep)) {
1202 spte &= ~SPTE_MMU_WRITEABLE;
1203 spte = spte & ~PT_WRITABLE_MASK;
1205 *flush |= mmu_spte_update(sptep, spte);
1209 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1213 struct rmap_iterator iter;
1216 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1217 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1218 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1219 sptep = rmap_get_first(*rmapp, &iter);
1223 sptep = rmap_get_next(&iter);
1230 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1231 * @kvm: kvm instance
1232 * @slot: slot to protect
1233 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1234 * @mask: indicates which pages we should protect
1236 * Used when we do not need to care about huge page mappings: e.g. during dirty
1237 * logging we do not have any such mappings.
1239 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1240 struct kvm_memory_slot *slot,
1241 gfn_t gfn_offset, unsigned long mask)
1243 unsigned long *rmapp;
1246 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1247 PT_PAGE_TABLE_LEVEL, slot);
1248 __rmap_write_protect(kvm, rmapp, false);
1250 /* clear the first set bit */
1255 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1257 struct kvm_memory_slot *slot;
1258 unsigned long *rmapp;
1260 bool write_protected = false;
1262 slot = gfn_to_memslot(kvm, gfn);
1264 for (i = PT_PAGE_TABLE_LEVEL;
1265 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1266 rmapp = __gfn_to_rmap(gfn, i, slot);
1267 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1270 return write_protected;
1273 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1274 struct kvm_memory_slot *slot, unsigned long data)
1277 struct rmap_iterator iter;
1278 int need_tlb_flush = 0;
1280 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1281 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1282 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1284 drop_spte(kvm, sptep);
1288 return need_tlb_flush;
1291 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1292 struct kvm_memory_slot *slot, unsigned long data)
1295 struct rmap_iterator iter;
1298 pte_t *ptep = (pte_t *)data;
1301 WARN_ON(pte_huge(*ptep));
1302 new_pfn = pte_pfn(*ptep);
1304 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1305 BUG_ON(!is_shadow_present_pte(*sptep));
1306 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1310 if (pte_write(*ptep)) {
1311 drop_spte(kvm, sptep);
1312 sptep = rmap_get_first(*rmapp, &iter);
1314 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1315 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1317 new_spte &= ~PT_WRITABLE_MASK;
1318 new_spte &= ~SPTE_HOST_WRITEABLE;
1319 new_spte &= ~shadow_accessed_mask;
1321 mmu_spte_clear_track_bits(sptep);
1322 mmu_spte_set(sptep, new_spte);
1323 sptep = rmap_get_next(&iter);
1328 kvm_flush_remote_tlbs(kvm);
1333 static int kvm_handle_hva_range(struct kvm *kvm,
1334 unsigned long start,
1337 int (*handler)(struct kvm *kvm,
1338 unsigned long *rmapp,
1339 struct kvm_memory_slot *slot,
1340 unsigned long data))
1344 struct kvm_memslots *slots;
1345 struct kvm_memory_slot *memslot;
1347 slots = kvm_memslots(kvm);
1349 kvm_for_each_memslot(memslot, slots) {
1350 unsigned long hva_start, hva_end;
1351 gfn_t gfn_start, gfn_end;
1353 hva_start = max(start, memslot->userspace_addr);
1354 hva_end = min(end, memslot->userspace_addr +
1355 (memslot->npages << PAGE_SHIFT));
1356 if (hva_start >= hva_end)
1359 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1360 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1362 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1363 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1365 for (j = PT_PAGE_TABLE_LEVEL;
1366 j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1367 unsigned long idx, idx_end;
1368 unsigned long *rmapp;
1371 * {idx(page_j) | page_j intersects with
1372 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1374 idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1375 idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1377 rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1379 for (; idx <= idx_end; ++idx)
1380 ret |= handler(kvm, rmapp++, memslot, data);
1387 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1389 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1390 struct kvm_memory_slot *slot,
1391 unsigned long data))
1393 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1396 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1398 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1401 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1403 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1406 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1408 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1411 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1412 struct kvm_memory_slot *slot, unsigned long data)
1415 struct rmap_iterator uninitialized_var(iter);
1419 * In case of absence of EPT Access and Dirty Bits supports,
1420 * emulate the accessed bit for EPT, by checking if this page has
1421 * an EPT mapping, and clearing it if it does. On the next access,
1422 * a new EPT mapping will be established.
1423 * This has some overhead, but not as much as the cost of swapping
1424 * out actively used pages or breaking up actively used hugepages.
1426 if (!shadow_accessed_mask) {
1427 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1431 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1432 sptep = rmap_get_next(&iter)) {
1433 BUG_ON(!is_shadow_present_pte(*sptep));
1435 if (*sptep & shadow_accessed_mask) {
1437 clear_bit((ffs(shadow_accessed_mask) - 1),
1438 (unsigned long *)sptep);
1442 /* @data has hva passed to kvm_age_hva(). */
1443 trace_kvm_age_page(data, slot, young);
1447 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1448 struct kvm_memory_slot *slot, unsigned long data)
1451 struct rmap_iterator iter;
1455 * If there's no access bit in the secondary pte set by the
1456 * hardware it's up to gup-fast/gup to set the access bit in
1457 * the primary pte or in the page structure.
1459 if (!shadow_accessed_mask)
1462 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1463 sptep = rmap_get_next(&iter)) {
1464 BUG_ON(!is_shadow_present_pte(*sptep));
1466 if (*sptep & shadow_accessed_mask) {
1475 #define RMAP_RECYCLE_THRESHOLD 1000
1477 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1479 unsigned long *rmapp;
1480 struct kvm_mmu_page *sp;
1482 sp = page_header(__pa(spte));
1484 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1486 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1487 kvm_flush_remote_tlbs(vcpu->kvm);
1490 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1492 return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1495 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1497 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1501 static int is_empty_shadow_page(u64 *spt)
1506 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1507 if (is_shadow_present_pte(*pos)) {
1508 printk(KERN_ERR "%s: %p %llx\n", __func__,
1517 * This value is the sum of all of the kvm instances's
1518 * kvm->arch.n_used_mmu_pages values. We need a global,
1519 * aggregate version in order to make the slab shrinker
1522 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1524 kvm->arch.n_used_mmu_pages += nr;
1525 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1528 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1530 ASSERT(is_empty_shadow_page(sp->spt));
1531 hlist_del(&sp->hash_link);
1532 list_del(&sp->link);
1533 free_page((unsigned long)sp->spt);
1534 if (!sp->role.direct)
1535 free_page((unsigned long)sp->gfns);
1536 kmem_cache_free(mmu_page_header_cache, sp);
1539 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1541 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1544 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1545 struct kvm_mmu_page *sp, u64 *parent_pte)
1550 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1553 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1556 pte_list_remove(parent_pte, &sp->parent_ptes);
1559 static void drop_parent_pte(struct kvm_mmu_page *sp,
1562 mmu_page_remove_parent_pte(sp, parent_pte);
1563 mmu_spte_clear_no_track(parent_pte);
1566 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1567 u64 *parent_pte, int direct)
1569 struct kvm_mmu_page *sp;
1571 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1572 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1574 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1575 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1578 * The active_mmu_pages list is the FIFO list, do not move the
1579 * page until it is zapped. kvm_zap_obsolete_pages depends on
1580 * this feature. See the comments in kvm_zap_obsolete_pages().
1582 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1583 sp->parent_ptes = 0;
1584 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1585 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1589 static void mark_unsync(u64 *spte);
1590 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1592 pte_list_walk(&sp->parent_ptes, mark_unsync);
1595 static void mark_unsync(u64 *spte)
1597 struct kvm_mmu_page *sp;
1600 sp = page_header(__pa(spte));
1601 index = spte - sp->spt;
1602 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1604 if (sp->unsync_children++)
1606 kvm_mmu_mark_parents_unsync(sp);
1609 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1610 struct kvm_mmu_page *sp)
1615 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1619 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1620 struct kvm_mmu_page *sp, u64 *spte,
1626 #define KVM_PAGE_ARRAY_NR 16
1628 struct kvm_mmu_pages {
1629 struct mmu_page_and_offset {
1630 struct kvm_mmu_page *sp;
1632 } page[KVM_PAGE_ARRAY_NR];
1636 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1642 for (i=0; i < pvec->nr; i++)
1643 if (pvec->page[i].sp == sp)
1646 pvec->page[pvec->nr].sp = sp;
1647 pvec->page[pvec->nr].idx = idx;
1649 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1652 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1653 struct kvm_mmu_pages *pvec)
1655 int i, ret, nr_unsync_leaf = 0;
1657 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1658 struct kvm_mmu_page *child;
1659 u64 ent = sp->spt[i];
1661 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1662 goto clear_child_bitmap;
1664 child = page_header(ent & PT64_BASE_ADDR_MASK);
1666 if (child->unsync_children) {
1667 if (mmu_pages_add(pvec, child, i))
1670 ret = __mmu_unsync_walk(child, pvec);
1672 goto clear_child_bitmap;
1674 nr_unsync_leaf += ret;
1677 } else if (child->unsync) {
1679 if (mmu_pages_add(pvec, child, i))
1682 goto clear_child_bitmap;
1687 __clear_bit(i, sp->unsync_child_bitmap);
1688 sp->unsync_children--;
1689 WARN_ON((int)sp->unsync_children < 0);
1693 return nr_unsync_leaf;
1696 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1697 struct kvm_mmu_pages *pvec)
1699 if (!sp->unsync_children)
1702 mmu_pages_add(pvec, sp, 0);
1703 return __mmu_unsync_walk(sp, pvec);
1706 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1708 WARN_ON(!sp->unsync);
1709 trace_kvm_mmu_sync_page(sp);
1711 --kvm->stat.mmu_unsync;
1714 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1715 struct list_head *invalid_list);
1716 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1717 struct list_head *invalid_list);
1720 * NOTE: we should pay more attention on the zapped-obsolete page
1721 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1722 * since it has been deleted from active_mmu_pages but still can be found
1725 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1726 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1727 * all the obsolete pages.
1729 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1730 hlist_for_each_entry(_sp, \
1731 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1732 if ((_sp)->gfn != (_gfn)) {} else
1734 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1735 for_each_gfn_sp(_kvm, _sp, _gfn) \
1736 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1738 /* @sp->gfn should be write-protected at the call site */
1739 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1740 struct list_head *invalid_list, bool clear_unsync)
1742 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1743 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1748 kvm_unlink_unsync_page(vcpu->kvm, sp);
1750 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1751 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1755 kvm_mmu_flush_tlb(vcpu);
1759 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1760 struct kvm_mmu_page *sp)
1762 LIST_HEAD(invalid_list);
1765 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1767 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1772 #ifdef CONFIG_KVM_MMU_AUDIT
1773 #include "mmu_audit.c"
1775 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1776 static void mmu_audit_disable(void) { }
1779 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1780 struct list_head *invalid_list)
1782 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1785 /* @gfn should be write-protected at the call site */
1786 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1788 struct kvm_mmu_page *s;
1789 LIST_HEAD(invalid_list);
1792 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1796 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1797 kvm_unlink_unsync_page(vcpu->kvm, s);
1798 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1799 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1800 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1806 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1808 kvm_mmu_flush_tlb(vcpu);
1811 struct mmu_page_path {
1812 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1813 unsigned int idx[PT64_ROOT_LEVEL-1];
1816 #define for_each_sp(pvec, sp, parents, i) \
1817 for (i = mmu_pages_next(&pvec, &parents, -1), \
1818 sp = pvec.page[i].sp; \
1819 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1820 i = mmu_pages_next(&pvec, &parents, i))
1822 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1823 struct mmu_page_path *parents,
1828 for (n = i+1; n < pvec->nr; n++) {
1829 struct kvm_mmu_page *sp = pvec->page[n].sp;
1831 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1832 parents->idx[0] = pvec->page[n].idx;
1836 parents->parent[sp->role.level-2] = sp;
1837 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1843 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1845 struct kvm_mmu_page *sp;
1846 unsigned int level = 0;
1849 unsigned int idx = parents->idx[level];
1851 sp = parents->parent[level];
1855 --sp->unsync_children;
1856 WARN_ON((int)sp->unsync_children < 0);
1857 __clear_bit(idx, sp->unsync_child_bitmap);
1859 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1862 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1863 struct mmu_page_path *parents,
1864 struct kvm_mmu_pages *pvec)
1866 parents->parent[parent->role.level-1] = NULL;
1870 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1871 struct kvm_mmu_page *parent)
1874 struct kvm_mmu_page *sp;
1875 struct mmu_page_path parents;
1876 struct kvm_mmu_pages pages;
1877 LIST_HEAD(invalid_list);
1879 kvm_mmu_pages_init(parent, &parents, &pages);
1880 while (mmu_unsync_walk(parent, &pages)) {
1881 bool protected = false;
1883 for_each_sp(pages, sp, parents, i)
1884 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1887 kvm_flush_remote_tlbs(vcpu->kvm);
1889 for_each_sp(pages, sp, parents, i) {
1890 kvm_sync_page(vcpu, sp, &invalid_list);
1891 mmu_pages_clear_parents(&parents);
1893 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1894 cond_resched_lock(&vcpu->kvm->mmu_lock);
1895 kvm_mmu_pages_init(parent, &parents, &pages);
1899 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1903 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1907 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1909 sp->write_flooding_count = 0;
1912 static void clear_sp_write_flooding_count(u64 *spte)
1914 struct kvm_mmu_page *sp = page_header(__pa(spte));
1916 __clear_sp_write_flooding_count(sp);
1919 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1921 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1924 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1932 union kvm_mmu_page_role role;
1934 struct kvm_mmu_page *sp;
1935 bool need_sync = false;
1937 role = vcpu->arch.mmu.base_role;
1939 role.direct = direct;
1942 role.access = access;
1943 if (!vcpu->arch.mmu.direct_map
1944 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1945 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1946 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1947 role.quadrant = quadrant;
1949 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
1950 if (is_obsolete_sp(vcpu->kvm, sp))
1953 if (!need_sync && sp->unsync)
1956 if (sp->role.word != role.word)
1959 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1962 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1963 if (sp->unsync_children) {
1964 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1965 kvm_mmu_mark_parents_unsync(sp);
1966 } else if (sp->unsync)
1967 kvm_mmu_mark_parents_unsync(sp);
1969 __clear_sp_write_flooding_count(sp);
1970 trace_kvm_mmu_get_page(sp, false);
1973 ++vcpu->kvm->stat.mmu_cache_miss;
1974 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1979 hlist_add_head(&sp->hash_link,
1980 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1982 if (rmap_write_protect(vcpu->kvm, gfn))
1983 kvm_flush_remote_tlbs(vcpu->kvm);
1984 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1985 kvm_sync_pages(vcpu, gfn);
1987 account_shadowed(vcpu->kvm, gfn);
1989 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1990 init_shadow_page_table(sp);
1991 trace_kvm_mmu_get_page(sp, true);
1995 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1996 struct kvm_vcpu *vcpu, u64 addr)
1998 iterator->addr = addr;
1999 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2000 iterator->level = vcpu->arch.mmu.shadow_root_level;
2002 if (iterator->level == PT64_ROOT_LEVEL &&
2003 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2004 !vcpu->arch.mmu.direct_map)
2007 if (iterator->level == PT32E_ROOT_LEVEL) {
2008 iterator->shadow_addr
2009 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2010 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2012 if (!iterator->shadow_addr)
2013 iterator->level = 0;
2017 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2019 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2022 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2023 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2027 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2030 if (is_last_spte(spte, iterator->level)) {
2031 iterator->level = 0;
2035 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2039 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2041 return __shadow_walk_next(iterator, *iterator->sptep);
2044 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
2048 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2049 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
2051 mmu_spte_set(sptep, spte);
2054 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2055 unsigned direct_access)
2057 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2058 struct kvm_mmu_page *child;
2061 * For the direct sp, if the guest pte's dirty bit
2062 * changed form clean to dirty, it will corrupt the
2063 * sp's access: allow writable in the read-only sp,
2064 * so we should update the spte at this point to get
2065 * a new sp with the correct access.
2067 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2068 if (child->role.access == direct_access)
2071 drop_parent_pte(child, sptep);
2072 kvm_flush_remote_tlbs(vcpu->kvm);
2076 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2080 struct kvm_mmu_page *child;
2083 if (is_shadow_present_pte(pte)) {
2084 if (is_last_spte(pte, sp->role.level)) {
2085 drop_spte(kvm, spte);
2086 if (is_large_pte(pte))
2089 child = page_header(pte & PT64_BASE_ADDR_MASK);
2090 drop_parent_pte(child, spte);
2095 if (is_mmio_spte(pte))
2096 mmu_spte_clear_no_track(spte);
2101 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2102 struct kvm_mmu_page *sp)
2106 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2107 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2110 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2112 mmu_page_remove_parent_pte(sp, parent_pte);
2115 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2118 struct rmap_iterator iter;
2120 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2121 drop_parent_pte(sp, sptep);
2124 static int mmu_zap_unsync_children(struct kvm *kvm,
2125 struct kvm_mmu_page *parent,
2126 struct list_head *invalid_list)
2129 struct mmu_page_path parents;
2130 struct kvm_mmu_pages pages;
2132 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2135 kvm_mmu_pages_init(parent, &parents, &pages);
2136 while (mmu_unsync_walk(parent, &pages)) {
2137 struct kvm_mmu_page *sp;
2139 for_each_sp(pages, sp, parents, i) {
2140 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2141 mmu_pages_clear_parents(&parents);
2144 kvm_mmu_pages_init(parent, &parents, &pages);
2150 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2151 struct list_head *invalid_list)
2155 trace_kvm_mmu_prepare_zap_page(sp);
2156 ++kvm->stat.mmu_shadow_zapped;
2157 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2158 kvm_mmu_page_unlink_children(kvm, sp);
2159 kvm_mmu_unlink_parents(kvm, sp);
2161 if (!sp->role.invalid && !sp->role.direct)
2162 unaccount_shadowed(kvm, sp->gfn);
2165 kvm_unlink_unsync_page(kvm, sp);
2166 if (!sp->root_count) {
2169 list_move(&sp->link, invalid_list);
2170 kvm_mod_used_mmu_pages(kvm, -1);
2172 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2175 * The obsolete pages can not be used on any vcpus.
2176 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2178 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2179 kvm_reload_remote_mmus(kvm);
2182 sp->role.invalid = 1;
2186 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2187 struct list_head *invalid_list)
2189 struct kvm_mmu_page *sp, *nsp;
2191 if (list_empty(invalid_list))
2195 * wmb: make sure everyone sees our modifications to the page tables
2196 * rmb: make sure we see changes to vcpu->mode
2201 * Wait for all vcpus to exit guest mode and/or lockless shadow
2204 kvm_flush_remote_tlbs(kvm);
2206 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2207 WARN_ON(!sp->role.invalid || sp->root_count);
2208 kvm_mmu_free_page(sp);
2212 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2213 struct list_head *invalid_list)
2215 struct kvm_mmu_page *sp;
2217 if (list_empty(&kvm->arch.active_mmu_pages))
2220 sp = list_entry(kvm->arch.active_mmu_pages.prev,
2221 struct kvm_mmu_page, link);
2222 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2228 * Changing the number of mmu pages allocated to the vm
2229 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2231 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2233 LIST_HEAD(invalid_list);
2235 spin_lock(&kvm->mmu_lock);
2237 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2238 /* Need to free some mmu pages to achieve the goal. */
2239 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2240 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2243 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2244 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2247 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2249 spin_unlock(&kvm->mmu_lock);
2252 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2254 struct kvm_mmu_page *sp;
2255 LIST_HEAD(invalid_list);
2258 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2260 spin_lock(&kvm->mmu_lock);
2261 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2262 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2265 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2267 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2268 spin_unlock(&kvm->mmu_lock);
2272 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2275 * The function is based on mtrr_type_lookup() in
2276 * arch/x86/kernel/cpu/mtrr/generic.c
2278 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2283 u8 prev_match, curr_match;
2284 int num_var_ranges = KVM_NR_VAR_MTRR;
2286 if (!mtrr_state->enabled)
2289 /* Make end inclusive end, instead of exclusive */
2292 /* Look in fixed ranges. Just return the type as per start */
2293 if (mtrr_state->have_fixed && (start < 0x100000)) {
2296 if (start < 0x80000) {
2298 idx += (start >> 16);
2299 return mtrr_state->fixed_ranges[idx];
2300 } else if (start < 0xC0000) {
2302 idx += ((start - 0x80000) >> 14);
2303 return mtrr_state->fixed_ranges[idx];
2304 } else if (start < 0x1000000) {
2306 idx += ((start - 0xC0000) >> 12);
2307 return mtrr_state->fixed_ranges[idx];
2312 * Look in variable ranges
2313 * Look of multiple ranges matching this address and pick type
2314 * as per MTRR precedence
2316 if (!(mtrr_state->enabled & 2))
2317 return mtrr_state->def_type;
2320 for (i = 0; i < num_var_ranges; ++i) {
2321 unsigned short start_state, end_state;
2323 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2326 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2327 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2328 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2329 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2331 start_state = ((start & mask) == (base & mask));
2332 end_state = ((end & mask) == (base & mask));
2333 if (start_state != end_state)
2336 if ((start & mask) != (base & mask))
2339 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2340 if (prev_match == 0xFF) {
2341 prev_match = curr_match;
2345 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2346 curr_match == MTRR_TYPE_UNCACHABLE)
2347 return MTRR_TYPE_UNCACHABLE;
2349 if ((prev_match == MTRR_TYPE_WRBACK &&
2350 curr_match == MTRR_TYPE_WRTHROUGH) ||
2351 (prev_match == MTRR_TYPE_WRTHROUGH &&
2352 curr_match == MTRR_TYPE_WRBACK)) {
2353 prev_match = MTRR_TYPE_WRTHROUGH;
2354 curr_match = MTRR_TYPE_WRTHROUGH;
2357 if (prev_match != curr_match)
2358 return MTRR_TYPE_UNCACHABLE;
2361 if (prev_match != 0xFF)
2364 return mtrr_state->def_type;
2367 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2371 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2372 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2373 if (mtrr == 0xfe || mtrr == 0xff)
2374 mtrr = MTRR_TYPE_WRBACK;
2377 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2379 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2381 trace_kvm_mmu_unsync_page(sp);
2382 ++vcpu->kvm->stat.mmu_unsync;
2385 kvm_mmu_mark_parents_unsync(sp);
2388 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2390 struct kvm_mmu_page *s;
2392 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2395 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2396 __kvm_unsync_page(vcpu, s);
2400 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2403 struct kvm_mmu_page *s;
2404 bool need_unsync = false;
2406 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2410 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2417 kvm_unsync_pages(vcpu, gfn);
2421 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2422 unsigned pte_access, int level,
2423 gfn_t gfn, pfn_t pfn, bool speculative,
2424 bool can_unsync, bool host_writable)
2429 if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access))
2432 spte = PT_PRESENT_MASK;
2434 spte |= shadow_accessed_mask;
2436 if (pte_access & ACC_EXEC_MASK)
2437 spte |= shadow_x_mask;
2439 spte |= shadow_nx_mask;
2441 if (pte_access & ACC_USER_MASK)
2442 spte |= shadow_user_mask;
2444 if (level > PT_PAGE_TABLE_LEVEL)
2445 spte |= PT_PAGE_SIZE_MASK;
2447 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2448 kvm_is_mmio_pfn(pfn));
2451 spte |= SPTE_HOST_WRITEABLE;
2453 pte_access &= ~ACC_WRITE_MASK;
2455 spte |= (u64)pfn << PAGE_SHIFT;
2457 if (pte_access & ACC_WRITE_MASK) {
2460 * Other vcpu creates new sp in the window between
2461 * mapping_level() and acquiring mmu-lock. We can
2462 * allow guest to retry the access, the mapping can
2463 * be fixed if guest refault.
2465 if (level > PT_PAGE_TABLE_LEVEL &&
2466 has_wrprotected_page(vcpu->kvm, gfn, level))
2469 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2472 * Optimization: for pte sync, if spte was writable the hash
2473 * lookup is unnecessary (and expensive). Write protection
2474 * is responsibility of mmu_get_page / kvm_sync_page.
2475 * Same reasoning can be applied to dirty page accounting.
2477 if (!can_unsync && is_writable_pte(*sptep))
2480 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2481 pgprintk("%s: found shadow page for %llx, marking ro\n",
2484 pte_access &= ~ACC_WRITE_MASK;
2485 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2489 if (pte_access & ACC_WRITE_MASK)
2490 mark_page_dirty(vcpu->kvm, gfn);
2493 if (mmu_spte_update(sptep, spte))
2494 kvm_flush_remote_tlbs(vcpu->kvm);
2499 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2500 unsigned pte_access, int write_fault, int *emulate,
2501 int level, gfn_t gfn, pfn_t pfn, bool speculative,
2504 int was_rmapped = 0;
2507 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2508 *sptep, write_fault, gfn);
2510 if (is_rmap_spte(*sptep)) {
2512 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2513 * the parent of the now unreachable PTE.
2515 if (level > PT_PAGE_TABLE_LEVEL &&
2516 !is_large_pte(*sptep)) {
2517 struct kvm_mmu_page *child;
2520 child = page_header(pte & PT64_BASE_ADDR_MASK);
2521 drop_parent_pte(child, sptep);
2522 kvm_flush_remote_tlbs(vcpu->kvm);
2523 } else if (pfn != spte_to_pfn(*sptep)) {
2524 pgprintk("hfn old %llx new %llx\n",
2525 spte_to_pfn(*sptep), pfn);
2526 drop_spte(vcpu->kvm, sptep);
2527 kvm_flush_remote_tlbs(vcpu->kvm);
2532 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2533 true, host_writable)) {
2536 kvm_mmu_flush_tlb(vcpu);
2539 if (unlikely(is_mmio_spte(*sptep) && emulate))
2542 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2543 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2544 is_large_pte(*sptep)? "2MB" : "4kB",
2545 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2547 if (!was_rmapped && is_large_pte(*sptep))
2548 ++vcpu->kvm->stat.lpages;
2550 if (is_shadow_present_pte(*sptep)) {
2552 rmap_count = rmap_add(vcpu, sptep, gfn);
2553 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2554 rmap_recycle(vcpu, sptep, gfn);
2558 kvm_release_pfn_clean(pfn);
2561 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2563 mmu_free_roots(vcpu);
2566 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2570 bit7 = (gpte >> 7) & 1;
2571 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2574 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2577 struct kvm_memory_slot *slot;
2579 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2581 return KVM_PFN_ERR_FAULT;
2583 return gfn_to_pfn_memslot_atomic(slot, gfn);
2586 static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu,
2587 struct kvm_mmu_page *sp, u64 *spte,
2590 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
2593 if (!is_present_gpte(gpte))
2596 if (!(gpte & PT_ACCESSED_MASK))
2602 drop_spte(vcpu->kvm, spte);
2606 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2607 struct kvm_mmu_page *sp,
2608 u64 *start, u64 *end)
2610 struct page *pages[PTE_PREFETCH_NUM];
2611 unsigned access = sp->role.access;
2615 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2616 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2619 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2623 for (i = 0; i < ret; i++, gfn++, start++)
2624 mmu_set_spte(vcpu, start, access, 0, NULL,
2625 sp->role.level, gfn, page_to_pfn(pages[i]),
2631 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2632 struct kvm_mmu_page *sp, u64 *sptep)
2634 u64 *spte, *start = NULL;
2637 WARN_ON(!sp->role.direct);
2639 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2642 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2643 if (is_shadow_present_pte(*spte) || spte == sptep) {
2646 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2654 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2656 struct kvm_mmu_page *sp;
2659 * Since it's no accessed bit on EPT, it's no way to
2660 * distinguish between actually accessed translations
2661 * and prefetched, so disable pte prefetch if EPT is
2664 if (!shadow_accessed_mask)
2667 sp = page_header(__pa(sptep));
2668 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2671 __direct_pte_prefetch(vcpu, sp, sptep);
2674 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2675 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2678 struct kvm_shadow_walk_iterator iterator;
2679 struct kvm_mmu_page *sp;
2683 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2684 if (iterator.level == level) {
2685 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2686 write, &emulate, level, gfn, pfn,
2687 prefault, map_writable);
2688 direct_pte_prefetch(vcpu, iterator.sptep);
2689 ++vcpu->stat.pf_fixed;
2693 if (!is_shadow_present_pte(*iterator.sptep)) {
2694 u64 base_addr = iterator.addr;
2696 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2697 pseudo_gfn = base_addr >> PAGE_SHIFT;
2698 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2700 1, ACC_ALL, iterator.sptep);
2702 link_shadow_page(iterator.sptep, sp);
2708 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2712 info.si_signo = SIGBUS;
2714 info.si_code = BUS_MCEERR_AR;
2715 info.si_addr = (void __user *)address;
2716 info.si_addr_lsb = PAGE_SHIFT;
2718 send_sig_info(SIGBUS, &info, tsk);
2721 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2724 * Do not cache the mmio info caused by writing the readonly gfn
2725 * into the spte otherwise read access on readonly gfn also can
2726 * caused mmio page fault and treat it as mmio access.
2727 * Return 1 to tell kvm to emulate it.
2729 if (pfn == KVM_PFN_ERR_RO_FAULT)
2732 if (pfn == KVM_PFN_ERR_HWPOISON) {
2733 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2740 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2741 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2745 int level = *levelp;
2748 * Check if it's a transparent hugepage. If this would be an
2749 * hugetlbfs page, level wouldn't be set to
2750 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2753 if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2754 level == PT_PAGE_TABLE_LEVEL &&
2755 PageTransCompound(pfn_to_page(pfn)) &&
2756 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2759 * mmu_notifier_retry was successful and we hold the
2760 * mmu_lock here, so the pmd can't become splitting
2761 * from under us, and in turn
2762 * __split_huge_page_refcount() can't run from under
2763 * us and we can safely transfer the refcount from
2764 * PG_tail to PG_head as we switch the pfn to tail to
2767 *levelp = level = PT_DIRECTORY_LEVEL;
2768 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2769 VM_BUG_ON((gfn & mask) != (pfn & mask));
2773 kvm_release_pfn_clean(pfn);
2781 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2782 pfn_t pfn, unsigned access, int *ret_val)
2786 /* The pfn is invalid, report the error! */
2787 if (unlikely(is_error_pfn(pfn))) {
2788 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2792 if (unlikely(is_noslot_pfn(pfn)))
2793 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2800 static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
2803 * #PF can be fast only if the shadow page table is present and it
2804 * is caused by write-protect, that means we just need change the
2805 * W bit of the spte which can be done out of mmu-lock.
2807 if (!(error_code & PFERR_PRESENT_MASK) ||
2808 !(error_code & PFERR_WRITE_MASK))
2815 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2817 struct kvm_mmu_page *sp = page_header(__pa(sptep));
2820 WARN_ON(!sp->role.direct);
2823 * The gfn of direct spte is stable since it is calculated
2826 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2828 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2829 mark_page_dirty(vcpu->kvm, gfn);
2836 * - true: let the vcpu to access on the same address again.
2837 * - false: let the real page fault path to fix it.
2839 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2842 struct kvm_shadow_walk_iterator iterator;
2846 if (!page_fault_can_be_fast(vcpu, error_code))
2849 walk_shadow_page_lockless_begin(vcpu);
2850 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2851 if (!is_shadow_present_pte(spte) || iterator.level < level)
2855 * If the mapping has been changed, let the vcpu fault on the
2856 * same address again.
2858 if (!is_rmap_spte(spte)) {
2863 if (!is_last_spte(spte, level))
2867 * Check if it is a spurious fault caused by TLB lazily flushed.
2869 * Need not check the access of upper level table entries since
2870 * they are always ACC_ALL.
2872 if (is_writable_pte(spte)) {
2878 * Currently, to simplify the code, only the spte write-protected
2879 * by dirty-log can be fast fixed.
2881 if (!spte_is_locklessly_modifiable(spte))
2885 * Currently, fast page fault only works for direct mapping since
2886 * the gfn is not stable for indirect shadow page.
2887 * See Documentation/virtual/kvm/locking.txt to get more detail.
2889 ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2891 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2893 walk_shadow_page_lockless_end(vcpu);
2898 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2899 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2900 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
2902 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2903 gfn_t gfn, bool prefault)
2909 unsigned long mmu_seq;
2910 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2912 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2913 if (likely(!force_pt_level)) {
2914 level = mapping_level(vcpu, gfn);
2916 * This path builds a PAE pagetable - so we can map
2917 * 2mb pages at maximum. Therefore check if the level
2918 * is larger than that.
2920 if (level > PT_DIRECTORY_LEVEL)
2921 level = PT_DIRECTORY_LEVEL;
2923 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2925 level = PT_PAGE_TABLE_LEVEL;
2927 if (fast_page_fault(vcpu, v, level, error_code))
2930 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2933 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2936 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2939 spin_lock(&vcpu->kvm->mmu_lock);
2940 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2942 make_mmu_pages_available(vcpu);
2943 if (likely(!force_pt_level))
2944 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2945 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2947 spin_unlock(&vcpu->kvm->mmu_lock);
2953 spin_unlock(&vcpu->kvm->mmu_lock);
2954 kvm_release_pfn_clean(pfn);
2959 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2962 struct kvm_mmu_page *sp;
2963 LIST_HEAD(invalid_list);
2965 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2968 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2969 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2970 vcpu->arch.mmu.direct_map)) {
2971 hpa_t root = vcpu->arch.mmu.root_hpa;
2973 spin_lock(&vcpu->kvm->mmu_lock);
2974 sp = page_header(root);
2976 if (!sp->root_count && sp->role.invalid) {
2977 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2978 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2980 spin_unlock(&vcpu->kvm->mmu_lock);
2981 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2985 spin_lock(&vcpu->kvm->mmu_lock);
2986 for (i = 0; i < 4; ++i) {
2987 hpa_t root = vcpu->arch.mmu.pae_root[i];
2990 root &= PT64_BASE_ADDR_MASK;
2991 sp = page_header(root);
2993 if (!sp->root_count && sp->role.invalid)
2994 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2997 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2999 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3000 spin_unlock(&vcpu->kvm->mmu_lock);
3001 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3004 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3008 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3009 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3016 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3018 struct kvm_mmu_page *sp;
3021 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3022 spin_lock(&vcpu->kvm->mmu_lock);
3023 make_mmu_pages_available(vcpu);
3024 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
3027 spin_unlock(&vcpu->kvm->mmu_lock);
3028 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3029 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3030 for (i = 0; i < 4; ++i) {
3031 hpa_t root = vcpu->arch.mmu.pae_root[i];
3033 ASSERT(!VALID_PAGE(root));
3034 spin_lock(&vcpu->kvm->mmu_lock);
3035 make_mmu_pages_available(vcpu);
3036 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3038 PT32_ROOT_LEVEL, 1, ACC_ALL,
3040 root = __pa(sp->spt);
3042 spin_unlock(&vcpu->kvm->mmu_lock);
3043 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3045 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3052 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3054 struct kvm_mmu_page *sp;
3059 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3061 if (mmu_check_root(vcpu, root_gfn))
3065 * Do we shadow a long mode page table? If so we need to
3066 * write-protect the guests page table root.
3068 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3069 hpa_t root = vcpu->arch.mmu.root_hpa;
3071 ASSERT(!VALID_PAGE(root));
3073 spin_lock(&vcpu->kvm->mmu_lock);
3074 make_mmu_pages_available(vcpu);
3075 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3077 root = __pa(sp->spt);
3079 spin_unlock(&vcpu->kvm->mmu_lock);
3080 vcpu->arch.mmu.root_hpa = root;
3085 * We shadow a 32 bit page table. This may be a legacy 2-level
3086 * or a PAE 3-level page table. In either case we need to be aware that
3087 * the shadow page table may be a PAE or a long mode page table.
3089 pm_mask = PT_PRESENT_MASK;
3090 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3091 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3093 for (i = 0; i < 4; ++i) {
3094 hpa_t root = vcpu->arch.mmu.pae_root[i];
3096 ASSERT(!VALID_PAGE(root));
3097 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3098 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3099 if (!is_present_gpte(pdptr)) {
3100 vcpu->arch.mmu.pae_root[i] = 0;
3103 root_gfn = pdptr >> PAGE_SHIFT;
3104 if (mmu_check_root(vcpu, root_gfn))
3107 spin_lock(&vcpu->kvm->mmu_lock);
3108 make_mmu_pages_available(vcpu);
3109 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3112 root = __pa(sp->spt);
3114 spin_unlock(&vcpu->kvm->mmu_lock);
3116 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3118 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3121 * If we shadow a 32 bit page table with a long mode page
3122 * table we enter this path.
3124 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3125 if (vcpu->arch.mmu.lm_root == NULL) {
3127 * The additional page necessary for this is only
3128 * allocated on demand.
3133 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3134 if (lm_root == NULL)
3137 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3139 vcpu->arch.mmu.lm_root = lm_root;
3142 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3148 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3150 if (vcpu->arch.mmu.direct_map)
3151 return mmu_alloc_direct_roots(vcpu);
3153 return mmu_alloc_shadow_roots(vcpu);
3156 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3159 struct kvm_mmu_page *sp;
3161 if (vcpu->arch.mmu.direct_map)
3164 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3167 vcpu_clear_mmio_info(vcpu, ~0ul);
3168 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3169 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3170 hpa_t root = vcpu->arch.mmu.root_hpa;
3171 sp = page_header(root);
3172 mmu_sync_children(vcpu, sp);
3173 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3176 for (i = 0; i < 4; ++i) {
3177 hpa_t root = vcpu->arch.mmu.pae_root[i];
3179 if (root && VALID_PAGE(root)) {
3180 root &= PT64_BASE_ADDR_MASK;
3181 sp = page_header(root);
3182 mmu_sync_children(vcpu, sp);
3185 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3188 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3190 spin_lock(&vcpu->kvm->mmu_lock);
3191 mmu_sync_roots(vcpu);
3192 spin_unlock(&vcpu->kvm->mmu_lock);
3195 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3196 u32 access, struct x86_exception *exception)
3199 exception->error_code = 0;
3203 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3205 struct x86_exception *exception)
3208 exception->error_code = 0;
3209 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3212 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3215 return vcpu_match_mmio_gpa(vcpu, addr);
3217 return vcpu_match_mmio_gva(vcpu, addr);
3222 * On direct hosts, the last spte is only allows two states
3223 * for mmio page fault:
3224 * - It is the mmio spte
3225 * - It is zapped or it is being zapped.
3227 * This function completely checks the spte when the last spte
3228 * is not the mmio spte.
3230 static bool check_direct_spte_mmio_pf(u64 spte)
3232 return __check_direct_spte_mmio_pf(spte);
3235 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3237 struct kvm_shadow_walk_iterator iterator;
3240 walk_shadow_page_lockless_begin(vcpu);
3241 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3242 if (!is_shadow_present_pte(spte))
3244 walk_shadow_page_lockless_end(vcpu);
3249 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3253 if (quickly_check_mmio_pf(vcpu, addr, direct))
3254 return RET_MMIO_PF_EMULATE;
3256 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3258 if (is_mmio_spte(spte)) {
3259 gfn_t gfn = get_mmio_spte_gfn(spte);
3260 unsigned access = get_mmio_spte_access(spte);
3262 if (!check_mmio_spte(vcpu->kvm, spte))
3263 return RET_MMIO_PF_INVALID;
3268 trace_handle_mmio_page_fault(addr, gfn, access);
3269 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3270 return RET_MMIO_PF_EMULATE;
3274 * It's ok if the gva is remapped by other cpus on shadow guest,
3275 * it's a BUG if the gfn is not a mmio page.
3277 if (direct && !check_direct_spte_mmio_pf(spte))
3278 return RET_MMIO_PF_BUG;
3281 * If the page table is zapped by other cpus, let CPU fault again on
3284 return RET_MMIO_PF_RETRY;
3286 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3288 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3289 u32 error_code, bool direct)
3293 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3294 WARN_ON(ret == RET_MMIO_PF_BUG);
3298 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3299 u32 error_code, bool prefault)
3304 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3306 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3307 r = handle_mmio_page_fault(vcpu, gva, error_code, true);
3309 if (likely(r != RET_MMIO_PF_INVALID))
3313 r = mmu_topup_memory_caches(vcpu);
3318 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3320 gfn = gva >> PAGE_SHIFT;
3322 return nonpaging_map(vcpu, gva & PAGE_MASK,
3323 error_code, gfn, prefault);
3326 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3328 struct kvm_arch_async_pf arch;
3330 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3332 arch.direct_map = vcpu->arch.mmu.direct_map;
3333 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3335 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3338 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3340 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3341 kvm_event_needs_reinjection(vcpu)))
3344 return kvm_x86_ops->interrupt_allowed(vcpu);
3347 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3348 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3352 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3355 return false; /* *pfn has correct page already */
3357 if (!prefault && can_do_async_pf(vcpu)) {
3358 trace_kvm_try_async_get_page(gva, gfn);
3359 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3360 trace_kvm_async_pf_doublefault(gva, gfn);
3361 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3363 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3367 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3372 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3379 gfn_t gfn = gpa >> PAGE_SHIFT;
3380 unsigned long mmu_seq;
3381 int write = error_code & PFERR_WRITE_MASK;
3385 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3387 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3388 r = handle_mmio_page_fault(vcpu, gpa, error_code, true);
3390 if (likely(r != RET_MMIO_PF_INVALID))
3394 r = mmu_topup_memory_caches(vcpu);
3398 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3399 if (likely(!force_pt_level)) {
3400 level = mapping_level(vcpu, gfn);
3401 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3403 level = PT_PAGE_TABLE_LEVEL;
3405 if (fast_page_fault(vcpu, gpa, level, error_code))
3408 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3411 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3414 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3417 spin_lock(&vcpu->kvm->mmu_lock);
3418 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3420 make_mmu_pages_available(vcpu);
3421 if (likely(!force_pt_level))
3422 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3423 r = __direct_map(vcpu, gpa, write, map_writable,
3424 level, gfn, pfn, prefault);
3425 spin_unlock(&vcpu->kvm->mmu_lock);
3430 spin_unlock(&vcpu->kvm->mmu_lock);
3431 kvm_release_pfn_clean(pfn);
3435 static void nonpaging_free(struct kvm_vcpu *vcpu)
3437 mmu_free_roots(vcpu);
3440 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3441 struct kvm_mmu *context)
3443 context->new_cr3 = nonpaging_new_cr3;
3444 context->page_fault = nonpaging_page_fault;
3445 context->gva_to_gpa = nonpaging_gva_to_gpa;
3446 context->free = nonpaging_free;
3447 context->sync_page = nonpaging_sync_page;
3448 context->invlpg = nonpaging_invlpg;
3449 context->update_pte = nonpaging_update_pte;
3450 context->root_level = 0;
3451 context->shadow_root_level = PT32E_ROOT_LEVEL;
3452 context->root_hpa = INVALID_PAGE;
3453 context->direct_map = true;
3454 context->nx = false;
3458 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3460 ++vcpu->stat.tlb_flush;
3461 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3464 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3466 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3467 mmu_free_roots(vcpu);
3470 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3472 return kvm_read_cr3(vcpu);
3475 static void inject_page_fault(struct kvm_vcpu *vcpu,
3476 struct x86_exception *fault)
3478 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3481 static void paging_free(struct kvm_vcpu *vcpu)
3483 nonpaging_free(vcpu);
3486 static inline void protect_clean_gpte(unsigned *access, unsigned gpte)
3490 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
3492 mask = (unsigned)~ACC_WRITE_MASK;
3493 /* Allow write access to dirty gptes */
3494 mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK;
3498 static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
3499 unsigned access, int *nr_present)
3501 if (unlikely(is_mmio_spte(*sptep))) {
3502 if (gfn != get_mmio_spte_gfn(*sptep)) {
3503 mmu_spte_clear_no_track(sptep);
3508 mark_mmio_spte(kvm, sptep, gfn, access);
3515 static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte)
3519 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
3520 access &= ~(gpte >> PT64_NX_SHIFT);
3525 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3530 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3531 return mmu->last_pte_bitmap & (1 << index);
3535 #include "paging_tmpl.h"
3539 #include "paging_tmpl.h"
3542 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3543 struct kvm_mmu *context)
3545 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3546 u64 exb_bit_rsvd = 0;
3549 exb_bit_rsvd = rsvd_bits(63, 63);
3550 switch (context->root_level) {
3551 case PT32_ROOT_LEVEL:
3552 /* no rsvd bits for 2 level 4K page table entries */
3553 context->rsvd_bits_mask[0][1] = 0;
3554 context->rsvd_bits_mask[0][0] = 0;
3555 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3557 if (!is_pse(vcpu)) {
3558 context->rsvd_bits_mask[1][1] = 0;
3562 if (is_cpuid_PSE36())
3563 /* 36bits PSE 4MB page */
3564 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3566 /* 32 bits PSE 4MB page */
3567 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3569 case PT32E_ROOT_LEVEL:
3570 context->rsvd_bits_mask[0][2] =
3571 rsvd_bits(maxphyaddr, 63) |
3572 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3573 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3574 rsvd_bits(maxphyaddr, 62); /* PDE */
3575 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3576 rsvd_bits(maxphyaddr, 62); /* PTE */
3577 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3578 rsvd_bits(maxphyaddr, 62) |
3579 rsvd_bits(13, 20); /* large page */
3580 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3582 case PT64_ROOT_LEVEL:
3583 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3584 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3585 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3586 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3587 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3588 rsvd_bits(maxphyaddr, 51);
3589 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3590 rsvd_bits(maxphyaddr, 51);
3591 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3592 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3593 rsvd_bits(maxphyaddr, 51) |
3595 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3596 rsvd_bits(maxphyaddr, 51) |
3597 rsvd_bits(13, 20); /* large page */
3598 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3603 static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3605 unsigned bit, byte, pfec;
3607 bool fault, x, w, u, wf, uf, ff, smep;
3609 smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3610 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3613 wf = pfec & PFERR_WRITE_MASK;
3614 uf = pfec & PFERR_USER_MASK;
3615 ff = pfec & PFERR_FETCH_MASK;
3616 for (bit = 0; bit < 8; ++bit) {
3617 x = bit & ACC_EXEC_MASK;
3618 w = bit & ACC_WRITE_MASK;
3619 u = bit & ACC_USER_MASK;
3621 /* Not really needed: !nx will cause pte.nx to fault */
3623 /* Allow supervisor writes if !cr0.wp */
3624 w |= !is_write_protection(vcpu) && !uf;
3625 /* Disallow supervisor fetches of user code if cr4.smep */
3626 x &= !(smep && u && !uf);
3628 fault = (ff && !x) || (uf && !u) || (wf && !w);
3629 map |= fault << bit;
3631 mmu->permissions[byte] = map;
3635 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3638 unsigned level, root_level = mmu->root_level;
3639 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3641 if (root_level == PT32E_ROOT_LEVEL)
3643 /* PT_PAGE_TABLE_LEVEL always terminates */
3644 map = 1 | (1 << ps_set_index);
3645 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3646 if (level <= PT_PDPE_LEVEL
3647 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3648 map |= 1 << (ps_set_index | (level - 1));
3650 mmu->last_pte_bitmap = map;
3653 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3654 struct kvm_mmu *context,
3657 context->nx = is_nx(vcpu);
3658 context->root_level = level;
3660 reset_rsvds_bits_mask(vcpu, context);
3661 update_permission_bitmask(vcpu, context);
3662 update_last_pte_bitmap(vcpu, context);
3664 ASSERT(is_pae(vcpu));
3665 context->new_cr3 = paging_new_cr3;
3666 context->page_fault = paging64_page_fault;
3667 context->gva_to_gpa = paging64_gva_to_gpa;
3668 context->sync_page = paging64_sync_page;
3669 context->invlpg = paging64_invlpg;
3670 context->update_pte = paging64_update_pte;
3671 context->free = paging_free;
3672 context->shadow_root_level = level;
3673 context->root_hpa = INVALID_PAGE;
3674 context->direct_map = false;
3678 static int paging64_init_context(struct kvm_vcpu *vcpu,
3679 struct kvm_mmu *context)
3681 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3684 static int paging32_init_context(struct kvm_vcpu *vcpu,
3685 struct kvm_mmu *context)
3687 context->nx = false;
3688 context->root_level = PT32_ROOT_LEVEL;
3690 reset_rsvds_bits_mask(vcpu, context);
3691 update_permission_bitmask(vcpu, context);
3692 update_last_pte_bitmap(vcpu, context);
3694 context->new_cr3 = paging_new_cr3;
3695 context->page_fault = paging32_page_fault;
3696 context->gva_to_gpa = paging32_gva_to_gpa;
3697 context->free = paging_free;
3698 context->sync_page = paging32_sync_page;
3699 context->invlpg = paging32_invlpg;
3700 context->update_pte = paging32_update_pte;
3701 context->shadow_root_level = PT32E_ROOT_LEVEL;
3702 context->root_hpa = INVALID_PAGE;
3703 context->direct_map = false;
3707 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3708 struct kvm_mmu *context)
3710 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3713 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3715 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3717 context->base_role.word = 0;
3718 context->new_cr3 = nonpaging_new_cr3;
3719 context->page_fault = tdp_page_fault;
3720 context->free = nonpaging_free;
3721 context->sync_page = nonpaging_sync_page;
3722 context->invlpg = nonpaging_invlpg;
3723 context->update_pte = nonpaging_update_pte;
3724 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3725 context->root_hpa = INVALID_PAGE;
3726 context->direct_map = true;
3727 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3728 context->get_cr3 = get_cr3;
3729 context->get_pdptr = kvm_pdptr_read;
3730 context->inject_page_fault = kvm_inject_page_fault;
3732 if (!is_paging(vcpu)) {
3733 context->nx = false;
3734 context->gva_to_gpa = nonpaging_gva_to_gpa;
3735 context->root_level = 0;
3736 } else if (is_long_mode(vcpu)) {
3737 context->nx = is_nx(vcpu);
3738 context->root_level = PT64_ROOT_LEVEL;
3739 reset_rsvds_bits_mask(vcpu, context);
3740 context->gva_to_gpa = paging64_gva_to_gpa;
3741 } else if (is_pae(vcpu)) {
3742 context->nx = is_nx(vcpu);
3743 context->root_level = PT32E_ROOT_LEVEL;
3744 reset_rsvds_bits_mask(vcpu, context);
3745 context->gva_to_gpa = paging64_gva_to_gpa;
3747 context->nx = false;
3748 context->root_level = PT32_ROOT_LEVEL;
3749 reset_rsvds_bits_mask(vcpu, context);
3750 context->gva_to_gpa = paging32_gva_to_gpa;
3753 update_permission_bitmask(vcpu, context);
3754 update_last_pte_bitmap(vcpu, context);
3759 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3762 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3764 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3766 if (!is_paging(vcpu))
3767 r = nonpaging_init_context(vcpu, context);
3768 else if (is_long_mode(vcpu))
3769 r = paging64_init_context(vcpu, context);
3770 else if (is_pae(vcpu))
3771 r = paging32E_init_context(vcpu, context);
3773 r = paging32_init_context(vcpu, context);
3775 vcpu->arch.mmu.base_role.nxe = is_nx(vcpu);
3776 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3777 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3778 vcpu->arch.mmu.base_role.smep_andnot_wp
3779 = smep && !is_write_protection(vcpu);
3783 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3785 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3787 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3789 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3790 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3791 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3792 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3797 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3799 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3801 g_context->get_cr3 = get_cr3;
3802 g_context->get_pdptr = kvm_pdptr_read;
3803 g_context->inject_page_fault = kvm_inject_page_fault;
3806 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3807 * translation of l2_gpa to l1_gpa addresses is done using the
3808 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3809 * functions between mmu and nested_mmu are swapped.
3811 if (!is_paging(vcpu)) {
3812 g_context->nx = false;
3813 g_context->root_level = 0;
3814 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3815 } else if (is_long_mode(vcpu)) {
3816 g_context->nx = is_nx(vcpu);
3817 g_context->root_level = PT64_ROOT_LEVEL;
3818 reset_rsvds_bits_mask(vcpu, g_context);
3819 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3820 } else if (is_pae(vcpu)) {
3821 g_context->nx = is_nx(vcpu);
3822 g_context->root_level = PT32E_ROOT_LEVEL;
3823 reset_rsvds_bits_mask(vcpu, g_context);
3824 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3826 g_context->nx = false;
3827 g_context->root_level = PT32_ROOT_LEVEL;
3828 reset_rsvds_bits_mask(vcpu, g_context);
3829 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3832 update_permission_bitmask(vcpu, g_context);
3833 update_last_pte_bitmap(vcpu, g_context);
3838 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3840 if (mmu_is_nested(vcpu))
3841 return init_kvm_nested_mmu(vcpu);
3842 else if (tdp_enabled)
3843 return init_kvm_tdp_mmu(vcpu);
3845 return init_kvm_softmmu(vcpu);
3848 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3851 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3852 /* mmu.free() should set root_hpa = INVALID_PAGE */
3853 vcpu->arch.mmu.free(vcpu);
3856 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3858 destroy_kvm_mmu(vcpu);
3859 return init_kvm_mmu(vcpu);
3861 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3863 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3867 r = mmu_topup_memory_caches(vcpu);
3870 r = mmu_alloc_roots(vcpu);
3871 kvm_mmu_sync_roots(vcpu);
3874 /* set_cr3() should ensure TLB has been flushed */
3875 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3879 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3881 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3883 mmu_free_roots(vcpu);
3885 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3887 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3888 struct kvm_mmu_page *sp, u64 *spte,
3891 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3892 ++vcpu->kvm->stat.mmu_pde_zapped;
3896 ++vcpu->kvm->stat.mmu_pte_updated;
3897 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3900 static bool need_remote_flush(u64 old, u64 new)
3902 if (!is_shadow_present_pte(old))
3904 if (!is_shadow_present_pte(new))
3906 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3908 old ^= PT64_NX_MASK;
3909 new ^= PT64_NX_MASK;
3910 return (old & ~new & PT64_PERM_MASK) != 0;
3913 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3914 bool remote_flush, bool local_flush)
3920 kvm_flush_remote_tlbs(vcpu->kvm);
3921 else if (local_flush)
3922 kvm_mmu_flush_tlb(vcpu);
3925 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3926 const u8 *new, int *bytes)
3932 * Assume that the pte write on a page table of the same type
3933 * as the current vcpu paging mode since we update the sptes only
3934 * when they have the same mode.
3936 if (is_pae(vcpu) && *bytes == 4) {
3937 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3940 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8);
3943 new = (const u8 *)&gentry;
3948 gentry = *(const u32 *)new;
3951 gentry = *(const u64 *)new;
3962 * If we're seeing too many writes to a page, it may no longer be a page table,
3963 * or we may be forking, in which case it is better to unmap the page.
3965 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3968 * Skip write-flooding detected for the sp whose level is 1, because
3969 * it can become unsync, then the guest page is not write-protected.
3971 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3974 return ++sp->write_flooding_count >= 3;
3978 * Misaligned accesses are too much trouble to fix up; also, they usually
3979 * indicate a page is not used as a page table.
3981 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3984 unsigned offset, pte_size, misaligned;
3986 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3987 gpa, bytes, sp->role.word);
3989 offset = offset_in_page(gpa);
3990 pte_size = sp->role.cr4_pae ? 8 : 4;
3993 * Sometimes, the OS only writes the last one bytes to update status
3994 * bits, for example, in linux, andb instruction is used in clear_bit().
3996 if (!(offset & (pte_size - 1)) && bytes == 1)
3999 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4000 misaligned |= bytes < 4;
4005 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4007 unsigned page_offset, quadrant;
4011 page_offset = offset_in_page(gpa);
4012 level = sp->role.level;
4014 if (!sp->role.cr4_pae) {
4015 page_offset <<= 1; /* 32->64 */
4017 * A 32-bit pde maps 4MB while the shadow pdes map
4018 * only 2MB. So we need to double the offset again
4019 * and zap two pdes instead of one.
4021 if (level == PT32_ROOT_LEVEL) {
4022 page_offset &= ~7; /* kill rounding error */
4026 quadrant = page_offset >> PAGE_SHIFT;
4027 page_offset &= ~PAGE_MASK;
4028 if (quadrant != sp->role.quadrant)
4032 spte = &sp->spt[page_offset / sizeof(*spte)];
4036 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4037 const u8 *new, int bytes)
4039 gfn_t gfn = gpa >> PAGE_SHIFT;
4040 union kvm_mmu_page_role mask = { .word = 0 };
4041 struct kvm_mmu_page *sp;
4042 LIST_HEAD(invalid_list);
4043 u64 entry, gentry, *spte;
4045 bool remote_flush, local_flush, zap_page;
4048 * If we don't have indirect shadow pages, it means no page is
4049 * write-protected, so we can exit simply.
4051 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4054 zap_page = remote_flush = local_flush = false;
4056 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4058 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4061 * No need to care whether allocation memory is successful
4062 * or not since pte prefetch is skiped if it does not have
4063 * enough objects in the cache.
4065 mmu_topup_memory_caches(vcpu);
4067 spin_lock(&vcpu->kvm->mmu_lock);
4068 ++vcpu->kvm->stat.mmu_pte_write;
4069 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4071 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
4072 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4073 if (detect_write_misaligned(sp, gpa, bytes) ||
4074 detect_write_flooding(sp)) {
4075 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
4077 ++vcpu->kvm->stat.mmu_flooded;
4081 spte = get_written_sptes(sp, gpa, &npte);
4088 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4090 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4091 & mask.word) && rmap_can_add(vcpu))
4092 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4093 if (need_remote_flush(entry, *spte))
4094 remote_flush = true;
4098 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
4099 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4100 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4101 spin_unlock(&vcpu->kvm->mmu_lock);
4104 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4109 if (vcpu->arch.mmu.direct_map)
4112 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4114 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4118 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4120 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4122 LIST_HEAD(invalid_list);
4124 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4127 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4128 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4131 ++vcpu->kvm->stat.mmu_recycled;
4133 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4136 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4138 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4139 return vcpu_match_mmio_gpa(vcpu, addr);
4141 return vcpu_match_mmio_gva(vcpu, addr);
4144 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4145 void *insn, int insn_len)
4147 int r, emulation_type = EMULTYPE_RETRY;
4148 enum emulation_result er;
4150 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4159 if (is_mmio_page_fault(vcpu, cr2))
4162 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4167 case EMULATE_DO_MMIO:
4168 ++vcpu->stat.mmio_exits;
4178 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4180 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4182 vcpu->arch.mmu.invlpg(vcpu, gva);
4183 kvm_mmu_flush_tlb(vcpu);
4184 ++vcpu->stat.invlpg;
4186 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4188 void kvm_enable_tdp(void)
4192 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4194 void kvm_disable_tdp(void)
4196 tdp_enabled = false;
4198 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4200 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4202 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4203 if (vcpu->arch.mmu.lm_root != NULL)
4204 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4207 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4215 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4216 * Therefore we need to allocate shadow page tables in the first
4217 * 4GB of memory, which happens to fit the DMA32 zone.
4219 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4223 vcpu->arch.mmu.pae_root = page_address(page);
4224 for (i = 0; i < 4; ++i)
4225 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4230 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4234 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4235 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4236 vcpu->arch.mmu.translate_gpa = translate_gpa;
4237 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4239 return alloc_mmu_pages(vcpu);
4242 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
4245 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4247 return init_kvm_mmu(vcpu);
4250 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4252 struct kvm_memory_slot *memslot;
4256 memslot = id_to_memslot(kvm->memslots, slot);
4257 last_gfn = memslot->base_gfn + memslot->npages - 1;
4259 spin_lock(&kvm->mmu_lock);
4261 for (i = PT_PAGE_TABLE_LEVEL;
4262 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
4263 unsigned long *rmapp;
4264 unsigned long last_index, index;
4266 rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL];
4267 last_index = gfn_to_index(last_gfn, memslot->base_gfn, i);
4269 for (index = 0; index <= last_index; ++index, ++rmapp) {
4271 __rmap_write_protect(kvm, rmapp, false);
4273 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4274 kvm_flush_remote_tlbs(kvm);
4275 cond_resched_lock(&kvm->mmu_lock);
4280 kvm_flush_remote_tlbs(kvm);
4281 spin_unlock(&kvm->mmu_lock);
4284 #define BATCH_ZAP_PAGES 10
4285 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4287 struct kvm_mmu_page *sp, *node;
4291 list_for_each_entry_safe_reverse(sp, node,
4292 &kvm->arch.active_mmu_pages, link) {
4296 * No obsolete page exists before new created page since
4297 * active_mmu_pages is the FIFO list.
4299 if (!is_obsolete_sp(kvm, sp))
4303 * Since we are reversely walking the list and the invalid
4304 * list will be moved to the head, skip the invalid page
4305 * can help us to avoid the infinity list walking.
4307 if (sp->role.invalid)
4311 * Need not flush tlb since we only zap the sp with invalid
4312 * generation number.
4314 if (batch >= BATCH_ZAP_PAGES &&
4315 cond_resched_lock(&kvm->mmu_lock)) {
4320 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4321 &kvm->arch.zapped_obsolete_pages);
4329 * Should flush tlb before free page tables since lockless-walking
4330 * may use the pages.
4332 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4336 * Fast invalidate all shadow pages and use lock-break technique
4337 * to zap obsolete pages.
4339 * It's required when memslot is being deleted or VM is being
4340 * destroyed, in these cases, we should ensure that KVM MMU does
4341 * not use any resource of the being-deleted slot or all slots
4342 * after calling the function.
4344 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4346 spin_lock(&kvm->mmu_lock);
4347 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4348 kvm->arch.mmu_valid_gen++;
4351 * Notify all vcpus to reload its shadow page table
4352 * and flush TLB. Then all vcpus will switch to new
4353 * shadow page table with the new mmu_valid_gen.
4355 * Note: we should do this under the protection of
4356 * mmu-lock, otherwise, vcpu would purge shadow page
4357 * but miss tlb flush.
4359 kvm_reload_remote_mmus(kvm);
4361 kvm_zap_obsolete_pages(kvm);
4362 spin_unlock(&kvm->mmu_lock);
4365 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4367 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4370 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm)
4373 * The very rare case: if the generation-number is round,
4374 * zap all shadow pages.
4376 * The max value is MMIO_MAX_GEN - 1 since it is not called
4377 * when mark memslot invalid.
4379 if (unlikely(kvm_current_mmio_generation(kvm) >= (MMIO_MAX_GEN - 1)))
4380 kvm_mmu_invalidate_zap_all_pages(kvm);
4383 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
4386 int nr_to_scan = sc->nr_to_scan;
4388 if (nr_to_scan == 0)
4391 raw_spin_lock(&kvm_lock);
4393 list_for_each_entry(kvm, &vm_list, vm_list) {
4395 LIST_HEAD(invalid_list);
4398 * Never scan more than sc->nr_to_scan VM instances.
4399 * Will not hit this condition practically since we do not try
4400 * to shrink more than one VM and it is very unlikely to see
4401 * !n_used_mmu_pages so many times.
4406 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4407 * here. We may skip a VM instance errorneosly, but we do not
4408 * want to shrink a VM that only started to populate its MMU
4411 if (!kvm->arch.n_used_mmu_pages &&
4412 !kvm_has_zapped_obsolete_pages(kvm))
4415 idx = srcu_read_lock(&kvm->srcu);
4416 spin_lock(&kvm->mmu_lock);
4418 if (kvm_has_zapped_obsolete_pages(kvm)) {
4419 kvm_mmu_commit_zap_page(kvm,
4420 &kvm->arch.zapped_obsolete_pages);
4424 prepare_zap_oldest_mmu_page(kvm, &invalid_list);
4425 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4428 spin_unlock(&kvm->mmu_lock);
4429 srcu_read_unlock(&kvm->srcu, idx);
4431 list_move_tail(&kvm->vm_list, &vm_list);
4435 raw_spin_unlock(&kvm_lock);
4438 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4441 static struct shrinker mmu_shrinker = {
4442 .shrink = mmu_shrink,
4443 .seeks = DEFAULT_SEEKS * 10,
4446 static void mmu_destroy_caches(void)
4448 if (pte_list_desc_cache)
4449 kmem_cache_destroy(pte_list_desc_cache);
4450 if (mmu_page_header_cache)
4451 kmem_cache_destroy(mmu_page_header_cache);
4454 int kvm_mmu_module_init(void)
4456 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4457 sizeof(struct pte_list_desc),
4459 if (!pte_list_desc_cache)
4462 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4463 sizeof(struct kvm_mmu_page),
4465 if (!mmu_page_header_cache)
4468 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4471 register_shrinker(&mmu_shrinker);
4476 mmu_destroy_caches();
4481 * Caculate mmu pages needed for kvm.
4483 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4485 unsigned int nr_mmu_pages;
4486 unsigned int nr_pages = 0;
4487 struct kvm_memslots *slots;
4488 struct kvm_memory_slot *memslot;
4490 slots = kvm_memslots(kvm);
4492 kvm_for_each_memslot(memslot, slots)
4493 nr_pages += memslot->npages;
4495 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4496 nr_mmu_pages = max(nr_mmu_pages,
4497 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4499 return nr_mmu_pages;
4502 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4504 struct kvm_shadow_walk_iterator iterator;
4508 walk_shadow_page_lockless_begin(vcpu);
4509 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4510 sptes[iterator.level-1] = spte;
4512 if (!is_shadow_present_pte(spte))
4515 walk_shadow_page_lockless_end(vcpu);
4519 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4521 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4525 destroy_kvm_mmu(vcpu);
4526 free_mmu_pages(vcpu);
4527 mmu_free_memory_caches(vcpu);
4530 void kvm_mmu_module_exit(void)
4532 mmu_destroy_caches();
4533 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4534 unregister_shrinker(&mmu_shrinker);
4535 mmu_audit_disable();