Pileus Git - ~andy/linux/blob - arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include "kvm_cache_regs.h"
  38 #include "irq.h"
  39 #include "trace.h"
  40 #include "x86.h"
  41 #include "cpuid.h"
  42
  43 #ifndef CONFIG_X86_64
  44 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  45 #else
  46 #define mod_64(x, y) ((x) % (y))
  47 #endif
  48
  49 #define PRId64 "d"
  50 #define PRIx64 "llx"
  51 #define PRIu64 "u"
  52 #define PRIo64 "o"
  53
  54 #define APIC_BUS_CYCLE_NS 1
  55
  56 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  57 #define apic_debug(fmt, arg...)
  58
  59 #define APIC_LVT_NUM                    6
  60 /* 14 is the version for Xeon and Pentium 8.4.8*/
  61 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  62 #define LAPIC_MMIO_LENGTH               (1 << 12)
  63 /* followed define is not in apicdef.h */
  64 #define APIC_SHORT_MASK                 0xc0000
  65 #define APIC_DEST_NOSHORT               0x0
  66 #define APIC_DEST_MASK                  0x800
  67 #define MAX_APIC_VECTOR                 256
  68
  69 #define VEC_POS(v) ((v) & (32 - 1))
  70 #define REG_POS(v) (((v) >> 5) << 4)
  71
  72 static unsigned int min_timer_period_us = 500;
  73 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
  74
  75 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  76 {
  77         return *((u32 *) (apic->regs + reg_off));
  78 }
  79
  80 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  81 {
  82         *((u32 *) (apic->regs + reg_off)) = val;
  83 }
  84
  85 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  86 {
  87         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  88 }
  89
  90 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  91 {
  92         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  93 }
  94
  95 static inline int apic_test_vector(int vec, void *bitmap)
  96 {
  97         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  98 }
  99
 100 static inline void apic_set_vector(int vec, void *bitmap)
 101 {
 102         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 103 }
 104
 105 static inline void apic_clear_vector(int vec, void *bitmap)
 106 {
 107         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 108 }
 109
 110 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 111 {
 112         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 113 }
 114
 115 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 116 {
 117         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 118 }
 119
 120 static inline int apic_hw_enabled(struct kvm_lapic *apic)
 121 {
 122         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 123 }
 124
 125 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 126 {
 127         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 128 }
 129
 130 static inline int apic_enabled(struct kvm_lapic *apic)
 131 {
 132         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 133 }
 134
 135 #define LVT_MASK        \
 136         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 137
 138 #define LINT_MASK       \
 139         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 140          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 141
 142 static inline int kvm_apic_id(struct kvm_lapic *apic)
 143 {
 144         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 145 }
 146
 147 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 148 {
 149         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 150 }
 151
 152 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 153 {
 154         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 155 }
 156
 157 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 158 {
 159         return ((apic_get_reg(apic, APIC_LVTT) &
 160                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
 161 }
 162
 163 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 164 {
 165         return ((apic_get_reg(apic, APIC_LVTT) &
 166                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
 167 }
 168
 169 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 170 {
 171         return ((apic_get_reg(apic, APIC_LVTT) &
 172                 apic->lapic_timer.timer_mode_mask) ==
 173                         APIC_LVT_TIMER_TSCDEADLINE);
 174 }
 175
 176 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 177 {
 178         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 179 }
 180
 181 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 182 {
 183         struct kvm_lapic *apic = vcpu->arch.apic;
 184         struct kvm_cpuid_entry2 *feat;
 185         u32 v = APIC_VERSION;
 186
 187         if (!irqchip_in_kernel(vcpu->kvm))
 188                 return;
 189
 190         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 191         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 192                 v |= APIC_LVR_DIRECTED_EOI;
 193         apic_set_reg(apic, APIC_LVR, v);
 194 }
 195
 196 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 197 {
 198         return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
 199 }
 200
 201 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 202         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 203         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 204         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 205         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 206         LVT_MASK                /* LVTERR */
 207 };
 208
 209 static int find_highest_vector(void *bitmap)
 210 {
 211         u32 *word = bitmap;
 212         int word_offset = MAX_APIC_VECTOR >> 5;
 213
 214         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 215                 continue;
 216
 217         if (likely(!word_offset && !word[0]))
 218                 return -1;
 219         else
 220                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 221 }
 222
 223 static u8 count_vectors(void *bitmap)
 224 {
 225         u32 *word = bitmap;
 226         int word_offset;
 227         u8 count = 0;
 228         for (word_offset = 0; word_offset < MAX_APIC_VECTOR >> 5; ++word_offset)
 229                 count += hweight32(word[word_offset << 2]);
 230         return count;
 231 }
 232
 233 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 234 {
 235         apic->irr_pending = true;
 236         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 237 }
 238
 239 static inline int apic_search_irr(struct kvm_lapic *apic)
 240 {
 241         return find_highest_vector(apic->regs + APIC_IRR);
 242 }
 243
 244 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 245 {
 246         int result;
 247
 248         if (!apic->irr_pending)
 249                 return -1;
 250
 251         result = apic_search_irr(apic);
 252         ASSERT(result == -1 || result >= 16);
 253
 254         return result;
 255 }
 256
 257 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 258 {
 259         apic->irr_pending = false;
 260         apic_clear_vector(vec, apic->regs + APIC_IRR);
 261         if (apic_search_irr(apic) != -1)
 262                 apic->irr_pending = true;
 263 }
 264
 265 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 266 {
 267         if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 268                 ++apic->isr_count;
 269         BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 270         /*
 271          * ISR (in service register) bit is set when injecting an interrupt.
 272          * The highest vector is injected. Thus the latest bit set matches
 273          * the highest bit in ISR.
 274          */
 275         apic->highest_isr_cache = vec;
 276 }
 277
 278 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 279 {
 280         if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 281                 --apic->isr_count;
 282         BUG_ON(apic->isr_count < 0);
 283         apic->highest_isr_cache = -1;
 284 }
 285
 286 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 287 {
 288         struct kvm_lapic *apic = vcpu->arch.apic;
 289         int highest_irr;
 290
 291         /* This may race with setting of irr in __apic_accept_irq() and
 292          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 293          * will cause vmexit immediately and the value will be recalculated
 294          * on the next vmentry.
 295          */
 296         if (!apic)
 297                 return 0;
 298         highest_irr = apic_find_highest_irr(apic);
 299
 300         return highest_irr;
 301 }
 302
 303 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 304                              int vector, int level, int trig_mode);
 305
 306 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 307 {
 308         struct kvm_lapic *apic = vcpu->arch.apic;
 309
 310         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 311                         irq->level, irq->trig_mode);
 312 }
 313
 314 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 315 {
 316         int result;
 317         if (!apic->isr_count)
 318                 return -1;
 319         if (likely(apic->highest_isr_cache != -1))
 320                 return apic->highest_isr_cache;
 321
 322         result = find_highest_vector(apic->regs + APIC_ISR);
 323         ASSERT(result == -1 || result >= 16);
 324
 325         return result;
 326 }
 327
 328 static void apic_update_ppr(struct kvm_lapic *apic)
 329 {
 330         u32 tpr, isrv, ppr, old_ppr;
 331         int isr;
 332
 333         old_ppr = apic_get_reg(apic, APIC_PROCPRI);
 334         tpr = apic_get_reg(apic, APIC_TASKPRI);
 335         isr = apic_find_highest_isr(apic);
 336         isrv = (isr != -1) ? isr : 0;
 337
 338         if ((tpr & 0xf0) >= (isrv & 0xf0))
 339                 ppr = tpr & 0xff;
 340         else
 341                 ppr = isrv & 0xf0;
 342
 343         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 344                    apic, ppr, isr, isrv);
 345
 346         if (old_ppr != ppr) {
 347                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 348                 if (ppr < old_ppr)
 349                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 350         }
 351 }
 352
 353 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 354 {
 355         apic_set_reg(apic, APIC_TASKPRI, tpr);
 356         apic_update_ppr(apic);
 357 }
 358
 359 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 360 {
 361         return dest == 0xff || kvm_apic_id(apic) == dest;
 362 }
 363
 364 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 365 {
 366         int result = 0;
 367         u32 logical_id;
 368
 369         if (apic_x2apic_mode(apic)) {
 370                 logical_id = apic_get_reg(apic, APIC_LDR);
 371                 return logical_id & mda;
 372         }
 373
 374         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 375
 376         switch (apic_get_reg(apic, APIC_DFR)) {
 377         case APIC_DFR_FLAT:
 378                 if (logical_id & mda)
 379                         result = 1;
 380                 break;
 381         case APIC_DFR_CLUSTER:
 382                 if (((logical_id >> 4) == (mda >> 0x4))
 383                     && (logical_id & mda & 0xf))
 384                         result = 1;
 385                 break;
 386         default:
 387                 apic_debug("Bad DFR vcpu %d: %08x\n",
 388                            apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 389                 break;
 390         }
 391
 392         return result;
 393 }
 394
 395 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 396                            int short_hand, int dest, int dest_mode)
 397 {
 398         int result = 0;
 399         struct kvm_lapic *target = vcpu->arch.apic;
 400
 401         apic_debug("target %p, source %p, dest 0x%x, "
 402                    "dest_mode 0x%x, short_hand 0x%x\n",
 403                    target, source, dest, dest_mode, short_hand);
 404
 405         ASSERT(target);
 406         switch (short_hand) {
 407         case APIC_DEST_NOSHORT:
 408                 if (dest_mode == 0)
 409                         /* Physical mode. */
 410                         result = kvm_apic_match_physical_addr(target, dest);
 411                 else
 412                         /* Logical mode. */
 413                         result = kvm_apic_match_logical_addr(target, dest);
 414                 break;
 415         case APIC_DEST_SELF:
 416                 result = (target == source);
 417                 break;
 418         case APIC_DEST_ALLINC:
 419                 result = 1;
 420                 break;
 421         case APIC_DEST_ALLBUT:
 422                 result = (target != source);
 423                 break;
 424         default:
 425                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 426                            short_hand);
 427                 break;
 428         }
 429
 430         return result;
 431 }
 432
 433 /*
 434  * Add a pending IRQ into lapic.
 435  * Return 1 if successfully added and 0 if discarded.
 436  */
 437 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 438                              int vector, int level, int trig_mode)
 439 {
 440         int result = 0;
 441         struct kvm_vcpu *vcpu = apic->vcpu;
 442
 443         switch (delivery_mode) {
 444         case APIC_DM_LOWEST:
 445                 vcpu->arch.apic_arb_prio++;
 446         case APIC_DM_FIXED:
 447                 /* FIXME add logic for vcpu on reset */
 448                 if (unlikely(!apic_enabled(apic)))
 449                         break;
 450
 451                 if (trig_mode) {
 452                         apic_debug("level trig mode for vector %d", vector);
 453                         apic_set_vector(vector, apic->regs + APIC_TMR);
 454                 } else
 455                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 456
 457                 result = !apic_test_and_set_irr(vector, apic);
 458                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 459                                           trig_mode, vector, !result);
 460                 if (!result) {
 461                         if (trig_mode)
 462                                 apic_debug("level trig mode repeatedly for "
 463                                                 "vector %d", vector);
 464                         break;
 465                 }
 466
 467                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 468                 kvm_vcpu_kick(vcpu);
 469                 break;
 470
 471         case APIC_DM_REMRD:
 472                 apic_debug("Ignoring delivery mode 3\n");
 473                 break;
 474
 475         case APIC_DM_SMI:
 476                 apic_debug("Ignoring guest SMI\n");
 477                 break;
 478
 479         case APIC_DM_NMI:
 480                 result = 1;
 481                 kvm_inject_nmi(vcpu);
 482                 kvm_vcpu_kick(vcpu);
 483                 break;
 484
 485         case APIC_DM_INIT:
 486                 if (!trig_mode || level) {
 487                         result = 1;
 488                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 489                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 490                         kvm_vcpu_kick(vcpu);
 491                 } else {
 492                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 493                                    vcpu->vcpu_id);
 494                 }
 495                 break;
 496
 497         case APIC_DM_STARTUP:
 498                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 499                            vcpu->vcpu_id, vector);
 500                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 501                         result = 1;
 502                         vcpu->arch.sipi_vector = vector;
 503                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 504                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 505                         kvm_vcpu_kick(vcpu);
 506                 }
 507                 break;
 508
 509         case APIC_DM_EXTINT:
 510                 /*
 511                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 512                  * before NMI watchdog was enabled. Already handled by
 513                  * kvm_apic_accept_pic_intr().
 514                  */
 515                 break;
 516
 517         default:
 518                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 519                        delivery_mode);
 520                 break;
 521         }
 522         return result;
 523 }
 524
 525 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 526 {
 527         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 528 }
 529
 530 static void apic_set_eoi(struct kvm_lapic *apic)
 531 {
 532         int vector = apic_find_highest_isr(apic);
 533         /*
 534          * Not every write EOI will has corresponding ISR,
 535          * one example is when Kernel check timer on setup_IO_APIC
 536          */
 537         if (vector == -1)
 538                 return;
 539
 540         apic_clear_isr(vector, apic);
 541         apic_update_ppr(apic);
 542
 543         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 544             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 545                 int trigger_mode;
 546                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 547                         trigger_mode = IOAPIC_LEVEL_TRIG;
 548                 else
 549                         trigger_mode = IOAPIC_EDGE_TRIG;
 550                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 551         }
 552         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 553 }
 554
 555 static void apic_send_ipi(struct kvm_lapic *apic)
 556 {
 557         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 558         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 559         struct kvm_lapic_irq irq;
 560
 561         irq.vector = icr_low & APIC_VECTOR_MASK;
 562         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 563         irq.dest_mode = icr_low & APIC_DEST_MASK;
 564         irq.level = icr_low & APIC_INT_ASSERT;
 565         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 566         irq.shorthand = icr_low & APIC_SHORT_MASK;
 567         if (apic_x2apic_mode(apic))
 568                 irq.dest_id = icr_high;
 569         else
 570                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 571
 572         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 573
 574         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 575                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 576                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 577                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 578                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 579                    irq.vector);
 580
 581         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
 582 }
 583
 584 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 585 {
 586         ktime_t remaining;
 587         s64 ns;
 588         u32 tmcct;
 589
 590         ASSERT(apic != NULL);
 591
 592         /* if initial count is 0, current count should also be 0 */
 593         if (apic_get_reg(apic, APIC_TMICT) == 0)
 594                 return 0;
 595
 596         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 597         if (ktime_to_ns(remaining) < 0)
 598                 remaining = ktime_set(0, 0);
 599
 600         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 601         tmcct = div64_u64(ns,
 602                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 603
 604         return tmcct;
 605 }
 606
 607 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 608 {
 609         struct kvm_vcpu *vcpu = apic->vcpu;
 610         struct kvm_run *run = vcpu->run;
 611
 612         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 613         run->tpr_access.rip = kvm_rip_read(vcpu);
 614         run->tpr_access.is_write = write;
 615 }
 616
 617 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 618 {
 619         if (apic->vcpu->arch.tpr_access_reporting)
 620                 __report_tpr_access(apic, write);
 621 }
 622
 623 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 624 {
 625         u32 val = 0;
 626
 627         if (offset >= LAPIC_MMIO_LENGTH)
 628                 return 0;
 629
 630         switch (offset) {
 631         case APIC_ID:
 632                 if (apic_x2apic_mode(apic))
 633                         val = kvm_apic_id(apic);
 634                 else
 635                         val = kvm_apic_id(apic) << 24;
 636                 break;
 637         case APIC_ARBPRI:
 638                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 639                 break;
 640
 641         case APIC_TMCCT:        /* Timer CCR */
 642                 if (apic_lvtt_tscdeadline(apic))
 643                         return 0;
 644
 645                 val = apic_get_tmcct(apic);
 646                 break;
 647
 648         case APIC_TASKPRI:
 649                 report_tpr_access(apic, false);
 650                 /* fall thru */
 651         default:
 652                 apic_update_ppr(apic);
 653                 val = apic_get_reg(apic, offset);
 654                 break;
 655         }
 656
 657         return val;
 658 }
 659
 660 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 661 {
 662         return container_of(dev, struct kvm_lapic, dev);
 663 }
 664
 665 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 666                 void *data)
 667 {
 668         unsigned char alignment = offset & 0xf;
 669         u32 result;
 670         /* this bitmask has a bit cleared for each reserver register */
 671         static const u64 rmask = 0x43ff01ffffffe70cULL;
 672
 673         if ((alignment + len) > 4) {
 674                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 675                            offset, len);
 676                 return 1;
 677         }
 678
 679         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 680                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 681                            offset);
 682                 return 1;
 683         }
 684
 685         result = __apic_read(apic, offset & ~0xf);
 686
 687         trace_kvm_apic_read(offset, result);
 688
 689         switch (len) {
 690         case 1:
 691         case 2:
 692         case 4:
 693                 memcpy(data, (char *)&result + alignment, len);
 694                 break;
 695         default:
 696                 printk(KERN_ERR "Local APIC read with len = %x, "
 697                        "should be 1,2, or 4 instead\n", len);
 698                 break;
 699         }
 700         return 0;
 701 }
 702
 703 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 704 {
 705         return apic_hw_enabled(apic) &&
 706             addr >= apic->base_address &&
 707             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 708 }
 709
 710 static int apic_mmio_read(struct kvm_io_device *this,
 711                            gpa_t address, int len, void *data)
 712 {
 713         struct kvm_lapic *apic = to_lapic(this);
 714         u32 offset = address - apic->base_address;
 715
 716         if (!apic_mmio_in_range(apic, address))
 717                 return -EOPNOTSUPP;
 718
 719         apic_reg_read(apic, offset, len, data);
 720
 721         return 0;
 722 }
 723
 724 static void update_divide_count(struct kvm_lapic *apic)
 725 {
 726         u32 tmp1, tmp2, tdcr;
 727
 728         tdcr = apic_get_reg(apic, APIC_TDCR);
 729         tmp1 = tdcr & 0xf;
 730         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 731         apic->divide_count = 0x1 << (tmp2 & 0x7);
 732
 733         apic_debug("timer divide count is 0x%x\n",
 734                                    apic->divide_count);
 735 }
 736
 737 static void start_apic_timer(struct kvm_lapic *apic)
 738 {
 739         ktime_t now;
 740         atomic_set(&apic->lapic_timer.pending, 0);
 741
 742         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
 743                 /* lapic timer in oneshot or peroidic mode */
 744                 now = apic->lapic_timer.timer.base->get_time();
 745                 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT)
 746                             * APIC_BUS_CYCLE_NS * apic->divide_count;
 747
 748                 if (!apic->lapic_timer.period)
 749                         return;
 750                 /*
 751                  * Do not allow the guest to program periodic timers with small
 752                  * interval, since the hrtimers are not throttled by the host
 753                  * scheduler.
 754                  */
 755                 if (apic_lvtt_period(apic)) {
 756                         s64 min_period = min_timer_period_us * 1000LL;
 757
 758                         if (apic->lapic_timer.period < min_period) {
 759                                 pr_info_ratelimited(
 760                                     "kvm: vcpu %i: requested %lld ns "
 761                                     "lapic timer period limited to %lld ns\n",
 762                                     apic->vcpu->vcpu_id,
 763                                     apic->lapic_timer.period, min_period);
 764                                 apic->lapic_timer.period = min_period;
 765                         }
 766                 }
 767
 768                 hrtimer_start(&apic->lapic_timer.timer,
 769                               ktime_add_ns(now, apic->lapic_timer.period),
 770                               HRTIMER_MODE_ABS);
 771
 772                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 773                            PRIx64 ", "
 774                            "timer initial count 0x%x, period %lldns, "
 775                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 776                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 777                            apic_get_reg(apic, APIC_TMICT),
 778                            apic->lapic_timer.period,
 779                            ktime_to_ns(ktime_add_ns(now,
 780                                         apic->lapic_timer.period)));
 781         } else if (apic_lvtt_tscdeadline(apic)) {
 782                 /* lapic timer in tsc deadline mode */
 783                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
 784                 u64 ns = 0;
 785                 struct kvm_vcpu *vcpu = apic->vcpu;
 786                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
 787                 unsigned long flags;
 788
 789                 if (unlikely(!tscdeadline || !this_tsc_khz))
 790                         return;
 791
 792                 local_irq_save(flags);
 793
 794                 now = apic->lapic_timer.timer.base->get_time();
 795                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
 796                 if (likely(tscdeadline > guest_tsc)) {
 797                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
 798                         do_div(ns, this_tsc_khz);
 799                 }
 800                 hrtimer_start(&apic->lapic_timer.timer,
 801                         ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
 802
 803                 local_irq_restore(flags);
 804         }
 805 }
 806
 807 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 808 {
 809         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 810
 811         if (apic_lvt_nmi_mode(lvt0_val)) {
 812                 if (!nmi_wd_enabled) {
 813                         apic_debug("Receive NMI setting on APIC_LVT0 "
 814                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 815                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 816                 }
 817         } else if (nmi_wd_enabled)
 818                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 819 }
 820
 821 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 822 {
 823         int ret = 0;
 824
 825         trace_kvm_apic_write(reg, val);
 826
 827         switch (reg) {
 828         case APIC_ID:           /* Local APIC ID */
 829                 if (!apic_x2apic_mode(apic))
 830                         apic_set_reg(apic, APIC_ID, val);
 831                 else
 832                         ret = 1;
 833                 break;
 834
 835         case APIC_TASKPRI:
 836                 report_tpr_access(apic, true);
 837                 apic_set_tpr(apic, val & 0xff);
 838                 break;
 839
 840         case APIC_EOI:
 841                 apic_set_eoi(apic);
 842                 break;
 843
 844         case APIC_LDR:
 845                 if (!apic_x2apic_mode(apic))
 846                         apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 847                 else
 848                         ret = 1;
 849                 break;
 850
 851         case APIC_DFR:
 852                 if (!apic_x2apic_mode(apic))
 853                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 854                 else
 855                         ret = 1;
 856                 break;
 857
 858         case APIC_SPIV: {
 859                 u32 mask = 0x3ff;
 860                 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
 861                         mask |= APIC_SPIV_DIRECTED_EOI;
 862                 apic_set_reg(apic, APIC_SPIV, val & mask);
 863                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 864                         int i;
 865                         u32 lvt_val;
 866
 867                         for (i = 0; i < APIC_LVT_NUM; i++) {
 868                                 lvt_val = apic_get_reg(apic,
 869                                                        APIC_LVTT + 0x10 * i);
 870                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 871                                              lvt_val | APIC_LVT_MASKED);
 872                         }
 873                         atomic_set(&apic->lapic_timer.pending, 0);
 874
 875                 }
 876                 break;
 877         }
 878         case APIC_ICR:
 879                 /* No delay here, so we always clear the pending bit */
 880                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 881                 apic_send_ipi(apic);
 882                 break;
 883
 884         case APIC_ICR2:
 885                 if (!apic_x2apic_mode(apic))
 886                         val &= 0xff000000;
 887                 apic_set_reg(apic, APIC_ICR2, val);
 888                 break;
 889
 890         case APIC_LVT0:
 891                 apic_manage_nmi_watchdog(apic, val);
 892         case APIC_LVTTHMR:
 893         case APIC_LVTPC:
 894         case APIC_LVT1:
 895         case APIC_LVTERR:
 896                 /* TODO: Check vector */
 897                 if (!apic_sw_enabled(apic))
 898                         val |= APIC_LVT_MASKED;
 899
 900                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
 901                 apic_set_reg(apic, reg, val);
 902
 903                 break;
 904
 905         case APIC_LVTT:
 906                 if ((apic_get_reg(apic, APIC_LVTT) &
 907                     apic->lapic_timer.timer_mode_mask) !=
 908                    (val & apic->lapic_timer.timer_mode_mask))
 909                         hrtimer_cancel(&apic->lapic_timer.timer);
 910
 911                 if (!apic_sw_enabled(apic))
 912                         val |= APIC_LVT_MASKED;
 913                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
 914                 apic_set_reg(apic, APIC_LVTT, val);
 915                 break;
 916
 917         case APIC_TMICT:
 918                 if (apic_lvtt_tscdeadline(apic))
 919                         break;
 920
 921                 hrtimer_cancel(&apic->lapic_timer.timer);
 922                 apic_set_reg(apic, APIC_TMICT, val);
 923                 start_apic_timer(apic);
 924                 break;
 925
 926         case APIC_TDCR:
 927                 if (val & 4)
 928                         apic_debug("KVM_WRITE:TDCR %x\n", val);
 929                 apic_set_reg(apic, APIC_TDCR, val);
 930                 update_divide_count(apic);
 931                 break;
 932
 933         case APIC_ESR:
 934                 if (apic_x2apic_mode(apic) && val != 0) {
 935                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
 936                         ret = 1;
 937                 }
 938                 break;
 939
 940         case APIC_SELF_IPI:
 941                 if (apic_x2apic_mode(apic)) {
 942                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
 943                 } else
 944                         ret = 1;
 945                 break;
 946         default:
 947                 ret = 1;
 948                 break;
 949         }
 950         if (ret)
 951                 apic_debug("Local APIC Write to read-only register %x\n", reg);
 952         return ret;
 953 }
 954
 955 static int apic_mmio_write(struct kvm_io_device *this,
 956                             gpa_t address, int len, const void *data)
 957 {
 958         struct kvm_lapic *apic = to_lapic(this);
 959         unsigned int offset = address - apic->base_address;
 960         u32 val;
 961
 962         if (!apic_mmio_in_range(apic, address))
 963                 return -EOPNOTSUPP;
 964
 965         /*
 966          * APIC register must be aligned on 128-bits boundary.
 967          * 32/64/128 bits registers must be accessed thru 32 bits.
 968          * Refer SDM 8.4.1
 969          */
 970         if (len != 4 || (offset & 0xf)) {
 971                 /* Don't shout loud, $infamous_os would cause only noise. */
 972                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
 973                 return 0;
 974         }
 975
 976         val = *(u32*)data;
 977
 978         /* too common printing */
 979         if (offset != APIC_EOI)
 980                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 981                            "0x%x\n", __func__, offset, len, val);
 982
 983         apic_reg_write(apic, offset & 0xff0, val);
 984
 985         return 0;
 986 }
 987
 988 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
 989 {
 990         struct kvm_lapic *apic = vcpu->arch.apic;
 991
 992         if (apic)
 993                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
 994 }
 995 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
 996
 997 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 998 {
 999         if (!vcpu->arch.apic)
1000                 return;
1001
1002         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
1003
1004         if (vcpu->arch.apic->regs)
1005                 free_page((unsigned long)vcpu->arch.apic->regs);
1006
1007         kfree(vcpu->arch.apic);
1008 }
1009
1010 /*
1011  *----------------------------------------------------------------------
1012  * LAPIC interface
1013  *----------------------------------------------------------------------
1014  */
1015
1016 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1017 {
1018         struct kvm_lapic *apic = vcpu->arch.apic;
1019         if (!apic)
1020                 return 0;
1021
1022         if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
1023                 return 0;
1024
1025         return apic->lapic_timer.tscdeadline;
1026 }
1027
1028 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1029 {
1030         struct kvm_lapic *apic = vcpu->arch.apic;
1031         if (!apic)
1032                 return;
1033
1034         if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
1035                 return;
1036
1037         hrtimer_cancel(&apic->lapic_timer.timer);
1038         apic->lapic_timer.tscdeadline = data;
1039         start_apic_timer(apic);
1040 }
1041
1042 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1043 {
1044         struct kvm_lapic *apic = vcpu->arch.apic;
1045
1046         if (!apic)
1047                 return;
1048         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1049                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
1050 }
1051
1052 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1053 {
1054         struct kvm_lapic *apic = vcpu->arch.apic;
1055         u64 tpr;
1056
1057         if (!apic)
1058                 return 0;
1059         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
1060
1061         return (tpr & 0xf0) >> 4;
1062 }
1063
1064 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1065 {
1066         struct kvm_lapic *apic = vcpu->arch.apic;
1067
1068         if (!apic) {
1069                 value |= MSR_IA32_APICBASE_BSP;
1070                 vcpu->arch.apic_base = value;
1071                 return;
1072         }
1073
1074         if (!kvm_vcpu_is_bsp(apic->vcpu))
1075                 value &= ~MSR_IA32_APICBASE_BSP;
1076
1077         vcpu->arch.apic_base = value;
1078         if (apic_x2apic_mode(apic)) {
1079                 u32 id = kvm_apic_id(apic);
1080                 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
1081                 apic_set_reg(apic, APIC_LDR, ldr);
1082         }
1083         apic->base_address = apic->vcpu->arch.apic_base &
1084                              MSR_IA32_APICBASE_BASE;
1085
1086         /* with FSB delivery interrupt, we can restart APIC functionality */
1087         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1088                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1089
1090 }
1091
1092 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1093 {
1094         struct kvm_lapic *apic;
1095         int i;
1096
1097         apic_debug("%s\n", __func__);
1098
1099         ASSERT(vcpu);
1100         apic = vcpu->arch.apic;
1101         ASSERT(apic != NULL);
1102
1103         /* Stop the timer in case it's a reset to an active apic */
1104         hrtimer_cancel(&apic->lapic_timer.timer);
1105
1106         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
1107         kvm_apic_set_version(apic->vcpu);
1108
1109         for (i = 0; i < APIC_LVT_NUM; i++)
1110                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1111         apic_set_reg(apic, APIC_LVT0,
1112                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1113
1114         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1115         apic_set_reg(apic, APIC_SPIV, 0xff);
1116         apic_set_reg(apic, APIC_TASKPRI, 0);
1117         apic_set_reg(apic, APIC_LDR, 0);
1118         apic_set_reg(apic, APIC_ESR, 0);
1119         apic_set_reg(apic, APIC_ICR, 0);
1120         apic_set_reg(apic, APIC_ICR2, 0);
1121         apic_set_reg(apic, APIC_TDCR, 0);
1122         apic_set_reg(apic, APIC_TMICT, 0);
1123         for (i = 0; i < 8; i++) {
1124                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1125                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1126                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1127         }
1128         apic->irr_pending = false;
1129         apic->isr_count = 0;
1130         apic->highest_isr_cache = -1;
1131         update_divide_count(apic);
1132         atomic_set(&apic->lapic_timer.pending, 0);
1133         if (kvm_vcpu_is_bsp(vcpu))
1134                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1135         apic_update_ppr(apic);
1136
1137         vcpu->arch.apic_arb_prio = 0;
1138         vcpu->arch.apic_attention = 0;
1139
1140         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1141                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1142                    vcpu, kvm_apic_id(apic),
1143                    vcpu->arch.apic_base, apic->base_address);
1144 }
1145
1146 bool kvm_apic_present(struct kvm_vcpu *vcpu)
1147 {
1148         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
1149 }
1150
1151 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1152 {
1153         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
1154 }
1155
1156 /*
1157  *----------------------------------------------------------------------
1158  * timer interface
1159  *----------------------------------------------------------------------
1160  */
1161
1162 static bool lapic_is_periodic(struct kvm_timer *ktimer)
1163 {
1164         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1165                                               lapic_timer);
1166         return apic_lvtt_period(apic);
1167 }
1168
1169 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1170 {
1171         struct kvm_lapic *lapic = vcpu->arch.apic;
1172
1173         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1174                 return atomic_read(&lapic->lapic_timer.pending);
1175
1176         return 0;
1177 }
1178
1179 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1180 {
1181         u32 reg = apic_get_reg(apic, lvt_type);
1182         int vector, mode, trig_mode;
1183
1184         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1185                 vector = reg & APIC_VECTOR_MASK;
1186                 mode = reg & APIC_MODE_MASK;
1187                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1188                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1189         }
1190         return 0;
1191 }
1192
1193 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1194 {
1195         struct kvm_lapic *apic = vcpu->arch.apic;
1196
1197         if (apic)
1198                 kvm_apic_local_deliver(apic, APIC_LVT0);
1199 }
1200
1201 static struct kvm_timer_ops lapic_timer_ops = {
1202         .is_periodic = lapic_is_periodic,
1203 };
1204
1205 static const struct kvm_io_device_ops apic_mmio_ops = {
1206         .read     = apic_mmio_read,
1207         .write    = apic_mmio_write,
1208 };
1209
1210 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1211 {
1212         struct kvm_lapic *apic;
1213
1214         ASSERT(vcpu != NULL);
1215         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1216
1217         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1218         if (!apic)
1219                 goto nomem;
1220
1221         vcpu->arch.apic = apic;
1222
1223         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1224         if (!apic->regs) {
1225                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1226                        vcpu->vcpu_id);
1227                 goto nomem_free_apic;
1228         }
1229         apic->vcpu = vcpu;
1230
1231         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1232                      HRTIMER_MODE_ABS);
1233         apic->lapic_timer.timer.function = kvm_timer_fn;
1234         apic->lapic_timer.t_ops = &lapic_timer_ops;
1235         apic->lapic_timer.kvm = vcpu->kvm;
1236         apic->lapic_timer.vcpu = vcpu;
1237
1238         apic->base_address = APIC_DEFAULT_PHYS_BASE;
1239         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1240
1241         kvm_lapic_reset(vcpu);
1242         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1243
1244         return 0;
1245 nomem_free_apic:
1246         kfree(apic);
1247 nomem:
1248         return -ENOMEM;
1249 }
1250
1251 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1252 {
1253         struct kvm_lapic *apic = vcpu->arch.apic;
1254         int highest_irr;
1255
1256         if (!apic || !apic_enabled(apic))
1257                 return -1;
1258
1259         apic_update_ppr(apic);
1260         highest_irr = apic_find_highest_irr(apic);
1261         if ((highest_irr == -1) ||
1262             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1263                 return -1;
1264         return highest_irr;
1265 }
1266
1267 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1268 {
1269         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1270         int r = 0;
1271
1272         if (!apic_hw_enabled(vcpu->arch.apic))
1273                 r = 1;
1274         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1275             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1276                 r = 1;
1277         return r;
1278 }
1279
1280 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1281 {
1282         struct kvm_lapic *apic = vcpu->arch.apic;
1283
1284         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1285                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1286                         atomic_dec(&apic->lapic_timer.pending);
1287         }
1288 }
1289
1290 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1291 {
1292         int vector = kvm_apic_has_interrupt(vcpu);
1293         struct kvm_lapic *apic = vcpu->arch.apic;
1294
1295         if (vector == -1)
1296                 return -1;
1297
1298         apic_set_isr(vector, apic);
1299         apic_update_ppr(apic);
1300         apic_clear_irr(vector, apic);
1301         return vector;
1302 }
1303
1304 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1305 {
1306         struct kvm_lapic *apic = vcpu->arch.apic;
1307
1308         apic->base_address = vcpu->arch.apic_base &
1309                              MSR_IA32_APICBASE_BASE;
1310         kvm_apic_set_version(vcpu);
1311
1312         apic_update_ppr(apic);
1313         hrtimer_cancel(&apic->lapic_timer.timer);
1314         update_divide_count(apic);
1315         start_apic_timer(apic);
1316         apic->irr_pending = true;
1317         apic->isr_count = count_vectors(apic->regs + APIC_ISR);
1318         apic->highest_isr_cache = -1;
1319         kvm_make_request(KVM_REQ_EVENT, vcpu);
1320 }
1321
1322 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1323 {
1324         struct kvm_lapic *apic = vcpu->arch.apic;
1325         struct hrtimer *timer;
1326
1327         if (!apic)
1328                 return;
1329
1330         timer = &apic->lapic_timer.timer;
1331         if (hrtimer_cancel(timer))
1332                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1333 }
1334
1335 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1336 {
1337         u32 data;
1338         void *vapic;
1339
1340         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1341                 return;
1342
1343         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1344         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1345         kunmap_atomic(vapic);
1346
1347         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1348 }
1349
1350 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1351 {
1352         u32 data, tpr;
1353         int max_irr, max_isr;
1354         struct kvm_lapic *apic;
1355         void *vapic;
1356
1357         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1358                 return;
1359
1360         apic = vcpu->arch.apic;
1361         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1362         max_irr = apic_find_highest_irr(apic);
1363         if (max_irr < 0)
1364                 max_irr = 0;
1365         max_isr = apic_find_highest_isr(apic);
1366         if (max_isr < 0)
1367                 max_isr = 0;
1368         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1369
1370         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1371         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1372         kunmap_atomic(vapic);
1373 }
1374
1375 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1376 {
1377         vcpu->arch.apic->vapic_addr = vapic_addr;
1378         if (vapic_addr)
1379                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1380         else
1381                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1382 }
1383
1384 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1385 {
1386         struct kvm_lapic *apic = vcpu->arch.apic;
1387         u32 reg = (msr - APIC_BASE_MSR) << 4;
1388
1389         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1390                 return 1;
1391
1392         /* if this is ICR write vector before command */
1393         if (msr == 0x830)
1394                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1395         return apic_reg_write(apic, reg, (u32)data);
1396 }
1397
1398 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1399 {
1400         struct kvm_lapic *apic = vcpu->arch.apic;
1401         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1402
1403         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1404                 return 1;
1405
1406         if (apic_reg_read(apic, reg, 4, &low))
1407                 return 1;
1408         if (msr == 0x830)
1409                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1410
1411         *data = (((u64)high) << 32) | low;
1412
1413         return 0;
1414 }
1415
1416 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1417 {
1418         struct kvm_lapic *apic = vcpu->arch.apic;
1419
1420         if (!irqchip_in_kernel(vcpu->kvm))
1421                 return 1;
1422
1423         /* if this is ICR write vector before command */
1424         if (reg == APIC_ICR)
1425                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1426         return apic_reg_write(apic, reg, (u32)data);
1427 }
1428
1429 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1430 {
1431         struct kvm_lapic *apic = vcpu->arch.apic;
1432         u32 low, high = 0;
1433
1434         if (!irqchip_in_kernel(vcpu->kvm))
1435                 return 1;
1436
1437         if (apic_reg_read(apic, reg, 4, &low))
1438                 return 1;
1439         if (reg == APIC_ICR)
1440                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1441
1442         *data = (((u64)high) << 32) | low;
1443
1444         return 0;
1445 }