2 * Copyright (C) 1995 Linus Torvalds
6 * This file handles the architecture-dependent parts of initialization
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/a.out.h>
19 #include <linux/screen_info.h>
20 #include <linux/ioport.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/initrd.h>
24 #include <linux/highmem.h>
25 #include <linux/bootmem.h>
26 #include <linux/module.h>
27 #include <asm/processor.h>
28 #include <linux/console.h>
29 #include <linux/seq_file.h>
30 #include <linux/crash_dump.h>
31 #include <linux/root_dev.h>
32 #include <linux/pci.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/mmzone.h>
38 #include <linux/kexec.h>
39 #include <linux/cpufreq.h>
40 #include <linux/dmi.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/ctype.h>
43 #include <linux/uaccess.h>
46 #include <asm/uaccess.h>
47 #include <asm/system.h>
48 #include <asm/vsyscall.h>
53 #include <video/edid.h>
57 #include <asm/mpspec.h>
58 #include <asm/mmu_context.h>
59 #include <asm/proto.h>
60 #include <asm/setup.h>
61 #include <asm/mach_apic.h>
63 #include <asm/sections.h>
65 #include <asm/cacheflush.h>
68 #include <asm/topology.h>
70 #ifdef CONFIG_PARAVIRT
71 #include <asm/paravirt.h>
80 struct cpuinfo_x86 boot_cpu_data __read_mostly;
81 EXPORT_SYMBOL(boot_cpu_data);
83 unsigned long mmu_cr4_features;
85 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
88 unsigned long saved_video_mode;
90 int force_mwait __cpuinitdata;
96 char dmi_alloc_data[DMI_MAX_DATA];
101 struct screen_info screen_info;
102 EXPORT_SYMBOL(screen_info);
103 struct sys_desc_table_struct {
104 unsigned short length;
105 unsigned char table[0];
108 struct edid_info edid_info;
109 EXPORT_SYMBOL_GPL(edid_info);
111 extern int root_mountflags;
113 char __initdata command_line[COMMAND_LINE_SIZE];
115 struct resource standard_io_resources[] = {
116 { .name = "dma1", .start = 0x00, .end = 0x1f,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "pic1", .start = 0x20, .end = 0x21,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "timer0", .start = 0x40, .end = 0x43,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "timer1", .start = 0x50, .end = 0x53,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "keyboard", .start = 0x60, .end = 0x6f,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
126 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
128 { .name = "pic2", .start = 0xa0, .end = 0xa1,
129 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
130 { .name = "dma2", .start = 0xc0, .end = 0xdf,
131 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
132 { .name = "fpu", .start = 0xf0, .end = 0xff,
133 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
136 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
138 static struct resource data_resource = {
139 .name = "Kernel data",
142 .flags = IORESOURCE_RAM,
144 static struct resource code_resource = {
145 .name = "Kernel code",
148 .flags = IORESOURCE_RAM,
150 static struct resource bss_resource = {
151 .name = "Kernel bss",
154 .flags = IORESOURCE_RAM,
157 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
159 #ifdef CONFIG_PROC_VMCORE
160 /* elfcorehdr= specifies the location of elf core header
161 * stored by the crashed kernel. This option will be passed
162 * by kexec loader to the capture kernel.
164 static int __init setup_elfcorehdr(char *arg)
169 elfcorehdr_addr = memparse(arg, &end);
170 return end > arg ? 0 : -EINVAL;
172 early_param("elfcorehdr", setup_elfcorehdr);
177 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
179 unsigned long bootmap_size, bootmap;
181 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
182 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
184 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
185 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
186 e820_register_active_regions(0, start_pfn, end_pfn);
187 free_bootmem_with_active_regions(0, end_pfn);
188 reserve_bootmem(bootmap, bootmap_size);
192 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
194 #ifdef CONFIG_EDD_MODULE
198 * copy_edd() - Copy the BIOS EDD information
199 * from boot_params into a safe place.
202 static inline void copy_edd(void)
204 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
205 sizeof(edd.mbr_signature));
206 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
207 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
208 edd.edd_info_nr = boot_params.eddbuf_entries;
211 static inline void copy_edd(void)
217 static void __init reserve_crashkernel(void)
219 unsigned long long free_mem;
220 unsigned long long crash_size, crash_base;
224 ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
226 ret = parse_crashkernel(boot_command_line, free_mem,
227 &crash_size, &crash_base);
228 if (ret == 0 && crash_size) {
229 if (crash_base > 0) {
230 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
231 "for crashkernel (System RAM: %ldMB)\n",
232 (unsigned long)(crash_size >> 20),
233 (unsigned long)(crash_base >> 20),
234 (unsigned long)(free_mem >> 20));
235 crashk_res.start = crash_base;
236 crashk_res.end = crash_base + crash_size - 1;
237 reserve_bootmem(crash_base, crash_size);
239 printk(KERN_INFO "crashkernel reservation failed - "
240 "you have to specify a base address\n");
244 static inline void __init reserve_crashkernel(void)
248 #define EBDA_ADDR_POINTER 0x40E
250 unsigned __initdata ebda_addr;
251 unsigned __initdata ebda_size;
253 static void __init discover_ebda(void)
256 * there is a real-mode segmented pointer pointing to the
257 * 4K EBDA area at 0x40E
259 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
261 * There can be some situations, like paravirtualized guests,
262 * in which there is no available ebda information. In such
272 ebda_size = *(unsigned short *)__va(ebda_addr);
274 /* Round EBDA up to pages */
278 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
279 if (ebda_size > 64*1024)
283 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
284 void __attribute__((weak)) __init memory_setup(void)
286 machine_specific_memory_setup();
289 void __init setup_arch(char **cmdline_p)
293 printk(KERN_INFO "Command line: %s\n", boot_command_line);
295 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
296 screen_info = boot_params.screen_info;
297 edid_info = boot_params.edid_info;
298 saved_video_mode = boot_params.hdr.vid_mode;
299 bootloader_type = boot_params.hdr.type_of_loader;
301 #ifdef CONFIG_BLK_DEV_RAM
302 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
303 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
304 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
307 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
317 if (!boot_params.hdr.root_flags)
318 root_mountflags &= ~MS_RDONLY;
319 init_mm.start_code = (unsigned long) &_text;
320 init_mm.end_code = (unsigned long) &_etext;
321 init_mm.end_data = (unsigned long) &_edata;
322 init_mm.brk = (unsigned long) &_end;
324 code_resource.start = virt_to_phys(&_text);
325 code_resource.end = virt_to_phys(&_etext)-1;
326 data_resource.start = virt_to_phys(&_etext);
327 data_resource.end = virt_to_phys(&_edata)-1;
328 bss_resource.start = virt_to_phys(&__bss_start);
329 bss_resource.end = virt_to_phys(&__bss_stop)-1;
331 early_identify_cpu(&boot_cpu_data);
333 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
334 *cmdline_p = command_line;
338 finish_e820_parsing();
340 early_gart_iommu_check();
342 e820_register_active_regions(0, 0, -1UL);
344 * partially used pages are not usable - thus
345 * we are rounding upwards:
347 end_pfn = e820_end_of_ram();
348 num_physpages = end_pfn;
354 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
363 /* setup to use the early static init tables during kernel startup */
364 x86_cpu_to_apicid_early_ptr = (void *)&x86_cpu_to_apicid_init;
365 x86_cpu_to_node_map_early_ptr = (void *)&x86_cpu_to_node_map_init;
370 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
371 * Call this early for SRAT node setup.
373 acpi_boot_table_init();
376 /* How many end-of-memory variables you have, grandma! */
377 max_low_pfn = end_pfn;
379 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
381 /* Remove active ranges so rediscovery with NUMA-awareness happens */
382 remove_all_active_ranges();
384 #ifdef CONFIG_ACPI_NUMA
386 * Parse SRAT to discover nodes.
392 numa_initmem_init(0, end_pfn);
394 contig_initmem_init(0, end_pfn);
397 /* Reserve direct mapping */
398 reserve_bootmem_generic(table_start << PAGE_SHIFT,
399 (table_end - table_start) << PAGE_SHIFT);
402 reserve_bootmem_generic(__pa_symbol(&_text),
403 __pa_symbol(&_end) - __pa_symbol(&_text));
406 * reserve physical page 0 - it's a special BIOS page on many boxes,
407 * enabling clean reboots, SMP operation, laptop functions.
409 reserve_bootmem_generic(0, PAGE_SIZE);
411 /* reserve ebda region */
413 reserve_bootmem_generic(ebda_addr, ebda_size);
415 /* reserve nodemap region */
417 reserve_bootmem_generic(nodemap_addr, nodemap_size);
421 /* Reserve SMP trampoline */
422 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
425 #ifdef CONFIG_ACPI_SLEEP
427 * Reserve low memory region for sleep support.
429 acpi_reserve_bootmem();
434 efi_reserve_bootmem();
438 * Find and reserve possible boot-time SMP configuration:
441 #ifdef CONFIG_BLK_DEV_INITRD
442 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
443 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
444 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
445 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
446 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
448 if (ramdisk_end <= end_of_mem) {
449 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
450 initrd_start = ramdisk_image + PAGE_OFFSET;
451 initrd_end = initrd_start+ramdisk_size;
453 printk(KERN_ERR "initrd extends beyond end of memory "
454 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
455 ramdisk_end, end_of_mem);
460 reserve_crashkernel();
467 * set this early, so we dont allocate cpu0
468 * if MADT list doesnt list BSP first
469 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
471 cpu_set(0, cpu_present_map);
474 * Read APIC and some other early information from ACPI tables.
482 * get boot-time SMP configuration:
484 if (smp_found_config)
486 init_apic_mappings();
487 ioapic_init_mappings();
490 * We trust e820 completely. No explicit ROM probing in memory.
492 e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
493 e820_mark_nosave_regions();
495 /* request I/O space for devices used on all i[345]86 PCs */
496 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
497 request_resource(&ioport_resource, &standard_io_resources[i]);
502 #if defined(CONFIG_VGA_CONSOLE)
503 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
504 conswitchp = &vga_con;
505 #elif defined(CONFIG_DUMMY_CONSOLE)
506 conswitchp = &dummy_con;
511 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
515 if (c->extended_cpuid_level < 0x80000004)
518 v = (unsigned int *) c->x86_model_id;
519 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
520 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
521 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
522 c->x86_model_id[48] = 0;
527 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
529 unsigned int n, dummy, eax, ebx, ecx, edx;
531 n = c->extended_cpuid_level;
533 if (n >= 0x80000005) {
534 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
535 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
536 "D cache %dK (%d bytes/line)\n",
537 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
538 c->x86_cache_size = (ecx>>24) + (edx>>24);
539 /* On K8 L1 TLB is inclusive, so don't count it */
543 if (n >= 0x80000006) {
544 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
545 ecx = cpuid_ecx(0x80000006);
546 c->x86_cache_size = ecx >> 16;
547 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
549 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
550 c->x86_cache_size, ecx & 0xFF);
552 if (n >= 0x80000008) {
553 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
554 c->x86_virt_bits = (eax >> 8) & 0xff;
555 c->x86_phys_bits = eax & 0xff;
560 static int nearby_node(int apicid)
564 for (i = apicid - 1; i >= 0; i--) {
565 node = apicid_to_node[i];
566 if (node != NUMA_NO_NODE && node_online(node))
569 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
570 node = apicid_to_node[i];
571 if (node != NUMA_NO_NODE && node_online(node))
574 return first_node(node_online_map); /* Shouldn't happen */
579 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
580 * Assumes number of cores is a power of two.
582 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
587 int cpu = smp_processor_id();
589 unsigned apicid = hard_smp_processor_id();
591 bits = c->x86_coreid_bits;
593 /* Low order bits define the core id (index of core in socket) */
594 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
595 /* Convert the APIC ID into the socket ID */
596 c->phys_proc_id = phys_pkg_id(bits);
599 node = c->phys_proc_id;
600 if (apicid_to_node[apicid] != NUMA_NO_NODE)
601 node = apicid_to_node[apicid];
602 if (!node_online(node)) {
603 /* Two possibilities here:
604 - The CPU is missing memory and no node was created.
605 In that case try picking one from a nearby CPU
606 - The APIC IDs differ from the HyperTransport node IDs
607 which the K8 northbridge parsing fills in.
608 Assume they are all increased by a constant offset,
609 but in the same order as the HT nodeids.
610 If that doesn't result in a usable node fall back to the
611 path for the previous case. */
613 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
615 if (ht_nodeid >= 0 &&
616 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
617 node = apicid_to_node[ht_nodeid];
618 /* Pick a nearby node */
619 if (!node_online(node))
620 node = nearby_node(apicid);
622 numa_set_node(cpu, node);
624 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
629 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
634 /* Multi core CPU? */
635 if (c->extended_cpuid_level < 0x80000008)
638 ecx = cpuid_ecx(0x80000008);
640 c->x86_max_cores = (ecx & 0xff) + 1;
642 /* CPU telling us the core id bits shift? */
643 bits = (ecx >> 12) & 0xF;
645 /* Otherwise recompute */
647 while ((1 << bits) < c->x86_max_cores)
651 c->x86_coreid_bits = bits;
656 #define ENABLE_C1E_MASK 0x18000000
657 #define CPUID_PROCESSOR_SIGNATURE 1
658 #define CPUID_XFAM 0x0ff00000
659 #define CPUID_XFAM_K8 0x00000000
660 #define CPUID_XFAM_10H 0x00100000
661 #define CPUID_XFAM_11H 0x00200000
662 #define CPUID_XMOD 0x000f0000
663 #define CPUID_XMOD_REV_F 0x00040000
665 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
666 static __cpuinit int amd_apic_timer_broken(void)
668 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
670 switch (eax & CPUID_XFAM) {
672 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
676 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
677 if (lo & ENABLE_C1E_MASK)
681 /* err on the side of caution */
687 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
689 early_init_amd_mc(c);
691 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
692 if (c->x86_power & (1<<8))
693 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
696 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
704 * Disable TLB flush filter by setting HWCR.FFDIS on K8
705 * bit 6 of msr C001_0015
707 * Errata 63 for SH-B3 steppings
708 * Errata 122 for all steppings (F+ have it disabled by default)
711 rdmsrl(MSR_K8_HWCR, value);
713 wrmsrl(MSR_K8_HWCR, value);
717 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
718 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
719 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
721 /* On C+ stepping K8 rep microcode works well for copy/memset */
722 level = cpuid_eax(1);
723 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
725 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
726 if (c->x86 == 0x10 || c->x86 == 0x11)
727 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
729 /* Enable workaround for FXSAVE leak */
731 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
733 level = get_model_name(c);
737 /* Should distinguish Models here, but this is only
738 a fallback anyways. */
739 strcpy(c->x86_model_id, "Hammer");
743 display_cacheinfo(c);
745 /* Multi core CPU? */
746 if (c->extended_cpuid_level >= 0x80000008)
749 if (c->extended_cpuid_level >= 0x80000006 &&
750 (cpuid_edx(0x80000006) & 0xf000))
751 num_cache_leaves = 4;
753 num_cache_leaves = 3;
755 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
756 set_cpu_cap(c, X86_FEATURE_K8);
758 /* MFENCE stops RDTSC speculation */
759 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
761 /* Family 10 doesn't support C states in MWAIT so don't use it */
762 if (c->x86 == 0x10 && !force_mwait)
763 clear_cpu_cap(c, X86_FEATURE_MWAIT);
765 if (amd_apic_timer_broken())
766 disable_apic_timer = 1;
769 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
772 u32 eax, ebx, ecx, edx;
773 int index_msb, core_bits;
775 cpuid(1, &eax, &ebx, &ecx, &edx);
778 if (!cpu_has(c, X86_FEATURE_HT))
780 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
783 smp_num_siblings = (ebx & 0xff0000) >> 16;
785 if (smp_num_siblings == 1) {
786 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
787 } else if (smp_num_siblings > 1) {
789 if (smp_num_siblings > NR_CPUS) {
790 printk(KERN_WARNING "CPU: Unsupported number of "
791 "siblings %d", smp_num_siblings);
792 smp_num_siblings = 1;
796 index_msb = get_count_order(smp_num_siblings);
797 c->phys_proc_id = phys_pkg_id(index_msb);
799 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
801 index_msb = get_count_order(smp_num_siblings);
803 core_bits = get_count_order(c->x86_max_cores);
805 c->cpu_core_id = phys_pkg_id(index_msb) &
806 ((1 << core_bits) - 1);
809 if ((c->x86_max_cores * smp_num_siblings) > 1) {
810 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
812 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
820 * find out the number of processor cores on the die
822 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
826 if (c->cpuid_level < 4)
829 cpuid_count(4, 0, &eax, &t, &t, &t);
832 return ((eax >> 26) + 1);
837 static void srat_detect_node(void)
841 int cpu = smp_processor_id();
842 int apicid = hard_smp_processor_id();
844 /* Don't do the funky fallback heuristics the AMD version employs
846 node = apicid_to_node[apicid];
847 if (node == NUMA_NO_NODE)
848 node = first_node(node_online_map);
849 numa_set_node(cpu, node);
851 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
855 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
857 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
858 (c->x86 == 0x6 && c->x86_model >= 0x0e))
859 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
862 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
867 init_intel_cacheinfo(c);
868 if (c->cpuid_level > 9) {
869 unsigned eax = cpuid_eax(10);
870 /* Check for version and the number of counters */
871 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
872 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
877 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
879 set_cpu_cap(c, X86_FEATURE_BTS);
881 set_cpu_cap(c, X86_FEATURE_PEBS);
888 n = c->extended_cpuid_level;
889 if (n >= 0x80000008) {
890 unsigned eax = cpuid_eax(0x80000008);
891 c->x86_virt_bits = (eax >> 8) & 0xff;
892 c->x86_phys_bits = eax & 0xff;
893 /* CPUID workaround for Intel 0F34 CPU */
894 if (c->x86_vendor == X86_VENDOR_INTEL &&
895 c->x86 == 0xF && c->x86_model == 0x3 &&
897 c->x86_phys_bits = 36;
901 c->x86_cache_alignment = c->x86_clflush_size * 2;
902 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
903 (c->x86 == 0x6 && c->x86_model >= 0x0e))
904 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
906 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
907 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
908 c->x86_max_cores = intel_num_cpu_cores(c);
913 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
915 char *v = c->x86_vendor_id;
917 if (!strcmp(v, "AuthenticAMD"))
918 c->x86_vendor = X86_VENDOR_AMD;
919 else if (!strcmp(v, "GenuineIntel"))
920 c->x86_vendor = X86_VENDOR_INTEL;
922 c->x86_vendor = X86_VENDOR_UNKNOWN;
925 struct cpu_model_info {
928 char *model_names[16];
931 /* Do some early cpuid on the boot CPU to get some parameter that are
932 needed before check_bugs. Everything advanced is in identify_cpu
934 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
938 c->loops_per_jiffy = loops_per_jiffy;
939 c->x86_cache_size = -1;
940 c->x86_vendor = X86_VENDOR_UNKNOWN;
941 c->x86_model = c->x86_mask = 0; /* So far unknown... */
942 c->x86_vendor_id[0] = '\0'; /* Unset */
943 c->x86_model_id[0] = '\0'; /* Unset */
944 c->x86_clflush_size = 64;
945 c->x86_cache_alignment = c->x86_clflush_size;
946 c->x86_max_cores = 1;
947 c->x86_coreid_bits = 0;
948 c->extended_cpuid_level = 0;
949 memset(&c->x86_capability, 0, sizeof c->x86_capability);
951 /* Get vendor name */
952 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
953 (unsigned int *)&c->x86_vendor_id[0],
954 (unsigned int *)&c->x86_vendor_id[8],
955 (unsigned int *)&c->x86_vendor_id[4]);
959 /* Initialize the standard set of capabilities */
960 /* Note that the vendor-specific code below might override */
962 /* Intel-defined flags: level 0x00000001 */
963 if (c->cpuid_level >= 0x00000001) {
965 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
966 &c->x86_capability[0]);
967 c->x86 = (tfms >> 8) & 0xf;
968 c->x86_model = (tfms >> 4) & 0xf;
969 c->x86_mask = tfms & 0xf;
971 c->x86 += (tfms >> 20) & 0xff;
973 c->x86_model += ((tfms >> 16) & 0xF) << 4;
974 if (c->x86_capability[0] & (1<<19))
975 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
977 /* Have CPUID level 0 only - unheard of */
982 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
984 /* AMD-defined flags: level 0x80000001 */
985 xlvl = cpuid_eax(0x80000000);
986 c->extended_cpuid_level = xlvl;
987 if ((xlvl & 0xffff0000) == 0x80000000) {
988 if (xlvl >= 0x80000001) {
989 c->x86_capability[1] = cpuid_edx(0x80000001);
990 c->x86_capability[6] = cpuid_ecx(0x80000001);
992 if (xlvl >= 0x80000004)
993 get_model_name(c); /* Default name */
996 /* Transmeta-defined flags: level 0x80860001 */
997 xlvl = cpuid_eax(0x80860000);
998 if ((xlvl & 0xffff0000) == 0x80860000) {
999 /* Don't set x86_cpuid_level here for now to not confuse. */
1000 if (xlvl >= 0x80860001)
1001 c->x86_capability[2] = cpuid_edx(0x80860001);
1004 c->extended_cpuid_level = cpuid_eax(0x80000000);
1005 if (c->extended_cpuid_level >= 0x80000007)
1006 c->x86_power = cpuid_edx(0x80000007);
1008 switch (c->x86_vendor) {
1009 case X86_VENDOR_AMD:
1017 * This does the hard work of actually picking apart the CPU stuff...
1019 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1023 early_identify_cpu(c);
1025 init_scattered_cpuid_features(c);
1027 c->apicid = phys_pkg_id(0);
1030 * Vendor-specific initialization. In this section we
1031 * canonicalize the feature flags, meaning if there are
1032 * features a certain CPU supports which CPUID doesn't
1033 * tell us, CPUID claiming incorrect flags, or other bugs,
1034 * we handle them here.
1036 * At the end of this section, c->x86_capability better
1037 * indicate the features this CPU genuinely supports!
1039 switch (c->x86_vendor) {
1040 case X86_VENDOR_AMD:
1044 case X86_VENDOR_INTEL:
1048 case X86_VENDOR_UNKNOWN:
1050 display_cacheinfo(c);
1054 select_idle_routine(c);
1058 * On SMP, boot_cpu_data holds the common feature set between
1059 * all CPUs; so make sure that we indicate which features are
1060 * common between the CPUs. The first time this routine gets
1061 * executed, c == &boot_cpu_data.
1063 if (c != &boot_cpu_data) {
1064 /* AND the already accumulated flags with these */
1065 for (i = 0; i < NCAPINTS; i++)
1066 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1069 #ifdef CONFIG_X86_MCE
1072 if (c != &boot_cpu_data)
1075 numa_add_cpu(smp_processor_id());
1078 switch (c->x86_vendor) {
1079 case X86_VENDOR_AMD:
1082 case X86_VENDOR_INTEL:
1083 early_init_intel(c);
1088 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1090 if (c->x86_model_id[0])
1091 printk(KERN_INFO "%s", c->x86_model_id);
1093 if (c->x86_mask || c->cpuid_level >= 0)
1094 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1096 printk(KERN_CONT "\n");
1100 * Get CPU information for use by the procfs.
1103 static int show_cpuinfo(struct seq_file *m, void *v)
1105 struct cpuinfo_x86 *c = v;
1109 * These flag bits must match the definitions in <asm/cpufeature.h>.
1110 * NULL means this bit is undefined or reserved; either way it doesn't
1111 * have meaning as far as Linux is concerned. Note that it's important
1112 * to realize there is a difference between this table and CPUID -- if
1113 * applications want to get the raw CPUID data, they should access
1114 * /dev/cpu/<cpu_nr>/cpuid instead.
1116 static const char *const x86_cap_flags[] = {
1118 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1119 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1120 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1121 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
1124 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1125 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1126 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1127 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
1128 "3dnowext", "3dnow",
1130 /* Transmeta-defined */
1131 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1136 /* Other (Linux-defined) */
1137 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
1138 NULL, NULL, NULL, NULL,
1139 "constant_tsc", "up", NULL, "arch_perfmon",
1140 "pebs", "bts", NULL, "sync_rdtsc",
1141 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1142 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1144 /* Intel-defined (#2) */
1145 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1146 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1147 NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
1148 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1150 /* VIA/Cyrix/Centaur-defined */
1151 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1152 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1153 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1156 /* AMD-defined (#2) */
1157 "lahf_lm", "cmp_legacy", "svm", "extapic",
1158 "cr8_legacy", "abm", "sse4a", "misalignsse",
1159 "3dnowprefetch", "osvw", "ibs", "sse5",
1160 "skinit", "wdt", NULL, NULL,
1161 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1162 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1164 /* Auxiliary (Linux-defined) */
1165 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1166 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1167 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1168 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1170 static const char *const x86_power_flags[] = {
1171 "ts", /* temperature sensor */
1172 "fid", /* frequency id control */
1173 "vid", /* voltage id control */
1174 "ttp", /* thermal trip */
1179 "", /* tsc invariant mapped to constant_tsc */
1188 seq_printf(m, "processor\t: %u\n"
1190 "cpu family\t: %d\n"
1192 "model name\t: %s\n",
1194 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1197 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1199 if (c->x86_mask || c->cpuid_level >= 0)
1200 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1202 seq_printf(m, "stepping\t: unknown\n");
1204 if (cpu_has(c, X86_FEATURE_TSC)) {
1205 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
1209 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1210 freq / 1000, (freq % 1000));
1214 if (c->x86_cache_size >= 0)
1215 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1218 if (smp_num_siblings * c->x86_max_cores > 1) {
1219 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1220 seq_printf(m, "siblings\t: %d\n",
1221 cpus_weight(per_cpu(cpu_core_map, cpu)));
1222 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1223 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1229 "fpu_exception\t: yes\n"
1230 "cpuid level\t: %d\n"
1235 for (i = 0; i < 32*NCAPINTS; i++)
1236 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1237 seq_printf(m, " %s", x86_cap_flags[i]);
1239 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1240 c->loops_per_jiffy/(500000/HZ),
1241 (c->loops_per_jiffy/(5000/HZ)) % 100);
1243 if (c->x86_tlbsize > 0)
1244 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1245 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1246 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1248 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1249 c->x86_phys_bits, c->x86_virt_bits);
1251 seq_printf(m, "power management:");
1252 for (i = 0; i < 32; i++) {
1253 if (c->x86_power & (1 << i)) {
1254 if (i < ARRAY_SIZE(x86_power_flags) &&
1256 seq_printf(m, "%s%s",
1257 x86_power_flags[i][0]?" ":"",
1258 x86_power_flags[i]);
1260 seq_printf(m, " [%d]", i);
1264 seq_printf(m, "\n\n");
1269 static void *c_start(struct seq_file *m, loff_t *pos)
1271 if (*pos == 0) /* just in case, cpu 0 is not the first */
1272 *pos = first_cpu(cpu_online_map);
1273 if ((*pos) < NR_CPUS && cpu_online(*pos))
1274 return &cpu_data(*pos);
1278 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1280 *pos = next_cpu(*pos, cpu_online_map);
1281 return c_start(m, pos);
1284 static void c_stop(struct seq_file *m, void *v)
1288 struct seq_operations cpuinfo_op = {
1292 .show = show_cpuinfo,