Pileus Git - ~andy/linux/blob - arch/x86/kernel/devicetree.c

   1 /*
   2  * Architecture specific OF callbacks.
   3  */
   4 #include <linux/bootmem.h>
   5 #include <linux/export.h>
   6 #include <linux/io.h>
   7 #include <linux/irqdomain.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/list.h>
  10 #include <linux/of.h>
  11 #include <linux/of_fdt.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/slab.h>
  16 #include <linux/pci.h>
  17 #include <linux/of_pci.h>
  18 #include <linux/initrd.h>
  19
  20 #include <asm/hpet.h>
  21 #include <asm/apic.h>
  22 #include <asm/pci_x86.h>
  23 #include <asm/setup.h>
  24
  25 __initdata u64 initial_dtb;
  26 char __initdata cmd_line[COMMAND_LINE_SIZE];
  27
  28 int __initdata of_ioapic;
  29
  30 void __init early_init_dt_scan_chosen_arch(unsigned long node)
  31 {
  32         BUG();
  33 }
  34
  35 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
  36 {
  37         BUG();
  38 }
  39
  40 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
  41 {
  42         return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
  43 }
  44
  45 void __init add_dtb(u64 data)
  46 {
  47         initial_dtb = data + offsetof(struct setup_data, data);
  48 }
  49
  50 /*
  51  * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
  52  */
  53 static struct of_device_id __initdata ce4100_ids[] = {
  54         { .compatible = "intel,ce4100-cp", },
  55         { .compatible = "isa", },
  56         { .compatible = "pci", },
  57         {},
  58 };
  59
  60 static int __init add_bus_probe(void)
  61 {
  62         if (!of_have_populated_dt())
  63                 return 0;
  64
  65         return of_platform_bus_probe(NULL, ce4100_ids, NULL);
  66 }
  67 module_init(add_bus_probe);
  68
  69 #ifdef CONFIG_PCI
  70 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
  71 {
  72         struct device_node *np;
  73
  74         for_each_node_by_type(np, "pci") {
  75                 const void *prop;
  76                 unsigned int bus_min;
  77
  78                 prop = of_get_property(np, "bus-range", NULL);
  79                 if (!prop)
  80                         continue;
  81                 bus_min = be32_to_cpup(prop);
  82                 if (bus->number == bus_min)
  83                         return np;
  84         }
  85         return NULL;
  86 }
  87
  88 static int x86_of_pci_irq_enable(struct pci_dev *dev)
  89 {
  90         u32 virq;
  91         int ret;
  92         u8 pin;
  93
  94         ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
  95         if (ret)
  96                 return ret;
  97         if (!pin)
  98                 return 0;
  99
 100         virq = of_irq_parse_and_map_pci(dev, 0, 0);
 101         if (virq == 0)
 102                 return -EINVAL;
 103         dev->irq = virq;
 104         return 0;
 105 }
 106
 107 static void x86_of_pci_irq_disable(struct pci_dev *dev)
 108 {
 109 }
 110
 111 void x86_of_pci_init(void)
 112 {
 113         pcibios_enable_irq = x86_of_pci_irq_enable;
 114         pcibios_disable_irq = x86_of_pci_irq_disable;
 115 }
 116 #endif
 117
 118 static void __init dtb_setup_hpet(void)
 119 {
 120 #ifdef CONFIG_HPET_TIMER
 121         struct device_node *dn;
 122         struct resource r;
 123         int ret;
 124
 125         dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
 126         if (!dn)
 127                 return;
 128         ret = of_address_to_resource(dn, 0, &r);
 129         if (ret) {
 130                 WARN_ON(1);
 131                 return;
 132         }
 133         hpet_address = r.start;
 134 #endif
 135 }
 136
 137 static void __init dtb_lapic_setup(void)
 138 {
 139 #ifdef CONFIG_X86_LOCAL_APIC
 140         struct device_node *dn;
 141         struct resource r;
 142         int ret;
 143
 144         dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
 145         if (!dn)
 146                 return;
 147
 148         ret = of_address_to_resource(dn, 0, &r);
 149         if (WARN_ON(ret))
 150                 return;
 151
 152         /* Did the boot loader setup the local APIC ? */
 153         if (!cpu_has_apic) {
 154                 if (apic_force_enable(r.start))
 155                         return;
 156         }
 157         smp_found_config = 1;
 158         pic_mode = 1;
 159         register_lapic_address(r.start);
 160         generic_processor_info(boot_cpu_physical_apicid,
 161                                GET_APIC_VERSION(apic_read(APIC_LVR)));
 162 #endif
 163 }
 164
 165 #ifdef CONFIG_X86_IO_APIC
 166 static unsigned int ioapic_id;
 167
 168 static void __init dtb_add_ioapic(struct device_node *dn)
 169 {
 170         struct resource r;
 171         int ret;
 172
 173         ret = of_address_to_resource(dn, 0, &r);
 174         if (ret) {
 175                 printk(KERN_ERR "Can't obtain address from node %s.\n",
 176                                 dn->full_name);
 177                 return;
 178         }
 179         mp_register_ioapic(++ioapic_id, r.start, gsi_top);
 180 }
 181
 182 static void __init dtb_ioapic_setup(void)
 183 {
 184         struct device_node *dn;
 185
 186         for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
 187                 dtb_add_ioapic(dn);
 188
 189         if (nr_ioapics) {
 190                 of_ioapic = 1;
 191                 return;
 192         }
 193         printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
 194 }
 195 #else
 196 static void __init dtb_ioapic_setup(void) {}
 197 #endif
 198
 199 static void __init dtb_apic_setup(void)
 200 {
 201         dtb_lapic_setup();
 202         dtb_ioapic_setup();
 203 }
 204
 205 #ifdef CONFIG_OF_FLATTREE
 206 static void __init x86_flattree_get_config(void)
 207 {
 208         u32 size, map_len;
 209         struct boot_param_header *dt;
 210
 211         if (!initial_dtb)
 212                 return;
 213
 214         map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK),
 215                         (u64)sizeof(struct boot_param_header));
 216
 217         dt = early_memremap(initial_dtb, map_len);
 218         size = be32_to_cpu(dt->totalsize);
 219         if (map_len < size) {
 220                 early_iounmap(dt, map_len);
 221                 dt = early_memremap(initial_dtb, size);
 222                 map_len = size;
 223         }
 224
 225         initial_boot_params = dt;
 226         unflatten_and_copy_device_tree();
 227         early_iounmap(dt, map_len);
 228 }
 229 #else
 230 static inline void x86_flattree_get_config(void) { }
 231 #endif
 232
 233 void __init x86_dtb_init(void)
 234 {
 235         x86_flattree_get_config();
 236
 237         if (!of_have_populated_dt())
 238                 return;
 239
 240         dtb_setup_hpet();
 241         dtb_apic_setup();
 242 }
 243
 244 #ifdef CONFIG_X86_IO_APIC
 245
 246 struct of_ioapic_type {
 247         u32 out_type;
 248         u32 trigger;
 249         u32 polarity;
 250 };
 251
 252 static struct of_ioapic_type of_ioapic_type[] =
 253 {
 254         {
 255                 .out_type       = IRQ_TYPE_EDGE_RISING,
 256                 .trigger        = IOAPIC_EDGE,
 257                 .polarity       = 1,
 258         },
 259         {
 260                 .out_type       = IRQ_TYPE_LEVEL_LOW,
 261                 .trigger        = IOAPIC_LEVEL,
 262                 .polarity       = 0,
 263         },
 264         {
 265                 .out_type       = IRQ_TYPE_LEVEL_HIGH,
 266                 .trigger        = IOAPIC_LEVEL,
 267                 .polarity       = 1,
 268         },
 269         {
 270                 .out_type       = IRQ_TYPE_EDGE_FALLING,
 271                 .trigger        = IOAPIC_EDGE,
 272                 .polarity       = 0,
 273         },
 274 };
 275
 276 static int ioapic_xlate(struct irq_domain *domain,
 277                         struct device_node *controller,
 278                         const u32 *intspec, u32 intsize,
 279                         irq_hw_number_t *out_hwirq, u32 *out_type)
 280 {
 281         struct io_apic_irq_attr attr;
 282         struct of_ioapic_type *it;
 283         u32 line, idx;
 284         int rc;
 285
 286         if (WARN_ON(intsize < 2))
 287                 return -EINVAL;
 288
 289         line = intspec[0];
 290
 291         if (intspec[1] >= ARRAY_SIZE(of_ioapic_type))
 292                 return -EINVAL;
 293
 294         it = &of_ioapic_type[intspec[1]];
 295
 296         idx = (u32) domain->host_data;
 297         set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
 298
 299         rc = io_apic_setup_irq_pin_once(irq_find_mapping(domain, line),
 300                                         cpu_to_node(0), &attr);
 301         if (rc)
 302                 return rc;
 303
 304         *out_hwirq = line;
 305         *out_type = it->out_type;
 306         return 0;
 307 }
 308
 309 const struct irq_domain_ops ioapic_irq_domain_ops = {
 310         .xlate = ioapic_xlate,
 311 };
 312
 313 static void dt_add_ioapic_domain(unsigned int ioapic_num,
 314                 struct device_node *np)
 315 {
 316         struct irq_domain *id;
 317         struct mp_ioapic_gsi *gsi_cfg;
 318         int ret;
 319         int num;
 320
 321         gsi_cfg = mp_ioapic_gsi_routing(ioapic_num);
 322         num = gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
 323
 324         id = irq_domain_add_linear(np, num, &ioapic_irq_domain_ops,
 325                         (void *)ioapic_num);
 326         BUG_ON(!id);
 327         if (gsi_cfg->gsi_base == 0) {
 328                 /*
 329                  * The first NR_IRQS_LEGACY irq descs are allocated in
 330                  * early_irq_init() and need just a mapping. The
 331                  * remaining irqs need both. All of them are preallocated
 332                  * and assigned so we can keep the 1:1 mapping which the ioapic
 333                  * is having.
 334                  */
 335                 irq_domain_associate_many(id, 0, 0, NR_IRQS_LEGACY);
 336
 337                 if (num > NR_IRQS_LEGACY) {
 338                         ret = irq_create_strict_mappings(id, NR_IRQS_LEGACY,
 339                                         NR_IRQS_LEGACY, num - NR_IRQS_LEGACY);
 340                         if (ret)
 341                                 pr_err("Error creating mapping for the "
 342                                                 "remaining IRQs: %d\n", ret);
 343                 }
 344                 irq_set_default_host(id);
 345         } else {
 346                 ret = irq_create_strict_mappings(id, gsi_cfg->gsi_base, 0, num);
 347                 if (ret)
 348                         pr_err("Error creating IRQ mapping: %d\n", ret);
 349         }
 350 }
 351
 352 static void __init ioapic_add_ofnode(struct device_node *np)
 353 {
 354         struct resource r;
 355         int i, ret;
 356
 357         ret = of_address_to_resource(np, 0, &r);
 358         if (ret) {
 359                 printk(KERN_ERR "Failed to obtain address for %s\n",
 360                                 np->full_name);
 361                 return;
 362         }
 363
 364         for (i = 0; i < nr_ioapics; i++) {
 365                 if (r.start == mpc_ioapic_addr(i)) {
 366                         dt_add_ioapic_domain(i, np);
 367                         return;
 368                 }
 369         }
 370         printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
 371 }
 372
 373 void __init x86_add_irq_domains(void)
 374 {
 375         struct device_node *dp;
 376
 377         if (!of_have_populated_dt())
 378                 return;
 379
 380         for_each_node_with_property(dp, "interrupt-controller") {
 381                 if (of_device_is_compatible(dp, "intel,ce4100-ioapic"))
 382                         ioapic_add_ofnode(dp);
 383         }
 384 }
 385 #else
 386 void __init x86_add_irq_domains(void) { }
 387 #endif