Pileus Git - ~andy/linux/blob - arch/x86/kernel/apic/summit_32.c

   1 /*
   2  * IBM Summit-Specific Code
   3  *
   4  * Written By: Matthew Dobson, IBM Corporation
   5  *
   6  * Copyright (c) 2003 IBM Corp.
   7  *
   8  * All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or (at
  13  * your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  18  * NON INFRINGEMENT.  See the GNU General Public License for more
  19  * details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  * Send feedback to <colpatch@us.ibm.com>
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) "summit: %s: " fmt, __func__
  30
  31 #include <linux/mm.h>
  32 #include <linux/init.h>
  33 #include <asm/io.h>
  34 #include <asm/bios_ebda.h>
  35
  36 /*
  37  * APIC driver for the IBM "Summit" chipset.
  38  */
  39 #include <linux/threads.h>
  40 #include <linux/cpumask.h>
  41 #include <asm/mpspec.h>
  42 #include <asm/apic.h>
  43 #include <asm/smp.h>
  44 #include <asm/fixmap.h>
  45 #include <asm/apicdef.h>
  46 #include <asm/ipi.h>
  47 #include <linux/kernel.h>
  48 #include <linux/string.h>
  49 #include <linux/gfp.h>
  50 #include <linux/smp.h>
  51
  52 static unsigned summit_get_apic_id(unsigned long x)
  53 {
  54         return (x >> 24) & 0xFF;
  55 }
  56
  57 static inline void summit_send_IPI_mask(const struct cpumask *mask, int vector)
  58 {
  59         default_send_IPI_mask_sequence_logical(mask, vector);
  60 }
  61
  62 static void summit_send_IPI_allbutself(int vector)
  63 {
  64         default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
  65 }
  66
  67 static void summit_send_IPI_all(int vector)
  68 {
  69         summit_send_IPI_mask(cpu_online_mask, vector);
  70 }
  71
  72 #include <asm/tsc.h>
  73
  74 extern int use_cyclone;
  75
  76 #ifdef CONFIG_X86_SUMMIT_NUMA
  77 static void setup_summit(void);
  78 #else
  79 static inline void setup_summit(void) {}
  80 #endif
  81
  82 static int summit_mps_oem_check(struct mpc_table *mpc, char *oem,
  83                 char *productid)
  84 {
  85         if (!strncmp(oem, "IBM ENSW", 8) &&
  86                         (!strncmp(productid, "VIGIL SMP", 9)
  87                          || !strncmp(productid, "EXA", 3)
  88                          || !strncmp(productid, "RUTHLESS SMP", 12))){
  89                 mark_tsc_unstable("Summit based system");
  90                 use_cyclone = 1; /*enable cyclone-timer*/
  91                 setup_summit();
  92                 return 1;
  93         }
  94         return 0;
  95 }
  96
  97 /* Hook from generic ACPI tables.c */
  98 static int summit_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  99 {
 100         if (!strncmp(oem_id, "IBM", 3) &&
 101             (!strncmp(oem_table_id, "SERVIGIL", 8)
 102              || !strncmp(oem_table_id, "EXA", 3))){
 103                 mark_tsc_unstable("Summit based system");
 104                 use_cyclone = 1; /*enable cyclone-timer*/
 105                 setup_summit();
 106                 return 1;
 107         }
 108         return 0;
 109 }
 110
 111 struct rio_table_hdr {
 112         unsigned char version;      /* Version number of this data structure           */
 113                                     /* Version 3 adds chassis_num & WP_index           */
 114         unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil)   */
 115         unsigned char num_rio_dev;  /* # of RIO I/O devices (Cyclones and Winnipegs)   */
 116 } __attribute__((packed));
 117
 118 struct scal_detail {
 119         unsigned char node_id;      /* Scalability Node ID                             */
 120         unsigned long CBAR;         /* Address of 1MB register space                   */
 121         unsigned char port0node;    /* Node ID port connected to: 0xFF=None            */
 122         unsigned char port0port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 123         unsigned char port1node;    /* Node ID port connected to: 0xFF = None          */
 124         unsigned char port1port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 125         unsigned char port2node;    /* Node ID port connected to: 0xFF = None          */
 126         unsigned char port2port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 127         unsigned char chassis_num;  /* 1 based Chassis number (1 = boot node)          */
 128 } __attribute__((packed));
 129
 130 struct rio_detail {
 131         unsigned char node_id;      /* RIO Node ID                                     */
 132         unsigned long BBAR;         /* Address of 1MB register space                   */
 133         unsigned char type;         /* Type of device                                  */
 134         unsigned char owner_id;     /* For WPEG: Node ID of Cyclone that owns this WPEG*/
 135                                     /* For CYC:  Node ID of Twister that owns this CYC */
 136         unsigned char port0node;    /* Node ID port connected to: 0xFF=None            */
 137         unsigned char port0port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 138         unsigned char port1node;    /* Node ID port connected to: 0xFF=None            */
 139         unsigned char port1port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 140         unsigned char first_slot;   /* For WPEG: Lowest slot number below this WPEG    */
 141                                     /* For CYC:  0                                     */
 142         unsigned char status;       /* For WPEG: Bit 0 = 1 : the XAPIC is used         */
 143                                     /*                 = 0 : the XAPIC is not used, ie:*/
 144                                     /*                     ints fwded to another XAPIC */
 145                                     /*           Bits1:7 Reserved                      */
 146                                     /* For CYC:  Bits0:7 Reserved                      */
 147         unsigned char WP_index;     /* For WPEG: WPEG instance index - lower ones have */
 148                                     /*           lower slot numbers/PCI bus numbers    */
 149                                     /* For CYC:  No meaning                            */
 150         unsigned char chassis_num;  /* 1 based Chassis number                          */
 151                                     /* For LookOut WPEGs this field indicates the      */
 152                                     /* Expansion Chassis #, enumerated from Boot       */
 153                                     /* Node WPEG external port, then Boot Node CYC     */
 154                                     /* external port, then Next Vigil chassis WPEG     */
 155                                     /* external port, etc.                             */
 156                                     /* Shared Lookouts have only 1 chassis number (the */
 157                                     /* first one assigned)                             */
 158 } __attribute__((packed));
 159
 160
 161 typedef enum {
 162         CompatTwister = 0,  /* Compatibility Twister               */
 163         AltTwister    = 1,  /* Alternate Twister of internal 8-way */
 164         CompatCyclone = 2,  /* Compatibility Cyclone               */
 165         AltCyclone    = 3,  /* Alternate Cyclone of internal 8-way */
 166         CompatWPEG    = 4,  /* Compatibility WPEG                  */
 167         AltWPEG       = 5,  /* Second Planar WPEG                  */
 168         LookOutAWPEG  = 6,  /* LookOut WPEG                        */
 169         LookOutBWPEG  = 7,  /* LookOut WPEG                        */
 170 } node_type;
 171
 172 static inline int is_WPEG(struct rio_detail *rio){
 173         return (rio->type == CompatWPEG || rio->type == AltWPEG ||
 174                 rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
 175 }
 176
 177 #define SUMMIT_APIC_DFR_VALUE   (APIC_DFR_CLUSTER)
 178
 179 static const struct cpumask *summit_target_cpus(void)
 180 {
 181         /* CPU_MASK_ALL (0xff) has undefined behaviour with
 182          * dest_LowestPrio mode logical clustered apic interrupt routing
 183          * Just start on cpu 0.  IRQ balancing will spread load
 184          */
 185         return cpumask_of(0);
 186 }
 187
 188 static unsigned long summit_check_apicid_used(physid_mask_t *map, int apicid)
 189 {
 190         return 0;
 191 }
 192
 193 /* we don't use the phys_cpu_present_map to indicate apicid presence */
 194 static unsigned long summit_check_apicid_present(int bit)
 195 {
 196         return 1;
 197 }
 198
 199 static int summit_early_logical_apicid(int cpu)
 200 {
 201         int count = 0;
 202         u8 my_id = early_per_cpu(x86_cpu_to_apicid, cpu);
 203         u8 my_cluster = APIC_CLUSTER(my_id);
 204 #ifdef CONFIG_SMP
 205         u8 lid;
 206         int i;
 207
 208         /* Create logical APIC IDs by counting CPUs already in cluster. */
 209         for (count = 0, i = nr_cpu_ids; --i >= 0; ) {
 210                 lid = early_per_cpu(x86_cpu_to_logical_apicid, i);
 211                 if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster)
 212                         ++count;
 213         }
 214 #endif
 215         /* We only have a 4 wide bitmap in cluster mode.  If a deranged
 216          * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
 217         BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
 218         return my_cluster | (1UL << count);
 219 }
 220
 221 static void summit_init_apic_ldr(void)
 222 {
 223         int cpu = smp_processor_id();
 224         unsigned long id = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
 225         unsigned long val;
 226
 227         apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE);
 228         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
 229         val |= SET_APIC_LOGICAL_ID(id);
 230         apic_write(APIC_LDR, val);
 231 }
 232
 233 static int summit_apic_id_registered(void)
 234 {
 235         return 1;
 236 }
 237
 238 static void summit_setup_apic_routing(void)
 239 {
 240         pr_info("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
 241                 nr_ioapics);
 242 }
 243
 244 static int summit_cpu_present_to_apicid(int mps_cpu)
 245 {
 246         if (mps_cpu < nr_cpu_ids)
 247                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 248         else
 249                 return BAD_APICID;
 250 }
 251
 252 static void summit_ioapic_phys_id_map(physid_mask_t *phys_id_map, physid_mask_t *retmap)
 253 {
 254         /* For clustered we don't have a good way to do this yet - hack */
 255         physids_promote(0x0FL, retmap);
 256 }
 257
 258 static void summit_apicid_to_cpu_present(int apicid, physid_mask_t *retmap)
 259 {
 260         physid_set_mask_of_physid(0, retmap);
 261 }
 262
 263 static int summit_check_phys_apicid_present(int physical_apicid)
 264 {
 265         return 1;
 266 }
 267
 268 static unsigned int summit_cpu_mask_to_apicid(const struct cpumask *cpumask)
 269 {
 270         unsigned int round = 0;
 271         int cpu, apicid = 0;
 272
 273         /*
 274          * The cpus in the mask must all be on the apic cluster.
 275          */
 276         for_each_cpu(cpu, cpumask) {
 277                 int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
 278
 279                 if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
 280                         pr_err("Not a valid mask!\n");
 281                         return BAD_APICID;
 282                 }
 283                 apicid |= new_apicid;
 284                 round++;
 285         }
 286         return apicid;
 287 }
 288
 289 static unsigned int summit_cpu_mask_to_apicid_and(const struct cpumask *inmask,
 290                               const struct cpumask *andmask)
 291 {
 292         int apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0);
 293         cpumask_var_t cpumask;
 294
 295         if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
 296                 return apicid;
 297
 298         cpumask_and(cpumask, inmask, andmask);
 299         cpumask_and(cpumask, cpumask, cpu_online_mask);
 300         apicid = summit_cpu_mask_to_apicid(cpumask);
 301
 302         free_cpumask_var(cpumask);
 303
 304         return apicid;
 305 }
 306
 307 /*
 308  * cpuid returns the value latched in the HW at reset, not the APIC ID
 309  * register's value.  For any box whose BIOS changes APIC IDs, like
 310  * clustered APIC systems, we must use hard_smp_processor_id.
 311  *
 312  * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
 313  */
 314 static int summit_phys_pkg_id(int cpuid_apic, int index_msb)
 315 {
 316         return hard_smp_processor_id() >> index_msb;
 317 }
 318
 319 static int probe_summit(void)
 320 {
 321         /* probed later in mptable/ACPI hooks */
 322         return 0;
 323 }
 324
 325 static void summit_vector_allocation_domain(int cpu, struct cpumask *retmask)
 326 {
 327         /* Careful. Some cpus do not strictly honor the set of cpus
 328          * specified in the interrupt destination when using lowest
 329          * priority interrupt delivery mode.
 330          *
 331          * In particular there was a hyperthreading cpu observed to
 332          * deliver interrupts to the wrong hyperthread when only one
 333          * hyperthread was specified in the interrupt desitination.
 334          */
 335         cpumask_clear(retmask);
 336         cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
 337 }
 338
 339 #ifdef CONFIG_X86_SUMMIT_NUMA
 340 static struct rio_table_hdr *rio_table_hdr;
 341 static struct scal_detail   *scal_devs[MAX_NUMNODES];
 342 static struct rio_detail    *rio_devs[MAX_NUMNODES*4];
 343
 344 #ifndef CONFIG_X86_NUMAQ
 345 static int mp_bus_id_to_node[MAX_MP_BUSSES];
 346 #endif
 347
 348 static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus)
 349 {
 350         int twister = 0, node = 0;
 351         int i, bus, num_buses;
 352
 353         for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
 354                 if (rio_devs[i]->node_id == rio_devs[wpeg_num]->owner_id) {
 355                         twister = rio_devs[i]->owner_id;
 356                         break;
 357                 }
 358         }
 359         if (i == rio_table_hdr->num_rio_dev) {
 360                 pr_err("Couldn't find owner Cyclone for Winnipeg!\n");
 361                 return last_bus;
 362         }
 363
 364         for (i = 0; i < rio_table_hdr->num_scal_dev; i++) {
 365                 if (scal_devs[i]->node_id == twister) {
 366                         node = scal_devs[i]->node_id;
 367                         break;
 368                 }
 369         }
 370         if (i == rio_table_hdr->num_scal_dev) {
 371                 pr_err("Couldn't find owner Twister for Cyclone!\n");
 372                 return last_bus;
 373         }
 374
 375         switch (rio_devs[wpeg_num]->type) {
 376         case CompatWPEG:
 377                 /*
 378                  * The Compatibility Winnipeg controls the 2 legacy buses,
 379                  * the 66MHz PCI bus [2 slots] and the 2 "extra" buses in case
 380                  * a PCI-PCI bridge card is used in either slot: total 5 buses.
 381                  */
 382                 num_buses = 5;
 383                 break;
 384         case AltWPEG:
 385                 /*
 386                  * The Alternate Winnipeg controls the 2 133MHz buses [1 slot
 387                  * each], their 2 "extra" buses, the 100MHz bus [2 slots] and
 388                  * the "extra" buses for each of those slots: total 7 buses.
 389                  */
 390                 num_buses = 7;
 391                 break;
 392         case LookOutAWPEG:
 393         case LookOutBWPEG:
 394                 /*
 395                  * A Lookout Winnipeg controls 3 100MHz buses [2 slots each]
 396                  * & the "extra" buses for each of those slots: total 9 buses.
 397                  */
 398                 num_buses = 9;
 399                 break;
 400         default:
 401                 pr_info("Unsupported Winnipeg type!\n");
 402                 return last_bus;
 403         }
 404
 405         for (bus = last_bus; bus < last_bus + num_buses; bus++)
 406                 mp_bus_id_to_node[bus] = node;
 407         return bus;
 408 }
 409
 410 static int build_detail_arrays(void)
 411 {
 412         unsigned long ptr;
 413         int i, scal_detail_size, rio_detail_size;
 414
 415         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) {
 416                 pr_warn("MAX_NUMNODES too low!  Defined as %d, but system has %d nodes\n",
 417                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
 418                 return 0;
 419         }
 420
 421         switch (rio_table_hdr->version) {
 422         default:
 423                 pr_warn("Invalid Rio Grande Table Version: %d\n",
 424                         rio_table_hdr->version);
 425                 return 0;
 426         case 2:
 427                 scal_detail_size = 11;
 428                 rio_detail_size = 13;
 429                 break;
 430         case 3:
 431                 scal_detail_size = 12;
 432                 rio_detail_size = 15;
 433                 break;
 434         }
 435
 436         ptr = (unsigned long)rio_table_hdr + 3;
 437         for (i = 0; i < rio_table_hdr->num_scal_dev; i++, ptr += scal_detail_size)
 438                 scal_devs[i] = (struct scal_detail *)ptr;
 439
 440         for (i = 0; i < rio_table_hdr->num_rio_dev; i++, ptr += rio_detail_size)
 441                 rio_devs[i] = (struct rio_detail *)ptr;
 442
 443         return 1;
 444 }
 445
 446 void setup_summit(void)
 447 {
 448         unsigned long           ptr;
 449         unsigned short          offset;
 450         int                     i, next_wpeg, next_bus = 0;
 451
 452         /* The pointer to the EBDA is stored in the word @ phys 0x40E(40:0E) */
 453         ptr = get_bios_ebda();
 454         ptr = (unsigned long)phys_to_virt(ptr);
 455
 456         rio_table_hdr = NULL;
 457         offset = 0x180;
 458         while (offset) {
 459                 /* The block id is stored in the 2nd word */
 460                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752) {
 461                         /* set the pointer past the offset & block id */
 462                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
 463                         break;
 464                 }
 465                 /* The next offset is stored in the 1st word.  0 means no more */
 466                 offset = *((unsigned short *)(ptr + offset));
 467         }
 468         if (!rio_table_hdr) {
 469                 pr_err("Unable to locate Rio Grande Table in EBDA - bailing!\n");
 470                 return;
 471         }
 472
 473         if (!build_detail_arrays())
 474                 return;
 475
 476         /* The first Winnipeg we're looking for has an index of 0 */
 477         next_wpeg = 0;
 478         do {
 479                 for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
 480                         if (is_WPEG(rio_devs[i]) && rio_devs[i]->WP_index == next_wpeg) {
 481                                 /* It's the Winnipeg we're looking for! */
 482                                 next_bus = setup_pci_node_map_for_wpeg(i, next_bus);
 483                                 next_wpeg++;
 484                                 break;
 485                         }
 486                 }
 487                 /*
 488                  * If we go through all Rio devices and don't find one with
 489                  * the next index, it means we've found all the Winnipegs,
 490                  * and thus all the PCI buses.
 491                  */
 492                 if (i == rio_table_hdr->num_rio_dev)
 493                         next_wpeg = 0;
 494         } while (next_wpeg != 0);
 495 }
 496 #endif
 497
 498 static struct apic apic_summit = {
 499
 500         .name                           = "summit",
 501         .probe                          = probe_summit,
 502         .acpi_madt_oem_check            = summit_acpi_madt_oem_check,
 503         .apic_id_valid                  = default_apic_id_valid,
 504         .apic_id_registered             = summit_apic_id_registered,
 505
 506         .irq_delivery_mode              = dest_LowestPrio,
 507         /* logical delivery broadcast to all CPUs: */
 508         .irq_dest_mode                  = 1,
 509
 510         .target_cpus                    = summit_target_cpus,
 511         .disable_esr                    = 1,
 512         .dest_logical                   = APIC_DEST_LOGICAL,
 513         .check_apicid_used              = summit_check_apicid_used,
 514         .check_apicid_present           = summit_check_apicid_present,
 515
 516         .vector_allocation_domain       = summit_vector_allocation_domain,
 517         .init_apic_ldr                  = summit_init_apic_ldr,
 518
 519         .ioapic_phys_id_map             = summit_ioapic_phys_id_map,
 520         .setup_apic_routing             = summit_setup_apic_routing,
 521         .multi_timer_check              = NULL,
 522         .cpu_present_to_apicid          = summit_cpu_present_to_apicid,
 523         .apicid_to_cpu_present          = summit_apicid_to_cpu_present,
 524         .setup_portio_remap             = NULL,
 525         .check_phys_apicid_present      = summit_check_phys_apicid_present,
 526         .enable_apic_mode               = NULL,
 527         .phys_pkg_id                    = summit_phys_pkg_id,
 528         .mps_oem_check                  = summit_mps_oem_check,
 529
 530         .get_apic_id                    = summit_get_apic_id,
 531         .set_apic_id                    = NULL,
 532         .apic_id_mask                   = 0xFF << 24,
 533
 534         .cpu_mask_to_apicid             = summit_cpu_mask_to_apicid,
 535         .cpu_mask_to_apicid_and         = summit_cpu_mask_to_apicid_and,
 536
 537         .send_IPI_mask                  = summit_send_IPI_mask,
 538         .send_IPI_mask_allbutself       = NULL,
 539         .send_IPI_allbutself            = summit_send_IPI_allbutself,
 540         .send_IPI_all                   = summit_send_IPI_all,
 541         .send_IPI_self                  = default_send_IPI_self,
 542
 543         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 544         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 545
 546         .wait_for_init_deassert         = default_wait_for_init_deassert,
 547
 548         .smp_callin_clear_local_apic    = NULL,
 549         .inquire_remote_apic            = default_inquire_remote_apic,
 550
 551         .read                           = native_apic_mem_read,
 552         .write                          = native_apic_mem_write,
 553         .eoi_write                      = native_apic_mem_write,
 554         .icr_read                       = native_apic_icr_read,
 555         .icr_write                      = native_apic_icr_write,
 556         .wait_icr_idle                  = native_apic_wait_icr_idle,
 557         .safe_wait_icr_idle             = native_safe_apic_wait_icr_idle,
 558
 559         .x86_32_early_logical_apicid    = summit_early_logical_apicid,
 560 };
 561
 562 apic_driver(apic_summit);