2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_RAW_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
91 /* The one past the highest gsi number used */
94 /* MP IRQ source entries */
95 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
97 /* # of MP IRQ source entries */
101 static int nr_irqs_gsi = NR_IRQS_LEGACY;
104 * Saved I/O APIC state during suspend/resume, or while enabling intr-remap.
106 static struct IO_APIC_route_entry *ioapic_saved_data[MAX_IO_APICS];
108 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
109 int mp_bus_id_to_type[MAX_MP_BUSSES];
112 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
114 int skip_ioapic_setup;
117 * disable_ioapic_support() - disables ioapic support at runtime
119 void disable_ioapic_support(void)
123 noioapicreroute = -1;
125 skip_ioapic_setup = 1;
128 static int __init parse_noapic(char *str)
130 /* disable IO-APIC */
131 disable_ioapic_support();
134 early_param("noapic", parse_noapic);
136 static int io_apic_setup_irq_pin(unsigned int irq, int node,
137 struct io_apic_irq_attr *attr);
139 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
140 void mp_save_irq(struct mpc_intsrc *m)
144 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
145 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
146 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
147 m->srcbusirq, m->dstapic, m->dstirq);
149 for (i = 0; i < mp_irq_entries; i++) {
150 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
154 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
155 if (++mp_irq_entries == MAX_IRQ_SOURCES)
156 panic("Max # of irq sources exceeded!!\n");
159 struct irq_pin_list {
161 struct irq_pin_list *next;
164 static struct irq_pin_list *alloc_irq_pin_list(int node)
166 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
170 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
171 #ifdef CONFIG_SPARSE_IRQ
172 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
174 static struct irq_cfg irq_cfgx[NR_IRQS];
177 int __init arch_early_irq_init(void)
182 if (!legacy_pic->nr_legacy_irqs) {
187 for (i = 0; i < nr_ioapics; i++) {
188 ioapic_saved_data[i] =
189 kzalloc(sizeof(struct IO_APIC_route_entry) *
190 nr_ioapic_registers[i], GFP_KERNEL);
191 if (!ioapic_saved_data[i])
192 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
196 count = ARRAY_SIZE(irq_cfgx);
197 node = cpu_to_node(0);
199 /* Make sure the legacy interrupts are marked in the bitmap */
200 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
202 for (i = 0; i < count; i++) {
203 irq_set_chip_data(i, &cfg[i]);
204 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
205 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
207 * For legacy IRQ's, start with assigning irq0 to irq15 to
208 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
210 if (i < legacy_pic->nr_legacy_irqs) {
211 cfg[i].vector = IRQ0_VECTOR + i;
212 cpumask_set_cpu(0, cfg[i].domain);
219 #ifdef CONFIG_SPARSE_IRQ
220 static struct irq_cfg *irq_cfg(unsigned int irq)
222 return irq_get_chip_data(irq);
225 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
229 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
232 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
234 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
238 free_cpumask_var(cfg->domain);
244 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
248 irq_set_chip_data(at, NULL);
249 free_cpumask_var(cfg->domain);
250 free_cpumask_var(cfg->old_domain);
256 struct irq_cfg *irq_cfg(unsigned int irq)
258 return irq < nr_irqs ? irq_cfgx + irq : NULL;
261 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
263 return irq_cfgx + irq;
266 static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { }
270 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
272 int res = irq_alloc_desc_at(at, node);
278 cfg = irq_get_chip_data(at);
283 cfg = alloc_irq_cfg(at, node);
285 irq_set_chip_data(at, cfg);
291 static int alloc_irq_from(unsigned int from, int node)
293 return irq_alloc_desc_from(from, node);
296 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
298 free_irq_cfg(at, cfg);
304 unsigned int unused[3];
306 unsigned int unused2[11];
310 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
312 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
313 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
316 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
318 struct io_apic __iomem *io_apic = io_apic_base(apic);
319 writel(vector, &io_apic->eoi);
322 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
324 struct io_apic __iomem *io_apic = io_apic_base(apic);
325 writel(reg, &io_apic->index);
326 return readl(&io_apic->data);
329 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
331 struct io_apic __iomem *io_apic = io_apic_base(apic);
332 writel(reg, &io_apic->index);
333 writel(value, &io_apic->data);
337 * Re-write a value: to be used for read-modify-write
338 * cycles where the read already set up the index register.
340 * Older SiS APIC requires we rewrite the index register
342 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
344 struct io_apic __iomem *io_apic = io_apic_base(apic);
347 writel(reg, &io_apic->index);
348 writel(value, &io_apic->data);
351 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
353 struct irq_pin_list *entry;
356 raw_spin_lock_irqsave(&ioapic_lock, flags);
357 for_each_irq_pin(entry, cfg->irq_2_pin) {
362 reg = io_apic_read(entry->apic, 0x10 + pin*2);
363 /* Is the remote IRR bit set? */
364 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
365 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
369 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
375 struct { u32 w1, w2; };
376 struct IO_APIC_route_entry entry;
379 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
381 union entry_union eu;
383 raw_spin_lock_irqsave(&ioapic_lock, flags);
384 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
385 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
386 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
391 * When we write a new IO APIC routing entry, we need to write the high
392 * word first! If the mask bit in the low word is clear, we will enable
393 * the interrupt, and we need to make sure the entry is fully populated
394 * before that happens.
397 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
399 union entry_union eu = {{0, 0}};
402 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
403 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
406 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
409 raw_spin_lock_irqsave(&ioapic_lock, flags);
410 __ioapic_write_entry(apic, pin, e);
411 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
415 * When we mask an IO APIC routing entry, we need to write the low
416 * word first, in order to set the mask bit before we change the
419 static void ioapic_mask_entry(int apic, int pin)
422 union entry_union eu = { .entry.mask = 1 };
424 raw_spin_lock_irqsave(&ioapic_lock, flags);
425 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
426 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
427 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
431 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
432 * shared ISA-space IRQs, so we have to support them. We are super
433 * fast in the common case, and fast for shared ISA-space IRQs.
436 __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
438 struct irq_pin_list **last, *entry;
440 /* don't allow duplicates */
441 last = &cfg->irq_2_pin;
442 for_each_irq_pin(entry, cfg->irq_2_pin) {
443 if (entry->apic == apic && entry->pin == pin)
448 entry = alloc_irq_pin_list(node);
450 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
461 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
463 if (__add_pin_to_irq_node(cfg, node, apic, pin))
464 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
468 * Reroute an IRQ to a different pin.
470 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
471 int oldapic, int oldpin,
472 int newapic, int newpin)
474 struct irq_pin_list *entry;
476 for_each_irq_pin(entry, cfg->irq_2_pin) {
477 if (entry->apic == oldapic && entry->pin == oldpin) {
478 entry->apic = newapic;
480 /* every one is different, right? */
485 /* old apic/pin didn't exist, so just add new ones */
486 add_pin_to_irq_node(cfg, node, newapic, newpin);
489 static void __io_apic_modify_irq(struct irq_pin_list *entry,
490 int mask_and, int mask_or,
491 void (*final)(struct irq_pin_list *entry))
493 unsigned int reg, pin;
496 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
499 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
504 static void io_apic_modify_irq(struct irq_cfg *cfg,
505 int mask_and, int mask_or,
506 void (*final)(struct irq_pin_list *entry))
508 struct irq_pin_list *entry;
510 for_each_irq_pin(entry, cfg->irq_2_pin)
511 __io_apic_modify_irq(entry, mask_and, mask_or, final);
514 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
516 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
517 IO_APIC_REDIR_MASKED, NULL);
520 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
522 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
523 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
526 static void io_apic_sync(struct irq_pin_list *entry)
529 * Synchronize the IO-APIC and the CPU by doing
530 * a dummy read from the IO-APIC
532 struct io_apic __iomem *io_apic;
533 io_apic = io_apic_base(entry->apic);
534 readl(&io_apic->data);
537 static void mask_ioapic(struct irq_cfg *cfg)
541 raw_spin_lock_irqsave(&ioapic_lock, flags);
542 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
543 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
546 static void mask_ioapic_irq(struct irq_data *data)
548 mask_ioapic(data->chip_data);
551 static void __unmask_ioapic(struct irq_cfg *cfg)
553 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
556 static void unmask_ioapic(struct irq_cfg *cfg)
560 raw_spin_lock_irqsave(&ioapic_lock, flags);
561 __unmask_ioapic(cfg);
562 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
565 static void unmask_ioapic_irq(struct irq_data *data)
567 unmask_ioapic(data->chip_data);
570 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
572 struct IO_APIC_route_entry entry;
574 /* Check delivery_mode to be sure we're not clearing an SMI pin */
575 entry = ioapic_read_entry(apic, pin);
576 if (entry.delivery_mode == dest_SMI)
579 * Disable it in the IO-APIC irq-routing table:
581 ioapic_mask_entry(apic, pin);
584 static void clear_IO_APIC (void)
588 for (apic = 0; apic < nr_ioapics; apic++)
589 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
590 clear_IO_APIC_pin(apic, pin);
595 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
596 * specific CPU-side IRQs.
600 static int pirq_entries[MAX_PIRQS] = {
601 [0 ... MAX_PIRQS - 1] = -1
604 static int __init ioapic_pirq_setup(char *str)
607 int ints[MAX_PIRQS+1];
609 get_options(str, ARRAY_SIZE(ints), ints);
611 apic_printk(APIC_VERBOSE, KERN_INFO
612 "PIRQ redirection, working around broken MP-BIOS.\n");
614 if (ints[0] < MAX_PIRQS)
617 for (i = 0; i < max; i++) {
618 apic_printk(APIC_VERBOSE, KERN_DEBUG
619 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
621 * PIRQs are mapped upside down, usually.
623 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
628 __setup("pirq=", ioapic_pirq_setup);
629 #endif /* CONFIG_X86_32 */
632 * Saves all the IO-APIC RTE's
634 int save_ioapic_entries(void)
639 for (apic = 0; apic < nr_ioapics; apic++) {
640 if (!ioapic_saved_data[apic]) {
645 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
646 ioapic_saved_data[apic][pin] =
647 ioapic_read_entry(apic, pin);
654 * Mask all IO APIC entries.
656 void mask_ioapic_entries(void)
660 for (apic = 0; apic < nr_ioapics; apic++) {
661 if (!ioapic_saved_data[apic])
664 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
665 struct IO_APIC_route_entry entry;
667 entry = ioapic_saved_data[apic][pin];
670 ioapic_write_entry(apic, pin, entry);
677 * Restore IO APIC entries which was saved in ioapic_saved_data
679 int restore_ioapic_entries(void)
683 for (apic = 0; apic < nr_ioapics; apic++) {
684 if (!ioapic_saved_data[apic])
687 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
688 ioapic_write_entry(apic, pin,
689 ioapic_saved_data[apic][pin]);
695 * Find the IRQ entry number of a certain pin.
697 static int find_irq_entry(int apic, int pin, int type)
701 for (i = 0; i < mp_irq_entries; i++)
702 if (mp_irqs[i].irqtype == type &&
703 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
704 mp_irqs[i].dstapic == MP_APIC_ALL) &&
705 mp_irqs[i].dstirq == pin)
712 * Find the pin to which IRQ[irq] (ISA) is connected
714 static int __init find_isa_irq_pin(int irq, int type)
718 for (i = 0; i < mp_irq_entries; i++) {
719 int lbus = mp_irqs[i].srcbus;
721 if (test_bit(lbus, mp_bus_not_pci) &&
722 (mp_irqs[i].irqtype == type) &&
723 (mp_irqs[i].srcbusirq == irq))
725 return mp_irqs[i].dstirq;
730 static int __init find_isa_irq_apic(int irq, int type)
734 for (i = 0; i < mp_irq_entries; i++) {
735 int lbus = mp_irqs[i].srcbus;
737 if (test_bit(lbus, mp_bus_not_pci) &&
738 (mp_irqs[i].irqtype == type) &&
739 (mp_irqs[i].srcbusirq == irq))
742 if (i < mp_irq_entries) {
744 for(apic = 0; apic < nr_ioapics; apic++) {
745 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
753 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
755 * EISA Edge/Level control register, ELCR
757 static int EISA_ELCR(unsigned int irq)
759 if (irq < legacy_pic->nr_legacy_irqs) {
760 unsigned int port = 0x4d0 + (irq >> 3);
761 return (inb(port) >> (irq & 7)) & 1;
763 apic_printk(APIC_VERBOSE, KERN_INFO
764 "Broken MPtable reports ISA irq %d\n", irq);
770 /* ISA interrupts are always polarity zero edge triggered,
771 * when listed as conforming in the MP table. */
773 #define default_ISA_trigger(idx) (0)
774 #define default_ISA_polarity(idx) (0)
776 /* EISA interrupts are always polarity zero and can be edge or level
777 * trigger depending on the ELCR value. If an interrupt is listed as
778 * EISA conforming in the MP table, that means its trigger type must
779 * be read in from the ELCR */
781 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
782 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
784 /* PCI interrupts are always polarity one level triggered,
785 * when listed as conforming in the MP table. */
787 #define default_PCI_trigger(idx) (1)
788 #define default_PCI_polarity(idx) (1)
790 /* MCA interrupts are always polarity zero level triggered,
791 * when listed as conforming in the MP table. */
793 #define default_MCA_trigger(idx) (1)
794 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
796 static int irq_polarity(int idx)
798 int bus = mp_irqs[idx].srcbus;
802 * Determine IRQ line polarity (high active or low active):
804 switch (mp_irqs[idx].irqflag & 3)
806 case 0: /* conforms, ie. bus-type dependent polarity */
807 if (test_bit(bus, mp_bus_not_pci))
808 polarity = default_ISA_polarity(idx);
810 polarity = default_PCI_polarity(idx);
812 case 1: /* high active */
817 case 2: /* reserved */
819 printk(KERN_WARNING "broken BIOS!!\n");
823 case 3: /* low active */
828 default: /* invalid */
830 printk(KERN_WARNING "broken BIOS!!\n");
838 static int irq_trigger(int idx)
840 int bus = mp_irqs[idx].srcbus;
844 * Determine IRQ trigger mode (edge or level sensitive):
846 switch ((mp_irqs[idx].irqflag>>2) & 3)
848 case 0: /* conforms, ie. bus-type dependent */
849 if (test_bit(bus, mp_bus_not_pci))
850 trigger = default_ISA_trigger(idx);
852 trigger = default_PCI_trigger(idx);
853 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
854 switch (mp_bus_id_to_type[bus]) {
855 case MP_BUS_ISA: /* ISA pin */
857 /* set before the switch */
860 case MP_BUS_EISA: /* EISA pin */
862 trigger = default_EISA_trigger(idx);
865 case MP_BUS_PCI: /* PCI pin */
867 /* set before the switch */
870 case MP_BUS_MCA: /* MCA pin */
872 trigger = default_MCA_trigger(idx);
877 printk(KERN_WARNING "broken BIOS!!\n");
889 case 2: /* reserved */
891 printk(KERN_WARNING "broken BIOS!!\n");
900 default: /* invalid */
902 printk(KERN_WARNING "broken BIOS!!\n");
910 static int pin_2_irq(int idx, int apic, int pin)
913 int bus = mp_irqs[idx].srcbus;
916 * Debugging check, we are in big trouble if this message pops up!
918 if (mp_irqs[idx].dstirq != pin)
919 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
921 if (test_bit(bus, mp_bus_not_pci)) {
922 irq = mp_irqs[idx].srcbusirq;
924 u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
926 if (gsi >= NR_IRQS_LEGACY)
934 * PCI IRQ command line redirection. Yes, limits are hardcoded.
936 if ((pin >= 16) && (pin <= 23)) {
937 if (pirq_entries[pin-16] != -1) {
938 if (!pirq_entries[pin-16]) {
939 apic_printk(APIC_VERBOSE, KERN_DEBUG
940 "disabling PIRQ%d\n", pin-16);
942 irq = pirq_entries[pin-16];
943 apic_printk(APIC_VERBOSE, KERN_DEBUG
944 "using PIRQ%d -> IRQ %d\n",
955 * Find a specific PCI IRQ entry.
956 * Not an __init, possibly needed by modules
958 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
959 struct io_apic_irq_attr *irq_attr)
961 int apic, i, best_guess = -1;
963 apic_printk(APIC_DEBUG,
964 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
966 if (test_bit(bus, mp_bus_not_pci)) {
967 apic_printk(APIC_VERBOSE,
968 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
971 for (i = 0; i < mp_irq_entries; i++) {
972 int lbus = mp_irqs[i].srcbus;
974 for (apic = 0; apic < nr_ioapics; apic++)
975 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
976 mp_irqs[i].dstapic == MP_APIC_ALL)
979 if (!test_bit(lbus, mp_bus_not_pci) &&
980 !mp_irqs[i].irqtype &&
982 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
983 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
985 if (!(apic || IO_APIC_IRQ(irq)))
988 if (pin == (mp_irqs[i].srcbusirq & 3)) {
989 set_io_apic_irq_attr(irq_attr, apic,
996 * Use the first all-but-pin matching entry as a
997 * best-guess fuzzy result for broken mptables.
999 if (best_guess < 0) {
1000 set_io_apic_irq_attr(irq_attr, apic,
1010 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1012 void lock_vector_lock(void)
1014 /* Used to the online set of cpus does not change
1015 * during assign_irq_vector.
1017 raw_spin_lock(&vector_lock);
1020 void unlock_vector_lock(void)
1022 raw_spin_unlock(&vector_lock);
1026 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1029 * NOTE! The local APIC isn't very good at handling
1030 * multiple interrupts at the same interrupt level.
1031 * As the interrupt level is determined by taking the
1032 * vector number and shifting that right by 4, we
1033 * want to spread these out a bit so that they don't
1034 * all fall in the same interrupt level.
1036 * Also, we've got to be careful not to trash gate
1037 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1039 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1040 static int current_offset = VECTOR_OFFSET_START % 8;
1041 unsigned int old_vector;
1043 cpumask_var_t tmp_mask;
1045 if (cfg->move_in_progress)
1048 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1051 old_vector = cfg->vector;
1053 cpumask_and(tmp_mask, mask, cpu_online_mask);
1054 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1055 if (!cpumask_empty(tmp_mask)) {
1056 free_cpumask_var(tmp_mask);
1061 /* Only try and allocate irqs on cpus that are present */
1063 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1067 apic->vector_allocation_domain(cpu, tmp_mask);
1069 vector = current_vector;
1070 offset = current_offset;
1073 if (vector >= first_system_vector) {
1074 /* If out of vectors on large boxen, must share them. */
1075 offset = (offset + 1) % 8;
1076 vector = FIRST_EXTERNAL_VECTOR + offset;
1078 if (unlikely(current_vector == vector))
1081 if (test_bit(vector, used_vectors))
1084 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1085 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1088 current_vector = vector;
1089 current_offset = offset;
1091 cfg->move_in_progress = 1;
1092 cpumask_copy(cfg->old_domain, cfg->domain);
1094 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1095 per_cpu(vector_irq, new_cpu)[vector] = irq;
1096 cfg->vector = vector;
1097 cpumask_copy(cfg->domain, tmp_mask);
1101 free_cpumask_var(tmp_mask);
1105 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1108 unsigned long flags;
1110 raw_spin_lock_irqsave(&vector_lock, flags);
1111 err = __assign_irq_vector(irq, cfg, mask);
1112 raw_spin_unlock_irqrestore(&vector_lock, flags);
1116 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1120 BUG_ON(!cfg->vector);
1122 vector = cfg->vector;
1123 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1124 per_cpu(vector_irq, cpu)[vector] = -1;
1127 cpumask_clear(cfg->domain);
1129 if (likely(!cfg->move_in_progress))
1131 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1132 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1134 if (per_cpu(vector_irq, cpu)[vector] != irq)
1136 per_cpu(vector_irq, cpu)[vector] = -1;
1140 cfg->move_in_progress = 0;
1143 void __setup_vector_irq(int cpu)
1145 /* Initialize vector_irq on a new cpu */
1147 struct irq_cfg *cfg;
1150 * vector_lock will make sure that we don't run into irq vector
1151 * assignments that might be happening on another cpu in parallel,
1152 * while we setup our initial vector to irq mappings.
1154 raw_spin_lock(&vector_lock);
1155 /* Mark the inuse vectors */
1156 for_each_active_irq(irq) {
1157 cfg = irq_get_chip_data(irq);
1161 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1162 * will be part of the irq_cfg's domain.
1164 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1165 cpumask_set_cpu(cpu, cfg->domain);
1167 if (!cpumask_test_cpu(cpu, cfg->domain))
1169 vector = cfg->vector;
1170 per_cpu(vector_irq, cpu)[vector] = irq;
1172 /* Mark the free vectors */
1173 for (vector = 0; vector < NR_VECTORS; ++vector) {
1174 irq = per_cpu(vector_irq, cpu)[vector];
1179 if (!cpumask_test_cpu(cpu, cfg->domain))
1180 per_cpu(vector_irq, cpu)[vector] = -1;
1182 raw_spin_unlock(&vector_lock);
1185 static struct irq_chip ioapic_chip;
1186 static struct irq_chip ir_ioapic_chip;
1188 #ifdef CONFIG_X86_32
1189 static inline int IO_APIC_irq_trigger(int irq)
1193 for (apic = 0; apic < nr_ioapics; apic++) {
1194 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1195 idx = find_irq_entry(apic, pin, mp_INT);
1196 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1197 return irq_trigger(idx);
1201 * nonexistent IRQs are edge default
1206 static inline int IO_APIC_irq_trigger(int irq)
1212 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1213 unsigned long trigger)
1215 struct irq_chip *chip = &ioapic_chip;
1216 irq_flow_handler_t hdl;
1219 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1220 trigger == IOAPIC_LEVEL) {
1221 irq_set_status_flags(irq, IRQ_LEVEL);
1224 irq_clear_status_flags(irq, IRQ_LEVEL);
1228 if (irq_remapped(cfg)) {
1229 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1230 chip = &ir_ioapic_chip;
1231 fasteoi = trigger != 0;
1234 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1235 irq_set_chip_and_handler_name(irq, chip, hdl,
1236 fasteoi ? "fasteoi" : "edge");
1239 static int setup_ioapic_entry(int apic_id, int irq,
1240 struct IO_APIC_route_entry *entry,
1241 unsigned int destination, int trigger,
1242 int polarity, int vector, int pin)
1245 * add it to the IO-APIC irq-routing table:
1247 memset(entry,0,sizeof(*entry));
1249 if (intr_remapping_enabled) {
1250 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1252 struct IR_IO_APIC_route_entry *ir_entry =
1253 (struct IR_IO_APIC_route_entry *) entry;
1257 panic("No mapping iommu for ioapic %d\n", apic_id);
1259 index = alloc_irte(iommu, irq, 1);
1261 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1263 prepare_irte(&irte, vector, destination);
1265 /* Set source-id of interrupt request */
1266 set_ioapic_sid(&irte, apic_id);
1268 modify_irte(irq, &irte);
1270 ir_entry->index2 = (index >> 15) & 0x1;
1272 ir_entry->format = 1;
1273 ir_entry->index = (index & 0x7fff);
1275 * IO-APIC RTE will be configured with virtual vector.
1276 * irq handler will do the explicit EOI to the io-apic.
1278 ir_entry->vector = pin;
1280 entry->delivery_mode = apic->irq_delivery_mode;
1281 entry->dest_mode = apic->irq_dest_mode;
1282 entry->dest = destination;
1283 entry->vector = vector;
1286 entry->mask = 0; /* enable IRQ */
1287 entry->trigger = trigger;
1288 entry->polarity = polarity;
1290 /* Mask level triggered irqs.
1291 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1298 static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
1299 struct irq_cfg *cfg, int trigger, int polarity)
1301 struct IO_APIC_route_entry entry;
1304 if (!IO_APIC_IRQ(irq))
1307 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1308 * controllers like 8259. Now that IO-APIC can handle this irq, update
1311 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1312 apic->vector_allocation_domain(0, cfg->domain);
1314 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1317 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1319 apic_printk(APIC_VERBOSE,KERN_DEBUG
1320 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1321 "IRQ %d Mode:%i Active:%i)\n",
1322 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1323 irq, trigger, polarity);
1326 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1327 dest, trigger, polarity, cfg->vector, pin)) {
1328 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1329 mp_ioapics[apic_id].apicid, pin);
1330 __clear_irq_vector(irq, cfg);
1334 ioapic_register_intr(irq, cfg, trigger);
1335 if (irq < legacy_pic->nr_legacy_irqs)
1336 legacy_pic->mask(irq);
1338 ioapic_write_entry(apic_id, pin, entry);
1342 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1343 } mp_ioapic_routing[MAX_IO_APICS];
1345 static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin)
1350 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1351 mp_ioapics[apic_id].apicid, pin);
1355 static void __init __io_apic_setup_irqs(unsigned int apic_id)
1357 int idx, node = cpu_to_node(0);
1358 struct io_apic_irq_attr attr;
1359 unsigned int pin, irq;
1361 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1362 idx = find_irq_entry(apic_id, pin, mp_INT);
1363 if (io_apic_pin_not_connected(idx, apic_id, pin))
1366 irq = pin_2_irq(idx, apic_id, pin);
1368 if ((apic_id > 0) && (irq > 16))
1372 * Skip the timer IRQ if there's a quirk handler
1373 * installed and if it returns 1:
1375 if (apic->multi_timer_check &&
1376 apic->multi_timer_check(apic_id, irq))
1379 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1382 io_apic_setup_irq_pin(irq, node, &attr);
1386 static void __init setup_IO_APIC_irqs(void)
1388 unsigned int apic_id;
1390 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1392 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1393 __io_apic_setup_irqs(apic_id);
1397 * for the gsit that is not in first ioapic
1398 * but could not use acpi_register_gsi()
1399 * like some special sci in IBM x3330
1401 void setup_IO_APIC_irq_extra(u32 gsi)
1403 int apic_id = 0, pin, idx, irq, node = cpu_to_node(0);
1404 struct io_apic_irq_attr attr;
1407 * Convert 'gsi' to 'ioapic.pin'.
1409 apic_id = mp_find_ioapic(gsi);
1413 pin = mp_find_ioapic_pin(apic_id, gsi);
1414 idx = find_irq_entry(apic_id, pin, mp_INT);
1418 irq = pin_2_irq(idx, apic_id, pin);
1420 /* Only handle the non legacy irqs on secondary ioapics */
1421 if (apic_id == 0 || irq < NR_IRQS_LEGACY)
1424 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1427 io_apic_setup_irq_pin_once(irq, node, &attr);
1431 * Set up the timer pin, possibly with the 8259A-master behind.
1433 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1436 struct IO_APIC_route_entry entry;
1438 if (intr_remapping_enabled)
1441 memset(&entry, 0, sizeof(entry));
1444 * We use logical delivery to get the timer IRQ
1447 entry.dest_mode = apic->irq_dest_mode;
1448 entry.mask = 0; /* don't mask IRQ for edge */
1449 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1450 entry.delivery_mode = apic->irq_delivery_mode;
1453 entry.vector = vector;
1456 * The timer IRQ doesn't have to know that behind the
1457 * scene we may have a 8259A-master in AEOI mode ...
1459 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1463 * Add it to the IO-APIC irq-routing table:
1465 ioapic_write_entry(apic_id, pin, entry);
1469 __apicdebuginit(void) print_IO_APIC(void)
1472 union IO_APIC_reg_00 reg_00;
1473 union IO_APIC_reg_01 reg_01;
1474 union IO_APIC_reg_02 reg_02;
1475 union IO_APIC_reg_03 reg_03;
1476 unsigned long flags;
1477 struct irq_cfg *cfg;
1480 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1481 for (i = 0; i < nr_ioapics; i++)
1482 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1483 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1486 * We are a bit conservative about what we expect. We have to
1487 * know about every hardware change ASAP.
1489 printk(KERN_INFO "testing the IO APIC.......................\n");
1491 for (apic = 0; apic < nr_ioapics; apic++) {
1493 raw_spin_lock_irqsave(&ioapic_lock, flags);
1494 reg_00.raw = io_apic_read(apic, 0);
1495 reg_01.raw = io_apic_read(apic, 1);
1496 if (reg_01.bits.version >= 0x10)
1497 reg_02.raw = io_apic_read(apic, 2);
1498 if (reg_01.bits.version >= 0x20)
1499 reg_03.raw = io_apic_read(apic, 3);
1500 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1503 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1504 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1505 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1506 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1507 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1509 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1510 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1512 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1513 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1516 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1517 * but the value of reg_02 is read as the previous read register
1518 * value, so ignore it if reg_02 == reg_01.
1520 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1521 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1522 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1526 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1527 * or reg_03, but the value of reg_0[23] is read as the previous read
1528 * register value, so ignore it if reg_03 == reg_0[12].
1530 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1531 reg_03.raw != reg_01.raw) {
1532 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1533 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1536 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1538 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1539 " Stat Dmod Deli Vect:\n");
1541 for (i = 0; i <= reg_01.bits.entries; i++) {
1542 struct IO_APIC_route_entry entry;
1544 entry = ioapic_read_entry(apic, i);
1546 printk(KERN_DEBUG " %02x %03X ",
1551 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1556 entry.delivery_status,
1558 entry.delivery_mode,
1563 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1564 for_each_active_irq(irq) {
1565 struct irq_pin_list *entry;
1567 cfg = irq_get_chip_data(irq);
1570 entry = cfg->irq_2_pin;
1573 printk(KERN_DEBUG "IRQ%d ", irq);
1574 for_each_irq_pin(entry, cfg->irq_2_pin)
1575 printk("-> %d:%d", entry->apic, entry->pin);
1579 printk(KERN_INFO ".................................... done.\n");
1584 __apicdebuginit(void) print_APIC_field(int base)
1590 for (i = 0; i < 8; i++)
1591 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1593 printk(KERN_CONT "\n");
1596 __apicdebuginit(void) print_local_APIC(void *dummy)
1598 unsigned int i, v, ver, maxlvt;
1601 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1602 smp_processor_id(), hard_smp_processor_id());
1603 v = apic_read(APIC_ID);
1604 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1605 v = apic_read(APIC_LVR);
1606 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1607 ver = GET_APIC_VERSION(v);
1608 maxlvt = lapic_get_maxlvt();
1610 v = apic_read(APIC_TASKPRI);
1611 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1613 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1614 if (!APIC_XAPIC(ver)) {
1615 v = apic_read(APIC_ARBPRI);
1616 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1617 v & APIC_ARBPRI_MASK);
1619 v = apic_read(APIC_PROCPRI);
1620 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1624 * Remote read supported only in the 82489DX and local APIC for
1625 * Pentium processors.
1627 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1628 v = apic_read(APIC_RRR);
1629 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1632 v = apic_read(APIC_LDR);
1633 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1634 if (!x2apic_enabled()) {
1635 v = apic_read(APIC_DFR);
1636 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1638 v = apic_read(APIC_SPIV);
1639 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1641 printk(KERN_DEBUG "... APIC ISR field:\n");
1642 print_APIC_field(APIC_ISR);
1643 printk(KERN_DEBUG "... APIC TMR field:\n");
1644 print_APIC_field(APIC_TMR);
1645 printk(KERN_DEBUG "... APIC IRR field:\n");
1646 print_APIC_field(APIC_IRR);
1648 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1649 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1650 apic_write(APIC_ESR, 0);
1652 v = apic_read(APIC_ESR);
1653 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1656 icr = apic_icr_read();
1657 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1658 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1660 v = apic_read(APIC_LVTT);
1661 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1663 if (maxlvt > 3) { /* PC is LVT#4. */
1664 v = apic_read(APIC_LVTPC);
1665 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1667 v = apic_read(APIC_LVT0);
1668 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1669 v = apic_read(APIC_LVT1);
1670 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1672 if (maxlvt > 2) { /* ERR is LVT#3. */
1673 v = apic_read(APIC_LVTERR);
1674 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1677 v = apic_read(APIC_TMICT);
1678 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1679 v = apic_read(APIC_TMCCT);
1680 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1681 v = apic_read(APIC_TDCR);
1682 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1684 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1685 v = apic_read(APIC_EFEAT);
1686 maxlvt = (v >> 16) & 0xff;
1687 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1688 v = apic_read(APIC_ECTRL);
1689 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1690 for (i = 0; i < maxlvt; i++) {
1691 v = apic_read(APIC_EILVTn(i));
1692 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1698 __apicdebuginit(void) print_local_APICs(int maxcpu)
1706 for_each_online_cpu(cpu) {
1709 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1714 __apicdebuginit(void) print_PIC(void)
1717 unsigned long flags;
1719 if (!legacy_pic->nr_legacy_irqs)
1722 printk(KERN_DEBUG "\nprinting PIC contents\n");
1724 raw_spin_lock_irqsave(&i8259A_lock, flags);
1726 v = inb(0xa1) << 8 | inb(0x21);
1727 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1729 v = inb(0xa0) << 8 | inb(0x20);
1730 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1734 v = inb(0xa0) << 8 | inb(0x20);
1738 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1740 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1742 v = inb(0x4d1) << 8 | inb(0x4d0);
1743 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1746 static int __initdata show_lapic = 1;
1747 static __init int setup_show_lapic(char *arg)
1751 if (strcmp(arg, "all") == 0) {
1752 show_lapic = CONFIG_NR_CPUS;
1754 get_option(&arg, &num);
1761 __setup("show_lapic=", setup_show_lapic);
1763 __apicdebuginit(int) print_ICs(void)
1765 if (apic_verbosity == APIC_QUIET)
1770 /* don't print out if apic is not there */
1771 if (!cpu_has_apic && !apic_from_smp_config())
1774 print_local_APICs(show_lapic);
1780 fs_initcall(print_ICs);
1783 /* Where if anywhere is the i8259 connect in external int mode */
1784 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1786 void __init enable_IO_APIC(void)
1788 int i8259_apic, i8259_pin;
1791 if (!legacy_pic->nr_legacy_irqs)
1794 for(apic = 0; apic < nr_ioapics; apic++) {
1796 /* See if any of the pins is in ExtINT mode */
1797 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1798 struct IO_APIC_route_entry entry;
1799 entry = ioapic_read_entry(apic, pin);
1801 /* If the interrupt line is enabled and in ExtInt mode
1802 * I have found the pin where the i8259 is connected.
1804 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1805 ioapic_i8259.apic = apic;
1806 ioapic_i8259.pin = pin;
1812 /* Look to see what if the MP table has reported the ExtINT */
1813 /* If we could not find the appropriate pin by looking at the ioapic
1814 * the i8259 probably is not connected the ioapic but give the
1815 * mptable a chance anyway.
1817 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1818 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1819 /* Trust the MP table if nothing is setup in the hardware */
1820 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1821 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1822 ioapic_i8259.pin = i8259_pin;
1823 ioapic_i8259.apic = i8259_apic;
1825 /* Complain if the MP table and the hardware disagree */
1826 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1827 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1829 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1833 * Do not trust the IO-APIC being empty at bootup
1839 * Not an __init, needed by the reboot code
1841 void disable_IO_APIC(void)
1844 * Clear the IO-APIC before rebooting:
1848 if (!legacy_pic->nr_legacy_irqs)
1852 * If the i8259 is routed through an IOAPIC
1853 * Put that IOAPIC in virtual wire mode
1854 * so legacy interrupts can be delivered.
1856 * With interrupt-remapping, for now we will use virtual wire A mode,
1857 * as virtual wire B is little complex (need to configure both
1858 * IOAPIC RTE as well as interrupt-remapping table entry).
1859 * As this gets called during crash dump, keep this simple for now.
1861 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1862 struct IO_APIC_route_entry entry;
1864 memset(&entry, 0, sizeof(entry));
1865 entry.mask = 0; /* Enabled */
1866 entry.trigger = 0; /* Edge */
1868 entry.polarity = 0; /* High */
1869 entry.delivery_status = 0;
1870 entry.dest_mode = 0; /* Physical */
1871 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1873 entry.dest = read_apic_id();
1876 * Add it to the IO-APIC irq-routing table:
1878 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1882 * Use virtual wire A mode when interrupt remapping is enabled.
1884 if (cpu_has_apic || apic_from_smp_config())
1885 disconnect_bsp_APIC(!intr_remapping_enabled &&
1886 ioapic_i8259.pin != -1);
1889 #ifdef CONFIG_X86_32
1891 * function to set the IO-APIC physical IDs based on the
1892 * values stored in the MPC table.
1894 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1896 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1898 union IO_APIC_reg_00 reg_00;
1899 physid_mask_t phys_id_present_map;
1902 unsigned char old_id;
1903 unsigned long flags;
1906 * This is broken; anything with a real cpu count has to
1907 * circumvent this idiocy regardless.
1909 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1912 * Set the IOAPIC ID to the value stored in the MPC table.
1914 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1916 /* Read the register 0 value */
1917 raw_spin_lock_irqsave(&ioapic_lock, flags);
1918 reg_00.raw = io_apic_read(apic_id, 0);
1919 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1921 old_id = mp_ioapics[apic_id].apicid;
1923 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
1924 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1925 apic_id, mp_ioapics[apic_id].apicid);
1926 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1928 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
1932 * Sanity check, is the ID really free? Every APIC in a
1933 * system must have a unique ID or we get lots of nice
1934 * 'stuck on smp_invalidate_needed IPI wait' messages.
1936 if (apic->check_apicid_used(&phys_id_present_map,
1937 mp_ioapics[apic_id].apicid)) {
1938 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1939 apic_id, mp_ioapics[apic_id].apicid);
1940 for (i = 0; i < get_physical_broadcast(); i++)
1941 if (!physid_isset(i, phys_id_present_map))
1943 if (i >= get_physical_broadcast())
1944 panic("Max APIC ID exceeded!\n");
1945 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1947 physid_set(i, phys_id_present_map);
1948 mp_ioapics[apic_id].apicid = i;
1951 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
1952 apic_printk(APIC_VERBOSE, "Setting %d in the "
1953 "phys_id_present_map\n",
1954 mp_ioapics[apic_id].apicid);
1955 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1959 * We need to adjust the IRQ routing table
1960 * if the ID changed.
1962 if (old_id != mp_ioapics[apic_id].apicid)
1963 for (i = 0; i < mp_irq_entries; i++)
1964 if (mp_irqs[i].dstapic == old_id)
1966 = mp_ioapics[apic_id].apicid;
1969 * Update the ID register according to the right value
1970 * from the MPC table if they are different.
1972 if (mp_ioapics[apic_id].apicid == reg_00.bits.ID)
1975 apic_printk(APIC_VERBOSE, KERN_INFO
1976 "...changing IO-APIC physical APIC ID to %d ...",
1977 mp_ioapics[apic_id].apicid);
1979 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
1980 raw_spin_lock_irqsave(&ioapic_lock, flags);
1981 io_apic_write(apic_id, 0, reg_00.raw);
1982 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1987 raw_spin_lock_irqsave(&ioapic_lock, flags);
1988 reg_00.raw = io_apic_read(apic_id, 0);
1989 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1990 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
1991 printk("could not set ID!\n");
1993 apic_printk(APIC_VERBOSE, " ok.\n");
1997 void __init setup_ioapic_ids_from_mpc(void)
2003 * Don't check I/O APIC IDs for xAPIC systems. They have
2004 * no meaning without the serial APIC bus.
2006 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2007 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2009 setup_ioapic_ids_from_mpc_nocheck();
2013 int no_timer_check __initdata;
2015 static int __init notimercheck(char *s)
2020 __setup("no_timer_check", notimercheck);
2023 * There is a nasty bug in some older SMP boards, their mptable lies
2024 * about the timer IRQ. We do the following to work around the situation:
2026 * - timer IRQ defaults to IO-APIC IRQ
2027 * - if this function detects that timer IRQs are defunct, then we fall
2028 * back to ISA timer IRQs
2030 static int __init timer_irq_works(void)
2032 unsigned long t1 = jiffies;
2033 unsigned long flags;
2038 local_save_flags(flags);
2040 /* Let ten ticks pass... */
2041 mdelay((10 * 1000) / HZ);
2042 local_irq_restore(flags);
2045 * Expect a few ticks at least, to be sure some possible
2046 * glue logic does not lock up after one or two first
2047 * ticks in a non-ExtINT mode. Also the local APIC
2048 * might have cached one ExtINT interrupt. Finally, at
2049 * least one tick may be lost due to delays.
2053 if (time_after(jiffies, t1 + 4))
2059 * In the SMP+IOAPIC case it might happen that there are an unspecified
2060 * number of pending IRQ events unhandled. These cases are very rare,
2061 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2062 * better to do it this way as thus we do not have to be aware of
2063 * 'pending' interrupts in the IRQ path, except at this point.
2066 * Edge triggered needs to resend any interrupt
2067 * that was delayed but this is now handled in the device
2072 * Starting up a edge-triggered IO-APIC interrupt is
2073 * nasty - we need to make sure that we get the edge.
2074 * If it is already asserted for some reason, we need
2075 * return 1 to indicate that is was pending.
2077 * This is not complete - we should be able to fake
2078 * an edge even if it isn't on the 8259A...
2081 static unsigned int startup_ioapic_irq(struct irq_data *data)
2083 int was_pending = 0, irq = data->irq;
2084 unsigned long flags;
2086 raw_spin_lock_irqsave(&ioapic_lock, flags);
2087 if (irq < legacy_pic->nr_legacy_irqs) {
2088 legacy_pic->mask(irq);
2089 if (legacy_pic->irq_pending(irq))
2092 __unmask_ioapic(data->chip_data);
2093 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2098 static int ioapic_retrigger_irq(struct irq_data *data)
2100 struct irq_cfg *cfg = data->chip_data;
2101 unsigned long flags;
2103 raw_spin_lock_irqsave(&vector_lock, flags);
2104 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2105 raw_spin_unlock_irqrestore(&vector_lock, flags);
2111 * Level and edge triggered IO-APIC interrupts need different handling,
2112 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2113 * handled with the level-triggered descriptor, but that one has slightly
2114 * more overhead. Level-triggered interrupts cannot be handled with the
2115 * edge-triggered handler, without risking IRQ storms and other ugly
2120 void send_cleanup_vector(struct irq_cfg *cfg)
2122 cpumask_var_t cleanup_mask;
2124 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2126 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2127 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2129 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2130 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2131 free_cpumask_var(cleanup_mask);
2133 cfg->move_in_progress = 0;
2136 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2139 struct irq_pin_list *entry;
2140 u8 vector = cfg->vector;
2142 for_each_irq_pin(entry, cfg->irq_2_pin) {
2148 * With interrupt-remapping, destination information comes
2149 * from interrupt-remapping table entry.
2151 if (!irq_remapped(cfg))
2152 io_apic_write(apic, 0x11 + pin*2, dest);
2153 reg = io_apic_read(apic, 0x10 + pin*2);
2154 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2156 io_apic_modify(apic, 0x10 + pin*2, reg);
2161 * Either sets data->affinity to a valid value, and returns
2162 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2163 * leaves data->affinity untouched.
2165 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2166 unsigned int *dest_id)
2168 struct irq_cfg *cfg = data->chip_data;
2170 if (!cpumask_intersects(mask, cpu_online_mask))
2173 if (assign_irq_vector(data->irq, data->chip_data, mask))
2176 cpumask_copy(data->affinity, mask);
2178 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2183 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2186 unsigned int dest, irq = data->irq;
2187 unsigned long flags;
2190 raw_spin_lock_irqsave(&ioapic_lock, flags);
2191 ret = __ioapic_set_affinity(data, mask, &dest);
2193 /* Only the high 8 bits are valid. */
2194 dest = SET_APIC_LOGICAL_ID(dest);
2195 __target_IO_APIC_irq(irq, dest, data->chip_data);
2197 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2201 #ifdef CONFIG_INTR_REMAP
2204 * Migrate the IO-APIC irq in the presence of intr-remapping.
2206 * For both level and edge triggered, irq migration is a simple atomic
2207 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2209 * For level triggered, we eliminate the io-apic RTE modification (with the
2210 * updated vector information), by using a virtual vector (io-apic pin number).
2211 * Real vector that is used for interrupting cpu will be coming from
2212 * the interrupt-remapping table entry.
2215 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2218 struct irq_cfg *cfg = data->chip_data;
2219 unsigned int dest, irq = data->irq;
2222 if (!cpumask_intersects(mask, cpu_online_mask))
2225 if (get_irte(irq, &irte))
2228 if (assign_irq_vector(irq, cfg, mask))
2231 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2233 irte.vector = cfg->vector;
2234 irte.dest_id = IRTE_DEST(dest);
2237 * Modified the IRTE and flushes the Interrupt entry cache.
2239 modify_irte(irq, &irte);
2241 if (cfg->move_in_progress)
2242 send_cleanup_vector(cfg);
2244 cpumask_copy(data->affinity, mask);
2250 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2257 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2259 unsigned vector, me;
2265 me = smp_processor_id();
2266 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2269 struct irq_desc *desc;
2270 struct irq_cfg *cfg;
2271 irq = __this_cpu_read(vector_irq[vector]);
2276 desc = irq_to_desc(irq);
2281 raw_spin_lock(&desc->lock);
2284 * Check if the irq migration is in progress. If so, we
2285 * haven't received the cleanup request yet for this irq.
2287 if (cfg->move_in_progress)
2290 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2293 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2295 * Check if the vector that needs to be cleanedup is
2296 * registered at the cpu's IRR. If so, then this is not
2297 * the best time to clean it up. Lets clean it up in the
2298 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2301 if (irr & (1 << (vector % 32))) {
2302 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2305 __this_cpu_write(vector_irq[vector], -1);
2307 raw_spin_unlock(&desc->lock);
2313 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2317 if (likely(!cfg->move_in_progress))
2320 me = smp_processor_id();
2322 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2323 send_cleanup_vector(cfg);
2326 static void irq_complete_move(struct irq_cfg *cfg)
2328 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2331 void irq_force_complete_move(int irq)
2333 struct irq_cfg *cfg = irq_get_chip_data(irq);
2338 __irq_complete_move(cfg, cfg->vector);
2341 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2344 static void ack_apic_edge(struct irq_data *data)
2346 irq_complete_move(data->chip_data);
2351 atomic_t irq_mis_count;
2354 * IO-APIC versions below 0x20 don't support EOI register.
2355 * For the record, here is the information about various versions:
2357 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2358 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2361 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2362 * version as 0x2. This is an error with documentation and these ICH chips
2363 * use io-apic's of version 0x20.
2365 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2366 * Otherwise, we simulate the EOI message manually by changing the trigger
2367 * mode to edge and then back to level, with RTE being masked during this.
2369 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2371 struct irq_pin_list *entry;
2372 unsigned long flags;
2374 raw_spin_lock_irqsave(&ioapic_lock, flags);
2375 for_each_irq_pin(entry, cfg->irq_2_pin) {
2376 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2378 * Intr-remapping uses pin number as the virtual vector
2379 * in the RTE. Actual vector is programmed in
2380 * intr-remapping table entry. Hence for the io-apic
2381 * EOI we use the pin number.
2383 if (irq_remapped(cfg))
2384 io_apic_eoi(entry->apic, entry->pin);
2386 io_apic_eoi(entry->apic, cfg->vector);
2388 __mask_and_edge_IO_APIC_irq(entry);
2389 __unmask_and_level_IO_APIC_irq(entry);
2392 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2395 static void ack_apic_level(struct irq_data *data)
2397 struct irq_cfg *cfg = data->chip_data;
2398 int i, do_unmask_irq = 0, irq = data->irq;
2401 irq_complete_move(cfg);
2402 #ifdef CONFIG_GENERIC_PENDING_IRQ
2403 /* If we are moving the irq we need to mask it */
2404 if (unlikely(irqd_is_setaffinity_pending(data))) {
2411 * It appears there is an erratum which affects at least version 0x11
2412 * of I/O APIC (that's the 82093AA and cores integrated into various
2413 * chipsets). Under certain conditions a level-triggered interrupt is
2414 * erroneously delivered as edge-triggered one but the respective IRR
2415 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2416 * message but it will never arrive and further interrupts are blocked
2417 * from the source. The exact reason is so far unknown, but the
2418 * phenomenon was observed when two consecutive interrupt requests
2419 * from a given source get delivered to the same CPU and the source is
2420 * temporarily disabled in between.
2422 * A workaround is to simulate an EOI message manually. We achieve it
2423 * by setting the trigger mode to edge and then to level when the edge
2424 * trigger mode gets detected in the TMR of a local APIC for a
2425 * level-triggered interrupt. We mask the source for the time of the
2426 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2427 * The idea is from Manfred Spraul. --macro
2429 * Also in the case when cpu goes offline, fixup_irqs() will forward
2430 * any unhandled interrupt on the offlined cpu to the new cpu
2431 * destination that is handling the corresponding interrupt. This
2432 * interrupt forwarding is done via IPI's. Hence, in this case also
2433 * level-triggered io-apic interrupt will be seen as an edge
2434 * interrupt in the IRR. And we can't rely on the cpu's EOI
2435 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2436 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2437 * supporting EOI register, we do an explicit EOI to clear the
2438 * remote IRR and on IO-APIC's which don't have an EOI register,
2439 * we use the above logic (mask+edge followed by unmask+level) from
2440 * Manfred Spraul to clear the remote IRR.
2443 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2446 * We must acknowledge the irq before we move it or the acknowledge will
2447 * not propagate properly.
2452 * Tail end of clearing remote IRR bit (either by delivering the EOI
2453 * message via io-apic EOI register write or simulating it using
2454 * mask+edge followed by unnask+level logic) manually when the
2455 * level triggered interrupt is seen as the edge triggered interrupt
2458 if (!(v & (1 << (i & 0x1f)))) {
2459 atomic_inc(&irq_mis_count);
2461 eoi_ioapic_irq(irq, cfg);
2464 /* Now we can move and renable the irq */
2465 if (unlikely(do_unmask_irq)) {
2466 /* Only migrate the irq if the ack has been received.
2468 * On rare occasions the broadcast level triggered ack gets
2469 * delayed going to ioapics, and if we reprogram the
2470 * vector while Remote IRR is still set the irq will never
2473 * To prevent this scenario we read the Remote IRR bit
2474 * of the ioapic. This has two effects.
2475 * - On any sane system the read of the ioapic will
2476 * flush writes (and acks) going to the ioapic from
2478 * - We get to see if the ACK has actually been delivered.
2480 * Based on failed experiments of reprogramming the
2481 * ioapic entry from outside of irq context starting
2482 * with masking the ioapic entry and then polling until
2483 * Remote IRR was clear before reprogramming the
2484 * ioapic I don't trust the Remote IRR bit to be
2485 * completey accurate.
2487 * However there appears to be no other way to plug
2488 * this race, so if the Remote IRR bit is not
2489 * accurate and is causing problems then it is a hardware bug
2490 * and you can go talk to the chipset vendor about it.
2492 if (!io_apic_level_ack_pending(cfg))
2493 irq_move_masked_irq(data);
2498 #ifdef CONFIG_INTR_REMAP
2499 static void ir_ack_apic_edge(struct irq_data *data)
2504 static void ir_ack_apic_level(struct irq_data *data)
2507 eoi_ioapic_irq(data->irq, data->chip_data);
2509 #endif /* CONFIG_INTR_REMAP */
2511 static struct irq_chip ioapic_chip __read_mostly = {
2513 .irq_startup = startup_ioapic_irq,
2514 .irq_mask = mask_ioapic_irq,
2515 .irq_unmask = unmask_ioapic_irq,
2516 .irq_ack = ack_apic_edge,
2517 .irq_eoi = ack_apic_level,
2519 .irq_set_affinity = ioapic_set_affinity,
2521 .irq_retrigger = ioapic_retrigger_irq,
2524 static struct irq_chip ir_ioapic_chip __read_mostly = {
2525 .name = "IR-IO-APIC",
2526 .irq_startup = startup_ioapic_irq,
2527 .irq_mask = mask_ioapic_irq,
2528 .irq_unmask = unmask_ioapic_irq,
2529 #ifdef CONFIG_INTR_REMAP
2530 .irq_ack = ir_ack_apic_edge,
2531 .irq_eoi = ir_ack_apic_level,
2533 .irq_set_affinity = ir_ioapic_set_affinity,
2536 .irq_retrigger = ioapic_retrigger_irq,
2539 static inline void init_IO_APIC_traps(void)
2541 struct irq_cfg *cfg;
2545 * NOTE! The local APIC isn't very good at handling
2546 * multiple interrupts at the same interrupt level.
2547 * As the interrupt level is determined by taking the
2548 * vector number and shifting that right by 4, we
2549 * want to spread these out a bit so that they don't
2550 * all fall in the same interrupt level.
2552 * Also, we've got to be careful not to trash gate
2553 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2555 for_each_active_irq(irq) {
2556 cfg = irq_get_chip_data(irq);
2557 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2559 * Hmm.. We don't have an entry for this,
2560 * so default to an old-fashioned 8259
2561 * interrupt if we can..
2563 if (irq < legacy_pic->nr_legacy_irqs)
2564 legacy_pic->make_irq(irq);
2566 /* Strange. Oh, well.. */
2567 irq_set_chip(irq, &no_irq_chip);
2573 * The local APIC irq-chip implementation:
2576 static void mask_lapic_irq(struct irq_data *data)
2580 v = apic_read(APIC_LVT0);
2581 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2584 static void unmask_lapic_irq(struct irq_data *data)
2588 v = apic_read(APIC_LVT0);
2589 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2592 static void ack_lapic_irq(struct irq_data *data)
2597 static struct irq_chip lapic_chip __read_mostly = {
2598 .name = "local-APIC",
2599 .irq_mask = mask_lapic_irq,
2600 .irq_unmask = unmask_lapic_irq,
2601 .irq_ack = ack_lapic_irq,
2604 static void lapic_register_intr(int irq)
2606 irq_clear_status_flags(irq, IRQ_LEVEL);
2607 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2612 * This looks a bit hackish but it's about the only one way of sending
2613 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2614 * not support the ExtINT mode, unfortunately. We need to send these
2615 * cycles as some i82489DX-based boards have glue logic that keeps the
2616 * 8259A interrupt line asserted until INTA. --macro
2618 static inline void __init unlock_ExtINT_logic(void)
2621 struct IO_APIC_route_entry entry0, entry1;
2622 unsigned char save_control, save_freq_select;
2624 pin = find_isa_irq_pin(8, mp_INT);
2629 apic = find_isa_irq_apic(8, mp_INT);
2635 entry0 = ioapic_read_entry(apic, pin);
2636 clear_IO_APIC_pin(apic, pin);
2638 memset(&entry1, 0, sizeof(entry1));
2640 entry1.dest_mode = 0; /* physical delivery */
2641 entry1.mask = 0; /* unmask IRQ now */
2642 entry1.dest = hard_smp_processor_id();
2643 entry1.delivery_mode = dest_ExtINT;
2644 entry1.polarity = entry0.polarity;
2648 ioapic_write_entry(apic, pin, entry1);
2650 save_control = CMOS_READ(RTC_CONTROL);
2651 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2652 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2654 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2659 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2663 CMOS_WRITE(save_control, RTC_CONTROL);
2664 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2665 clear_IO_APIC_pin(apic, pin);
2667 ioapic_write_entry(apic, pin, entry0);
2670 static int disable_timer_pin_1 __initdata;
2671 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2672 static int __init disable_timer_pin_setup(char *arg)
2674 disable_timer_pin_1 = 1;
2677 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2679 int timer_through_8259 __initdata;
2682 * This code may look a bit paranoid, but it's supposed to cooperate with
2683 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2684 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2685 * fanatically on his truly buggy board.
2687 * FIXME: really need to revamp this for all platforms.
2689 static inline void __init check_timer(void)
2691 struct irq_cfg *cfg = irq_get_chip_data(0);
2692 int node = cpu_to_node(0);
2693 int apic1, pin1, apic2, pin2;
2694 unsigned long flags;
2697 local_irq_save(flags);
2700 * get/set the timer IRQ vector:
2702 legacy_pic->mask(0);
2703 assign_irq_vector(0, cfg, apic->target_cpus());
2706 * As IRQ0 is to be enabled in the 8259A, the virtual
2707 * wire has to be disabled in the local APIC. Also
2708 * timer interrupts need to be acknowledged manually in
2709 * the 8259A for the i82489DX when using the NMI
2710 * watchdog as that APIC treats NMIs as level-triggered.
2711 * The AEOI mode will finish them in the 8259A
2714 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2715 legacy_pic->init(1);
2717 pin1 = find_isa_irq_pin(0, mp_INT);
2718 apic1 = find_isa_irq_apic(0, mp_INT);
2719 pin2 = ioapic_i8259.pin;
2720 apic2 = ioapic_i8259.apic;
2722 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2723 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2724 cfg->vector, apic1, pin1, apic2, pin2);
2727 * Some BIOS writers are clueless and report the ExtINTA
2728 * I/O APIC input from the cascaded 8259A as the timer
2729 * interrupt input. So just in case, if only one pin
2730 * was found above, try it both directly and through the
2734 if (intr_remapping_enabled)
2735 panic("BIOS bug: timer not connected to IO-APIC");
2739 } else if (pin2 == -1) {
2746 * Ok, does IRQ0 through the IOAPIC work?
2749 add_pin_to_irq_node(cfg, node, apic1, pin1);
2750 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2752 /* for edge trigger, setup_ioapic_irq already
2753 * leave it unmasked.
2754 * so only need to unmask if it is level-trigger
2755 * do we really have level trigger timer?
2758 idx = find_irq_entry(apic1, pin1, mp_INT);
2759 if (idx != -1 && irq_trigger(idx))
2762 if (timer_irq_works()) {
2763 if (disable_timer_pin_1 > 0)
2764 clear_IO_APIC_pin(0, pin1);
2767 if (intr_remapping_enabled)
2768 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2769 local_irq_disable();
2770 clear_IO_APIC_pin(apic1, pin1);
2772 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2773 "8254 timer not connected to IO-APIC\n");
2775 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2776 "(IRQ0) through the 8259A ...\n");
2777 apic_printk(APIC_QUIET, KERN_INFO
2778 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2780 * legacy devices should be connected to IO APIC #0
2782 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2783 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2784 legacy_pic->unmask(0);
2785 if (timer_irq_works()) {
2786 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2787 timer_through_8259 = 1;
2791 * Cleanup, just in case ...
2793 local_irq_disable();
2794 legacy_pic->mask(0);
2795 clear_IO_APIC_pin(apic2, pin2);
2796 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2799 apic_printk(APIC_QUIET, KERN_INFO
2800 "...trying to set up timer as Virtual Wire IRQ...\n");
2802 lapic_register_intr(0);
2803 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2804 legacy_pic->unmask(0);
2806 if (timer_irq_works()) {
2807 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2810 local_irq_disable();
2811 legacy_pic->mask(0);
2812 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2813 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2815 apic_printk(APIC_QUIET, KERN_INFO
2816 "...trying to set up timer as ExtINT IRQ...\n");
2818 legacy_pic->init(0);
2819 legacy_pic->make_irq(0);
2820 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2822 unlock_ExtINT_logic();
2824 if (timer_irq_works()) {
2825 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2828 local_irq_disable();
2829 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2830 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2831 "report. Then try booting with the 'noapic' option.\n");
2833 local_irq_restore(flags);
2837 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2838 * to devices. However there may be an I/O APIC pin available for
2839 * this interrupt regardless. The pin may be left unconnected, but
2840 * typically it will be reused as an ExtINT cascade interrupt for
2841 * the master 8259A. In the MPS case such a pin will normally be
2842 * reported as an ExtINT interrupt in the MP table. With ACPI
2843 * there is no provision for ExtINT interrupts, and in the absence
2844 * of an override it would be treated as an ordinary ISA I/O APIC
2845 * interrupt, that is edge-triggered and unmasked by default. We
2846 * used to do this, but it caused problems on some systems because
2847 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2848 * the same ExtINT cascade interrupt to drive the local APIC of the
2849 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2850 * the I/O APIC in all cases now. No actual device should request
2851 * it anyway. --macro
2853 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2855 void __init setup_IO_APIC(void)
2859 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2861 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2863 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2865 * Set up IO-APIC IRQ routing.
2867 x86_init.mpparse.setup_ioapic_ids();
2870 setup_IO_APIC_irqs();
2871 init_IO_APIC_traps();
2872 if (legacy_pic->nr_legacy_irqs)
2877 * Called after all the initialization is done. If we didn't find any
2878 * APIC bugs then we can allow the modify fast path
2881 static int __init io_apic_bug_finalize(void)
2883 if (sis_apic_bug == -1)
2888 late_initcall(io_apic_bug_finalize);
2890 static void resume_ioapic_id(int ioapic_id)
2892 unsigned long flags;
2893 union IO_APIC_reg_00 reg_00;
2896 raw_spin_lock_irqsave(&ioapic_lock, flags);
2897 reg_00.raw = io_apic_read(ioapic_id, 0);
2898 if (reg_00.bits.ID != mp_ioapics[ioapic_id].apicid) {
2899 reg_00.bits.ID = mp_ioapics[ioapic_id].apicid;
2900 io_apic_write(ioapic_id, 0, reg_00.raw);
2902 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2905 static void ioapic_resume(void)
2909 for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--)
2910 resume_ioapic_id(ioapic_id);
2912 restore_ioapic_entries();
2915 static struct syscore_ops ioapic_syscore_ops = {
2916 .suspend = save_ioapic_entries,
2917 .resume = ioapic_resume,
2920 static int __init ioapic_init_ops(void)
2922 register_syscore_ops(&ioapic_syscore_ops);
2927 device_initcall(ioapic_init_ops);
2930 * Dynamic irq allocate and deallocation
2932 unsigned int create_irq_nr(unsigned int from, int node)
2934 struct irq_cfg *cfg;
2935 unsigned long flags;
2936 unsigned int ret = 0;
2939 if (from < nr_irqs_gsi)
2942 irq = alloc_irq_from(from, node);
2945 cfg = alloc_irq_cfg(irq, node);
2947 free_irq_at(irq, NULL);
2951 raw_spin_lock_irqsave(&vector_lock, flags);
2952 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
2954 raw_spin_unlock_irqrestore(&vector_lock, flags);
2957 irq_set_chip_data(irq, cfg);
2958 irq_clear_status_flags(irq, IRQ_NOREQUEST);
2960 free_irq_at(irq, cfg);
2965 int create_irq(void)
2967 int node = cpu_to_node(0);
2968 unsigned int irq_want;
2971 irq_want = nr_irqs_gsi;
2972 irq = create_irq_nr(irq_want, node);
2980 void destroy_irq(unsigned int irq)
2982 struct irq_cfg *cfg = irq_get_chip_data(irq);
2983 unsigned long flags;
2985 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
2987 if (irq_remapped(cfg))
2989 raw_spin_lock_irqsave(&vector_lock, flags);
2990 __clear_irq_vector(irq, cfg);
2991 raw_spin_unlock_irqrestore(&vector_lock, flags);
2992 free_irq_at(irq, cfg);
2996 * MSI message composition
2998 #ifdef CONFIG_PCI_MSI
2999 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3000 struct msi_msg *msg, u8 hpet_id)
3002 struct irq_cfg *cfg;
3010 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3014 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3016 if (irq_remapped(cfg)) {
3021 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3022 BUG_ON(ir_index == -1);
3024 prepare_irte(&irte, cfg->vector, dest);
3026 /* Set source-id of interrupt request */
3028 set_msi_sid(&irte, pdev);
3030 set_hpet_sid(&irte, hpet_id);
3032 modify_irte(irq, &irte);
3034 msg->address_hi = MSI_ADDR_BASE_HI;
3035 msg->data = sub_handle;
3036 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3038 MSI_ADDR_IR_INDEX1(ir_index) |
3039 MSI_ADDR_IR_INDEX2(ir_index);
3041 if (x2apic_enabled())
3042 msg->address_hi = MSI_ADDR_BASE_HI |
3043 MSI_ADDR_EXT_DEST_ID(dest);
3045 msg->address_hi = MSI_ADDR_BASE_HI;
3049 ((apic->irq_dest_mode == 0) ?
3050 MSI_ADDR_DEST_MODE_PHYSICAL:
3051 MSI_ADDR_DEST_MODE_LOGICAL) |
3052 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3053 MSI_ADDR_REDIRECTION_CPU:
3054 MSI_ADDR_REDIRECTION_LOWPRI) |
3055 MSI_ADDR_DEST_ID(dest);
3058 MSI_DATA_TRIGGER_EDGE |
3059 MSI_DATA_LEVEL_ASSERT |
3060 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3061 MSI_DATA_DELIVERY_FIXED:
3062 MSI_DATA_DELIVERY_LOWPRI) |
3063 MSI_DATA_VECTOR(cfg->vector);
3070 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3072 struct irq_cfg *cfg = data->chip_data;
3076 if (__ioapic_set_affinity(data, mask, &dest))
3079 __get_cached_msi_msg(data->msi_desc, &msg);
3081 msg.data &= ~MSI_DATA_VECTOR_MASK;
3082 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3083 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3084 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3086 __write_msi_msg(data->msi_desc, &msg);
3090 #ifdef CONFIG_INTR_REMAP
3092 * Migrate the MSI irq to another cpumask. This migration is
3093 * done in the process context using interrupt-remapping hardware.
3096 ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3099 struct irq_cfg *cfg = data->chip_data;
3100 unsigned int dest, irq = data->irq;
3103 if (get_irte(irq, &irte))
3106 if (__ioapic_set_affinity(data, mask, &dest))
3109 irte.vector = cfg->vector;
3110 irte.dest_id = IRTE_DEST(dest);
3113 * atomically update the IRTE with the new destination and vector.
3115 modify_irte(irq, &irte);
3118 * After this point, all the interrupts will start arriving
3119 * at the new destination. So, time to cleanup the previous
3120 * vector allocation.
3122 if (cfg->move_in_progress)
3123 send_cleanup_vector(cfg);
3129 #endif /* CONFIG_SMP */
3132 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3133 * which implement the MSI or MSI-X Capability Structure.
3135 static struct irq_chip msi_chip = {
3137 .irq_unmask = unmask_msi_irq,
3138 .irq_mask = mask_msi_irq,
3139 .irq_ack = ack_apic_edge,
3141 .irq_set_affinity = msi_set_affinity,
3143 .irq_retrigger = ioapic_retrigger_irq,
3146 static struct irq_chip msi_ir_chip = {
3147 .name = "IR-PCI-MSI",
3148 .irq_unmask = unmask_msi_irq,
3149 .irq_mask = mask_msi_irq,
3150 #ifdef CONFIG_INTR_REMAP
3151 .irq_ack = ir_ack_apic_edge,
3153 .irq_set_affinity = ir_msi_set_affinity,
3156 .irq_retrigger = ioapic_retrigger_irq,
3160 * Map the PCI dev to the corresponding remapping hardware unit
3161 * and allocate 'nvec' consecutive interrupt-remapping table entries
3164 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3166 struct intel_iommu *iommu;
3169 iommu = map_dev_to_ir(dev);
3172 "Unable to map PCI %s to iommu\n", pci_name(dev));
3176 index = alloc_irte(iommu, irq, nvec);
3179 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3186 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3188 struct irq_chip *chip = &msi_chip;
3192 ret = msi_compose_msg(dev, irq, &msg, -1);
3196 irq_set_msi_desc(irq, msidesc);
3197 write_msi_msg(irq, &msg);
3199 if (irq_remapped(irq_get_chip_data(irq))) {
3200 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3201 chip = &msi_ir_chip;
3204 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3206 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3211 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3213 int node, ret, sub_handle, index = 0;
3214 unsigned int irq, irq_want;
3215 struct msi_desc *msidesc;
3216 struct intel_iommu *iommu = NULL;
3218 /* x86 doesn't support multiple MSI yet */
3219 if (type == PCI_CAP_ID_MSI && nvec > 1)
3222 node = dev_to_node(&dev->dev);
3223 irq_want = nr_irqs_gsi;
3225 list_for_each_entry(msidesc, &dev->msi_list, list) {
3226 irq = create_irq_nr(irq_want, node);
3230 if (!intr_remapping_enabled)
3235 * allocate the consecutive block of IRTE's
3238 index = msi_alloc_irte(dev, irq, nvec);
3244 iommu = map_dev_to_ir(dev);
3250 * setup the mapping between the irq and the IRTE
3251 * base index, the sub_handle pointing to the
3252 * appropriate interrupt remap table entry.
3254 set_irte_irq(irq, iommu, index, sub_handle);
3257 ret = setup_msi_irq(dev, msidesc, irq);
3269 void native_teardown_msi_irq(unsigned int irq)
3274 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3277 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3280 struct irq_cfg *cfg = data->chip_data;
3281 unsigned int dest, irq = data->irq;
3284 if (__ioapic_set_affinity(data, mask, &dest))
3287 dmar_msi_read(irq, &msg);
3289 msg.data &= ~MSI_DATA_VECTOR_MASK;
3290 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3291 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3292 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3293 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3295 dmar_msi_write(irq, &msg);
3300 #endif /* CONFIG_SMP */
3302 static struct irq_chip dmar_msi_type = {
3304 .irq_unmask = dmar_msi_unmask,
3305 .irq_mask = dmar_msi_mask,
3306 .irq_ack = ack_apic_edge,
3308 .irq_set_affinity = dmar_msi_set_affinity,
3310 .irq_retrigger = ioapic_retrigger_irq,
3313 int arch_setup_dmar_msi(unsigned int irq)
3318 ret = msi_compose_msg(NULL, irq, &msg, -1);
3321 dmar_msi_write(irq, &msg);
3322 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3328 #ifdef CONFIG_HPET_TIMER
3331 static int hpet_msi_set_affinity(struct irq_data *data,
3332 const struct cpumask *mask, bool force)
3334 struct irq_cfg *cfg = data->chip_data;
3338 if (__ioapic_set_affinity(data, mask, &dest))
3341 hpet_msi_read(data->handler_data, &msg);
3343 msg.data &= ~MSI_DATA_VECTOR_MASK;
3344 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3345 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3346 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3348 hpet_msi_write(data->handler_data, &msg);
3353 #endif /* CONFIG_SMP */
3355 static struct irq_chip ir_hpet_msi_type = {
3356 .name = "IR-HPET_MSI",
3357 .irq_unmask = hpet_msi_unmask,
3358 .irq_mask = hpet_msi_mask,
3359 #ifdef CONFIG_INTR_REMAP
3360 .irq_ack = ir_ack_apic_edge,
3362 .irq_set_affinity = ir_msi_set_affinity,
3365 .irq_retrigger = ioapic_retrigger_irq,
3368 static struct irq_chip hpet_msi_type = {
3370 .irq_unmask = hpet_msi_unmask,
3371 .irq_mask = hpet_msi_mask,
3372 .irq_ack = ack_apic_edge,
3374 .irq_set_affinity = hpet_msi_set_affinity,
3376 .irq_retrigger = ioapic_retrigger_irq,
3379 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3381 struct irq_chip *chip = &hpet_msi_type;
3385 if (intr_remapping_enabled) {
3386 struct intel_iommu *iommu = map_hpet_to_ir(id);
3392 index = alloc_irte(iommu, irq, 1);
3397 ret = msi_compose_msg(NULL, irq, &msg, id);
3401 hpet_msi_write(irq_get_handler_data(irq), &msg);
3402 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3403 if (irq_remapped(irq_get_chip_data(irq)))
3404 chip = &ir_hpet_msi_type;
3406 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3411 #endif /* CONFIG_PCI_MSI */
3413 * Hypertransport interrupt support
3415 #ifdef CONFIG_HT_IRQ
3419 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3421 struct ht_irq_msg msg;
3422 fetch_ht_irq_msg(irq, &msg);
3424 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3425 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3427 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3428 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3430 write_ht_irq_msg(irq, &msg);
3434 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3436 struct irq_cfg *cfg = data->chip_data;
3439 if (__ioapic_set_affinity(data, mask, &dest))
3442 target_ht_irq(data->irq, dest, cfg->vector);
3448 static struct irq_chip ht_irq_chip = {
3450 .irq_mask = mask_ht_irq,
3451 .irq_unmask = unmask_ht_irq,
3452 .irq_ack = ack_apic_edge,
3454 .irq_set_affinity = ht_set_affinity,
3456 .irq_retrigger = ioapic_retrigger_irq,
3459 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3461 struct irq_cfg *cfg;
3468 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3470 struct ht_irq_msg msg;
3473 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3474 apic->target_cpus());
3476 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3480 HT_IRQ_LOW_DEST_ID(dest) |
3481 HT_IRQ_LOW_VECTOR(cfg->vector) |
3482 ((apic->irq_dest_mode == 0) ?
3483 HT_IRQ_LOW_DM_PHYSICAL :
3484 HT_IRQ_LOW_DM_LOGICAL) |
3485 HT_IRQ_LOW_RQEOI_EDGE |
3486 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3487 HT_IRQ_LOW_MT_FIXED :
3488 HT_IRQ_LOW_MT_ARBITRATED) |
3489 HT_IRQ_LOW_IRQ_MASKED;
3491 write_ht_irq_msg(irq, &msg);
3493 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3494 handle_edge_irq, "edge");
3496 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3500 #endif /* CONFIG_HT_IRQ */
3503 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3505 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3510 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3512 setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg,
3513 attr->trigger, attr->polarity);
3517 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3518 struct io_apic_irq_attr *attr)
3520 unsigned int id = attr->ioapic, pin = attr->ioapic_pin;
3523 /* Avoid redundant programming */
3524 if (test_bit(pin, mp_ioapic_routing[id].pin_programmed)) {
3525 pr_debug("Pin %d-%d already programmed\n",
3526 mp_ioapics[id].apicid, pin);
3529 ret = io_apic_setup_irq_pin(irq, node, attr);
3531 set_bit(pin, mp_ioapic_routing[id].pin_programmed);
3535 static int __init io_apic_get_redir_entries(int ioapic)
3537 union IO_APIC_reg_01 reg_01;
3538 unsigned long flags;
3540 raw_spin_lock_irqsave(&ioapic_lock, flags);
3541 reg_01.raw = io_apic_read(ioapic, 1);
3542 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3544 /* The register returns the maximum index redir index
3545 * supported, which is one less than the total number of redir
3548 return reg_01.bits.entries + 1;
3551 static void __init probe_nr_irqs_gsi(void)
3555 nr = gsi_top + NR_IRQS_LEGACY;
3556 if (nr > nr_irqs_gsi)
3559 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3562 int get_nr_irqs_gsi(void)
3567 #ifdef CONFIG_SPARSE_IRQ
3568 int __init arch_probe_nr_irqs(void)
3572 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3573 nr_irqs = NR_VECTORS * nr_cpu_ids;
3575 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3576 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3578 * for MSI and HT dyn irq
3580 nr += nr_irqs_gsi * 16;
3585 return NR_IRQS_LEGACY;
3589 int io_apic_set_pci_routing(struct device *dev, int irq,
3590 struct io_apic_irq_attr *irq_attr)
3594 if (!IO_APIC_IRQ(irq)) {
3595 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3600 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3602 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3605 #ifdef CONFIG_X86_32
3606 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3608 union IO_APIC_reg_00 reg_00;
3609 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3611 unsigned long flags;
3615 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3616 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3617 * supports up to 16 on one shared APIC bus.
3619 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3620 * advantage of new APIC bus architecture.
3623 if (physids_empty(apic_id_map))
3624 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3626 raw_spin_lock_irqsave(&ioapic_lock, flags);
3627 reg_00.raw = io_apic_read(ioapic, 0);
3628 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3630 if (apic_id >= get_physical_broadcast()) {
3631 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3632 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3633 apic_id = reg_00.bits.ID;
3637 * Every APIC in a system must have a unique ID or we get lots of nice
3638 * 'stuck on smp_invalidate_needed IPI wait' messages.
3640 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3642 for (i = 0; i < get_physical_broadcast(); i++) {
3643 if (!apic->check_apicid_used(&apic_id_map, i))
3647 if (i == get_physical_broadcast())
3648 panic("Max apic_id exceeded!\n");
3650 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3651 "trying %d\n", ioapic, apic_id, i);
3656 apic->apicid_to_cpu_present(apic_id, &tmp);
3657 physids_or(apic_id_map, apic_id_map, tmp);
3659 if (reg_00.bits.ID != apic_id) {
3660 reg_00.bits.ID = apic_id;
3662 raw_spin_lock_irqsave(&ioapic_lock, flags);
3663 io_apic_write(ioapic, 0, reg_00.raw);
3664 reg_00.raw = io_apic_read(ioapic, 0);
3665 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3668 if (reg_00.bits.ID != apic_id) {
3669 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3674 apic_printk(APIC_VERBOSE, KERN_INFO
3675 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3680 static u8 __init io_apic_unique_id(u8 id)
3682 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3683 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3684 return io_apic_get_unique_id(nr_ioapics, id);
3689 static u8 __init io_apic_unique_id(u8 id)
3692 DECLARE_BITMAP(used, 256);
3694 bitmap_zero(used, 256);
3695 for (i = 0; i < nr_ioapics; i++) {
3696 struct mpc_ioapic *ia = &mp_ioapics[i];
3697 __set_bit(ia->apicid, used);
3699 if (!test_bit(id, used))
3701 return find_first_zero_bit(used, 256);
3705 static int __init io_apic_get_version(int ioapic)
3707 union IO_APIC_reg_01 reg_01;
3708 unsigned long flags;
3710 raw_spin_lock_irqsave(&ioapic_lock, flags);
3711 reg_01.raw = io_apic_read(ioapic, 1);
3712 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3714 return reg_01.bits.version;
3717 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3719 int ioapic, pin, idx;
3721 if (skip_ioapic_setup)
3724 ioapic = mp_find_ioapic(gsi);
3728 pin = mp_find_ioapic_pin(ioapic, gsi);
3732 idx = find_irq_entry(ioapic, pin, mp_INT);
3736 *trigger = irq_trigger(idx);
3737 *polarity = irq_polarity(idx);
3742 * This function currently is only a helper for the i386 smp boot process where
3743 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3744 * so mask in all cases should simply be apic->target_cpus()
3747 void __init setup_ioapic_dest(void)
3749 int pin, ioapic, irq, irq_entry;
3750 const struct cpumask *mask;
3751 struct irq_data *idata;
3753 if (skip_ioapic_setup == 1)
3756 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3757 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3758 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3759 if (irq_entry == -1)
3761 irq = pin_2_irq(irq_entry, ioapic, pin);
3763 if ((ioapic > 0) && (irq > 16))
3766 idata = irq_get_irq_data(irq);
3769 * Honour affinities which have been set in early boot
3771 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3772 mask = idata->affinity;
3774 mask = apic->target_cpus();
3776 if (intr_remapping_enabled)
3777 ir_ioapic_set_affinity(idata, mask, false);
3779 ioapic_set_affinity(idata, mask, false);
3785 #define IOAPIC_RESOURCE_NAME_SIZE 11
3787 static struct resource *ioapic_resources;
3789 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3792 struct resource *res;
3796 if (nr_ioapics <= 0)
3799 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3802 mem = alloc_bootmem(n);
3805 mem += sizeof(struct resource) * nr_ioapics;
3807 for (i = 0; i < nr_ioapics; i++) {
3809 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3810 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3811 mem += IOAPIC_RESOURCE_NAME_SIZE;
3814 ioapic_resources = res;
3819 void __init ioapic_and_gsi_init(void)
3821 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3822 struct resource *ioapic_res;
3825 ioapic_res = ioapic_setup_resources(nr_ioapics);
3826 for (i = 0; i < nr_ioapics; i++) {
3827 if (smp_found_config) {
3828 ioapic_phys = mp_ioapics[i].apicaddr;
3829 #ifdef CONFIG_X86_32
3832 "WARNING: bogus zero IO-APIC "
3833 "address found in MPTABLE, "
3834 "disabling IO/APIC support!\n");
3835 smp_found_config = 0;
3836 skip_ioapic_setup = 1;
3837 goto fake_ioapic_page;
3841 #ifdef CONFIG_X86_32
3844 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3845 ioapic_phys = __pa(ioapic_phys);
3847 set_fixmap_nocache(idx, ioapic_phys);
3848 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3849 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3853 ioapic_res->start = ioapic_phys;
3854 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3858 probe_nr_irqs_gsi();
3861 void __init ioapic_insert_resources(void)
3864 struct resource *r = ioapic_resources;
3869 "IO APIC resources couldn't be allocated.\n");
3873 for (i = 0; i < nr_ioapics; i++) {
3874 insert_resource(&iomem_resource, r);
3879 int mp_find_ioapic(u32 gsi)
3883 if (nr_ioapics == 0)
3886 /* Find the IOAPIC that manages this GSI. */
3887 for (i = 0; i < nr_ioapics; i++) {
3888 if ((gsi >= mp_gsi_routing[i].gsi_base)
3889 && (gsi <= mp_gsi_routing[i].gsi_end))
3893 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3897 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3899 if (WARN_ON(ioapic == -1))
3901 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
3904 return gsi - mp_gsi_routing[ioapic].gsi_base;
3907 static __init int bad_ioapic(unsigned long address)
3909 if (nr_ioapics >= MAX_IO_APICS) {
3910 printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded "
3911 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
3915 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
3916 " found in table, skipping!\n");
3922 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3927 if (bad_ioapic(address))
3932 mp_ioapics[idx].type = MP_IOAPIC;
3933 mp_ioapics[idx].flags = MPC_APIC_USABLE;
3934 mp_ioapics[idx].apicaddr = address;
3936 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3937 mp_ioapics[idx].apicid = io_apic_unique_id(id);
3938 mp_ioapics[idx].apicver = io_apic_get_version(idx);
3941 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3942 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3944 entries = io_apic_get_redir_entries(idx);
3945 mp_gsi_routing[idx].gsi_base = gsi_base;
3946 mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
3949 * The number of IO-APIC IRQ registers (== #pins):
3951 nr_ioapic_registers[idx] = entries;
3953 if (mp_gsi_routing[idx].gsi_end >= gsi_top)
3954 gsi_top = mp_gsi_routing[idx].gsi_end + 1;
3956 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
3957 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
3958 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
3959 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
3964 /* Enable IOAPIC early just for system timer */
3965 void __init pre_init_apic_IRQ0(void)
3967 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
3969 printk(KERN_INFO "Early APIC setup for system timer0\n");
3971 physid_set_mask_of_physid(boot_cpu_physical_apicid,
3972 &phys_cpu_present_map);
3976 io_apic_setup_irq_pin(0, 0, &attr);
3977 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,