2 * Shared support code for AMD K8 northbridges and derivates.
3 * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/types.h>
9 #include <linux/slab.h>
10 #include <linux/init.h>
11 #include <linux/errno.h>
12 #include <linux/module.h>
13 #include <linux/spinlock.h>
14 #include <asm/amd_nb.h>
16 static u32 *flush_words;
18 const struct pci_device_id amd_nb_misc_ids[] = {
19 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
20 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
21 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
24 EXPORT_SYMBOL(amd_nb_misc_ids);
26 static struct pci_device_id amd_nb_link_ids[] = {
27 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
31 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
38 struct amd_northbridge_info amd_northbridges;
39 EXPORT_SYMBOL(amd_northbridges);
41 static struct pci_dev *next_northbridge(struct pci_dev *dev,
42 const struct pci_device_id *ids)
45 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
48 } while (!pci_match_id(ids, dev));
52 int amd_cache_northbridges(void)
55 struct amd_northbridge *nb;
56 struct pci_dev *misc, *link;
62 while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
68 nb = kzalloc(i * sizeof(struct amd_northbridge), GFP_KERNEL);
72 amd_northbridges.nb = nb;
73 amd_northbridges.num = i;
76 for (i = 0; i != amd_nb_num(); i++) {
77 node_to_amd_nb(i)->misc = misc =
78 next_northbridge(misc, amd_nb_misc_ids);
79 node_to_amd_nb(i)->link = link =
80 next_northbridge(link, amd_nb_link_ids);
83 /* some CPU families (e.g. family 0x11) do not support GART */
84 if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
85 boot_cpu_data.x86 == 0x15)
86 amd_northbridges.flags |= AMD_NB_GART;
89 * Some CPU families support L3 Cache Index Disable. There are some
90 * limitations because of E382 and E388 on family 0x10.
92 if (boot_cpu_data.x86 == 0x10 &&
93 boot_cpu_data.x86_model >= 0x8 &&
94 (boot_cpu_data.x86_model > 0x9 ||
95 boot_cpu_data.x86_mask >= 0x1))
96 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
98 if (boot_cpu_data.x86 == 0x15)
99 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
101 /* L3 cache partitioning is supported on family 0x15 */
102 if (boot_cpu_data.x86 == 0x15)
103 amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
107 EXPORT_SYMBOL_GPL(amd_cache_northbridges);
110 * Ignores subdevice/subvendor but as far as I can figure out
111 * they're useless anyways
113 bool __init early_is_amd_nb(u32 device)
115 const struct pci_device_id *id;
116 u32 vendor = device & 0xffff;
119 for (id = amd_nb_misc_ids; id->vendor; id++)
120 if (vendor == id->vendor && device == id->device)
125 struct resource *amd_get_mmconfig_range(struct resource *res)
129 unsigned segn_busn_bits;
131 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
134 /* assume all cpus from fam10h have mmconfig */
135 if (boot_cpu_data.x86 < 0x10)
138 address = MSR_FAM10H_MMIO_CONF_BASE;
139 rdmsrl(address, msr);
141 /* mmconfig is not enabled */
142 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
145 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
147 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
148 FAM10H_MMIO_CONF_BUSRANGE_MASK;
150 res->flags = IORESOURCE_MEM;
152 res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
156 int amd_get_subcaches(int cpu)
158 struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
162 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
165 pci_read_config_dword(link, 0x1d4, &mask);
167 cuid = cpu_data(cpu).compute_unit_id;
168 return (mask >> (4 * cuid)) & 0xf;
171 int amd_set_subcaches(int cpu, int mask)
173 static unsigned int reset, ban;
174 struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
178 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
181 /* if necessary, collect reset state of L3 partitioning and BAN mode */
183 pci_read_config_dword(nb->link, 0x1d4, &reset);
184 pci_read_config_dword(nb->misc, 0x1b8, &ban);
188 /* deactivate BAN mode if any subcaches are to be disabled */
190 pci_read_config_dword(nb->misc, 0x1b8, ®);
191 pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
194 cuid = cpu_data(cpu).compute_unit_id;
196 mask |= (0xf ^ (1 << cuid)) << 26;
198 pci_write_config_dword(nb->link, 0x1d4, mask);
200 /* reset BAN mode if L3 partitioning returned to reset state */
201 pci_read_config_dword(nb->link, 0x1d4, ®);
203 pci_read_config_dword(nb->misc, 0x1b8, ®);
205 pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
211 static int amd_cache_gart(void)
215 if (!amd_nb_has_feature(AMD_NB_GART))
218 flush_words = kmalloc(amd_nb_num() * sizeof(u32), GFP_KERNEL);
220 amd_northbridges.flags &= ~AMD_NB_GART;
224 for (i = 0; i != amd_nb_num(); i++)
225 pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c,
231 void amd_flush_garts(void)
235 static DEFINE_SPINLOCK(gart_lock);
237 if (!amd_nb_has_feature(AMD_NB_GART))
240 /* Avoid races between AGP and IOMMU. In theory it's not needed
241 but I'm not sure if the hardware won't lose flush requests
242 when another is pending. This whole thing is so expensive anyways
243 that it doesn't matter to serialize more. -AK */
244 spin_lock_irqsave(&gart_lock, flags);
246 for (i = 0; i < amd_nb_num(); i++) {
247 pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
251 for (i = 0; i < amd_nb_num(); i++) {
253 /* Make sure the hardware actually executed the flush*/
255 pci_read_config_dword(node_to_amd_nb(i)->misc,
262 spin_unlock_irqrestore(&gart_lock, flags);
264 pr_notice("nothing to flush?\n");
266 EXPORT_SYMBOL_GPL(amd_flush_garts);
268 static __init int init_amd_nbs(void)
272 err = amd_cache_northbridges();
275 pr_notice("Cannot enumerate AMD northbridges\n");
277 if (amd_cache_gart() < 0)
278 pr_notice("Cannot initialize GART flush words, GART support disabled\n");
283 /* This has to go after the PCI subsystem */
284 fs_initcall(init_amd_nbs);