1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
22 #include <asm/desc_defs.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
35 * Default implementation of macro that returns current
36 * instruction pointer ("program counter").
38 static inline void *current_text_addr(void)
42 asm volatile("mov $1f, %0; 1:":"=r" (pc));
47 #ifdef CONFIG_X86_VSMP
48 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
49 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
51 # define ARCH_MIN_TASKALIGN 16
52 # define ARCH_MIN_MMSTRUCT_ALIGN 0
56 * CPU type and hardware bug flags. Kept separately for each CPU.
57 * Members of this structure are referenced in head.S, so think twice
58 * before touching them. [mj]
62 __u8 x86; /* CPU family */
63 __u8 x86_vendor; /* CPU vendor */
67 char wp_works_ok; /* It doesn't on 386's */
69 /* Problems on some 486Dx4's and old 386's: */
78 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
83 /* CPUID returned core id bits: */
85 /* Max extended CPUID function supported: */
86 __u32 extended_cpuid_level;
87 /* Maximum supported CPUID level, -1=no CPUID: */
89 __u32 x86_capability[NCAPINTS];
90 char x86_vendor_id[16];
91 char x86_model_id[64];
92 /* in KB - valid for CPUS which support this call: */
94 int x86_cache_alignment; /* In bytes */
96 unsigned long loops_per_jiffy;
97 /* cpuid returned max cores value: */
101 u16 x86_clflush_size;
103 /* number of cores as seen by the OS: */
105 /* Physical processor id: */
109 /* Compute unit id */
111 /* Index into per_cpu list: */
115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
117 #define X86_VENDOR_INTEL 0
118 #define X86_VENDOR_CYRIX 1
119 #define X86_VENDOR_AMD 2
120 #define X86_VENDOR_UMC 3
121 #define X86_VENDOR_CENTAUR 5
122 #define X86_VENDOR_TRANSMETA 7
123 #define X86_VENDOR_NSC 8
124 #define X86_VENDOR_NUM 9
126 #define X86_VENDOR_UNKNOWN 0xff
129 * capabilities of CPUs
131 extern struct cpuinfo_x86 boot_cpu_data;
132 extern struct cpuinfo_x86 new_cpu_data;
134 extern struct tss_struct doublefault_tss;
135 extern __u32 cpu_caps_cleared[NCAPINTS];
136 extern __u32 cpu_caps_set[NCAPINTS];
139 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
140 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
142 #define cpu_info boot_cpu_data
143 #define cpu_data(cpu) boot_cpu_data
146 extern const struct seq_operations cpuinfo_op;
148 static inline int hlt_works(int cpu)
151 return cpu_data(cpu).hlt_works_ok;
157 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
159 extern void cpu_detect(struct cpuinfo_x86 *c);
161 extern struct pt_regs *idle_regs(struct pt_regs *);
163 extern void early_cpu_init(void);
164 extern void identify_boot_cpu(void);
165 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
166 extern void print_cpu_info(struct cpuinfo_x86 *);
167 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
168 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
169 extern unsigned short num_cache_leaves;
171 extern void detect_extended_topology(struct cpuinfo_x86 *c);
172 extern void detect_ht(struct cpuinfo_x86 *c);
174 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
175 unsigned int *ecx, unsigned int *edx)
177 /* ecx is often an input as well as an output. */
183 : "0" (*eax), "2" (*ecx)
187 static inline void load_cr3(pgd_t *pgdir)
189 write_cr3(__pa(pgdir));
193 /* This is the TSS defined by the hardware. */
195 unsigned short back_link, __blh;
197 unsigned short ss0, __ss0h;
199 /* ss1 caches MSR_IA32_SYSENTER_CS: */
200 unsigned short ss1, __ss1h;
202 unsigned short ss2, __ss2h;
214 unsigned short es, __esh;
215 unsigned short cs, __csh;
216 unsigned short ss, __ssh;
217 unsigned short ds, __dsh;
218 unsigned short fs, __fsh;
219 unsigned short gs, __gsh;
220 unsigned short ldt, __ldth;
221 unsigned short trace;
222 unsigned short io_bitmap_base;
224 } __attribute__((packed));
238 } __attribute__((packed)) ____cacheline_aligned;
244 #define IO_BITMAP_BITS 65536
245 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
246 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
247 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
248 #define INVALID_IO_BITMAP_OFFSET 0x8000
252 * The hardware state:
254 struct x86_hw_tss x86_tss;
257 * The extra 1 is there because the CPU will access an
258 * additional byte beyond the end of the IO permission
259 * bitmap. The extra byte must be all 1 bits, and must
260 * be within the limit.
262 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
265 * .. and then another 0x100 bytes for the emergency kernel stack:
267 unsigned long stack[64];
269 } ____cacheline_aligned;
271 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
274 * Save the original ist values for checking stack pointers during debugging
277 unsigned long ist[7];
280 #define MXCSR_DEFAULT 0x1f80
282 struct i387_fsave_struct {
283 u32 cwd; /* FPU Control Word */
284 u32 swd; /* FPU Status Word */
285 u32 twd; /* FPU Tag Word */
286 u32 fip; /* FPU IP Offset */
287 u32 fcs; /* FPU IP Selector */
288 u32 foo; /* FPU Operand Pointer Offset */
289 u32 fos; /* FPU Operand Pointer Selector */
291 /* 8*10 bytes for each FP-reg = 80 bytes: */
294 /* Software status information [not touched by FSAVE ]: */
298 struct i387_fxsave_struct {
299 u16 cwd; /* Control Word */
300 u16 swd; /* Status Word */
301 u16 twd; /* Tag Word */
302 u16 fop; /* Last Instruction Opcode */
305 u64 rip; /* Instruction Pointer */
306 u64 rdp; /* Data Pointer */
309 u32 fip; /* FPU IP Offset */
310 u32 fcs; /* FPU IP Selector */
311 u32 foo; /* FPU Operand Offset */
312 u32 fos; /* FPU Operand Selector */
315 u32 mxcsr; /* MXCSR Register State */
316 u32 mxcsr_mask; /* MXCSR Mask */
318 /* 8*16 bytes for each FP-reg = 128 bytes: */
321 /* 16*16 bytes for each XMM-reg = 256 bytes: */
331 } __attribute__((aligned(16)));
333 struct i387_soft_struct {
341 /* 8*10 bytes for each FP-reg = 80 bytes: */
349 struct math_emu_info *info;
354 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
358 struct xsave_hdr_struct {
362 } __attribute__((packed));
364 struct xsave_struct {
365 struct i387_fxsave_struct i387;
366 struct xsave_hdr_struct xsave_hdr;
367 struct ymmh_struct ymmh;
368 /* new processor state extensions will go here */
369 } __attribute__ ((packed, aligned (64)));
371 union thread_xstate {
372 struct i387_fsave_struct fsave;
373 struct i387_fxsave_struct fxsave;
374 struct i387_soft_struct soft;
375 struct xsave_struct xsave;
379 union thread_xstate *state;
383 DECLARE_PER_CPU(struct orig_ist, orig_ist);
385 union irq_stack_union {
386 char irq_stack[IRQ_STACK_SIZE];
388 * GCC hardcodes the stack canary as %gs:40. Since the
389 * irq_stack is the object at %gs:0, we reserve the bottom
390 * 48 bytes of the irq stack for the canary.
394 unsigned long stack_canary;
398 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
399 DECLARE_INIT_PER_CPU(irq_stack_union);
401 DECLARE_PER_CPU(char *, irq_stack_ptr);
402 DECLARE_PER_CPU(unsigned int, irq_count);
403 extern unsigned long kernel_eflags;
404 extern asmlinkage void ignore_sysret(void);
405 int is_debug_stack(unsigned long addr);
406 void debug_stack_set_zero(void);
407 void debug_stack_reset(void);
409 #ifdef CONFIG_CC_STACKPROTECTOR
411 * Make sure stack canary segment base is cached-aligned:
412 * "For Intel Atom processors, avoid non zero segment base address
413 * that is not aligned to cache line boundary at all cost."
414 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
416 struct stack_canary {
417 char __pad[20]; /* canary at %gs:20 */
418 unsigned long canary;
420 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
422 static inline int is_debug_stack(unsigned long addr) { return 0; }
423 static inline void debug_stack_set_zero(void) { }
424 static inline void debug_stack_reset(void) { }
427 extern unsigned int xstate_size;
428 extern void free_thread_xstate(struct task_struct *);
429 extern struct kmem_cache *task_xstate_cachep;
433 struct thread_struct {
434 /* Cached TLS descriptors: */
435 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
439 unsigned long sysenter_cs;
441 unsigned long usersp; /* Copy from PDA */
444 unsigned short fsindex;
445 unsigned short gsindex;
454 /* Save middle states of ptrace breakpoints */
455 struct perf_event *ptrace_bps[HBP_NUM];
456 /* Debug status used for traps, single steps, etc... */
457 unsigned long debugreg6;
458 /* Keep track of the exact dr7 value set by the user */
459 unsigned long ptrace_dr7;
462 unsigned long trap_no;
463 unsigned long error_code;
464 /* floating point and extended processor state */
467 /* Virtual 86 mode info */
468 struct vm86_struct __user *vm86_info;
469 unsigned long screen_bitmap;
470 unsigned long v86flags;
471 unsigned long v86mask;
472 unsigned long saved_sp0;
473 unsigned int saved_fs;
474 unsigned int saved_gs;
476 /* IO permissions: */
477 unsigned long *io_bitmap_ptr;
479 /* Max allowed port in the bitmap, in bytes: */
480 unsigned io_bitmap_max;
483 static inline unsigned long native_get_debugreg(int regno)
485 unsigned long val = 0; /* Damn you, gcc! */
489 asm("mov %%db0, %0" :"=r" (val));
492 asm("mov %%db1, %0" :"=r" (val));
495 asm("mov %%db2, %0" :"=r" (val));
498 asm("mov %%db3, %0" :"=r" (val));
501 asm("mov %%db6, %0" :"=r" (val));
504 asm("mov %%db7, %0" :"=r" (val));
512 static inline void native_set_debugreg(int regno, unsigned long value)
516 asm("mov %0, %%db0" ::"r" (value));
519 asm("mov %0, %%db1" ::"r" (value));
522 asm("mov %0, %%db2" ::"r" (value));
525 asm("mov %0, %%db3" ::"r" (value));
528 asm("mov %0, %%db6" ::"r" (value));
531 asm("mov %0, %%db7" ::"r" (value));
539 * Set IOPL bits in EFLAGS from given mask
541 static inline void native_set_iopl_mask(unsigned mask)
546 asm volatile ("pushfl;"
553 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
558 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
560 tss->x86_tss.sp0 = thread->sp0;
562 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
563 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
564 tss->x86_tss.ss1 = thread->sysenter_cs;
565 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
570 static inline void native_swapgs(void)
573 asm volatile("swapgs" ::: "memory");
577 #ifdef CONFIG_PARAVIRT
578 #include <asm/paravirt.h>
580 #define __cpuid native_cpuid
581 #define paravirt_enabled() 0
584 * These special macros can be used to get or set a debugging register
586 #define get_debugreg(var, register) \
587 (var) = native_get_debugreg(register)
588 #define set_debugreg(value, register) \
589 native_set_debugreg(register, value)
591 static inline void load_sp0(struct tss_struct *tss,
592 struct thread_struct *thread)
594 native_load_sp0(tss, thread);
597 #define set_iopl_mask native_set_iopl_mask
598 #endif /* CONFIG_PARAVIRT */
601 * Save the cr4 feature set we're using (ie
602 * Pentium 4MB enable and PPro Global page
603 * enable), so that any CPU's that boot up
604 * after us can get the correct flags.
606 extern unsigned long mmu_cr4_features;
608 static inline void set_in_cr4(unsigned long mask)
612 mmu_cr4_features |= mask;
618 static inline void clear_in_cr4(unsigned long mask)
622 mmu_cr4_features &= ~mask;
634 * create a kernel thread without removing it from tasklists
636 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
638 /* Free all resources held by a thread. */
639 extern void release_thread(struct task_struct *);
641 /* Prepare to copy thread state - unlazy all lazy state */
642 extern void prepare_to_copy(struct task_struct *tsk);
644 unsigned long get_wchan(struct task_struct *p);
647 * Generic CPUID function
648 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
649 * resulting in stale register contents being returned.
651 static inline void cpuid(unsigned int op,
652 unsigned int *eax, unsigned int *ebx,
653 unsigned int *ecx, unsigned int *edx)
657 __cpuid(eax, ebx, ecx, edx);
660 /* Some CPUID calls want 'count' to be placed in ecx */
661 static inline void cpuid_count(unsigned int op, int count,
662 unsigned int *eax, unsigned int *ebx,
663 unsigned int *ecx, unsigned int *edx)
667 __cpuid(eax, ebx, ecx, edx);
671 * CPUID functions returning a single datum
673 static inline unsigned int cpuid_eax(unsigned int op)
675 unsigned int eax, ebx, ecx, edx;
677 cpuid(op, &eax, &ebx, &ecx, &edx);
682 static inline unsigned int cpuid_ebx(unsigned int op)
684 unsigned int eax, ebx, ecx, edx;
686 cpuid(op, &eax, &ebx, &ecx, &edx);
691 static inline unsigned int cpuid_ecx(unsigned int op)
693 unsigned int eax, ebx, ecx, edx;
695 cpuid(op, &eax, &ebx, &ecx, &edx);
700 static inline unsigned int cpuid_edx(unsigned int op)
702 unsigned int eax, ebx, ecx, edx;
704 cpuid(op, &eax, &ebx, &ecx, &edx);
709 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
710 static inline void rep_nop(void)
712 asm volatile("rep; nop" ::: "memory");
715 static inline void cpu_relax(void)
720 /* Stop speculative execution and prefetching of modified code. */
721 static inline void sync_core(void)
725 #if defined(CONFIG_M386) || defined(CONFIG_M486)
726 if (boot_cpu_data.x86 < 5)
727 /* There is no speculative execution.
728 * jmp is a barrier to prefetching. */
729 asm volatile("jmp 1f\n1:\n" ::: "memory");
732 /* cpuid is a barrier to speculative execution.
733 * Prefetched instructions are automatically
734 * invalidated when modified. */
735 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
736 : "ebx", "ecx", "edx", "memory");
739 static inline void __monitor(const void *eax, unsigned long ecx,
742 /* "monitor %eax, %ecx, %edx;" */
743 asm volatile(".byte 0x0f, 0x01, 0xc8;"
744 :: "a" (eax), "c" (ecx), "d"(edx));
747 static inline void __mwait(unsigned long eax, unsigned long ecx)
749 /* "mwait %eax, %ecx;" */
750 asm volatile(".byte 0x0f, 0x01, 0xc9;"
751 :: "a" (eax), "c" (ecx));
754 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
757 /* "mwait %eax, %ecx;" */
758 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
759 :: "a" (eax), "c" (ecx));
762 extern void select_idle_routine(const struct cpuinfo_x86 *c);
763 extern void init_amd_e400_c1e_mask(void);
765 extern unsigned long boot_option_idle_override;
766 extern bool amd_e400_c1e_detected;
768 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
769 IDLE_POLL, IDLE_FORCE_MWAIT};
771 extern void enable_sep_cpu(void);
772 extern int sysenter_setup(void);
774 extern void early_trap_init(void);
776 /* Defined in head.S */
777 extern struct desc_ptr early_gdt_descr;
779 extern void cpu_set_gdt(int);
780 extern void switch_to_new_gdt(int);
781 extern void load_percpu_segment(int);
782 extern void cpu_init(void);
784 static inline unsigned long get_debugctlmsr(void)
786 unsigned long debugctlmsr = 0;
788 #ifndef CONFIG_X86_DEBUGCTLMSR
789 if (boot_cpu_data.x86 < 6)
792 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
797 static inline void update_debugctlmsr(unsigned long debugctlmsr)
799 #ifndef CONFIG_X86_DEBUGCTLMSR
800 if (boot_cpu_data.x86 < 6)
803 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
807 * from system description table in BIOS. Mostly for MCA use, but
808 * others may find it useful:
810 extern unsigned int machine_id;
811 extern unsigned int machine_submodel_id;
812 extern unsigned int BIOS_revision;
814 /* Boot loader type from the setup header: */
815 extern int bootloader_type;
816 extern int bootloader_version;
818 extern char ignore_fpu_irq;
820 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
821 #define ARCH_HAS_PREFETCHW
822 #define ARCH_HAS_SPINLOCK_PREFETCH
825 # define BASE_PREFETCH ASM_NOP4
826 # define ARCH_HAS_PREFETCH
828 # define BASE_PREFETCH "prefetcht0 (%1)"
832 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
834 * It's not worth to care about 3dnow prefetches for the K6
835 * because they are microcoded there and very slow.
837 static inline void prefetch(const void *x)
839 alternative_input(BASE_PREFETCH,
846 * 3dnow prefetch to get an exclusive cache line.
847 * Useful for spinlocks to avoid one state transition in the
848 * cache coherency protocol:
850 static inline void prefetchw(const void *x)
852 alternative_input(BASE_PREFETCH,
858 static inline void spin_lock_prefetch(const void *x)
865 * User space process size: 3GB (default).
867 #define TASK_SIZE PAGE_OFFSET
868 #define TASK_SIZE_MAX TASK_SIZE
869 #define STACK_TOP TASK_SIZE
870 #define STACK_TOP_MAX STACK_TOP
872 #define INIT_THREAD { \
873 .sp0 = sizeof(init_stack) + (long)&init_stack, \
875 .sysenter_cs = __KERNEL_CS, \
876 .io_bitmap_ptr = NULL, \
880 * Note that the .io_bitmap member must be extra-big. This is because
881 * the CPU will access an additional byte beyond the end of the IO
882 * permission bitmap. The extra byte must be all 1 bits, and must
883 * be within the limit.
887 .sp0 = sizeof(init_stack) + (long)&init_stack, \
888 .ss0 = __KERNEL_DS, \
889 .ss1 = __KERNEL_CS, \
890 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
892 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
895 extern unsigned long thread_saved_pc(struct task_struct *tsk);
897 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
898 #define KSTK_TOP(info) \
900 unsigned long *__ptr = (unsigned long *)(info); \
901 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
905 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
906 * This is necessary to guarantee that the entire "struct pt_regs"
907 * is accessible even if the CPU haven't stored the SS/ESP registers
908 * on the stack (interrupt gate does not save these registers
909 * when switching to the same priv ring).
910 * Therefore beware: accessing the ss/esp fields of the
911 * "struct pt_regs" is possible, but they may contain the
912 * completely wrong values.
914 #define task_pt_regs(task) \
916 struct pt_regs *__regs__; \
917 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
921 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
925 * User space process size. 47bits minus one guard page.
927 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
929 /* This decides where the kernel will search for a free chunk of vm
930 * space during mmap's.
932 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
933 0xc0000000 : 0xFFFFe000)
935 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
936 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
937 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
938 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
940 #define STACK_TOP TASK_SIZE
941 #define STACK_TOP_MAX TASK_SIZE_MAX
943 #define INIT_THREAD { \
944 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
948 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
952 * Return saved PC of a blocked thread.
953 * What is this good for? it will be always the scheduler or ret_from_fork.
955 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
957 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
958 extern unsigned long KSTK_ESP(struct task_struct *task);
959 #endif /* CONFIG_X86_64 */
961 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
962 unsigned long new_sp);
965 * This decides where the kernel will search for a free chunk of vm
966 * space during mmap's.
968 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
970 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
972 /* Get/set a process' ability to use the timestamp counter instruction */
973 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
974 #define SET_TSC_CTL(val) set_tsc_mode((val))
976 extern int get_tsc_mode(unsigned long adr);
977 extern int set_tsc_mode(unsigned int val);
979 extern int amd_get_nb_id(int cpu);
985 static inline void get_aperfmperf(struct aperfmperf *am)
987 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
989 rdmsrl(MSR_IA32_APERF, am->aperf);
990 rdmsrl(MSR_IA32_MPERF, am->mperf);
993 #define APERFMPERF_SHIFT 10
996 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
997 struct aperfmperf *new)
999 u64 aperf = new->aperf - old->aperf;
1000 u64 mperf = new->mperf - old->mperf;
1001 unsigned long ratio = aperf;
1003 mperf >>= APERFMPERF_SHIFT;
1005 ratio = div64_u64(aperf, mperf);
1011 * AMD errata checking
1013 #ifdef CONFIG_CPU_SUP_AMD
1014 extern const int amd_erratum_383[];
1015 extern const int amd_erratum_400[];
1016 extern bool cpu_has_amd_erratum(const int *);
1018 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1019 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1020 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1021 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1022 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1023 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1024 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1027 #define cpu_has_amd_erratum(x) (false)
1028 #endif /* CONFIG_CPU_SUP_AMD */
1030 #endif /* _ASM_X86_PROCESSOR_H */