4 #include <uapi/asm/mce.h>
13 bool bios_cmci_threshold;
22 extern struct mca_config mca_cfg;
23 extern void mce_register_decode_chain(struct notifier_block *nb);
24 extern void mce_unregister_decode_chain(struct notifier_block *nb);
26 #include <linux/percpu.h>
27 #include <linux/init.h>
28 #include <linux/atomic.h>
30 extern int mce_p5_enabled;
33 int mcheck_init(void);
34 void mcheck_cpu_init(struct cpuinfo_x86 *c);
36 static inline int mcheck_init(void) { return 0; }
37 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
40 #ifdef CONFIG_X86_ANCIENT_MCE
41 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
42 void winchip_mcheck_init(struct cpuinfo_x86 *c);
43 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
45 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
46 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
47 static inline void enable_p5_mce(void) {}
50 void mce_setup(struct mce *m);
51 void mce_log(struct mce *m);
52 DECLARE_PER_CPU(struct device *, mce_device);
55 * Maximum banks number.
56 * This is the limit of the current register layout on
59 #define MAX_NR_BANKS 32
61 #ifdef CONFIG_X86_MCE_INTEL
62 void mce_intel_feature_init(struct cpuinfo_x86 *c);
63 void cmci_clear(void);
64 void cmci_reenable(void);
65 void cmci_rediscover(int dying);
66 void cmci_recheck(void);
68 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
69 static inline void cmci_clear(void) {}
70 static inline void cmci_reenable(void) {}
71 static inline void cmci_rediscover(int dying) {}
72 static inline void cmci_recheck(void) {}
75 #ifdef CONFIG_X86_MCE_AMD
76 void mce_amd_feature_init(struct cpuinfo_x86 *c);
78 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
81 int mce_available(struct cpuinfo_x86 *c);
83 DECLARE_PER_CPU(unsigned, mce_exception_count);
84 DECLARE_PER_CPU(unsigned, mce_poll_count);
86 extern atomic_t mce_entry;
88 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
89 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
92 MCP_TIMESTAMP = (1 << 0), /* log time stamp */
93 MCP_UC = (1 << 1), /* log uncorrected errors */
94 MCP_DONTLOG = (1 << 2), /* only clear, don't log */
96 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
98 int mce_notify_irq(void);
99 void mce_notify_process(void);
101 DECLARE_PER_CPU(struct mce, injectm);
103 extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
104 const char __user *ubuf,
105 size_t usize, loff_t *off));
111 /* Call the installed machine check handler for this CPU setup. */
112 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
113 void do_machine_check(struct pt_regs *, long);
119 extern void (*mce_threshold_vector)(void);
120 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
126 void intel_init_thermal(struct cpuinfo_x86 *c);
128 void mce_log_therm_throt_event(__u64 status);
130 /* Interrupt Handler for core thermal thresholds */
131 extern int (*platform_thermal_notify)(__u64 msr_val);
133 #ifdef CONFIG_X86_THERMAL_VECTOR
134 extern void mcheck_intel_therm_init(void);
136 static inline void mcheck_intel_therm_init(void) { }
140 * Used by APEI to report memory error via /dev/mcelog
143 struct cper_sec_mem_err;
144 extern void apei_mce_report_mem_error(int corrected,
145 struct cper_sec_mem_err *mem_err);
147 #endif /* _ASM_X86_MCE_H */