Pileus Git - ~andy/linux/blob - arch/x86/boot/cpuflags.c

   1 #include <linux/types.h>
   2 #include "bitops.h"
   3
   4 #include <asm/processor-flags.h>
   5 #include <asm/required-features.h>
   6 #include <asm/msr-index.h>
   7 #include "cpuflags.h"
   8
   9 struct cpu_features cpu;
  10 u32 cpu_vendor[3];
  11
  12 static bool loaded_flags;
  13
  14 static int has_fpu(void)
  15 {
  16         u16 fcw = -1, fsw = -1;
  17         unsigned long cr0;
  18
  19         asm volatile("mov %%cr0,%0" : "=r" (cr0));
  20         if (cr0 & (X86_CR0_EM|X86_CR0_TS)) {
  21                 cr0 &= ~(X86_CR0_EM|X86_CR0_TS);
  22                 asm volatile("mov %0,%%cr0" : : "r" (cr0));
  23         }
  24
  25         asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
  26                      : "+m" (fsw), "+m" (fcw));
  27
  28         return fsw == 0 && (fcw & 0x103f) == 0x003f;
  29 }
  30
  31 int has_eflag(unsigned long mask)
  32 {
  33         unsigned long f0, f1;
  34
  35         asm volatile("pushf     \n\t"
  36                      "pushf     \n\t"
  37                      "pop %0    \n\t"
  38                      "mov %0,%1 \n\t"
  39                      "xor %2,%1 \n\t"
  40                      "push %1   \n\t"
  41                      "popf      \n\t"
  42                      "pushf     \n\t"
  43                      "pop %1    \n\t"
  44                      "popf"
  45                      : "=&r" (f0), "=&r" (f1)
  46                      : "ri" (mask));
  47
  48         return !!((f0^f1) & mask);
  49 }
  50
  51 /* Handle x86_32 PIC using ebx. */
  52 #if defined(__i386__) && defined(__PIC__)
  53 # define EBX_REG "=r"
  54 #else
  55 # define EBX_REG "=b"
  56 #endif
  57
  58 static inline void cpuid(u32 id, u32 *a, u32 *b, u32 *c, u32 *d)
  59 {
  60         asm volatile(".ifnc %%ebx,%3 ; movl  %%ebx,%3 ; .endif  \n\t"
  61                      "cpuid                                     \n\t"
  62                      ".ifnc %%ebx,%3 ; xchgl %%ebx,%3 ; .endif  \n\t"
  63                     : "=a" (*a), "=c" (*c), "=d" (*d), EBX_REG (*b)
  64                     : "a" (id)
  65         );
  66 }
  67
  68 void get_cpuflags(void)
  69 {
  70         u32 max_intel_level, max_amd_level;
  71         u32 tfms;
  72         u32 ignored;
  73
  74         if (loaded_flags)
  75                 return;
  76         loaded_flags = true;
  77
  78         if (has_fpu())
  79                 set_bit(X86_FEATURE_FPU, cpu.flags);
  80
  81         if (has_eflag(X86_EFLAGS_ID)) {
  82                 cpuid(0x0, &max_intel_level, &cpu_vendor[0], &cpu_vendor[2],
  83                       &cpu_vendor[1]);
  84
  85                 if (max_intel_level >= 0x00000001 &&
  86                     max_intel_level <= 0x0000ffff) {
  87                         cpuid(0x1, &tfms, &ignored, &cpu.flags[4],
  88                               &cpu.flags[0]);
  89                         cpu.level = (tfms >> 8) & 15;
  90                         cpu.model = (tfms >> 4) & 15;
  91                         if (cpu.level >= 6)
  92                                 cpu.model += ((tfms >> 16) & 0xf) << 4;
  93                 }
  94
  95                 cpuid(0x80000000, &max_amd_level, &ignored, &ignored,
  96                       &ignored);
  97
  98                 if (max_amd_level >= 0x80000001 &&
  99                     max_amd_level <= 0x8000ffff) {
 100                         cpuid(0x80000001, &ignored, &ignored, &cpu.flags[6],
 101                               &cpu.flags[1]);
 102                 }
 103         }
 104 }