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[SPARC64]: Don't be picky about virtual-dma values on sun4v.
[~andy/linux] / arch / sparc64 / kernel / pci_sun4v.c
1 /* pci_sun4v.c: SUN4V specific PCI controller support.
2  *
3  * Copyright (C) 2006, 2007 David S. Miller (davem@davemloft.net)
4  */
5
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/percpu.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15 #include <linux/log2.h>
16
17 #include <asm/iommu.h>
18 #include <asm/irq.h>
19 #include <asm/upa.h>
20 #include <asm/pstate.h>
21 #include <asm/oplib.h>
22 #include <asm/hypervisor.h>
23 #include <asm/prom.h>
24
25 #include "pci_impl.h"
26 #include "iommu_common.h"
27
28 #include "pci_sun4v.h"
29
30 #define PGLIST_NENTS    (PAGE_SIZE / sizeof(u64))
31
32 struct iommu_batch {
33         struct pci_dev  *pdev;          /* Device mapping is for.       */
34         unsigned long   prot;           /* IOMMU page protections       */
35         unsigned long   entry;          /* Index into IOTSB.            */
36         u64             *pglist;        /* List of physical pages       */
37         unsigned long   npages;         /* Number of pages in list.     */
38 };
39
40 static DEFINE_PER_CPU(struct iommu_batch, pci_iommu_batch);
41
42 /* Interrupts must be disabled.  */
43 static inline void pci_iommu_batch_start(struct pci_dev *pdev, unsigned long prot, unsigned long entry)
44 {
45         struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
46
47         p->pdev         = pdev;
48         p->prot         = prot;
49         p->entry        = entry;
50         p->npages       = 0;
51 }
52
53 /* Interrupts must be disabled.  */
54 static long pci_iommu_batch_flush(struct iommu_batch *p)
55 {
56         struct pci_pbm_info *pbm = p->pdev->dev.archdata.host_controller;
57         unsigned long devhandle = pbm->devhandle;
58         unsigned long prot = p->prot;
59         unsigned long entry = p->entry;
60         u64 *pglist = p->pglist;
61         unsigned long npages = p->npages;
62
63         while (npages != 0) {
64                 long num;
65
66                 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
67                                           npages, prot, __pa(pglist));
68                 if (unlikely(num < 0)) {
69                         if (printk_ratelimit())
70                                 printk("pci_iommu_batch_flush: IOMMU map of "
71                                        "[%08lx:%08lx:%lx:%lx:%lx] failed with "
72                                        "status %ld\n",
73                                        devhandle, HV_PCI_TSBID(0, entry),
74                                        npages, prot, __pa(pglist), num);
75                         return -1;
76                 }
77
78                 entry += num;
79                 npages -= num;
80                 pglist += num;
81         }
82
83         p->entry = entry;
84         p->npages = 0;
85
86         return 0;
87 }
88
89 /* Interrupts must be disabled.  */
90 static inline long pci_iommu_batch_add(u64 phys_page)
91 {
92         struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
93
94         BUG_ON(p->npages >= PGLIST_NENTS);
95
96         p->pglist[p->npages++] = phys_page;
97         if (p->npages == PGLIST_NENTS)
98                 return pci_iommu_batch_flush(p);
99
100         return 0;
101 }
102
103 /* Interrupts must be disabled.  */
104 static inline long pci_iommu_batch_end(void)
105 {
106         struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
107
108         BUG_ON(p->npages >= PGLIST_NENTS);
109
110         return pci_iommu_batch_flush(p);
111 }
112
113 static long pci_arena_alloc(struct iommu_arena *arena, unsigned long npages)
114 {
115         unsigned long n, i, start, end, limit;
116         int pass;
117
118         limit = arena->limit;
119         start = arena->hint;
120         pass = 0;
121
122 again:
123         n = find_next_zero_bit(arena->map, limit, start);
124         end = n + npages;
125         if (unlikely(end >= limit)) {
126                 if (likely(pass < 1)) {
127                         limit = start;
128                         start = 0;
129                         pass++;
130                         goto again;
131                 } else {
132                         /* Scanned the whole thing, give up. */
133                         return -1;
134                 }
135         }
136
137         for (i = n; i < end; i++) {
138                 if (test_bit(i, arena->map)) {
139                         start = i + 1;
140                         goto again;
141                 }
142         }
143
144         for (i = n; i < end; i++)
145                 __set_bit(i, arena->map);
146
147         arena->hint = end;
148
149         return n;
150 }
151
152 static void pci_arena_free(struct iommu_arena *arena, unsigned long base, unsigned long npages)
153 {
154         unsigned long i;
155
156         for (i = base; i < (base + npages); i++)
157                 __clear_bit(i, arena->map);
158 }
159
160 static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
161 {
162         struct iommu *iommu;
163         unsigned long flags, order, first_page, npages, n;
164         void *ret;
165         long entry;
166
167         size = IO_PAGE_ALIGN(size);
168         order = get_order(size);
169         if (unlikely(order >= MAX_ORDER))
170                 return NULL;
171
172         npages = size >> IO_PAGE_SHIFT;
173
174         first_page = __get_free_pages(gfp, order);
175         if (unlikely(first_page == 0UL))
176                 return NULL;
177
178         memset((char *)first_page, 0, PAGE_SIZE << order);
179
180         iommu = pdev->dev.archdata.iommu;
181
182         spin_lock_irqsave(&iommu->lock, flags);
183         entry = pci_arena_alloc(&iommu->arena, npages);
184         spin_unlock_irqrestore(&iommu->lock, flags);
185
186         if (unlikely(entry < 0L))
187                 goto arena_alloc_fail;
188
189         *dma_addrp = (iommu->page_table_map_base +
190                       (entry << IO_PAGE_SHIFT));
191         ret = (void *) first_page;
192         first_page = __pa(first_page);
193
194         local_irq_save(flags);
195
196         pci_iommu_batch_start(pdev,
197                               (HV_PCI_MAP_ATTR_READ |
198                                HV_PCI_MAP_ATTR_WRITE),
199                               entry);
200
201         for (n = 0; n < npages; n++) {
202                 long err = pci_iommu_batch_add(first_page + (n * PAGE_SIZE));
203                 if (unlikely(err < 0L))
204                         goto iommu_map_fail;
205         }
206
207         if (unlikely(pci_iommu_batch_end() < 0L))
208                 goto iommu_map_fail;
209
210         local_irq_restore(flags);
211
212         return ret;
213
214 iommu_map_fail:
215         /* Interrupts are disabled.  */
216         spin_lock(&iommu->lock);
217         pci_arena_free(&iommu->arena, entry, npages);
218         spin_unlock_irqrestore(&iommu->lock, flags);
219
220 arena_alloc_fail:
221         free_pages(first_page, order);
222         return NULL;
223 }
224
225 static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
226 {
227         struct pci_pbm_info *pbm;
228         struct iommu *iommu;
229         unsigned long flags, order, npages, entry;
230         u32 devhandle;
231
232         npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
233         iommu = pdev->dev.archdata.iommu;
234         pbm = pdev->dev.archdata.host_controller;
235         devhandle = pbm->devhandle;
236         entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
237
238         spin_lock_irqsave(&iommu->lock, flags);
239
240         pci_arena_free(&iommu->arena, entry, npages);
241
242         do {
243                 unsigned long num;
244
245                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
246                                             npages);
247                 entry += num;
248                 npages -= num;
249         } while (npages != 0);
250
251         spin_unlock_irqrestore(&iommu->lock, flags);
252
253         order = get_order(size);
254         if (order < 10)
255                 free_pages((unsigned long)cpu, order);
256 }
257
258 static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
259 {
260         struct iommu *iommu;
261         unsigned long flags, npages, oaddr;
262         unsigned long i, base_paddr;
263         u32 bus_addr, ret;
264         unsigned long prot;
265         long entry;
266
267         iommu = pdev->dev.archdata.iommu;
268
269         if (unlikely(direction == PCI_DMA_NONE))
270                 goto bad;
271
272         oaddr = (unsigned long)ptr;
273         npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
274         npages >>= IO_PAGE_SHIFT;
275
276         spin_lock_irqsave(&iommu->lock, flags);
277         entry = pci_arena_alloc(&iommu->arena, npages);
278         spin_unlock_irqrestore(&iommu->lock, flags);
279
280         if (unlikely(entry < 0L))
281                 goto bad;
282
283         bus_addr = (iommu->page_table_map_base +
284                     (entry << IO_PAGE_SHIFT));
285         ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
286         base_paddr = __pa(oaddr & IO_PAGE_MASK);
287         prot = HV_PCI_MAP_ATTR_READ;
288         if (direction != PCI_DMA_TODEVICE)
289                 prot |= HV_PCI_MAP_ATTR_WRITE;
290
291         local_irq_save(flags);
292
293         pci_iommu_batch_start(pdev, prot, entry);
294
295         for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
296                 long err = pci_iommu_batch_add(base_paddr);
297                 if (unlikely(err < 0L))
298                         goto iommu_map_fail;
299         }
300         if (unlikely(pci_iommu_batch_end() < 0L))
301                 goto iommu_map_fail;
302
303         local_irq_restore(flags);
304
305         return ret;
306
307 bad:
308         if (printk_ratelimit())
309                 WARN_ON(1);
310         return PCI_DMA_ERROR_CODE;
311
312 iommu_map_fail:
313         /* Interrupts are disabled.  */
314         spin_lock(&iommu->lock);
315         pci_arena_free(&iommu->arena, entry, npages);
316         spin_unlock_irqrestore(&iommu->lock, flags);
317
318         return PCI_DMA_ERROR_CODE;
319 }
320
321 static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
322 {
323         struct pci_pbm_info *pbm;
324         struct iommu *iommu;
325         unsigned long flags, npages;
326         long entry;
327         u32 devhandle;
328
329         if (unlikely(direction == PCI_DMA_NONE)) {
330                 if (printk_ratelimit())
331                         WARN_ON(1);
332                 return;
333         }
334
335         iommu = pdev->dev.archdata.iommu;
336         pbm = pdev->dev.archdata.host_controller;
337         devhandle = pbm->devhandle;
338
339         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
340         npages >>= IO_PAGE_SHIFT;
341         bus_addr &= IO_PAGE_MASK;
342
343         spin_lock_irqsave(&iommu->lock, flags);
344
345         entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
346         pci_arena_free(&iommu->arena, entry, npages);
347
348         do {
349                 unsigned long num;
350
351                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
352                                             npages);
353                 entry += num;
354                 npages -= num;
355         } while (npages != 0);
356
357         spin_unlock_irqrestore(&iommu->lock, flags);
358 }
359
360 #define SG_ENT_PHYS_ADDRESS(SG) \
361         (__pa(page_address((SG)->page)) + (SG)->offset)
362
363 static inline long fill_sg(long entry, struct pci_dev *pdev,
364                            struct scatterlist *sg,
365                            int nused, int nelems, unsigned long prot)
366 {
367         struct scatterlist *dma_sg = sg;
368         struct scatterlist *sg_end = sg + nelems;
369         unsigned long flags;
370         int i;
371
372         local_irq_save(flags);
373
374         pci_iommu_batch_start(pdev, prot, entry);
375
376         for (i = 0; i < nused; i++) {
377                 unsigned long pteval = ~0UL;
378                 u32 dma_npages;
379
380                 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
381                               dma_sg->dma_length +
382                               ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
383                 do {
384                         unsigned long offset;
385                         signed int len;
386
387                         /* If we are here, we know we have at least one
388                          * more page to map.  So walk forward until we
389                          * hit a page crossing, and begin creating new
390                          * mappings from that spot.
391                          */
392                         for (;;) {
393                                 unsigned long tmp;
394
395                                 tmp = SG_ENT_PHYS_ADDRESS(sg);
396                                 len = sg->length;
397                                 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
398                                         pteval = tmp & IO_PAGE_MASK;
399                                         offset = tmp & (IO_PAGE_SIZE - 1UL);
400                                         break;
401                                 }
402                                 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
403                                         pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
404                                         offset = 0UL;
405                                         len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
406                                         break;
407                                 }
408                                 sg++;
409                         }
410
411                         pteval = (pteval & IOPTE_PAGE);
412                         while (len > 0) {
413                                 long err;
414
415                                 err = pci_iommu_batch_add(pteval);
416                                 if (unlikely(err < 0L))
417                                         goto iommu_map_failed;
418
419                                 pteval += IO_PAGE_SIZE;
420                                 len -= (IO_PAGE_SIZE - offset);
421                                 offset = 0;
422                                 dma_npages--;
423                         }
424
425                         pteval = (pteval & IOPTE_PAGE) + len;
426                         sg++;
427
428                         /* Skip over any tail mappings we've fully mapped,
429                          * adjusting pteval along the way.  Stop when we
430                          * detect a page crossing event.
431                          */
432                         while (sg < sg_end &&
433                                (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
434                                (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
435                                ((pteval ^
436                                  (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
437                                 pteval += sg->length;
438                                 sg++;
439                         }
440                         if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
441                                 pteval = ~0UL;
442                 } while (dma_npages != 0);
443                 dma_sg++;
444         }
445
446         if (unlikely(pci_iommu_batch_end() < 0L))
447                 goto iommu_map_failed;
448
449         local_irq_restore(flags);
450         return 0;
451
452 iommu_map_failed:
453         local_irq_restore(flags);
454         return -1L;
455 }
456
457 static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
458 {
459         struct iommu *iommu;
460         unsigned long flags, npages, prot;
461         u32 dma_base;
462         struct scatterlist *sgtmp;
463         long entry, err;
464         int used;
465
466         /* Fast path single entry scatterlists. */
467         if (nelems == 1) {
468                 sglist->dma_address =
469                         pci_4v_map_single(pdev,
470                                           (page_address(sglist->page) + sglist->offset),
471                                           sglist->length, direction);
472                 if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
473                         return 0;
474                 sglist->dma_length = sglist->length;
475                 return 1;
476         }
477
478         iommu = pdev->dev.archdata.iommu;
479         
480         if (unlikely(direction == PCI_DMA_NONE))
481                 goto bad;
482
483         /* Step 1: Prepare scatter list. */
484         npages = prepare_sg(sglist, nelems);
485
486         /* Step 2: Allocate a cluster and context, if necessary. */
487         spin_lock_irqsave(&iommu->lock, flags);
488         entry = pci_arena_alloc(&iommu->arena, npages);
489         spin_unlock_irqrestore(&iommu->lock, flags);
490
491         if (unlikely(entry < 0L))
492                 goto bad;
493
494         dma_base = iommu->page_table_map_base +
495                 (entry << IO_PAGE_SHIFT);
496
497         /* Step 3: Normalize DMA addresses. */
498         used = nelems;
499
500         sgtmp = sglist;
501         while (used && sgtmp->dma_length) {
502                 sgtmp->dma_address += dma_base;
503                 sgtmp++;
504                 used--;
505         }
506         used = nelems - used;
507
508         /* Step 4: Create the mappings. */
509         prot = HV_PCI_MAP_ATTR_READ;
510         if (direction != PCI_DMA_TODEVICE)
511                 prot |= HV_PCI_MAP_ATTR_WRITE;
512
513         err = fill_sg(entry, pdev, sglist, used, nelems, prot);
514         if (unlikely(err < 0L))
515                 goto iommu_map_failed;
516
517         return used;
518
519 bad:
520         if (printk_ratelimit())
521                 WARN_ON(1);
522         return 0;
523
524 iommu_map_failed:
525         spin_lock_irqsave(&iommu->lock, flags);
526         pci_arena_free(&iommu->arena, entry, npages);
527         spin_unlock_irqrestore(&iommu->lock, flags);
528
529         return 0;
530 }
531
532 static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
533 {
534         struct pci_pbm_info *pbm;
535         struct iommu *iommu;
536         unsigned long flags, i, npages;
537         long entry;
538         u32 devhandle, bus_addr;
539
540         if (unlikely(direction == PCI_DMA_NONE)) {
541                 if (printk_ratelimit())
542                         WARN_ON(1);
543         }
544
545         iommu = pdev->dev.archdata.iommu;
546         pbm = pdev->dev.archdata.host_controller;
547         devhandle = pbm->devhandle;
548         
549         bus_addr = sglist->dma_address & IO_PAGE_MASK;
550
551         for (i = 1; i < nelems; i++)
552                 if (sglist[i].dma_length == 0)
553                         break;
554         i--;
555         npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
556                   bus_addr) >> IO_PAGE_SHIFT;
557
558         entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
559
560         spin_lock_irqsave(&iommu->lock, flags);
561
562         pci_arena_free(&iommu->arena, entry, npages);
563
564         do {
565                 unsigned long num;
566
567                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
568                                             npages);
569                 entry += num;
570                 npages -= num;
571         } while (npages != 0);
572
573         spin_unlock_irqrestore(&iommu->lock, flags);
574 }
575
576 static void pci_4v_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
577 {
578         /* Nothing to do... */
579 }
580
581 static void pci_4v_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
582 {
583         /* Nothing to do... */
584 }
585
586 const struct pci_iommu_ops pci_sun4v_iommu_ops = {
587         .alloc_consistent               = pci_4v_alloc_consistent,
588         .free_consistent                = pci_4v_free_consistent,
589         .map_single                     = pci_4v_map_single,
590         .unmap_single                   = pci_4v_unmap_single,
591         .map_sg                         = pci_4v_map_sg,
592         .unmap_sg                       = pci_4v_unmap_sg,
593         .dma_sync_single_for_cpu        = pci_4v_dma_sync_single_for_cpu,
594         .dma_sync_sg_for_cpu            = pci_4v_dma_sync_sg_for_cpu,
595 };
596
597 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm)
598 {
599         struct property *prop;
600         struct device_node *dp;
601
602         dp = pbm->prom_node;
603         prop = of_find_property(dp, "66mhz-capable", NULL);
604         pbm->is_66mhz_capable = (prop != NULL);
605         pbm->pci_bus = pci_scan_one_pbm(pbm);
606
607         /* XXX register error interrupt handlers XXX */
608 }
609
610 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
611                                             struct iommu *iommu)
612 {
613         struct iommu_arena *arena = &iommu->arena;
614         unsigned long i, cnt = 0;
615         u32 devhandle;
616
617         devhandle = pbm->devhandle;
618         for (i = 0; i < arena->limit; i++) {
619                 unsigned long ret, io_attrs, ra;
620
621                 ret = pci_sun4v_iommu_getmap(devhandle,
622                                              HV_PCI_TSBID(0, i),
623                                              &io_attrs, &ra);
624                 if (ret == HV_EOK) {
625                         if (page_in_phys_avail(ra)) {
626                                 pci_sun4v_iommu_demap(devhandle,
627                                                       HV_PCI_TSBID(0, i), 1);
628                         } else {
629                                 cnt++;
630                                 __set_bit(i, arena->map);
631                         }
632                 }
633         }
634
635         return cnt;
636 }
637
638 static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
639 {
640         struct iommu *iommu = pbm->iommu;
641         struct property *prop;
642         unsigned long num_tsb_entries, sz, tsbsize;
643         u32 vdma[2], dma_mask, dma_offset;
644
645         prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
646         if (prop) {
647                 u32 *val = prop->value;
648
649                 vdma[0] = val[0];
650                 vdma[1] = val[1];
651         } else {
652                 /* No property, use default values. */
653                 vdma[0] = 0x80000000;
654                 vdma[1] = 0x80000000;
655         }
656
657         if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
658                 prom_printf("PCI-SUN4V: strange virtual-dma[%08x:%08x].\n",
659                             vdma[0], vdma[1]);
660                 prom_halt();
661         };
662
663         dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
664         num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
665         tsbsize = num_tsb_entries * sizeof(iopte_t);
666
667         dma_offset = vdma[0];
668
669         /* Setup initial software IOMMU state. */
670         spin_lock_init(&iommu->lock);
671         iommu->ctx_lowest_free = 1;
672         iommu->page_table_map_base = dma_offset;
673         iommu->dma_addr_mask = dma_mask;
674
675         /* Allocate and initialize the free area map.  */
676         sz = (num_tsb_entries + 7) / 8;
677         sz = (sz + 7UL) & ~7UL;
678         iommu->arena.map = kzalloc(sz, GFP_KERNEL);
679         if (!iommu->arena.map) {
680                 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
681                 prom_halt();
682         }
683         iommu->arena.limit = num_tsb_entries;
684
685         sz = probe_existing_entries(pbm, iommu);
686         if (sz)
687                 printk("%s: Imported %lu TSB entries from OBP\n",
688                        pbm->name, sz);
689 }
690
691 #ifdef CONFIG_PCI_MSI
692 struct pci_sun4v_msiq_entry {
693         u64             version_type;
694 #define MSIQ_VERSION_MASK               0xffffffff00000000UL
695 #define MSIQ_VERSION_SHIFT              32
696 #define MSIQ_TYPE_MASK                  0x00000000000000ffUL
697 #define MSIQ_TYPE_SHIFT                 0
698 #define MSIQ_TYPE_NONE                  0x00
699 #define MSIQ_TYPE_MSG                   0x01
700 #define MSIQ_TYPE_MSI32                 0x02
701 #define MSIQ_TYPE_MSI64                 0x03
702 #define MSIQ_TYPE_INTX                  0x08
703 #define MSIQ_TYPE_NONE2                 0xff
704
705         u64             intx_sysino;
706         u64             reserved1;
707         u64             stick;
708         u64             req_id;  /* bus/device/func */
709 #define MSIQ_REQID_BUS_MASK             0xff00UL
710 #define MSIQ_REQID_BUS_SHIFT            8
711 #define MSIQ_REQID_DEVICE_MASK          0x00f8UL
712 #define MSIQ_REQID_DEVICE_SHIFT         3
713 #define MSIQ_REQID_FUNC_MASK            0x0007UL
714 #define MSIQ_REQID_FUNC_SHIFT           0
715
716         u64             msi_address;
717
718         /* The format of this value is message type dependent.
719          * For MSI bits 15:0 are the data from the MSI packet.
720          * For MSI-X bits 31:0 are the data from the MSI packet.
721          * For MSG, the message code and message routing code where:
722          *      bits 39:32 is the bus/device/fn of the msg target-id
723          *      bits 18:16 is the message routing code
724          *      bits 7:0 is the message code
725          * For INTx the low order 2-bits are:
726          *      00 - INTA
727          *      01 - INTB
728          *      10 - INTC
729          *      11 - INTD
730          */
731         u64             msi_data;
732
733         u64             reserved2;
734 };
735
736 /* For now this just runs as a pre-handler for the real interrupt handler.
737  * So we just walk through the queue and ACK all the entries, update the
738  * head pointer, and return.
739  *
740  * In the longer term it would be nice to do something more integrated
741  * wherein we can pass in some of this MSI info to the drivers.  This
742  * would be most useful for PCIe fabric error messages, although we could
743  * invoke those directly from the loop here in order to pass the info around.
744  */
745 static void pci_sun4v_msi_prehandler(unsigned int ino, void *data1, void *data2)
746 {
747         struct pci_pbm_info *pbm = data1;
748         struct pci_sun4v_msiq_entry *base, *ep;
749         unsigned long msiqid, orig_head, head, type, err;
750
751         msiqid = (unsigned long) data2;
752
753         head = 0xdeadbeef;
754         err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, &head);
755         if (unlikely(err))
756                 goto hv_error_get;
757
758         if (unlikely(head >= (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))))
759                 goto bad_offset;
760
761         head /= sizeof(struct pci_sun4v_msiq_entry);
762         orig_head = head;
763         base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
764                                    (pbm->msiq_ent_count *
765                                     sizeof(struct pci_sun4v_msiq_entry))));
766         ep = &base[head];
767         while ((ep->version_type & MSIQ_TYPE_MASK) != 0) {
768                 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
769                 if (unlikely(type != MSIQ_TYPE_MSI32 &&
770                              type != MSIQ_TYPE_MSI64))
771                         goto bad_type;
772
773                 pci_sun4v_msi_setstate(pbm->devhandle,
774                                        ep->msi_data /* msi_num */,
775                                        HV_MSISTATE_IDLE);
776
777                 /* Clear the entry.  */
778                 ep->version_type &= ~MSIQ_TYPE_MASK;
779
780                 /* Go to next entry in ring.  */
781                 head++;
782                 if (head >= pbm->msiq_ent_count)
783                         head = 0;
784                 ep = &base[head];
785         }
786
787         if (likely(head != orig_head)) {
788                 /* ACK entries by updating head pointer.  */
789                 head *= sizeof(struct pci_sun4v_msiq_entry);
790                 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
791                 if (unlikely(err))
792                         goto hv_error_set;
793         }
794         return;
795
796 hv_error_set:
797         printk(KERN_EMERG "MSI: Hypervisor set head gives error %lu\n", err);
798         goto hv_error_cont;
799
800 hv_error_get:
801         printk(KERN_EMERG "MSI: Hypervisor get head gives error %lu\n", err);
802
803 hv_error_cont:
804         printk(KERN_EMERG "MSI: devhandle[%x] msiqid[%lx] head[%lu]\n",
805                pbm->devhandle, msiqid, head);
806         return;
807
808 bad_offset:
809         printk(KERN_EMERG "MSI: Hypervisor gives bad offset %lx max(%lx)\n",
810                head, pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry));
811         return;
812
813 bad_type:
814         printk(KERN_EMERG "MSI: Entry has bad type %lx\n", type);
815         return;
816 }
817
818 static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
819 {
820         unsigned long size, bits_per_ulong;
821
822         bits_per_ulong = sizeof(unsigned long) * 8;
823         size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
824         size /= 8;
825         BUG_ON(size % sizeof(unsigned long));
826
827         pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
828         if (!pbm->msi_bitmap)
829                 return -ENOMEM;
830
831         return 0;
832 }
833
834 static void msi_bitmap_free(struct pci_pbm_info *pbm)
835 {
836         kfree(pbm->msi_bitmap);
837         pbm->msi_bitmap = NULL;
838 }
839
840 static int msi_queue_alloc(struct pci_pbm_info *pbm)
841 {
842         unsigned long q_size, alloc_size, pages, order;
843         int i;
844
845         q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
846         alloc_size = (pbm->msiq_num * q_size);
847         order = get_order(alloc_size);
848         pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
849         if (pages == 0UL) {
850                 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
851                        order);
852                 return -ENOMEM;
853         }
854         memset((char *)pages, 0, PAGE_SIZE << order);
855         pbm->msi_queues = (void *) pages;
856
857         for (i = 0; i < pbm->msiq_num; i++) {
858                 unsigned long err, base = __pa(pages + (i * q_size));
859                 unsigned long ret1, ret2;
860
861                 err = pci_sun4v_msiq_conf(pbm->devhandle,
862                                           pbm->msiq_first + i,
863                                           base, pbm->msiq_ent_count);
864                 if (err) {
865                         printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
866                                err);
867                         goto h_error;
868                 }
869
870                 err = pci_sun4v_msiq_info(pbm->devhandle,
871                                           pbm->msiq_first + i,
872                                           &ret1, &ret2);
873                 if (err) {
874                         printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
875                                err);
876                         goto h_error;
877                 }
878                 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
879                         printk(KERN_ERR "MSI: Bogus qconf "
880                                "expected[%lx:%x] got[%lx:%lx]\n",
881                                base, pbm->msiq_ent_count,
882                                ret1, ret2);
883                         goto h_error;
884                 }
885         }
886
887         return 0;
888
889 h_error:
890         free_pages(pages, order);
891         return -EINVAL;
892 }
893
894
895 static int alloc_msi(struct pci_pbm_info *pbm)
896 {
897         int i;
898
899         for (i = 0; i < pbm->msi_num; i++) {
900                 if (!test_and_set_bit(i, pbm->msi_bitmap))
901                         return i + pbm->msi_first;
902         }
903
904         return -ENOENT;
905 }
906
907 static void free_msi(struct pci_pbm_info *pbm, int msi_num)
908 {
909         msi_num -= pbm->msi_first;
910         clear_bit(msi_num, pbm->msi_bitmap);
911 }
912
913 static int pci_sun4v_setup_msi_irq(unsigned int *virt_irq_p,
914                                    struct pci_dev *pdev,
915                                    struct msi_desc *entry)
916 {
917         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
918         unsigned long devino, msiqid;
919         struct msi_msg msg;
920         int msi_num, err;
921
922         *virt_irq_p = 0;
923
924         msi_num = alloc_msi(pbm);
925         if (msi_num < 0)
926                 return msi_num;
927
928         devino = sun4v_build_msi(pbm->devhandle, virt_irq_p,
929                                  pbm->msiq_first_devino,
930                                  (pbm->msiq_first_devino +
931                                   pbm->msiq_num));
932         err = -ENOMEM;
933         if (!devino)
934                 goto out_err;
935
936         msiqid = ((devino - pbm->msiq_first_devino) +
937                   pbm->msiq_first);
938
939         err = -EINVAL;
940         if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
941         if (err)
942                 goto out_err;
943
944         if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
945                 goto out_err;
946
947         if (pci_sun4v_msi_setmsiq(pbm->devhandle,
948                                   msi_num, msiqid,
949                                   (entry->msi_attrib.is_64 ?
950                                    HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
951                 goto out_err;
952
953         if (pci_sun4v_msi_setstate(pbm->devhandle, msi_num, HV_MSISTATE_IDLE))
954                 goto out_err;
955
956         if (pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_VALID))
957                 goto out_err;
958
959         pdev->dev.archdata.msi_num = msi_num;
960
961         if (entry->msi_attrib.is_64) {
962                 msg.address_hi = pbm->msi64_start >> 32;
963                 msg.address_lo = pbm->msi64_start & 0xffffffff;
964         } else {
965                 msg.address_hi = 0;
966                 msg.address_lo = pbm->msi32_start;
967         }
968         msg.data = msi_num;
969
970         set_irq_msi(*virt_irq_p, entry);
971         write_msi_msg(*virt_irq_p, &msg);
972
973         irq_install_pre_handler(*virt_irq_p,
974                                 pci_sun4v_msi_prehandler,
975                                 pbm, (void *) msiqid);
976
977         return 0;
978
979 out_err:
980         free_msi(pbm, msi_num);
981         sun4v_destroy_msi(*virt_irq_p);
982         *virt_irq_p = 0;
983         return err;
984
985 }
986
987 static void pci_sun4v_teardown_msi_irq(unsigned int virt_irq,
988                                        struct pci_dev *pdev)
989 {
990         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
991         unsigned long msiqid, err;
992         unsigned int msi_num;
993
994         msi_num = pdev->dev.archdata.msi_num;
995         err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi_num, &msiqid);
996         if (err) {
997                 printk(KERN_ERR "%s: getmsiq gives error %lu\n",
998                        pbm->name, err);
999                 return;
1000         }
1001
1002         pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_INVALID);
1003         pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_INVALID);
1004
1005         free_msi(pbm, msi_num);
1006
1007         /* The sun4v_destroy_msi() will liberate the devino and thus the MSIQ
1008          * allocation.
1009          */
1010         sun4v_destroy_msi(virt_irq);
1011 }
1012
1013 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1014 {
1015         const u32 *val;
1016         int len;
1017
1018         val = of_get_property(pbm->prom_node, "#msi-eqs", &len);
1019         if (!val || len != 4)
1020                 goto no_msi;
1021         pbm->msiq_num = *val;
1022         if (pbm->msiq_num) {
1023                 const struct msiq_prop {
1024                         u32 first_msiq;
1025                         u32 num_msiq;
1026                         u32 first_devino;
1027                 } *mqp;
1028                 const struct msi_range_prop {
1029                         u32 first_msi;
1030                         u32 num_msi;
1031                 } *mrng;
1032                 const struct addr_range_prop {
1033                         u32 msi32_high;
1034                         u32 msi32_low;
1035                         u32 msi32_len;
1036                         u32 msi64_high;
1037                         u32 msi64_low;
1038                         u32 msi64_len;
1039                 } *arng;
1040
1041                 val = of_get_property(pbm->prom_node, "msi-eq-size", &len);
1042                 if (!val || len != 4)
1043                         goto no_msi;
1044
1045                 pbm->msiq_ent_count = *val;
1046
1047                 mqp = of_get_property(pbm->prom_node,
1048                                       "msi-eq-to-devino", &len);
1049                 if (!mqp || len != sizeof(struct msiq_prop))
1050                         goto no_msi;
1051
1052                 pbm->msiq_first = mqp->first_msiq;
1053                 pbm->msiq_first_devino = mqp->first_devino;
1054
1055                 val = of_get_property(pbm->prom_node, "#msi", &len);
1056                 if (!val || len != 4)
1057                         goto no_msi;
1058                 pbm->msi_num = *val;
1059
1060                 mrng = of_get_property(pbm->prom_node, "msi-ranges", &len);
1061                 if (!mrng || len != sizeof(struct msi_range_prop))
1062                         goto no_msi;
1063                 pbm->msi_first = mrng->first_msi;
1064
1065                 val = of_get_property(pbm->prom_node, "msi-data-mask", &len);
1066                 if (!val || len != 4)
1067                         goto no_msi;
1068                 pbm->msi_data_mask = *val;
1069
1070                 val = of_get_property(pbm->prom_node, "msix-data-width", &len);
1071                 if (!val || len != 4)
1072                         goto no_msi;
1073                 pbm->msix_data_width = *val;
1074
1075                 arng = of_get_property(pbm->prom_node, "msi-address-ranges",
1076                                        &len);
1077                 if (!arng || len != sizeof(struct addr_range_prop))
1078                         goto no_msi;
1079                 pbm->msi32_start = ((u64)arng->msi32_high << 32) |
1080                         (u64) arng->msi32_low;
1081                 pbm->msi64_start = ((u64)arng->msi64_high << 32) |
1082                         (u64) arng->msi64_low;
1083                 pbm->msi32_len = arng->msi32_len;
1084                 pbm->msi64_len = arng->msi64_len;
1085
1086                 if (msi_bitmap_alloc(pbm))
1087                         goto no_msi;
1088
1089                 if (msi_queue_alloc(pbm)) {
1090                         msi_bitmap_free(pbm);
1091                         goto no_msi;
1092                 }
1093
1094                 printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
1095                        "devino[0x%x]\n",
1096                        pbm->name,
1097                        pbm->msiq_first, pbm->msiq_num,
1098                        pbm->msiq_ent_count,
1099                        pbm->msiq_first_devino);
1100                 printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
1101                        "width[%u]\n",
1102                        pbm->name,
1103                        pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
1104                        pbm->msix_data_width);
1105                 printk(KERN_INFO "%s: MSI addr32[0x%lx:0x%x] "
1106                        "addr64[0x%lx:0x%x]\n",
1107                        pbm->name,
1108                        pbm->msi32_start, pbm->msi32_len,
1109                        pbm->msi64_start, pbm->msi64_len);
1110                 printk(KERN_INFO "%s: MSI queues at RA [%p]\n",
1111                        pbm->name,
1112                        pbm->msi_queues);
1113         }
1114         pbm->setup_msi_irq = pci_sun4v_setup_msi_irq;
1115         pbm->teardown_msi_irq = pci_sun4v_teardown_msi_irq;
1116
1117         return;
1118
1119 no_msi:
1120         pbm->msiq_num = 0;
1121         printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
1122 }
1123 #else /* CONFIG_PCI_MSI */
1124 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1125 {
1126 }
1127 #endif /* !(CONFIG_PCI_MSI) */
1128
1129 static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle)
1130 {
1131         struct pci_pbm_info *pbm;
1132
1133         if (devhandle & 0x40)
1134                 pbm = &p->pbm_B;
1135         else
1136                 pbm = &p->pbm_A;
1137
1138         pbm->next = pci_pbm_root;
1139         pci_pbm_root = pbm;
1140
1141         pbm->scan_bus = pci_sun4v_scan_bus;
1142         pbm->pci_ops = &sun4v_pci_ops;
1143         pbm->config_space_reg_bits = 12;
1144
1145         pbm->index = pci_num_pbms++;
1146
1147         pbm->parent = p;
1148         pbm->prom_node = dp;
1149
1150         pbm->devhandle = devhandle;
1151
1152         pbm->name = dp->full_name;
1153
1154         printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1155
1156         pci_determine_mem_io_space(pbm);
1157
1158         pci_get_pbm_props(pbm);
1159         pci_sun4v_iommu_init(pbm);
1160         pci_sun4v_msi_init(pbm);
1161 }
1162
1163 void sun4v_pci_init(struct device_node *dp, char *model_name)
1164 {
1165         struct pci_controller_info *p;
1166         struct pci_pbm_info *pbm;
1167         struct iommu *iommu;
1168         struct property *prop;
1169         struct linux_prom64_registers *regs;
1170         u32 devhandle;
1171         int i;
1172
1173         prop = of_find_property(dp, "reg", NULL);
1174         regs = prop->value;
1175
1176         devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1177
1178         for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1179                 if (pbm->devhandle == (devhandle ^ 0x40)) {
1180                         pci_sun4v_pbm_init(pbm->parent, dp, devhandle);
1181                         return;
1182                 }
1183         }
1184
1185         for_each_possible_cpu(i) {
1186                 unsigned long page = get_zeroed_page(GFP_ATOMIC);
1187
1188                 if (!page)
1189                         goto fatal_memory_error;
1190
1191                 per_cpu(pci_iommu_batch, i).pglist = (u64 *) page;
1192         }
1193
1194         p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1195         if (!p)
1196                 goto fatal_memory_error;
1197
1198         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1199         if (!iommu)
1200                 goto fatal_memory_error;
1201
1202         p->pbm_A.iommu = iommu;
1203
1204         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1205         if (!iommu)
1206                 goto fatal_memory_error;
1207
1208         p->pbm_B.iommu = iommu;
1209
1210         /* Like PSYCHO and SCHIZO we have a 2GB aligned area
1211          * for memory space.
1212          */
1213         pci_memspace_mask = 0x7fffffffUL;
1214
1215         pci_sun4v_pbm_init(p, dp, devhandle);
1216         return;
1217
1218 fatal_memory_error:
1219         prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
1220         prom_halt();
1221 }