Pileus Git - ~andy/linux/blob - arch/sparc/mm/srmmu.c

   1 /*
   2  * srmmu.c:  SRMMU specific routines for memory management.
   3  *
   4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
   6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/vmalloc.h>
  14 #include <linux/pagemap.h>
  15 #include <linux/init.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/bootmem.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/kdebug.h>
  21 #include <linux/log2.h>
  22 #include <linux/gfp.h>
  23
  24 #include <asm/bitext.h>
  25 #include <asm/page.h>
  26 #include <asm/pgalloc.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/io.h>
  29 #include <asm/vaddrs.h>
  30 #include <asm/traps.h>
  31 #include <asm/smp.h>
  32 #include <asm/mbus.h>
  33 #include <asm/cache.h>
  34 #include <asm/oplib.h>
  35 #include <asm/asi.h>
  36 #include <asm/msi.h>
  37 #include <asm/mmu_context.h>
  38 #include <asm/io-unit.h>
  39 #include <asm/cacheflush.h>
  40 #include <asm/tlbflush.h>
  41
  42 /* Now the cpu specific definitions. */
  43 #include <asm/viking.h>
  44 #include <asm/mxcc.h>
  45 #include <asm/ross.h>
  46 #include <asm/tsunami.h>
  47 #include <asm/swift.h>
  48 #include <asm/turbosparc.h>
  49 #include <asm/leon.h>
  50
  51 #include "srmmu.h"
  52
  53 enum mbus_module srmmu_modtype;
  54 static unsigned int hwbug_bitmask;
  55 int vac_cache_size;
  56 int vac_line_size;
  57
  58 struct ctx_list *ctx_list_pool;
  59 struct ctx_list ctx_free;
  60 struct ctx_list ctx_used;
  61
  62 extern struct resource sparc_iomap;
  63
  64 extern unsigned long last_valid_pfn;
  65
  66 static pgd_t *srmmu_swapper_pg_dir;
  67
  68 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
  69
  70 #ifdef CONFIG_SMP
  71 const struct sparc32_cachetlb_ops *local_ops;
  72
  73 #define FLUSH_BEGIN(mm)
  74 #define FLUSH_END
  75 #else
  76 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
  77 #define FLUSH_END       }
  78 #endif
  79
  80 int flush_page_for_dma_global = 1;
  81
  82 char *srmmu_name;
  83
  84 ctxd_t *srmmu_ctx_table_phys;
  85 static ctxd_t *srmmu_context_table;
  86
  87 int viking_mxcc_present;
  88 static DEFINE_SPINLOCK(srmmu_context_spinlock);
  89
  90 static int is_hypersparc;
  91
  92 static int srmmu_cache_pagetables;
  93
  94 /* these will be initialized in srmmu_nocache_calcsize() */
  95 static unsigned long srmmu_nocache_size;
  96 static unsigned long srmmu_nocache_end;
  97
  98 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
  99 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
 100
 101 /* The context table is a nocache user with the biggest alignment needs. */
 102 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 103
 104 void *srmmu_nocache_pool;
 105 void *srmmu_nocache_bitmap;
 106 static struct bit_map srmmu_nocache_map;
 107
 108 static inline int srmmu_pmd_none(pmd_t pmd)
 109 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 110
 111 /* XXX should we hyper_flush_whole_icache here - Anton */
 112 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 113 { set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
 114
 115 void pmd_set(pmd_t *pmdp, pte_t *ptep)
 116 {
 117         unsigned long ptp;      /* Physical address, shifted right by 4 */
 118         int i;
 119
 120         ptp = __nocache_pa((unsigned long) ptep) >> 4;
 121         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 122                 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 123                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 124         }
 125 }
 126
 127 void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
 128 {
 129         unsigned long ptp;      /* Physical address, shifted right by 4 */
 130         int i;
 131
 132         ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
 133         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 134                 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 135                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 136         }
 137 }
 138
 139 /* Find an entry in the third-level page table.. */
 140 pte_t *pte_offset_kernel(pmd_t * dir, unsigned long address)
 141 {
 142         void *pte;
 143
 144         pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
 145         return (pte_t *) pte +
 146             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 147 }
 148
 149 /*
 150  * size: bytes to allocate in the nocache area.
 151  * align: bytes, number to align at.
 152  * Returns the virtual address of the allocated area.
 153  */
 154 static unsigned long __srmmu_get_nocache(int size, int align)
 155 {
 156         int offset;
 157
 158         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 159                 printk("Size 0x%x too small for nocache request\n", size);
 160                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
 161         }
 162         if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
 163                 printk("Size 0x%x unaligned int nocache request\n", size);
 164                 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
 165         }
 166         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 167
 168         offset = bit_map_string_get(&srmmu_nocache_map,
 169                                         size >> SRMMU_NOCACHE_BITMAP_SHIFT,
 170                                         align >> SRMMU_NOCACHE_BITMAP_SHIFT);
 171         if (offset == -1) {
 172                 printk("srmmu: out of nocache %d: %d/%d\n",
 173                     size, (int) srmmu_nocache_size,
 174                     srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 175                 return 0;
 176         }
 177
 178         return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 179 }
 180
 181 unsigned long srmmu_get_nocache(int size, int align)
 182 {
 183         unsigned long tmp;
 184
 185         tmp = __srmmu_get_nocache(size, align);
 186
 187         if (tmp)
 188                 memset((void *)tmp, 0, size);
 189
 190         return tmp;
 191 }
 192
 193 void srmmu_free_nocache(unsigned long vaddr, int size)
 194 {
 195         int offset;
 196
 197         if (vaddr < SRMMU_NOCACHE_VADDR) {
 198                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
 199                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
 200                 BUG();
 201         }
 202         if (vaddr+size > srmmu_nocache_end) {
 203                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
 204                     vaddr, srmmu_nocache_end);
 205                 BUG();
 206         }
 207         if (!is_power_of_2(size)) {
 208                 printk("Size 0x%x is not a power of 2\n", size);
 209                 BUG();
 210         }
 211         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 212                 printk("Size 0x%x is too small\n", size);
 213                 BUG();
 214         }
 215         if (vaddr & (size-1)) {
 216                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
 217                 BUG();
 218         }
 219
 220         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 221         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 222
 223         bit_map_clear(&srmmu_nocache_map, offset, size);
 224 }
 225
 226 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
 227                                                  unsigned long end);
 228
 229 extern unsigned long probe_memory(void);        /* in fault.c */
 230
 231 /*
 232  * Reserve nocache dynamically proportionally to the amount of
 233  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 234  */
 235 static void srmmu_nocache_calcsize(void)
 236 {
 237         unsigned long sysmemavail = probe_memory() / 1024;
 238         int srmmu_nocache_npages;
 239
 240         srmmu_nocache_npages =
 241                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 242
 243  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
 244         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
 245         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
 246                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
 247
 248         /* anything above 1280 blows up */
 249         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
 250                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
 251
 252         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 253         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 254 }
 255
 256 static void __init srmmu_nocache_init(void)
 257 {
 258         unsigned int bitmap_bits;
 259         pgd_t *pgd;
 260         pmd_t *pmd;
 261         pte_t *pte;
 262         unsigned long paddr, vaddr;
 263         unsigned long pteval;
 264
 265         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 266
 267         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
 268                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
 269         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 270
 271         srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
 272         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 273
 274         srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 275         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 276         init_mm.pgd = srmmu_swapper_pg_dir;
 277
 278         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 279
 280         paddr = __pa((unsigned long)srmmu_nocache_pool);
 281         vaddr = SRMMU_NOCACHE_VADDR;
 282
 283         while (vaddr < srmmu_nocache_end) {
 284                 pgd = pgd_offset_k(vaddr);
 285                 pmd = pmd_offset(__nocache_fix(pgd), vaddr);
 286                 pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
 287
 288                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 289
 290                 if (srmmu_cache_pagetables)
 291                         pteval |= SRMMU_CACHE;
 292
 293                 set_pte(__nocache_fix(pte), __pte(pteval));
 294
 295                 vaddr += PAGE_SIZE;
 296                 paddr += PAGE_SIZE;
 297         }
 298
 299         flush_cache_all();
 300         flush_tlb_all();
 301 }
 302
 303 pgd_t *get_pgd_fast(void)
 304 {
 305         pgd_t *pgd = NULL;
 306
 307         pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 308         if (pgd) {
 309                 pgd_t *init = pgd_offset_k(0);
 310                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 311                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 312                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 313         }
 314
 315         return pgd;
 316 }
 317
 318 /*
 319  * Hardware needs alignment to 256 only, but we align to whole page size
 320  * to reduce fragmentation problems due to the buddy principle.
 321  * XXX Provide actual fragmentation statistics in /proc.
 322  *
 323  * Alignments up to the page size are the same for physical and virtual
 324  * addresses of the nocache area.
 325  */
 326 pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
 327 {
 328         unsigned long pte;
 329         struct page *page;
 330
 331         if ((pte = (unsigned long)pte_alloc_one_kernel(mm, address)) == 0)
 332                 return NULL;
 333         page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
 334         pgtable_page_ctor(page);
 335         return page;
 336 }
 337
 338 void pte_free(struct mm_struct *mm, pgtable_t pte)
 339 {
 340         unsigned long p;
 341
 342         pgtable_page_dtor(pte);
 343         p = (unsigned long)page_address(pte);   /* Cached address (for test) */
 344         if (p == 0)
 345                 BUG();
 346         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
 347         p = (unsigned long) __nocache_va(p);    /* Nocached virtual */
 348         srmmu_free_nocache(p, PTE_SIZE);
 349 }
 350
 351 /*
 352  */
 353 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 354 {
 355         struct ctx_list *ctxp;
 356
 357         ctxp = ctx_free.next;
 358         if(ctxp != &ctx_free) {
 359                 remove_from_ctx_list(ctxp);
 360                 add_to_used_ctxlist(ctxp);
 361                 mm->context = ctxp->ctx_number;
 362                 ctxp->ctx_mm = mm;
 363                 return;
 364         }
 365         ctxp = ctx_used.next;
 366         if(ctxp->ctx_mm == old_mm)
 367                 ctxp = ctxp->next;
 368         if(ctxp == &ctx_used)
 369                 panic("out of mmu contexts");
 370         flush_cache_mm(ctxp->ctx_mm);
 371         flush_tlb_mm(ctxp->ctx_mm);
 372         remove_from_ctx_list(ctxp);
 373         add_to_used_ctxlist(ctxp);
 374         ctxp->ctx_mm->context = NO_CONTEXT;
 375         ctxp->ctx_mm = mm;
 376         mm->context = ctxp->ctx_number;
 377 }
 378
 379 static inline void free_context(int context)
 380 {
 381         struct ctx_list *ctx_old;
 382
 383         ctx_old = ctx_list_pool + context;
 384         remove_from_ctx_list(ctx_old);
 385         add_to_free_ctxlist(ctx_old);
 386 }
 387
 388
 389 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 390                struct task_struct *tsk)
 391 {
 392         if(mm->context == NO_CONTEXT) {
 393                 spin_lock(&srmmu_context_spinlock);
 394                 alloc_context(old_mm, mm);
 395                 spin_unlock(&srmmu_context_spinlock);
 396                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 397         }
 398
 399         if (sparc_cpu_model == sparc_leon)
 400                 leon_switch_mm();
 401
 402         if (is_hypersparc)
 403                 hyper_flush_whole_icache();
 404
 405         srmmu_set_context(mm->context);
 406 }
 407
 408 /* Low level IO area allocation on the SRMMU. */
 409 static inline void srmmu_mapioaddr(unsigned long physaddr,
 410     unsigned long virt_addr, int bus_type)
 411 {
 412         pgd_t *pgdp;
 413         pmd_t *pmdp;
 414         pte_t *ptep;
 415         unsigned long tmp;
 416
 417         physaddr &= PAGE_MASK;
 418         pgdp = pgd_offset_k(virt_addr);
 419         pmdp = pmd_offset(pgdp, virt_addr);
 420         ptep = pte_offset_kernel(pmdp, virt_addr);
 421         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 422
 423         /*
 424          * I need to test whether this is consistent over all
 425          * sun4m's.  The bus_type represents the upper 4 bits of
 426          * 36-bit physical address on the I/O space lines...
 427          */
 428         tmp |= (bus_type << 28);
 429         tmp |= SRMMU_PRIV;
 430         __flush_page_to_ram(virt_addr);
 431         set_pte(ptep, __pte(tmp));
 432 }
 433
 434 void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
 435                       unsigned long xva, unsigned int len)
 436 {
 437         while (len != 0) {
 438                 len -= PAGE_SIZE;
 439                 srmmu_mapioaddr(xpa, xva, bus);
 440                 xva += PAGE_SIZE;
 441                 xpa += PAGE_SIZE;
 442         }
 443         flush_tlb_all();
 444 }
 445
 446 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
 447 {
 448         pgd_t *pgdp;
 449         pmd_t *pmdp;
 450         pte_t *ptep;
 451
 452         pgdp = pgd_offset_k(virt_addr);
 453         pmdp = pmd_offset(pgdp, virt_addr);
 454         ptep = pte_offset_kernel(pmdp, virt_addr);
 455
 456         /* No need to flush uncacheable page. */
 457         __pte_clear(ptep);
 458 }
 459
 460 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 461 {
 462         while (len != 0) {
 463                 len -= PAGE_SIZE;
 464                 srmmu_unmapioaddr(virt_addr);
 465                 virt_addr += PAGE_SIZE;
 466         }
 467         flush_tlb_all();
 468 }
 469
 470 /*
 471  * On the SRMMU we do not have the problems with limited tlb entries
 472  * for mapping kernel pages, so we just take things from the free page
 473  * pool.  As a side effect we are putting a little too much pressure
 474  * on the gfp() subsystem.  This setup also makes the logic of the
 475  * iommu mapping code a lot easier as we can transparently handle
 476  * mappings on the kernel stack without any special code.
 477  */
 478 struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
 479 {
 480         struct thread_info *ret;
 481
 482         ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
 483                                                      THREAD_INFO_ORDER);
 484 #ifdef CONFIG_DEBUG_STACK_USAGE
 485         if (ret)
 486                 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
 487 #endif /* DEBUG_STACK_USAGE */
 488
 489         return ret;
 490 }
 491
 492 void free_thread_info(struct thread_info *ti)
 493 {
 494         free_pages((unsigned long)ti, THREAD_INFO_ORDER);
 495 }
 496
 497 /* tsunami.S */
 498 extern void tsunami_flush_cache_all(void);
 499 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 500 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 501 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 502 extern void tsunami_flush_page_to_ram(unsigned long page);
 503 extern void tsunami_flush_page_for_dma(unsigned long page);
 504 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 505 extern void tsunami_flush_tlb_all(void);
 506 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 507 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 508 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 509 extern void tsunami_setup_blockops(void);
 510
 511 /* swift.S */
 512 extern void swift_flush_cache_all(void);
 513 extern void swift_flush_cache_mm(struct mm_struct *mm);
 514 extern void swift_flush_cache_range(struct vm_area_struct *vma,
 515                                     unsigned long start, unsigned long end);
 516 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 517 extern void swift_flush_page_to_ram(unsigned long page);
 518 extern void swift_flush_page_for_dma(unsigned long page);
 519 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 520 extern void swift_flush_tlb_all(void);
 521 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 522 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
 523                                   unsigned long start, unsigned long end);
 524 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 525
 526 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 527 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 528 {
 529         int cctx, ctx1;
 530
 531         page &= PAGE_MASK;
 532         if ((ctx1 = vma->vm_mm->context) != -1) {
 533                 cctx = srmmu_get_context();
 534 /* Is context # ever different from current context? P3 */
 535                 if (cctx != ctx1) {
 536                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 537                         srmmu_set_context(ctx1);
 538                         swift_flush_page(page);
 539                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 540                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 541                         srmmu_set_context(cctx);
 542                 } else {
 543                          /* Rm. prot. bits from virt. c. */
 544                         /* swift_flush_cache_all(); */
 545                         /* swift_flush_cache_page(vma, page); */
 546                         swift_flush_page(page);
 547
 548                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 549                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 550                         /* same as above: srmmu_flush_tlb_page() */
 551                 }
 552         }
 553 }
 554 #endif
 555
 556 /*
 557  * The following are all MBUS based SRMMU modules, and therefore could
 558  * be found in a multiprocessor configuration.  On the whole, these
 559  * chips seems to be much more touchy about DVMA and page tables
 560  * with respect to cache coherency.
 561  */
 562
 563 /* viking.S */
 564 extern void viking_flush_cache_all(void);
 565 extern void viking_flush_cache_mm(struct mm_struct *mm);
 566 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
 567                                      unsigned long end);
 568 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 569 extern void viking_flush_page_to_ram(unsigned long page);
 570 extern void viking_flush_page_for_dma(unsigned long page);
 571 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
 572 extern void viking_flush_page(unsigned long page);
 573 extern void viking_mxcc_flush_page(unsigned long page);
 574 extern void viking_flush_tlb_all(void);
 575 extern void viking_flush_tlb_mm(struct mm_struct *mm);
 576 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 577                                    unsigned long end);
 578 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
 579                                   unsigned long page);
 580 extern void sun4dsmp_flush_tlb_all(void);
 581 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
 582 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 583                                    unsigned long end);
 584 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
 585                                   unsigned long page);
 586
 587 /* hypersparc.S */
 588 extern void hypersparc_flush_cache_all(void);
 589 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
 590 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 591 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 592 extern void hypersparc_flush_page_to_ram(unsigned long page);
 593 extern void hypersparc_flush_page_for_dma(unsigned long page);
 594 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 595 extern void hypersparc_flush_tlb_all(void);
 596 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
 597 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 598 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 599 extern void hypersparc_setup_blockops(void);
 600
 601 /*
 602  * NOTE: All of this startup code assumes the low 16mb (approx.) of
 603  *       kernel mappings are done with one single contiguous chunk of
 604  *       ram.  On small ram machines (classics mainly) we only get
 605  *       around 8mb mapped for us.
 606  */
 607
 608 static void __init early_pgtable_allocfail(char *type)
 609 {
 610         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
 611         prom_halt();
 612 }
 613
 614 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
 615                                                         unsigned long end)
 616 {
 617         pgd_t *pgdp;
 618         pmd_t *pmdp;
 619         pte_t *ptep;
 620
 621         while(start < end) {
 622                 pgdp = pgd_offset_k(start);
 623                 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
 624                         pmdp = (pmd_t *) __srmmu_get_nocache(
 625                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 626                         if (pmdp == NULL)
 627                                 early_pgtable_allocfail("pmd");
 628                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
 629                         pgd_set(__nocache_fix(pgdp), pmdp);
 630                 }
 631                 pmdp = pmd_offset(__nocache_fix(pgdp), start);
 632                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
 633                         ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 634                         if (ptep == NULL)
 635                                 early_pgtable_allocfail("pte");
 636                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
 637                         pmd_set(__nocache_fix(pmdp), ptep);
 638                 }
 639                 if (start > (0xffffffffUL - PMD_SIZE))
 640                         break;
 641                 start = (start + PMD_SIZE) & PMD_MASK;
 642         }
 643 }
 644
 645 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
 646                                                   unsigned long end)
 647 {
 648         pgd_t *pgdp;
 649         pmd_t *pmdp;
 650         pte_t *ptep;
 651
 652         while(start < end) {
 653                 pgdp = pgd_offset_k(start);
 654                 if (pgd_none(*pgdp)) {
 655                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 656                         if (pmdp == NULL)
 657                                 early_pgtable_allocfail("pmd");
 658                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
 659                         pgd_set(pgdp, pmdp);
 660                 }
 661                 pmdp = pmd_offset(pgdp, start);
 662                 if(srmmu_pmd_none(*pmdp)) {
 663                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
 664                                                              PTE_SIZE);
 665                         if (ptep == NULL)
 666                                 early_pgtable_allocfail("pte");
 667                         memset(ptep, 0, PTE_SIZE);
 668                         pmd_set(pmdp, ptep);
 669                 }
 670                 if (start > (0xffffffffUL - PMD_SIZE))
 671                         break;
 672                 start = (start + PMD_SIZE) & PMD_MASK;
 673         }
 674 }
 675
 676 /*
 677  * This is much cleaner than poking around physical address space
 678  * looking at the prom's page table directly which is what most
 679  * other OS's do.  Yuck... this is much better.
 680  */
 681 static void __init srmmu_inherit_prom_mappings(unsigned long start,
 682                                                unsigned long end)
 683 {
 684         pgd_t *pgdp;
 685         pmd_t *pmdp;
 686         pte_t *ptep;
 687         int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
 688         unsigned long prompte;
 689
 690         while(start <= end) {
 691                 if (start == 0)
 692                         break; /* probably wrap around */
 693                 if(start == 0xfef00000)
 694                         start = KADB_DEBUGGER_BEGVM;
 695                 if(!(prompte = srmmu_hwprobe(start))) {
 696                         start += PAGE_SIZE;
 697                         continue;
 698                 }
 699
 700                 /* A red snapper, see what it really is. */
 701                 what = 0;
 702
 703                 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
 704                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
 705                                 what = 1;
 706                 }
 707
 708                 if(!(start & ~(SRMMU_PGDIR_MASK))) {
 709                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
 710                            prompte)
 711                                 what = 2;
 712                 }
 713
 714                 pgdp = pgd_offset_k(start);
 715                 if(what == 2) {
 716                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
 717                         start += SRMMU_PGDIR_SIZE;
 718                         continue;
 719                 }
 720                 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
 721                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 722                         if (pmdp == NULL)
 723                                 early_pgtable_allocfail("pmd");
 724                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
 725                         pgd_set(__nocache_fix(pgdp), pmdp);
 726                 }
 727                 pmdp = pmd_offset(__nocache_fix(pgdp), start);
 728                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
 729                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
 730                                                              PTE_SIZE);
 731                         if (ptep == NULL)
 732                                 early_pgtable_allocfail("pte");
 733                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
 734                         pmd_set(__nocache_fix(pmdp), ptep);
 735                 }
 736                 if(what == 1) {
 737                         /*
 738                          * We bend the rule where all 16 PTPs in a pmd_t point
 739                          * inside the same PTE page, and we leak a perfectly
 740                          * good hardware PTE piece. Alternatives seem worse.
 741                          */
 742                         unsigned int x; /* Index of HW PMD in soft cluster */
 743                         x = (start >> PMD_SHIFT) & 15;
 744                         *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
 745                         start += SRMMU_REAL_PMD_SIZE;
 746                         continue;
 747                 }
 748                 ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
 749                 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
 750                 start += PAGE_SIZE;
 751         }
 752 }
 753
 754 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
 755
 756 /* Create a third-level SRMMU 16MB page mapping. */
 757 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
 758 {
 759         pgd_t *pgdp = pgd_offset_k(vaddr);
 760         unsigned long big_pte;
 761
 762         big_pte = KERNEL_PTE(phys_base >> 4);
 763         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
 764 }
 765
 766 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
 767 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
 768 {
 769         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
 770         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
 771         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
 772         /* Map "low" memory only */
 773         const unsigned long min_vaddr = PAGE_OFFSET;
 774         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
 775
 776         if (vstart < min_vaddr || vstart >= max_vaddr)
 777                 return vstart;
 778
 779         if (vend > max_vaddr || vend < min_vaddr)
 780                 vend = max_vaddr;
 781
 782         while(vstart < vend) {
 783                 do_large_mapping(vstart, pstart);
 784                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
 785         }
 786         return vstart;
 787 }
 788
 789 static inline void map_kernel(void)
 790 {
 791         int i;
 792
 793         if (phys_base > 0) {
 794                 do_large_mapping(PAGE_OFFSET, phys_base);
 795         }
 796
 797         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
 798                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
 799         }
 800 }
 801
 802 /* Paging initialization on the Sparc Reference MMU. */
 803 extern void sparc_context_init(int);
 804
 805 void (*poke_srmmu)(void) __cpuinitdata = NULL;
 806
 807 extern unsigned long bootmem_init(unsigned long *pages_avail);
 808
 809 void __init srmmu_paging_init(void)
 810 {
 811         int i;
 812         phandle cpunode;
 813         char node_str[128];
 814         pgd_t *pgd;
 815         pmd_t *pmd;
 816         pte_t *pte;
 817         unsigned long pages_avail;
 818
 819         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
 820
 821         if (sparc_cpu_model == sun4d)
 822                 num_contexts = 65536; /* We know it is Viking */
 823         else {
 824                 /* Find the number of contexts on the srmmu. */
 825                 cpunode = prom_getchild(prom_root_node);
 826                 num_contexts = 0;
 827                 while(cpunode != 0) {
 828                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
 829                         if(!strcmp(node_str, "cpu")) {
 830                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
 831                                 break;
 832                         }
 833                         cpunode = prom_getsibling(cpunode);
 834                 }
 835         }
 836
 837         if(!num_contexts) {
 838                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
 839                 prom_halt();
 840         }
 841
 842         pages_avail = 0;
 843         last_valid_pfn = bootmem_init(&pages_avail);
 844
 845         srmmu_nocache_calcsize();
 846         srmmu_nocache_init();
 847         srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
 848         map_kernel();
 849
 850         /* ctx table has to be physically aligned to its size */
 851         srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
 852         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
 853
 854         for(i = 0; i < num_contexts; i++)
 855                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
 856
 857         flush_cache_all();
 858         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
 859 #ifdef CONFIG_SMP
 860         /* Stop from hanging here... */
 861         local_ops->tlb_all();
 862 #else
 863         flush_tlb_all();
 864 #endif
 865         poke_srmmu();
 866
 867         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
 868         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
 869
 870         srmmu_allocate_ptable_skeleton(
 871                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
 872         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
 873
 874         pgd = pgd_offset_k(PKMAP_BASE);
 875         pmd = pmd_offset(pgd, PKMAP_BASE);
 876         pte = pte_offset_kernel(pmd, PKMAP_BASE);
 877         pkmap_page_table = pte;
 878
 879         flush_cache_all();
 880         flush_tlb_all();
 881
 882         sparc_context_init(num_contexts);
 883
 884         kmap_init();
 885
 886         {
 887                 unsigned long zones_size[MAX_NR_ZONES];
 888                 unsigned long zholes_size[MAX_NR_ZONES];
 889                 unsigned long npages;
 890                 int znum;
 891
 892                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
 893                         zones_size[znum] = zholes_size[znum] = 0;
 894
 895                 npages = max_low_pfn - pfn_base;
 896
 897                 zones_size[ZONE_DMA] = npages;
 898                 zholes_size[ZONE_DMA] = npages - pages_avail;
 899
 900                 npages = highend_pfn - max_low_pfn;
 901                 zones_size[ZONE_HIGHMEM] = npages;
 902                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
 903
 904                 free_area_init_node(0, zones_size, pfn_base, zholes_size);
 905         }
 906 }
 907
 908 void mmu_info(struct seq_file *m)
 909 {
 910         seq_printf(m,
 911                    "MMU type\t: %s\n"
 912                    "contexts\t: %d\n"
 913                    "nocache total\t: %ld\n"
 914                    "nocache used\t: %d\n",
 915                    srmmu_name,
 916                    num_contexts,
 917                    srmmu_nocache_size,
 918                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 919 }
 920
 921 void destroy_context(struct mm_struct *mm)
 922 {
 923
 924         if(mm->context != NO_CONTEXT) {
 925                 flush_cache_mm(mm);
 926                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
 927                 flush_tlb_mm(mm);
 928                 spin_lock(&srmmu_context_spinlock);
 929                 free_context(mm->context);
 930                 spin_unlock(&srmmu_context_spinlock);
 931                 mm->context = NO_CONTEXT;
 932         }
 933 }
 934
 935 /* Init various srmmu chip types. */
 936 static void __init srmmu_is_bad(void)
 937 {
 938         prom_printf("Could not determine SRMMU chip type.\n");
 939         prom_halt();
 940 }
 941
 942 static void __init init_vac_layout(void)
 943 {
 944         phandle nd;
 945         int cache_lines;
 946         char node_str[128];
 947 #ifdef CONFIG_SMP
 948         int cpu = 0;
 949         unsigned long max_size = 0;
 950         unsigned long min_line_size = 0x10000000;
 951 #endif
 952
 953         nd = prom_getchild(prom_root_node);
 954         while((nd = prom_getsibling(nd)) != 0) {
 955                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
 956                 if(!strcmp(node_str, "cpu")) {
 957                         vac_line_size = prom_getint(nd, "cache-line-size");
 958                         if (vac_line_size == -1) {
 959                                 prom_printf("can't determine cache-line-size, "
 960                                             "halting.\n");
 961                                 prom_halt();
 962                         }
 963                         cache_lines = prom_getint(nd, "cache-nlines");
 964                         if (cache_lines == -1) {
 965                                 prom_printf("can't determine cache-nlines, halting.\n");
 966                                 prom_halt();
 967                         }
 968
 969                         vac_cache_size = cache_lines * vac_line_size;
 970 #ifdef CONFIG_SMP
 971                         if(vac_cache_size > max_size)
 972                                 max_size = vac_cache_size;
 973                         if(vac_line_size < min_line_size)
 974                                 min_line_size = vac_line_size;
 975                         //FIXME: cpus not contiguous!!
 976                         cpu++;
 977                         if (cpu >= nr_cpu_ids || !cpu_online(cpu))
 978                                 break;
 979 #else
 980                         break;
 981 #endif
 982                 }
 983         }
 984         if(nd == 0) {
 985                 prom_printf("No CPU nodes found, halting.\n");
 986                 prom_halt();
 987         }
 988 #ifdef CONFIG_SMP
 989         vac_cache_size = max_size;
 990         vac_line_size = min_line_size;
 991 #endif
 992         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
 993                (int)vac_cache_size, (int)vac_line_size);
 994 }
 995
 996 static void __cpuinit poke_hypersparc(void)
 997 {
 998         volatile unsigned long clear;
 999         unsigned long mreg = srmmu_get_mmureg();
1000
1001         hyper_flush_unconditional_combined();
1002
1003         mreg &= ~(HYPERSPARC_CWENABLE);
1004         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1005         mreg |= (HYPERSPARC_CMODE);
1006
1007         srmmu_set_mmureg(mreg);
1008
1009 #if 0 /* XXX I think this is bad news... -DaveM */
1010         hyper_clear_all_tags();
1011 #endif
1012
1013         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1014         hyper_flush_whole_icache();
1015         clear = srmmu_get_faddr();
1016         clear = srmmu_get_fstatus();
1017 }
1018
1019 static const struct sparc32_cachetlb_ops hypersparc_ops = {
1020         .cache_all      = hypersparc_flush_cache_all,
1021         .cache_mm       = hypersparc_flush_cache_mm,
1022         .cache_page     = hypersparc_flush_cache_page,
1023         .cache_range    = hypersparc_flush_cache_range,
1024         .tlb_all        = hypersparc_flush_tlb_all,
1025         .tlb_mm         = hypersparc_flush_tlb_mm,
1026         .tlb_page       = hypersparc_flush_tlb_page,
1027         .tlb_range      = hypersparc_flush_tlb_range,
1028         .page_to_ram    = hypersparc_flush_page_to_ram,
1029         .sig_insns      = hypersparc_flush_sig_insns,
1030         .page_for_dma   = hypersparc_flush_page_for_dma,
1031 };
1032
1033 static void __init init_hypersparc(void)
1034 {
1035         srmmu_name = "ROSS HyperSparc";
1036         srmmu_modtype = HyperSparc;
1037
1038         init_vac_layout();
1039
1040         is_hypersparc = 1;
1041         sparc32_cachetlb_ops = &hypersparc_ops;
1042
1043         poke_srmmu = poke_hypersparc;
1044
1045         hypersparc_setup_blockops();
1046 }
1047
1048 static void __cpuinit poke_swift(void)
1049 {
1050         unsigned long mreg;
1051
1052         /* Clear any crap from the cache or else... */
1053         swift_flush_cache_all();
1054
1055         /* Enable I & D caches */
1056         mreg = srmmu_get_mmureg();
1057         mreg |= (SWIFT_IE | SWIFT_DE);
1058         /*
1059          * The Swift branch folding logic is completely broken.  At
1060          * trap time, if things are just right, if can mistakenly
1061          * think that a trap is coming from kernel mode when in fact
1062          * it is coming from user mode (it mis-executes the branch in
1063          * the trap code).  So you see things like crashme completely
1064          * hosing your machine which is completely unacceptable.  Turn
1065          * this shit off... nice job Fujitsu.
1066          */
1067         mreg &= ~(SWIFT_BF);
1068         srmmu_set_mmureg(mreg);
1069 }
1070
1071 static const struct sparc32_cachetlb_ops swift_ops = {
1072         .cache_all      = swift_flush_cache_all,
1073         .cache_mm       = swift_flush_cache_mm,
1074         .cache_page     = swift_flush_cache_page,
1075         .cache_range    = swift_flush_cache_range,
1076         .tlb_all        = swift_flush_tlb_all,
1077         .tlb_mm         = swift_flush_tlb_mm,
1078         .tlb_page       = swift_flush_tlb_page,
1079         .tlb_range      = swift_flush_tlb_range,
1080         .page_to_ram    = swift_flush_page_to_ram,
1081         .sig_insns      = swift_flush_sig_insns,
1082         .page_for_dma   = swift_flush_page_for_dma,
1083 };
1084
1085 #define SWIFT_MASKID_ADDR  0x10003018
1086 static void __init init_swift(void)
1087 {
1088         unsigned long swift_rev;
1089
1090         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1091                              "srl %0, 0x18, %0\n\t" :
1092                              "=r" (swift_rev) :
1093                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1094         srmmu_name = "Fujitsu Swift";
1095         switch(swift_rev) {
1096         case 0x11:
1097         case 0x20:
1098         case 0x23:
1099         case 0x30:
1100                 srmmu_modtype = Swift_lots_o_bugs;
1101                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1102                 /*
1103                  * Gee george, I wonder why Sun is so hush hush about
1104                  * this hardware bug... really braindamage stuff going
1105                  * on here.  However I think we can find a way to avoid
1106                  * all of the workaround overhead under Linux.  Basically,
1107                  * any page fault can cause kernel pages to become user
1108                  * accessible (the mmu gets confused and clears some of
1109                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1110                  * horrible eh?  But wait, after extensive testing it appears
1111                  * that if you use pgd_t level large kernel pte's (like the
1112                  * 4MB pages on the Pentium) the bug does not get tripped
1113                  * at all.  This avoids almost all of the major overhead.
1114                  * Welcome to a world where your vendor tells you to,
1115                  * "apply this kernel patch" instead of "sorry for the
1116                  * broken hardware, send it back and we'll give you
1117                  * properly functioning parts"
1118                  */
1119                 break;
1120         case 0x25:
1121         case 0x31:
1122                 srmmu_modtype = Swift_bad_c;
1123                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1124                 /*
1125                  * You see Sun allude to this hardware bug but never
1126                  * admit things directly, they'll say things like,
1127                  * "the Swift chip cache problems" or similar.
1128                  */
1129                 break;
1130         default:
1131                 srmmu_modtype = Swift_ok;
1132                 break;
1133         }
1134
1135         sparc32_cachetlb_ops = &swift_ops;
1136         flush_page_for_dma_global = 0;
1137
1138         /*
1139          * Are you now convinced that the Swift is one of the
1140          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1141          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1142          * you examined the microcode of the Swift you'd find
1143          * XXX's all over the place.
1144          */
1145         poke_srmmu = poke_swift;
1146 }
1147
1148 static void turbosparc_flush_cache_all(void)
1149 {
1150         flush_user_windows();
1151         turbosparc_idflash_clear();
1152 }
1153
1154 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1155 {
1156         FLUSH_BEGIN(mm)
1157         flush_user_windows();
1158         turbosparc_idflash_clear();
1159         FLUSH_END
1160 }
1161
1162 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1163 {
1164         FLUSH_BEGIN(vma->vm_mm)
1165         flush_user_windows();
1166         turbosparc_idflash_clear();
1167         FLUSH_END
1168 }
1169
1170 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1171 {
1172         FLUSH_BEGIN(vma->vm_mm)
1173         flush_user_windows();
1174         if (vma->vm_flags & VM_EXEC)
1175                 turbosparc_flush_icache();
1176         turbosparc_flush_dcache();
1177         FLUSH_END
1178 }
1179
1180 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1181 static void turbosparc_flush_page_to_ram(unsigned long page)
1182 {
1183 #ifdef TURBOSPARC_WRITEBACK
1184         volatile unsigned long clear;
1185
1186         if (srmmu_hwprobe(page))
1187                 turbosparc_flush_page_cache(page);
1188         clear = srmmu_get_fstatus();
1189 #endif
1190 }
1191
1192 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1193 {
1194 }
1195
1196 static void turbosparc_flush_page_for_dma(unsigned long page)
1197 {
1198         turbosparc_flush_dcache();
1199 }
1200
1201 static void turbosparc_flush_tlb_all(void)
1202 {
1203         srmmu_flush_whole_tlb();
1204 }
1205
1206 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1207 {
1208         FLUSH_BEGIN(mm)
1209         srmmu_flush_whole_tlb();
1210         FLUSH_END
1211 }
1212
1213 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1214 {
1215         FLUSH_BEGIN(vma->vm_mm)
1216         srmmu_flush_whole_tlb();
1217         FLUSH_END
1218 }
1219
1220 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1221 {
1222         FLUSH_BEGIN(vma->vm_mm)
1223         srmmu_flush_whole_tlb();
1224         FLUSH_END
1225 }
1226
1227
1228 static void __cpuinit poke_turbosparc(void)
1229 {
1230         unsigned long mreg = srmmu_get_mmureg();
1231         unsigned long ccreg;
1232
1233         /* Clear any crap from the cache or else... */
1234         turbosparc_flush_cache_all();
1235         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1236         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1237         srmmu_set_mmureg(mreg);
1238
1239         ccreg = turbosparc_get_ccreg();
1240
1241 #ifdef TURBOSPARC_WRITEBACK
1242         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1243         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1244                         /* Write-back D-cache, emulate VLSI
1245                          * abortion number three, not number one */
1246 #else
1247         /* For now let's play safe, optimize later */
1248         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1249                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1250         ccreg &= ~(TURBOSPARC_uS2);
1251                         /* Emulate VLSI abortion number three, not number one */
1252 #endif
1253
1254         switch (ccreg & 7) {
1255         case 0: /* No SE cache */
1256         case 7: /* Test mode */
1257                 break;
1258         default:
1259                 ccreg |= (TURBOSPARC_SCENABLE);
1260         }
1261         turbosparc_set_ccreg (ccreg);
1262
1263         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1264         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1265         srmmu_set_mmureg(mreg);
1266 }
1267
1268 static const struct sparc32_cachetlb_ops turbosparc_ops = {
1269         .cache_all      = turbosparc_flush_cache_all,
1270         .cache_mm       = turbosparc_flush_cache_mm,
1271         .cache_page     = turbosparc_flush_cache_page,
1272         .cache_range    = turbosparc_flush_cache_range,
1273         .tlb_all        = turbosparc_flush_tlb_all,
1274         .tlb_mm         = turbosparc_flush_tlb_mm,
1275         .tlb_page       = turbosparc_flush_tlb_page,
1276         .tlb_range      = turbosparc_flush_tlb_range,
1277         .page_to_ram    = turbosparc_flush_page_to_ram,
1278         .sig_insns      = turbosparc_flush_sig_insns,
1279         .page_for_dma   = turbosparc_flush_page_for_dma,
1280 };
1281
1282 static void __init init_turbosparc(void)
1283 {
1284         srmmu_name = "Fujitsu TurboSparc";
1285         srmmu_modtype = TurboSparc;
1286         sparc32_cachetlb_ops = &turbosparc_ops;
1287         poke_srmmu = poke_turbosparc;
1288 }
1289
1290 static void __cpuinit poke_tsunami(void)
1291 {
1292         unsigned long mreg = srmmu_get_mmureg();
1293
1294         tsunami_flush_icache();
1295         tsunami_flush_dcache();
1296         mreg &= ~TSUNAMI_ITD;
1297         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1298         srmmu_set_mmureg(mreg);
1299 }
1300
1301 static const struct sparc32_cachetlb_ops tsunami_ops = {
1302         .cache_all      = tsunami_flush_cache_all,
1303         .cache_mm       = tsunami_flush_cache_mm,
1304         .cache_page     = tsunami_flush_cache_page,
1305         .cache_range    = tsunami_flush_cache_range,
1306         .tlb_all        = tsunami_flush_tlb_all,
1307         .tlb_mm         = tsunami_flush_tlb_mm,
1308         .tlb_page       = tsunami_flush_tlb_page,
1309         .tlb_range      = tsunami_flush_tlb_range,
1310         .page_to_ram    = tsunami_flush_page_to_ram,
1311         .sig_insns      = tsunami_flush_sig_insns,
1312         .page_for_dma   = tsunami_flush_page_for_dma,
1313 };
1314
1315 static void __init init_tsunami(void)
1316 {
1317         /*
1318          * Tsunami's pretty sane, Sun and TI actually got it
1319          * somewhat right this time.  Fujitsu should have
1320          * taken some lessons from them.
1321          */
1322
1323         srmmu_name = "TI Tsunami";
1324         srmmu_modtype = Tsunami;
1325         sparc32_cachetlb_ops = &tsunami_ops;
1326         poke_srmmu = poke_tsunami;
1327
1328         tsunami_setup_blockops();
1329 }
1330
1331 static void __cpuinit poke_viking(void)
1332 {
1333         unsigned long mreg = srmmu_get_mmureg();
1334         static int smp_catch;
1335
1336         if (viking_mxcc_present) {
1337                 unsigned long mxcc_control = mxcc_get_creg();
1338
1339                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1340                 mxcc_control &= ~(MXCC_CTL_RRC);
1341                 mxcc_set_creg(mxcc_control);
1342
1343                 /*
1344                  * We don't need memory parity checks.
1345                  * XXX This is a mess, have to dig out later. ecd.
1346                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1347                  */
1348
1349                 /* We do cache ptables on MXCC. */
1350                 mreg |= VIKING_TCENABLE;
1351         } else {
1352                 unsigned long bpreg;
1353
1354                 mreg &= ~(VIKING_TCENABLE);
1355                 if(smp_catch++) {
1356                         /* Must disable mixed-cmd mode here for other cpu's. */
1357                         bpreg = viking_get_bpreg();
1358                         bpreg &= ~(VIKING_ACTION_MIX);
1359                         viking_set_bpreg(bpreg);
1360
1361                         /* Just in case PROM does something funny. */
1362                         msi_set_sync();
1363                 }
1364         }
1365
1366         mreg |= VIKING_SPENABLE;
1367         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1368         mreg |= VIKING_SBENABLE;
1369         mreg &= ~(VIKING_ACENABLE);
1370         srmmu_set_mmureg(mreg);
1371 }
1372
1373 static struct sparc32_cachetlb_ops viking_ops = {
1374         .cache_all      = viking_flush_cache_all,
1375         .cache_mm       = viking_flush_cache_mm,
1376         .cache_page     = viking_flush_cache_page,
1377         .cache_range    = viking_flush_cache_range,
1378         .tlb_all        = viking_flush_tlb_all,
1379         .tlb_mm         = viking_flush_tlb_mm,
1380         .tlb_page       = viking_flush_tlb_page,
1381         .tlb_range      = viking_flush_tlb_range,
1382         .page_to_ram    = viking_flush_page_to_ram,
1383         .sig_insns      = viking_flush_sig_insns,
1384         .page_for_dma   = viking_flush_page_for_dma,
1385 };
1386
1387 #ifdef CONFIG_SMP
1388 /* On sun4d the cpu broadcasts local TLB flushes, so we can just
1389  * perform the local TLB flush and all the other cpus will see it.
1390  * But, unfortunately, there is a bug in the sun4d XBUS backplane
1391  * that requires that we add some synchronization to these flushes.
1392  *
1393  * The bug is that the fifo which keeps track of all the pending TLB
1394  * broadcasts in the system is an entry or two too small, so if we
1395  * have too many going at once we'll overflow that fifo and lose a TLB
1396  * flush resulting in corruption.
1397  *
1398  * Our workaround is to take a global spinlock around the TLB flushes,
1399  * which guarentees we won't ever have too many pending.  It's a big
1400  * hammer, but a semaphore like system to make sure we only have N TLB
1401  * flushes going at once will require SMP locking anyways so there's
1402  * no real value in trying any harder than this.
1403  */
1404 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops = {
1405         .cache_all      = viking_flush_cache_all,
1406         .cache_mm       = viking_flush_cache_mm,
1407         .cache_page     = viking_flush_cache_page,
1408         .cache_range    = viking_flush_cache_range,
1409         .tlb_all        = sun4dsmp_flush_tlb_all,
1410         .tlb_mm         = sun4dsmp_flush_tlb_mm,
1411         .tlb_page       = sun4dsmp_flush_tlb_page,
1412         .tlb_range      = sun4dsmp_flush_tlb_range,
1413         .page_to_ram    = viking_flush_page_to_ram,
1414         .sig_insns      = viking_flush_sig_insns,
1415         .page_for_dma   = viking_flush_page_for_dma,
1416 };
1417 #endif
1418
1419 static void __init init_viking(void)
1420 {
1421         unsigned long mreg = srmmu_get_mmureg();
1422
1423         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1424         if(mreg & VIKING_MMODE) {
1425                 srmmu_name = "TI Viking";
1426                 viking_mxcc_present = 0;
1427                 msi_set_sync();
1428
1429                 /*
1430                  * We need this to make sure old viking takes no hits
1431                  * on it's cache for dma snoops to workaround the
1432                  * "load from non-cacheable memory" interrupt bug.
1433                  * This is only necessary because of the new way in
1434                  * which we use the IOMMU.
1435                  */
1436                 viking_ops.page_for_dma = viking_flush_page;
1437 #ifdef CONFIG_SMP
1438                 viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
1439 #endif
1440                 flush_page_for_dma_global = 0;
1441         } else {
1442                 srmmu_name = "TI Viking/MXCC";
1443                 viking_mxcc_present = 1;
1444                 srmmu_cache_pagetables = 1;
1445         }
1446
1447         sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1448                 &viking_ops;
1449 #ifdef CONFIG_SMP
1450         if (sparc_cpu_model == sun4d)
1451                 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1452                         &viking_sun4d_smp_ops;
1453 #endif
1454
1455         poke_srmmu = poke_viking;
1456 }
1457
1458 /* Probe for the srmmu chip version. */
1459 static void __init get_srmmu_type(void)
1460 {
1461         unsigned long mreg, psr;
1462         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1463
1464         srmmu_modtype = SRMMU_INVAL_MOD;
1465         hwbug_bitmask = 0;
1466
1467         mreg = srmmu_get_mmureg(); psr = get_psr();
1468         mod_typ = (mreg & 0xf0000000) >> 28;
1469         mod_rev = (mreg & 0x0f000000) >> 24;
1470         psr_typ = (psr >> 28) & 0xf;
1471         psr_vers = (psr >> 24) & 0xf;
1472
1473         /* First, check for sparc-leon. */
1474         if (sparc_cpu_model == sparc_leon) {
1475                 init_leon();
1476                 return;
1477         }
1478
1479         /* Second, check for HyperSparc or Cypress. */
1480         if(mod_typ == 1) {
1481                 switch(mod_rev) {
1482                 case 7:
1483                         /* UP or MP Hypersparc */
1484                         init_hypersparc();
1485                         break;
1486                 case 0:
1487                 case 2:
1488                 case 10:
1489                 case 11:
1490                 case 12:
1491                 case 13:
1492                 case 14:
1493                 case 15:
1494                 default:
1495                         prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1496                         prom_halt();
1497                         break;
1498                 }
1499                 return;
1500         }
1501
1502         /*
1503          * Now Fujitsu TurboSparc. It might happen that it is
1504          * in Swift emulation mode, so we will check later...
1505          */
1506         if (psr_typ == 0 && psr_vers == 5) {
1507                 init_turbosparc();
1508                 return;
1509         }
1510
1511         /* Next check for Fujitsu Swift. */
1512         if(psr_typ == 0 && psr_vers == 4) {
1513                 phandle cpunode;
1514                 char node_str[128];
1515
1516                 /* Look if it is not a TurboSparc emulating Swift... */
1517                 cpunode = prom_getchild(prom_root_node);
1518                 while((cpunode = prom_getsibling(cpunode)) != 0) {
1519                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1520                         if(!strcmp(node_str, "cpu")) {
1521                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1522                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1523                                         init_turbosparc();
1524                                         return;
1525                                 }
1526                                 break;
1527                         }
1528                 }
1529
1530                 init_swift();
1531                 return;
1532         }
1533
1534         /* Now the Viking family of srmmu. */
1535         if(psr_typ == 4 &&
1536            ((psr_vers == 0) ||
1537             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1538                 init_viking();
1539                 return;
1540         }
1541
1542         /* Finally the Tsunami. */
1543         if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1544                 init_tsunami();
1545                 return;
1546         }
1547
1548         /* Oh well */
1549         srmmu_is_bad();
1550 }
1551
1552 #ifdef CONFIG_SMP
1553 /* Local cross-calls. */
1554 static void smp_flush_page_for_dma(unsigned long page)
1555 {
1556         xc1((smpfunc_t) local_ops->page_for_dma, page);
1557         local_ops->page_for_dma(page);
1558 }
1559
1560 static void smp_flush_cache_all(void)
1561 {
1562         xc0((smpfunc_t) local_ops->cache_all);
1563         local_ops->cache_all();
1564 }
1565
1566 static void smp_flush_tlb_all(void)
1567 {
1568         xc0((smpfunc_t) local_ops->tlb_all);
1569         local_ops->tlb_all();
1570 }
1571
1572 static void smp_flush_cache_mm(struct mm_struct *mm)
1573 {
1574         if (mm->context != NO_CONTEXT) {
1575                 cpumask_t cpu_mask;
1576                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1577                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1578                 if (!cpumask_empty(&cpu_mask))
1579                         xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm);
1580                 local_ops->cache_mm(mm);
1581         }
1582 }
1583
1584 static void smp_flush_tlb_mm(struct mm_struct *mm)
1585 {
1586         if (mm->context != NO_CONTEXT) {
1587                 cpumask_t cpu_mask;
1588                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1589                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1590                 if (!cpumask_empty(&cpu_mask)) {
1591                         xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm);
1592                         if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
1593                                 cpumask_copy(mm_cpumask(mm),
1594                                              cpumask_of(smp_processor_id()));
1595                 }
1596                 local_ops->tlb_mm(mm);
1597         }
1598 }
1599
1600 static void smp_flush_cache_range(struct vm_area_struct *vma,
1601                                   unsigned long start,
1602                                   unsigned long end)
1603 {
1604         struct mm_struct *mm = vma->vm_mm;
1605
1606         if (mm->context != NO_CONTEXT) {
1607                 cpumask_t cpu_mask;
1608                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1609                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1610                 if (!cpumask_empty(&cpu_mask))
1611                         xc3((smpfunc_t) local_ops->cache_range,
1612                             (unsigned long) vma, start, end);
1613                 local_ops->cache_range(vma, start, end);
1614         }
1615 }
1616
1617 static void smp_flush_tlb_range(struct vm_area_struct *vma,
1618                                 unsigned long start,
1619                                 unsigned long end)
1620 {
1621         struct mm_struct *mm = vma->vm_mm;
1622
1623         if (mm->context != NO_CONTEXT) {
1624                 cpumask_t cpu_mask;
1625                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1626                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1627                 if (!cpumask_empty(&cpu_mask))
1628                         xc3((smpfunc_t) local_ops->tlb_range,
1629                             (unsigned long) vma, start, end);
1630                 local_ops->tlb_range(vma, start, end);
1631         }
1632 }
1633
1634 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1635 {
1636         struct mm_struct *mm = vma->vm_mm;
1637
1638         if (mm->context != NO_CONTEXT) {
1639                 cpumask_t cpu_mask;
1640                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1641                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1642                 if (!cpumask_empty(&cpu_mask))
1643                         xc2((smpfunc_t) local_ops->cache_page,
1644                             (unsigned long) vma, page);
1645                 local_ops->cache_page(vma, page);
1646         }
1647 }
1648
1649 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1650 {
1651         struct mm_struct *mm = vma->vm_mm;
1652
1653         if (mm->context != NO_CONTEXT) {
1654                 cpumask_t cpu_mask;
1655                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1656                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1657                 if (!cpumask_empty(&cpu_mask))
1658                         xc2((smpfunc_t) local_ops->tlb_page,
1659                             (unsigned long) vma, page);
1660                 local_ops->tlb_page(vma, page);
1661         }
1662 }
1663
1664 static void smp_flush_page_to_ram(unsigned long page)
1665 {
1666         /* Current theory is that those who call this are the one's
1667          * who have just dirtied their cache with the pages contents
1668          * in kernel space, therefore we only run this on local cpu.
1669          *
1670          * XXX This experiment failed, research further... -DaveM
1671          */
1672 #if 1
1673         xc1((smpfunc_t) local_ops->page_to_ram, page);
1674 #endif
1675         local_ops->page_to_ram(page);
1676 }
1677
1678 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1679 {
1680         cpumask_t cpu_mask;
1681         cpumask_copy(&cpu_mask, mm_cpumask(mm));
1682         cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1683         if (!cpumask_empty(&cpu_mask))
1684                 xc2((smpfunc_t) local_ops->sig_insns,
1685                     (unsigned long) mm, insn_addr);
1686         local_ops->sig_insns(mm, insn_addr);
1687 }
1688
1689 static struct sparc32_cachetlb_ops smp_cachetlb_ops = {
1690         .cache_all      = smp_flush_cache_all,
1691         .cache_mm       = smp_flush_cache_mm,
1692         .cache_page     = smp_flush_cache_page,
1693         .cache_range    = smp_flush_cache_range,
1694         .tlb_all        = smp_flush_tlb_all,
1695         .tlb_mm         = smp_flush_tlb_mm,
1696         .tlb_page       = smp_flush_tlb_page,
1697         .tlb_range      = smp_flush_tlb_range,
1698         .page_to_ram    = smp_flush_page_to_ram,
1699         .sig_insns      = smp_flush_sig_insns,
1700         .page_for_dma   = smp_flush_page_for_dma,
1701 };
1702 #endif
1703
1704 /* Load up routines and constants for sun4m and sun4d mmu */
1705 void __init load_mmu(void)
1706 {
1707         extern void ld_mmu_iommu(void);
1708         extern void ld_mmu_iounit(void);
1709
1710         /* Functions */
1711         get_srmmu_type();
1712
1713 #ifdef CONFIG_SMP
1714         /* El switcheroo... */
1715         local_ops = sparc32_cachetlb_ops;
1716
1717         if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
1718                 smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
1719                 smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
1720                 smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
1721                 smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
1722         }
1723
1724         if (poke_srmmu == poke_viking) {
1725                 /* Avoid unnecessary cross calls. */
1726                 smp_cachetlb_ops.cache_all = local_ops->cache_all;
1727                 smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
1728                 smp_cachetlb_ops.cache_range = local_ops->cache_range;
1729                 smp_cachetlb_ops.cache_page = local_ops->cache_page;
1730
1731                 smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
1732                 smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
1733                 smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
1734         }
1735
1736         /* It really is const after this point. */
1737         sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1738                 &smp_cachetlb_ops;
1739 #endif
1740
1741         if (sparc_cpu_model == sun4d)
1742                 ld_mmu_iounit();
1743         else
1744                 ld_mmu_iommu();
1745 #ifdef CONFIG_SMP
1746         if (sparc_cpu_model == sun4d)
1747                 sun4d_init_smp();
1748         else if (sparc_cpu_model == sparc_leon)
1749                 leon_init_smp();
1750         else
1751                 sun4m_init_smp();
1752 #endif
1753 }